adding full files to github, with all updates

author: zedarider <ymherklotz@gmail.com> 2016-12-12 13:19:22 +0000
committer: zedarider <ymherklotz@gmail.com> 2016-12-12 13:19:22 +0000
commit: aee06a47eca6d7f5532a10e59e394fd33904670a (patch)
tree: 9abf1adeec021a72863f1bfc8e1270513b26f1cb
parent: c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff)
download: VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.tar.gz
VerilogCoursework-aee06a47eca6d7f5532a10e59e394fd33904670a.zip
1879 files changed, 188178 insertions, 34784 deletions
diff --git a/part_1/ex1/db/_cmp.kpt b/part_1/ex1/db/_cmp.kpt
deleted file mode 100644
index 454d272..0000000
--- a/part_1/ex1/db/_cmp.kpt
+++ /dev/null
diff --git a/part_1/ex2/db/_cmp.kpt b/part_1/ex2/db/_cmp.kpt
deleted file mode 100644
index 8d0efe5..0000000
--- a/part_1/ex2/db/_cmp.kpt
+++ /dev/null
diff --git a/part_1/ex2/extra_files/pin_assignment.txt b/part_1/ex2/extra_files/pin_assignment.txt
index 4a576a0..04a3a75 100755
--- a/part_1/ex2/extra_files/pin_assignment.txt
+++ b/part_1/ex2/extra_files/pin_assignment.txt
@@ -1,211 +1,211 @@
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_AF14 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# Add-on Card Interface Pins
-#============================================================
-set_location_assignment PIN_AJ20 -to PWM_OUT
-set_location_assignment PIN_AK21 -to DAC_LD
-set_location_assignment PIN_AD20 -to DAC_CS
-set_location_assignment PIN_AF20 -to DAC_SCK
-set_location_assignment PIN_AF21 -to ADC_SCK
-set_location_assignment PIN_AG21 -to ADC_SDI
-set_location_assignment PIN_AG20 -to ADC_CS
-set_location_assignment PIN_AG18 -to DAC_SDI
-set_location_assignment PIN_AJ21 -to ADC_SDO
-set_location_assignment PIN_Y17 -to OLED_CS
-set_location_assignment PIN_Y18 -to OLED_RST
-set_location_assignment PIN_AK18 -to OLED_DC
-set_location_assignment PIN_AJ19 -to OLED_CLK
-set_location_assignment PIN_AJ16 -to OLED_DATA
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
-
-
-#============================================================
-# HEX0
-#============================================================
-set_location_assignment PIN_AE26 -to HEX0[0]
-set_location_assignment PIN_AE27 -to HEX0[1]
-set_location_assignment PIN_AE28 -to HEX0[2]
-set_location_assignment PIN_AG27 -to HEX0[3]
-set_location_assignment PIN_AF28 -to HEX0[4]
-set_location_assignment PIN_AG28 -to HEX0[5]
-set_location_assignment PIN_AH28 -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
-
-#============================================================
-# HEX1
-#============================================================
-set_location_assignment PIN_AJ29 -to HEX1[0]
-set_location_assignment PIN_AH29 -to HEX1[1]
-set_location_assignment PIN_AH30 -to HEX1[2]
-set_location_assignment PIN_AG30 -to HEX1[3]
-set_location_assignment PIN_AF29 -to HEX1[4]
-set_location_assignment PIN_AF30 -to HEX1[5]
-set_location_assignment PIN_AD27 -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
-
-#============================================================
-# HEX2
-#============================================================
-set_location_assignment PIN_AB23 -to HEX2[0]
-set_location_assignment PIN_AE29 -to HEX2[1]
-set_location_assignment PIN_AD29 -to HEX2[2]
-set_location_assignment PIN_AC28 -to HEX2[3]
-set_location_assignment PIN_AD30 -to HEX2[4]
-set_location_assignment PIN_AC29 -to HEX2[5]
-set_location_assignment PIN_AC30 -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
-
-#============================================================
-# HEX3
-#============================================================
-set_location_assignment PIN_AD26 -to HEX3[0]
-set_location_assignment PIN_AC27 -to HEX3[1]
-set_location_assignment PIN_AD25 -to HEX3[2]
-set_location_assignment PIN_AC25 -to HEX3[3]
-set_location_assignment PIN_AB28 -to HEX3[4]
-set_location_assignment PIN_AB25 -to HEX3[5]
-set_location_assignment PIN_AB22 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-
-#============================================================
-# HEX4
-#============================================================
-set_location_assignment PIN_AA24 -to HEX4[0]
-set_location_assignment PIN_Y23 -to HEX4[1]
-set_location_assignment PIN_Y24 -to HEX4[2]
-set_location_assignment PIN_W22 -to HEX4[3]
-set_location_assignment PIN_W24 -to HEX4[4]
-set_location_assignment PIN_V23 -to HEX4[5]
-set_location_assignment PIN_W25 -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-
-#============================================================
-# HEX5
-#============================================================
-set_location_assignment PIN_V25 -to HEX5[0]
-set_location_assignment PIN_AA28 -to HEX5[1]
-set_location_assignment PIN_Y27 -to HEX5[2]
-set_location_assignment PIN_AB27 -to HEX5[3]
-set_location_assignment PIN_AB26 -to HEX5[4]
-set_location_assignment PIN_AA26 -to HEX5[5]
-set_location_assignment PIN_AA25 -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-
-#============================================================
-# KEY
-#============================================================
-set_location_assignment PIN_AA14 -to KEY[0]
-set_location_assignment PIN_AA15 -to KEY[1]
-set_location_assignment PIN_W15 -to KEY[2]
-set_location_assignment PIN_Y16 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
-
-#============================================================
-# LEDR
-#============================================================
-set_location_assignment PIN_V16 -to LEDR[0]
-set_location_assignment PIN_W16 -to LEDR[1]
-set_location_assignment PIN_V17 -to LEDR[2]
-set_location_assignment PIN_V18 -to LEDR[3]
-set_location_assignment PIN_W17 -to LEDR[4]
-set_location_assignment PIN_W19 -to LEDR[5]
-set_location_assignment PIN_Y19 -to LEDR[6]
-set_location_assignment PIN_W20 -to LEDR[7]
-set_location_assignment PIN_W21 -to LEDR[8]
-set_location_assignment PIN_Y21 -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
-
-#============================================================
-# SW
-#============================================================
-set_location_assignment PIN_AB12 -to SW[0]
-set_location_assignment PIN_AC12 -to SW[1]
-set_location_assignment PIN_AF9 -to SW[2]
-set_location_assignment PIN_AF10 -to SW[3]
-set_location_assignment PIN_AD11 -to SW[4]
-set_location_assignment PIN_AD12 -to SW[5]
-set_location_assignment PIN_AE11 -to SW[6]
-set_location_assignment PIN_AC9 -to SW[7]
-set_location_assignment PIN_AD10 -to SW[8]
-set_location_assignment PIN_AE12 -to SW[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
-
-#============================================================
-# End of pin and io_standard assignments
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
 #============================================================
 \ No newline at end of file
diff --git a/part_1/ex3/db/_cmp.kpt b/part_1/ex3/db/_cmp.kpt
deleted file mode 100644
index bdb612b..0000000
--- a/part_1/ex3/db/_cmp.kpt
+++ /dev/null
diff --git a/part_1/ex4/db/_cmp.kpt b/part_1/ex4/db/_cmp.kpt
deleted file mode 100644
index 580e170..0000000
--- a/part_1/ex4/db/_cmp.kpt
+++ /dev/null
diff --git a/part_2/ex5/db/_cmp.kpt b/part_2/ex5/db/_cmp.kpt
deleted file mode 100644
index 1dafbef..0000000
--- a/part_2/ex5/db/_cmp.kpt
+++ /dev/null
diff --git a/part_2/ex5/pin_assignment.txt b/part_2/ex5/pin_assignment.txt
index 4a576a0..04a3a75 100755
--- a/part_2/ex5/pin_assignment.txt
+++ b/part_2/ex5/pin_assignment.txt
@@ -1,211 +1,211 @@
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_AF14 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# Add-on Card Interface Pins
-#============================================================
-set_location_assignment PIN_AJ20 -to PWM_OUT
-set_location_assignment PIN_AK21 -to DAC_LD
-set_location_assignment PIN_AD20 -to DAC_CS
-set_location_assignment PIN_AF20 -to DAC_SCK
-set_location_assignment PIN_AF21 -to ADC_SCK
-set_location_assignment PIN_AG21 -to ADC_SDI
-set_location_assignment PIN_AG20 -to ADC_CS
-set_location_assignment PIN_AG18 -to DAC_SDI
-set_location_assignment PIN_AJ21 -to ADC_SDO
-set_location_assignment PIN_Y17 -to OLED_CS
-set_location_assignment PIN_Y18 -to OLED_RST
-set_location_assignment PIN_AK18 -to OLED_DC
-set_location_assignment PIN_AJ19 -to OLED_CLK
-set_location_assignment PIN_AJ16 -to OLED_DATA
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
-
-
-#============================================================
-# HEX0
-#============================================================
-set_location_assignment PIN_AE26 -to HEX0[0]
-set_location_assignment PIN_AE27 -to HEX0[1]
-set_location_assignment PIN_AE28 -to HEX0[2]
-set_location_assignment PIN_AG27 -to HEX0[3]
-set_location_assignment PIN_AF28 -to HEX0[4]
-set_location_assignment PIN_AG28 -to HEX0[5]
-set_location_assignment PIN_AH28 -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
-
-#============================================================
-# HEX1
-#============================================================
-set_location_assignment PIN_AJ29 -to HEX1[0]
-set_location_assignment PIN_AH29 -to HEX1[1]
-set_location_assignment PIN_AH30 -to HEX1[2]
-set_location_assignment PIN_AG30 -to HEX1[3]
-set_location_assignment PIN_AF29 -to HEX1[4]
-set_location_assignment PIN_AF30 -to HEX1[5]
-set_location_assignment PIN_AD27 -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
-
-#============================================================
-# HEX2
-#============================================================
-set_location_assignment PIN_AB23 -to HEX2[0]
-set_location_assignment PIN_AE29 -to HEX2[1]
-set_location_assignment PIN_AD29 -to HEX2[2]
-set_location_assignment PIN_AC28 -to HEX2[3]
-set_location_assignment PIN_AD30 -to HEX2[4]
-set_location_assignment PIN_AC29 -to HEX2[5]
-set_location_assignment PIN_AC30 -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
-
-#============================================================
-# HEX3
-#============================================================
-set_location_assignment PIN_AD26 -to HEX3[0]
-set_location_assignment PIN_AC27 -to HEX3[1]
-set_location_assignment PIN_AD25 -to HEX3[2]
-set_location_assignment PIN_AC25 -to HEX3[3]
-set_location_assignment PIN_AB28 -to HEX3[4]
-set_location_assignment PIN_AB25 -to HEX3[5]
-set_location_assignment PIN_AB22 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-
-#============================================================
-# HEX4
-#============================================================
-set_location_assignment PIN_AA24 -to HEX4[0]
-set_location_assignment PIN_Y23 -to HEX4[1]
-set_location_assignment PIN_Y24 -to HEX4[2]
-set_location_assignment PIN_W22 -to HEX4[3]
-set_location_assignment PIN_W24 -to HEX4[4]
-set_location_assignment PIN_V23 -to HEX4[5]
-set_location_assignment PIN_W25 -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-
-#============================================================
-# HEX5
-#============================================================
-set_location_assignment PIN_V25 -to HEX5[0]
-set_location_assignment PIN_AA28 -to HEX5[1]
-set_location_assignment PIN_Y27 -to HEX5[2]
-set_location_assignment PIN_AB27 -to HEX5[3]
-set_location_assignment PIN_AB26 -to HEX5[4]
-set_location_assignment PIN_AA26 -to HEX5[5]
-set_location_assignment PIN_AA25 -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-
-#============================================================
-# KEY
-#============================================================
-set_location_assignment PIN_AA14 -to KEY[0]
-set_location_assignment PIN_AA15 -to KEY[1]
-set_location_assignment PIN_W15 -to KEY[2]
-set_location_assignment PIN_Y16 -to KEY[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
-
-#============================================================
-# LEDR
-#============================================================
-set_location_assignment PIN_V16 -to LEDR[0]
-set_location_assignment PIN_W16 -to LEDR[1]
-set_location_assignment PIN_V17 -to LEDR[2]
-set_location_assignment PIN_V18 -to LEDR[3]
-set_location_assignment PIN_W17 -to LEDR[4]
-set_location_assignment PIN_W19 -to LEDR[5]
-set_location_assignment PIN_Y19 -to LEDR[6]
-set_location_assignment PIN_W20 -to LEDR[7]
-set_location_assignment PIN_W21 -to LEDR[8]
-set_location_assignment PIN_Y21 -to LEDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
-
-#============================================================
-# SW
-#============================================================
-set_location_assignment PIN_AB12 -to SW[0]
-set_location_assignment PIN_AC12 -to SW[1]
-set_location_assignment PIN_AF9 -to SW[2]
-set_location_assignment PIN_AF10 -to SW[3]
-set_location_assignment PIN_AD11 -to SW[4]
-set_location_assignment PIN_AD12 -to SW[5]
-set_location_assignment PIN_AE11 -to SW[6]
-set_location_assignment PIN_AC9 -to SW[7]
-set_location_assignment PIN_AD10 -to SW[8]
-set_location_assignment PIN_AE12 -to SW[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
-
-#============================================================
-# End of pin and io_standard assignments
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
 #============================================================
 \ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_info b/part_2/ex5/simulation/modelsim/rtl_work/_info
index 9a0155e..9a599cc 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/_info
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\simulation\modelsim
-vcounter_8
-!i10b 1
-!s100 ;ldZ:oUkgLo?@Aa7ibdbm2
-Ia91@O_<g0BVIc?WTzTbB62
-Vdn7aTnOzPKdeZA;zmQ`Cl3
-Z1 dC:\New folder\simulation\modelsim
-w1479807538
-8C:/New folder/verilog_files/counter_8.v
-FC:/New folder/verilog_files/counter_8.v
-L0 3
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1479807676.024000
-!s107 C:/New folder/verilog_files/counter_8.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\simulation\modelsim
+vcounter_8
+!i10b 1
+!s100 ;ldZ:oUkgLo?@Aa7ibdbm2
+Ia91@O_<g0BVIc?WTzTbB62
+Vdn7aTnOzPKdeZA;zmQ`Cl3
+Z1 dC:\New folder\simulation\modelsim
+w1479807538
+8C:/New folder/verilog_files/counter_8.v
+FC:/New folder/verilog_files/counter_8.v
+L0 3
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1479807676.024000
+!s107 C:/New folder/verilog_files/counter_8.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/verilog_files|C:/New folder/verilog_files/counter_8.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/verilog_files} -O0
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/_vmake b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
index b51b305..2f7e729 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/_vmake
+++ b/part_2/ex5/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
index 8ada04e..0dd84bc 100755
--- a/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
+++ b/part_2/ex5/simulation/modelsim/rtl_work/counter_8/_primary.vhd
@@ -1,14 +1,14 @@
-library verilog;
-use verilog.vl_types.all;
-entity counter_8 is
-    generic(
-        BIT_SZ          : integer := 8
-    );
-    port(
-        clock           : in     vl_logic;
-        enable          : in     vl_logic;
-        count           : out    vl_logic_vector
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
-end counter_8;
+library verilog;
+use verilog.vl_types.all;
+entity counter_8 is
+    generic(
+        BIT_SZ          : integer := 8
+    );
+    port(
+        clock           : in     vl_logic;
+        enable          : in     vl_logic;
+        count           : out    vl_logic_vector
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BIT_SZ : constant is 1;
+end counter_8;
diff --git a/part_2/ex5/simulation/modelsim/tb_counter b/part_2/ex5/simulation/modelsim/tb_counter
index 4544d6a..6256691 100755
--- a/part_2/ex5/simulation/modelsim/tb_counter
+++ b/part_2/ex5/simulation/modelsim/tb_counter
@@ -1,9 +1,9 @@
-add wave clock enable
-add wave -hexadecimal count
-force clock 0 0, 1 10ns -repeat 20ns
-force enable 1
-run 100ns
-force enable 0
-run 100ns
-force enable 1
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
 run 1000
 \ No newline at end of file
diff --git a/part_2/ex5/simulation/modelsim/tb_counter.do b/part_2/ex5/simulation/modelsim/tb_counter.do
index 4544d6a..6256691 100755
--- a/part_2/ex5/simulation/modelsim/tb_counter.do
+++ b/part_2/ex5/simulation/modelsim/tb_counter.do
@@ -1,9 +1,9 @@
-add wave clock enable
-add wave -hexadecimal count
-force clock 0 0, 1 10ns -repeat 20ns
-force enable 1
-run 100ns
-force enable 0
-run 100ns
-force enable 1
+add wave clock enable
+add wave -hexadecimal count
+force clock 0 0, 1 10ns -repeat 20ns
+force enable 1
+run 100ns
+force enable 0
+run 100ns
+force enable 1
 run 1000
 \ No newline at end of file
diff --git a/part_2/ex6/c5_pin_model_dump.txt b/part_2/ex6/c5_pin_model_dump.txt
index 31bb72c..a895a64 100755
--- a/part_2/ex6/c5_pin_model_dump.txt
+++ b/part_2/ex6/c5_pin_model_dump.txt
@@ -1,118 +1,118 @@
-io_4iomodule_c5_index: 55gpio_index: 2
-io_4iomodule_c5_index: 54gpio_index: 465
-io_4iomodule_c5_index: 33gpio_index: 6
-io_4iomodule_c5_index: 51gpio_index: 461
-io_4iomodule_c5_index: 27gpio_index: 10
-io_4iomodule_c5_index: 57gpio_index: 457
-io_4iomodule_c5_index: 34gpio_index: 14
-io_4iomodule_c5_index: 28gpio_index: 453
-io_4iomodule_c5_index: 26gpio_index: 19
-io_4iomodule_c5_index: 47gpio_index: 449
-io_4iomodule_c5_index: 29gpio_index: 22
-io_4iomodule_c5_index: 3gpio_index: 445
-io_4iomodule_c5_index: 16gpio_index: 27
-io_4iomodule_c5_index: 6gpio_index: 441
-io_4iomodule_c5_index: 50gpio_index: 30
-io_4iomodule_c5_index: 35gpio_index: 437
-io_4iomodule_c5_index: 7gpio_index: 35
-io_4iomodule_c5_index: 53gpio_index: 433
-io_4iomodule_c5_index: 12gpio_index: 38
-io_4iomodule_c5_index: 1gpio_index: 429
-io_4iomodule_c5_index: 22gpio_index: 43
-io_4iomodule_c5_index: 8gpio_index: 425
-io_4iomodule_c5_index: 20gpio_index: 46
-io_4iomodule_c5_index: 30gpio_index: 421
-io_4iomodule_c5_index: 2gpio_index: 51
-io_4iomodule_c5_index: 31gpio_index: 417
-io_4iomodule_c5_index: 39gpio_index: 54
-io_4iomodule_c5_index: 18gpio_index: 413
-io_4iomodule_c5_index: 10gpio_index: 59
-io_4iomodule_c5_index: 42gpio_index: 409
-io_4iomodule_c5_index: 5gpio_index: 62
-io_4iomodule_c5_index: 24gpio_index: 405
-io_4iomodule_c5_index: 37gpio_index: 67
-io_4iomodule_c5_index: 13gpio_index: 401
-io_4iomodule_c5_index: 0gpio_index: 70
-io_4iomodule_c5_index: 44gpio_index: 397
-io_4iomodule_c5_index: 38gpio_index: 75
-io_4iomodule_c5_index: 52gpio_index: 393
-io_4iomodule_c5_index: 32gpio_index: 78
-io_4iomodule_c5_index: 56gpio_index: 389
-io_4iomodule_a_index: 13gpio_index: 385
-io_4iomodule_c5_index: 4gpio_index: 83
-io_4iomodule_c5_index: 23gpio_index: 86
-io_4iomodule_a_index: 15gpio_index: 381
-io_4iomodule_a_index: 8gpio_index: 377
-io_4iomodule_c5_index: 46gpio_index: 91
-io_4iomodule_a_index: 5gpio_index: 373
-io_4iomodule_a_index: 11gpio_index: 369
-io_4iomodule_c5_index: 41gpio_index: 94
-io_4iomodule_a_index: 3gpio_index: 365
-io_4iomodule_c5_index: 25gpio_index: 99
-io_4iomodule_a_index: 7gpio_index: 361
-io_4iomodule_c5_index: 9gpio_index: 102
-io_4iomodule_a_index: 0gpio_index: 357
-io_4iomodule_c5_index: 14gpio_index: 107
-io_4iomodule_a_index: 12gpio_index: 353
-io_4iomodule_c5_index: 45gpio_index: 110
-io_4iomodule_c5_index: 17gpio_index: 115
-io_4iomodule_a_index: 4gpio_index: 349
-io_4iomodule_c5_index: 36gpio_index: 118
-io_4iomodule_a_index: 10gpio_index: 345
-io_4iomodule_a_index: 16gpio_index: 341
-io_4iomodule_c5_index: 15gpio_index: 123
-io_4iomodule_a_index: 14gpio_index: 337
-io_4iomodule_c5_index: 43gpio_index: 126
-io_4iomodule_c5_index: 19gpio_index: 131
-io_4iomodule_a_index: 1gpio_index: 333
-io_4iomodule_c5_index: 59gpio_index: 134
-io_4iomodule_a_index: 2gpio_index: 329
-io_4iomodule_a_index: 9gpio_index: 325
-io_4iomodule_c5_index: 48gpio_index: 139
-io_4iomodule_a_index: 6gpio_index: 321
-io_4iomodule_a_index: 17gpio_index: 317
-io_4iomodule_c5_index: 40gpio_index: 142
-io_4iomodule_c5_index: 11gpio_index: 147
-io_4iomodule_c5_index: 58gpio_index: 150
-io_4iomodule_c5_index: 21gpio_index: 155
-io_4iomodule_c5_index: 49gpio_index: 158
-io_4iomodule_h_c5_index: 0gpio_index: 161
-io_4iomodule_h_c5_index: 6gpio_index: 165
-io_4iomodule_h_c5_index: 10gpio_index: 169
-io_4iomodule_h_c5_index: 3gpio_index: 173
-io_4iomodule_h_c5_index: 8gpio_index: 176
-io_4iomodule_h_c5_index: 11gpio_index: 180
-io_4iomodule_h_c5_index: 7gpio_index: 184
-io_4iomodule_h_c5_index: 5gpio_index: 188
-io_4iomodule_h_c5_index: 1gpio_index: 192
-io_4iomodule_h_c5_index: 2gpio_index: 196
-io_4iomodule_h_c5_index: 9gpio_index: 200
-io_4iomodule_h_c5_index: 4gpio_index: 204
-io_4iomodule_h_index: 15gpio_index: 208
-io_4iomodule_h_index: 1gpio_index: 212
-io_4iomodule_h_index: 3gpio_index: 216
-io_4iomodule_h_index: 2gpio_index: 220
-io_4iomodule_h_index: 11gpio_index: 224
-io_4iomodule_vref_h_index: 1gpio_index: 228
-io_4iomodule_h_index: 20gpio_index: 231
-io_4iomodule_h_index: 8gpio_index: 235
-io_4iomodule_h_index: 6gpio_index: 239
-io_4iomodule_h_index: 10gpio_index: 243
-io_4iomodule_h_index: 23gpio_index: 247
-io_4iomodule_h_index: 7gpio_index: 251
-io_4iomodule_h_index: 22gpio_index: 255
-io_4iomodule_h_index: 5gpio_index: 259
-io_4iomodule_h_index: 24gpio_index: 263
-io_4iomodule_h_index: 0gpio_index: 267
-io_4iomodule_h_index: 13gpio_index: 271
-io_4iomodule_h_index: 21gpio_index: 275
-io_4iomodule_h_index: 16gpio_index: 279
-io_4iomodule_vref_h_index: 0gpio_index: 283
-io_4iomodule_h_index: 12gpio_index: 286
-io_4iomodule_h_index: 4gpio_index: 290
-io_4iomodule_h_index: 19gpio_index: 294
-io_4iomodule_h_index: 18gpio_index: 298
-io_4iomodule_h_index: 17gpio_index: 302
-io_4iomodule_h_index: 25gpio_index: 306
-io_4iomodule_h_index: 14gpio_index: 310
-io_4iomodule_h_index: 9gpio_index: 314
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_2/ex6/db/.cmp.kpt b/part_2/ex6/db/.cmp.kpt
index a87068f..38aa87b 100755
--- a/part_2/ex6/db/.cmp.kpt
+++ b/part_2/ex6/db/.cmp.kpt
diff --git a/part_2/ex6/db/_cmp.kpt b/part_2/ex6/db/_cmp.kpt
deleted file mode 100644
index 38aa87b..0000000
--- a/part_2/ex6/db/_cmp.kpt
+++ /dev/null
diff --git a/part_2/ex6/db/ex6.(0).cnf.cdb b/part_2/ex6/db/ex6.(0).cnf.cdb
index 15f19bc..e44f8a1 100755
--- a/part_2/ex6/db/ex6.(0).cnf.cdb
+++ b/part_2/ex6/db/ex6.(0).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(0).cnf.hdb b/part_2/ex6/db/ex6.(0).cnf.hdb
index b973444..de77324 100755
--- a/part_2/ex6/db/ex6.(0).cnf.hdb
+++ b/part_2/ex6/db/ex6.(0).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(1).cnf.cdb b/part_2/ex6/db/ex6.(1).cnf.cdb
index 70d8f69..4079d9b 100755
--- a/part_2/ex6/db/ex6.(1).cnf.cdb
+++ b/part_2/ex6/db/ex6.(1).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(1).cnf.hdb b/part_2/ex6/db/ex6.(1).cnf.hdb
index 4ce43db..39c74f3 100755
--- a/part_2/ex6/db/ex6.(1).cnf.hdb
+++ b/part_2/ex6/db/ex6.(1).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(2).cnf.cdb b/part_2/ex6/db/ex6.(2).cnf.cdb
index e19eb61..c1f3aaf 100755
--- a/part_2/ex6/db/ex6.(2).cnf.cdb
+++ b/part_2/ex6/db/ex6.(2).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(2).cnf.hdb b/part_2/ex6/db/ex6.(2).cnf.hdb
index 971fb3d..ebbfbca 100755
--- a/part_2/ex6/db/ex6.(2).cnf.hdb
+++ b/part_2/ex6/db/ex6.(2).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(3).cnf.cdb b/part_2/ex6/db/ex6.(3).cnf.cdb
index 3593c12..adf12ca 100755
--- a/part_2/ex6/db/ex6.(3).cnf.cdb
+++ b/part_2/ex6/db/ex6.(3).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(3).cnf.hdb b/part_2/ex6/db/ex6.(3).cnf.hdb
index 900e5a3..3d54105 100755
--- a/part_2/ex6/db/ex6.(3).cnf.hdb
+++ b/part_2/ex6/db/ex6.(3).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(4).cnf.cdb b/part_2/ex6/db/ex6.(4).cnf.cdb
index 742ef6f..9bd5391 100755
--- a/part_2/ex6/db/ex6.(4).cnf.cdb
+++ b/part_2/ex6/db/ex6.(4).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(4).cnf.hdb b/part_2/ex6/db/ex6.(4).cnf.hdb
index 9f10e3d..88032e3 100755
--- a/part_2/ex6/db/ex6.(4).cnf.hdb
+++ b/part_2/ex6/db/ex6.(4).cnf.hdb
diff --git a/part_2/ex6/db/ex6.(5).cnf.cdb b/part_2/ex6/db/ex6.(5).cnf.cdb
index ccc0067..7e272ba 100755
--- a/part_2/ex6/db/ex6.(5).cnf.cdb
+++ b/part_2/ex6/db/ex6.(5).cnf.cdb
diff --git a/part_2/ex6/db/ex6.(5).cnf.hdb b/part_2/ex6/db/ex6.(5).cnf.hdb
index fc48afc..74844fd 100755
--- a/part_2/ex6/db/ex6.(5).cnf.hdb
+++ b/part_2/ex6/db/ex6.(5).cnf.hdb
diff --git a/part_2/ex6/db/ex6.ae.hdb b/part_2/ex6/db/ex6.ae.hdb
new file mode 100755
index 0000000..b847279
--- /dev/null
+++ b/part_2/ex6/db/ex6.ae.hdb
diff --git a/part_2/ex6/db/ex6.analyze_file.qmsg b/part_2/ex6/db/ex6.analyze_file.qmsg
new file mode 100755
index 0000000..44ee136
--- /dev/null
+++ b/part_2/ex6/db/ex6.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479812643770 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:04:03 2016 " "Processing started: Tue Nov 22 11:04:03 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479812643771 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 --analyze_file=\"C:/New folder/ex6/ex6.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 --analyze_file=\"C:/New folder/ex6/ex6.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479812643772 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479812644221 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479812644221 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "832 " "Peak virtual memory: 832 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:04:12 2016 " "Processing ended: Tue Nov 22 11:04:12 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479812652563 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479812652563 ""}
diff --git a/part_2/ex6/db/ex6.asm.qmsg b/part_2/ex6/db/ex6.asm.qmsg
index 2fb3897..f23ddd0 100755
--- a/part_2/ex6/db/ex6.asm.qmsg
+++ b/part_2/ex6/db/ex6.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481479710522 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481479710535 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 18:08:30 2016 " "Processing started: Sun Dec 11 18:08:30 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481479710535 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481479710535 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481479710535 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481479711198 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481479716231 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "976 " "Peak virtual memory: 976 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481479716578 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 18:08:36 2016 " "Processing ended: Sun Dec 11 18:08:36 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481479716578 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481479716578 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481479716578 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481479716578 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479815014816 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479815014818 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:43:34 2016 " "Processing started: Tue Nov 22 11:43:34 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479815014818 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479815014818 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479815014818 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479815015570 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479815020100 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "893 " "Peak virtual memory: 893 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:40 2016 " "Processing ended: Tue Nov 22 11:43:40 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815020437 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479815020437 ""}
diff --git a/part_2/ex6/db/ex6.asm.rdb b/part_2/ex6/db/ex6.asm.rdb
index db1450b..0ef85b8 100755
--- a/part_2/ex6/db/ex6.asm.rdb
+++ b/part_2/ex6/db/ex6.asm.rdb
diff --git a/part_2/ex6/db/ex6.cbx.xml b/part_2/ex6/db/ex6.cbx.xml
index 1e74979..8b16f5b 100755
--- a/part_2/ex6/db/ex6.cbx.xml
+++ b/part_2/ex6/db/ex6.cbx.xml
@@ -1,5 +1,5 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
-	<PROJECT NAME="ex6">
-	</PROJECT>
-</LOG_ROOT>
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ex6">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/part_2/ex6/db/ex6.cmp.ammdb b/part_2/ex6/db/ex6.cmp.ammdb
new file mode 100755
index 0000000..14e19ae
--- /dev/null
+++ b/part_2/ex6/db/ex6.cmp.ammdb
diff --git a/part_2/ex6/db/ex6.cmp.bpm b/part_2/ex6/db/ex6.cmp.bpm
index 513167e..9fc0368 100755
--- a/part_2/ex6/db/ex6.cmp.bpm
+++ b/part_2/ex6/db/ex6.cmp.bpm
diff --git a/part_2/ex6/db/ex6.cmp.cdb b/part_2/ex6/db/ex6.cmp.cdb
index e2b2023..f2b998b 100755
--- a/part_2/ex6/db/ex6.cmp.cdb
+++ b/part_2/ex6/db/ex6.cmp.cdb
diff --git a/part_2/ex6/db/ex6.cmp.hdb b/part_2/ex6/db/ex6.cmp.hdb
index 3dcd013..4c3f7f7 100755
--- a/part_2/ex6/db/ex6.cmp.hdb
+++ b/part_2/ex6/db/ex6.cmp.hdb
diff --git a/part_2/ex6/db/ex6.cmp.idb b/part_2/ex6/db/ex6.cmp.idb
index 189a33e..08a2505 100755
--- a/part_2/ex6/db/ex6.cmp.idb
+++ b/part_2/ex6/db/ex6.cmp.idb
diff --git a/part_2/ex6/db/ex6.cmp.logdb b/part_2/ex6/db/ex6.cmp.logdb
index 2c1b2b8..b26a4d2 100755
--- a/part_2/ex6/db/ex6.cmp.logdb
+++ b/part_2/ex6/db/ex6.cmp.logdb
@@ -1,77 +1,77 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000003;IO_000001;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000022;IO_000021;IO_000046;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000047;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
-IO_RULES_MATRIX,Total Pass,0;38;38;0;0;38;38;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;38;38;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,38;0;0;38;38;0;0;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;0;0;38,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,38;0;38;0;0;38;38;0;38;38;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;38;0;38;38;0;0;38;0;0;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38;38,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_2/ex6/db/ex6.cmp.rdb b/part_2/ex6/db/ex6.cmp.rdb
index ddee90b..2650c4f 100755
--- a/part_2/ex6/db/ex6.cmp.rdb
+++ b/part_2/ex6/db/ex6.cmp.rdb
diff --git a/part_2/ex6/db/ex6.cmp_merge.kpt b/part_2/ex6/db/ex6.cmp_merge.kpt
index 432d0d8..ee1a16d 100755
--- a/part_2/ex6/db/ex6.cmp_merge.kpt
+++ b/part_2/ex6/db/ex6.cmp_merge.kpt
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd
index f484435..5b115d6 100755
--- a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd
index 8ebe269..3a7a497 100755
--- a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd
index 8d531ee..aa473fa 100755
--- a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd
index 29d0225..dce4f6b 100755
--- a/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd
+++ b/part_2/ex6/db/ex6.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex6/db/ex6.db_info b/part_2/ex6/db/ex6.db_info
index 4f976f6..d880372 100755
--- a/part_2/ex6/db/ex6.db_info
+++ b/part_2/ex6/db/ex6.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Version_Index = 419480576
-Creation_Time = Sun Dec 11 17:54:40 2016
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 22 11:44:41 2016
diff --git a/part_2/ex6/db/ex6.fit.qmsg b/part_2/ex6/db/ex6.fit.qmsg
index dd491d6..520ed32 100755
--- a/part_2/ex6/db/ex6.fit.qmsg
+++ b/part_2/ex6/db/ex6.fit.qmsg
@@ -1,46 +1,45 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481479681292 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481479681292 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481479681298 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481479681329 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481479681329 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481479681733 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481479681754 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481479681813 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481479692596 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481479692676 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481479692676 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479692676 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481479692680 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481479692680 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481479692681 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481479692681 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481479692681 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481479692681 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481479692681 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481479692682 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481479692682 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481479692720 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481479692720 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479692722 ""}
-{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1481479697536 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479697538 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1481479697538 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481479697539 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481479697539 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1481479697539 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481479697540 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481479697540 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481479697540 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1481479697540 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481479697546 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481479697639 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479698137 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481479698776 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481479699121 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479699121 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481479700015 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y11 X89_Y22 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22" {  } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22"} { { 12 { 0 ""} 78 11 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481479704739 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481479704739 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481479705011 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1481479705011 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481479705011 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479705013 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481479706219 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481479706252 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481479706612 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481479706612 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481479706949 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481479708912 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481479709016 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481479709072 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 49 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 49 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2132 " "Peak virtual memory: 2132 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481479709421 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 18:08:29 2016 " "Processing ended: Sun Dec 11 18:08:29 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481479709421 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Elapsed time: 00:00:29" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481479709421 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481479709421 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481479709421 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479814984340 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479814984340 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479814984583 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814984640 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814984640 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479814985024 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479814985159 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479814995125 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479814995207 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479814995207 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814995207 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479814995209 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814995210 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814995210 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479814995211 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479814995211 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479814995211 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479814995211 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479814995211 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479814995211 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814995247 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479814995247 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814995249 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1479815000743 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815000745 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1479815000745 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479815000746 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479815000747 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1479815000747 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479815000747 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1479815000747 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479815000751 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479815000837 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815001449 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479815002122 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479815002452 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815002452 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479815003554 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479815008086 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479815008086 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479815008384 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479815008384 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479815008384 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815008388 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479815009521 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479815009559 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479815009945 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479815009945 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479815010330 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479815012667 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479815012909 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479815012966 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 48 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 48 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2591 " "Peak virtual memory: 2591 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:33 2016 " "Processing ended: Tue Nov 22 11:43:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:53 " "Total CPU time (on all processors): 00:00:53" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815013395 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479815013395 ""}
diff --git a/part_2/ex6/db/ex6.hier_info b/part_2/ex6/db/ex6.hier_info
index 35806ed..df23cf1 100755
--- a/part_2/ex6/db/ex6.hier_info
+++ b/part_2/ex6/db/ex6.hier_info
@@ -1,557 +1,557 @@
-|ex6
-CLOCK_50 => CLOCK_50.IN1
-KEY[0] => _.IN1
-KEY[1] => _.IN1
-HEX0[0] << hex_to_7seg:SEG0.port0
-HEX0[1] << hex_to_7seg:SEG0.port0
-HEX0[2] << hex_to_7seg:SEG0.port0
-HEX0[3] << hex_to_7seg:SEG0.port0
-HEX0[4] << hex_to_7seg:SEG0.port0
-HEX0[5] << hex_to_7seg:SEG0.port0
-HEX0[6] << hex_to_7seg:SEG0.port0
-HEX1[0] << hex_to_7seg:SEG1.port0
-HEX1[1] << hex_to_7seg:SEG1.port0
-HEX1[2] << hex_to_7seg:SEG1.port0
-HEX1[3] << hex_to_7seg:SEG1.port0
-HEX1[4] << hex_to_7seg:SEG1.port0
-HEX1[5] << hex_to_7seg:SEG1.port0
-HEX1[6] << hex_to_7seg:SEG1.port0
-HEX2[0] << hex_to_7seg:SEG2.port0
-HEX2[1] << hex_to_7seg:SEG2.port0
-HEX2[2] << hex_to_7seg:SEG2.port0
-HEX2[3] << hex_to_7seg:SEG2.port0
-HEX2[4] << hex_to_7seg:SEG2.port0
-HEX2[5] << hex_to_7seg:SEG2.port0
-HEX2[6] << hex_to_7seg:SEG2.port0
-HEX3[0] << hex_to_7seg:SEG3.port0
-HEX3[1] << hex_to_7seg:SEG3.port0
-HEX3[2] << hex_to_7seg:SEG3.port0
-HEX3[3] << hex_to_7seg:SEG3.port0
-HEX3[4] << hex_to_7seg:SEG3.port0
-HEX3[5] << hex_to_7seg:SEG3.port0
-HEX3[6] << hex_to_7seg:SEG3.port0
-HEX4[0] << hex_to_7seg:SEG4.port0
-HEX4[1] << hex_to_7seg:SEG4.port0
-HEX4[2] << hex_to_7seg:SEG4.port0
-HEX4[3] << hex_to_7seg:SEG4.port0
-HEX4[4] << hex_to_7seg:SEG4.port0
-HEX4[5] << hex_to_7seg:SEG4.port0
-HEX4[6] << hex_to_7seg:SEG4.port0
-
-
-|ex6|tick_50000:tck
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|counter_16:C
-clock => count[0]~reg0.CLK
-clock => count[1]~reg0.CLK
-clock => count[2]~reg0.CLK
-clock => count[3]~reg0.CLK
-clock => count[4]~reg0.CLK
-clock => count[5]~reg0.CLK
-clock => count[6]~reg0.CLK
-clock => count[7]~reg0.CLK
-clock => count[8]~reg0.CLK
-clock => count[9]~reg0.CLK
-clock => count[10]~reg0.CLK
-clock => count[11]~reg0.CLK
-clock => count[12]~reg0.CLK
-clock => count[13]~reg0.CLK
-clock => count[14]~reg0.CLK
-clock => count[15]~reg0.CLK
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-enable => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-reset => count.OUTPUTSELECT
-count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B
-B[0] => BCD_0[0].DATAIN
-B[1] => w29[0].IN1
-B[2] => w25[0].IN1
-B[3] => w21[0].IN1
-B[4] => w17[0].IN1
-B[5] => w14[0].IN1
-B[6] => w11[0].IN1
-B[7] => w8[0].IN1
-B[8] => w6[0].IN1
-B[9] => w4[0].IN1
-B[10] => w2[0].IN1
-B[11] => w1[0].IN1
-B[12] => w1[1].IN1
-B[13] => w1[2].IN1
-B[14] => w1[3].IN1
-B[15] => w3[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A29.port1
-BCD_0[2] <= add3_ge5:A29.port1
-BCD_0[3] <= add3_ge5:A29.port1
-BCD_1[0] <= add3_ge5:A29.port1
-BCD_1[1] <= add3_ge5:A28.port1
-BCD_1[2] <= add3_ge5:A28.port1
-BCD_1[3] <= add3_ge5:A28.port1
-BCD_2[0] <= add3_ge5:A28.port1
-BCD_2[1] <= add3_ge5:A27.port1
-BCD_2[2] <= add3_ge5:A27.port1
-BCD_2[3] <= add3_ge5:A27.port1
-BCD_3[0] <= add3_ge5:A27.port1
-BCD_3[1] <= add3_ge5:A26.port1
-BCD_3[2] <= add3_ge5:A26.port1
-BCD_3[3] <= add3_ge5:A26.port1
-BCD_4[0] <= add3_ge5:A26.port1
-BCD_4[1] <= add3_ge5:A22.port1
-BCD_4[2] <= add3_ge5:A18.port1
-BCD_4[3] <= <GND>
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A1
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A2
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A3
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A4
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A5
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A6
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A7
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A8
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A9
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A10
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A11
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A12
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A13
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A14
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A15
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A16
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A17
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A18
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A19
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A20
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A21
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A22
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A23
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A24
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A25
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A26
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A27
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A28
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|bin2bcd_16:B|add3_ge5:A29
-w[0] => Decoder0.IN3
-w[1] => Decoder0.IN2
-w[2] => Decoder0.IN1
-w[3] => Decoder0.IN0
-a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex6|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex6|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex6|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex6|hex_to_7seg:SEG3
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex6|hex_to_7seg:SEG4
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
+|ex6
+CLOCK_50 => CLOCK_50.IN1
+KEY[0] => _.IN1
+KEY[1] => _.IN1
+HEX0[0] <= hex_to_7seg:SEG0.port0
+HEX0[1] <= hex_to_7seg:SEG0.port0
+HEX0[2] <= hex_to_7seg:SEG0.port0
+HEX0[3] <= hex_to_7seg:SEG0.port0
+HEX0[4] <= hex_to_7seg:SEG0.port0
+HEX0[5] <= hex_to_7seg:SEG0.port0
+HEX0[6] <= hex_to_7seg:SEG0.port0
+HEX1[0] <= hex_to_7seg:SEG1.port0
+HEX1[1] <= hex_to_7seg:SEG1.port0
+HEX1[2] <= hex_to_7seg:SEG1.port0
+HEX1[3] <= hex_to_7seg:SEG1.port0
+HEX1[4] <= hex_to_7seg:SEG1.port0
+HEX1[5] <= hex_to_7seg:SEG1.port0
+HEX1[6] <= hex_to_7seg:SEG1.port0
+HEX2[0] <= hex_to_7seg:SEG2.port0
+HEX2[1] <= hex_to_7seg:SEG2.port0
+HEX2[2] <= hex_to_7seg:SEG2.port0
+HEX2[3] <= hex_to_7seg:SEG2.port0
+HEX2[4] <= hex_to_7seg:SEG2.port0
+HEX2[5] <= hex_to_7seg:SEG2.port0
+HEX2[6] <= hex_to_7seg:SEG2.port0
+HEX3[0] <= hex_to_7seg:SEG3.port0
+HEX3[1] <= hex_to_7seg:SEG3.port0
+HEX3[2] <= hex_to_7seg:SEG3.port0
+HEX3[3] <= hex_to_7seg:SEG3.port0
+HEX3[4] <= hex_to_7seg:SEG3.port0
+HEX3[5] <= hex_to_7seg:SEG3.port0
+HEX3[6] <= hex_to_7seg:SEG3.port0
+HEX4[0] <= hex_to_7seg:SEG4.port0
+HEX4[1] <= hex_to_7seg:SEG4.port0
+HEX4[2] <= hex_to_7seg:SEG4.port0
+HEX4[3] <= hex_to_7seg:SEG4.port0
+HEX4[4] <= hex_to_7seg:SEG4.port0
+HEX4[5] <= hex_to_7seg:SEG4.port0
+HEX4[6] <= hex_to_7seg:SEG4.port0
+
+
+|ex6|tick_50000:tck
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|counter_16:C
+clock => count[0]~reg0.CLK
+clock => count[1]~reg0.CLK
+clock => count[2]~reg0.CLK
+clock => count[3]~reg0.CLK
+clock => count[4]~reg0.CLK
+clock => count[5]~reg0.CLK
+clock => count[6]~reg0.CLK
+clock => count[7]~reg0.CLK
+clock => count[8]~reg0.CLK
+clock => count[9]~reg0.CLK
+clock => count[10]~reg0.CLK
+clock => count[11]~reg0.CLK
+clock => count[12]~reg0.CLK
+clock => count[13]~reg0.CLK
+clock => count[14]~reg0.CLK
+clock => count[15]~reg0.CLK
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+enable => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+reset => count.OUTPUTSELECT
+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B
+B[0] => BCD_0[0].DATAIN
+B[1] => w29[0].IN1
+B[2] => w25[0].IN1
+B[3] => w21[0].IN1
+B[4] => w17[0].IN1
+B[5] => w14[0].IN1
+B[6] => w11[0].IN1
+B[7] => w8[0].IN1
+B[8] => w6[0].IN1
+B[9] => w4[0].IN1
+B[10] => w2[0].IN1
+B[11] => w1[0].IN1
+B[12] => w1[1].IN1
+B[13] => w1[2].IN1
+B[14] => w1[3].IN1
+B[15] => w3[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A29.port1
+BCD_0[2] <= add3_ge5:A29.port1
+BCD_0[3] <= add3_ge5:A29.port1
+BCD_1[0] <= add3_ge5:A29.port1
+BCD_1[1] <= add3_ge5:A28.port1
+BCD_1[2] <= add3_ge5:A28.port1
+BCD_1[3] <= add3_ge5:A28.port1
+BCD_2[0] <= add3_ge5:A28.port1
+BCD_2[1] <= add3_ge5:A27.port1
+BCD_2[2] <= add3_ge5:A27.port1
+BCD_2[3] <= add3_ge5:A27.port1
+BCD_3[0] <= add3_ge5:A27.port1
+BCD_3[1] <= add3_ge5:A26.port1
+BCD_3[2] <= add3_ge5:A26.port1
+BCD_3[3] <= add3_ge5:A26.port1
+BCD_4[0] <= add3_ge5:A26.port1
+BCD_4[1] <= add3_ge5:A22.port1
+BCD_4[2] <= add3_ge5:A18.port1
+BCD_4[3] <= <GND>
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A1
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A2
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A3
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A4
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A5
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A6
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A7
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A8
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A9
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A10
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A11
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A12
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A13
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A14
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A15
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A16
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A17
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A18
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A19
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A20
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A21
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A22
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A23
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A24
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A25
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A26
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A27
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A28
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex6|bin2bcd_16:B|add3_ge5:A29
+w[0] => Decoder0.IN3
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diff --git a/part_2/ex6/db/ex6.hif b/part_2/ex6/db/ex6.hif
index f1930bf..922b5ce 100755
--- a/part_2/ex6/db/ex6.hif
+++ b/part_2/ex6/db/ex6.hif
diff --git a/part_2/ex6/db/ex6.lpc.html b/part_2/ex6/db/ex6.lpc.html
index e1700bc..86c7f81 100755
--- a/part_2/ex6/db/ex6.lpc.html
+++ b/part_2/ex6/db/ex6.lpc.html
@@ -1,610 +1,610 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >SEG4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A29</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A28</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A27</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A26</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A25</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A24</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A23</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A22</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A21</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A20</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A19</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A18</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A17</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A16</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A15</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A14</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A13</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A12</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A11</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A10</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A9</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A8</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A7</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A6</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A5</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A3</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B|A1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >B</TD>
-<TD >16</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >20</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >C</TD>
-<TD >3</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >16</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >tck</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A29</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A28</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A27</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A26</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A19</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A18</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A10</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A9</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A3</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B|A1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >B</TD>
+<TD >16</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >20</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >C</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >tck</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_2/ex6/db/ex6.lpc.rdb b/part_2/ex6/db/ex6.lpc.rdb
index c83ad8a..0635761 100755
--- a/part_2/ex6/db/ex6.lpc.rdb
+++ b/part_2/ex6/db/ex6.lpc.rdb
diff --git a/part_2/ex6/db/ex6.lpc.txt b/part_2/ex6/db/ex6.lpc.txt
index f546b48..f2fb5a2 100755
--- a/part_2/ex6/db/ex6.lpc.txt
+++ b/part_2/ex6/db/ex6.lpc.txt
@@ -1,43 +1,43 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A29     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A28     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A27     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A26     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A25     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A24     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A23     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A22     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A21     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A20     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A19     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A18     ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A17     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A16     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A15     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A14     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A13     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A12     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A11     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A10     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A9      ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A8      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A7      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A6      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A5      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A4      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A3      ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A2      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B|A1      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; B         ; 16    ; 1              ; 0            ; 1              ; 20     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; C         ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; tck       ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A29     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A28     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A27     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A26     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A25     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A24     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A23     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A22     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
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+; B|A15     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A14     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
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+; B|A12     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A11     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A10     ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A9      ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A8      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A7      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A6      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A5      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A4      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A3      ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A2      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B|A1      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; B         ; 16    ; 1              ; 0            ; 1              ; 20     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; C         ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; tck       ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex6/db/ex6.map.ammdb b/part_2/ex6/db/ex6.map.ammdb
index a4afc79..174eb00 100755
--- a/part_2/ex6/db/ex6.map.ammdb
+++ b/part_2/ex6/db/ex6.map.ammdb
diff --git a/part_2/ex6/db/ex6.map.bpm b/part_2/ex6/db/ex6.map.bpm
index c10665c..bb857d4 100755
--- a/part_2/ex6/db/ex6.map.bpm
+++ b/part_2/ex6/db/ex6.map.bpm
diff --git a/part_2/ex6/db/ex6.map.cdb b/part_2/ex6/db/ex6.map.cdb
index 0e9e5f2..728c972 100755
--- a/part_2/ex6/db/ex6.map.cdb
+++ b/part_2/ex6/db/ex6.map.cdb
diff --git a/part_2/ex6/db/ex6.map.hdb b/part_2/ex6/db/ex6.map.hdb
index 230028c..774cef6 100755
--- a/part_2/ex6/db/ex6.map.hdb
+++ b/part_2/ex6/db/ex6.map.hdb
diff --git a/part_2/ex6/db/ex6.map.kpt b/part_2/ex6/db/ex6.map.kpt
index 1110780..4c58c4c 100755
--- a/part_2/ex6/db/ex6.map.kpt
+++ b/part_2/ex6/db/ex6.map.kpt
diff --git a/part_2/ex6/db/ex6.map.logdb b/part_2/ex6/db/ex6.map.logdb
index 626799f..d45424f 100755
--- a/part_2/ex6/db/ex6.map.logdb
+++ b/part_2/ex6/db/ex6.map.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex6/db/ex6.map.qmsg b/part_2/ex6/db/ex6.map.qmsg
index 9e929a3..591b373 100755
--- a/part_2/ex6/db/ex6.map.qmsg
+++ b/part_2/ex6/db/ex6.map.qmsg
@@ -1,50 +1,51 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481479670637 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481479670651 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 18:07:50 2016 " "Processing started: Sun Dec 11 18:07:50 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481479670651 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479670651 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479670651 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481479670912 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481479670912 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679501 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679501 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679502 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679503 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679503 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679504 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679504 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679504 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679504 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" {  } { { "ex6.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679505 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679505 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481479679505 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479679505 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481479679548 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" {  } { { "ex6.v" "tck" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679550 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" {  } { { "ex6.v" "C" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679550 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" {  } { { "ex6.v" "B" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679551 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679552 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex6.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479679559 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481479680040 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481479680334 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481479680334 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481479680373 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481479680373 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481479680373 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481479680373 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1071 " "Peak virtual memory: 1071 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481479680379 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 18:08:00 2016 " "Processing ended: Sun Dec 11 18:08:00 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481479680379 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481479680379 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481479680379 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481479680379 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479814972603 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814972605 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:42:52 2016 " "Processing started: Tue Nov 22 11:42:52 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814972605 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814972605 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814972605 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479814973084 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479814973084 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981494 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981494 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981495 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981496 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981496 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex6/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981498 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981498 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex6/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981500 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981500 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" {  } { { "ex6.v" "" { Text "C:/New folder/ex6/ex6.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981503 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981503 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex6/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814981504 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814981504 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479814981532 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" {  } { { "ex6.v" "tck" { Text "C:/New folder/ex6/ex6.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981539 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" {  } { { "ex6.v" "C" { Text "C:/New folder/ex6/ex6.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981540 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" {  } { { "ex6.v" "B" { Text "C:/New folder/ex6/ex6.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981541 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981542 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex6.v" "SEG0" { Text "C:/New folder/ex6/ex6.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814981546 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479814982201 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.map.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814982507 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479814982587 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814982587 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479814982622 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479814982622 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479814982622 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479814982622 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "897 " "Peak virtual memory: 897 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:02 2016 " "Processing ended: Tue Nov 22 11:43:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814982634 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814982634 ""}
diff --git a/part_2/ex6/db/ex6.map.rdb b/part_2/ex6/db/ex6.map.rdb
index b328103..8b9a683 100755
--- a/part_2/ex6/db/ex6.map.rdb
+++ b/part_2/ex6/db/ex6.map.rdb
diff --git a/part_2/ex6/db/ex6.map_bb.cdb b/part_2/ex6/db/ex6.map_bb.cdb
index 21d85e3..b4b07ef 100755
--- a/part_2/ex6/db/ex6.map_bb.cdb
+++ b/part_2/ex6/db/ex6.map_bb.cdb
diff --git a/part_2/ex6/db/ex6.map_bb.hdb b/part_2/ex6/db/ex6.map_bb.hdb
index 7a1ee8d..d29fcef 100755
--- a/part_2/ex6/db/ex6.map_bb.hdb
+++ b/part_2/ex6/db/ex6.map_bb.hdb
diff --git a/part_2/ex6/db/ex6.map_bb.logdb b/part_2/ex6/db/ex6.map_bb.logdb
index 626799f..d45424f 100755
--- a/part_2/ex6/db/ex6.map_bb.logdb
+++ b/part_2/ex6/db/ex6.map_bb.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex6/db/ex6.pre_map.cdb b/part_2/ex6/db/ex6.pre_map.cdb
new file mode 100755
index 0000000..b754542
--- /dev/null
+++ b/part_2/ex6/db/ex6.pre_map.cdb
diff --git a/part_2/ex6/db/ex6.pre_map.hdb b/part_2/ex6/db/ex6.pre_map.hdb
index ed5b85a..8df99d8 100755
--- a/part_2/ex6/db/ex6.pre_map.hdb
+++ b/part_2/ex6/db/ex6.pre_map.hdb
diff --git a/part_2/ex6/db/ex6.quiproj.2528.rdr.flock b/part_2/ex6/db/ex6.quiproj.2528.rdr.flock
deleted file mode 100644
index e69de29..0000000
--- a/part_2/ex6/db/ex6.quiproj.2528.rdr.flock
+++ /dev/null
diff --git a/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb b/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb
index c5ac118..62aaf66 100755
--- a/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb
+++ b/part_2/ex6/db/ex6.root_partition.map.reg_db.cdb
diff --git a/part_2/ex6/db/ex6.routing.rdb b/part_2/ex6/db/ex6.routing.rdb
index 8c6966f..3790313 100755
--- a/part_2/ex6/db/ex6.routing.rdb
+++ b/part_2/ex6/db/ex6.routing.rdb
diff --git a/part_2/ex6/db/ex6.rtlv.hdb b/part_2/ex6/db/ex6.rtlv.hdb
index 98d4df4..ba7fb52 100755
--- a/part_2/ex6/db/ex6.rtlv.hdb
+++ b/part_2/ex6/db/ex6.rtlv.hdb
diff --git a/part_2/ex6/db/ex6.rtlv_sg.cdb b/part_2/ex6/db/ex6.rtlv_sg.cdb
index 497481a..ca2154e 100755
--- a/part_2/ex6/db/ex6.rtlv_sg.cdb
+++ b/part_2/ex6/db/ex6.rtlv_sg.cdb
diff --git a/part_2/ex6/db/ex6.rtlv_sg_swap.cdb b/part_2/ex6/db/ex6.rtlv_sg_swap.cdb
index dc11731..69494b0 100755
--- a/part_2/ex6/db/ex6.rtlv_sg_swap.cdb
+++ b/part_2/ex6/db/ex6.rtlv_sg_swap.cdb
diff --git a/part_2/ex6/db/ex6.sld_design_entry.sci b/part_2/ex6/db/ex6.sld_design_entry.sci
index 03eacdc..92c1102 100755
--- a/part_2/ex6/db/ex6.sld_design_entry.sci
+++ b/part_2/ex6/db/ex6.sld_design_entry.sci
diff --git a/part_2/ex6/db/ex6.sld_design_entry_dsc.sci b/part_2/ex6/db/ex6.sld_design_entry_dsc.sci
index 03eacdc..92c1102 100755
--- a/part_2/ex6/db/ex6.sld_design_entry_dsc.sci
+++ b/part_2/ex6/db/ex6.sld_design_entry_dsc.sci
diff --git a/part_2/ex6/db/ex6.smart_action.txt b/part_2/ex6/db/ex6.smart_action.txt
index c8e8a13..437a63e 100755
--- a/part_2/ex6/db/ex6.smart_action.txt
+++ b/part_2/ex6/db/ex6.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/part_2/ex6/db/ex6.sta.qmsg b/part_2/ex6/db/ex6.sta.qmsg
index 4203916..c1af911 100755
--- a/part_2/ex6/db/ex6.sta.qmsg
+++ b/part_2/ex6/db/ex6.sta.qmsg
@@ -1,50 +1,50 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481479717313 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481479717320 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 18:08:37 2016 " "Processing started: Sun Dec 11 18:08:37 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481479717320 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717320 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717320 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479717361 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717881 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717881 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717909 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479717909 ""}
-{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718392 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479718394 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718394 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718395 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718395 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479718396 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479718400 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.240 " "Worst-case setup slack is 15.240" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718404 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.240               0.000 CLOCK_50  " "   15.240               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718404 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718404 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.387 " "Worst-case hold slack is 0.387" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718405 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.387               0.000 CLOCK_50  " "    0.387               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718405 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718405 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718406 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718407 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.843 " "Worst-case minimum pulse width slack is 8.843" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.843               0.000 CLOCK_50  " "    8.843               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479718407 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718407 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479718412 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479718439 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719199 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479719243 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719243 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719244 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.100 " "Worst-case setup slack is 15.100" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.100               0.000 CLOCK_50  " "   15.100               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719246 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.386 " "Worst-case hold slack is 0.386" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.386               0.000 CLOCK_50  " "    0.386               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719246 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719246 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719247 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719247 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.841 " "Worst-case minimum pulse width slack is 8.841" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719248 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.841               0.000 CLOCK_50  " "    8.841               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479719248 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719248 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479719252 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479719378 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720016 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479720057 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720057 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720057 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.054 " "Worst-case setup slack is 17.054" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720058 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720058 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.054               0.000 CLOCK_50  " "   17.054               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720058 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720058 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.204               0.000 CLOCK_50  " "    0.204               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720059 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720059 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720059 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720060 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.791 " "Worst-case minimum pulse width slack is 8.791" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720060 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720060 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.791               0.000 CLOCK_50  " "    8.791               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720060 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720060 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481479720064 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481479720192 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720192 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720192 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.214 " "Worst-case setup slack is 17.214" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.214               0.000 CLOCK_50  " "   17.214               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720194 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.194               0.000 CLOCK_50  " "    0.194               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720194 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720194 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720195 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720195 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.764 " "Worst-case minimum pulse width slack is 8.764" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.764               0.000 CLOCK_50  " "    8.764               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481479720196 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479720196 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479721486 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479721487 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1214 " "Peak virtual memory: 1214 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481479721513 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 18:08:41 2016 " "Processing ended: Sun Dec 11 18:08:41 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481479721513 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481479721513 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481479721513 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481479721513 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479815021994 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479815021995 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:43:41 2016 " "Processing started: Tue Nov 22 11:43:41 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479815021995 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815021995 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815021995 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815022120 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022663 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022663 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022709 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815022709 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023227 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815023230 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023230 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023231 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023231 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023232 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023239 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.377 " "Worst-case setup slack is 15.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.377               0.000 CLOCK_50  " "   15.377               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023245 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023245 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.388 " "Worst-case hold slack is 0.388" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.388               0.000 CLOCK_50  " "    0.388               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023247 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023247 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023248 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023250 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.900 " "Worst-case minimum pulse width slack is 8.900" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.900               0.000 CLOCK_50  " "    8.900               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815023251 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023251 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815023260 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815023294 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024133 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815024176 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024176 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024176 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.286 " "Worst-case setup slack is 15.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.286               0.000 CLOCK_50  " "   15.286               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024181 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024181 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.385 " "Worst-case hold slack is 0.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024183 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024183 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024184 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024186 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.899 " "Worst-case minimum pulse width slack is 8.899" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.899               0.000 CLOCK_50  " "    8.899               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815024188 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024188 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815024196 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815024344 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025047 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815025091 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025091 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025091 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.068 " "Worst-case setup slack is 17.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.068               0.000 CLOCK_50  " "   17.068               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025094 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025094 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.204               0.000 CLOCK_50  " "    0.204               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025095 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025095 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025097 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025098 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.836 " "Worst-case minimum pulse width slack is 8.836" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.836               0.000 CLOCK_50  " "    8.836               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025100 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025100 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479815025108 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479815025253 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025253 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025253 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.237 " "Worst-case setup slack is 17.237" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.237               0.000 CLOCK_50  " "   17.237               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025256 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025256 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.194               0.000 CLOCK_50  " "    0.194               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025258 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025258 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025259 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025261 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.806 " "Worst-case minimum pulse width slack is 8.806" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.806               0.000 CLOCK_50  " "    8.806               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479815025262 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815025262 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026650 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026651 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1209 " "Peak virtual memory: 1209 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:43:46 2016 " "Processing ended: Tue Nov 22 11:43:46 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479815026692 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479815026692 ""}
diff --git a/part_2/ex6/db/ex6.sta.rdb b/part_2/ex6/db/ex6.sta.rdb
index 3775235..ee18610 100755
--- a/part_2/ex6/db/ex6.sta.rdb
+++ b/part_2/ex6/db/ex6.sta.rdb
diff --git a/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb
index f96e901..8e7dea4 100755
--- a/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb
+++ b/part_2/ex6/db/ex6.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex6/db/ex6.tis_db_list.ddb b/part_2/ex6/db/ex6.tis_db_list.ddb
index 2df45d7..88225e8 100755
--- a/part_2/ex6/db/ex6.tis_db_list.ddb
+++ b/part_2/ex6/db/ex6.tis_db_list.ddb
diff --git a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb
index 5a8d3c0..ff58cae 100755
--- a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb
+++ b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb
index 845e816..c8bf679 100755
--- a/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb
+++ b/part_2/ex6/db/ex6.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb
index e22b58a..6e31afe 100755
--- a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb
+++ b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb
index 2234005..9ed3347 100755
--- a/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb
+++ b/part_2/ex6/db/ex6.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex6/db/ex6.tmw_info b/part_2/ex6/db/ex6.tmw_info
index 3f7354a..7f48734 100755
--- a/part_2/ex6/db/ex6.tmw_info
+++ b/part_2/ex6/db/ex6.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:00:52
-start_analysis_synthesis:s:00:00:11-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:29-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
-start_timing_analyzer:s:00:00:05-start_full_compilation
+start_full_compilation:s
+start_analysis_synthesis:s-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s-start_full_compilation
+start_assembler:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
diff --git a/part_2/ex6/db/ex6.vpr.ammdb b/part_2/ex6/db/ex6.vpr.ammdb
index bbc75a3..b265f17 100755
--- a/part_2/ex6/db/ex6.vpr.ammdb
+++ b/part_2/ex6/db/ex6.vpr.ammdb
diff --git a/part_2/ex6/db/ex6_partition_pins.json b/part_2/ex6/db/ex6_partition_pins.json
index 4227300..1a004e3 100755
--- a/part_2/ex6/db/ex6_partition_pins.json
+++ b/part_2/ex6/db/ex6_partition_pins.json
@@ -1,161 +1,161 @@
-{
-	"partitions" : [
-		{
-			"name" : "Top",
-			"pins" : [
-				{
-					"name" : "HEX0[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[6]",
-					"strict" : false
-				},
-				{
-					"name" : "KEY[1]",
-					"strict" : false
-				},
-				{
-					"name" : "KEY[0]",
-					"strict" : false
-				},
-				{
-					"name" : "CLOCK_50",
-					"strict" : false
-				}
-			]
-		}
-	]
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[6]",
+					"strict" : false
+				},
+				{
+					"name" : "KEY[1]",
+					"strict" : false
+				},
+				{
+					"name" : "KEY[0]",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				}
+			]
+		}
+	]
 }
 \ No newline at end of file
diff --git a/part_2/ex6/db/prev_cmp_ex6.qmsg b/part_2/ex6/db/prev_cmp_ex6.qmsg
index 9ed0041..3ef48ff 100755
--- a/part_2/ex6/db/prev_cmp_ex6.qmsg
+++ b/part_2/ex6/db/prev_cmp_ex6.qmsg
@@ -1,160 +1,160 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481478912139 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481478912154 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 17:55:11 2016 " "Processing started: Sun Dec 11 17:55:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481478912154 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478912154 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478912154 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481478912723 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481478912723 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921441 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921441 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921443 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921444 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921444 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921445 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921445 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921446 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921446 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" {  } { { "ex6.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921447 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921447 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481478921447 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478921447 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481478921538 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" {  } { { "ex6.v" "tck" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921631 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" {  } { { "ex6.v" "C" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921639 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" {  } { { "ex6.v" "B" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921644 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921655 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex6.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478921668 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481478922578 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481478923202 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481478923202 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481478923789 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481478923789 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481478923789 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481478923789 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1052 " "Peak virtual memory: 1052 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481478923801 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 17:55:23 2016 " "Processing ended: Sun Dec 11 17:55:23 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481478923801 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481478923801 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481478923801 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481478923801 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1481478925691 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481478925699 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 17:55:24 2016 " "Processing started: Sun Dec 11 17:55:24 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481478925699 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1481478925699 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1481478925699 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1481478926149 ""}
-{ "Info" "0" "" "Project  = ex6" {  } {  } 0 0 "Project  = ex6" 0 0 "Fitter" 0 0 1481478926156 ""}
-{ "Info" "0" "" "Revision = ex6" {  } {  } 0 0 "Revision = ex6" 0 0 "Fitter" 0 0 1481478926156 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481478926329 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481478926329 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481478926347 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481478926466 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481478926466 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481478927033 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481478927140 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481478927728 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481478938933 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481478939030 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481478939030 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478939030 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481478939053 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481478939053 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481478939054 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481478939054 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481478939054 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481478939054 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481478939054 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481478939055 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481478939055 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481478939237 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481478939237 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478939239 ""}
-{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1481478945297 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478945312 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1481478945312 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481478945323 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481478945323 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1481478945324 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481478945325 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481478945325 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1481478945325 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1481478945325 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481478945341 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481478945481 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478946550 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481478947153 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481478947480 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478947480 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481478948735 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y11 X89_Y22 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22" {  } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22"} { { 12 { 0 ""} 78 11 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481478953134 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481478953134 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481478953372 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1481478953372 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481478953372 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478953374 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.11 " "Total time spent on timing analysis during the Fitter is 0.11 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481478955241 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481478955281 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481478955855 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481478955855 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481478956206 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481478958150 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481478958279 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481478958364 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 49 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 49 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2136 " "Peak virtual memory: 2136 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481478958789 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 17:55:58 2016 " "Processing ended: Sun Dec 11 17:55:58 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481478958789 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481478958789 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:50 " "Total CPU time (on all processors): 00:00:50" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481478958789 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481478958789 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1481478960949 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481478960966 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 17:56:00 2016 " "Processing started: Sun Dec 11 17:56:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481478960966 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481478960966 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481478960967 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481478961599 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481478967716 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "977 " "Peak virtual memory: 977 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481478968247 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 17:56:08 2016 " "Processing ended: Sun Dec 11 17:56:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481478968247 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481478968247 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481478968247 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481478968247 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1481478968422 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1481478969236 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481478969243 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 17:56:08 2016 " "Processing started: Sun Dec 11 17:56:08 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481478969243 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969243 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969244 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478969319 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969844 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969844 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969888 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478969888 ""}
-{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970377 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478970380 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970380 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970381 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970381 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478970381 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478970386 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.240 " "Worst-case setup slack is 15.240" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970396 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970396 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.240               0.000 CLOCK_50  " "   15.240               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970396 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970396 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.387 " "Worst-case hold slack is 0.387" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.387               0.000 CLOCK_50  " "    0.387               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970397 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970397 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970398 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970398 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.843 " "Worst-case minimum pulse width slack is 8.843" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970399 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970399 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.843               0.000 CLOCK_50  " "    8.843               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478970399 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970399 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478970424 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478970479 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971484 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478971528 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971528 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971529 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.100 " "Worst-case setup slack is 15.100" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.100               0.000 CLOCK_50  " "   15.100               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971531 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.386 " "Worst-case hold slack is 0.386" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.386               0.000 CLOCK_50  " "    0.386               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971531 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971531 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971532 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971532 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.841 " "Worst-case minimum pulse width slack is 8.841" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.841               0.000 CLOCK_50  " "    8.841               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478971533 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971533 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478971537 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478971687 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972489 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478972532 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972532 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972532 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.054 " "Worst-case setup slack is 17.054" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.054               0.000 CLOCK_50  " "   17.054               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972533 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972533 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.204               0.000 CLOCK_50  " "    0.204               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972534 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972534 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972535 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972535 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.791 " "Worst-case minimum pulse width slack is 8.791" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972536 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972536 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.791               0.000 CLOCK_50  " "    8.791               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972536 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972536 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481478972540 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1481478972668 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972668 "|ex6|tick_50000:tck|CLK_OUT"}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972669 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.214 " "Worst-case setup slack is 17.214" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972670 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.214               0.000 CLOCK_50  " "   17.214               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972670 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972670 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972671 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972671 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.194               0.000 CLOCK_50  " "    0.194               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972671 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972671 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972671 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972672 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.764 " "Worst-case minimum pulse width slack is 8.764" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.764               0.000 CLOCK_50  " "    8.764               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481478972673 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478972673 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478973979 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478973981 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1222 " "Peak virtual memory: 1222 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481478974007 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 17:56:14 2016 " "Processing ended: Sun Dec 11 17:56:14 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481478974007 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481478974007 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481478974007 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478974007 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 56 s " "Quartus Prime Full Compilation was successful. 0 errors, 56 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481478974202 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479814855590 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814855591 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:40:55 2016 " "Processing started: Tue Nov 22 11:40:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814855591 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814855591 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814855592 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1479814856068 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1479814856068 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex6/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864502 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864502 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864503 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1479814864504 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864505 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864505 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex6/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864506 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864506 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex6/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864507 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864507 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex6.v 1 1 " "Found 1 design units, including 1 entities, in source file ex6.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex6 " "Found entity 1: ex6" {  } { { "ex6.v" "" { Text "C:/New folder/ex6/ex6.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864509 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864509 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex6/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1479814864512 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814864512 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex6 " "Elaborating entity \"ex6\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1479814864538 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:tck " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:tck\"" {  } { { "ex6.v" "tck" { Text "C:/New folder/ex6/ex6.v" 11 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864541 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:C " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:C\"" {  } { { "ex6.v" "C" { Text "C:/New folder/ex6/ex6.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864547 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:B " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:B\"" {  } { { "ex6.v" "B" { Text "C:/New folder/ex6/ex6.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864547 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:B\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:B\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex6/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864548 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex6.v" "SEG0" { Text "C:/New folder/ex6/ex6.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814864552 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1479814865202 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.map.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814865495 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1479814865576 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1479814865576 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "225 " "Implemented 225 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1479814865610 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1479814865610 ""} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Implemented 187 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1479814865610 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1479814865610 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "899 " "Peak virtual memory: 899 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:05 2016 " "Processing ended: Tue Nov 22 11:41:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814865623 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1479814865623 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1479814867084 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814867085 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:06 2016 " "Processing started: Tue Nov 22 11:41:06 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814867085 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1479814867085 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1479814867085 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1479814867201 ""}
+{ "Info" "0" "" "Project  = ex6" {  } {  } 0 0 "Project  = ex6" 0 0 "Fitter" 0 0 1479814867202 ""}
+{ "Info" "0" "" "Revision = ex6" {  } {  } 0 0 "Revision = ex6" 0 0 "Fitter" 0 0 1479814867202 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1479814867313 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1479814867314 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex6 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex6\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1479814867575 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814867638 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1479814867638 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1479814868022 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1479814868156 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1479814878204 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1479814878285 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1479814878285 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814878285 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1479814878288 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814878288 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1479814878288 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1479814878289 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1479814878289 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1479814878289 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1479814878289 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1479814878290 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1479814878290 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1479814878324 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1479814878324 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814878326 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1479814883778 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814883780 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1479814883780 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1479814883781 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1479814883781 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1479814883782 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1479814883782 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1479814883782 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1479814883786 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1479814883871 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814884487 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1479814885162 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1479814885489 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814885489 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1479814886599 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex6/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1479814891026 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1479814891026 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1479814891312 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1479814891312 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1479814891312 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814891315 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1479814892475 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479814892512 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479814892890 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1479814892891 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1479814893257 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1479814895619 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1479814895860 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex6/output_files/ex6.fit.smsg " "Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1479814895916 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 48 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 48 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2589 " "Peak virtual memory: 2589 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:36 2016 " "Processing ended: Tue Nov 22 11:41:36 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:53 " "Total CPU time (on all processors): 00:00:53" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814896340 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1479814896340 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1479814897635 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814897638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:37 2016 " "Processing started: Tue Nov 22 11:41:37 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814897638 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1479814897638 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1479814897638 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1479814898389 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1479814902980 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "893 " "Peak virtual memory: 893 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:43 2016 " "Processing ended: Tue Nov 22 11:41:43 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814903314 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1479814903314 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1479814903979 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1479814904803 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479814904804 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 22 11:41:44 2016 " "Processing started: Tue Nov 22 11:41:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479814904804 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814904804 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex6 -c ex6 " "Command: quartus_sta ex6 -c ex6" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814904804 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814904930 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905472 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905472 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905519 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814905519 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex6.sdc " "Reading SDC File: 'ex6.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906037 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814906040 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906040 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906041 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906041 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906042 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906049 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.377 " "Worst-case setup slack is 15.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.377               0.000 CLOCK_50  " "   15.377               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906055 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906055 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.388 " "Worst-case hold slack is 0.388" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.388               0.000 CLOCK_50  " "    0.388               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906057 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906057 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906058 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906060 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.900 " "Worst-case minimum pulse width slack is 8.900" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.900               0.000 CLOCK_50  " "    8.900               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906061 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906061 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906070 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906104 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906927 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814906969 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906969 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906969 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 15.286 " "Worst-case setup slack is 15.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.286               0.000 CLOCK_50  " "   15.286               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906974 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906974 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.385 " "Worst-case hold slack is 0.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906976 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906976 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906977 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906979 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.899 " "Worst-case minimum pulse width slack is 8.899" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.899               0.000 CLOCK_50  " "    8.899               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814906980 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814906980 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814906989 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907132 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907832 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814907877 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907877 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907877 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.068 " "Worst-case setup slack is 17.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.068               0.000 CLOCK_50  " "   17.068               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907880 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907880 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.204 " "Worst-case hold slack is 0.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.204               0.000 CLOCK_50  " "    0.204               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907883 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907883 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907885 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907887 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.836 " "Worst-case minimum pulse width slack is 8.836" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.836               0.000 CLOCK_50  " "    8.836               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814907888 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814907888 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1479814907897 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "tick_50000:tck\|CLK_OUT " "Node: tick_50000:tck\|CLK_OUT was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register counter_16:C\|count\[0\] tick_50000:tck\|CLK_OUT " "Register counter_16:C\|count\[0\] is being clocked by tick_50000:tck\|CLK_OUT" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1479814908038 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908038 "|ex6|tick_50000:tck|CLK_OUT"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908039 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.237 " "Worst-case setup slack is 17.237" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.237               0.000 CLOCK_50  " "   17.237               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908041 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908041 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.194 " "Worst-case hold slack is 0.194" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.194               0.000 CLOCK_50  " "    0.194               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908043 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908043 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908045 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908046 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.806 " "Worst-case minimum pulse width slack is 8.806" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.806               0.000 CLOCK_50  " "    8.806               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1479814908048 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814908048 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909430 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909431 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1207 " "Peak virtual memory: 1207 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 22 11:41:49 2016 " "Processing ended: Tue Nov 22 11:41:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479814909471 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814909471 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 55 s " "Quartus Prime Full Compilation was successful. 0 errors, 55 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1479814910195 ""}
diff --git a/part_2/ex6/ex6.qsf b/part_2/ex6/ex6.qsf
index 7d53d75..1352d53 100755
--- a/part_2/ex6/ex6.qsf
+++ b/part_2/ex6/ex6.qsf
@@ -252,7 +252,7 @@ set_global_assignment -name DEVICE 5CSEMA5F31C6
 set_global_assignment -name TOP_LEVEL_ENTITY ex6
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:55:22  NOVEMBER 22, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
diff --git a/part_2/ex6/ex6.qws b/part_2/ex6/ex6.qws
new file mode 100755
index 0000000..63563b7
--- /dev/null
+++ b/part_2/ex6/ex6.qws
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info b/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info
index 4f976f6..41f92fa 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Version_Index = 419480576
-Creation_Time = Sun Dec 11 17:54:40 2016
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Nov 22 10:11:38 2016
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb
index b5923ef..ab3bea2 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.ammdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb
index 7ee96a8..dae0e0b 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb
index 996a72c..21a86b2 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb
index 48ea6fd..8907c68 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb
index a0b4222..26f78b7 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb
index 626799f..d45424f 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb
index 4f6e44b..cd9fac3 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.cmp.rcfdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb
index 97b904d..3b77930 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi
index d6def8f..10da539 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.dpi
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb
index ac84755..5b4ee25 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb
index f4f72fa..0cd555d 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hbdb.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb
index 96c2f5b..9c8db47 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt
index 9d8eb24..722be46 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.kpt
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb
new file mode 100755
index 0000000..1f45a5a
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olf.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb
new file mode 100755
index 0000000..6e951b6
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.olm.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb
new file mode 100755
index 0000000..c78c5d1
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.oln.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.opi b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi
index 56a6051..56a6051 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.opi
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.opi
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb
new file mode 100755
index 0000000..1f45a5a
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orf.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb
new file mode 100755
index 0000000..d995b24
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orm.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb
new file mode 100755
index 0000000..450e420
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.map.orn.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb
new file mode 100755
index 0000000..3b77930
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdb
index 9f6309e..5b4ee25 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.cdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..0cd555d
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hbdb.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb
new file mode 100755
index 0000000..9c8db47
--- /dev/null
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.root_partition.rrp.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb
index add48cc..88368d0 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrp.hdb
diff --git a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb
index 7f54a15..971696d 100755
--- a/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb
+++ b/part_2/ex6/incremental_db/compiled_partitions/ex6.rrs.cdb
diff --git a/part_2/ex6/output_files/ex6.asm.rpt b/part_2/ex6/output_files/ex6.asm.rpt
index 303516d..c99b821 100755
--- a/part_2/ex6/output_files/ex6.asm.rpt
+++ b/part_2/ex6/output_files/ex6.asm.rpt
@@ -1,92 +1,92 @@
-Assembler report for ex6
-Sun Dec 11 18:08:36 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: ex6.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Sun Dec 11 18:08:36 2016 ;
-; Revision Name         ; ex6                                   ;
-; Top-level Entity Name ; ex6                                   ;
-; Family                ; Cyclone V                             ;
-; Device                ; 5CSEMA5F31C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings               ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+---------------------------+
-; Assembler Generated Files ;
-+---------------------------+
-; File Name                 ;
-+---------------------------+
-; ex6.sof                   ;
-+---------------------------+
-
-
-+-----------------------------------+
-; Assembler Device Options: ex6.sof ;
-+----------------+------------------+
-; Option         ; Setting          ;
-+----------------+------------------+
-; Device         ; 5CSEMA5F31C6     ;
-; JTAG usercode  ; 0x00B261DF       ;
-; Checksum       ; 0x00B261DF       ;
-+----------------+------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 18:08:30 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 976 megabytes
-    Info: Processing ended: Sun Dec 11 18:08:36 2016
-    Info: Elapsed time: 00:00:06
-    Info: Total CPU time (on all processors): 00:00:06
-
-
+Assembler report for ex6
+Tue Nov 22 11:43:40 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/New folder/ex6/output_files/ex6.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Nov 22 11:43:40 2016 ;
+; Revision Name         ; ex6                                   ;
+; Top-level Entity Name ; ex6                                   ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++----------------------------------------+
+; Assembler Generated Files              ;
++----------------------------------------+
+; File Name                              ;
++----------------------------------------+
+; C:/New folder/ex6/output_files/ex6.sof ;
++----------------------------------------+
+
+
++------------------------------------------------------------------+
+; Assembler Device Options: C:/New folder/ex6/output_files/ex6.sof ;
++----------------+-------------------------------------------------+
+; Option         ; Setting                                         ;
++----------------+-------------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                    ;
+; JTAG usercode  ; 0x00B27652                                      ;
+; Checksum       ; 0x00B27652                                      ;
++----------------+-------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Tue Nov 22 11:43:34 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 893 megabytes
+    Info: Processing ended: Tue Nov 22 11:43:40 2016
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex6/output_files/ex6.done b/part_2/ex6/output_files/ex6.done
index 5572926..33dea98 100755
--- a/part_2/ex6/output_files/ex6.done
+++ b/part_2/ex6/output_files/ex6.done
@@ -1 +1 @@
-Sun Dec 11 18:08:41 2016
+Tue Nov 22 11:43:47 2016
diff --git a/part_2/ex6/output_files/ex6.fit.rpt b/part_2/ex6/output_files/ex6.fit.rpt
index dc8ac28..b0a72b2 100755
--- a/part_2/ex6/output_files/ex6.fit.rpt
+++ b/part_2/ex6/output_files/ex6.fit.rpt
@@ -1,2034 +1,2034 @@
-Fitter report for ex6
-Sun Dec 11 18:08:29 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. Fitter Netlist Optimizations
-  6. Ignored Assignments
-  7. Incremental Compilation Preservation Summary
-  8. Incremental Compilation Partition Settings
-  9. Incremental Compilation Placement Preservation
- 10. Pin-Out File
- 11. Fitter Resource Usage Summary
- 12. Fitter Partition Statistics
- 13. Input Pins
- 14. Output Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. I/O Rules Summary
- 25. I/O Rules Details
- 26. I/O Rules Matrix
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing Summary
- 30. Estimated Delay Added for Hold Timing Details
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Fitter Summary                                                                ;
-+---------------------------------+---------------------------------------------+
-; Fitter Status                   ; Successful - Sun Dec 11 18:08:29 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex6                                         ;
-; Top-level Entity Name           ; ex6                                         ;
-; Family                          ; Cyclone V                                   ;
-; Device                          ; 5CSEMA5F31C6                                ;
-; Timing Models                   ; Final                                       ;
-; Logic utilization (in ALMs)     ; 99 / 32,070 ( < 1 % )                       ;
-; Total registers                 ; 33                                          ;
-; Total pins                      ; 38 / 457 ( 8 % )                            ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                       ;
-; Total RAM Blocks                ; 0 / 397 ( 0 % )                             ;
-; Total DSP Blocks                ; 0 / 87 ( 0 % )                              ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0 / 6 ( 0 % )                               ;
-; Total DLLs                      ; 0 / 4 ( 0 % )                               ;
-+---------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
-; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
-; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
-; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; Clamping Diode                                                             ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.01        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.5%      ;
-;     Processor 3            ;   0.5%      ;
-;     Processor 4            ;   0.5%      ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations                                                                                                                                        ;
-+-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
-; Node                  ; Action  ; Operation ; Reason                     ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
-+-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ;           ;                ;                  ;                  ;                       ;
-+-----------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Ignored Assignments                                                                        ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
-; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;
-; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;
-; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;
-; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
-; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
-; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
-; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex6            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                     ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 )         ; 0.00 % ( 0 / 298 )       ;
-;     -- Achieved     ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 )         ; 0.00 % ( 0 / 298 )       ;
-;                     ;                    ;                            ;                          ;
-; Routing (by net)    ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 298 )    ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.pin.
-
-
-+------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                                            ;
-+-------------------------------------------------------------+--------------------+-------+
-; Resource                                                    ; Usage              ; %     ;
-+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 99 / 32,070        ; < 1 % ;
-; ALMs needed [=A-B+C]                                        ; 99                 ;       ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 100 / 32,070       ; < 1 % ;
-;         [a] ALMs used for LUT logic and registers           ; 16                 ;       ;
-;         [b] ALMs used for LUT logic                         ; 83                 ;       ;
-;         [c] ALMs used for registers                         ; 1                  ;       ;
-;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 1 / 32,070         ; < 1 % ;
-;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
-;         [a] Due to location constrained logic               ; 0                  ;       ;
-;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
-;         [c] Due to LAB input limits                         ; 0                  ;       ;
-;         [d] Due to virtual I/Os                             ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Difficulty packing design                                   ; Low                ;       ;
-;                                                             ;                    ;       ;
-; Total LABs:  partially or completely used                   ; 15 / 3,207         ; < 1 % ;
-;     -- Logic LABs                                           ; 15                 ;       ;
-;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Combinational ALUT usage for logic                          ; 188                ;       ;
-;     -- 7 input functions                                    ; 0                  ;       ;
-;     -- 6 input functions                                    ; 9                  ;       ;
-;     -- 5 input functions                                    ; 3                  ;       ;
-;     -- 4 input functions                                    ; 124                ;       ;
-;     -- <=3 input functions                                  ; 52                 ;       ;
-; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;
-;                                                             ;                    ;       ;
-; Dedicated logic registers                                   ; 33                 ;       ;
-;     -- By type:                                             ;                    ;       ;
-;         -- Primary logic registers                          ; 33 / 64,140        ; < 1 % ;
-;         -- Secondary logic registers                        ; 0 / 64,140         ; 0 %   ;
-;     -- By function:                                         ;                    ;       ;
-;         -- Design implementation registers                  ; 33                 ;       ;
-;         -- Routing optimization registers                   ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Virtual pins                                                ; 0                  ;       ;
-; I/O pins                                                    ; 38 / 457           ; 8 %   ;
-;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;
-;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
-;                                                             ;                    ;       ;
-; Hard processor system peripheral utilization                ;                    ;       ;
-;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
-;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
-;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
-;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
-;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
-;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
-;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
-;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
-;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
-;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
-;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
-;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
-;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
-;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
-;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
-;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
-;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
-;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
-;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
-;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
-;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
-;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
-;                                                             ;                    ;       ;
-; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
-; Total MLAB memory bits                                      ; 0                  ;       ;
-; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
-; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
-;                                                             ;                    ;       ;
-; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
-;                                                             ;                    ;       ;
-; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
-; Global signals                                              ; 1                  ;       ;
-;     -- Global clocks                                        ; 1 / 16             ; 6 %   ;
-;     -- Quadrant clocks                                      ; 0 / 66             ; 0 %   ;
-;     -- Horizontal periphery clocks                          ; 0 / 18             ; 0 %   ;
-; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
-; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
-; JTAGs                                                       ; 0 / 1              ; 0 %   ;
-; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
-; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
-; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
-; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
-; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
-; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
-; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
-; Peak interconnect usage (total/H/V)                         ; 0.8% / 0.7% / 1.0% ;       ;
-; Maximum fan-out                                             ; 17                 ;       ;
-; Highest non-global fan-out                                  ; 17                 ;       ;
-; Total fan-out                                               ; 848                ;       ;
-; Average fan-out                                             ; 2.84               ;       ;
-+-------------------------------------------------------------+--------------------+-------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                                          ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 99 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
-; ALMs needed [=A-B+C]                                        ; 99                    ; 0                              ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 100 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-;         [a] ALMs used for LUT logic and registers           ; 16                    ; 0                              ;
-;         [b] ALMs used for LUT logic                         ; 83                    ; 0                              ;
-;         [c] ALMs used for registers                         ; 1                     ; 0                              ;
-;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 1 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
-;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
-;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
-;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
-;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
-;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Difficulty packing design                                   ; Low                   ; Low                            ;
-;                                                             ;                       ;                                ;
-; Total LABs:  partially or completely used                   ; 15 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
-;     -- Logic LABs                                           ; 15                    ; 0                              ;
-;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Combinational ALUT usage for logic                          ; 188                   ; 0                              ;
-;     -- 7 input functions                                    ; 0                     ; 0                              ;
-;     -- 6 input functions                                    ; 9                     ; 0                              ;
-;     -- 5 input functions                                    ; 3                     ; 0                              ;
-;     -- 4 input functions                                    ; 124                   ; 0                              ;
-;     -- <=3 input functions                                  ; 52                    ; 0                              ;
-; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;
-; Memory ALUT usage                                           ; 0                     ; 0                              ;
-;     -- 64-address deep                                      ; 0                     ; 0                              ;
-;     -- 32-address deep                                      ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Dedicated logic registers                                   ; 0                     ; 0                              ;
-;     -- By type:                                             ;                       ;                                ;
-;         -- Primary logic registers                          ; 33 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
-;         -- Secondary logic registers                        ; 0 / 64140 ( 0 % )     ; 0 / 64140 ( 0 % )              ;
-;     -- By function:                                         ;                       ;                                ;
-;         -- Design implementation registers                  ; 33                    ; 0                              ;
-;         -- Routing optimization registers                   ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-;                                                             ;                       ;                                ;
-; Virtual pins                                                ; 0                     ; 0                              ;
-; I/O pins                                                    ; 38                    ; 0                              ;
-; I/O registers                                               ; 0                     ; 0                              ;
-; Total block memory bits                                     ; 0                     ; 0                              ;
-; Total block memory implementation bits                      ; 0                     ; 0                              ;
-; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
-;                                                             ;                       ;                                ;
-; Connections                                                 ;                       ;                                ;
-;     -- Input Connections                                    ; 0                     ; 0                              ;
-;     -- Registered Input Connections                         ; 0                     ; 0                              ;
-;     -- Output Connections                                   ; 0                     ; 0                              ;
-;     -- Registered Output Connections                        ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Internal Connections                                        ;                       ;                                ;
-;     -- Total Connections                                    ; 848                   ; 0                              ;
-;     -- Registered Connections                               ; 139                   ; 0                              ;
-;                                                             ;                       ;                                ;
-; External Connections                                        ;                       ;                                ;
-;     -- Top                                                  ; 0                     ; 0                              ;
-;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Partition Interface                                         ;                       ;                                ;
-;     -- Input Ports                                          ; 3                     ; 0                              ;
-;     -- Output Ports                                         ; 35                    ; 0                              ;
-;     -- Bidir Ports                                          ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Registered Ports                                            ;                       ;                                ;
-;     -- Registered Input Ports                               ; 0                     ; 0                              ;
-;     -- Registered Output Ports                              ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Port Connectivity                                           ;                       ;                                ;
-;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
-;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
-;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
-;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
-;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
-;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
-;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
-;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                              ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 17                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 17                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+----------------------------------------------------------------------------+
-; I/O Bank Usage                                                             ;
-+----------+------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+------------------+---------------+--------------+---------------+
-; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
-; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
-; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 3B       ; 3 / 48 ( 6 % )   ; 3.3V          ; --           ; 3.3V          ;
-; 4A       ; 0 / 80 ( 0 % )   ; 3.3V          ; --           ; 3.3V          ;
-; 5A       ; 27 / 32 ( 84 % ) ; 3.3V          ; --           ; 3.3V          ;
-; 5B       ; 8 / 16 ( 50 % )  ; 3.3V          ; --           ; 3.3V          ;
-; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-+----------+------------------+---------------+--------------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                  ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
-; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
-; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
-; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
-; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings                         ;
-+----------+--------------------------------------+
-; Pin Name ; Reason                               ;
-+----------+--------------------------------------+
-; HEX0[0]  ; Missing drive strength and slew rate ;
-; HEX0[1]  ; Missing drive strength and slew rate ;
-; HEX0[2]  ; Missing drive strength and slew rate ;
-; HEX0[3]  ; Missing drive strength and slew rate ;
-; HEX0[4]  ; Missing drive strength and slew rate ;
-; HEX0[5]  ; Missing drive strength and slew rate ;
-; HEX0[6]  ; Missing drive strength and slew rate ;
-; HEX1[0]  ; Missing drive strength and slew rate ;
-; HEX1[1]  ; Missing drive strength and slew rate ;
-; HEX1[2]  ; Missing drive strength and slew rate ;
-; HEX1[3]  ; Missing drive strength and slew rate ;
-; HEX1[4]  ; Missing drive strength and slew rate ;
-; HEX1[5]  ; Missing drive strength and slew rate ;
-; HEX1[6]  ; Missing drive strength and slew rate ;
-; HEX2[0]  ; Missing drive strength and slew rate ;
-; HEX2[1]  ; Missing drive strength and slew rate ;
-; HEX2[2]  ; Missing drive strength and slew rate ;
-; HEX2[3]  ; Missing drive strength and slew rate ;
-; HEX2[4]  ; Missing drive strength and slew rate ;
-; HEX2[5]  ; Missing drive strength and slew rate ;
-; HEX2[6]  ; Missing drive strength and slew rate ;
-; HEX3[0]  ; Missing drive strength and slew rate ;
-; HEX3[1]  ; Missing drive strength and slew rate ;
-; HEX3[2]  ; Missing drive strength and slew rate ;
-; HEX3[3]  ; Missing drive strength and slew rate ;
-; HEX3[4]  ; Missing drive strength and slew rate ;
-; HEX3[5]  ; Missing drive strength and slew rate ;
-; HEX3[6]  ; Missing drive strength and slew rate ;
-; HEX4[0]  ; Missing drive strength and slew rate ;
-; HEX4[1]  ; Missing drive strength and slew rate ;
-; HEX4[2]  ; Missing drive strength and slew rate ;
-; HEX4[3]  ; Missing drive strength and slew rate ;
-; HEX4[4]  ; Missing drive strength and slew rate ;
-; HEX4[5]  ; Missing drive strength and slew rate ;
-; HEX4[6]  ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                             ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
-; |ex6                       ; 98.5 (0.5)           ; 99.5 (0.5)                       ; 1.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 188 (1)             ; 33 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 38   ; 0            ; |ex6                           ; ex6         ; work         ;
-;    |bin2bcd_16:B|          ; 57.0 (0.0)           ; 57.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 106 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A1|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A10|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 1.5 (1.5)            ; 1.5 (1.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:C|          ; 8.5 (8.5)            ; 8.5 (8.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 16 (16)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|counter_16:C              ; counter_16  ; work         ;
-;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG0          ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG1          ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG2          ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG3          ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG4          ; hex_to_7seg ; work         ;
-;    |tick_50000:tck|        ; 15.0 (15.0)          ; 16.0 (16.0)                      ; 1.0 (1.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 29 (29)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|tick_50000:tck            ; tick_50000  ; work         ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                                                     ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; KEY[1]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[0]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-
-
-+---------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                                ;
-+---------------------------------+-------------------+---------+
-; Source Pin / Fanout             ; Pad To Core Index ; Setting ;
-+---------------------------------+-------------------+---------+
-; KEY[1]                          ;                   ;         ;
-;      - counter_16:C|count[11]   ; 0                 ; 0       ;
-;      - counter_16:C|count[15]   ; 0                 ; 0       ;
-;      - counter_16:C|count[14]   ; 0                 ; 0       ;
-;      - counter_16:C|count[13]   ; 0                 ; 0       ;
-;      - counter_16:C|count[12]   ; 0                 ; 0       ;
-;      - counter_16:C|count[10]   ; 0                 ; 0       ;
-;      - counter_16:C|count[9]    ; 0                 ; 0       ;
-;      - counter_16:C|count[7]    ; 0                 ; 0       ;
-;      - counter_16:C|count[8]    ; 0                 ; 0       ;
-;      - counter_16:C|count[6]    ; 0                 ; 0       ;
-;      - counter_16:C|count[5]    ; 0                 ; 0       ;
-;      - counter_16:C|count[4]    ; 0                 ; 0       ;
-;      - counter_16:C|count[3]    ; 0                 ; 0       ;
-;      - counter_16:C|count[2]    ; 0                 ; 0       ;
-;      - counter_16:C|count[1]    ; 0                 ; 0       ;
-;      - counter_16:C|count[0]    ; 0                 ; 0       ;
-;      - counter_16:C|count[11]~0 ; 0                 ; 0       ;
-; KEY[0]                          ;                   ;         ;
-;      - counter_16:C|count[11]~0 ; 1                 ; 0       ;
-; CLOCK_50                        ;                   ;         ;
-;      - tick_50000:tck|CLK_OUT   ; 0                 ; 0       ;
-+---------------------------------+-------------------+---------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                                                       ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; Name                     ; Location           ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50                 ; PIN_AF14           ; 2       ; Clock        ; no     ; --                   ; --               ; --                        ;
-; CLOCK_50                 ; PIN_AF14           ; 16      ; Clock        ; yes    ; Global Clock         ; GCLK6            ; --                        ;
-; KEY[1]                   ; PIN_AA15           ; 17      ; Sync. clear  ; no     ; --                   ; --               ; --                        ;
-; counter_16:C|count[11]~0 ; LABCELL_X40_Y2_N0  ; 16      ; Clock enable ; no     ; --                   ; --               ; --                        ;
-; tick_50000:tck|CLK_OUT   ; FF_X33_Y2_N2       ; 17      ; Clock        ; no     ; --                   ; --               ; --                        ;
-; tick_50000:tck|Equal0~3  ; LABCELL_X31_Y1_N30 ; 8       ; Sync. clear  ; no     ; --                   ; --               ; --                        ;
-+--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals                                                                         ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 16      ; Global Clock         ; GCLK6            ; --                        ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------+
-; Routing Usage Summary                                                 ;
-+---------------------------------------------+-------------------------+
-; Routing Resource Type                       ; Usage                   ;
-+---------------------------------------------+-------------------------+
-; Block interconnects                         ; 160 / 289,320 ( < 1 % ) ;
-; C12 interconnects                           ; 2 / 13,420 ( < 1 % )    ;
-; C2 interconnects                            ; 58 / 119,108 ( < 1 % )  ;
-; C4 interconnects                            ; 63 / 56,300 ( < 1 % )   ;
-; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
-; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
-; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
-; Direct links                                ; 40 / 289,320 ( < 1 % )  ;
-; Global clocks                               ; 1 / 16 ( 6 % )          ;
-; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
-; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
-; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
-; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
-; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
-; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
-; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
-; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
-; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
-; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
-; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
-; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
-; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
-; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
-; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
-; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
-; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
-; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
-; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
-; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
-; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
-; Local interconnects                         ; 85 / 84,580 ( < 1 % )   ;
-; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
-; R14 interconnects                           ; 22 / 12,676 ( < 1 % )   ;
-; R14/C12 interconnect drivers                ; 24 / 20,720 ( < 1 % )   ;
-; R3 interconnects                            ; 67 / 130,992 ( < 1 % )  ;
-; R6 interconnects                            ; 132 / 266,960 ( < 1 % ) ;
-; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
-; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
-+---------------------------------------------+-------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 28    ;
-; Number of I/O Rules Passed       ; 6     ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 22    ;
-+----------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                  ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
-; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
-; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
-; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
-; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Pin/Rules          ; IO_000002    ; IO_000003 ; IO_000001 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000022    ; IO_000021    ; IO_000046    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000047    ; IO_000020    ; IO_000019    ; IO_000018    ; IO_000015    ; IO_000014    ; IO_000013    ; IO_000012    ; IO_000011    ; IO_000010 ; IO_000009 ; IO_000034    ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Total Pass         ; 0            ; 38        ; 38        ; 0            ; 0            ; 38        ; 38        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 38        ; 38        ; 0            ;
-; Total Unchecked    ; 0            ; 0         ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ;
-; Total Inapplicable ; 38           ; 0         ; 0         ; 38           ; 38           ; 0         ; 0         ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 0         ; 0         ; 38           ;
-; Total Fail         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ;
-; HEX0[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; KEY[1]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; KEY[0]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; CLOCK_50           ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                          ;
-+------------------------------------------------------------------+-----------------------------+
-; Option                                                           ; Setting                     ;
-+------------------------------------------------------------------+-----------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
-; Enable INIT_DONE output                                          ; Off                         ;
-; Configuration scheme                                             ; Passive Serial              ;
-; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
-; Enable CvP_CONFDONE pin                                          ; Off                         ;
-; Enable open drain on CRC_ERROR pin                               ; On                          ;
-; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
-; Enable open drain on INIT_DONE pin                               ; On                          ;
-; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
-; Enable open drain on nCEO pin                                    ; On                          ;
-; Enable Partial Reconfiguration pins                              ; Off                         ;
-; Enable input tri-state on active configuration pins in user mode ; Off                         ;
-; Enable internal scrubbing                                        ; Off                         ;
-; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
-; Device initialization clock source                               ; Internal Oscillator         ;
-; Configuration via Protocol                                       ; Off                         ;
-; Configuration Voltage Level                                      ; Auto                        ;
-; Force Configuration Voltage Level                                ; Off                         ;
-; Enable nCEO output                                               ; Off                         ;
-; Data[15..8]                                                      ; Unreserved                  ;
-; Data[7..5]                                                       ; Unreserved                  ;
-; Base pin-out file on sameframe device                            ; Off                         ;
-+------------------------------------------------------------------+-----------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.10 V ;
-; Low Junction Temperature  ; 0 �C   ;
-; High Junction Temperature ; 85 �C  ;
-+---------------------------+--------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary              ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
-
-
-+-----------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details                         ;
-+--------------------------+------------------------+-------------------+
-; Source Register          ; Destination Register   ; Delay Added in ns ;
-+--------------------------+------------------------+-------------------+
-; tick_50000:tck|count[14] ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[13] ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[15] ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[11] ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[9]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[8]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[12] ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[6]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[5]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[4]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[3]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[2]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[1]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[0]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[7]  ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|count[10] ; tick_50000:tck|CLK_OUT ; 0.748             ;
-; tick_50000:tck|CLK_OUT   ; tick_50000:tck|CLK_OUT ; 0.748             ;
-+--------------------------+------------------------+-------------------+
-Note: This table only shows the top 17 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex6"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (184020): Starting Fitter periphery placement operations
-Info (11191): Automatically promoted 1 clock (1 global)
-    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
-Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
-Info (176233): Starting register packing
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
-    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
-Info (332104): Reading SDC File: 'ex6.sdc'
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
-    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
-Info (332111): Found 1 clocks
-    Info (332111):   Period   Clock Name
-    Info (332111): ======== ============
-    Info (332111):   20.000     CLOCK_50
-Info (170189): Fitter placement preparation operations beginning
-Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y11 to location X89_Y22
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-    Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
-Info (11888): Total time spent on timing analysis during the Fitter is 0.14 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 49 warnings
-    Info: Peak virtual memory: 2132 megabytes
-    Info: Processing ended: Sun Dec 11 18:08:29 2016
-    Info: Elapsed time: 00:00:29
-    Info: Total CPU time (on all processors): 00:00:48
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/output_files/ex6.fit.smsg.
-
-
+Fitter report for ex6
+Tue Nov 22 11:43:32 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Routing Usage Summary
+ 24. I/O Rules Summary
+ 25. I/O Rules Details
+ 26. I/O Rules Matrix
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing Summary
+ 30. Estimated Delay Added for Hold Timing Details
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Tue Nov 22 11:43:32 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex6                                             ;
+; Top-level Entity Name           ; ex6                                             ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 99 / 32,070 ( < 1 % )                           ;
+; Total registers                 ; 35                                              ;
+; Total pins                      ; 38 / 457 ( 8 % )                                ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.01        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.5%      ;
+;     Processor 3            ;   0.5%      ;
+;     Processor 4            ;   0.4%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; HEX0[0]  ; Missing drive strength and slew rate ;
+; HEX0[1]  ; Missing drive strength and slew rate ;
+; HEX0[2]  ; Missing drive strength and slew rate ;
+; HEX0[3]  ; Missing drive strength and slew rate ;
+; HEX0[4]  ; Missing drive strength and slew rate ;
+; HEX0[5]  ; Missing drive strength and slew rate ;
+; HEX0[6]  ; Missing drive strength and slew rate ;
+; HEX1[0]  ; Missing drive strength and slew rate ;
+; HEX1[1]  ; Missing drive strength and slew rate ;
+; HEX1[2]  ; Missing drive strength and slew rate ;
+; HEX1[3]  ; Missing drive strength and slew rate ;
+; HEX1[4]  ; Missing drive strength and slew rate ;
+; HEX1[5]  ; Missing drive strength and slew rate ;
+; HEX1[6]  ; Missing drive strength and slew rate ;
+; HEX2[0]  ; Missing drive strength and slew rate ;
+; HEX2[1]  ; Missing drive strength and slew rate ;
+; HEX2[2]  ; Missing drive strength and slew rate ;
+; HEX2[3]  ; Missing drive strength and slew rate ;
+; HEX2[4]  ; Missing drive strength and slew rate ;
+; HEX2[5]  ; Missing drive strength and slew rate ;
+; HEX2[6]  ; Missing drive strength and slew rate ;
+; HEX3[0]  ; Missing drive strength and slew rate ;
+; HEX3[1]  ; Missing drive strength and slew rate ;
+; HEX3[2]  ; Missing drive strength and slew rate ;
+; HEX3[3]  ; Missing drive strength and slew rate ;
+; HEX3[4]  ; Missing drive strength and slew rate ;
+; HEX3[5]  ; Missing drive strength and slew rate ;
+; HEX3[6]  ; Missing drive strength and slew rate ;
+; HEX4[0]  ; Missing drive strength and slew rate ;
+; HEX4[1]  ; Missing drive strength and slew rate ;
+; HEX4[2]  ; Missing drive strength and slew rate ;
+; HEX4[3]  ; Missing drive strength and slew rate ;
+; HEX4[4]  ; Missing drive strength and slew rate ;
+; HEX4[5]  ; Missing drive strength and slew rate ;
+; HEX4[6]  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                      ;
++-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+
+; Node                    ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                  ; Destination Port ; Destination Port Name ;
++-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0   ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                   ;                  ;                       ;
+; tick_50000:tck|count[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:tck|count[1]~DUPLICATE ;                  ;                       ;
+; tick_50000:tck|count[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:tck|count[5]~DUPLICATE ;                  ;                       ;
++-------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                        ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex6            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 )         ; 0.00 % ( 0 / 298 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 298 ) ; 0.00 % ( 0 / 298 )         ; 0.00 % ( 0 / 298 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 298 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/New folder/ex6/output_files/ex6.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 99 / 32,070        ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 99                 ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 100 / 32,070       ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 16                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 83                 ;       ;
+;         [c] ALMs used for registers                         ; 1                  ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 1 / 32,070         ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 17 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 17                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 188                ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 9                  ;       ;
+;     -- 5 input functions                                    ; 3                  ;       ;
+;     -- 4 input functions                                    ; 124                ;       ;
+;     -- <=3 input functions                                  ; 52                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;
+; Dedicated logic registers                                   ; 35                 ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 33 / 64,140        ; < 1 % ;
+;         -- Secondary logic registers                        ; 2 / 64,140         ; < 1 % ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 33                 ;       ;
+;         -- Routing optimization registers                   ; 2                  ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 38 / 457           ; 8 %   ;
+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 0.9% / 0.9% / 1.0% ;       ;
+; Maximum fan-out                                             ; 18                 ;       ;
+; Highest non-global fan-out                                  ; 17                 ;       ;
+; Total fan-out                                               ; 852                ;       ;
+; Average fan-out                                             ; 2.83               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                          ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 99 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 99                    ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 100 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 16                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 83                    ; 0                              ;
+;         [c] ALMs used for registers                         ; 1                     ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 1 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Difficulty packing design                                   ; Low                   ; Low                            ;
+;                                                             ;                       ;                                ;
+; Total LABs:  partially or completely used                   ; 17 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 17                    ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Combinational ALUT usage for logic                          ; 188                   ; 0                              ;
+;     -- 7 input functions                                    ; 0                     ; 0                              ;
+;     -- 6 input functions                                    ; 9                     ; 0                              ;
+;     -- 5 input functions                                    ; 3                     ; 0                              ;
+;     -- 4 input functions                                    ; 124                   ; 0                              ;
+;     -- <=3 input functions                                  ; 52                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;
+; Memory ALUT usage                                           ; 0                     ; 0                              ;
+;     -- 64-address deep                                      ; 0                     ; 0                              ;
+;     -- 32-address deep                                      ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Dedicated logic registers                                   ; 0                     ; 0                              ;
+;     -- By type:                                             ;                       ;                                ;
+;         -- Primary logic registers                          ; 33 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 2 / 64140 ( < 1 % )   ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                       ;                                ;
+;         -- Design implementation registers                  ; 33                    ; 0                              ;
+;         -- Routing optimization registers                   ; 2                     ; 0                              ;
+;                                                             ;                       ;                                ;
+;                                                             ;                       ;                                ;
+; Virtual pins                                                ; 0                     ; 0                              ;
+; I/O pins                                                    ; 38                    ; 0                              ;
+; I/O registers                                               ; 0                     ; 0                              ;
+; Total block memory bits                                     ; 0                     ; 0                              ;
+; Total block memory implementation bits                      ; 0                     ; 0                              ;
+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
+;                                                             ;                       ;                                ;
+; Connections                                                 ;                       ;                                ;
+;     -- Input Connections                                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections                         ; 0                     ; 0                              ;
+;     -- Output Connections                                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections                        ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Internal Connections                                        ;                       ;                                ;
+;     -- Total Connections                                    ; 852                   ; 0                              ;
+;     -- Registered Connections                               ; 139                   ; 0                              ;
+;                                                             ;                       ;                                ;
+; External Connections                                        ;                       ;                                ;
+;     -- Top                                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Partition Interface                                         ;                       ;                                ;
+;     -- Input Ports                                          ; 3                     ; 0                              ;
+;     -- Output Ports                                         ; 35                    ; 0                              ;
+;     -- Bidir Ports                                          ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Registered Ports                                            ;                       ;                                ;
+;     -- Registered Input Ports                               ; 0                     ; 0                              ;
+;     -- Registered Output Ports                              ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Port Connectivity                                           ;                       ;                                ;
+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 19                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 17                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 3 / 48 ( 6 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 0 / 80 ( 0 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 27 / 32 ( 84 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 8 / 16 ( 50 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                             ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
+; |ex6                       ; 98.5 (0.5)           ; 99.5 (0.5)                       ; 1.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 188 (1)             ; 35 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 38   ; 0            ; |ex6                           ; ex6         ; work         ;
+;    |bin2bcd_16:B|          ; 57.0 (0.0)           ; 57.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 106 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B              ; bin2bcd_16  ; work         ;
+;       |add3_ge5:A1|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A1  ; add3_ge5    ; work         ;
+;       |add3_ge5:A10|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5    ; work         ;
+;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5    ; work         ;
+;       |add3_ge5:A12|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5    ; work         ;
+;       |add3_ge5:A13|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5    ; work         ;
+;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5    ; work         ;
+;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5    ; work         ;
+;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5    ; work         ;
+;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5    ; work         ;
+;       |add3_ge5:A18|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5    ; work         ;
+;       |add3_ge5:A19|       ; 1.5 (1.5)            ; 1.5 (1.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5    ; work         ;
+;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A2  ; add3_ge5    ; work         ;
+;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5    ; work         ;
+;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5    ; work         ;
+;       |add3_ge5:A22|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5    ; work         ;
+;       |add3_ge5:A23|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5    ; work         ;
+;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5    ; work         ;
+;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5    ; work         ;
+;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5    ; work         ;
+;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5    ; work         ;
+;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5    ; work         ;
+;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5    ; work         ;
+;       |add3_ge5:A3|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A3  ; add3_ge5    ; work         ;
+;       |add3_ge5:A4|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A4  ; add3_ge5    ; work         ;
+;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A5  ; add3_ge5    ; work         ;
+;       |add3_ge5:A6|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A6  ; add3_ge5    ; work         ;
+;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A7  ; add3_ge5    ; work         ;
+;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A8  ; add3_ge5    ; work         ;
+;       |add3_ge5:A9|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A9  ; add3_ge5    ; work         ;
+;    |counter_16:C|          ; 8.5 (8.5)            ; 8.5 (8.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 16 (16)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|counter_16:C              ; counter_16  ; work         ;
+;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG0          ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG1          ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG2          ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG3          ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG4|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG4          ; hex_to_7seg ; work         ;
+;    |tick_50000:tck|        ; 15.0 (15.0)          ; 16.0 (16.0)                      ; 1.0 (1.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 29 (29)             ; 19 (19)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex6|tick_50000:tck            ; tick_50000  ; work         ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; KEY[1]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; KEY[0]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++---------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                ;
++---------------------------------+-------------------+---------+
+; Source Pin / Fanout             ; Pad To Core Index ; Setting ;
++---------------------------------+-------------------+---------+
+; KEY[1]                          ;                   ;         ;
+;      - counter_16:C|count[14]   ; 0                 ; 0       ;
+;      - counter_16:C|count[15]   ; 0                 ; 0       ;
+;      - counter_16:C|count[0]    ; 0                 ; 0       ;
+;      - counter_16:C|count[1]    ; 0                 ; 0       ;
+;      - counter_16:C|count[2]    ; 0                 ; 0       ;
+;      - counter_16:C|count[3]    ; 0                 ; 0       ;
+;      - counter_16:C|count[4]    ; 0                 ; 0       ;
+;      - counter_16:C|count[5]    ; 0                 ; 0       ;
+;      - counter_16:C|count[6]    ; 0                 ; 0       ;
+;      - counter_16:C|count[7]    ; 0                 ; 0       ;
+;      - counter_16:C|count[8]    ; 0                 ; 0       ;
+;      - counter_16:C|count[9]    ; 0                 ; 0       ;
+;      - counter_16:C|count[10]   ; 0                 ; 0       ;
+;      - counter_16:C|count[11]   ; 0                 ; 0       ;
+;      - counter_16:C|count[12]   ; 0                 ; 0       ;
+;      - counter_16:C|count[13]   ; 0                 ; 0       ;
+;      - counter_16:C|count[14]~0 ; 0                 ; 0       ;
+; KEY[0]                          ;                   ;         ;
+;      - counter_16:C|count[14]~0 ; 0                 ; 0       ;
+; CLOCK_50                        ;                   ;         ;
+;      - tick_50000:tck|CLK_OUT   ; 0                 ; 0       ;
++---------------------------------+-------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                       ;
++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name                     ; Location           ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                 ; PIN_AF14           ; 2       ; Clock        ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                 ; PIN_AF14           ; 18      ; Clock        ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; KEY[1]                   ; PIN_AA15           ; 17      ; Sync. clear  ; no     ; --                   ; --               ; --                        ;
+; counter_16:C|count[14]~0 ; LABCELL_X46_Y1_N30 ; 16      ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; tick_50000:tck|CLK_OUT   ; FF_X33_Y1_N20      ; 17      ; Clock        ; no     ; --                   ; --               ; --                        ;
+; tick_50000:tck|Equal0~3  ; LABCELL_X33_Y1_N48 ; 8       ; Sync. clear  ; no     ; --                   ; --               ; --                        ;
++--------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 18      ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 179 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 5 / 13,420 ( < 1 % )    ;
+; C2 interconnects                            ; 61 / 119,108 ( < 1 % )  ;
+; C4 interconnects                            ; 56 / 56,300 ( < 1 % )   ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 45 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 1 / 16 ( 6 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 81 / 84,580 ( < 1 % )   ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 7 / 12,676 ( < 1 % )    ;
+; R14/C12 interconnect drivers                ; 12 / 20,720 ( < 1 % )   ;
+; R3 interconnects                            ; 80 / 130,992 ( < 1 % )  ;
+; R6 interconnects                            ; 160 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                  ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 38        ; 0            ; 38        ; 0            ; 0            ; 38        ; 38        ; 0            ; 38        ; 38        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 38           ; 0         ; 38           ; 38           ; 0         ; 0         ; 38           ; 0         ; 0         ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ; 38           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                         ;
++--------------------------+------------------------+-------------------+
+; Source Register          ; Destination Register   ; Delay Added in ns ;
++--------------------------+------------------------+-------------------+
+; tick_50000:tck|count[14] ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[13] ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[12] ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[11] ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[10] ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[9]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[8]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[15] ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[5]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[4]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[3]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[2]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[1]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[0]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[7]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|count[6]  ; tick_50000:tck|CLK_OUT ; 0.948             ;
+; tick_50000:tck|CLK_OUT   ; tick_50000:tck|CLK_OUT ; 0.948             ;
++--------------------------+------------------------+-------------------+
+Note: This table only shows the top 17 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex6"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
+Info (332104): Reading SDC File: 'ex6.sdc'
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 1 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file C:/New folder/ex6/output_files/ex6.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 48 warnings
+    Info: Peak virtual memory: 2591 megabytes
+    Info: Processing ended: Tue Nov 22 11:43:33 2016
+    Info: Elapsed time: 00:00:30
+    Info: Total CPU time (on all processors): 00:00:53
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/New folder/ex6/output_files/ex6.fit.smsg.
+
+
diff --git a/part_2/ex6/output_files/ex6.fit.smsg b/part_2/ex6/output_files/ex6.fit.smsg
index 9302919..43eead5 100755
--- a/part_2/ex6/output_files/ex6.fit.smsg
+++ b/part_2/ex6/output_files/ex6.fit.smsg
@@ -1,6 +1,6 @@
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
-Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex6/output_files/ex6.fit.summary b/part_2/ex6/output_files/ex6.fit.summary
index 54af65e..bc14ca7 100755
--- a/part_2/ex6/output_files/ex6.fit.summary
+++ b/part_2/ex6/output_files/ex6.fit.summary
@@ -1,20 +1,20 @@
-Fitter Status : Successful - Sun Dec 11 18:08:29 2016
-Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Revision Name : ex6
-Top-level Entity Name : ex6
-Family : Cyclone V
-Device : 5CSEMA5F31C6
-Timing Models : Final
-Logic utilization (in ALMs) : 99 / 32,070 ( < 1 % )
-Total registers : 33
-Total pins : 38 / 457 ( 8 % )
-Total virtual pins : 0
-Total block memory bits : 0 / 4,065,280 ( 0 % )
-Total RAM Blocks : 0 / 397 ( 0 % )
-Total DSP Blocks : 0 / 87 ( 0 % )
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0 / 6 ( 0 % )
-Total DLLs : 0 / 4 ( 0 % )
+Fitter Status : Successful - Tue Nov 22 11:43:32 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex6
+Top-level Entity Name : ex6
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 99 / 32,070 ( < 1 % )
+Total registers : 35
+Total pins : 38 / 457 ( 8 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_2/ex6/output_files/ex6.flow.rpt b/part_2/ex6/output_files/ex6.flow.rpt
index 5369166..1e44f79 100755
--- a/part_2/ex6/output_files/ex6.flow.rpt
+++ b/part_2/ex6/output_files/ex6.flow.rpt
@@ -1,128 +1,128 @@
-Flow report for ex6
-Sun Dec 11 18:08:41 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Flow Summary                                                                  ;
-+---------------------------------+---------------------------------------------+
-; Flow Status                     ; Successful - Sun Dec 11 18:08:36 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex6                                         ;
-; Top-level Entity Name           ; ex6                                         ;
-; Family                          ; Cyclone V                                   ;
-; Device                          ; 5CSEMA5F31C6                                ;
-; Timing Models                   ; Final                                       ;
-; Logic utilization (in ALMs)     ; 99 / 32,070 ( < 1 % )                       ;
-; Total registers                 ; 33                                          ;
-; Total pins                      ; 38 / 457 ( 8 % )                            ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                       ;
-; Total DSP Blocks                ; 0 / 87 ( 0 % )                              ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0 / 6 ( 0 % )                               ;
-; Total DLLs                      ; 0 / 4 ( 0 % )                               ;
-+---------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 12/11/2016 18:07:50 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; ex6                 ;
-+-------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                        ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID               ; 158515234070422.148147967004252        ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --          ; --         ;
-; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                    ; --            ; --          ; --         ;
-; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW  ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --         ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 1028 MB             ; 00:00:24                           ;
-; Fitter                    ; 00:00:29     ; 1.0                     ; 2132 MB             ; 00:00:48                           ;
-; Assembler                 ; 00:00:06     ; 1.0                     ; 976 MB              ; 00:00:06                           ;
-; TimeQuest Timing Analyzer ; 00:00:04     ; 1.1                     ; 1214 MB             ; 00:00:05                           ;
-; Total                     ; 00:00:49     ; --                      ; --                  ; 00:01:23                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                         ;
-+---------------------------+------------------+------------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
-+---------------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis      ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; Fitter                    ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; Assembler                 ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; TimeQuest Timing Analyzer ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-+---------------------------+------------------+------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6
-quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6
-quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6
-quartus_sta ex6 -c ex6
-
-
-
+Flow report for ex6
+Tue Nov 22 11:43:46 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Tue Nov 22 11:43:40 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex6                                             ;
+; Top-level Entity Name           ; ex6                                             ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 99 / 32,070 ( < 1 % )                           ;
+; Total registers                 ; 35                                              ;
+; Total pins                      ; 38 / 457 ( 8 % )                                ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 11/22/2016 11:42:53 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex6                 ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564170200.147981497204968       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 897 MB              ; 00:00:21                           ;
+; Fitter                    ; 00:00:29     ; 1.0                     ; 2591 MB             ; 00:00:53                           ;
+; Assembler                 ; 00:00:06     ; 1.0                     ; 892 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:05     ; 1.1                     ; 1209 MB             ; 00:00:05                           ;
+; Total                     ; 00:00:50     ; --                      ; --                  ; 00:01:25                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6
+quartus_fit --read_settings_files=off --write_settings_files=off ex6 -c ex6
+quartus_asm --read_settings_files=off --write_settings_files=off ex6 -c ex6
+quartus_sta ex6 -c ex6
+
+
+
diff --git a/part_2/ex6/output_files/ex6.jdi b/part_2/ex6/output_files/ex6.jdi
index e913aee..30e9a8a 100755
--- a/part_2/ex6/output_files/ex6.jdi
+++ b/part_2/ex6/output_files/ex6.jdi
@@ -1,8 +1,8 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="486dd37dbb5b652de768"/>
-  </project>
-  <file_info>
-    <file device="5CSEMA5F31C6" path="ex6.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="baef6963dc4d960fc697"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex6.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_2/ex6/output_files/ex6.map.rpt b/part_2/ex6/output_files/ex6.map.rpt
index 6d7a2e4..a381799 100755
--- a/part_2/ex6/output_files/ex6.map.rpt
+++ b/part_2/ex6/output_files/ex6.map.rpt
@@ -1,430 +1,438 @@
-Analysis & Synthesis report for ex6
-Sun Dec 11 18:08:00 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. General Register Statistics
-  9. Inverted Register Statistics
- 10. Multiplexer Restructuring Statistics (Restructuring Performed)
- 11. Parameter Settings for User Entity Instance: tick_50000:tck
- 12. Parameter Settings for User Entity Instance: counter_16:C
- 13. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18"
- 14. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9"
- 15. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3"
- 16. Post-Synthesis Netlist Statistics for Top Partition
- 17. Elapsed Time Per Partition
- 18. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                  ;
-+---------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status     ; Successful - Sun Dec 11 18:08:00 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex6                                         ;
-; Top-level Entity Name           ; ex6                                         ;
-; Family                          ; Cyclone V                                   ;
-; Logic utilization (in ALMs)     ; N/A                                         ;
-; Total registers                 ; 33                                          ;
-; Total pins                      ; 38                                          ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0                                           ;
-; Total DSP Blocks                ; 0                                           ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0                                           ;
-; Total DLLs                      ; 0                                           ;
-+---------------------------------+---------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                             ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                          ; Setting            ; Default Value      ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
-; Top-level entity name                                                           ; ex6                ; ex6                ;
-; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
-; Use smart compilation                                                           ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
-; Enable compact report table                                                     ; Off                ; Off                ;
-; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
-; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
-; Preserve fewer node names                                                       ; On                 ; On                 ;
-; OpenCore Plus hardware evaluation                                               ; Enable             ; Enable             ;
-; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                                        ; Auto               ; Auto               ;
-; Safe State Machine                                                              ; Off                ; Off                ;
-; Extract Verilog State Machines                                                  ; On                 ; On                 ;
-; Extract VHDL State Machines                                                     ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
-; Parallel Synthesis                                                              ; On                 ; On                 ;
-; DSP Block Balancing                                                             ; Auto               ; Auto               ;
-; NOT Gate Push-Back                                                              ; On                 ; On                 ;
-; Power-Up Don't Care                                                             ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
-; Remove Duplicate Registers                                                      ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
-; Optimization Technique                                                          ; Balanced           ; Balanced           ;
-; Carry Chain Length                                                              ; 70                 ; 70                 ;
-; Auto Carry Chains                                                               ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
-; Auto ROM Replacement                                                            ; On                 ; On                 ;
-; Auto RAM Replacement                                                            ; On                 ; On                 ;
-; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
-; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
-; Strict RAM Replacement                                                          ; Off                ; Off                ;
-; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
-; Auto Resource Sharing                                                           ; Off                ; Off                ;
-; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
-; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
-; Report Parameter Settings                                                       ; On                 ; On                 ;
-; Report Source Assignments                                                       ; On                 ; On                 ;
-; Report Connectivity Checks                                                      ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
-; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
-; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
-; HDL message level                                                               ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
-; Clock MUX Protection                                                            ; On                 ; On                 ;
-; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
-; Block Design Naming                                                             ; Auto               ; Auto               ;
-; SDC constraint protection                                                       ; Off                ; Off                ;
-; Synthesis Effort                                                                ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
-; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
-; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
-; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
-;     Processors 3-4         ;   0.0%      ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                              ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                                ; Library ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/hex_to_7seg.v ;         ;
-; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v  ;         ;
-; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/add3_ge5.v    ;         ;
-; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/counter_16.v  ;         ;
-; ex6.v                            ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v                       ;         ;
-; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/tick_50000.v  ;         ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-
-
-+----------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary                          ;
-+---------------------------------------------+------------------------+
-; Resource                                    ; Usage                  ;
-+---------------------------------------------+------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 98                     ;
-;                                             ;                        ;
-; Combinational ALUT usage for logic          ; 187                    ;
-;     -- 7 input functions                    ; 0                      ;
-;     -- 6 input functions                    ; 9                      ;
-;     -- 5 input functions                    ; 3                      ;
-;     -- 4 input functions                    ; 124                    ;
-;     -- <=3 input functions                  ; 51                     ;
-;                                             ;                        ;
-; Dedicated logic registers                   ; 33                     ;
-;                                             ;                        ;
-; I/O pins                                    ; 38                     ;
-;                                             ;                        ;
-; Total DSP Blocks                            ; 0                      ;
-;                                             ;                        ;
-; Maximum fan-out node                        ; tick_50000:tck|CLK_OUT ;
-; Maximum fan-out                             ; 17                     ;
-; Total fan-out                               ; 846                    ;
-; Average fan-out                             ; 2.86                   ;
-+---------------------------------------------+------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                               ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
-; |ex6                       ; 187 (0)             ; 33 (0)                    ; 0                 ; 0          ; 38   ; 0            ; |ex6                           ; ex6         ; work         ;
-;    |bin2bcd_16:B|          ; 106 (0)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A10|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A1|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:C|          ; 17 (17)             ; 16 (16)                   ; 0                 ; 0          ; 0    ; 0            ; |ex6|counter_16:C              ; counter_16  ; work         ;
-;    |hex_to_7seg:SEG0|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG0          ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG1          ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG2          ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG3          ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG4          ; hex_to_7seg ; work         ;
-;    |tick_50000:tck|        ; 29 (29)             ; 17 (17)                   ; 0                 ; 0          ; 0    ; 0            ; |ex6|tick_50000:tck            ; tick_50000  ; work         ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 33    ;
-; Number of registers using Synchronous Clear  ; 24    ;
-; Number of registers using Synchronous Load   ; 0     ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 16    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------+
-; Inverted Register Statistics                     ;
-+----------------------------------------+---------+
-; Inverted Register                      ; Fan out ;
-+----------------------------------------+---------+
-; tick_50000:tck|count[8]                ; 3       ;
-; tick_50000:tck|count[0]                ; 2       ;
-; tick_50000:tck|count[1]                ; 2       ;
-; tick_50000:tck|count[2]                ; 2       ;
-; tick_50000:tck|count[5]                ; 2       ;
-; tick_50000:tck|count[7]                ; 2       ;
-; tick_50000:tck|count[13]               ; 2       ;
-; tick_50000:tck|count[14]               ; 2       ;
-; Total number of inverted registers = 8 ;         ;
-+----------------------------------------+---------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
-; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex6|counter_16:C|count[11] ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
-
-
-+-------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:tck ;
-+----------------+-------+------------------------------------+
-; Parameter Name ; Value ; Type                               ;
-+----------------+-------+------------------------------------+
-; NBIT           ; 16    ; Signed Integer                     ;
-+----------------+-------+------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------+
-; Parameter Settings for User Entity Instance: counter_16:C ;
-+----------------+-------+----------------------------------+
-; Parameter Name ; Value ; Type                             ;
-+----------------+-------+----------------------------------+
-; BIT_SZ         ; 16    ; Signed Integer                   ;
-+----------------+-------+----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18" ;
-+------+-------+----------+-----------------------------+
-; Port ; Type  ; Severity ; Details                     ;
-+------+-------+----------+-----------------------------+
-; w[3] ; Input ; Info     ; Stuck at GND                ;
-+------+-------+----------+-----------------------------+
-
-
-+------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9" ;
-+------+-------+----------+----------------------------+
-; Port ; Type  ; Severity ; Details                    ;
-+------+-------+----------+----------------------------+
-; w[3] ; Input ; Info     ; Stuck at GND               ;
-+------+-------+----------+----------------------------+
-
-
-+------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3" ;
-+------+-------+----------+----------------------------+
-; Port ; Type  ; Severity ; Details                    ;
-+------+-------+----------+----------------------------+
-; w[3] ; Input ; Info     ; Stuck at GND               ;
-+------+-------+----------+----------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type                  ; Count                       ;
-+-----------------------+-----------------------------+
-; arriav_ff             ; 33                          ;
-;     ENA SCLR          ; 16                          ;
-;     SCLR              ; 8                           ;
-;     plain             ; 9                           ;
-; arriav_lcell_comb     ; 204                         ;
-;     arith             ; 32                          ;
-;         1 data inputs ; 32                          ;
-;     normal            ; 172                         ;
-;         1 data inputs ; 25                          ;
-;         2 data inputs ; 1                           ;
-;         3 data inputs ; 10                          ;
-;         4 data inputs ; 124                         ;
-;         5 data inputs ; 3                           ;
-;         6 data inputs ; 9                           ;
-; boundary_port         ; 38                          ;
-;                       ;                             ;
-; Max LUT depth         ; 13.00                       ;
-; Average LUT depth     ; 8.75                        ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:00     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 18:07:50 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
-    Info (12023): Found entity 1: hex_to_7seg File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
-    Info (12023): Found entity 1: bin2bcd_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
-    Info (12023): Found entity 1: add3_ge5 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/add3_ge5.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
-    Info (12023): Found entity 1: counter_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/counter_16.v Line: 3
-Info (12021): Found 1 design units, including 1 entities, in source file ex6.v
-    Info (12023): Found entity 1: ex6 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
-    Info (12023): Found entity 1: tick_50000 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/tick_50000.v Line: 1
-Info (12127): Elaborating entity "ex6" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:tck" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 11
-Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:C" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 13
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:B" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 15
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:B|add3_ge5:A1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex6/ex6.v Line: 17
-Info (286030): Timing-Driven Synthesis is running
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Info (21057): Implemented 225 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 3 input pins
-    Info (21059): Implemented 35 output pins
-    Info (21061): Implemented 187 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 1071 megabytes
-    Info: Processing ended: Sun Dec 11 18:08:00 2016
-    Info: Elapsed time: 00:00:10
-    Info: Total CPU time (on all processors): 00:00:25
-
-
+Analysis & Synthesis report for ex6
+Tue Nov 22 11:43:02 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Inverted Register Statistics
+ 10. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 11. Parameter Settings for User Entity Instance: tick_50000:tck
+ 12. Parameter Settings for User Entity Instance: counter_16:C
+ 13. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18"
+ 14. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9"
+ 15. Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3"
+ 16. Post-Synthesis Netlist Statistics for Top Partition
+ 17. Elapsed Time Per Partition
+ 18. Analysis & Synthesis Messages
+ 19. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Tue Nov 22 11:43:02 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex6                                             ;
+; Top-level Entity Name           ; ex6                                             ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 33                                              ;
+; Total pins                      ; 38                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0                                               ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex6                ; ex6                ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ; Library ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/hex_to_7seg.v ;         ;
+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/bin2bcd_16.v  ;         ;
+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/add3_ge5.v    ;         ;
+; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/counter_16.v  ;         ;
+; ex6.v                            ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/ex6.v                       ;         ;
+; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex6/verilog_files/tick_50000.v  ;         ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
+
+
++----------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                          ;
++---------------------------------------------+------------------------+
+; Resource                                    ; Usage                  ;
++---------------------------------------------+------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 98                     ;
+;                                             ;                        ;
+; Combinational ALUT usage for logic          ; 187                    ;
+;     -- 7 input functions                    ; 0                      ;
+;     -- 6 input functions                    ; 9                      ;
+;     -- 5 input functions                    ; 3                      ;
+;     -- 4 input functions                    ; 124                    ;
+;     -- <=3 input functions                  ; 51                     ;
+;                                             ;                        ;
+; Dedicated logic registers                   ; 33                     ;
+;                                             ;                        ;
+; I/O pins                                    ; 38                     ;
+;                                             ;                        ;
+; Total DSP Blocks                            ; 0                      ;
+;                                             ;                        ;
+; Maximum fan-out node                        ; tick_50000:tck|CLK_OUT ;
+; Maximum fan-out                             ; 17                     ;
+; Total fan-out                               ; 846                    ;
+; Average fan-out                             ; 2.86                   ;
++---------------------------------------------+------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name            ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
+; |ex6                       ; 187 (0)           ; 33 (0)       ; 0                 ; 0          ; 38   ; 0            ; |ex6                           ; ex6         ; work         ;
+;    |bin2bcd_16:B|          ; 106 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B              ; bin2bcd_16  ; work         ;
+;       |add3_ge5:A10|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A10 ; add3_ge5    ; work         ;
+;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A11 ; add3_ge5    ; work         ;
+;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A12 ; add3_ge5    ; work         ;
+;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A13 ; add3_ge5    ; work         ;
+;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A14 ; add3_ge5    ; work         ;
+;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A15 ; add3_ge5    ; work         ;
+;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A16 ; add3_ge5    ; work         ;
+;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A17 ; add3_ge5    ; work         ;
+;       |add3_ge5:A18|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A18 ; add3_ge5    ; work         ;
+;       |add3_ge5:A19|       ; 3 (3)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A19 ; add3_ge5    ; work         ;
+;       |add3_ge5:A1|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A1  ; add3_ge5    ; work         ;
+;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A20 ; add3_ge5    ; work         ;
+;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A21 ; add3_ge5    ; work         ;
+;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A22 ; add3_ge5    ; work         ;
+;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A23 ; add3_ge5    ; work         ;
+;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A24 ; add3_ge5    ; work         ;
+;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A25 ; add3_ge5    ; work         ;
+;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A26 ; add3_ge5    ; work         ;
+;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A27 ; add3_ge5    ; work         ;
+;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A28 ; add3_ge5    ; work         ;
+;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A29 ; add3_ge5    ; work         ;
+;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A2  ; add3_ge5    ; work         ;
+;       |add3_ge5:A3|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A3  ; add3_ge5    ; work         ;
+;       |add3_ge5:A4|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A4  ; add3_ge5    ; work         ;
+;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A5  ; add3_ge5    ; work         ;
+;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A6  ; add3_ge5    ; work         ;
+;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A7  ; add3_ge5    ; work         ;
+;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A8  ; add3_ge5    ; work         ;
+;       |add3_ge5:A9|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|bin2bcd_16:B|add3_ge5:A9  ; add3_ge5    ; work         ;
+;    |counter_16:C|          ; 17 (17)           ; 16 (16)      ; 0                 ; 0          ; 0    ; 0            ; |ex6|counter_16:C              ; counter_16  ; work         ;
+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG0          ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG1          ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG2          ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG3          ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG4|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex6|hex_to_7seg:SEG4          ; hex_to_7seg ; work         ;
+;    |tick_50000:tck|        ; 29 (29)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex6|tick_50000:tck            ; tick_50000  ; work         ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 33    ;
+; Number of registers using Synchronous Clear  ; 24    ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 16    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; tick_50000:tck|count[8]                ; 3       ;
+; tick_50000:tck|count[0]                ; 2       ;
+; tick_50000:tck|count[1]                ; 2       ;
+; tick_50000:tck|count[2]                ; 2       ;
+; tick_50000:tck|count[5]                ; 2       ;
+; tick_50000:tck|count[7]                ; 2       ;
+; tick_50000:tck|count[13]               ; 2       ;
+; tick_50000:tck|count[14]               ; 2       ;
+; Total number of inverted registers = 8 ;         ;
++----------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex6|counter_16:C|count[14] ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+
+
++-------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_50000:tck ;
++----------------+-------+------------------------------------+
+; Parameter Name ; Value ; Type                               ;
++----------------+-------+------------------------------------+
+; NBIT           ; 16    ; Signed Integer                     ;
++----------------+-------+------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------+
+; Parameter Settings for User Entity Instance: counter_16:C ;
++----------------+-------+----------------------------------+
+; Parameter Name ; Value ; Type                             ;
++----------------+-------+----------------------------------+
+; BIT_SZ         ; 16    ; Signed Integer                   ;
++----------------+-------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A18" ;
++------+-------+----------+-----------------------------+
+; Port ; Type  ; Severity ; Details                     ;
++------+-------+----------+-----------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                ;
++------+-------+----------+-----------------------------+
+
+
++------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A9" ;
++------+-------+----------+----------------------------+
+; Port ; Type  ; Severity ; Details                    ;
++------+-------+----------+----------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND               ;
++------+-------+----------+----------------------------+
+
+
++------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:B|add3_ge5:A3" ;
++------+-------+----------+----------------------------+
+; Port ; Type  ; Severity ; Details                    ;
++------+-------+----------+----------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND               ;
++------+-------+----------+----------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 33                          ;
+;     ENA SCLR          ; 16                          ;
+;     SCLR              ; 8                           ;
+;     plain             ; 9                           ;
+; arriav_lcell_comb     ; 204                         ;
+;     arith             ; 32                          ;
+;         1 data inputs ; 32                          ;
+;     normal            ; 172                         ;
+;         1 data inputs ; 25                          ;
+;         2 data inputs ; 1                           ;
+;         3 data inputs ; 10                          ;
+;         4 data inputs ; 124                         ;
+;         5 data inputs ; 3                           ;
+;         6 data inputs ; 9                           ;
+; boundary_port         ; 38                          ;
+;                       ;                             ;
+; Max LUT depth         ; 13.00                       ;
+; Average LUT depth     ; 8.75                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Tue Nov 22 11:42:52 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex6 -c ex6
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex6/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex6/verilog_files/add3_ge5.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
+    Info (12023): Found entity 1: counter_16 File: C:/New folder/ex6/verilog_files/counter_16.v Line: 3
+Info (12021): Found 1 design units, including 1 entities, in source file ex6.v
+    Info (12023): Found entity 1: ex6 File: C:/New folder/ex6/ex6.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
+    Info (12023): Found entity 1: tick_50000 File: C:/New folder/ex6/verilog_files/tick_50000.v Line: 1
+Info (12127): Elaborating entity "ex6" for the top level hierarchy
+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:tck" File: C:/New folder/ex6/ex6.v Line: 11
+Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:C" File: C:/New folder/ex6/ex6.v Line: 13
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:B" File: C:/New folder/ex6/ex6.v Line: 15
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:B|add3_ge5:A1" File: C:/New folder/ex6/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex6/ex6.v Line: 17
+Info (286030): Timing-Driven Synthesis is running
+Info (144001): Generated suppressed messages file C:/New folder/ex6/output_files/ex6.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 225 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 3 input pins
+    Info (21059): Implemented 35 output pins
+    Info (21061): Implemented 187 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 897 megabytes
+    Info: Processing ended: Tue Nov 22 11:43:02 2016
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:21
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in C:/New folder/ex6/output_files/ex6.map.smsg.
+
+
diff --git a/part_2/ex6/output_files/ex6.map.summary b/part_2/ex6/output_files/ex6.map.summary
index 7cf513f..c25655f 100755
--- a/part_2/ex6/output_files/ex6.map.summary
+++ b/part_2/ex6/output_files/ex6.map.summary
@@ -1,17 +1,17 @@
-Analysis & Synthesis Status : Successful - Sun Dec 11 18:08:00 2016
-Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Revision Name : ex6
-Top-level Entity Name : ex6
-Family : Cyclone V
-Logic utilization (in ALMs) : N/A
-Total registers : 33
-Total pins : 38
-Total virtual pins : 0
-Total block memory bits : 0
-Total DSP Blocks : 0
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0
-Total DLLs : 0
+Analysis & Synthesis Status : Successful - Tue Nov 22 11:43:02 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex6
+Top-level Entity Name : ex6
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 33
+Total pins : 38
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_2/ex6/output_files/ex6.pin b/part_2/ex6/output_files/ex6.pin
index 119ca1d..c13fc33 100755
--- a/part_2/ex6/output_files/ex6.pin
+++ b/part_2/ex6/output_files/ex6.pin
@@ -1,977 +1,976 @@
- -- Copyright (C) 2016  Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Intel Program License 
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel MegaCore Function License Agreement, or other 
- -- applicable license agreement, including, without limitation, 
- -- that your use is for the sole purpose of programming logic 
- -- devices manufactured by Intel and sold by Intel or its 
- -- authorized distributors.  Please refer to the applicable 
- -- agreement for further details.
- -- 
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --                  Bank 3A:       2.5V
- --                  Bank 3B:       3.3V
- --                  Bank 4A:       3.3V
- --                  Bank 5A:       3.3V
- --                  Bank 5B:       3.3V
- --                  Bank 6B:       2.5V
- --                  Bank 6A:  2.5V
- --                  Bank 7A:  2.5V
- --                  Bank 7B:  2.5V
- --                  Bank 7C:  2.5V
- --                  Bank 7D:  2.5V
- --                  Bank 8A:  2.5V
- --                  Bank 9A:  Dedicated configuration pins only, no VCCIO required.
- -- RREF          : External reference resistor for the quad, MUST be connected to
- --                 GND via a 2k Ohm resistor.
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --                  It can also be used to report unused dedicated pins. The connection
- --                  on the board for unused dedicated pins depends on whether this will
- --                  be used in a future design. One example is device migration. When
- --                  using device migration, refer to the device pin-tables. If it is a
- --                  GND pin in the pin table or if it will not be used in a future design
- --                  for another purpose the it MUST be connected to GND. If it is an unused
- --                  dedicated pin, then it can be connected to a valid signal on the board
- --                  (low, high, or toggling) if that signal is required for a different
- --                  revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --                  This pin should be connected to GND. It may also be connected  to a
- --                  valid signal  on the board  (low, high, or toggling)  if that signal
- --                  is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --                  or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
- --                 must not be connected.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-CHIP  "ex6"  ASSIGNED TO AN: 5CSEMA5F31C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A2        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
-VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
-GND                          : A12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
-GND                          : A17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
-GND                          : A26       :        :                   :         : 7A        :                
-GND                          : A27       : gnd    :                   :         :           :                
-HPS_TRST                     : A28       :        :                   :         : 7A        :                
-HPS_TMS                      : A29       :        :                   :         : 7A        :                
-GND                          : AA1       : gnd    :                   :         :           :                
-GND                          : AA2       : gnd    :                   :         :           :                
-GND                          : AA3       : gnd    :                   :         :           :                
-GND                          : AA4       : gnd    :                   :         :           :                
-VCC                          : AA5       : power  :                   : 1.1V    :           :                
-GND                          : AA6       : gnd    :                   :         :           :                
-DNU                          : AA7       :        :                   :         :           :                
-VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
-GND                          : AA9       : gnd    :                   :         :           :                
-VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
-GND                          : AA11      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
-KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
-VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
-GND                          : AA22      : gnd    :                   :         :           :                
-VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
-VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
-VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
-GND                          : AB1       : gnd    :                   :         :           :                
-GND                          : AB2       : gnd    :                   :         :           :                
-DNU                          : AB3       :        :                   :         :           :                
-DNU                          : AB4       :        :                   :         :           :                
-GND                          : AB5       : gnd    :                   :         :           :                
-VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
-GND                          : AB7       : gnd    :                   :         :           :                
-nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
-TDO                          : AB9       : output :                   :         : 3A        :                
-VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
-VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
-VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
-VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
-GND                          : AB19      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
-HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
-HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
-HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AB29      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
-GND                          : AC1       : gnd    :                   :         :           :                
-GND                          : AC2       : gnd    :                   :         :           :                
-GND                          : AC3       : gnd    :                   :         :           :                
-GND                          : AC4       : gnd    :                   :         :           :                
-TCK                          : AC5       : input  :                   :         : 3A        :                
-GND                          : AC6       : gnd    :                   :         :           :                
-AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
-GND                          : AC8       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
-VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
-VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
-VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
-VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
-GND                          : AC16      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
-VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
-VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
-VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
-HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AC26      : gnd    :                   :         :           :                
-HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AD1       : gnd    :                   :         :           :                
-GND                          : AD2       : gnd    :                   :         :           :                
-DNU                          : AD3       :        :                   :         :           :                
-DNU                          : AD4       :        :                   :         :           :                
-GND                          : AD5       : gnd    :                   :         :           :                
-VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
-VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
-VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
-DNU                          : AD15      :        :                   :         :           :                
-VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
-VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
-VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
-GND                          : AD23      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
-HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
-HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AE1       : gnd    :                   :         :           :                
-GND                          : AE2       : gnd    :                   :         :           :                
-GND                          : AE3       : gnd    :                   :         :           :                
-GND                          : AE4       : gnd    :                   :         :           :                
-AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
-AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
-AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
-GND                          : AE10      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
-VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
-GND                          : AE20      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
-VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
-HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
-GND                          : AF1       : gnd    :                   :         :           :                
-GND                          : AF2       : gnd    :                   :         :           :                
-GND                          : AF3       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
-VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
-GND                          : AF12      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
-CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
-GND                          : AF17      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
-VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
-GND                          : AF27      : gnd    :                   :         :           :                
-HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
-VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
-GND                          : AG9       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
-GND                          : AG14      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
-VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
-GND                          : AG24      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
-HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
-HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AH1       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
-GND                          : AH6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
-GND                          : AH11      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
-VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
-GND                          : AH21      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
-VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
-HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
-GND                          : AJ3       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
-VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
-VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
-VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
-GND                          : AJ18      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
-VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
-GND                          : AJ28      : gnd    :                   :         :           :                
-HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AJ30      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
-GND                          : AK5       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
-VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
-GND                          : AK15      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
-VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
-VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
-GND                          : AK25      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
-VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
-GND                          : B9        : gnd    :                   :         :           :                
-VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
-GND                          : B14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
-GND                          : B19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
-GND                          : B24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
-HPS_TDI                      : B27       :        :                   :         : 7A        :                
-HPS_TDO                      : B28       :        :                   :         : 7A        :                
-GND                          : B29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
-GND                          : C1        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
-GND                          : C6        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
-VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
-GND                          : C21       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
-GND                          : C26       : gnd    :                   :         :           :                
-HPS_nRST                     : C27       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
-GND                          : D3        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
-VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
-GND                          : D13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
-VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
-GND                          : D23       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
-HPS_CLK1                     : D25       :        :                   :         : 7A        :                
-GND                          : D26       :        :                   :         : 7A        :                
-HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
-VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
-GND                          : E10       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
-VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
-VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
-VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
-GND                          : E25       : gnd    :                   :         :           :                
-DNU                          : E26       :        :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
-GND                          : E30       : gnd    :                   :         :           :                
-DNU                          : F1        :        :                   :         :           :                
-GND                          : F2        : gnd    :                   :         :           :                
-CONF_DONE                    : F3        :        :                   :         : 9A        :                
-nSTATUS                      : F4        :        :                   :         : 9A        :                
-GND                          : F5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
-GND                          : F7        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
-VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
-GND                          : F17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
-VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
-HPS_nPOR                     : F23       :        :                   :         : 7A        :                
-HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
-HPS_CLK2                     : F25       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
-GND                          : F27       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
-GND                          : G1        :        :                   :         :           :                
-DNU                          : G2        :        :                   :         :           :                
-GND                          : G3        : gnd    :                   :         :           :                
-GND                          : G4        : gnd    :                   :         :           :                
-nCE                          : G5        :        :                   :         : 9A        :                
-MSEL2                        : G6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
-VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
-VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
-VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
-VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
-GND                          : G24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
-GND                          : H1        : gnd    :                   :         :           :                
-GND                          : H2        : gnd    :                   :         :           :                
-DNU                          : H3        :        :                   :         :           :                
-DNU                          : H4        :        :                   :         :           :                
-GND                          : H5        : gnd    :                   :         :           :                
-VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
-VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
-VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
-GND                          : H11       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
-VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
-VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
-HPS_TCK                      : H22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
-GND                          : J1        : gnd    :                   :         :           :                
-GND                          : J2        : gnd    :                   :         :           :                
-GND                          : J3        : gnd    :                   :         :           :                
-GND                          : J4        : gnd    :                   :         :           :                
-nCONFIG                      : J5        :        :                   :         : 9A        :                
-GND                          : J6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
-GND                          : J8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
-VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
-VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
-DNU                          : J15       :        :                   :         :           :                
-VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
-VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
-GND                          : J18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
-VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
-GND                          : J22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
-GND                          : J28       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
-GND                          : K1        : gnd    :                   :         :           :                
-GND                          : K2        : gnd    :                   :         :           :                
-DNU                          : K3        :        :                   :         :           :                
-DNU                          : K4        :        :                   :         :           :                
-GND                          : K5        : gnd    :                   :         :           :                
-MSEL1                        : K6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
-VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
-VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
-GND                          : K15       : gnd    :                   :         :           :                
-VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
-VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
-VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
-GND                          : K20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
-GND                          : K25       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
-GND                          : L1        : gnd    :                   :         :           :                
-GND                          : L2        : gnd    :                   :         :           :                
-GND                          : L3        : gnd    :                   :         :           :                
-GND                          : L4        : gnd    :                   :         :           :                
-VCC                          : L5        : power  :                   : 1.1V    :           :                
-GND                          : L6        : gnd    :                   :         :           :                
-MSEL3                        : L7        :        :                   :         : 9A        :                
-MSEL0                        : L8        :        :                   :         : 9A        :                
-MSEL4                        : L9        :        :                   :         : 9A        :                
-VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
-GND                          : L11       : gnd    :                   :         :           :                
-VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
-GND                          : L15       : gnd    :                   :         :           :                
-VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
-GND                          : L17       : gnd    :                   :         :           :                
-VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
-GND                          : L19       : gnd    :                   :         :           :                
-VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
-VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
-GND                          : L22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
-GND                          : M1        : gnd    :                   :         :           :                
-GND                          : M2        : gnd    :                   :         :           :                
-DNU                          : M3        :        :                   :         :           :                
-DNU                          : M4        :        :                   :         :           :                
-GND                          : M5        : gnd    :                   :         :           :                
-VCC                          : M6        : power  :                   : 1.1V    :           :                
-GND                          : M7        : gnd    :                   :         :           :                
-GND                          : M8        : gnd    :                   :         :           :                
-VCC                          : M9        : power  :                   : 1.1V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-VCC                          : M11       : power  :                   : 1.1V    :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-VCC                          : M13       : power  :                   : 1.1V    :           :                
-GND                          : M14       : gnd    :                   :         :           :                
-VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
-GND                          : M16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
-GND                          : M18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
-GND                          : M20       : gnd    :                   :         :           :                
-VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
-GND                          : M29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
-GND                          : N1        : gnd    :                   :         :           :                
-GND                          : N2        : gnd    :                   :         :           :                
-GND                          : N3        : gnd    :                   :         :           :                
-GND                          : N4        : gnd    :                   :         :           :                
-VCC                          : N5        : power  :                   : 1.1V    :           :                
-GND                          : N6        : gnd    :                   :         :           :                
-VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
-GND                          : N8        : gnd    :                   :         :           :                
-GND                          : N9        : gnd    :                   :         :           :                
-VCC                          : N10       : power  :                   : 1.1V    :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-VCC                          : N12       : power  :                   : 1.1V    :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-VCC                          : N14       : power  :                   : 1.1V    :           :                
-GND                          : N15       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
-GND                          : N17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
-GND                          : N19       : gnd    :                   :         :           :                
-VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
-VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
-VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
-GND                          : N26       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
-GND                          : P1        : gnd    :                   :         :           :                
-GND                          : P2        : gnd    :                   :         :           :                
-DNU                          : P3        :        :                   :         :           :                
-DNU                          : P4        :        :                   :         :           :                
-GND                          : P5        : gnd    :                   :         :           :                
-VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
-GND                          : P7        : gnd    :                   :         :           :                
-GND                          : P8        : gnd    :                   :         :           :                
-GND                          : P9        : gnd    :                   :         :           :                
-GND                          : P10       : gnd    :                   :         :           :                
-VCC                          : P11       : power  :                   : 1.1V    :           :                
-GND                          : P12       : gnd    :                   :         :           :                
-VCC                          : P13       : power  :                   : 1.1V    :           :                
-GND                          : P14       : gnd    :                   :         :           :                
-VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
-GND                          : P16       : gnd    :                   :         :           :                
-VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
-GND                          : P18       : gnd    :                   :         :           :                
-VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
-GND                          : P20       : gnd    :                   :         :           :                
-VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
-GND                          : R1        : gnd    :                   :         :           :                
-GND                          : R2        : gnd    :                   :         :           :                
-GND                          : R3        : gnd    :                   :         :           :                
-GND                          : R4        : gnd    :                   :         :           :                
-VCC                          : R5        : power  :                   : 1.1V    :           :                
-GND                          : R6        : gnd    :                   :         :           :                
-VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
-GND                          : R8        : gnd    :                   :         :           :                
-GND                          : R9        : gnd    :                   :         :           :                
-VCC                          : R10       : power  :                   : 1.1V    :           :                
-GND                          : R11       : gnd    :                   :         :           :                
-VCC                          : R12       : power  :                   : 1.1V    :           :                
-GND                          : R13       : gnd    :                   :         :           :                
-VCC                          : R14       : power  :                   : 1.1V    :           :                
-GND                          : R15       : gnd    :                   :         :           :                
-VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
-GND                          : R17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
-VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
-VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
-GND                          : R30       : gnd    :                   :         :           :                
-GND                          : T1        : gnd    :                   :         :           :                
-GND                          : T2        : gnd    :                   :         :           :                
-DNU                          : T3        :        :                   :         :           :                
-DNU                          : T4        :        :                   :         :           :                
-GND                          : T5        : gnd    :                   :         :           :                
-VCC                          : T6        : power  :                   : 1.1V    :           :                
-GND                          : T7        : gnd    :                   :         :           :                
-GND                          : T8        : gnd    :                   :         :           :                
-GND                          : T9        : gnd    :                   :         :           :                
-GND                          : T10       : gnd    :                   :         :           :                
-VCC                          : T11       : power  :                   : 1.1V    :           :                
-GND                          : T12       : gnd    :                   :         :           :                
-VCC                          : T13       : power  :                   : 1.1V    :           :                
-GND                          : T14       : gnd    :                   :         :           :                
-GND                          : T15       : gnd    :                   :         :           :                
-GND                          : T16       : gnd    :                   :         :           :                
-VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
-GND                          : T18       : gnd    :                   :         :           :                
-VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
-GND                          : T20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
-GND                          : T27       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
-GND                          : U1        : gnd    :                   :         :           :                
-GND                          : U2        : gnd    :                   :         :           :                
-GND                          : U3        : gnd    :                   :         :           :                
-GND                          : U4        : gnd    :                   :         :           :                
-VCC                          : U5        : power  :                   : 1.1V    :           :                
-GND                          : U6        : gnd    :                   :         :           :                
-DCLK                         : U7        :        :                   :         : 3A        :                
-TDI                          : U8        : input  :                   :         : 3A        :                
-GND                          : U9        : gnd    :                   :         :           :                
-VCC                          : U10       : power  :                   : 1.1V    :           :                
-GND                          : U11       : gnd    :                   :         :           :                
-VCC                          : U12       : power  :                   : 1.1V    :           :                
-GND                          : U13       : gnd    :                   :         :           :                
-VCC                          : U14       : power  :                   : 1.1V    :           :                
-GND                          : U15       : gnd    :                   :         :           :                
-VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
-GND                          : U17       : gnd    :                   :         :           :                
-VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
-VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
-VCC                          : U21       : power  :                   : 1.1V    :           :                
-GND                          : U22       : gnd    :                   :         :           :                
-VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
-GND                          : U24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
-GND                          : U29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
-GND                          : V1        : gnd    :                   :         :           :                
-GND                          : V2        : gnd    :                   :         :           :                
-DNU                          : V3        :        :                   :         :           :                
-DNU                          : V4        :        :                   :         :           :                
-GND                          : V5        : gnd    :                   :         :           :                
-VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
-GND                          : V7        : gnd    :                   :         :           :                
-VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
-TMS                          : V9        : input  :                   :         : 3A        :                
-GND                          : V10       : gnd    :                   :         :           :                
-VCC                          : V11       : power  :                   : 1.1V    :           :                
-GND                          : V12       : gnd    :                   :         :           :                
-VCC                          : V13       : power  :                   : 1.1V    :           :                
-GND                          : V14       : gnd    :                   :         :           :                
-VCC                          : V15       : power  :                   : 1.1V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
-GND                          : V19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
-GND                          : V21       : gnd    :                   :         :           :                
-VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
-HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
-VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
-GND                          : W1        : gnd    :                   :         :           :                
-GND                          : W2        : gnd    :                   :         :           :                
-GND                          : W3        : gnd    :                   :         :           :                
-GND                          : W4        : gnd    :                   :         :           :                
-VCC                          : W5        : power  :                   : 1.1V    :           :                
-GND                          : W6        : gnd    :                   :         :           :                
-GND                          : W7        : gnd    :                   :         :           :                
-GND                          : W8        : gnd    :                   :         :           :                
-GND                          : W9        : gnd    :                   :         :           :                
-VCC                          : W10       : power  :                   : 1.1V    :           :                
-GND                          : W11       : gnd    :                   :         :           :                
-VCC                          : W12       : power  :                   : 1.1V    :           :                
-GND                          : W13       : gnd    :                   :         :           :                
-VCC                          : W14       : power  :                   : 1.1V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
-GND                          : W18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                
-HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
-HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
-GND                          : W28       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
-GND                          : Y1        : gnd    :                   :         :           :                
-GND                          : Y2        : gnd    :                   :         :           :                
-DNU                          : Y3        :        :                   :         :           :                
-DNU                          : Y4        :        :                   :         :           :                
-GND                          : Y5        : gnd    :                   :         :           :                
-VCC                          : Y6        : power  :                   : 1.1V    :           :                
-GND                          : Y7        : gnd    :                   :         :           :                
-GND                          : Y8        : gnd    :                   :         :           :                
-VCC                          : Y9        : power  :                   : 1.1V    :           :                
-GND                          : Y10       : gnd    :                   :         :           :                
-VCC                          : Y11       : power  :                   : 1.1V    :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-VCC                          : Y13       : power  :                   : 1.1V    :           :                
-GND                          : Y14       : gnd    :                   :         :           :                
-GND                          : Y15       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
-GND                          : Y20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
-VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
-HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : Y25       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
-GND                          : Y30       : gnd    :                   :         :           :                
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       2.5V
+ --                  Bank 3B:       3.3V
+ --                  Bank 4A:       3.3V
+ --                  Bank 5A:       3.3V
+ --                  Bank 5B:       3.3V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex6"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
+HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AC26      : gnd    :                   :         :           :                
+HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
+HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
+GND                          : W18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                
+HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
+HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_2/ex6/output_files/ex6.sld b/part_2/ex6/output_files/ex6.sld
index f7d3ed7..41a6030 100755
--- a/part_2/ex6/output_files/ex6.sld
+++ b/part_2/ex6/output_files/ex6.sld
@@ -1 +1 @@
-<sld_project_info/>
+<sld_project_info/>
diff --git a/part_2/ex6/output_files/ex6.sof b/part_2/ex6/output_files/ex6.sof
index bf15168..596fc0b 100755
--- a/part_2/ex6/output_files/ex6.sof
+++ b/part_2/ex6/output_files/ex6.sof
diff --git a/part_2/ex6/output_files/ex6.sta.rpt b/part_2/ex6/output_files/ex6.sta.rpt
index 628adb0..48220e4 100755
--- a/part_2/ex6/output_files/ex6.sta.rpt
+++ b/part_2/ex6/output_files/ex6.sta.rpt
@@ -1,839 +1,839 @@
-TimeQuest Timing Analyzer report for ex6
-Sun Dec 11 18:08:41 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. SDC File List
-  5. Clocks
-  6. Slow 1100mV 85C Model Fmax Summary
-  7. Timing Closure Recommendations
-  8. Slow 1100mV 85C Model Setup Summary
-  9. Slow 1100mV 85C Model Hold Summary
- 10. Slow 1100mV 85C Model Recovery Summary
- 11. Slow 1100mV 85C Model Removal Summary
- 12. Slow 1100mV 85C Model Minimum Pulse Width Summary
- 13. Slow 1100mV 85C Model Metastability Summary
- 14. Slow 1100mV 0C Model Fmax Summary
- 15. Slow 1100mV 0C Model Setup Summary
- 16. Slow 1100mV 0C Model Hold Summary
- 17. Slow 1100mV 0C Model Recovery Summary
- 18. Slow 1100mV 0C Model Removal Summary
- 19. Slow 1100mV 0C Model Minimum Pulse Width Summary
- 20. Slow 1100mV 0C Model Metastability Summary
- 21. Fast 1100mV 85C Model Setup Summary
- 22. Fast 1100mV 85C Model Hold Summary
- 23. Fast 1100mV 85C Model Recovery Summary
- 24. Fast 1100mV 85C Model Removal Summary
- 25. Fast 1100mV 85C Model Minimum Pulse Width Summary
- 26. Fast 1100mV 85C Model Metastability Summary
- 27. Fast 1100mV 0C Model Setup Summary
- 28. Fast 1100mV 0C Model Hold Summary
- 29. Fast 1100mV 0C Model Recovery Summary
- 30. Fast 1100mV 0C Model Removal Summary
- 31. Fast 1100mV 0C Model Minimum Pulse Width Summary
- 32. Fast 1100mV 0C Model Metastability Summary
- 33. Multicorner Timing Analysis Summary
- 34. Board Trace Model Assignments
- 35. Input Transition Times
- 36. Signal Integrity Metrics (Slow 1100mv 0c Model)
- 37. Signal Integrity Metrics (Slow 1100mv 85c Model)
- 38. Signal Integrity Metrics (Fast 1100mv 0c Model)
- 39. Signal Integrity Metrics (Fast 1100mv 85c Model)
- 40. Setup Transfers
- 41. Hold Transfers
- 42. Report TCCS
- 43. Report RSKM
- 44. Unconstrained Paths Summary
- 45. Clock Status Summary
- 46. Unconstrained Input Ports
- 47. Unconstrained Output Ports
- 48. Unconstrained Input Ports
- 49. Unconstrained Output Ports
- 50. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                           ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Timing Analyzer       ; TimeQuest                                           ;
-; Revision Name         ; ex6                                                 ;
-; Device Family         ; Cyclone V                                           ;
-; Device Name           ; 5CSEMA5F31C6                                        ;
-; Timing Models         ; Final                                               ;
-; Delay Model           ; Combined                                            ;
-; Rise/Fall Delays      ; Enabled                                             ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.12        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   3.9%      ;
-;     Processor 3            ;   3.9%      ;
-;     Processor 4            ;   3.8%      ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------+
-; SDC File List                                     ;
-+---------------+--------+--------------------------+
-; SDC File Path ; Status ; Read at                  ;
-+---------------+--------+--------------------------+
-; ex6.sdc       ; OK     ; Sun Dec 11 18:08:38 2016 ;
-+---------------+--------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                               ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets      ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-; CLOCK_50   ; Base ; 20.000 ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 } ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-
-
-+--------------------------------------------------+
-; Slow 1100mV 85C Model Fmax Summary               ;
-+------------+-----------------+------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 210.08 MHz ; 210.08 MHz      ; CLOCK_50   ;      ;
-+------------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+-------------------------------------+
-; Slow 1100mV 85C Model Setup Summary ;
-+----------+--------+-----------------+
-; Clock    ; Slack  ; End Point TNS   ;
-+----------+--------+-----------------+
-; CLOCK_50 ; 15.240 ; 0.000           ;
-+----------+--------+-----------------+
-
-
-+------------------------------------+
-; Slow 1100mV 85C Model Hold Summary ;
-+----------+-------+-----------------+
-; Clock    ; Slack ; End Point TNS   ;
-+----------+-------+-----------------+
-; CLOCK_50 ; 0.387 ; 0.000           ;
-+----------+-------+-----------------+
-
-
-------------------------------------------
-; Slow 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
-+----------+-------+--------------------------------+
-; Clock    ; Slack ; End Point TNS                  ;
-+----------+-------+--------------------------------+
-; CLOCK_50 ; 8.843 ; 0.000                          ;
-+----------+-------+--------------------------------+
-
-
------------------------------------------------
-; Slow 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary                ;
-+------------+-----------------+------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 204.08 MHz ; 204.08 MHz      ; CLOCK_50   ;      ;
-+------------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+------------------------------------+
-; Slow 1100mV 0C Model Setup Summary ;
-+----------+--------+----------------+
-; Clock    ; Slack  ; End Point TNS  ;
-+----------+--------+----------------+
-; CLOCK_50 ; 15.100 ; 0.000          ;
-+----------+--------+----------------+
-
-
-+-----------------------------------+
-; Slow 1100mV 0C Model Hold Summary ;
-+----------+-------+----------------+
-; Clock    ; Slack ; End Point TNS  ;
-+----------+-------+----------------+
-; CLOCK_50 ; 0.386 ; 0.000          ;
-+----------+-------+----------------+
-
-
------------------------------------------
-; Slow 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
-+----------+-------+-------------------------------+
-; Clock    ; Slack ; End Point TNS                 ;
-+----------+-------+-------------------------------+
-; CLOCK_50 ; 8.841 ; 0.000                         ;
-+----------+-------+-------------------------------+
-
-
-----------------------------------------------
-; Slow 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+-------------------------------------+
-; Fast 1100mV 85C Model Setup Summary ;
-+----------+--------+-----------------+
-; Clock    ; Slack  ; End Point TNS   ;
-+----------+--------+-----------------+
-; CLOCK_50 ; 17.054 ; 0.000           ;
-+----------+--------+-----------------+
-
-
-+------------------------------------+
-; Fast 1100mV 85C Model Hold Summary ;
-+----------+-------+-----------------+
-; Clock    ; Slack ; End Point TNS   ;
-+----------+-------+-----------------+
-; CLOCK_50 ; 0.204 ; 0.000           ;
-+----------+-------+-----------------+
-
-
-------------------------------------------
-; Fast 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
-+----------+-------+--------------------------------+
-; Clock    ; Slack ; End Point TNS                  ;
-+----------+-------+--------------------------------+
-; CLOCK_50 ; 8.791 ; 0.000                          ;
-+----------+-------+--------------------------------+
-
-
------------------------------------------------
-; Fast 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+------------------------------------+
-; Fast 1100mV 0C Model Setup Summary ;
-+----------+--------+----------------+
-; Clock    ; Slack  ; End Point TNS  ;
-+----------+--------+----------------+
-; CLOCK_50 ; 17.214 ; 0.000          ;
-+----------+--------+----------------+
-
-
-+-----------------------------------+
-; Fast 1100mV 0C Model Hold Summary ;
-+----------+-------+----------------+
-; Clock    ; Slack ; End Point TNS  ;
-+----------+-------+----------------+
-; CLOCK_50 ; 0.194 ; 0.000          ;
-+----------+-------+----------------+
-
-
------------------------------------------
-; Fast 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
-+----------+-------+-------------------------------+
-; Clock    ; Slack ; End Point TNS                 ;
-+----------+-------+-------------------------------+
-; CLOCK_50 ; 8.764 ; 0.000                         ;
-+----------+-------+-------------------------------+
-
-
-----------------------------------------------
-; Fast 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                          ;
-+------------------+--------+-------+----------+---------+---------------------+
-; Clock            ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+--------+-------+----------+---------+---------------------+
-; Worst-case Slack ; 15.100 ; 0.194 ; N/A      ; N/A     ; 8.764               ;
-;  CLOCK_50        ; 15.100 ; 0.194 ; N/A      ; N/A     ; 8.764               ;
-; Design-wide TNS  ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
-;  CLOCK_50        ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
-+------------------+--------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+-------------------------------------------------------------+
-; Input Transition Times                                      ;
-+----------+--------------+-----------------+-----------------+
-; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+----------+--------------+-----------------+-----------------+
-; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-+----------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-------------------------------------------------------------------+
-; Setup Transfers                                                   ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; CLOCK_50   ; CLOCK_50 ; 281      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------+
-; Hold Transfers                                                    ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; CLOCK_50   ; CLOCK_50 ; 281      ; 0        ; 0        ; 0        ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary                    ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 1     ; 1    ;
-; Unconstrained Input Ports       ; 2     ; 2    ;
-; Unconstrained Input Port Paths  ; 32    ; 32   ;
-; Unconstrained Output Ports      ; 35    ; 35   ;
-; Unconstrained Output Port Paths ; 483   ; 483  ;
-+---------------------------------+-------+------+
-
-
-+----------------------------------------------------------+
-; Clock Status Summary                                     ;
-+------------------------+----------+------+---------------+
-; Target                 ; Clock    ; Type ; Status        ;
-+------------------------+----------+------+---------------+
-; CLOCK_50               ; CLOCK_50 ; Base ; Constrained   ;
-; tick_50000:tck|CLK_OUT ;          ; Base ; Unconstrained ;
-+------------------------+----------+------+---------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime TimeQuest Timing Analyzer
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 18:08:37 2016
-Info: Command: quartus_sta ex6 -c ex6
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (332104): Reading SDC File: 'ex6.sdc'
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
-    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1100mV 85C Model
-Info (332146): Worst-case setup slack is 15.240
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    15.240               0.000 CLOCK_50 
-Info (332146): Worst-case hold slack is 0.387
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.387               0.000 CLOCK_50 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 8.843
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     8.843               0.000 CLOCK_50 
-Info: Analyzing Slow 1100mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
-    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332146): Worst-case setup slack is 15.100
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    15.100               0.000 CLOCK_50 
-Info (332146): Worst-case hold slack is 0.386
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.386               0.000 CLOCK_50 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 8.841
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     8.841               0.000 CLOCK_50 
-Info: Analyzing Fast 1100mV 85C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
-    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332146): Worst-case setup slack is 17.054
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    17.054               0.000 CLOCK_50 
-Info (332146): Worst-case hold slack is 0.204
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.204               0.000 CLOCK_50 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 8.791
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     8.791               0.000 CLOCK_50 
-Info: Analyzing Fast 1100mV 0C Model
-Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
-    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332146): Worst-case setup slack is 17.214
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    17.214               0.000 CLOCK_50 
-Info (332146): Worst-case hold slack is 0.194
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.194               0.000 CLOCK_50 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 8.764
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     8.764               0.000 CLOCK_50 
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 1214 megabytes
-    Info: Processing ended: Sun Dec 11 18:08:41 2016
-    Info: Elapsed time: 00:00:04
-    Info: Total CPU time (on all processors): 00:00:05
-
-
+TimeQuest Timing Analyzer report for ex6
+Tue Nov 22 11:43:46 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Slow 1100mV 85C Model Fmax Summary
+  7. Timing Closure Recommendations
+  8. Slow 1100mV 85C Model Setup Summary
+  9. Slow 1100mV 85C Model Hold Summary
+ 10. Slow 1100mV 85C Model Recovery Summary
+ 11. Slow 1100mV 85C Model Removal Summary
+ 12. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1100mV 85C Model Metastability Summary
+ 14. Slow 1100mV 0C Model Fmax Summary
+ 15. Slow 1100mV 0C Model Setup Summary
+ 16. Slow 1100mV 0C Model Hold Summary
+ 17. Slow 1100mV 0C Model Recovery Summary
+ 18. Slow 1100mV 0C Model Removal Summary
+ 19. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 20. Slow 1100mV 0C Model Metastability Summary
+ 21. Fast 1100mV 85C Model Setup Summary
+ 22. Fast 1100mV 85C Model Hold Summary
+ 23. Fast 1100mV 85C Model Recovery Summary
+ 24. Fast 1100mV 85C Model Removal Summary
+ 25. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 26. Fast 1100mV 85C Model Metastability Summary
+ 27. Fast 1100mV 0C Model Setup Summary
+ 28. Fast 1100mV 0C Model Hold Summary
+ 29. Fast 1100mV 0C Model Recovery Summary
+ 30. Fast 1100mV 0C Model Removal Summary
+ 31. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 32. Fast 1100mV 0C Model Metastability Summary
+ 33. Multicorner Timing Analysis Summary
+ 34. Board Trace Model Assignments
+ 35. Input Transition Times
+ 36. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 37. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 39. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 40. Setup Transfers
+ 41. Hold Transfers
+ 42. Report TCCS
+ 43. Report RSKM
+ 44. Unconstrained Paths Summary
+ 45. Clock Status Summary
+ 46. Unconstrained Input Ports
+ 47. Unconstrained Output Ports
+ 48. Unconstrained Input Ports
+ 49. Unconstrained Output Ports
+ 50. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex6                                                     ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CSEMA5F31C6                                            ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.10        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   3.2%      ;
+;     Processor 3            ;   3.2%      ;
+;     Processor 4            ;   3.2%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; ex6.sdc       ; OK     ; Tue Nov 22 11:43:43 2016 ;
++---------------+--------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                               ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; Clock Name ; Type ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets      ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; CLOCK_50   ; Base ; 20.000 ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 } ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+
+
++--------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary               ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 216.31 MHz ; 216.31 MHz      ; CLOCK_50   ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1100mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock    ; Slack  ; End Point TNS   ;
++----------+--------+-----------------+
+; CLOCK_50 ; 15.377 ; 0.000           ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Slow 1100mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock    ; Slack ; End Point TNS   ;
++----------+-------+-----------------+
+; CLOCK_50 ; 0.388 ; 0.000           ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++----------+-------+--------------------------------+
+; Clock    ; Slack ; End Point TNS                  ;
++----------+-------+--------------------------------+
+; CLOCK_50 ; 8.900 ; 0.000                          ;
++----------+-------+--------------------------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 212.13 MHz ; 212.13 MHz      ; CLOCK_50   ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1100mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock    ; Slack  ; End Point TNS  ;
++----------+--------+----------------+
+; CLOCK_50 ; 15.286 ; 0.000          ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Slow 1100mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock    ; Slack ; End Point TNS  ;
++----------+-------+----------------+
+; CLOCK_50 ; 0.385 ; 0.000          ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
++----------+-------+-------------------------------+
+; Clock    ; Slack ; End Point TNS                 ;
++----------+-------+-------------------------------+
+; CLOCK_50 ; 8.899 ; 0.000                         ;
++----------+-------+-------------------------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------+
+; Fast 1100mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock    ; Slack  ; End Point TNS   ;
++----------+--------+-----------------+
+; CLOCK_50 ; 17.068 ; 0.000           ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Fast 1100mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock    ; Slack ; End Point TNS   ;
++----------+-------+-----------------+
+; CLOCK_50 ; 0.204 ; 0.000           ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++----------+-------+--------------------------------+
+; Clock    ; Slack ; End Point TNS                  ;
++----------+-------+--------------------------------+
+; CLOCK_50 ; 8.836 ; 0.000                          ;
++----------+-------+--------------------------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1100mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock    ; Slack  ; End Point TNS  ;
++----------+--------+----------------+
+; CLOCK_50 ; 17.237 ; 0.000          ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Fast 1100mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock    ; Slack ; End Point TNS  ;
++----------+-------+----------------+
+; CLOCK_50 ; 0.194 ; 0.000          ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
++----------+-------+-------------------------------+
+; Clock    ; Slack ; End Point TNS                 ;
++----------+-------+-------------------------------+
+; CLOCK_50 ; 8.806 ; 0.000                         ;
++----------+-------+-------------------------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                          ;
++------------------+--------+-------+----------+---------+---------------------+
+; Clock            ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+--------+-------+----------+---------+---------------------+
+; Worst-case Slack ; 15.286 ; 0.194 ; N/A      ; N/A     ; 8.806               ;
+;  CLOCK_50        ; 15.286 ; 0.194 ; N/A      ; N/A     ; 8.806               ;
+; Design-wide TNS  ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
+;  CLOCK_50        ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
++------------------+--------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50 ; 289      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50 ; 289      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 1     ; 1    ;
+; Unconstrained Input Ports       ; 2     ; 2    ;
+; Unconstrained Input Port Paths  ; 32    ; 32   ;
+; Unconstrained Output Ports      ; 35    ; 35   ;
+; Unconstrained Output Port Paths ; 483   ; 483  ;
++---------------------------------+-------+------+
+
+
++----------------------------------------------------------+
+; Clock Status Summary                                     ;
++------------------------+----------+------+---------------+
+; Target                 ; Clock    ; Type ; Status        ;
++------------------------+----------+------+---------------+
+; CLOCK_50               ; CLOCK_50 ; Base ; Constrained   ;
+; tick_50000:tck|CLK_OUT ;          ; Base ; Unconstrained ;
++------------------------+----------+------+---------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Tue Nov 22 11:43:41 2016
+Info: Command: quartus_sta ex6 -c ex6
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332104): Reading SDC File: 'ex6.sdc'
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Info (332146): Worst-case setup slack is 15.377
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    15.377               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.388
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.388               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.900
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     8.900               0.000 CLOCK_50 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 15.286
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    15.286               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.385
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.385               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.899
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     8.899               0.000 CLOCK_50 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 17.068
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    17.068               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.204
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.204               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.836
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     8.836               0.000 CLOCK_50 
+Info: Analyzing Fast 1100mV 0C Model
+Warning (332060): Node: tick_50000:tck|CLK_OUT was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register counter_16:C|count[0] is being clocked by tick_50000:tck|CLK_OUT
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 17.237
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    17.237               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.194
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.194               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.806
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     8.806               0.000 CLOCK_50 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 1209 megabytes
+    Info: Processing ended: Tue Nov 22 11:43:46 2016
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/part_2/ex6/output_files/ex6.sta.summary b/part_2/ex6/output_files/ex6.sta.summary
index 01d120f..d09b990 100755
--- a/part_2/ex6/output_files/ex6.sta.summary
+++ b/part_2/ex6/output_files/ex6.sta.summary
@@ -1,53 +1,53 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 15.240
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.387
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.843
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 15.100
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.386
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.841
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 17.054
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.204
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.791
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 17.214
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.194
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.764
-TNS   : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : 15.377
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.388
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.900
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : 15.286
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.385
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.899
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : 17.068
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.204
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.836
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : 17.237
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.194
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.806
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_2/ex7/db/_cmp.kpt b/part_2/ex7/db/_cmp.kpt
deleted file mode 100644
index 7fc2356..0000000
--- a/part_2/ex7/db/_cmp.kpt
+++ /dev/null
diff --git a/part_2/ex8/c5_pin_model_dump.txt b/part_2/ex8/c5_pin_model_dump.txt
index 31bb72c..a895a64 100755
--- a/part_2/ex8/c5_pin_model_dump.txt
+++ b/part_2/ex8/c5_pin_model_dump.txt
@@ -1,118 +1,118 @@
-io_4iomodule_c5_index: 55gpio_index: 2
-io_4iomodule_c5_index: 54gpio_index: 465
-io_4iomodule_c5_index: 33gpio_index: 6
-io_4iomodule_c5_index: 51gpio_index: 461
-io_4iomodule_c5_index: 27gpio_index: 10
-io_4iomodule_c5_index: 57gpio_index: 457
-io_4iomodule_c5_index: 34gpio_index: 14
-io_4iomodule_c5_index: 28gpio_index: 453
-io_4iomodule_c5_index: 26gpio_index: 19
-io_4iomodule_c5_index: 47gpio_index: 449
-io_4iomodule_c5_index: 29gpio_index: 22
-io_4iomodule_c5_index: 3gpio_index: 445
-io_4iomodule_c5_index: 16gpio_index: 27
-io_4iomodule_c5_index: 6gpio_index: 441
-io_4iomodule_c5_index: 50gpio_index: 30
-io_4iomodule_c5_index: 35gpio_index: 437
-io_4iomodule_c5_index: 7gpio_index: 35
-io_4iomodule_c5_index: 53gpio_index: 433
-io_4iomodule_c5_index: 12gpio_index: 38
-io_4iomodule_c5_index: 1gpio_index: 429
-io_4iomodule_c5_index: 22gpio_index: 43
-io_4iomodule_c5_index: 8gpio_index: 425
-io_4iomodule_c5_index: 20gpio_index: 46
-io_4iomodule_c5_index: 30gpio_index: 421
-io_4iomodule_c5_index: 2gpio_index: 51
-io_4iomodule_c5_index: 31gpio_index: 417
-io_4iomodule_c5_index: 39gpio_index: 54
-io_4iomodule_c5_index: 18gpio_index: 413
-io_4iomodule_c5_index: 10gpio_index: 59
-io_4iomodule_c5_index: 42gpio_index: 409
-io_4iomodule_c5_index: 5gpio_index: 62
-io_4iomodule_c5_index: 24gpio_index: 405
-io_4iomodule_c5_index: 37gpio_index: 67
-io_4iomodule_c5_index: 13gpio_index: 401
-io_4iomodule_c5_index: 0gpio_index: 70
-io_4iomodule_c5_index: 44gpio_index: 397
-io_4iomodule_c5_index: 38gpio_index: 75
-io_4iomodule_c5_index: 52gpio_index: 393
-io_4iomodule_c5_index: 32gpio_index: 78
-io_4iomodule_c5_index: 56gpio_index: 389
-io_4iomodule_a_index: 13gpio_index: 385
-io_4iomodule_c5_index: 4gpio_index: 83
-io_4iomodule_c5_index: 23gpio_index: 86
-io_4iomodule_a_index: 15gpio_index: 381
-io_4iomodule_a_index: 8gpio_index: 377
-io_4iomodule_c5_index: 46gpio_index: 91
-io_4iomodule_a_index: 5gpio_index: 373
-io_4iomodule_a_index: 11gpio_index: 369
-io_4iomodule_c5_index: 41gpio_index: 94
-io_4iomodule_a_index: 3gpio_index: 365
-io_4iomodule_c5_index: 25gpio_index: 99
-io_4iomodule_a_index: 7gpio_index: 361
-io_4iomodule_c5_index: 9gpio_index: 102
-io_4iomodule_a_index: 0gpio_index: 357
-io_4iomodule_c5_index: 14gpio_index: 107
-io_4iomodule_a_index: 12gpio_index: 353
-io_4iomodule_c5_index: 45gpio_index: 110
-io_4iomodule_c5_index: 17gpio_index: 115
-io_4iomodule_a_index: 4gpio_index: 349
-io_4iomodule_c5_index: 36gpio_index: 118
-io_4iomodule_a_index: 10gpio_index: 345
-io_4iomodule_a_index: 16gpio_index: 341
-io_4iomodule_c5_index: 15gpio_index: 123
-io_4iomodule_a_index: 14gpio_index: 337
-io_4iomodule_c5_index: 43gpio_index: 126
-io_4iomodule_c5_index: 19gpio_index: 131
-io_4iomodule_a_index: 1gpio_index: 333
-io_4iomodule_c5_index: 59gpio_index: 134
-io_4iomodule_a_index: 2gpio_index: 329
-io_4iomodule_a_index: 9gpio_index: 325
-io_4iomodule_c5_index: 48gpio_index: 139
-io_4iomodule_a_index: 6gpio_index: 321
-io_4iomodule_a_index: 17gpio_index: 317
-io_4iomodule_c5_index: 40gpio_index: 142
-io_4iomodule_c5_index: 11gpio_index: 147
-io_4iomodule_c5_index: 58gpio_index: 150
-io_4iomodule_c5_index: 21gpio_index: 155
-io_4iomodule_c5_index: 49gpio_index: 158
-io_4iomodule_h_c5_index: 0gpio_index: 161
-io_4iomodule_h_c5_index: 6gpio_index: 165
-io_4iomodule_h_c5_index: 10gpio_index: 169
-io_4iomodule_h_c5_index: 3gpio_index: 173
-io_4iomodule_h_c5_index: 8gpio_index: 176
-io_4iomodule_h_c5_index: 11gpio_index: 180
-io_4iomodule_h_c5_index: 7gpio_index: 184
-io_4iomodule_h_c5_index: 5gpio_index: 188
-io_4iomodule_h_c5_index: 1gpio_index: 192
-io_4iomodule_h_c5_index: 2gpio_index: 196
-io_4iomodule_h_c5_index: 9gpio_index: 200
-io_4iomodule_h_c5_index: 4gpio_index: 204
-io_4iomodule_h_index: 15gpio_index: 208
-io_4iomodule_h_index: 1gpio_index: 212
-io_4iomodule_h_index: 3gpio_index: 216
-io_4iomodule_h_index: 2gpio_index: 220
-io_4iomodule_h_index: 11gpio_index: 224
-io_4iomodule_vref_h_index: 1gpio_index: 228
-io_4iomodule_h_index: 20gpio_index: 231
-io_4iomodule_h_index: 8gpio_index: 235
-io_4iomodule_h_index: 6gpio_index: 239
-io_4iomodule_h_index: 10gpio_index: 243
-io_4iomodule_h_index: 23gpio_index: 247
-io_4iomodule_h_index: 7gpio_index: 251
-io_4iomodule_h_index: 22gpio_index: 255
-io_4iomodule_h_index: 5gpio_index: 259
-io_4iomodule_h_index: 24gpio_index: 263
-io_4iomodule_h_index: 0gpio_index: 267
-io_4iomodule_h_index: 13gpio_index: 271
-io_4iomodule_h_index: 21gpio_index: 275
-io_4iomodule_h_index: 16gpio_index: 279
-io_4iomodule_vref_h_index: 0gpio_index: 283
-io_4iomodule_h_index: 12gpio_index: 286
-io_4iomodule_h_index: 4gpio_index: 290
-io_4iomodule_h_index: 19gpio_index: 294
-io_4iomodule_h_index: 18gpio_index: 298
-io_4iomodule_h_index: 17gpio_index: 302
-io_4iomodule_h_index: 25gpio_index: 306
-io_4iomodule_h_index: 14gpio_index: 310
-io_4iomodule_h_index: 9gpio_index: 314
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_2/ex8/db/.cmp.kpt b/part_2/ex8/db/.cmp.kpt
deleted file mode 100755
index 0d971a6..0000000
--- a/part_2/ex8/db/.cmp.kpt
+++ /dev/null
diff --git a/part_2/ex8/db/_cmp.kpt b/part_2/ex8/db/_cmp.kpt
index 810fa45..810fa45 100644..100755
--- a/part_2/ex8/db/_cmp.kpt
+++ b/part_2/ex8/db/_cmp.kpt
diff --git a/part_2/ex8/db/ex8.(0).cnf.cdb b/part_2/ex8/db/ex8.(0).cnf.cdb
index 384ecf4..5cdd1d4 100755
--- a/part_2/ex8/db/ex8.(0).cnf.cdb
+++ b/part_2/ex8/db/ex8.(0).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(0).cnf.hdb b/part_2/ex8/db/ex8.(0).cnf.hdb
index ce68447..1ffd6a6 100755
--- a/part_2/ex8/db/ex8.(0).cnf.hdb
+++ b/part_2/ex8/db/ex8.(0).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(1).cnf.cdb b/part_2/ex8/db/ex8.(1).cnf.cdb
index 57cfdcd..4aa533b 100755
--- a/part_2/ex8/db/ex8.(1).cnf.cdb
+++ b/part_2/ex8/db/ex8.(1).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(1).cnf.hdb b/part_2/ex8/db/ex8.(1).cnf.hdb
index 5f35188..592417b 100755
--- a/part_2/ex8/db/ex8.(1).cnf.hdb
+++ b/part_2/ex8/db/ex8.(1).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(2).cnf.cdb b/part_2/ex8/db/ex8.(2).cnf.cdb
index f243f2d..fa21ea0 100755
--- a/part_2/ex8/db/ex8.(2).cnf.cdb
+++ b/part_2/ex8/db/ex8.(2).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(2).cnf.hdb b/part_2/ex8/db/ex8.(2).cnf.hdb
index 5c5a19f..9b7ef11 100755
--- a/part_2/ex8/db/ex8.(2).cnf.hdb
+++ b/part_2/ex8/db/ex8.(2).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(3).cnf.cdb b/part_2/ex8/db/ex8.(3).cnf.cdb
index 6fc4545..64a5fa0 100755
--- a/part_2/ex8/db/ex8.(3).cnf.cdb
+++ b/part_2/ex8/db/ex8.(3).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(3).cnf.hdb b/part_2/ex8/db/ex8.(3).cnf.hdb
index d9a96e9..df64d5f 100755
--- a/part_2/ex8/db/ex8.(3).cnf.hdb
+++ b/part_2/ex8/db/ex8.(3).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(4).cnf.cdb b/part_2/ex8/db/ex8.(4).cnf.cdb
index fb6e8f4..e6a0005 100755
--- a/part_2/ex8/db/ex8.(4).cnf.cdb
+++ b/part_2/ex8/db/ex8.(4).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(4).cnf.hdb b/part_2/ex8/db/ex8.(4).cnf.hdb
index 3e83407..1aa2860 100755
--- a/part_2/ex8/db/ex8.(4).cnf.hdb
+++ b/part_2/ex8/db/ex8.(4).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(5).cnf.cdb b/part_2/ex8/db/ex8.(5).cnf.cdb
index 010f7bf..e02c97b 100755
--- a/part_2/ex8/db/ex8.(5).cnf.cdb
+++ b/part_2/ex8/db/ex8.(5).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(5).cnf.hdb b/part_2/ex8/db/ex8.(5).cnf.hdb
index 57f6d11..92790f4 100755
--- a/part_2/ex8/db/ex8.(5).cnf.hdb
+++ b/part_2/ex8/db/ex8.(5).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(6).cnf.cdb b/part_2/ex8/db/ex8.(6).cnf.cdb
index 5e29665..2ef9091 100755
--- a/part_2/ex8/db/ex8.(6).cnf.cdb
+++ b/part_2/ex8/db/ex8.(6).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(6).cnf.hdb b/part_2/ex8/db/ex8.(6).cnf.hdb
index b5187a6..af5dcd5 100755
--- a/part_2/ex8/db/ex8.(6).cnf.hdb
+++ b/part_2/ex8/db/ex8.(6).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(7).cnf.cdb b/part_2/ex8/db/ex8.(7).cnf.cdb
index 96d06c4..280aa80 100755
--- a/part_2/ex8/db/ex8.(7).cnf.cdb
+++ b/part_2/ex8/db/ex8.(7).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(7).cnf.hdb b/part_2/ex8/db/ex8.(7).cnf.hdb
index 6472597..42ab8b5 100755
--- a/part_2/ex8/db/ex8.(7).cnf.hdb
+++ b/part_2/ex8/db/ex8.(7).cnf.hdb
diff --git a/part_2/ex8/db/ex8.(8).cnf.cdb b/part_2/ex8/db/ex8.(8).cnf.cdb
index 21f3e91..75ea495 100755
--- a/part_2/ex8/db/ex8.(8).cnf.cdb
+++ b/part_2/ex8/db/ex8.(8).cnf.cdb
diff --git a/part_2/ex8/db/ex8.(8).cnf.hdb b/part_2/ex8/db/ex8.(8).cnf.hdb
index 19237fb..1df751e 100755
--- a/part_2/ex8/db/ex8.(8).cnf.hdb
+++ b/part_2/ex8/db/ex8.(8).cnf.hdb
diff --git a/part_2/ex8/db/ex8.ae.hdb b/part_2/ex8/db/ex8.ae.hdb
new file mode 100755
index 0000000..58cff3f
--- /dev/null
+++ b/part_2/ex8/db/ex8.ae.hdb
diff --git a/part_2/ex8/db/ex8.analyze_file.qmsg b/part_2/ex8/db/ex8.analyze_file.qmsg
new file mode 100755
index 0000000..34ad0f8
--- /dev/null
+++ b/part_2/ex8/db/ex8.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479898397112 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 23 10:53:16 2016 " "Processing started: Wed Nov 23 10:53:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479898397113 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 --analyze_file=\"C:/New folder/ex8/verilog_files/formula_fsm.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 --analyze_file=\"C:/New folder/ex8/verilog_files/formula_fsm.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479898397114 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479898397537 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479898397537 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "827 " "Peak virtual memory: 827 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 23 10:53:26 2016 " "Processing ended: Wed Nov 23 10:53:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479898406239 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479898406239 ""}
diff --git a/part_2/ex8/db/ex8.asm.qmsg b/part_2/ex8/db/ex8.asm.qmsg
index fc431f6..578d460 100755
--- a/part_2/ex8/db/ex8.asm.qmsg
+++ b/part_2/ex8/db/ex8.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481487937303 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487937309 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:25:37 2016 " "Processing started: Sun Dec 11 20:25:37 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487937309 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481487937309 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481487937310 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481487937932 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481487942927 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "972 " "Peak virtual memory: 972 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487943285 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:25:43 2016 " "Processing ended: Sun Dec 11 20:25:43 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487943285 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487943285 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487943285 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481487943285 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481113330953 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481113330956 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:22:10 2016 " "Processing started: Wed Dec 07 12:22:10 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481113330956 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481113330956 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481113330957 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481113331992 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481113336870 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "891 " "Peak virtual memory: 891 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113340323 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:22:20 2016 " "Processing ended: Wed Dec 07 12:22:20 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113340323 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113340323 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113340323 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481113340323 ""}
diff --git a/part_2/ex8/db/ex8.asm.rdb b/part_2/ex8/db/ex8.asm.rdb
index 17c9d85..a03ad06 100755
--- a/part_2/ex8/db/ex8.asm.rdb
+++ b/part_2/ex8/db/ex8.asm.rdb
diff --git a/part_2/ex8/db/ex8.cbx.xml b/part_2/ex8/db/ex8.cbx.xml
index 4d64333..721f2cf 100755
--- a/part_2/ex8/db/ex8.cbx.xml
+++ b/part_2/ex8/db/ex8.cbx.xml
@@ -1,5 +1,5 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
-	<PROJECT NAME="ex8">
-	</PROJECT>
-</LOG_ROOT>
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ex8">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/part_2/ex8/db/ex8.cmp.ammdb b/part_2/ex8/db/ex8.cmp.ammdb
new file mode 100755
index 0000000..bafd7cb
--- /dev/null
+++ b/part_2/ex8/db/ex8.cmp.ammdb
diff --git a/part_2/ex8/db/ex8.cmp.bpm b/part_2/ex8/db/ex8.cmp.bpm
index 029c54f..ba5a84b 100755
--- a/part_2/ex8/db/ex8.cmp.bpm
+++ b/part_2/ex8/db/ex8.cmp.bpm
diff --git a/part_2/ex8/db/ex8.cmp.cdb b/part_2/ex8/db/ex8.cmp.cdb
index ae6fe71..3efffc3 100755
--- a/part_2/ex8/db/ex8.cmp.cdb
+++ b/part_2/ex8/db/ex8.cmp.cdb
diff --git a/part_2/ex8/db/ex8.cmp.hdb b/part_2/ex8/db/ex8.cmp.hdb
index 88b87e4..e0384e8 100755
--- a/part_2/ex8/db/ex8.cmp.hdb
+++ b/part_2/ex8/db/ex8.cmp.hdb
diff --git a/part_2/ex8/db/ex8.cmp.idb b/part_2/ex8/db/ex8.cmp.idb
index d39ad21..120b989 100755
--- a/part_2/ex8/db/ex8.cmp.idb
+++ b/part_2/ex8/db/ex8.cmp.idb
diff --git a/part_2/ex8/db/ex8.cmp.logdb b/part_2/ex8/db/ex8.cmp.logdb
index ba5f5be..b69cd55 100755
--- a/part_2/ex8/db/ex8.cmp.logdb
+++ b/part_2/ex8/db/ex8.cmp.logdb
@@ -1,75 +1,75 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000003;IO_000001;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000022;IO_000021;IO_000046;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000047;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
-IO_RULES_MATRIX,Total Pass,0;36;36;0;0;36;36;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;36;36;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,36;0;0;36;36;0;0;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;0;0;36,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,36;0;36;0;0;36;36;0;36;36;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;36;0;36;36;0;0;36;0;0;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36;36,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_2/ex8/db/ex8.cmp.rdb b/part_2/ex8/db/ex8.cmp.rdb
index 59651dc..2035ace 100755
--- a/part_2/ex8/db/ex8.cmp.rdb
+++ b/part_2/ex8/db/ex8.cmp.rdb
diff --git a/part_2/ex8/db/ex8.cmp_merge.kpt b/part_2/ex8/db/ex8.cmp_merge.kpt
index 06da287..214a1dd 100755
--- a/part_2/ex8/db/ex8.cmp_merge.kpt
+++ b/part_2/ex8/db/ex8.cmp_merge.kpt
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
index 826025e..5b115d6 100755
--- a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
index 8ebe269..3a7a497 100755
--- a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
index 8d531ee..aa473fa 100755
--- a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
index 1e5e40e..dce4f6b 100755
--- a/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
+++ b/part_2/ex8/db/ex8.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex8/db/ex8.db_info b/part_2/ex8/db/ex8.db_info
index 00e5756..5713658 100755
--- a/part_2/ex8/db/ex8.db_info
+++ b/part_2/ex8/db/ex8.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Version_Index = 419480576
-Creation_Time = Sun Dec 11 20:04:49 2016
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Wed Dec 07 12:09:52 2016
diff --git a/part_2/ex8/db/ex8.fit.qmsg b/part_2/ex8/db/ex8.fit.qmsg
index f77cc3c..340170b 100755
--- a/part_2/ex8/db/ex8.fit.qmsg
+++ b/part_2/ex8/db/ex8.fit.qmsg
@@ -1,46 +1,45 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481487904510 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481487904510 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481487904517 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481487904547 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481487904547 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481487904907 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481487904925 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481487904980 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481487915708 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481487915784 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481487915784 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487915784 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481487915787 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481487915788 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481487915789 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481487915789 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481487915789 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481487915790 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481487916319 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481487916319 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481487916320 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481487916323 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481487916323 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481487916323 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481487916328 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481487916328 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481487916328 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487916364 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481487916364 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487916365 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481487920695 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481487920887 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487921404 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481487921908 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481487922990 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487922990 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481487923869 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481487928353 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481487928353 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481487931749 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481487931749 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487931751 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.37 " "Total time spent on timing analysis during the Fitter is 0.37 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481487933164 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481487933195 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481487933545 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481487933545 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481487933894 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487935921 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481487936019 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481487936076 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 52 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 52 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2138 " "Peak virtual memory: 2138 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487936446 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:25:36 2016 " "Processing ended: Sun Dec 11 20:25:36 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487936446 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487936446 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:57 " "Total CPU time (on all processors): 00:00:57" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487936446 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481487936446 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481113289327 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481113289328 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481113289716 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481113289786 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481113289787 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481113290194 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481113290376 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481113300447 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481113300524 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481113300524 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113300525 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481113300528 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481113300528 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481113300529 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481113300529 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481113300530 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481113300530 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481113301210 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481113301211 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481113301211 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481113301214 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481113301215 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481113301215 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481113301218 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481113301219 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481113301219 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481113301254 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481113301254 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113301261 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481113306208 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481113306410 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113307023 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481113307561 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481113308475 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113308476 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481113309633 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "H:/GitHub/digital_verilog_coursework/part_2/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481113314203 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481113314203 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481113316533 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481113316533 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113316537 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.44 " "Total time spent on timing analysis during the Fitter is 0.44 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481113318295 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481113318336 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481113318765 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481113318765 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481113319187 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481113321673 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481113321945 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481113322178 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 51 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 51 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2608 " "Peak virtual memory: 2608 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113325553 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:22:05 2016 " "Processing ended: Wed Dec 07 12:22:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113325553 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Elapsed time: 00:00:38" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113325553 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:58 " "Total CPU time (on all processors): 00:00:58" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113325553 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481113325553 ""}
diff --git a/part_2/ex8/db/ex8.hier_info b/part_2/ex8/db/ex8.hier_info
index 2996260..4fd5199 100755
--- a/part_2/ex8/db/ex8.hier_info
+++ b/part_2/ex8/db/ex8.hier_info
@@ -1,679 +1,682 @@
-|ex8
-CLOCK_50 => CLOCK_50.IN2
-KEY[0] => ~NO_FANOUT~
-KEY[1] => ~NO_FANOUT~
-KEY[2] => ~NO_FANOUT~
-KEY[3] => _.IN1
-HEX0[0] << hex_to_7seg:SEG0.port0
-HEX0[1] << hex_to_7seg:SEG0.port0
-HEX0[2] << hex_to_7seg:SEG0.port0
-HEX0[3] << hex_to_7seg:SEG0.port0
-HEX0[4] << hex_to_7seg:SEG0.port0
-HEX0[5] << hex_to_7seg:SEG0.port0
-HEX0[6] << hex_to_7seg:SEG0.port0
-HEX1[0] << hex_to_7seg:SEG1.port0
-HEX1[1] << hex_to_7seg:SEG1.port0
-HEX1[2] << hex_to_7seg:SEG1.port0
-HEX1[3] << hex_to_7seg:SEG1.port0
-HEX1[4] << hex_to_7seg:SEG1.port0
-HEX1[5] << hex_to_7seg:SEG1.port0
-HEX1[6] << hex_to_7seg:SEG1.port0
-HEX2[0] << hex_to_7seg:SEG2.port0
-HEX2[1] << hex_to_7seg:SEG2.port0
-HEX2[2] << hex_to_7seg:SEG2.port0
-HEX2[3] << hex_to_7seg:SEG2.port0
-HEX2[4] << hex_to_7seg:SEG2.port0
-HEX2[5] << hex_to_7seg:SEG2.port0
-HEX2[6] << hex_to_7seg:SEG2.port0
-LEDR[0] << formula_fsm:FSM.port6
-LEDR[1] << formula_fsm:FSM.port6
-LEDR[2] << formula_fsm:FSM.port6
-LEDR[3] << formula_fsm:FSM.port6
-LEDR[4] << formula_fsm:FSM.port6
-LEDR[5] << formula_fsm:FSM.port6
-LEDR[6] << formula_fsm:FSM.port6
-LEDR[7] << formula_fsm:FSM.port6
-LEDR[8] << formula_fsm:FSM.port6
-LEDR[9] << formula_fsm:FSM.port6
-
-
-|ex8|tick_50000:TICK0
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|tick_2500:TICK1
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-en => CLK_OUT.OUTPUTSELECT
-en => count[0].ENA
-en => count[1].ENA
-en => count[2].ENA
-en => count[3].ENA
-en => count[4].ENA
-en => count[5].ENA
-en => count[6].ENA
-en => count[7].ENA
-en => count[8].ENA
-en => count[9].ENA
-en => count[10].ENA
-en => count[11].ENA
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|formula_fsm:FSM
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => ledr[0]~reg0.CLK
-clk => ledr[1]~reg0.CLK
-clk => ledr[2]~reg0.CLK
-clk => ledr[3]~reg0.CLK
-clk => ledr[4]~reg0.CLK
-clk => ledr[5]~reg0.CLK
-clk => ledr[6]~reg0.CLK
-clk => ledr[7]~reg0.CLK
-clk => ledr[8]~reg0.CLK
-clk => ledr[9]~reg0.CLK
-clk => state~3.DATAIN
-tick => ~NO_FANOUT~
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
-start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
-ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|LFSR:LFSR0
-CLK => COUNT[1]~reg0.CLK
-CLK => COUNT[2]~reg0.CLK
-CLK => COUNT[3]~reg0.CLK
-CLK => COUNT[4]~reg0.CLK
-CLK => COUNT[5]~reg0.CLK
-CLK => COUNT[6]~reg0.CLK
-CLK => COUNT[7]~reg0.CLK
-en => COUNT[1]~reg0.ENA
-en => COUNT[2]~reg0.ENA
-en => COUNT[3]~reg0.ENA
-en => COUNT[4]~reg0.ENA
-en => COUNT[5]~reg0.ENA
-en => COUNT[6]~reg0.ENA
-en => COUNT[7]~reg0.ENA
-COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|delay:DEL0
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => count[12].CLK
-clk => count[13].CLK
-clk => state~4.DATAIN
-N[0] => count.DATAB
-N[1] => count.DATAB
-N[2] => count.DATAB
-N[3] => count.DATAB
-N[4] => count.DATAB
-N[5] => count.DATAB
-N[6] => count.DATAB
-N[7] => ~NO_FANOUT~
-N[8] => ~NO_FANOUT~
-N[9] => ~NO_FANOUT~
-N[10] => ~NO_FANOUT~
-N[11] => ~NO_FANOUT~
-N[12] => ~NO_FANOUT~
-N[13] => ~NO_FANOUT~
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector17.IN3
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector14.IN2
-time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD
-B[0] => BCD_0[0].DATAIN
-B[1] => w35[0].IN1
-B[2] => w30[0].IN1
-B[3] => w26[0].IN1
-B[4] => w22[0].IN1
-B[5] => w18[0].IN1
-B[6] => w15[0].IN1
-B[7] => w12[0].IN1
-B[8] => w9[0].IN1
-B[9] => w7[0].IN1
-B[10] => w5[0].IN1
-B[11] => w3[0].IN1
-B[12] => w2[0].IN1
-B[13] => w1[0].IN1
-B[14] => w1[1].IN1
-B[15] => w1[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A35.port1
-BCD_0[2] <= add3_ge5:A35.port1
-BCD_0[3] <= add3_ge5:A35.port1
-BCD_1[0] <= add3_ge5:A35.port1
-BCD_1[1] <= add3_ge5:A34.port1
-BCD_1[2] <= add3_ge5:A34.port1
-BCD_1[3] <= add3_ge5:A34.port1
-BCD_2[0] <= add3_ge5:A34.port1
-BCD_2[1] <= add3_ge5:A33.port1
-BCD_2[2] <= add3_ge5:A33.port1
-BCD_2[3] <= add3_ge5:A33.port1
-BCD_3[0] <= add3_ge5:A33.port1
-BCD_3[1] <= add3_ge5:A32.port1
-BCD_3[2] <= add3_ge5:A32.port1
-BCD_3[3] <= add3_ge5:A32.port1
-BCD_4[0] <= add3_ge5:A32.port1
-BCD_4[1] <= add3_ge5:A31.port1
-BCD_4[2] <= add3_ge5:A31.port1
-BCD_4[3] <= add3_ge5:A31.port1
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A1
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A2
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A3
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A4
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A5
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A6
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A7
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A8
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A9
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A10
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A11
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A12
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A13
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A14
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A15
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A16
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A17
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A18
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A19
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A20
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A21
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A22
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A23
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A24
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A25
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A26
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A27
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A28
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A29
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A30
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A31
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A32
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A33
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A34
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|bin2bcd_16:BCD|add3_ge5:A35
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex8|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex8|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex8|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
+|ex8
+CLOCK_50 => CLOCK_50.IN2
+KEY[0] => ~NO_FANOUT~
+KEY[1] => ~NO_FANOUT~
+KEY[2] => ~NO_FANOUT~
+KEY[3] => _.IN1
+HEX0[0] <= hex_to_7seg:SEG0.port0
+HEX0[1] <= hex_to_7seg:SEG0.port0
+HEX0[2] <= hex_to_7seg:SEG0.port0
+HEX0[3] <= hex_to_7seg:SEG0.port0
+HEX0[4] <= hex_to_7seg:SEG0.port0
+HEX0[5] <= hex_to_7seg:SEG0.port0
+HEX0[6] <= hex_to_7seg:SEG0.port0
+HEX1[0] <= hex_to_7seg:SEG1.port0
+HEX1[1] <= hex_to_7seg:SEG1.port0
+HEX1[2] <= hex_to_7seg:SEG1.port0
+HEX1[3] <= hex_to_7seg:SEG1.port0
+HEX1[4] <= hex_to_7seg:SEG1.port0
+HEX1[5] <= hex_to_7seg:SEG1.port0
+HEX1[6] <= hex_to_7seg:SEG1.port0
+HEX2[0] <= hex_to_7seg:SEG2.port0
+HEX2[1] <= hex_to_7seg:SEG2.port0
+HEX2[2] <= hex_to_7seg:SEG2.port0
+HEX2[3] <= hex_to_7seg:SEG2.port0
+HEX2[4] <= hex_to_7seg:SEG2.port0
+HEX2[5] <= hex_to_7seg:SEG2.port0
+HEX2[6] <= hex_to_7seg:SEG2.port0
+LEDR[0] <= formula_fsm:FSM.port6
+LEDR[1] <= formula_fsm:FSM.port6
+LEDR[2] <= formula_fsm:FSM.port6
+LEDR[3] <= formula_fsm:FSM.port6
+LEDR[4] <= formula_fsm:FSM.port6
+LEDR[5] <= formula_fsm:FSM.port6
+LEDR[6] <= formula_fsm:FSM.port6
+LEDR[7] <= formula_fsm:FSM.port6
+LEDR[8] <= formula_fsm:FSM.port6
+LEDR[9] <= formula_fsm:FSM.port6
+
+
+|ex8|tick_50000:TICK0
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|tick_2500:TICK1
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+en => CLK_OUT.OUTPUTSELECT
+en => count[0].ENA
+en => count[1].ENA
+en => count[2].ENA
+en => count[3].ENA
+en => count[4].ENA
+en => count[5].ENA
+en => count[6].ENA
+en => count[7].ENA
+en => count[8].ENA
+en => count[9].ENA
+en => count[10].ENA
+en => count[11].ENA
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|formula_fsm:FSM
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => count[10].CLK
+clk => count[11].CLK
+clk => ledr[0]~reg0.CLK
+clk => ledr[1]~reg0.CLK
+clk => ledr[2]~reg0.CLK
+clk => ledr[3]~reg0.CLK
+clk => ledr[4]~reg0.CLK
+clk => ledr[5]~reg0.CLK
+clk => ledr[6]~reg0.CLK
+clk => ledr[7]~reg0.CLK
+clk => ledr[8]~reg0.CLK
+clk => ledr[9]~reg0.CLK
+clk => state~3.DATAIN
+tick => ~NO_FANOUT~
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|LFSR:LFSR0
+CLK => COUNT[1]~reg0.CLK
+CLK => COUNT[2]~reg0.CLK
+CLK => COUNT[3]~reg0.CLK
+CLK => COUNT[4]~reg0.CLK
+CLK => COUNT[5]~reg0.CLK
+CLK => COUNT[6]~reg0.CLK
+CLK => COUNT[7]~reg0.CLK
+en => COUNT[1]~reg0.ENA
+en => COUNT[2]~reg0.ENA
+en => COUNT[3]~reg0.ENA
+en => COUNT[4]~reg0.ENA
+en => COUNT[5]~reg0.ENA
+en => COUNT[6]~reg0.ENA
+en => COUNT[7]~reg0.ENA
+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|delay:DEL0
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => count[10].CLK
+clk => count[11].CLK
+clk => count[12].CLK
+clk => count[13].CLK
+clk => state~4.DATAIN
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => ~NO_FANOUT~
+N[8] => ~NO_FANOUT~
+N[9] => ~NO_FANOUT~
+N[10] => ~NO_FANOUT~
+N[11] => ~NO_FANOUT~
+N[12] => ~NO_FANOUT~
+N[13] => ~NO_FANOUT~
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector17.IN3
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector14.IN2
+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD
+B[0] => BCD_0[0].DATAIN
+B[1] => w35[0].IN1
+B[2] => w30[0].IN1
+B[3] => w26[0].IN1
+B[4] => w22[0].IN1
+B[5] => w18[0].IN1
+B[6] => w15[0].IN1
+B[7] => w12[0].IN1
+B[8] => w9[0].IN1
+B[9] => w7[0].IN1
+B[10] => w5[0].IN1
+B[11] => w3[0].IN1
+B[12] => w2[0].IN1
+B[13] => w1[0].IN1
+B[14] => w1[1].IN1
+B[15] => w1[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A35.port1
+BCD_0[2] <= add3_ge5:A35.port1
+BCD_0[3] <= add3_ge5:A35.port1
+BCD_1[0] <= add3_ge5:A35.port1
+BCD_1[1] <= add3_ge5:A34.port1
+BCD_1[2] <= add3_ge5:A34.port1
+BCD_1[3] <= add3_ge5:A34.port1
+BCD_2[0] <= add3_ge5:A34.port1
+BCD_2[1] <= add3_ge5:A33.port1
+BCD_2[2] <= add3_ge5:A33.port1
+BCD_2[3] <= add3_ge5:A33.port1
+BCD_3[0] <= add3_ge5:A33.port1
+BCD_3[1] <= add3_ge5:A32.port1
+BCD_3[2] <= add3_ge5:A32.port1
+BCD_3[3] <= add3_ge5:A32.port1
+BCD_4[0] <= add3_ge5:A32.port1
+BCD_4[1] <= add3_ge5:A31.port1
+BCD_4[2] <= add3_ge5:A31.port1
+BCD_4[3] <= add3_ge5:A31.port1
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A1
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A2
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A3
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A4
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A5
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A6
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A7
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A8
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A9
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A10
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A11
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A12
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A13
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A14
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A15
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A16
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A17
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A18
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A19
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A20
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A21
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A22
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A23
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A24
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A25
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A26
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A27
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A28
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A29
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A30
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A31
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A32
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A33
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A34
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|bin2bcd_16:BCD|add3_ge5:A35
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex8|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex8|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex8|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_2/ex8/db/ex8.hif b/part_2/ex8/db/ex8.hif
index 4e2955c..e8d44fd 100755
--- a/part_2/ex8/db/ex8.hif
+++ b/part_2/ex8/db/ex8.hif
diff --git a/part_2/ex8/db/ex8.lpc.html b/part_2/ex8/db/ex8.lpc.html
index ca68812..deaeb7d 100755
--- a/part_2/ex8/db/ex8.lpc.html
+++ b/part_2/ex8/db/ex8.lpc.html
@@ -1,722 +1,722 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >SEG2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A35</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A34</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A33</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A32</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A31</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A30</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A29</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A28</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A27</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A26</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A25</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A24</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A23</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A22</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A21</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A20</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A19</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A18</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A17</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A16</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A15</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A14</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A13</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A12</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A11</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A10</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A9</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A8</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A7</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A6</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A5</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A4</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD</TD>
-<TD >16</TD>
-<TD >9</TD>
-<TD >0</TD>
-<TD >9</TD>
-<TD >20</TD>
-<TD >9</TD>
-<TD >9</TD>
-<TD >9</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >DEL0</TD>
-<TD >16</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >1</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >LFSR0</TD>
-<TD >2</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >FSM</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >12</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >TICK1</TD>
-<TD >2</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >TICK0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A35</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A34</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A33</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A32</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A31</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A30</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A29</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A28</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A27</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A26</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A19</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A18</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A10</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A9</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A4</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD</TD>
+<TD >16</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >9</TD>
+<TD >20</TD>
+<TD >9</TD>
+<TD >9</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >DEL0</TD>
+<TD >16</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >1</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >LFSR0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >FSM</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >TICK1</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >TICK0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_2/ex8/db/ex8.lpc.rdb b/part_2/ex8/db/ex8.lpc.rdb
index 99d82ad..c015e5f 100755
--- a/part_2/ex8/db/ex8.lpc.rdb
+++ b/part_2/ex8/db/ex8.lpc.rdb
diff --git a/part_2/ex8/db/ex8.lpc.txt b/part_2/ex8/db/ex8.lpc.txt
index c5b5022..1eae4bb 100755
--- a/part_2/ex8/db/ex8.lpc.txt
+++ b/part_2/ex8/db/ex8.lpc.txt
@@ -1,50 +1,50 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD       ; 16    ; 9              ; 0            ; 9              ; 20     ; 9               ; 9             ; 9               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; FSM       ; 4     ; 0              ; 1            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; TICK1     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD       ; 16    ; 9              ; 0            ; 9              ; 20     ; 9               ; 9             ; 9               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; FSM       ; 4     ; 0              ; 1            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; TICK1     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex8/db/ex8.map.ammdb b/part_2/ex8/db/ex8.map.ammdb
index a4afc79..174eb00 100755
--- a/part_2/ex8/db/ex8.map.ammdb
+++ b/part_2/ex8/db/ex8.map.ammdb
diff --git a/part_2/ex8/db/ex8.map.bpm b/part_2/ex8/db/ex8.map.bpm
index fcdf140..909f07b 100755
--- a/part_2/ex8/db/ex8.map.bpm
+++ b/part_2/ex8/db/ex8.map.bpm
diff --git a/part_2/ex8/db/ex8.map.cdb b/part_2/ex8/db/ex8.map.cdb
index 417692e..1e91d4a 100755
--- a/part_2/ex8/db/ex8.map.cdb
+++ b/part_2/ex8/db/ex8.map.cdb
diff --git a/part_2/ex8/db/ex8.map.hdb b/part_2/ex8/db/ex8.map.hdb
index 51bd19b..68c0470 100755
--- a/part_2/ex8/db/ex8.map.hdb
+++ b/part_2/ex8/db/ex8.map.hdb
diff --git a/part_2/ex8/db/ex8.map.kpt b/part_2/ex8/db/ex8.map.kpt
index bd5a8c6..6dedea4 100755
--- a/part_2/ex8/db/ex8.map.kpt
+++ b/part_2/ex8/db/ex8.map.kpt
diff --git a/part_2/ex8/db/ex8.map.logdb b/part_2/ex8/db/ex8.map.logdb
index 626799f..d45424f 100755
--- a/part_2/ex8/db/ex8.map.logdb
+++ b/part_2/ex8/db/ex8.map.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex8/db/ex8.map.qmsg b/part_2/ex8/db/ex8.map.qmsg
index ff3a9e9..687e014 100755
--- a/part_2/ex8/db/ex8.map.qmsg
+++ b/part_2/ex8/db/ex8.map.qmsg
@@ -1,74 +1,74 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481487894025 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487894033 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:24:53 2016 " "Processing started: Sun Dec 11 20:24:53 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487894033 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487894033 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487894033 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481487894281 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481487894281 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902862 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902862 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/LFSR.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902863 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902863 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902864 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902864 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902864 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902864 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902865 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902865 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902866 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902867 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902867 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902867 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481487902868 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902868 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902868 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487902869 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902869 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902869 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902870 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902870 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487902870 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902870 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481487902915 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex8.v" "TICK0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902917 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" {  } { { "verilog_files/ex8.v" "TICK1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902918 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex8.v" "FSM" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902919 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481487902920 "|ex8|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481487902920 "|ex8|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487902921 "|ex8|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex8.v" "LFSR0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902928 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex8.v" "DEL0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902929 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481487902929 "|ex8|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex8.v" "BCD" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902930 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902931 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex8.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487902939 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481487903244 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487903286 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487903286 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Pin \"HEX2\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487903286 "|ex8|HEX2[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481487903286 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481487903337 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481487903471 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487903489 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481487903556 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487903556 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487903594 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487903594 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487903594 "|ex8|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481487903594 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "178 " "Implemented 178 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481487903595 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481487903595 ""} { "Info" "ICUT_CUT_TM_LCELLS" "142 " "Implemented 142 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481487903595 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481487903595 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1054 " "Peak virtual memory: 1054 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487903602 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:25:03 2016 " "Processing ended: Sun Dec 11 20:25:03 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487903602 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487903602 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487903602 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487903602 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481113272271 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481113272275 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:21:11 2016 " "Processing started: Wed Dec 07 12:21:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481113272275 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113272275 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113272275 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481113272802 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481113272803 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281367 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281367 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281372 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281372 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281377 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281377 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281382 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281382 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281388 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281396 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281399 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281399 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281399 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281400 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281401 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281402 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281403 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281403 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281403 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281403 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281403 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281408 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281408 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481113281419 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281420 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281420 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113281425 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281425 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281425 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281433 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281433 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" {  } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113281437 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281437 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481113281536 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex8.v" "TICK0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281573 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" {  } { { "verilog_files/ex8.v" "TICK1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281579 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex8.v" "FSM" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281584 ""}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481113281586 "|ex8|formula_fsm:FSM"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481113281586 "|ex8|formula_fsm:FSM"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113281586 "|ex8|formula_fsm:FSM"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex8.v" "LFSR0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281616 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex8.v" "DEL0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281621 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481113281626 "|ex8|delay:comb_8"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex8.v" "BCD" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281627 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281633 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex8.v" "SEG0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113281642 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481113282426 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481113282524 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481113282524 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Pin \"HEX2\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481113282524 "|ex8|HEX2[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481113282524 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481113282602 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481113282980 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113283089 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481113283663 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481113283663 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" {  } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481113284041 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481113284041 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481113284041 "|ex8|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481113284041 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "184 " "Implemented 184 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481113284046 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481113284046 ""} { "Info" "ICUT_CUT_TM_LCELLS" "148 " "Implemented 148 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481113284046 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481113284046 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113284242 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:21:24 2016 " "Processing ended: Wed Dec 07 12:21:24 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113284242 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113284242 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113284242 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113284242 ""}
diff --git a/part_2/ex8/db/ex8.map.rdb b/part_2/ex8/db/ex8.map.rdb
index c16f519..95ea26b 100755
--- a/part_2/ex8/db/ex8.map.rdb
+++ b/part_2/ex8/db/ex8.map.rdb
diff --git a/part_2/ex8/db/ex8.map_bb.cdb b/part_2/ex8/db/ex8.map_bb.cdb
index 7d8d82c..7530825 100755
--- a/part_2/ex8/db/ex8.map_bb.cdb
+++ b/part_2/ex8/db/ex8.map_bb.cdb
diff --git a/part_2/ex8/db/ex8.map_bb.hdb b/part_2/ex8/db/ex8.map_bb.hdb
index 63b4a90..f30501a 100755
--- a/part_2/ex8/db/ex8.map_bb.hdb
+++ b/part_2/ex8/db/ex8.map_bb.hdb
diff --git a/part_2/ex8/db/ex8.map_bb.logdb b/part_2/ex8/db/ex8.map_bb.logdb
index 626799f..d45424f 100755
--- a/part_2/ex8/db/ex8.map_bb.logdb
+++ b/part_2/ex8/db/ex8.map_bb.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex8/db/ex8.pre_map.cdb b/part_2/ex8/db/ex8.pre_map.cdb
new file mode 100755
index 0000000..7e3e287
--- /dev/null
+++ b/part_2/ex8/db/ex8.pre_map.cdb
diff --git a/part_2/ex8/db/ex8.pre_map.hdb b/part_2/ex8/db/ex8.pre_map.hdb
index d0a76ab..caf9ee5 100755
--- a/part_2/ex8/db/ex8.pre_map.hdb
+++ b/part_2/ex8/db/ex8.pre_map.hdb
diff --git a/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb b/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
index 7a1d4da..8818b3a 100755
--- a/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
+++ b/part_2/ex8/db/ex8.root_partition.map.reg_db.cdb
diff --git a/part_2/ex8/db/ex8.routing.rdb b/part_2/ex8/db/ex8.routing.rdb
index f425873..6bc3097 100755
--- a/part_2/ex8/db/ex8.routing.rdb
+++ b/part_2/ex8/db/ex8.routing.rdb
diff --git a/part_2/ex8/db/ex8.rtlv.hdb b/part_2/ex8/db/ex8.rtlv.hdb
index 724866d..ba43d17 100755
--- a/part_2/ex8/db/ex8.rtlv.hdb
+++ b/part_2/ex8/db/ex8.rtlv.hdb
diff --git a/part_2/ex8/db/ex8.rtlv_sg.cdb b/part_2/ex8/db/ex8.rtlv_sg.cdb
index 7d4f463..0ee2c0b 100755
--- a/part_2/ex8/db/ex8.rtlv_sg.cdb
+++ b/part_2/ex8/db/ex8.rtlv_sg.cdb
diff --git a/part_2/ex8/db/ex8.rtlv_sg_swap.cdb b/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
index e5bd34b..ed8d69c 100755
--- a/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
+++ b/part_2/ex8/db/ex8.rtlv_sg_swap.cdb
diff --git a/part_2/ex8/db/ex8.sld_design_entry.sci b/part_2/ex8/db/ex8.sld_design_entry.sci
index 03eacdc..92c1102 100755
--- a/part_2/ex8/db/ex8.sld_design_entry.sci
+++ b/part_2/ex8/db/ex8.sld_design_entry.sci
diff --git a/part_2/ex8/db/ex8.sld_design_entry_dsc.sci b/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
index 03eacdc..92c1102 100755
--- a/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
+++ b/part_2/ex8/db/ex8.sld_design_entry_dsc.sci
diff --git a/part_2/ex8/db/ex8.smart_action.txt b/part_2/ex8/db/ex8.smart_action.txt
index c8e8a13..437a63e 100755
--- a/part_2/ex8/db/ex8.smart_action.txt
+++ b/part_2/ex8/db/ex8.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/part_2/ex8/db/ex8.smp_dump.txt b/part_2/ex8/db/ex8.smp_dump.txt
index 05f4abe..04f2111 100755
--- a/part_2/ex8/db/ex8.smp_dump.txt
+++ b/part_2/ex8/db/ex8.smp_dump.txt
@@ -1,13 +1,13 @@
-
-State Machine - |ex8|delay:DEL0|state
-Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 
-state.IDLE 0 0 0 0 
-state.COUNTING 0 0 1 1 
-state.TIME_OUT 0 1 0 1 
-state.WAIT_LOW 1 0 0 1 
-
-State Machine - |ex8|formula_fsm:FSM|state
-Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 
-state.WAIT_TRIGGER 0 0 0 
-state.LIGHT_UP_LEDS 1 0 1 
-state.WAIT_FOR_TIMEOUT 1 1 0 
+
+State Machine - |ex8|delay:DEL0|state
+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 
+state.IDLE 0 0 0 0 
+state.COUNTING 0 0 1 1 
+state.TIME_OUT 0 1 0 1 
+state.WAIT_LOW 1 0 0 1 
+
+State Machine - |ex8|formula_fsm:FSM|state
+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 
+state.WAIT_TRIGGER 0 0 0 
+state.LIGHT_UP_LEDS 1 0 1 
+state.WAIT_FOR_TIMEOUT 1 1 0 
diff --git a/part_2/ex8/db/ex8.sta.qmsg b/part_2/ex8/db/ex8.sta.qmsg
index 2d589df..b2592ab 100755
--- a/part_2/ex8/db/ex8.sta.qmsg
+++ b/part_2/ex8/db/ex8.sta.qmsg
@@ -1,53 +1,53 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481487944063 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487944068 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:25:43 2016 " "Processing started: Sun Dec 11 20:25:43 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487944068 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944068 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944069 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487944110 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944645 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944645 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944673 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487944674 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945136 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945151 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945152 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487945153 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487945153 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487945153 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945153 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945154 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945159 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487945159 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487945164 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487945179 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945179 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.968 " "Worst-case setup slack is -2.968" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.968            -107.976 tick_50000:TICK0\|CLK_OUT  " "   -2.968            -107.976 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.534             -41.925 CLOCK_50  " "   -2.534             -41.925 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.603              -1.603 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.603              -1.603 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945180 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945180 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.203 " "Worst-case hold slack is 0.203" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.203               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.203               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.384               0.000 CLOCK_50  " "    0.384               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.419               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.419               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945181 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945181 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945182 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945182 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.643 " "Worst-case minimum pulse width slack is -0.643" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.643             -16.740 CLOCK_50  " "   -0.643             -16.740 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -26.810 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -26.810 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.357               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.357               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487945183 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945183 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487945189 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945217 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487945990 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946064 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487946069 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946069 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.963 " "Worst-case setup slack is -2.963" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.963            -106.734 tick_50000:TICK0\|CLK_OUT  " "   -2.963            -106.734 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.784             -42.820 CLOCK_50  " "   -2.784             -42.820 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.493              -1.493 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.493              -1.493 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946069 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946069 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.233 " "Worst-case hold slack is 0.233" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.233               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.233               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.302               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.302               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.406               0.000 CLOCK_50  " "    0.406               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946071 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946071 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946072 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946072 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.717 " "Worst-case minimum pulse width slack is -0.717" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.717             -15.605 CLOCK_50  " "   -0.717             -15.605 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -26.816 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -26.816 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.396               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.396               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946073 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946073 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487946079 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946211 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946858 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946927 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487946928 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946928 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.503 " "Worst-case setup slack is -1.503" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.503             -52.250 tick_50000:TICK0\|CLK_OUT  " "   -1.503             -52.250 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.304             -15.219 CLOCK_50  " "   -1.304             -15.219 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.568              -0.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.568              -0.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946929 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946929 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.034 " "Worst-case hold slack is -0.034" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.034              -0.067 tick_50000:TICK0\|CLK_OUT  " "   -0.034              -0.067 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.057               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.057               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 CLOCK_50  " "    0.185               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946931 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946931 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946933 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946934 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.786 " "Worst-case minimum pulse width slack is -0.786" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.786             -12.110 CLOCK_50  " "   -0.786             -12.110 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.065               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.065               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.369               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.369               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487946934 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487946934 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487946941 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947080 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487947081 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947081 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.311 " "Worst-case setup slack is -1.311" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.311             -45.679 tick_50000:TICK0\|CLK_OUT  " "   -1.311             -45.679 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.229             -13.104 CLOCK_50  " "   -1.229             -13.104 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.445              -0.445 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.445              -0.445 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947082 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947082 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.034 " "Worst-case hold slack is -0.034" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.034              -0.067 tick_50000:TICK0\|CLK_OUT  " "   -0.034              -0.067 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.014              -0.014 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.014              -0.014 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947083 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947083 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947084 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947085 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.844 " "Worst-case minimum pulse width slack is -0.844" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.844             -14.423 CLOCK_50  " "   -0.844             -14.423 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.081               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.081               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.396               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.396               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487947085 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487947085 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487948344 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487948344 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1214 " "Peak virtual memory: 1214 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487948372 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:25:48 2016 " "Processing ended: Sun Dec 11 20:25:48 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487948372 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487948372 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487948372 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487948372 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481113342093 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481113342095 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:22:21 2016 " "Processing started: Wed Dec 07 12:22:21 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481113342095 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113342095 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113342095 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113342229 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113342955 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113342955 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343007 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343007 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343557 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343669 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343670 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481113343672 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481113343672 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481113343672 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343672 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343678 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343697 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113343698 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113343778 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481113343812 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343812 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.351 " "Worst-case setup slack is -3.351" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.351            -141.123 tick_50000:TICK0\|CLK_OUT  " "   -3.351            -141.123 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.370             -46.721 CLOCK_50  " "   -2.370             -46.721 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.669              -1.669 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.669              -1.669 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343838 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343838 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.287 " "Worst-case hold slack is 0.287" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.287               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.287               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.375               0.000 CLOCK_50  " "    0.375               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.603               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.603               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343875 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343875 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343922 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343945 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.655 " "Worst-case minimum pulse width slack is -0.655" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.655             -20.255 CLOCK_50  " "   -0.655             -20.255 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -31.614 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -31.614 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.435               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.435               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113343968 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113343968 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113344049 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113344098 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345078 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345313 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481113345356 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345356 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.267 " "Worst-case setup slack is -3.267" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.267            -138.732 tick_50000:TICK0\|CLK_OUT  " "   -3.267            -138.732 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.588             -48.020 CLOCK_50  " "   -2.588             -48.020 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.583              -1.583 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.583              -1.583 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345389 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345389 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.289 " "Worst-case hold slack is 0.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.289               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.289               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.391               0.000 CLOCK_50  " "    0.391               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.463               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.463               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345410 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345410 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345427 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345446 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.714 " "Worst-case minimum pulse width slack is -0.714" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.714             -18.725 CLOCK_50  " "   -0.714             -18.725 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -30.708 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -30.708 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.391               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.391               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113345465 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345465 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113345570 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113345953 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113346861 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113346985 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481113346987 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113346987 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.909 " "Worst-case setup slack is -1.909" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.909             -72.643 tick_50000:TICK0\|CLK_OUT  " "   -1.909             -72.643 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.138             -16.318 CLOCK_50  " "   -1.138             -16.318 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.609              -0.609 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.609              -0.609 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347001 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347001 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.048 " "Worst-case hold slack is 0.048" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.048               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.048               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.181               0.000 CLOCK_50  " "    0.181               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.219               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.219               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347016 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347016 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347032 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347053 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.779 " "Worst-case minimum pulse width slack is -0.779" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.779             -14.378 CLOCK_50  " "   -0.779             -14.378 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.014              -0.134 tick_50000:TICK0\|CLK_OUT  " "   -0.014              -0.134 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347115 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347115 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481113347179 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347594 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481113347597 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347597 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.657 " "Worst-case setup slack is -1.657" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.657             -63.529 tick_50000:TICK0\|CLK_OUT  " "   -1.657             -63.529 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.092             -13.791 CLOCK_50  " "   -1.092             -13.791 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.488              -0.488 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.488              -0.488 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347648 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347648 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.013 " "Worst-case hold slack is 0.013" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.013               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.013               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.128               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.128               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.171               0.000 CLOCK_50  " "    0.171               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347667 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347667 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347684 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347701 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.829 " "Worst-case minimum pulse width slack is -0.829" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.829             -17.064 CLOCK_50  " "   -0.829             -17.064 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.025               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.025               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.460               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.460               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481113347717 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113347717 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113350193 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113350195 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1209 " "Peak virtual memory: 1209 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113350528 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:22:30 2016 " "Processing ended: Wed Dec 07 12:22:30 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113350528 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113350528 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113350528 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481113350528 ""}
diff --git a/part_2/ex8/db/ex8.sta.rdb b/part_2/ex8/db/ex8.sta.rdb
index 259c48b..97d602f 100755
--- a/part_2/ex8/db/ex8.sta.rdb
+++ b/part_2/ex8/db/ex8.sta.rdb
diff --git a/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
index eaaa80a..e20c7c2 100755
--- a/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
+++ b/part_2/ex8/db/ex8.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex8/db/ex8.tis_db_list.ddb b/part_2/ex8/db/ex8.tis_db_list.ddb
index 2df45d7..88225e8 100755
--- a/part_2/ex8/db/ex8.tis_db_list.ddb
+++ b/part_2/ex8/db/ex8.tis_db_list.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
index 6f4c35a..3485514 100755
--- a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
+++ b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
index 06bb7a7..e7e3c75 100755
--- a/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
+++ b/part_2/ex8/db/ex8.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
index 77e6657..4c6cdc1 100755
--- a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
+++ b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
index e4e6026..0f83314 100755
--- a/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
+++ b/part_2/ex8/db/ex8.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex8/db/ex8.tmw_info b/part_2/ex8/db/ex8.tmw_info
index 7c14f97..9b49b2f 100755
--- a/part_2/ex8/db/ex8.tmw_info
+++ b/part_2/ex8/db/ex8.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:00:55
-start_analysis_synthesis:s:00:00:10-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:33-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
-start_timing_analyzer:s:00:00:05-start_full_compilation
+start_full_compilation:s:00:01:22
+start_analysis_synthesis:s:00:00:17-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:43-start_full_compilation
+start_assembler:s:00:00:11-start_full_compilation
+start_timing_analyzer:s:00:00:11-start_full_compilation
diff --git a/part_2/ex8/db/ex8.vpr.ammdb b/part_2/ex8/db/ex8.vpr.ammdb
index 1232dc3..7636fff 100755
--- a/part_2/ex8/db/ex8.vpr.ammdb
+++ b/part_2/ex8/db/ex8.vpr.ammdb
diff --git a/part_2/ex8/db/ex8_partition_pins.json b/part_2/ex8/db/ex8_partition_pins.json
index 677a906..ad28bfb 100755
--- a/part_2/ex8/db/ex8_partition_pins.json
+++ b/part_2/ex8/db/ex8_partition_pins.json
@@ -1,129 +1,129 @@
-{
-	"partitions" : [
-		{
-			"name" : "Top",
-			"pins" : [
-				{
-					"name" : "HEX0[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[5]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[0]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[1]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[2]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[3]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[4]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[5]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[6]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[7]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[8]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[9]",
-					"strict" : false
-				},
-				{
-					"name" : "KEY[3]",
-					"strict" : false
-				},
-				{
-					"name" : "CLOCK_50",
-					"strict" : false
-				}
-			]
-		}
-	]
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[0]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[1]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[2]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[3]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[4]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[5]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[6]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[7]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[8]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[9]",
+					"strict" : false
+				},
+				{
+					"name" : "KEY[3]",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				}
+			]
+		}
+	]
 }
 \ No newline at end of file
diff --git a/part_2/ex8/db/prev_cmp_ex8.qmsg b/part_2/ex8/db/prev_cmp_ex8.qmsg
index 08aed7e..7ea8680 100755
--- a/part_2/ex8/db/prev_cmp_ex8.qmsg
+++ b/part_2/ex8/db/prev_cmp_ex8.qmsg
@@ -1,189 +1,59 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481487062604 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487062611 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:11:02 2016 " "Processing started: Sun Dec 11 20:11:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487062611 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487062611 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487062612 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481487062858 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481487062858 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071574 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071574 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/LFSR.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071575 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071575 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071575 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071575 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071576 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071576 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071577 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071578 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071578 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071579 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071579 ""}
-{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "8 formula_fsm.v(47) " "Verilog HDL Expression warning at formula_fsm.v(47): truncated literal to match 8 bits" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1481487071579 ""}
-{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "8 formula_fsm.v(54) " "Verilog HDL Expression warning at formula_fsm.v(54): truncated literal to match 8 bits" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 54 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1481487071579 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481487071579 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071580 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071580 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481487071580 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071580 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071580 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071581 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071581 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481487071582 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071582 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex8 " "Elaborating entity \"ex8\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481487071635 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex8.v" "TICK0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 13 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071637 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" {  } { { "verilog_files/ex8.v" "TICK1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071638 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex8.v" "FSM" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071639 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481487071640 "|ex8|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481487071640 "|ex8|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487071641 "|ex8|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex8.v" "LFSR0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071648 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex8.v" "DEL0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071649 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481487071650 "|ex8|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex8.v" "BCD" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071650 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071651 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex8.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487071659 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481487071976 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487072030 "|ex8|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] GND " "Pin \"HEX2\[2\]\" is stuck at GND" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487072030 "|ex8|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[6\] VCC " "Pin \"HEX2\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481487072030 "|ex8|HEX2[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481487072030 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481487072086 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481487072222 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487072241 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481487072309 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481487072309 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487072347 "|ex8|KEY[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487072347 "|ex8|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex8.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481487072347 "|ex8|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481487072347 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "176 " "Implemented 176 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481487072348 ""} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Implemented 31 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481487072348 ""} { "Info" "ICUT_CUT_TM_LCELLS" "140 " "Implemented 140 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481487072348 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481487072348 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1050 " "Peak virtual memory: 1050 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487072355 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:11:12 2016 " "Processing ended: Sun Dec 11 20:11:12 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487072355 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487072355 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487072355 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481487072355 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1481487073099 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487073104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:11:12 2016 " "Processing started: Sun Dec 11 20:11:12 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487073104 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1481487073104 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1481487073105 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1481487073150 ""}
-{ "Info" "0" "" "Project  = ex8" {  } {  } 0 0 "Project  = ex8" 0 0 "Fitter" 0 0 1481487073151 ""}
-{ "Info" "0" "" "Revision = ex8" {  } {  } 0 0 "Revision = ex8" 0 0 "Fitter" 0 0 1481487073151 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481487073247 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481487073247 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex8 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex8\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481487073251 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481487073277 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481487073277 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481487073638 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481487073655 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481487073712 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481487084449 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481487084525 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481487084525 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487084525 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481487084528 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481487084528 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481487084529 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481487084530 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481487084530 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481487084530 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481487085060 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481487085061 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481487085061 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481487085064 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481487085064 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481487085065 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481487085069 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481487085070 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481487085070 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481487085106 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481487085106 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487085108 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481487089399 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481487089589 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487090058 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481487090520 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481487091660 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487091660 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481487092540 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481487097058 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481487097058 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481487098971 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481487098971 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487098973 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.36 " "Total time spent on timing analysis during the Fitter is 0.36 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481487100387 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481487100421 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481487100765 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481487100765 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481487101119 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481487103102 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481487103203 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481487103258 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 52 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 52 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2132 " "Peak virtual memory: 2132 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487103623 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:11:43 2016 " "Processing ended: Sun Dec 11 20:11:43 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487103623 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Elapsed time: 00:00:31" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487103623 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:51 " "Total CPU time (on all processors): 00:00:51" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487103623 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481487103623 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1481487104690 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487104697 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:11:44 2016 " "Processing started: Sun Dec 11 20:11:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487104697 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481487104697 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481487104697 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481487105322 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481487110230 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "977 " "Peak virtual memory: 977 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487110573 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:11:50 2016 " "Processing ended: Sun Dec 11 20:11:50 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487110573 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487110573 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487110573 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481487110573 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1481487110702 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1481487111307 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481487111312 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:11:51 2016 " "Processing started: Sun Dec 11 20:11:51 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481487111312 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111312 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex8 -c ex8 " "Command: quartus_sta ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111312 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487111354 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111864 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111864 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111891 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487111891 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112389 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex8.sdc " "Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112406 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112406 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487112408 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487112408 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481487112408 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112408 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112409 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112414 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487112415 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487112419 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487112433 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112433 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.776 " "Worst-case setup slack is -2.776" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.776            -103.897 tick_50000:TICK0\|CLK_OUT  " "   -2.776            -103.897 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.523             -37.773 CLOCK_50  " "   -2.523             -37.773 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.483              -1.483 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.483              -1.483 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112434 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112434 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.279 " "Worst-case hold slack is 0.279" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.279               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.279               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.382               0.000 CLOCK_50  " "    0.382               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.405               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.405               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112436 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112436 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112436 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112437 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.630 " "Worst-case minimum pulse width slack is -0.630" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.630             -15.485 CLOCK_50  " "   -0.630             -15.485 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -26.353 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -26.353 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.450               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.450               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487112437 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112437 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487112444 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487112471 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113253 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113316 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487113320 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113320 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.772 " "Worst-case setup slack is -2.772" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.772            -102.400 tick_50000:TICK0\|CLK_OUT  " "   -2.772            -102.400 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.763             -38.066 CLOCK_50  " "   -2.763             -38.066 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.393              -1.393 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.393              -1.393 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113321 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113321 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.281 " "Worst-case hold slack is 0.281" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.281               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.281               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.281               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.281               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.404               0.000 CLOCK_50  " "    0.404               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113322 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113322 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113323 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113323 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.709 " "Worst-case minimum pulse width slack is -0.709" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.709             -14.425 CLOCK_50  " "   -0.709             -14.425 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -26.143 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -26.143 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.456               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.456               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487113324 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113324 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487113330 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487113471 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114155 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114222 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487114224 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114224 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.423 " "Worst-case setup slack is -1.423" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.423             -50.727 tick_50000:TICK0\|CLK_OUT  " "   -1.423             -50.727 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.177             -13.311 CLOCK_50  " "   -1.177             -13.311 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.511              -0.511 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.511              -0.511 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114224 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114224 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.068 " "Worst-case hold slack is 0.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.068               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.068               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.076               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.076               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.184               0.000 CLOCK_50  " "    0.184               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114226 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114226 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114227 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114228 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.786 " "Worst-case minimum pulse width slack is -0.786" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.786             -11.293 CLOCK_50  " "   -0.786             -11.293 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.059               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.059               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.431               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.431               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114229 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114229 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481487114235 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114378 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481487114379 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114379 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.279 " "Worst-case setup slack is -1.279" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.279             -44.144 tick_50000:TICK0\|CLK_OUT  " "   -1.279             -44.144 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.143             -11.225 CLOCK_50  " "   -1.143             -11.225 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.396              -0.396 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.396              -0.396 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114380 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114380 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.000 " "Worst-case hold slack is 0.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.000               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.000               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.045               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.045               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.176               0.000 CLOCK_50  " "    0.176               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114381 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114381 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114382 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114383 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.844 " "Worst-case minimum pulse width slack is -0.844" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.844             -13.411 CLOCK_50  " "   -0.844             -13.411 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.077               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.077               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.444               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.444               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481487114383 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487114383 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487115666 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487115667 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1217 " "Peak virtual memory: 1217 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481487115694 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:11:55 2016 " "Processing ended: Sun Dec 11 20:11:55 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481487115694 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481487115694 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481487115694 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487115694 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 74 s " "Quartus Prime Full Compilation was successful. 0 errors, 74 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481487115852 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481113236662 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481113236665 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:20:36 2016 " "Processing started: Wed Dec 07 12:20:36 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481113236665 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113236665 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113236665 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481113237277 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481113237277 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245775 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245775 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245781 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245781 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245785 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245785 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245790 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245790 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245795 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245795 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245795 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245795 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245797 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245798 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245799 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245799 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245799 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245800 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245801 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245801 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245806 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245806 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481113245821 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245822 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245822 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481113245828 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245828 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245828 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245833 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245833 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex8.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex8.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex8 " "Found entity 1: ex8" {  } { { "verilog_files/ex8.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481113245837 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245837 ""}
+{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count formula_fsm.v(42) " "Verilog HDL error at formula_fsm.v(42): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 42 0 0 } }  } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1481113245838 ""}
+{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count formula_fsm.v(45) " "Verilog HDL error at formula_fsm.v(45): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 45 0 0 } }  } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1481113245838 ""}
+{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count formula_fsm.v(49) " "Verilog HDL error at formula_fsm.v(49): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 49 0 0 } }  } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1481113245839 ""}
+{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count formula_fsm.v(52) " "Verilog HDL error at formula_fsm.v(52): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v" 52 0 0 } }  } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1481113245839 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113245876 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 4 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 4 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "830 " "Peak virtual memory: 830 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481113246053 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Dec 07 12:20:46 2016 " "Processing ended: Wed Dec 07 12:20:46 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481113246053 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481113246053 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481113246053 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113246053 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 6 s 1  " "Quartus Prime Full Compilation was unsuccessful. 6 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481113247275 ""}
diff --git a/part_2/ex8/ex8.qsf b/part_2/ex8/ex8.qsf
index 9d2c16a..b806fc9 100755
--- a/part_2/ex8/ex8.qsf
+++ b/part_2/ex8/ex8.qsf
@@ -252,7 +252,7 @@ set_global_assignment -name DEVICE 5CSEMA5F31C6
 set_global_assignment -name TOP_LEVEL_ENTITY ex8
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:21:41  NOVEMBER 23, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
diff --git a/part_2/ex8/ex8.qws b/part_2/ex8/ex8.qws
index b5716f0..b770ba8 100755
--- a/part_2/ex8/ex8.qws
+++ b/part_2/ex8/ex8.qws
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info b/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info
index 00e5756..2914929 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Version_Index = 419480576
-Creation_Time = Sun Dec 11 20:04:49 2016
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Wed Nov 23 10:30:54 2016
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb
index 93bee56..ba81eb9 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.ammdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb
index e0f1bca..ac6620f 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb
index 88f54a4..a677ce0 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb
index 7f5d0fc..dfc8697 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb
index d51f8f2..4335c17 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb
index 626799f..d45424f 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb
index 9c7dd08..6d87d95 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.cmp.rcfdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb
index 8e88130..d523670 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi
index a8f9221..dbcb729 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.dpi
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb
index f39023f..22dbf8c 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb
index 4f448b3..8339a7a 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hbdb.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb
index f3d911b..75f106f 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt
index 4b9feaa..cc179b3 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.kpt
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb
new file mode 100755
index 0000000..0c49a16
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olf.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb
new file mode 100755
index 0000000..ae4b3c7
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.olm.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb
new file mode 100755
index 0000000..64265ec
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.oln.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.opi b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi
index 56a6051..56a6051 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.opi
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.opi
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb
new file mode 100755
index 0000000..cc61be4
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orf.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb
new file mode 100755
index 0000000..9ad923c
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orm.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb
new file mode 100755
index 0000000..5f1bbfa
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.map.orn.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb
new file mode 100755
index 0000000..d523670
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdb
index 9f6309e..22dbf8c 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.cdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..8339a7a
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hbdb.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb
new file mode 100755
index 0000000..75f106f
--- /dev/null
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.root_partition.rrp.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb
index b5cb404..db11b7c 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrp.hdb
diff --git a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb
index fab13d7..7d10985 100755
--- a/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb
+++ b/part_2/ex8/incremental_db/compiled_partitions/ex8.rrs.cdb
diff --git a/part_2/ex8/output_files/ex8.asm.rpt b/part_2/ex8/output_files/ex8.asm.rpt
index 8aaf367..cdabd79 100755
--- a/part_2/ex8/output_files/ex8.asm.rpt
+++ b/part_2/ex8/output_files/ex8.asm.rpt
@@ -1,92 +1,92 @@
-Assembler report for ex8
-Sun Dec 11 20:25:43 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: ex8.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Sun Dec 11 20:25:43 2016 ;
-; Revision Name         ; ex8                                   ;
-; Top-level Entity Name ; ex8                                   ;
-; Family                ; Cyclone V                             ;
-; Device                ; 5CSEMA5F31C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings               ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+---------------------------+
-; Assembler Generated Files ;
-+---------------------------+
-; File Name                 ;
-+---------------------------+
-; ex8.sof                   ;
-+---------------------------+
-
-
-+-----------------------------------+
-; Assembler Device Options: ex8.sof ;
-+----------------+------------------+
-; Option         ; Setting          ;
-+----------------+------------------+
-; Device         ; 5CSEMA5F31C6     ;
-; JTAG usercode  ; 0x00B2101D       ;
-; Checksum       ; 0x00B2101D       ;
-+----------------+------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 20:25:37 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 972 megabytes
-    Info: Processing ended: Sun Dec 11 20:25:43 2016
-    Info: Elapsed time: 00:00:06
-    Info: Total CPU time (on all processors): 00:00:06
-
-
+Assembler report for ex8
+Wed Dec 07 12:22:20 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Wed Dec 07 12:22:20 2016 ;
+; Revision Name         ; ex8                                   ;
+; Top-level Entity Name ; ex8                                   ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++----------------------------------------------------------------------+
+; Assembler Generated Files                                            ;
++----------------------------------------------------------------------+
+; File Name                                                            ;
++----------------------------------------------------------------------+
+; H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.sof ;
++----------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.sof ;
++----------------+-------------------------------------------------------------------------------+
+; Option         ; Setting                                                                       ;
++----------------+-------------------------------------------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                                                  ;
+; JTAG usercode  ; 0x00B23777                                                                    ;
+; Checksum       ; 0x00B23777                                                                    ;
++----------------+-------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:22:10 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 891 megabytes
+    Info: Processing ended: Wed Dec 07 12:22:20 2016
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex8/output_files/ex8.done b/part_2/ex8/output_files/ex8.done
index 2600f85..3ad0054 100755
--- a/part_2/ex8/output_files/ex8.done
+++ b/part_2/ex8/output_files/ex8.done
@@ -1 +1 @@
-Sun Dec 11 20:25:48 2016
+Wed Dec 07 12:22:33 2016
diff --git a/part_2/ex8/output_files/ex8.fit.rpt b/part_2/ex8/output_files/ex8.fit.rpt
index 06f6aa9..6167809 100755
--- a/part_2/ex8/output_files/ex8.fit.rpt
+++ b/part_2/ex8/output_files/ex8.fit.rpt
@@ -1,2053 +1,2060 @@
-Fitter report for ex8
-Sun Dec 11 20:25:36 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. Fitter Netlist Optimizations
-  6. Ignored Assignments
-  7. Incremental Compilation Preservation Summary
-  8. Incremental Compilation Partition Settings
-  9. Incremental Compilation Placement Preservation
- 10. Pin-Out File
- 11. Fitter Resource Usage Summary
- 12. Fitter Partition Statistics
- 13. Input Pins
- 14. Output Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. I/O Rules Summary
- 25. I/O Rules Details
- 26. I/O Rules Matrix
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing Summary
- 30. Estimated Delay Added for Hold Timing Details
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Fitter Summary                                                                ;
-+---------------------------------+---------------------------------------------+
-; Fitter Status                   ; Successful - Sun Dec 11 20:25:36 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex8                                         ;
-; Top-level Entity Name           ; ex8                                         ;
-; Family                          ; Cyclone V                                   ;
-; Device                          ; 5CSEMA5F31C6                                ;
-; Timing Models                   ; Final                                       ;
-; Logic utilization (in ALMs)     ; 76 / 32,070 ( < 1 % )                       ;
-; Total registers                 ; 75                                          ;
-; Total pins                      ; 36 / 457 ( 8 % )                            ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                       ;
-; Total RAM Blocks                ; 0 / 397 ( 0 % )                             ;
-; Total DSP Blocks                ; 0 / 87 ( 0 % )                              ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0 / 6 ( 0 % )                               ;
-; Total DLLs                      ; 0 / 4 ( 0 % )                               ;
-+---------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
-; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
-; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
-; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; Clamping Diode                                                             ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.02        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.6%      ;
-;     Processor 3            ;   0.6%      ;
-;     Processor 4            ;   0.5%      ;
-+----------------------------+-------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations                                                                                                                                                                                                            ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;
-; delay:DEL0|state.TIME_OUT  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; delay:DEL0|state.TIME_OUT~DUPLICATE  ;                  ;                       ;
-; formula_fsm:FSM|count[4]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[4]~DUPLICATE   ;                  ;                       ;
-; formula_fsm:FSM|count[6]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[6]~DUPLICATE   ;                  ;                       ;
-; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[6]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[6]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[7]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[7]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[11]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[14]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Ignored Assignments                                                                        ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
-; Location     ;                ;              ; HEX3[0]    ; PIN_AD26      ; QSF Assignment ;
-; Location     ;                ;              ; HEX3[1]    ; PIN_AC27      ; QSF Assignment ;
-; Location     ;                ;              ; HEX3[2]    ; PIN_AD25      ; QSF Assignment ;
-; Location     ;                ;              ; HEX3[3]    ; PIN_AC25      ; QSF Assignment ;
-; Location     ;                ;              ; HEX3[4]    ; PIN_AB28      ; QSF Assignment ;
-; Location     ;                ;              ; HEX3[5]    ; PIN_AB25      ; QSF Assignment ;
-; Location     ;                ;              ; HEX3[6]    ; PIN_AB22      ; QSF Assignment ;
-; Location     ;                ;              ; HEX4[0]    ; PIN_AA24      ; QSF Assignment ;
-; Location     ;                ;              ; HEX4[1]    ; PIN_Y23       ; QSF Assignment ;
-; Location     ;                ;              ; HEX4[2]    ; PIN_Y24       ; QSF Assignment ;
-; Location     ;                ;              ; HEX4[3]    ; PIN_W22       ; QSF Assignment ;
-; Location     ;                ;              ; HEX4[4]    ; PIN_W24       ; QSF Assignment ;
-; Location     ;                ;              ; HEX4[5]    ; PIN_V23       ; QSF Assignment ;
-; Location     ;                ;              ; HEX4[6]    ; PIN_W25       ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
-; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
-; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
-; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
-; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX3[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX3[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX3[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX3[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX3[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX3[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX3[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX4[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX4[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX4[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX4[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX4[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX4[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX4[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex8            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                     ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 273 ) ; 0.00 % ( 0 / 273 )         ; 0.00 % ( 0 / 273 )       ;
-;     -- Achieved     ; 0.00 % ( 0 / 273 ) ; 0.00 % ( 0 / 273 )         ; 0.00 % ( 0 / 273 )       ;
-;                     ;                    ;                            ;                          ;
-; Routing (by net)    ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 273 )    ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.pin.
-
-
-+------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                                            ;
-+-------------------------------------------------------------+--------------------+-------+
-; Resource                                                    ; Usage              ; %     ;
-+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 76 / 32,070        ; < 1 % ;
-; ALMs needed [=A-B+C]                                        ; 76                 ;       ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 80 / 32,070        ; < 1 % ;
-;         [a] ALMs used for LUT logic and registers           ; 27                 ;       ;
-;         [b] ALMs used for LUT logic                         ; 47                 ;       ;
-;         [c] ALMs used for registers                         ; 6                  ;       ;
-;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 4 / 32,070         ; < 1 % ;
-;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
-;         [a] Due to location constrained logic               ; 0                  ;       ;
-;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
-;         [c] Due to LAB input limits                         ; 0                  ;       ;
-;         [d] Due to virtual I/Os                             ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Difficulty packing design                                   ; Low                ;       ;
-;                                                             ;                    ;       ;
-; Total LABs:  partially or completely used                   ; 10 / 3,207         ; < 1 % ;
-;     -- Logic LABs                                           ; 10                 ;       ;
-;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Combinational ALUT usage for logic                          ; 136                ;       ;
-;     -- 7 input functions                                    ; 1                  ;       ;
-;     -- 6 input functions                                    ; 24                 ;       ;
-;     -- 5 input functions                                    ; 5                  ;       ;
-;     -- 4 input functions                                    ; 39                 ;       ;
-;     -- <=3 input functions                                  ; 67                 ;       ;
-; Combinational ALUT usage for route-throughs                 ; 4                  ;       ;
-;                                                             ;                    ;       ;
-; Dedicated logic registers                                   ; 75                 ;       ;
-;     -- By type:                                             ;                    ;       ;
-;         -- Primary logic registers                          ; 64 / 64,140        ; < 1 % ;
-;         -- Secondary logic registers                        ; 11 / 64,140        ; < 1 % ;
-;     -- By function:                                         ;                    ;       ;
-;         -- Design implementation registers                  ; 64                 ;       ;
-;         -- Routing optimization registers                   ; 11                 ;       ;
-;                                                             ;                    ;       ;
-; Virtual pins                                                ; 0                  ;       ;
-; I/O pins                                                    ; 36 / 457           ; 8 %   ;
-;     -- Clock pins                                           ; 2 / 8              ; 25 %  ;
-;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
-;                                                             ;                    ;       ;
-; Hard processor system peripheral utilization                ;                    ;       ;
-;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
-;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
-;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
-;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
-;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
-;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
-;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
-;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
-;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
-;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
-;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
-;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
-;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
-;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
-;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
-;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
-;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
-;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
-;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
-;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
-;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
-;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
-;                                                             ;                    ;       ;
-; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
-; Total MLAB memory bits                                      ; 0                  ;       ;
-; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
-; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
-;                                                             ;                    ;       ;
-; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
-;                                                             ;                    ;       ;
-; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
-; Global signals                                              ; 1                  ;       ;
-;     -- Global clocks                                        ; 1 / 16             ; 6 %   ;
-;     -- Quadrant clocks                                      ; 0 / 66             ; 0 %   ;
-;     -- Horizontal periphery clocks                          ; 0 / 18             ; 0 %   ;
-; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
-; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
-; JTAGs                                                       ; 0 / 1              ; 0 %   ;
-; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
-; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
-; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
-; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
-; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
-; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
-; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
-; Peak interconnect usage (total/H/V)                         ; 2.5% / 2.5% / 2.2% ;       ;
-; Maximum fan-out                                             ; 50                 ;       ;
-; Highest non-global fan-out                                  ; 50                 ;       ;
-; Total fan-out                                               ; 737                ;       ;
-; Average fan-out                                             ; 2.56               ;       ;
-+-------------------------------------------------------------+--------------------+-------+
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                                         ;
-+-------------------------------------------------------------+----------------------+--------------------------------+
-; Statistic                                                   ; Top                  ; hard_block:auto_generated_inst ;
-+-------------------------------------------------------------+----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 76 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-; ALMs needed [=A-B+C]                                        ; 76                   ; 0                              ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 80 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-;         [a] ALMs used for LUT logic and registers           ; 27                   ; 0                              ;
-;         [b] ALMs used for LUT logic                         ; 47                   ; 0                              ;
-;         [c] ALMs used for registers                         ; 6                    ; 0                              ;
-;         [d] ALMs used for memory (up to half of total ALMs) ; 0                    ; 0                              ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 4 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
-;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )    ; 0 / 32070 ( 0 % )              ;
-;         [a] Due to location constrained logic               ; 0                    ; 0                              ;
-;         [b] Due to LAB-wide signal conflicts                ; 0                    ; 0                              ;
-;         [c] Due to LAB input limits                         ; 0                    ; 0                              ;
-;         [d] Due to virtual I/Os                             ; 0                    ; 0                              ;
-;                                                             ;                      ;                                ;
-; Difficulty packing design                                   ; Low                  ; Low                            ;
-;                                                             ;                      ;                                ;
-; Total LABs:  partially or completely used                   ; 10 / 3207 ( < 1 % )  ; 0 / 3207 ( 0 % )               ;
-;     -- Logic LABs                                           ; 10                   ; 0                              ;
-;     -- Memory LABs (up to half of total LABs)               ; 0                    ; 0                              ;
-;                                                             ;                      ;                                ;
-; Combinational ALUT usage for logic                          ; 136                  ; 0                              ;
-;     -- 7 input functions                                    ; 1                    ; 0                              ;
-;     -- 6 input functions                                    ; 24                   ; 0                              ;
-;     -- 5 input functions                                    ; 5                    ; 0                              ;
-;     -- 4 input functions                                    ; 39                   ; 0                              ;
-;     -- <=3 input functions                                  ; 67                   ; 0                              ;
-; Combinational ALUT usage for route-throughs                 ; 4                    ; 0                              ;
-; Memory ALUT usage                                           ; 0                    ; 0                              ;
-;     -- 64-address deep                                      ; 0                    ; 0                              ;
-;     -- 32-address deep                                      ; 0                    ; 0                              ;
-;                                                             ;                      ;                                ;
-; Dedicated logic registers                                   ; 0                    ; 0                              ;
-;     -- By type:                                             ;                      ;                                ;
-;         -- Primary logic registers                          ; 64 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;
-;         -- Secondary logic registers                        ; 11 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;
-;     -- By function:                                         ;                      ;                                ;
-;         -- Design implementation registers                  ; 64                   ; 0                              ;
-;         -- Routing optimization registers                   ; 11                   ; 0                              ;
-;                                                             ;                      ;                                ;
-;                                                             ;                      ;                                ;
-; Virtual pins                                                ; 0                    ; 0                              ;
-; I/O pins                                                    ; 36                   ; 0                              ;
-; I/O registers                                               ; 0                    ; 0                              ;
-; Total block memory bits                                     ; 0                    ; 0                              ;
-; Total block memory implementation bits                      ; 0                    ; 0                              ;
-; Clock enable block                                          ; 1 / 116 ( < 1 % )    ; 0 / 116 ( 0 % )                ;
-;                                                             ;                      ;                                ;
-; Connections                                                 ;                      ;                                ;
-;     -- Input Connections                                    ; 0                    ; 0                              ;
-;     -- Registered Input Connections                         ; 0                    ; 0                              ;
-;     -- Output Connections                                   ; 0                    ; 0                              ;
-;     -- Registered Output Connections                        ; 0                    ; 0                              ;
-;                                                             ;                      ;                                ;
-; Internal Connections                                        ;                      ;                                ;
-;     -- Total Connections                                    ; 737                  ; 0                              ;
-;     -- Registered Connections                               ; 318                  ; 0                              ;
-;                                                             ;                      ;                                ;
-; External Connections                                        ;                      ;                                ;
-;     -- Top                                                  ; 0                    ; 0                              ;
-;     -- hard_block:auto_generated_inst                       ; 0                    ; 0                              ;
-;                                                             ;                      ;                                ;
-; Partition Interface                                         ;                      ;                                ;
-;     -- Input Ports                                          ; 5                    ; 0                              ;
-;     -- Output Ports                                         ; 31                   ; 0                              ;
-;     -- Bidir Ports                                          ; 0                    ; 0                              ;
-;                                                             ;                      ;                                ;
-; Registered Ports                                            ;                      ;                                ;
-;     -- Registered Input Ports                               ; 0                    ; 0                              ;
-;     -- Registered Output Ports                              ; 0                    ; 0                              ;
-;                                                             ;                      ;                                ;
-; Port Connectivity                                           ;                      ;                                ;
-;     -- Input Ports driven by GND                            ; 0                    ; 0                              ;
-;     -- Output Ports driven by GND                           ; 0                    ; 0                              ;
-;     -- Input Ports driven by VCC                            ; 0                    ; 0                              ;
-;     -- Output Ports driven by VCC                           ; 0                    ; 0                              ;
-;     -- Input Ports with no Source                           ; 0                    ; 0                              ;
-;     -- Output Ports with no Source                          ; 0                    ; 0                              ;
-;     -- Input Ports with no Fanout                           ; 0                    ; 0                              ;
-;     -- Output Ports with no Fanout                          ; 0                    ; 0                              ;
-+-------------------------------------------------------------+----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                              ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 25                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+----------------------------------------------------------------------------+
-; I/O Bank Usage                                                             ;
-+----------+------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+------------------+---------------+--------------+---------------+
-; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
-; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
-; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 3B       ; 5 / 48 ( 10 % )  ; 3.3V          ; --           ; 3.3V          ;
-; 4A       ; 7 / 80 ( 9 % )   ; 3.3V          ; --           ; 3.3V          ;
-; 5A       ; 18 / 32 ( 56 % ) ; 3.3V          ; --           ; 3.3V          ;
-; 5B       ; 6 / 16 ( 38 % )  ; 3.3V          ; --           ; 3.3V          ;
-; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
-+----------+------------------+---------------+--------------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                  ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AA24     ; 228        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB22     ; 225        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB25     ; 230        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AD26     ; 240        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
-; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
-; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
-; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
-; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V23      ; 236        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W22      ; 223        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; W24      ; 238        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; Y23      ; 232        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y24      ; 234        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings                         ;
-+----------+--------------------------------------+
-; Pin Name ; Reason                               ;
-+----------+--------------------------------------+
-; HEX0[0]  ; Missing drive strength and slew rate ;
-; HEX0[1]  ; Missing drive strength and slew rate ;
-; HEX0[2]  ; Missing drive strength and slew rate ;
-; HEX0[3]  ; Missing drive strength and slew rate ;
-; HEX0[4]  ; Missing drive strength and slew rate ;
-; HEX0[5]  ; Missing drive strength and slew rate ;
-; HEX0[6]  ; Missing drive strength and slew rate ;
-; HEX1[0]  ; Missing drive strength and slew rate ;
-; HEX1[1]  ; Missing drive strength and slew rate ;
-; HEX1[2]  ; Missing drive strength and slew rate ;
-; HEX1[3]  ; Missing drive strength and slew rate ;
-; HEX1[4]  ; Missing drive strength and slew rate ;
-; HEX1[5]  ; Missing drive strength and slew rate ;
-; HEX1[6]  ; Missing drive strength and slew rate ;
-; HEX2[0]  ; Missing drive strength and slew rate ;
-; HEX2[1]  ; Missing drive strength and slew rate ;
-; HEX2[2]  ; Missing drive strength and slew rate ;
-; HEX2[3]  ; Missing drive strength and slew rate ;
-; HEX2[4]  ; Missing drive strength and slew rate ;
-; HEX2[5]  ; Missing drive strength and slew rate ;
-; HEX2[6]  ; Missing drive strength and slew rate ;
-; LEDR[0]  ; Missing drive strength and slew rate ;
-; LEDR[1]  ; Missing drive strength and slew rate ;
-; LEDR[2]  ; Missing drive strength and slew rate ;
-; LEDR[3]  ; Missing drive strength and slew rate ;
-; LEDR[4]  ; Missing drive strength and slew rate ;
-; LEDR[5]  ; Missing drive strength and slew rate ;
-; LEDR[6]  ; Missing drive strength and slew rate ;
-; LEDR[7]  ; Missing drive strength and slew rate ;
-; LEDR[8]  ; Missing drive strength and slew rate ;
-; LEDR[9]  ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex8                       ; 75.5 (0.5)           ; 78.5 (0.5)                       ; 3.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 136 (1)             ; 75 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 36   ; 0            ; |ex8                             ; ex8         ; work         ;
-;    |LFSR:LFSR0|            ; 2.9 (2.9)            ; 4.3 (4.3)                        ; 1.4 (1.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 6.1 (0.0)            ; 6.7 (0.0)                        ; 0.6 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 14 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A22|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 1.2 (1.2)            ; 1.7 (1.7)                        ; 0.4 (0.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 1.8 (1.8)            ; 2.0 (2.0)                        ; 0.2 (0.2)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;    |delay:DEL0|            ; 14.6 (14.6)          ; 15.7 (15.7)                      ; 1.2 (1.2)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 25 (25)             ; 19 (19)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 21.3 (21.3)          ; 21.3 (21.3)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 37 (37)             ; 24 (24)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 7.2 (7.2)            ; 7.5 (7.5)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |tick_50000:TICK0|      ; 18.5 (18.5)          ; 19.0 (19.0)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 25 (25)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                                                     ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; KEY[0]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; KEY[3]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                                                ;
-+-------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;
-+-------------------------------------------------+-------------------+---------+
-; KEY[0]                                          ;                   ;         ;
-; KEY[1]                                          ;                   ;         ;
-; KEY[2]                                          ;                   ;         ;
-; KEY[3]                                          ;                   ;         ;
-;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~1 ; 0                 ; 0       ;
-;      - formula_fsm:FSM|Selector2~0              ; 0                 ; 0       ;
-;      - formula_fsm:FSM|Selector3~0              ; 0                 ; 0       ;
-; CLOCK_50                                        ;                   ;         ;
-;      - tick_50000:TICK0|CLK_OUT                 ; 0                 ; 0       ;
-+-------------------------------------------------+-------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                                                                                ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; Name                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50                            ; PIN_AF14           ; 2       ; Clock                      ; no     ; --                   ; --               ; --                        ;
-; CLOCK_50                            ; PIN_AF14           ; 24      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
-; delay:DEL0|count[6]~0               ; LABCELL_X81_Y8_N48 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|state.COUNTING           ; FF_X82_Y8_N29      ; 20      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X81_Y6_N14      ; 22      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.WAIT_TRIGGER  ; FF_X82_Y6_N41      ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; tick_50000:TICK0|CLK_OUT            ; FF_X81_Y4_N32      ; 50      ; Clock                      ; no     ; --                   ; --               ; --                        ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals                                                                         ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 24      ; Global Clock         ; GCLK6            ; --                        ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------+
-; Routing Usage Summary                                                 ;
-+---------------------------------------------+-------------------------+
-; Routing Resource Type                       ; Usage                   ;
-+---------------------------------------------+-------------------------+
-; Block interconnects                         ; 221 / 289,320 ( < 1 % ) ;
-; C12 interconnects                           ; 3 / 13,420 ( < 1 % )    ;
-; C2 interconnects                            ; 73 / 119,108 ( < 1 % )  ;
-; C4 interconnects                            ; 50 / 56,300 ( < 1 % )   ;
-; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
-; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
-; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
-; Direct links                                ; 38 / 289,320 ( < 1 % )  ;
-; Global clocks                               ; 1 / 16 ( 6 % )          ;
-; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
-; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
-; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
-; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
-; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
-; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
-; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
-; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
-; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
-; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
-; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
-; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
-; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
-; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
-; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
-; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
-; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
-; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
-; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
-; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
-; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
-; Local interconnects                         ; 68 / 84,580 ( < 1 % )   ;
-; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
-; R14 interconnects                           ; 34 / 12,676 ( < 1 % )   ;
-; R14/C12 interconnect drivers                ; 34 / 20,720 ( < 1 % )   ;
-; R3 interconnects                            ; 127 / 130,992 ( < 1 % ) ;
-; R6 interconnects                            ; 106 / 266,960 ( < 1 % ) ;
-; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
-; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
-+---------------------------------------------+-------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 28    ;
-; Number of I/O Rules Passed       ; 6     ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 22    ;
-+----------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                  ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
-; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
-; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
-; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
-; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Pin/Rules          ; IO_000002    ; IO_000003 ; IO_000001 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000022    ; IO_000021    ; IO_000046    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000047    ; IO_000020    ; IO_000019    ; IO_000018    ; IO_000015    ; IO_000014    ; IO_000013    ; IO_000012    ; IO_000011    ; IO_000010 ; IO_000009 ; IO_000034    ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Total Pass         ; 0            ; 36        ; 36        ; 0            ; 0            ; 36        ; 36        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 36        ; 36        ; 0            ;
-; Total Unchecked    ; 0            ; 0         ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ;
-; Total Inapplicable ; 36           ; 0         ; 0         ; 36           ; 36           ; 0         ; 0         ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 0         ; 0         ; 36           ;
-; Total Fail         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ;
-; KEY[0]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; KEY[1]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; KEY[2]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[7]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[8]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[9]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; KEY[3]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; CLOCK_50           ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                          ;
-+------------------------------------------------------------------+-----------------------------+
-; Option                                                           ; Setting                     ;
-+------------------------------------------------------------------+-----------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
-; Enable INIT_DONE output                                          ; Off                         ;
-; Configuration scheme                                             ; Passive Serial              ;
-; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
-; Enable CvP_CONFDONE pin                                          ; Off                         ;
-; Enable open drain on CRC_ERROR pin                               ; On                          ;
-; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
-; Enable open drain on INIT_DONE pin                               ; On                          ;
-; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
-; Enable open drain on nCEO pin                                    ; On                          ;
-; Enable Partial Reconfiguration pins                              ; Off                         ;
-; Enable input tri-state on active configuration pins in user mode ; Off                         ;
-; Enable internal scrubbing                                        ; Off                         ;
-; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
-; Device initialization clock source                               ; Internal Oscillator         ;
-; Configuration via Protocol                                       ; Off                         ;
-; Configuration Voltage Level                                      ; Auto                        ;
-; Force Configuration Voltage Level                                ; Off                         ;
-; Enable nCEO output                                               ; Off                         ;
-; Data[15..8]                                                      ; Unreserved                  ;
-; Data[7..5]                                                       ; Unreserved                  ;
-; Base pin-out file on sameframe device                            ; Off                         ;
-+------------------------------------------------------------------+-----------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.10 V ;
-; Low Junction Temperature  ; 0 �C   ;
-; High Junction Temperature ; 85 �C  ;
-+---------------------------+--------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary                                                               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 68.7              ;
-; CLOCK_50                                                     ; CLOCK_50                 ; 14.9              ;
-; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 2.9               ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 2.6               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details                                                       ;
-+----------------------------------------+----------------------------------------+-------------------+
-; Source Register                        ; Destination Register                   ; Delay Added in ns ;
-+----------------------------------------+----------------------------------------+-------------------+
-; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT               ; 2.060             ;
-; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT               ; 2.035             ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[1]                ; 2.002             ;
-; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT               ; 1.958             ;
-; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT               ; 1.946             ;
-; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT               ; 1.935             ;
-; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT               ; 1.923             ;
-; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT               ; 1.920             ;
-; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT               ; 1.905             ;
-; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT               ; 1.903             ;
-; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT               ; 1.902             ;
-; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT               ; 1.881             ;
-; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT               ; 1.881             ;
-; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT               ; 1.878             ;
-; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT               ; 1.848             ;
-; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT               ; 1.847             ;
-; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT               ; 1.816             ;
-; formula_fsm:FSM|start_delay            ; delay:DEL0|state.IDLE                  ; 1.356             ;
-; formula_fsm:FSM|count[6]               ; formula_fsm:FSM|ledr[2]                ; 1.043             ;
-; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[2]                    ; 0.981             ;
-; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.937             ;
-; delay:DEL0|count[8]                    ; delay:DEL0|state.IDLE                  ; 0.932             ;
-; formula_fsm:FSM|count[2]               ; formula_fsm:FSM|ledr[2]                ; 0.928             ;
-; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.926             ;
-; formula_fsm:FSM|count[1]               ; formula_fsm:FSM|ledr[2]                ; 0.924             ;
-; delay:DEL0|state.COUNTING              ; delay:DEL0|state.IDLE                  ; 0.922             ;
-; delay:DEL0|count[6]                    ; delay:DEL0|state.IDLE                  ; 0.920             ;
-; delay:DEL0|count[2]                    ; delay:DEL0|state.IDLE                  ; 0.919             ;
-; delay:DEL0|count[3]                    ; delay:DEL0|state.IDLE                  ; 0.915             ;
-; formula_fsm:FSM|count[0]               ; formula_fsm:FSM|ledr[2]                ; 0.903             ;
-; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.899             ;
-; formula_fsm:FSM|count[4]               ; formula_fsm:FSM|ledr[2]                ; 0.867             ;
-; delay:DEL0|count[10]                   ; delay:DEL0|state.IDLE                  ; 0.866             ;
-; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.859             ;
-; delay:DEL0|count[4]                    ; delay:DEL0|state.IDLE                  ; 0.851             ;
-; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.850             ;
-; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.836             ;
-; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.820             ;
-; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.790             ;
-; formula_fsm:FSM|count[7]               ; formula_fsm:FSM|ledr[2]                ; 0.782             ;
-; formula_fsm:FSM|count[3]               ; formula_fsm:FSM|ledr[2]                ; 0.782             ;
-; formula_fsm:FSM|count[5]               ; formula_fsm:FSM|ledr[2]                ; 0.782             ;
-; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[2]                ; 0.782             ;
-; formula_fsm:FSM|count[8]               ; formula_fsm:FSM|ledr[2]                ; 0.782             ;
-; delay:DEL0|count[7]                    ; delay:DEL0|state.IDLE                  ; 0.750             ;
-; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE                  ; 0.748             ;
-; delay:DEL0|count[11]                   ; delay:DEL0|state.IDLE                  ; 0.746             ;
-; delay:DEL0|count[5]                    ; delay:DEL0|state.IDLE                  ; 0.746             ;
-; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                    ; 0.735             ;
-; LFSR:LFSR0|COUNT[5]                    ; LFSR:LFSR0|COUNT[6]                    ; 0.735             ;
-; delay:DEL0|count[0]                    ; delay:DEL0|state.IDLE                  ; 0.734             ;
-; delay:DEL0|count[1]                    ; delay:DEL0|state.IDLE                  ; 0.729             ;
-; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|ledr[6]                ; 0.728             ;
-; LFSR:LFSR0|COUNT[4]                    ; LFSR:LFSR0|COUNT[5]                    ; 0.722             ;
-; LFSR:LFSR0|COUNT[6]                    ; LFSR:LFSR0|COUNT[7]                    ; 0.722             ;
-; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; 0.696             ;
-; delay:DEL0|count[9]                    ; delay:DEL0|state.IDLE                  ; 0.690             ;
-; delay:DEL0|state.TIME_OUT              ; delay:DEL0|state.IDLE                  ; 0.671             ;
-; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                    ; 0.649             ;
-; delay:DEL0|state.IDLE                  ; delay:DEL0|state.IDLE                  ; 0.638             ;
-; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.633             ;
-; delay:DEL0|count[13]                   ; delay:DEL0|state.TIME_OUT              ; 0.631             ;
-; delay:DEL0|count[12]                   ; delay:DEL0|state.TIME_OUT              ; 0.609             ;
-; LFSR:LFSR0|COUNT[2]                    ; LFSR:LFSR0|COUNT[3]                    ; 0.563             ;
-; tick_50000:TICK0|CLK_OUT               ; delay:DEL0|count[0]                    ; 0.110             ;
-; KEY[3]                                 ; formula_fsm:FSM|state.WAIT_TRIGGER     ; 0.024             ;
-+----------------------------------------+----------------------------------------+-------------------+
-Note: This table only shows the top 66 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex8"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (184020): Starting Fitter periphery placement operations
-Info (11191): Automatically promoted 1 clock (1 global)
-    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
-Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
-Info (176233): Starting register packing
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
-    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:12
-Info (170189): Fitter placement preparation operations beginning
-Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
-Info (11888): Total time spent on timing analysis during the Fitter is 0.37 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:02
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 52 warnings
-    Info: Peak virtual memory: 2138 megabytes
-    Info: Processing ended: Sun Dec 11 20:25:36 2016
-    Info: Elapsed time: 00:00:32
-    Info: Total CPU time (on all processors): 00:00:57
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg.
-
-
+Fitter report for ex8
+Wed Dec 07 12:22:02 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Routing Usage Summary
+ 24. I/O Rules Summary
+ 25. I/O Rules Details
+ 26. I/O Rules Matrix
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing Summary
+ 30. Estimated Delay Added for Hold Timing Details
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Wed Dec 07 12:22:02 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex8                                             ;
+; Top-level Entity Name           ; ex8                                             ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 79 / 32,070 ( < 1 % )                           ;
+; Total registers                 ; 84                                              ;
+; Total pins                      ; 36 / 457 ( 8 % )                                ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.02        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.6%      ;
+;     Processor 3            ;   0.5%      ;
+;     Processor 4            ;   0.5%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; HEX0[0]  ; Missing drive strength and slew rate ;
+; HEX0[1]  ; Missing drive strength and slew rate ;
+; HEX0[2]  ; Missing drive strength and slew rate ;
+; HEX0[3]  ; Missing drive strength and slew rate ;
+; HEX0[4]  ; Missing drive strength and slew rate ;
+; HEX0[5]  ; Missing drive strength and slew rate ;
+; HEX0[6]  ; Missing drive strength and slew rate ;
+; HEX1[0]  ; Missing drive strength and slew rate ;
+; HEX1[1]  ; Missing drive strength and slew rate ;
+; HEX1[2]  ; Missing drive strength and slew rate ;
+; HEX1[3]  ; Missing drive strength and slew rate ;
+; HEX1[4]  ; Missing drive strength and slew rate ;
+; HEX1[5]  ; Missing drive strength and slew rate ;
+; HEX1[6]  ; Missing drive strength and slew rate ;
+; HEX2[0]  ; Missing drive strength and slew rate ;
+; HEX2[1]  ; Missing drive strength and slew rate ;
+; HEX2[2]  ; Missing drive strength and slew rate ;
+; HEX2[3]  ; Missing drive strength and slew rate ;
+; HEX2[4]  ; Missing drive strength and slew rate ;
+; HEX2[5]  ; Missing drive strength and slew rate ;
+; HEX2[6]  ; Missing drive strength and slew rate ;
+; LEDR[0]  ; Missing drive strength and slew rate ;
+; LEDR[1]  ; Missing drive strength and slew rate ;
+; LEDR[2]  ; Missing drive strength and slew rate ;
+; LEDR[3]  ; Missing drive strength and slew rate ;
+; LEDR[4]  ; Missing drive strength and slew rate ;
+; LEDR[5]  ; Missing drive strength and slew rate ;
+; LEDR[6]  ; Missing drive strength and slew rate ;
+; LEDR[7]  ; Missing drive strength and slew rate ;
+; LEDR[8]  ; Missing drive strength and slew rate ;
+; LEDR[9]  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                            ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;
+; delay:DEL0|state.TIME_OUT  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; delay:DEL0|state.TIME_OUT~DUPLICATE  ;                  ;                       ;
+; formula_fsm:FSM|count[1]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[1]~DUPLICATE   ;                  ;                       ;
+; formula_fsm:FSM|count[7]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[7]~DUPLICATE   ;                  ;                       ;
+; formula_fsm:FSM|count[11]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[11]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[0]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[0]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[2]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[3]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[3]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[4]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[4]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[6]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[6]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[9]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[9]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[11]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[13]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                        ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[0]    ; PIN_AD26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[1]    ; PIN_AC27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[2]    ; PIN_AD25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[3]    ; PIN_AC25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[4]    ; PIN_AB28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[5]    ; PIN_AB25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[6]    ; PIN_AB22      ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[0]    ; PIN_AA24      ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[1]    ; PIN_Y23       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[2]    ; PIN_Y24       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[3]    ; PIN_W22       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[4]    ; PIN_W24       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[5]    ; PIN_V23       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[6]    ; PIN_W25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX3[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX3[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX3[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX3[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX3[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX3[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX3[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX4[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX4[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX4[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX4[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX4[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX4[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX4[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex8            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 282 ) ; 0.00 % ( 0 / 282 )         ; 0.00 % ( 0 / 282 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 282 ) ; 0.00 % ( 0 / 282 )         ; 0.00 % ( 0 / 282 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 282 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 79 / 32,070        ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 79                 ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 82 / 32,070        ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 28                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 48                 ;       ;
+;         [c] ALMs used for registers                         ; 6                  ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32,070         ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 10 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 10                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 142                ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 29                 ;       ;
+;     -- 5 input functions                                    ; 5                  ;       ;
+;     -- 4 input functions                                    ; 40                 ;       ;
+;     -- <=3 input functions                                  ; 68                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;
+; Dedicated logic registers                                   ; 84                 ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 67 / 64,140        ; < 1 % ;
+;         -- Secondary logic registers                        ; 17 / 64,140        ; < 1 % ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 67                 ;       ;
+;         -- Routing optimization registers                   ; 17                 ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 36 / 457           ; 8 %   ;
+;     -- Clock pins                                           ; 2 / 8              ; 25 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 2.0% / 2.2% / 1.4% ;       ;
+; Maximum fan-out                                             ; 54                 ;       ;
+; Highest non-global fan-out                                  ; 54                 ;       ;
+; Total fan-out                                               ; 780                ;       ;
+; Average fan-out                                             ; 2.60               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                         ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+; Statistic                                                   ; Top                  ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 79 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 79                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 82 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 28                   ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 48                   ; 0                              ;
+;         [c] ALMs used for registers                         ; 6                    ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                    ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )    ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                    ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                    ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                    ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Difficulty packing design                                   ; Low                  ; Low                            ;
+;                                                             ;                      ;                                ;
+; Total LABs:  partially or completely used                   ; 10 / 3207 ( < 1 % )  ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 10                   ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Combinational ALUT usage for logic                          ; 142                  ; 0                              ;
+;     -- 7 input functions                                    ; 0                    ; 0                              ;
+;     -- 6 input functions                                    ; 29                   ; 0                              ;
+;     -- 5 input functions                                    ; 5                    ; 0                              ;
+;     -- 4 input functions                                    ; 40                   ; 0                              ;
+;     -- <=3 input functions                                  ; 68                   ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 1                    ; 0                              ;
+; Memory ALUT usage                                           ; 0                    ; 0                              ;
+;     -- 64-address deep                                      ; 0                    ; 0                              ;
+;     -- 32-address deep                                      ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Dedicated logic registers                                   ; 0                    ; 0                              ;
+;     -- By type:                                             ;                      ;                                ;
+;         -- Primary logic registers                          ; 67 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 17 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                      ;                                ;
+;         -- Design implementation registers                  ; 67                   ; 0                              ;
+;         -- Routing optimization registers                   ; 17                   ; 0                              ;
+;                                                             ;                      ;                                ;
+;                                                             ;                      ;                                ;
+; Virtual pins                                                ; 0                    ; 0                              ;
+; I/O pins                                                    ; 36                   ; 0                              ;
+; I/O registers                                               ; 0                    ; 0                              ;
+; Total block memory bits                                     ; 0                    ; 0                              ;
+; Total block memory implementation bits                      ; 0                    ; 0                              ;
+; Clock enable block                                          ; 1 / 116 ( < 1 % )    ; 0 / 116 ( 0 % )                ;
+;                                                             ;                      ;                                ;
+; Connections                                                 ;                      ;                                ;
+;     -- Input Connections                                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections                         ; 0                    ; 0                              ;
+;     -- Output Connections                                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections                        ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Internal Connections                                        ;                      ;                                ;
+;     -- Total Connections                                    ; 780                  ; 0                              ;
+;     -- Registered Connections                               ; 339                  ; 0                              ;
+;                                                             ;                      ;                                ;
+; External Connections                                        ;                      ;                                ;
+;     -- Top                                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Partition Interface                                         ;                      ;                                ;
+;     -- Input Ports                                          ; 5                    ; 0                              ;
+;     -- Output Ports                                         ; 31                   ; 0                              ;
+;     -- Bidir Ports                                          ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Registered Ports                                            ;                      ;                                ;
+;     -- Registered Input Ports                               ; 0                    ; 0                              ;
+;     -- Registered Output Ports                              ; 0                    ; 0                              ;
+;                                                             ;                      ;                                ;
+; Port Connectivity                                           ;                      ;                                ;
+;     -- Input Ports driven by GND                            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                    ; 0                              ;
++-------------------------------------------------------------+----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 30                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 5 / 48 ( 10 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 7 / 80 ( 9 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 18 / 32 ( 56 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 6 / 16 ( 38 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD26     ; 240        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W22      ; 223        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y24      ; 234        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex8                       ; 78.5 (0.5)           ; 81.0 (0.5)                       ; 2.5 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 142 (1)             ; 84 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 36   ; 0            ; |ex8                             ; ex8         ; work         ;
+;    |LFSR:LFSR0|            ; 2.9 (2.9)            ; 3.6 (3.6)                        ; 0.7 (0.7)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|LFSR:LFSR0                  ; LFSR        ; work         ;
+;    |bin2bcd_16:BCD|        ; 5.4 (0.0)            ; 5.6 (0.0)                        ; 0.2 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
+;       |add3_ge5:A22|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
+;       |add3_ge5:A26|       ; 1.3 (1.3)            ; 1.6 (1.6)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
+;       |add3_ge5:A30|       ; 1.7 (1.7)            ; 1.7 (1.7)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
+;       |add3_ge5:A35|       ; 1.7 (1.7)            ; 1.8 (1.8)                        ; 0.2 (0.2)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
+;    |delay:DEL0|            ; 14.3 (14.3)          ; 14.3 (14.3)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 25 (25)             ; 19 (19)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|delay:DEL0                  ; delay       ; work         ;
+;    |formula_fsm:FSM|       ; 25.6 (25.6)          ; 26.5 (26.5)                      ; 0.9 (0.9)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 43 (43)             ; 28 (28)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|formula_fsm:FSM             ; formula_fsm ; work         ;
+;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 7.7 (7.7)            ; 8.0 (8.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
+;    |tick_50000:TICK0|      ; 18.5 (18.5)          ; 19.0 (19.0)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 30 (30)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex8|tick_50000:TICK0            ; tick_50000  ; work         ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; KEY[0]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; KEY[3]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                ;
++-------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;
++-------------------------------------------------+-------------------+---------+
+; KEY[0]                                          ;                   ;         ;
+; KEY[1]                                          ;                   ;         ;
+; KEY[2]                                          ;                   ;         ;
+; KEY[3]                                          ;                   ;         ;
+;      - formula_fsm:FSM|Selector3~0              ; 0                 ; 0       ;
+;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 0                 ; 0       ;
+;      - formula_fsm:FSM|Selector2~0              ; 0                 ; 0       ;
+; CLOCK_50                                        ;                   ;         ;
+;      - tick_50000:TICK0|CLK_OUT                 ; 0                 ; 0       ;
++-------------------------------------------------+-------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                            ; PIN_AF14           ; 2       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                            ; PIN_AF14           ; 29      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; delay:DEL0|count[0]~0               ; LABCELL_X80_Y3_N54 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; delay:DEL0|state.COUNTING           ; FF_X79_Y3_N8       ; 20      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X80_Y3_N59      ; 26      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;
+; formula_fsm:FSM|state.WAIT_TRIGGER  ; FF_X78_Y3_N14      ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; tick_50000:TICK0|CLK_OUT            ; FF_X75_Y3_N50      ; 54      ; Clock                      ; no     ; --                   ; --               ; --                        ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 29      ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 243 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 2 / 13,420 ( < 1 % )    ;
+; C2 interconnects                            ; 78 / 119,108 ( < 1 % )  ;
+; C4 interconnects                            ; 45 / 56,300 ( < 1 % )   ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 49 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 1 / 16 ( 6 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 72 / 84,580 ( < 1 % )   ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 37 / 12,676 ( < 1 % )   ;
+; R14/C12 interconnect drivers                ; 35 / 20,720 ( < 1 % )   ;
+; R3 interconnects                            ; 127 / 130,992 ( < 1 % ) ;
+; R6 interconnects                            ; 124 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                  ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 36        ; 0            ; 36        ; 0            ; 0            ; 36        ; 36        ; 0            ; 36        ; 36        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 36           ; 0         ; 36           ; 36           ; 0         ; 0         ; 36           ; 0         ; 0         ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ; 36           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                               ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 58.9              ;
+; CLOCK_50                                                     ; CLOCK_50                 ; 12.7              ;
+; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.8               ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 3.3               ;
+; tick_50000:TICK0|CLK_OUT,I/O                                 ; tick_50000:TICK0|CLK_OUT ; 1.6               ;
++--------------------------------------------------------------+--------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                       ;
++----------------------------------------+----------------------------------------+-------------------+
+; Source Register                        ; Destination Register                   ; Delay Added in ns ;
++----------------------------------------+----------------------------------------+-------------------+
+; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[1]                ; 2.039             ;
+; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT               ; 1.697             ;
+; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT               ; 1.669             ;
+; formula_fsm:FSM|start_delay            ; delay:DEL0|state.IDLE                  ; 1.640             ;
+; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT               ; 1.620             ;
+; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT               ; 1.620             ;
+; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT               ; 1.617             ;
+; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT               ; 1.583             ;
+; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT               ; 1.577             ;
+; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT               ; 1.577             ;
+; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT               ; 1.576             ;
+; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT               ; 1.573             ;
+; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT               ; 1.561             ;
+; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT               ; 1.535             ;
+; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT               ; 1.534             ;
+; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT               ; 1.519             ;
+; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT               ; 1.499             ;
+; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT               ; 1.470             ;
+; delay:DEL0|count[6]                    ; delay:DEL0|count[11]                   ; 1.038             ;
+; delay:DEL0|count[8]                    ; delay:DEL0|count[11]                   ; 1.036             ;
+; delay:DEL0|count[13]                   ; delay:DEL0|count[11]                   ; 1.008             ;
+; formula_fsm:FSM|count[1]               ; formula_fsm:FSM|ledr[0]                ; 0.996             ;
+; formula_fsm:FSM|count[6]               ; formula_fsm:FSM|ledr[0]                ; 0.988             ;
+; formula_fsm:FSM|count[8]               ; formula_fsm:FSM|ledr[0]                ; 0.985             ;
+; delay:DEL0|count[4]                    ; delay:DEL0|count[11]                   ; 0.981             ;
+; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[2]                    ; 0.980             ;
+; delay:DEL0|count[10]                   ; delay:DEL0|count[11]                   ; 0.980             ;
+; formula_fsm:FSM|count[0]               ; formula_fsm:FSM|ledr[0]                ; 0.975             ;
+; formula_fsm:FSM|count[7]               ; formula_fsm:FSM|ledr[0]                ; 0.968             ;
+; delay:DEL0|state.COUNTING              ; delay:DEL0|state.IDLE                  ; 0.923             ;
+; delay:DEL0|count[0]                    ; delay:DEL0|count[11]                   ; 0.895             ;
+; delay:DEL0|count[1]                    ; delay:DEL0|count[11]                   ; 0.874             ;
+; delay:DEL0|count[7]                    ; delay:DEL0|count[11]                   ; 0.872             ;
+; delay:DEL0|count[2]                    ; delay:DEL0|count[11]                   ; 0.845             ;
+; delay:DEL0|count[11]                   ; delay:DEL0|count[11]                   ; 0.843             ;
+; delay:DEL0|state.IDLE                  ; delay:DEL0|state.COUNTING              ; 0.836             ;
+; delay:DEL0|count[12]                   ; delay:DEL0|count[11]                   ; 0.833             ;
+; formula_fsm:FSM|count[11]              ; formula_fsm:FSM|ledr[0]                ; 0.830             ;
+; delay:DEL0|state.TIME_OUT              ; delay:DEL0|state.IDLE                  ; 0.820             ;
+; delay:DEL0|count[3]                    ; delay:DEL0|count[11]                   ; 0.813             ;
+; delay:DEL0|count[9]                    ; delay:DEL0|count[11]                   ; 0.801             ;
+; delay:DEL0|count[5]                    ; delay:DEL0|count[11]                   ; 0.801             ;
+; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|ledr[2]                ; 0.795             ;
+; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|count[8]               ; 0.791             ;
+; formula_fsm:FSM|count[3]               ; formula_fsm:FSM|ledr[0]                ; 0.768             ;
+; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE                  ; 0.768             ;
+; formula_fsm:FSM|count[2]               ; formula_fsm:FSM|ledr[0]                ; 0.766             ;
+; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|ledr[0]                ; 0.737             ;
+; formula_fsm:FSM|count[10]              ; formula_fsm:FSM|ledr[0]                ; 0.737             ;
+; formula_fsm:FSM|count[9]               ; formula_fsm:FSM|ledr[0]                ; 0.737             ;
+; formula_fsm:FSM|count[4]               ; formula_fsm:FSM|ledr[0]                ; 0.737             ;
+; formula_fsm:FSM|count[5]               ; formula_fsm:FSM|ledr[0]                ; 0.737             ;
+; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                    ; 0.731             ;
+; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|ledr[9]                ; 0.729             ;
+; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|ledr[9]                ; 0.729             ;
+; LFSR:LFSR0|COUNT[4]                    ; LFSR:LFSR0|COUNT[5]                    ; 0.719             ;
+; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711             ;
+; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711             ;
+; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711             ;
+; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711             ;
+; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711             ;
+; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711             ;
+; KEY[3]                                 ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711             ;
+; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 0.711             ;
+; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                    ; 0.663             ;
+; LFSR:LFSR0|COUNT[5]                    ; LFSR:LFSR0|COUNT[6]                    ; 0.580             ;
+; LFSR:LFSR0|COUNT[6]                    ; LFSR:LFSR0|COUNT[7]                    ; 0.570             ;
+; LFSR:LFSR0|COUNT[2]                    ; LFSR:LFSR0|COUNT[3]                    ; 0.563             ;
++----------------------------------------+----------------------------------------+-------------------+
+Note: This table only shows the top 68 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex8"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:03
+Info (11888): Total time spent on timing analysis during the Fitter is 0.44 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 51 warnings
+    Info: Peak virtual memory: 2608 megabytes
+    Info: Processing ended: Wed Dec 07 12:22:05 2016
+    Info: Elapsed time: 00:00:38
+    Info: Total CPU time (on all processors): 00:00:58
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.fit.smsg.
+
+
diff --git a/part_2/ex8/output_files/ex8.fit.smsg b/part_2/ex8/output_files/ex8.fit.smsg
index 9302919..43eead5 100755
--- a/part_2/ex8/output_files/ex8.fit.smsg
+++ b/part_2/ex8/output_files/ex8.fit.smsg
@@ -1,6 +1,6 @@
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
-Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex8/output_files/ex8.fit.summary b/part_2/ex8/output_files/ex8.fit.summary
index 4340a86..3ae19a5 100755
--- a/part_2/ex8/output_files/ex8.fit.summary
+++ b/part_2/ex8/output_files/ex8.fit.summary
@@ -1,20 +1,20 @@
-Fitter Status : Successful - Sun Dec 11 20:25:36 2016
-Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Revision Name : ex8
-Top-level Entity Name : ex8
-Family : Cyclone V
-Device : 5CSEMA5F31C6
-Timing Models : Final
-Logic utilization (in ALMs) : 76 / 32,070 ( < 1 % )
-Total registers : 75
-Total pins : 36 / 457 ( 8 % )
-Total virtual pins : 0
-Total block memory bits : 0 / 4,065,280 ( 0 % )
-Total RAM Blocks : 0 / 397 ( 0 % )
-Total DSP Blocks : 0 / 87 ( 0 % )
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0 / 6 ( 0 % )
-Total DLLs : 0 / 4 ( 0 % )
+Fitter Status : Successful - Wed Dec 07 12:22:02 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex8
+Top-level Entity Name : ex8
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 79 / 32,070 ( < 1 % )
+Total registers : 84
+Total pins : 36 / 457 ( 8 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_2/ex8/output_files/ex8.flow.rpt b/part_2/ex8/output_files/ex8.flow.rpt
index 0dd5be9..8f0c739 100755
--- a/part_2/ex8/output_files/ex8.flow.rpt
+++ b/part_2/ex8/output_files/ex8.flow.rpt
@@ -1,128 +1,128 @@
-Flow report for ex8
-Sun Dec 11 20:25:48 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Flow Summary                                                                  ;
-+---------------------------------+---------------------------------------------+
-; Flow Status                     ; Successful - Sun Dec 11 20:25:43 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex8                                         ;
-; Top-level Entity Name           ; ex8                                         ;
-; Family                          ; Cyclone V                                   ;
-; Device                          ; 5CSEMA5F31C6                                ;
-; Timing Models                   ; Final                                       ;
-; Logic utilization (in ALMs)     ; 76 / 32,070 ( < 1 % )                       ;
-; Total registers                 ; 75                                          ;
-; Total pins                      ; 36 / 457 ( 8 % )                            ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                       ;
-; Total DSP Blocks                ; 0 / 87 ( 0 % )                              ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0 / 6 ( 0 % )                               ;
-; Total DLLs                      ; 0 / 4 ( 0 % )                               ;
-+---------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 12/11/2016 20:24:54 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; ex8                 ;
-+-------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                        ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID               ; 158515234070422.148148789408646        ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --          ; --         ;
-; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                    ; --            ; --          ; --         ;
-; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW  ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --         ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 1012 MB             ; 00:00:24                           ;
-; Fitter                    ; 00:00:32     ; 1.0                     ; 2138 MB             ; 00:00:56                           ;
-; Assembler                 ; 00:00:06     ; 1.0                     ; 972 MB              ; 00:00:06                           ;
-; TimeQuest Timing Analyzer ; 00:00:05     ; 1.1                     ; 1214 MB             ; 00:00:05                           ;
-; Total                     ; 00:00:53     ; --                      ; --                  ; 00:01:31                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                         ;
-+---------------------------+------------------+------------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
-+---------------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis      ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; Fitter                    ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; Assembler                 ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; TimeQuest Timing Analyzer ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-+---------------------------+------------------+------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
-quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8
-quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8
-quartus_sta ex8 -c ex8
-
-
-
+Flow report for ex8
+Wed Dec 07 12:22:30 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Wed Dec 07 12:22:20 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex8                                             ;
+; Top-level Entity Name           ; ex8                                             ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 79 / 32,070 ( < 1 % )                           ;
+; Total registers                 ; 84                                              ;
+; Total pins                      ; 36 / 457 ( 8 % )                                ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 12/07/2016 12:21:12 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex8                 ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564297098.148111327202376       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:12     ; 1.0                     ; 895 MB              ; 00:00:22                           ;
+; Fitter                    ; 00:00:35     ; 1.0                     ; 2608 MB             ; 00:00:57                           ;
+; Assembler                 ; 00:00:10     ; 1.0                     ; 891 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:09     ; 1.1                     ; 1209 MB             ; 00:00:06                           ;
+; Total                     ; 00:01:06     ; --                      ; --                  ; 00:01:31                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
+quartus_fit --read_settings_files=off --write_settings_files=off ex8 -c ex8
+quartus_asm --read_settings_files=off --write_settings_files=off ex8 -c ex8
+quartus_sta ex8 -c ex8
+
+
+
diff --git a/part_2/ex8/output_files/ex8.jdi b/part_2/ex8/output_files/ex8.jdi
index a69b658..d856c57 100755
--- a/part_2/ex8/output_files/ex8.jdi
+++ b/part_2/ex8/output_files/ex8.jdi
@@ -1,8 +1,8 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="226e380111dba8ff1ed0"/>
-  </project>
-  <file_info>
-    <file device="5CSEMA5F31C6" path="ex8.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="ebb09f580b225437ab24"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex8.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_2/ex8/output_files/ex8.map.rpt b/part_2/ex8/output_files/ex8.map.rpt
index cf3e200..ace9229 100755
--- a/part_2/ex8/output_files/ex8.map.rpt
+++ b/part_2/ex8/output_files/ex8.map.rpt
@@ -1,573 +1,572 @@
-Analysis & Synthesis report for ex8
-Sun Dec 11 20:25:03 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. State Machine - |ex8|delay:DEL0|state
-  9. State Machine - |ex8|formula_fsm:FSM|state
- 10. User-Specified and Inferred Latches
- 11. Registers Removed During Synthesis
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
- 16. Parameter Settings for User Entity Instance: tick_2500:TICK1
- 17. Parameter Settings for User Entity Instance: formula_fsm:FSM
- 18. Parameter Settings for User Entity Instance: delay:DEL0
- 19. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
- 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
- 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
- 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
- 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
- 24. Port Connectivity Checks: "bin2bcd_16:BCD"
- 25. Port Connectivity Checks: "delay:DEL0"
- 26. Post-Synthesis Netlist Statistics for Top Partition
- 27. Elapsed Time Per Partition
- 28. Analysis & Synthesis Messages
- 29. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                  ;
-+---------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status     ; Successful - Sun Dec 11 20:25:03 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex8                                         ;
-; Top-level Entity Name           ; ex8                                         ;
-; Family                          ; Cyclone V                                   ;
-; Logic utilization (in ALMs)     ; N/A                                         ;
-; Total registers                 ; 64                                          ;
-; Total pins                      ; 36                                          ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0                                           ;
-; Total DSP Blocks                ; 0                                           ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0                                           ;
-; Total DLLs                      ; 0                                           ;
-+---------------------------------+---------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                             ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                          ; Setting            ; Default Value      ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
-; Top-level entity name                                                           ; ex8                ; ex8                ;
-; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
-; Use smart compilation                                                           ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
-; Enable compact report table                                                     ; Off                ; Off                ;
-; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
-; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
-; Preserve fewer node names                                                       ; On                 ; On                 ;
-; OpenCore Plus hardware evaluation                                               ; Enable             ; Enable             ;
-; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                                        ; Auto               ; Auto               ;
-; Safe State Machine                                                              ; Off                ; Off                ;
-; Extract Verilog State Machines                                                  ; On                 ; On                 ;
-; Extract VHDL State Machines                                                     ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
-; Parallel Synthesis                                                              ; On                 ; On                 ;
-; DSP Block Balancing                                                             ; Auto               ; Auto               ;
-; NOT Gate Push-Back                                                              ; On                 ; On                 ;
-; Power-Up Don't Care                                                             ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
-; Remove Duplicate Registers                                                      ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
-; Optimization Technique                                                          ; Balanced           ; Balanced           ;
-; Carry Chain Length                                                              ; 70                 ; 70                 ;
-; Auto Carry Chains                                                               ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
-; Auto ROM Replacement                                                            ; On                 ; On                 ;
-; Auto RAM Replacement                                                            ; On                 ; On                 ;
-; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
-; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
-; Strict RAM Replacement                                                          ; Off                ; Off                ;
-; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
-; Auto Resource Sharing                                                           ; Off                ; Off                ;
-; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
-; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
-; Report Parameter Settings                                                       ; On                 ; On                 ;
-; Report Source Assignments                                                       ; On                 ; On                 ;
-; Report Connectivity Checks                                                      ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
-; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
-; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
-; HDL message level                                                               ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
-; Clock MUX Protection                                                            ; On                 ; On                 ;
-; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
-; Block Design Naming                                                             ; Auto               ; Auto               ;
-; SDC constraint protection                                                       ; Off                ; Off                ;
-; Synthesis Effort                                                                ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
-; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
-; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
-; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processors 2-4         ;   0.0%      ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                              ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                                ; Library ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v  ;         ;
-; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v        ;         ;
-; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v ;         ;
-; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v  ;         ;
-; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v    ;         ;
-; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v ;         ;
-; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v       ;         ;
-; verilog_files/tick_2500.v        ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v   ;         ;
-; verilog_files/ex8.v              ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v         ;         ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary                            ;
-+---------------------------------------------+--------------------------+
-; Resource                                    ; Usage                    ;
-+---------------------------------------------+--------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 81                       ;
-;                                             ;                          ;
-; Combinational ALUT usage for logic          ; 136                      ;
-;     -- 7 input functions                    ; 1                        ;
-;     -- 6 input functions                    ; 24                       ;
-;     -- 5 input functions                    ; 5                        ;
-;     -- 4 input functions                    ; 39                       ;
-;     -- <=3 input functions                  ; 67                       ;
-;                                             ;                          ;
-; Dedicated logic registers                   ; 64                       ;
-;                                             ;                          ;
-; I/O pins                                    ; 36                       ;
-;                                             ;                          ;
-; Total DSP Blocks                            ; 0                        ;
-;                                             ;                          ;
-; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;
-; Maximum fan-out                             ; 47                       ;
-; Total fan-out                               ; 706                      ;
-; Average fan-out                             ; 2.60                     ;
-+---------------------------------------------+--------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                 ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex8                       ; 136 (1)             ; 64 (0)                    ; 0                 ; 0          ; 36   ; 0            ; |ex8                             ; ex8         ; work         ;
-;    |LFSR:LFSR0|            ; 3 (3)               ; 7 (7)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 14 (0)              ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A22|       ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;    |delay:DEL0|            ; 25 (25)             ; 18 (18)                   ; 0                 ; 0          ; 0    ; 0            ; |ex8|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 37 (37)             ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |ex8|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 13 (13)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |tick_50000:TICK0|      ; 36 (36)             ; 17 (17)                   ; 0                 ; 0          ; 0    ; 0            ; |ex8|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------+
-; State Machine - |ex8|delay:DEL0|state                                          ;
-+----------------+----------------+----------------+----------------+------------+
-; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
-+----------------+----------------+----------------+----------------+------------+
-; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;
-; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;
-; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;
-; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;
-+----------------+----------------+----------------+----------------+------------+
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------------------+
-; State Machine - |ex8|formula_fsm:FSM|state                                                 ;
-+------------------------+--------------------+------------------------+---------------------+
-; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
-+------------------------+--------------------+------------------------+---------------------+
-; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;
-; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;
-; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;
-+------------------------+--------------------+------------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches                                                                               ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;
-; Number of user-specified and inferred latches = 1  ;                                     ;                        ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------+
-; Registers Removed During Synthesis                         ;
-+---------------------------------------+--------------------+
-; Register name                         ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; delay:DEL0|state~5                    ; Lost fanout        ;
-; delay:DEL0|state~6                    ; Lost fanout        ;
-; Total Number of Removed Registers = 2 ;                    ;
-+---------------------------------------+--------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 64    ;
-; Number of registers using Synchronous Clear  ; 0     ;
-; Number of registers using Synchronous Load   ; 15    ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 27    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+---------------------------------------------------+
-; Inverted Register Statistics                      ;
-+-----------------------------------------+---------+
-; Inverted Register                       ; Fan out ;
-+-----------------------------------------+---------+
-; LFSR:LFSR0|COUNT[1]                     ; 10      ;
-; tick_50000:TICK0|count[14]              ; 2       ;
-; tick_50000:TICK0|count[15]              ; 2       ;
-; tick_50000:TICK0|count[0]               ; 2       ;
-; tick_50000:TICK0|count[1]               ; 2       ;
-; tick_50000:TICK0|count[2]               ; 2       ;
-; tick_50000:TICK0|count[3]               ; 2       ;
-; tick_50000:TICK0|count[6]               ; 2       ;
-; tick_50000:TICK0|count[8]               ; 2       ;
-; tick_50000:TICK0|count[9]               ; 2       ;
-; Total number of inverted registers = 10 ;         ;
-+-----------------------------------------+---------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                               ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output     ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |ex8|formula_fsm:FSM|count[4]  ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex8|delay:DEL0|count[6]       ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex8|delay:DEL0|count[7]       ;
-; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex8|formula_fsm:FSM|Selector4 ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex8|delay:DEL0|Selector16     ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex8|delay:DEL0|Selector17     ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
-+----------------+-------+--------------------------------------+
-; Parameter Name ; Value ; Type                                 ;
-+----------------+-------+--------------------------------------+
-; NBIT           ; 16    ; Signed Integer                       ;
-+----------------+-------+--------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;
-+----------------+-------+-------------------------------------+
-; Parameter Name ; Value ; Type                                ;
-+----------------+-------+-------------------------------------+
-; NBIT           ; 12    ; Signed Integer                      ;
-+----------------+-------+-------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
-+------------------+-------+-----------------------------------+
-; Parameter Name   ; Value ; Type                              ;
-+------------------+-------+-----------------------------------+
-; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;
-; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;
-; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;
-+------------------+-------+-----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------+
-; Parameter Settings for User Entity Instance: delay:DEL0 ;
-+----------------+-------+--------------------------------+
-; Parameter Name ; Value ; Type                           ;
-+----------------+-------+--------------------------------+
-; BIT_SZ         ; 14    ; Signed Integer                 ;
-; IDLE           ; 00    ; Unsigned Binary                ;
-; COUNTING       ; 01    ; Unsigned Binary                ;
-; TIME_OUT       ; 10    ; Unsigned Binary                ;
-; WAIT_LOW       ; 11    ; Unsigned Binary                ;
-+----------------+-------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; Port  ; Type   ; Severity ; Details                                                                             ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
-; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD"                                                                                                                              ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port  ; Type   ; Severity ; Details                                                                                                                                     ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; B     ; Input  ; Warning  ; Input port expression (7 bits) is smaller than the input port (16 bits) it drives.  Extra input bit(s) "B[15..7]" will be connected to GND. ;
-; BCD_3 ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                         ;
-; BCD_4 ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                         ;
-+-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type  ; Severity ; Details                                                                                                                                     ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type                  ; Count                       ;
-+-----------------------+-----------------------------+
-; arriav_ff             ; 64                          ;
-;     ENA               ; 13                          ;
-;     ENA SLD           ; 14                          ;
-;     SLD               ; 1                           ;
-;     plain             ; 36                          ;
-; arriav_lcell_comb     ; 140                         ;
-;     arith             ; 39                          ;
-;         1 data inputs ; 39                          ;
-;     extend            ; 1                           ;
-;         7 data inputs ; 1                           ;
-;     normal            ; 100                         ;
-;         0 data inputs ; 2                           ;
-;         1 data inputs ; 14                          ;
-;         2 data inputs ; 9                           ;
-;         3 data inputs ; 7                           ;
-;         4 data inputs ; 39                          ;
-;         5 data inputs ; 5                           ;
-;         6 data inputs ; 24                          ;
-; boundary_port         ; 36                          ;
-;                       ;                             ;
-; Max LUT depth         ; 6.00                        ;
-; Average LUT depth     ; 2.82                        ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:00     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 20:24:53 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
-    Info (12023): Found entity 1: tick_50000 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v
-    Info (12023): Found entity 1: LFSR File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
-    Info (12023): Found entity 1: hex_to_7seg File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
-    Info (12023): Found entity 1: counter_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v Line: 3
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
-    Info (12023): Found entity 1: bin2bcd_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
-    Info (12023): Found entity 1: add3_ge5 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v Line: 9
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
-    Info (12023): Found entity 1: formula_fsm File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
-    Info (12023): Found entity 1: delay File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v
-    Info (12023): Found entity 1: tick_2500 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex8.v
-    Info (12023): Found entity 1: ex8 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 1
-Info (12127): Elaborating entity "ex8" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 13
-Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 14
-Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 15
-Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 39
-Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
-Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
-Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 16
-Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 17
-Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 24
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 18
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 19
-Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
-    Warning (13410): Pin "HEX2[1]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
-    Warning (13410): Pin "HEX2[2]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
-    Warning (13410): Pin "HEX2[6]" is stuck at VCC File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 2 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 3 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "KEY[0]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
-    Warning (15610): No output dependent on input pin "KEY[1]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
-    Warning (15610): No output dependent on input pin "KEY[2]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
-Info (21057): Implemented 178 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 5 input pins
-    Info (21059): Implemented 31 output pins
-    Info (21061): Implemented 142 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
-    Info: Peak virtual memory: 1054 megabytes
-    Info: Processing ended: Sun Dec 11 20:25:03 2016
-    Info: Elapsed time: 00:00:10
-    Info: Total CPU time (on all processors): 00:00:24
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg.
-
-
+Analysis & Synthesis report for ex8
+Wed Dec 07 12:21:24 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. State Machine - |ex8|delay:DEL0|state
+  9. State Machine - |ex8|formula_fsm:FSM|state
+ 10. User-Specified and Inferred Latches
+ 11. Registers Removed During Synthesis
+ 12. General Register Statistics
+ 13. Inverted Register Statistics
+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
+ 16. Parameter Settings for User Entity Instance: tick_2500:TICK1
+ 17. Parameter Settings for User Entity Instance: formula_fsm:FSM
+ 18. Parameter Settings for User Entity Instance: delay:DEL0
+ 19. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
+ 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
+ 24. Port Connectivity Checks: "bin2bcd_16:BCD"
+ 25. Port Connectivity Checks: "delay:DEL0"
+ 26. Post-Synthesis Netlist Statistics for Top Partition
+ 27. Elapsed Time Per Partition
+ 28. Analysis & Synthesis Messages
+ 29. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Wed Dec 07 12:21:23 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex8                                             ;
+; Top-level Entity Name           ; ex8                                             ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 67                                              ;
+; Total pins                      ; 36                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0                                               ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex8                ; ex8                ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                              ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                ; Library ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
+; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v  ;         ;
+; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v        ;         ;
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v ;         ;
+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v  ;         ;
+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v    ;         ;
+; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v ;         ;
+; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v       ;         ;
+; verilog_files/tick_2500.v        ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v   ;         ;
+; verilog_files/ex8.v              ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v         ;         ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                            ;
++---------------------------------------------+--------------------------+
+; Resource                                    ; Usage                    ;
++---------------------------------------------+--------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 86                       ;
+;                                             ;                          ;
+; Combinational ALUT usage for logic          ; 142                      ;
+;     -- 7 input functions                    ; 0                        ;
+;     -- 6 input functions                    ; 29                       ;
+;     -- 5 input functions                    ; 5                        ;
+;     -- 4 input functions                    ; 40                       ;
+;     -- <=3 input functions                  ; 68                       ;
+;                                             ;                          ;
+; Dedicated logic registers                   ; 67                       ;
+;                                             ;                          ;
+; I/O pins                                    ; 36                       ;
+;                                             ;                          ;
+; Total DSP Blocks                            ; 0                        ;
+;                                             ;                          ;
+; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;
+; Maximum fan-out                             ; 50                       ;
+; Total fan-out                               ; 739                      ;
+; Average fan-out                             ; 2.63                     ;
++---------------------------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex8                       ; 142 (1)           ; 67 (0)       ; 0                 ; 0          ; 36   ; 0            ; |ex8                             ; ex8         ; work         ;
+;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|LFSR:LFSR0                  ; LFSR        ; work         ;
+;    |bin2bcd_16:BCD|        ; 13 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
+;       |add3_ge5:A22|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
+;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
+;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
+;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
+;    |delay:DEL0|            ; 25 (25)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex8|delay:DEL0                  ; delay       ; work         ;
+;    |formula_fsm:FSM|       ; 43 (43)           ; 25 (25)      ; 0                 ; 0          ; 0    ; 0            ; |ex8|formula_fsm:FSM             ; formula_fsm ; work         ;
+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex8|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
+;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex8|tick_50000:TICK0            ; tick_50000  ; work         ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |ex8|delay:DEL0|state                                          ;
++----------------+----------------+----------------+----------------+------------+
+; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
++----------------+----------------+----------------+----------------+------------+
+; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;
+; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;
+; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;
+; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;
++----------------+----------------+----------------+----------------+------------+
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------------------+
+; State Machine - |ex8|formula_fsm:FSM|state                                                 ;
++------------------------+--------------------+------------------------+---------------------+
+; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
++------------------------+--------------------+------------------------+---------------------+
+; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;
+; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;
+; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;
++------------------------+--------------------+------------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches                                                                               ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;
+; Number of user-specified and inferred latches = 1  ;                                     ;                        ;
++----------------------------------------------------+-------------------------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------------+
+; Registers Removed During Synthesis                         ;
++---------------------------------------+--------------------+
+; Register name                         ; Reason for Removal ;
++---------------------------------------+--------------------+
+; delay:DEL0|state~5                    ; Lost fanout        ;
+; delay:DEL0|state~6                    ; Lost fanout        ;
+; Total Number of Removed Registers = 2 ;                    ;
++---------------------------------------+--------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 67    ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 15    ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 26    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------+
+; Inverted Register Statistics                      ;
++-----------------------------------------+---------+
+; Inverted Register                       ; Fan out ;
++-----------------------------------------+---------+
+; LFSR:LFSR0|COUNT[1]                     ; 10      ;
+; tick_50000:TICK0|count[14]              ; 2       ;
+; tick_50000:TICK0|count[15]              ; 2       ;
+; tick_50000:TICK0|count[0]               ; 2       ;
+; tick_50000:TICK0|count[1]               ; 2       ;
+; tick_50000:TICK0|count[2]               ; 2       ;
+; tick_50000:TICK0|count[3]               ; 2       ;
+; tick_50000:TICK0|count[6]               ; 2       ;
+; tick_50000:TICK0|count[8]               ; 2       ;
+; tick_50000:TICK0|count[9]               ; 2       ;
+; Total number of inverted registers = 10 ;         ;
++-----------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                               ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output     ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |ex8|formula_fsm:FSM|count[11] ;
+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex8|delay:DEL0|count[0]       ;
+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex8|delay:DEL0|count[9]       ;
+; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex8|formula_fsm:FSM|Selector3 ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex8|delay:DEL0|Selector15     ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex8|delay:DEL0|Selector14     ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+
+
++---------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
++----------------+-------+--------------------------------------+
+; Parameter Name ; Value ; Type                                 ;
++----------------+-------+--------------------------------------+
+; NBIT           ; 16    ; Signed Integer                       ;
++----------------+-------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; NBIT           ; 12    ; Signed Integer                      ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
++------------------+-------+-----------------------------------+
+; Parameter Name   ; Value ; Type                              ;
++------------------+-------+-----------------------------------+
+; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;
+; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;
+; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;
++------------------+-------+-----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------+
+; Parameter Settings for User Entity Instance: delay:DEL0 ;
++----------------+-------+--------------------------------+
+; Parameter Name ; Value ; Type                           ;
++----------------+-------+--------------------------------+
+; BIT_SZ         ; 14    ; Signed Integer                 ;
+; IDLE           ; 00    ; Unsigned Binary                ;
+; COUNTING       ; 01    ; Unsigned Binary                ;
+; TIME_OUT       ; 10    ; Unsigned Binary                ;
+; WAIT_LOW       ; 11    ; Unsigned Binary                ;
++----------------+-------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; Port  ; Type   ; Severity ; Details                                                                             ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
+; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
++-------+-------+----------+------------------------------+
+; Port  ; Type  ; Severity ; Details                      ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                 ;
++-------+-------+----------+------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
++-------+-------+----------+------------------------------+
+; Port  ; Type  ; Severity ; Details                      ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                 ;
++-------+-------+----------+------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
++-------+-------+----------+-----------------------------+
+; Port  ; Type  ; Severity ; Details                     ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                ;
++-------+-------+----------+-----------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
++-------+-------+----------+-----------------------------+
+; Port  ; Type  ; Severity ; Details                     ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                ;
++-------+-------+----------+-----------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD"                                                                                                                              ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port  ; Type   ; Severity ; Details                                                                                                                                     ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; B     ; Input  ; Warning  ; Input port expression (7 bits) is smaller than the input port (16 bits) it drives.  Extra input bit(s) "B[15..7]" will be connected to GND. ;
+; BCD_3 ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                         ;
+; BCD_4 ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                         ;
++-------+--------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                                                                                                     ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 67                          ;
+;     ENA               ; 12                          ;
+;     ENA SLD           ; 14                          ;
+;     SLD               ; 1                           ;
+;     plain             ; 40                          ;
+; arriav_lcell_comb     ; 145                         ;
+;     arith             ; 42                          ;
+;         1 data inputs ; 42                          ;
+;     normal            ; 103                         ;
+;         0 data inputs ; 2                           ;
+;         1 data inputs ; 13                          ;
+;         2 data inputs ; 8                           ;
+;         3 data inputs ; 6                           ;
+;         4 data inputs ; 40                          ;
+;         5 data inputs ; 5                           ;
+;         6 data inputs ; 29                          ;
+; boundary_port         ; 36                          ;
+;                       ;                             ;
+; Max LUT depth         ; 6.00                        ;
+; Average LUT depth     ; 2.87                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:21:11 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex8 -c ex8
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
+    Info (12023): Found entity 1: tick_50000 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_50000.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
+    Info (12023): Found entity 1: LFSR File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/LFSR.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
+    Info (12023): Found entity 1: counter_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/counter_16.v Line: 3
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
+    Info (12023): Found entity 1: formula_fsm File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
+    Info (12023): Found entity 1: delay File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v
+    Info (12023): Found entity 1: tick_2500 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/tick_2500.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex8.v
+    Info (12023): Found entity 1: ex8 File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 1
+Info (12127): Elaborating entity "ex8" for the top level hierarchy
+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 13
+Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 14
+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 15
+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 39
+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 58
+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 16
+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 17
+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 24
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 18
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 19
+Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX2[1]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+    Warning (13410): Pin "HEX2[2]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+    Warning (13410): Pin "HEX2[6]" is stuck at VCC File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 6
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 2 registers lost all their fanouts during netlist optimizations.
+Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 3 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "KEY[0]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+    Warning (15610): No output dependent on input pin "KEY[1]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+    Warning (15610): No output dependent on input pin "KEY[2]" File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/ex8.v Line: 4
+Info (21057): Implemented 184 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 5 input pins
+    Info (21059): Implemented 31 output pins
+    Info (21061): Implemented 148 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
+    Info: Peak virtual memory: 895 megabytes
+    Info: Processing ended: Wed Dec 07 12:21:24 2016
+    Info: Elapsed time: 00:00:13
+    Info: Total CPU time (on all processors): 00:00:22
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex8/output_files/ex8.map.smsg.
+
+
diff --git a/part_2/ex8/output_files/ex8.map.smsg b/part_2/ex8/output_files/ex8.map.smsg
index 79c40b9..c655eb9 100755
--- a/part_2/ex8/output_files/ex8.map.smsg
+++ b/part_2/ex8/output_files/ex8.map.smsg
@@ -1,37 +1,37 @@
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
-Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 38
-Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/bin2bcd_16.v Line: 22
+Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/formula_fsm.v Line: 38
+Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex8/verilog_files/delay.v Line: 7
diff --git a/part_2/ex8/output_files/ex8.map.summary b/part_2/ex8/output_files/ex8.map.summary
index f52138b..00a2e0f 100755
--- a/part_2/ex8/output_files/ex8.map.summary
+++ b/part_2/ex8/output_files/ex8.map.summary
@@ -1,17 +1,17 @@
-Analysis & Synthesis Status : Successful - Sun Dec 11 20:25:03 2016
-Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Revision Name : ex8
-Top-level Entity Name : ex8
-Family : Cyclone V
-Logic utilization (in ALMs) : N/A
-Total registers : 64
-Total pins : 36
-Total virtual pins : 0
-Total block memory bits : 0
-Total DSP Blocks : 0
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0
-Total DLLs : 0
+Analysis & Synthesis Status : Successful - Wed Dec 07 12:21:23 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex8
+Top-level Entity Name : ex8
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 67
+Total pins : 36
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_2/ex8/output_files/ex8.pin b/part_2/ex8/output_files/ex8.pin
index 4e698e3..7f57443 100755
--- a/part_2/ex8/output_files/ex8.pin
+++ b/part_2/ex8/output_files/ex8.pin
@@ -1,977 +1,976 @@
- -- Copyright (C) 2016  Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Intel Program License 
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel MegaCore Function License Agreement, or other 
- -- applicable license agreement, including, without limitation, 
- -- that your use is for the sole purpose of programming logic 
- -- devices manufactured by Intel and sold by Intel or its 
- -- authorized distributors.  Please refer to the applicable 
- -- agreement for further details.
- -- 
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --                  Bank 3A:       2.5V
- --                  Bank 3B:       3.3V
- --                  Bank 4A:       3.3V
- --                  Bank 5A:       3.3V
- --                  Bank 5B:       3.3V
- --                  Bank 6B:       2.5V
- --                  Bank 6A:  2.5V
- --                  Bank 7A:  2.5V
- --                  Bank 7B:  2.5V
- --                  Bank 7C:  2.5V
- --                  Bank 7D:  2.5V
- --                  Bank 8A:  2.5V
- --                  Bank 9A:  Dedicated configuration pins only, no VCCIO required.
- -- RREF          : External reference resistor for the quad, MUST be connected to
- --                 GND via a 2k Ohm resistor.
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --                  It can also be used to report unused dedicated pins. The connection
- --                  on the board for unused dedicated pins depends on whether this will
- --                  be used in a future design. One example is device migration. When
- --                  using device migration, refer to the device pin-tables. If it is a
- --                  GND pin in the pin table or if it will not be used in a future design
- --                  for another purpose the it MUST be connected to GND. If it is an unused
- --                  dedicated pin, then it can be connected to a valid signal on the board
- --                  (low, high, or toggling) if that signal is required for a different
- --                  revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --                  This pin should be connected to GND. It may also be connected  to a
- --                  valid signal  on the board  (low, high, or toggling)  if that signal
- --                  is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --                  or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
- --                 must not be connected.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-CHIP  "ex8"  ASSIGNED TO AN: 5CSEMA5F31C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A2        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
-VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
-GND                          : A12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
-GND                          : A17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
-GND                          : A26       :        :                   :         : 7A        :                
-GND                          : A27       : gnd    :                   :         :           :                
-HPS_TRST                     : A28       :        :                   :         : 7A        :                
-HPS_TMS                      : A29       :        :                   :         : 7A        :                
-GND                          : AA1       : gnd    :                   :         :           :                
-GND                          : AA2       : gnd    :                   :         :           :                
-GND                          : AA3       : gnd    :                   :         :           :                
-GND                          : AA4       : gnd    :                   :         :           :                
-VCC                          : AA5       : power  :                   : 1.1V    :           :                
-GND                          : AA6       : gnd    :                   :         :           :                
-DNU                          : AA7       :        :                   :         :           :                
-VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
-GND                          : AA9       : gnd    :                   :         :           :                
-VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
-GND                          : AA11      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
-KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
-VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
-GND                          : AA22      : gnd    :                   :         :           :                
-VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24      :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
-VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
-VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
-GND                          : AB1       : gnd    :                   :         :           :                
-GND                          : AB2       : gnd    :                   :         :           :                
-DNU                          : AB3       :        :                   :         :           :                
-DNU                          : AB4       :        :                   :         :           :                
-GND                          : AB5       : gnd    :                   :         :           :                
-VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
-GND                          : AB7       : gnd    :                   :         :           :                
-nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
-TDO                          : AB9       : output :                   :         : 3A        :                
-VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
-VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
-VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
-VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
-GND                          : AB19      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 5A        :                
-HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB25      :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                
-GND                          : AB29      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
-GND                          : AC1       : gnd    :                   :         :           :                
-GND                          : AC2       : gnd    :                   :         :           :                
-GND                          : AC3       : gnd    :                   :         :           :                
-GND                          : AC4       : gnd    :                   :         :           :                
-TCK                          : AC5       : input  :                   :         : 3A        :                
-GND                          : AC6       : gnd    :                   :         :           :                
-AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
-GND                          : AC8       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
-VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
-VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
-VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
-VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
-GND                          : AC16      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
-VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
-VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
-VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                
-GND                          : AC26      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                
-HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AD1       : gnd    :                   :         :           :                
-GND                          : AD2       : gnd    :                   :         :           :                
-DNU                          : AD3       :        :                   :         :           :                
-DNU                          : AD4       :        :                   :         :           :                
-GND                          : AD5       : gnd    :                   :         :           :                
-VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
-VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
-VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
-DNU                          : AD15      :        :                   :         :           :                
-VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
-VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
-VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
-GND                          : AD23      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26      :        :                   :         : 5A        :                
-HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
-HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AE1       : gnd    :                   :         :           :                
-GND                          : AE2       : gnd    :                   :         :           :                
-GND                          : AE3       : gnd    :                   :         :           :                
-GND                          : AE4       : gnd    :                   :         :           :                
-AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
-AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
-AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
-GND                          : AE10      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
-VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
-GND                          : AE20      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
-VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
-HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
-GND                          : AF1       : gnd    :                   :         :           :                
-GND                          : AF2       : gnd    :                   :         :           :                
-GND                          : AF3       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
-VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
-GND                          : AF12      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
-CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
-GND                          : AF17      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
-VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
-GND                          : AF27      : gnd    :                   :         :           :                
-HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
-VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
-GND                          : AG9       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
-GND                          : AG14      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
-VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
-GND                          : AG24      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
-HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
-HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AH1       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
-GND                          : AH6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
-GND                          : AH11      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
-VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
-GND                          : AH21      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
-VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
-HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
-GND                          : AJ3       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
-VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
-VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
-VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
-GND                          : AJ18      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
-VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
-GND                          : AJ28      : gnd    :                   :         :           :                
-HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AJ30      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
-GND                          : AK5       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
-VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
-GND                          : AK15      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
-VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
-VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
-GND                          : AK25      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
-VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
-GND                          : B9        : gnd    :                   :         :           :                
-VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
-GND                          : B14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
-GND                          : B19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
-GND                          : B24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
-HPS_TDI                      : B27       :        :                   :         : 7A        :                
-HPS_TDO                      : B28       :        :                   :         : 7A        :                
-GND                          : B29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
-GND                          : C1        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
-GND                          : C6        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
-VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
-GND                          : C21       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
-GND                          : C26       : gnd    :                   :         :           :                
-HPS_nRST                     : C27       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
-GND                          : D3        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
-VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
-GND                          : D13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
-VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
-GND                          : D23       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
-HPS_CLK1                     : D25       :        :                   :         : 7A        :                
-GND                          : D26       :        :                   :         : 7A        :                
-HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
-VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
-GND                          : E10       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
-VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
-VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
-VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
-GND                          : E25       : gnd    :                   :         :           :                
-DNU                          : E26       :        :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
-GND                          : E30       : gnd    :                   :         :           :                
-DNU                          : F1        :        :                   :         :           :                
-GND                          : F2        : gnd    :                   :         :           :                
-CONF_DONE                    : F3        :        :                   :         : 9A        :                
-nSTATUS                      : F4        :        :                   :         : 9A        :                
-GND                          : F5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
-GND                          : F7        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
-VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
-GND                          : F17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
-VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
-HPS_nPOR                     : F23       :        :                   :         : 7A        :                
-HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
-HPS_CLK2                     : F25       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
-GND                          : F27       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
-GND                          : G1        :        :                   :         :           :                
-DNU                          : G2        :        :                   :         :           :                
-GND                          : G3        : gnd    :                   :         :           :                
-GND                          : G4        : gnd    :                   :         :           :                
-nCE                          : G5        :        :                   :         : 9A        :                
-MSEL2                        : G6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
-VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
-VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
-VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
-VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
-GND                          : G24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
-GND                          : H1        : gnd    :                   :         :           :                
-GND                          : H2        : gnd    :                   :         :           :                
-DNU                          : H3        :        :                   :         :           :                
-DNU                          : H4        :        :                   :         :           :                
-GND                          : H5        : gnd    :                   :         :           :                
-VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
-VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
-VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
-GND                          : H11       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
-VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
-VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
-HPS_TCK                      : H22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
-GND                          : J1        : gnd    :                   :         :           :                
-GND                          : J2        : gnd    :                   :         :           :                
-GND                          : J3        : gnd    :                   :         :           :                
-GND                          : J4        : gnd    :                   :         :           :                
-nCONFIG                      : J5        :        :                   :         : 9A        :                
-GND                          : J6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
-GND                          : J8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
-VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
-VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
-DNU                          : J15       :        :                   :         :           :                
-VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
-VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
-GND                          : J18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
-VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
-GND                          : J22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
-GND                          : J28       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
-GND                          : K1        : gnd    :                   :         :           :                
-GND                          : K2        : gnd    :                   :         :           :                
-DNU                          : K3        :        :                   :         :           :                
-DNU                          : K4        :        :                   :         :           :                
-GND                          : K5        : gnd    :                   :         :           :                
-MSEL1                        : K6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
-VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
-VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
-GND                          : K15       : gnd    :                   :         :           :                
-VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
-VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
-VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
-GND                          : K20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
-GND                          : K25       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
-GND                          : L1        : gnd    :                   :         :           :                
-GND                          : L2        : gnd    :                   :         :           :                
-GND                          : L3        : gnd    :                   :         :           :                
-GND                          : L4        : gnd    :                   :         :           :                
-VCC                          : L5        : power  :                   : 1.1V    :           :                
-GND                          : L6        : gnd    :                   :         :           :                
-MSEL3                        : L7        :        :                   :         : 9A        :                
-MSEL0                        : L8        :        :                   :         : 9A        :                
-MSEL4                        : L9        :        :                   :         : 9A        :                
-VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
-GND                          : L11       : gnd    :                   :         :           :                
-VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
-GND                          : L15       : gnd    :                   :         :           :                
-VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
-GND                          : L17       : gnd    :                   :         :           :                
-VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
-GND                          : L19       : gnd    :                   :         :           :                
-VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
-VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
-GND                          : L22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
-GND                          : M1        : gnd    :                   :         :           :                
-GND                          : M2        : gnd    :                   :         :           :                
-DNU                          : M3        :        :                   :         :           :                
-DNU                          : M4        :        :                   :         :           :                
-GND                          : M5        : gnd    :                   :         :           :                
-VCC                          : M6        : power  :                   : 1.1V    :           :                
-GND                          : M7        : gnd    :                   :         :           :                
-GND                          : M8        : gnd    :                   :         :           :                
-VCC                          : M9        : power  :                   : 1.1V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-VCC                          : M11       : power  :                   : 1.1V    :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-VCC                          : M13       : power  :                   : 1.1V    :           :                
-GND                          : M14       : gnd    :                   :         :           :                
-VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
-GND                          : M16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
-GND                          : M18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
-GND                          : M20       : gnd    :                   :         :           :                
-VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
-GND                          : M29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
-GND                          : N1        : gnd    :                   :         :           :                
-GND                          : N2        : gnd    :                   :         :           :                
-GND                          : N3        : gnd    :                   :         :           :                
-GND                          : N4        : gnd    :                   :         :           :                
-VCC                          : N5        : power  :                   : 1.1V    :           :                
-GND                          : N6        : gnd    :                   :         :           :                
-VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
-GND                          : N8        : gnd    :                   :         :           :                
-GND                          : N9        : gnd    :                   :         :           :                
-VCC                          : N10       : power  :                   : 1.1V    :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-VCC                          : N12       : power  :                   : 1.1V    :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-VCC                          : N14       : power  :                   : 1.1V    :           :                
-GND                          : N15       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
-GND                          : N17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
-GND                          : N19       : gnd    :                   :         :           :                
-VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
-VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
-VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
-GND                          : N26       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
-GND                          : P1        : gnd    :                   :         :           :                
-GND                          : P2        : gnd    :                   :         :           :                
-DNU                          : P3        :        :                   :         :           :                
-DNU                          : P4        :        :                   :         :           :                
-GND                          : P5        : gnd    :                   :         :           :                
-VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
-GND                          : P7        : gnd    :                   :         :           :                
-GND                          : P8        : gnd    :                   :         :           :                
-GND                          : P9        : gnd    :                   :         :           :                
-GND                          : P10       : gnd    :                   :         :           :                
-VCC                          : P11       : power  :                   : 1.1V    :           :                
-GND                          : P12       : gnd    :                   :         :           :                
-VCC                          : P13       : power  :                   : 1.1V    :           :                
-GND                          : P14       : gnd    :                   :         :           :                
-VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
-GND                          : P16       : gnd    :                   :         :           :                
-VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
-GND                          : P18       : gnd    :                   :         :           :                
-VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
-GND                          : P20       : gnd    :                   :         :           :                
-VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
-GND                          : R1        : gnd    :                   :         :           :                
-GND                          : R2        : gnd    :                   :         :           :                
-GND                          : R3        : gnd    :                   :         :           :                
-GND                          : R4        : gnd    :                   :         :           :                
-VCC                          : R5        : power  :                   : 1.1V    :           :                
-GND                          : R6        : gnd    :                   :         :           :                
-VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
-GND                          : R8        : gnd    :                   :         :           :                
-GND                          : R9        : gnd    :                   :         :           :                
-VCC                          : R10       : power  :                   : 1.1V    :           :                
-GND                          : R11       : gnd    :                   :         :           :                
-VCC                          : R12       : power  :                   : 1.1V    :           :                
-GND                          : R13       : gnd    :                   :         :           :                
-VCC                          : R14       : power  :                   : 1.1V    :           :                
-GND                          : R15       : gnd    :                   :         :           :                
-VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
-GND                          : R17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
-VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
-VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
-GND                          : R30       : gnd    :                   :         :           :                
-GND                          : T1        : gnd    :                   :         :           :                
-GND                          : T2        : gnd    :                   :         :           :                
-DNU                          : T3        :        :                   :         :           :                
-DNU                          : T4        :        :                   :         :           :                
-GND                          : T5        : gnd    :                   :         :           :                
-VCC                          : T6        : power  :                   : 1.1V    :           :                
-GND                          : T7        : gnd    :                   :         :           :                
-GND                          : T8        : gnd    :                   :         :           :                
-GND                          : T9        : gnd    :                   :         :           :                
-GND                          : T10       : gnd    :                   :         :           :                
-VCC                          : T11       : power  :                   : 1.1V    :           :                
-GND                          : T12       : gnd    :                   :         :           :                
-VCC                          : T13       : power  :                   : 1.1V    :           :                
-GND                          : T14       : gnd    :                   :         :           :                
-GND                          : T15       : gnd    :                   :         :           :                
-GND                          : T16       : gnd    :                   :         :           :                
-VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
-GND                          : T18       : gnd    :                   :         :           :                
-VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
-GND                          : T20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
-GND                          : T27       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
-GND                          : U1        : gnd    :                   :         :           :                
-GND                          : U2        : gnd    :                   :         :           :                
-GND                          : U3        : gnd    :                   :         :           :                
-GND                          : U4        : gnd    :                   :         :           :                
-VCC                          : U5        : power  :                   : 1.1V    :           :                
-GND                          : U6        : gnd    :                   :         :           :                
-DCLK                         : U7        :        :                   :         : 3A        :                
-TDI                          : U8        : input  :                   :         : 3A        :                
-GND                          : U9        : gnd    :                   :         :           :                
-VCC                          : U10       : power  :                   : 1.1V    :           :                
-GND                          : U11       : gnd    :                   :         :           :                
-VCC                          : U12       : power  :                   : 1.1V    :           :                
-GND                          : U13       : gnd    :                   :         :           :                
-VCC                          : U14       : power  :                   : 1.1V    :           :                
-GND                          : U15       : gnd    :                   :         :           :                
-VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
-GND                          : U17       : gnd    :                   :         :           :                
-VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
-VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
-VCC                          : U21       : power  :                   : 1.1V    :           :                
-GND                          : U22       : gnd    :                   :         :           :                
-VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
-GND                          : U24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
-GND                          : U29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
-GND                          : V1        : gnd    :                   :         :           :                
-GND                          : V2        : gnd    :                   :         :           :                
-DNU                          : V3        :        :                   :         :           :                
-DNU                          : V4        :        :                   :         :           :                
-GND                          : V5        : gnd    :                   :         :           :                
-VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
-GND                          : V7        : gnd    :                   :         :           :                
-VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
-TMS                          : V9        : input  :                   :         : 3A        :                
-GND                          : V10       : gnd    :                   :         :           :                
-VCC                          : V11       : power  :                   : 1.1V    :           :                
-GND                          : V12       : gnd    :                   :         :           :                
-VCC                          : V13       : power  :                   : 1.1V    :           :                
-GND                          : V14       : gnd    :                   :         :           :                
-VCC                          : V15       : power  :                   : 1.1V    :           :                
-LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : V19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
-GND                          : V21       : gnd    :                   :         :           :                
-VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23       :        :                   :         : 5A        :                
-VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
-VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
-GND                          : W1        : gnd    :                   :         :           :                
-GND                          : W2        : gnd    :                   :         :           :                
-GND                          : W3        : gnd    :                   :         :           :                
-GND                          : W4        : gnd    :                   :         :           :                
-VCC                          : W5        : power  :                   : 1.1V    :           :                
-GND                          : W6        : gnd    :                   :         :           :                
-GND                          : W7        : gnd    :                   :         :           :                
-GND                          : W8        : gnd    :                   :         :           :                
-GND                          : W9        : gnd    :                   :         :           :                
-VCC                          : W10       : power  :                   : 1.1V    :           :                
-GND                          : W11       : gnd    :                   :         :           :                
-VCC                          : W12       : power  :                   : 1.1V    :           :                
-GND                          : W13       : gnd    :                   :         :           :                
-VCC                          : W14       : power  :                   : 1.1V    :           :                
-KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              
-LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : W18       : gnd    :                   :         :           :                
-LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              
-LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5A        :                
-VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W24       :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
-GND                          : W28       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
-GND                          : Y1        : gnd    :                   :         :           :                
-GND                          : Y2        : gnd    :                   :         :           :                
-DNU                          : Y3        :        :                   :         :           :                
-DNU                          : Y4        :        :                   :         :           :                
-GND                          : Y5        : gnd    :                   :         :           :                
-VCC                          : Y6        : power  :                   : 1.1V    :           :                
-GND                          : Y7        : gnd    :                   :         :           :                
-GND                          : Y8        : gnd    :                   :         :           :                
-VCC                          : Y9        : power  :                   : 1.1V    :           :                
-GND                          : Y10       : gnd    :                   :         :           :                
-VCC                          : Y11       : power  :                   : 1.1V    :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-VCC                          : Y13       : power  :                   : 1.1V    :           :                
-GND                          : Y14       : gnd    :                   :         :           :                
-GND                          : Y15       : gnd    :                   :         :           :                
-KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
-LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : Y20       : gnd    :                   :         :           :                
-LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y23       :        :                   :         : 5A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24       :        :                   :         : 5A        :                
-GND                          : Y25       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
-GND                          : Y30       : gnd    :                   :         :           :                
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       2.5V
+ --                  Bank 3B:       3.3V
+ --                  Bank 4A:       3.3V
+ --                  Bank 5A:       3.3V
+ --                  Bank 5B:       3.3V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex8"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 5A        :                
+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                
+GND                          : AC26      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                
+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26      :        :                   :         : 5A        :                
+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23       :        :                   :         : 5A        :                
+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              
+LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : W18       : gnd    :                   :         :           :                
+LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              
+LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5A        :                
+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : Y20       : gnd    :                   :         :           :                
+LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24       :        :                   :         : 5A        :                
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_2/ex8/output_files/ex8.sld b/part_2/ex8/output_files/ex8.sld
index f7d3ed7..41a6030 100755
--- a/part_2/ex8/output_files/ex8.sld
+++ b/part_2/ex8/output_files/ex8.sld
@@ -1 +1 @@
-<sld_project_info/>
+<sld_project_info/>
diff --git a/part_2/ex8/output_files/ex8.sof b/part_2/ex8/output_files/ex8.sof
index aa1c290..ee348cb 100755
--- a/part_2/ex8/output_files/ex8.sof
+++ b/part_2/ex8/output_files/ex8.sof
diff --git a/part_2/ex8/output_files/ex8.sta.rpt b/part_2/ex8/output_files/ex8.sta.rpt
index 5e481c2..d9b936c 100755
--- a/part_2/ex8/output_files/ex8.sta.rpt
+++ b/part_2/ex8/output_files/ex8.sta.rpt
@@ -1,864 +1,864 @@
-TimeQuest Timing Analyzer report for ex8
-Sun Dec 11 20:25:48 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Slow 1100mV 85C Model Fmax Summary
-  6. Timing Closure Recommendations
-  7. Slow 1100mV 85C Model Setup Summary
-  8. Slow 1100mV 85C Model Hold Summary
-  9. Slow 1100mV 85C Model Recovery Summary
- 10. Slow 1100mV 85C Model Removal Summary
- 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1100mV 85C Model Metastability Summary
- 13. Slow 1100mV 0C Model Fmax Summary
- 14. Slow 1100mV 0C Model Setup Summary
- 15. Slow 1100mV 0C Model Hold Summary
- 16. Slow 1100mV 0C Model Recovery Summary
- 17. Slow 1100mV 0C Model Removal Summary
- 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1100mV 0C Model Metastability Summary
- 20. Fast 1100mV 85C Model Setup Summary
- 21. Fast 1100mV 85C Model Hold Summary
- 22. Fast 1100mV 85C Model Recovery Summary
- 23. Fast 1100mV 85C Model Removal Summary
- 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
- 25. Fast 1100mV 85C Model Metastability Summary
- 26. Fast 1100mV 0C Model Setup Summary
- 27. Fast 1100mV 0C Model Hold Summary
- 28. Fast 1100mV 0C Model Recovery Summary
- 29. Fast 1100mV 0C Model Removal Summary
- 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
- 31. Fast 1100mV 0C Model Metastability Summary
- 32. Multicorner Timing Analysis Summary
- 33. Board Trace Model Assignments
- 34. Input Transition Times
- 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
- 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
- 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
- 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
- 39. Setup Transfers
- 40. Hold Transfers
- 41. Report TCCS
- 42. Report RSKM
- 43. Unconstrained Paths Summary
- 44. Clock Status Summary
- 45. Unconstrained Input Ports
- 46. Unconstrained Output Ports
- 47. Unconstrained Input Ports
- 48. Unconstrained Output Ports
- 49. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                           ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Timing Analyzer       ; TimeQuest                                           ;
-; Revision Name         ; ex8                                                 ;
-; Device Family         ; Cyclone V                                           ;
-; Device Name           ; 5CSEMA5F31C6                                        ;
-; Timing Models         ; Final                                               ;
-; Delay Model           ; Combined                                            ;
-; Rise/Fall Delays      ; Enabled                                             ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.12        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   4.1%      ;
-;     Processor 3            ;   4.0%      ;
-;     Processor 4            ;   3.8%      ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                                                                                   ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
-; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 85C Model Fmax Summary                             ;
-+------------+-----------------+--------------------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
-+------------+-----------------+--------------------------+------+
-; 252.02 MHz ; 252.02 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 282.97 MHz ; 282.97 MHz      ; CLOCK_50                 ;      ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -2.968 ; -107.976      ;
-; CLOCK_50                            ; -2.534 ; -41.925       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.603 ; -1.603        ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 85C Model Hold Summary                          ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.203 ; 0.000         ;
-; CLOCK_50                            ; 0.384 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.419 ; 0.000         ;
-+-------------------------------------+-------+---------------+
-
-
-------------------------------------------
-; Slow 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.643 ; -16.740       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -26.810       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.357  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Slow 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary                              ;
-+------------+-----------------+--------------------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
-+------------+-----------------+--------------------------+------+
-; 252.33 MHz ; 252.33 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 264.27 MHz ; 264.27 MHz      ; CLOCK_50                 ;      ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -2.963 ; -106.734      ;
-; CLOCK_50                            ; -2.784 ; -42.820       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.493 ; -1.493        ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 0C Model Hold Summary                           ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.233 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.302 ; 0.000         ;
-; CLOCK_50                            ; 0.406 ; 0.000         ;
-+-------------------------------------+-------+---------------+
-
-
------------------------------------------
-; Slow 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.717 ; -15.605       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -26.816       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.396  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Slow 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -1.503 ; -52.250       ;
-; CLOCK_50                            ; -1.304 ; -15.219       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.568 ; -0.568        ;
-+-------------------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Hold Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -0.034 ; -0.067        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.057  ; 0.000         ;
-; CLOCK_50                            ; 0.185  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
-------------------------------------------
-; Fast 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.786 ; -12.110       ;
-; tick_50000:TICK0|CLK_OUT            ; 0.065  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.369  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Fast 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -1.311 ; -45.679       ;
-; CLOCK_50                            ; -1.229 ; -13.104       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.445 ; -0.445        ;
-+-------------------------------------+--------+---------------+
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Hold Summary                            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -0.034 ; -0.067        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.014 ; -0.014        ;
-; CLOCK_50                            ; 0.177  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------
-; Fast 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.844 ; -14.423       ;
-; tick_50000:TICK0|CLK_OUT            ; 0.081  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.396  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Fast 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                                                 ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Clock                                ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Worst-case Slack                     ; -2.968   ; -0.034 ; N/A      ; N/A     ; -0.844              ;
-;  CLOCK_50                            ; -2.784   ; 0.177  ; N/A      ; N/A     ; -0.844              ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.603   ; -0.014 ; N/A      ; N/A     ; 0.357               ;
-;  tick_50000:TICK0|CLK_OUT            ; -2.968   ; -0.034 ; N/A      ; N/A     ; -0.394              ;
-; Design-wide TNS                      ; -151.504 ; -0.081 ; 0.0      ; 0.0     ; -43.55              ;
-;  CLOCK_50                            ; -42.820  ; 0.000  ; N/A      ; N/A     ; -16.740             ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.603   ; -0.014 ; N/A      ; N/A     ; 0.000               ;
-;  tick_50000:TICK0|CLK_OUT            ; -107.976 ; -0.067 ; N/A      ; N/A     ; -26.816             ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+-------------------------------------------------------------+
-; Input Transition Times                                      ;
-+----------+--------------+-----------------+-----------------+
-; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+----------+--------------+-----------------+-----------------+
-; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-+----------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Setup Transfers                                                                                                       ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 405      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 39       ; 21       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 752      ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Hold Transfers                                                                                                        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 405      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 39       ; 21       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 752      ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary                    ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 1     ; 1    ;
-; Unconstrained Input Port Paths  ; 3     ; 3    ;
-; Unconstrained Output Ports      ; 28    ; 28   ;
-; Unconstrained Output Port Paths ; 121   ; 121  ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Clock Status Summary                                                                           ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; Target                              ; Clock                               ; Type ; Status      ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;
-+-------------------------------------+-------------------------------------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime TimeQuest Timing Analyzer
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 20:25:43 2016
-Info: Command: quartus_sta ex8 -c ex8
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
-    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
-    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
-    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1100mV 85C Model
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -2.968
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -2.968            -107.976 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -2.534             -41.925 CLOCK_50 
-    Info (332119):    -1.603              -1.603 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is 0.203
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.203               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.384               0.000 CLOCK_50 
-    Info (332119):     0.419               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.643
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.643             -16.740 CLOCK_50 
-    Info (332119):    -0.394             -26.810 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.357               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Slow 1100mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -2.963
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -2.963            -106.734 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -2.784             -42.820 CLOCK_50 
-    Info (332119):    -1.493              -1.493 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is 0.233
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.233               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.302               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-    Info (332119):     0.406               0.000 CLOCK_50 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.717
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.717             -15.605 CLOCK_50 
-    Info (332119):    -0.394             -26.816 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.396               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Fast 1100mV 85C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.503
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -1.503             -52.250 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -1.304             -15.219 CLOCK_50 
-    Info (332119):    -0.568              -0.568 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -0.034
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.034              -0.067 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.057               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-    Info (332119):     0.185               0.000 CLOCK_50 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.786
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.786             -12.110 CLOCK_50 
-    Info (332119):     0.065               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.369               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Fast 1100mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.311
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -1.311             -45.679 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -1.229             -13.104 CLOCK_50 
-    Info (332119):    -0.445              -0.445 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -0.034
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.034              -0.067 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.014              -0.014 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-    Info (332119):     0.177               0.000 CLOCK_50 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.844
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.844             -14.423 CLOCK_50 
-    Info (332119):     0.081               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.396               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
-    Info: Peak virtual memory: 1214 megabytes
-    Info: Processing ended: Sun Dec 11 20:25:48 2016
-    Info: Elapsed time: 00:00:05
-    Info: Total CPU time (on all processors): 00:00:05
-
-
+TimeQuest Timing Analyzer report for ex8
+Wed Dec 07 12:22:30 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex8                                                     ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CSEMA5F31C6                                            ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.06        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   2.2%      ;
+;     Processor 3            ;   2.1%      ;
+;     Processor 4            ;   2.1%      ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                   ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
+; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary                             ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 229.83 MHz ; 229.83 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
+; 296.74 MHz ; 296.74 MHz      ; CLOCK_50                 ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary                          ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -3.351 ; -141.123      ;
+; CLOCK_50                            ; -2.370 ; -46.721       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.669 ; -1.669        ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary                          ;
++-------------------------------------+-------+---------------+
+; Clock                               ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; 0.287 ; 0.000         ;
+; CLOCK_50                            ; 0.375 ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.603 ; 0.000         ;
++-------------------------------------+-------+---------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.655 ; -20.255       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -31.614       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.435  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                              ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 234.36 MHz ; 234.36 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
+; 278.71 MHz ; 278.71 MHz      ; CLOCK_50                 ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary                           ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -3.267 ; -138.732      ;
+; CLOCK_50                            ; -2.588 ; -48.020       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.583 ; -1.583        ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary                           ;
++-------------------------------------+-------+---------------+
+; Clock                               ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; 0.289 ; 0.000         ;
+; CLOCK_50                            ; 0.391 ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.463 ; 0.000         ;
++-------------------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.714 ; -18.725       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -30.708       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.391  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary                          ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -1.909 ; -72.643       ;
+; CLOCK_50                            ; -1.138 ; -16.318       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.609 ; -0.609        ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary                          ;
++-------------------------------------+-------+---------------+
+; Clock                               ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; 0.048 ; 0.000         ;
+; CLOCK_50                            ; 0.181 ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.219 ; 0.000         ;
++-------------------------------------+-------+---------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.779 ; -14.378       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.014 ; -0.134        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.468  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary                           ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -1.657 ; -63.529       ;
+; CLOCK_50                            ; -1.092 ; -13.791       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.488 ; -0.488        ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary                           ;
++-------------------------------------+-------+---------------+
+; Clock                               ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; 0.013 ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.128 ; 0.000         ;
+; CLOCK_50                            ; 0.171 ; 0.000         ;
++-------------------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.829 ; -17.064       ;
+; tick_50000:TICK0|CLK_OUT            ; 0.025  ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.460  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                ;
++--------------------------------------+----------+-------+----------+---------+---------------------+
+; Clock                                ; Setup    ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++--------------------------------------+----------+-------+----------+---------+---------------------+
+; Worst-case Slack                     ; -3.351   ; 0.013 ; N/A      ; N/A     ; -0.829              ;
+;  CLOCK_50                            ; -2.588   ; 0.171 ; N/A      ; N/A     ; -0.829              ;
+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.669   ; 0.128 ; N/A      ; N/A     ; 0.391               ;
+;  tick_50000:TICK0|CLK_OUT            ; -3.351   ; 0.013 ; N/A      ; N/A     ; -0.394              ;
+; Design-wide TNS                      ; -189.513 ; 0.0   ; 0.0      ; 0.0     ; -51.869             ;
+;  CLOCK_50                            ; -48.020  ; 0.000 ; N/A      ; N/A     ; -20.255             ;
+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.669   ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+;  tick_50000:TICK0|CLK_OUT            ; -141.123 ; 0.000 ; N/A      ; N/A     ; -31.614             ;
++--------------------------------------+----------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                       ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                            ; CLOCK_50                            ; 451      ; 0        ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 914      ; 0        ; 0        ; 0        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                            ; CLOCK_50                            ; 451      ; 0        ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 914      ; 0        ; 0        ; 0        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 1     ; 1    ;
+; Unconstrained Input Port Paths  ; 3     ; 3    ;
+; Unconstrained Output Ports      ; 28    ; 28   ;
+; Unconstrained Output Port Paths ; 121   ; 121  ;
++---------------------------------+-------+------+
+
+
++------------------------------------------------------------------------------------------------+
+; Clock Status Summary                                                                           ;
++-------------------------------------+-------------------------------------+------+-------------+
+; Target                              ; Clock                               ; Type ; Status      ;
++-------------------------------------+-------------------------------------+------+-------------+
+; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;
++-------------------------------------+-------------------------------------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:22:21 2016
+Info: Command: quartus_sta ex8 -c ex8
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex8.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.351
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.351            -141.123 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -2.370             -46.721 CLOCK_50 
+    Info (332119):    -1.669              -1.669 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is 0.287
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.287               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.375               0.000 CLOCK_50 
+    Info (332119):     0.603               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.655
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.655             -20.255 CLOCK_50 
+    Info (332119):    -0.394             -31.614 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.435               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.267
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.267            -138.732 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -2.588             -48.020 CLOCK_50 
+    Info (332119):    -1.583              -1.583 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is 0.289
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.289               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.391               0.000 CLOCK_50 
+    Info (332119):     0.463               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.714
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.714             -18.725 CLOCK_50 
+    Info (332119):    -0.394             -30.708 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.391               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.909
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.909             -72.643 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -1.138             -16.318 CLOCK_50 
+    Info (332119):    -0.609              -0.609 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is 0.048
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.048               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.181               0.000 CLOCK_50 
+    Info (332119):     0.219               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.779
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.779             -14.378 CLOCK_50 
+    Info (332119):    -0.014              -0.134 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.468               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.657
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.657             -63.529 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -1.092             -13.791 CLOCK_50 
+    Info (332119):    -0.488              -0.488 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is 0.013
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.013               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.128               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):     0.171               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.829
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.829             -17.064 CLOCK_50 
+    Info (332119):     0.025               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.460               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
+    Info: Peak virtual memory: 1209 megabytes
+    Info: Processing ended: Wed Dec 07 12:22:30 2016
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex8/output_files/ex8.sta.summary b/part_2/ex8/output_files/ex8.sta.summary
index 3a5916d..0dc051d 100755
--- a/part_2/ex8/output_files/ex8.sta.summary
+++ b/part_2/ex8/output_files/ex8.sta.summary
@@ -1,149 +1,149 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -2.968
-TNS   : -107.976
-
-Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -2.534
-TNS   : -41.925
-
-Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.603
-TNS   : -1.603
-
-Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.203
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.384
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.419
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.643
-TNS   : -16.740
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -26.810
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.357
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -2.963
-TNS   : -106.734
-
-Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -2.784
-TNS   : -42.820
-
-Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.493
-TNS   : -1.493
-
-Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.233
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.302
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.406
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.717
-TNS   : -15.605
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -26.816
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.396
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.503
-TNS   : -52.250
-
-Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -1.304
-TNS   : -15.219
-
-Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.568
-TNS   : -0.568
-
-Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.034
-TNS   : -0.067
-
-Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.057
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.185
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.786
-TNS   : -12.110
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.065
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.369
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.311
-TNS   : -45.679
-
-Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -1.229
-TNS   : -13.104
-
-Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.445
-TNS   : -0.445
-
-Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.034
-TNS   : -0.067
-
-Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.014
-TNS   : -0.014
-
-Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.177
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.844
-TNS   : -14.423
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.081
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.396
-TNS   : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -3.351
+TNS   : -141.123
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -2.370
+TNS   : -46.721
+
+Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.669
+TNS   : -1.669
+
+Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.287
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.375
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.603
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.655
+TNS   : -20.255
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS   : -31.614
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.435
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -3.267
+TNS   : -138.732
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.588
+TNS   : -48.020
+
+Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.583
+TNS   : -1.583
+
+Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.289
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.391
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.463
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.714
+TNS   : -18.725
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS   : -30.708
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.391
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.909
+TNS   : -72.643
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -1.138
+TNS   : -16.318
+
+Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.609
+TNS   : -0.609
+
+Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.048
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.181
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.219
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.779
+TNS   : -14.378
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.014
+TNS   : -0.134
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.468
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.657
+TNS   : -63.529
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -1.092
+TNS   : -13.791
+
+Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.488
+TNS   : -0.488
+
+Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.013
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.128
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.171
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.829
+TNS   : -17.064
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.025
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.460
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_2/ex8/verilog_files/formula_fsm.v b/part_2/ex8/verilog_files/formula_fsm.v
index 36c5668..aba959e 100755
--- a/part_2/ex8/verilog_files/formula_fsm.v
+++ b/part_2/ex8/verilog_files/formula_fsm.v
@@ -12,7 +12,7 @@ reg [8:0] count;
 
 parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
 
-initial 
+initial
 	begin
 		state = WAIT_TRIGGER;
 		en_lfsr = 1'b0;
@@ -21,7 +21,7 @@ initial
 
 always @ (posedge clk)
 	case(state)
-		WAIT_TRIGGER: 
+		WAIT_TRIGGER:
 			begin
 				if(trigger == 1'b1)
 					state <= LIGHT_UP_LEDS;
@@ -41,7 +41,7 @@ always @ (posedge clk)
 			ledr = 0;
 		LIGHT_UP_LEDS:
 			begin
-				if(count == 9'b0)
+				if(count == 1'b0)
 					begin
 						ledr <= {ledr[8:0], 1'b1};
 						count <= 9'd499;
@@ -53,7 +53,7 @@ always @ (posedge clk)
 			end
 		default: count <= 9'd499;
 	endcase
-	
+
 always @ (*)
 	case(state)
 		WAIT_TRIGGER:
@@ -74,4 +74,4 @@ always @ (*)
 		default: ;
 	endcase
 
-endmodule
-\ No newline at end of file
+endmodule
diff --git a/part_2/ex9/c5_pin_model_dump.txt b/part_2/ex9/c5_pin_model_dump.txt
index 31bb72c..a895a64 100644..100755
--- a/part_2/ex9/c5_pin_model_dump.txt
+++ b/part_2/ex9/c5_pin_model_dump.txt
@@ -1,118 +1,118 @@
-io_4iomodule_c5_index: 55gpio_index: 2
-io_4iomodule_c5_index: 54gpio_index: 465
-io_4iomodule_c5_index: 33gpio_index: 6
-io_4iomodule_c5_index: 51gpio_index: 461
-io_4iomodule_c5_index: 27gpio_index: 10
-io_4iomodule_c5_index: 57gpio_index: 457
-io_4iomodule_c5_index: 34gpio_index: 14
-io_4iomodule_c5_index: 28gpio_index: 453
-io_4iomodule_c5_index: 26gpio_index: 19
-io_4iomodule_c5_index: 47gpio_index: 449
-io_4iomodule_c5_index: 29gpio_index: 22
-io_4iomodule_c5_index: 3gpio_index: 445
-io_4iomodule_c5_index: 16gpio_index: 27
-io_4iomodule_c5_index: 6gpio_index: 441
-io_4iomodule_c5_index: 50gpio_index: 30
-io_4iomodule_c5_index: 35gpio_index: 437
-io_4iomodule_c5_index: 7gpio_index: 35
-io_4iomodule_c5_index: 53gpio_index: 433
-io_4iomodule_c5_index: 12gpio_index: 38
-io_4iomodule_c5_index: 1gpio_index: 429
-io_4iomodule_c5_index: 22gpio_index: 43
-io_4iomodule_c5_index: 8gpio_index: 425
-io_4iomodule_c5_index: 20gpio_index: 46
-io_4iomodule_c5_index: 30gpio_index: 421
-io_4iomodule_c5_index: 2gpio_index: 51
-io_4iomodule_c5_index: 31gpio_index: 417
-io_4iomodule_c5_index: 39gpio_index: 54
-io_4iomodule_c5_index: 18gpio_index: 413
-io_4iomodule_c5_index: 10gpio_index: 59
-io_4iomodule_c5_index: 42gpio_index: 409
-io_4iomodule_c5_index: 5gpio_index: 62
-io_4iomodule_c5_index: 24gpio_index: 405
-io_4iomodule_c5_index: 37gpio_index: 67
-io_4iomodule_c5_index: 13gpio_index: 401
-io_4iomodule_c5_index: 0gpio_index: 70
-io_4iomodule_c5_index: 44gpio_index: 397
-io_4iomodule_c5_index: 38gpio_index: 75
-io_4iomodule_c5_index: 52gpio_index: 393
-io_4iomodule_c5_index: 32gpio_index: 78
-io_4iomodule_c5_index: 56gpio_index: 389
-io_4iomodule_a_index: 13gpio_index: 385
-io_4iomodule_c5_index: 4gpio_index: 83
-io_4iomodule_c5_index: 23gpio_index: 86
-io_4iomodule_a_index: 15gpio_index: 381
-io_4iomodule_a_index: 8gpio_index: 377
-io_4iomodule_c5_index: 46gpio_index: 91
-io_4iomodule_a_index: 5gpio_index: 373
-io_4iomodule_a_index: 11gpio_index: 369
-io_4iomodule_c5_index: 41gpio_index: 94
-io_4iomodule_a_index: 3gpio_index: 365
-io_4iomodule_c5_index: 25gpio_index: 99
-io_4iomodule_a_index: 7gpio_index: 361
-io_4iomodule_c5_index: 9gpio_index: 102
-io_4iomodule_a_index: 0gpio_index: 357
-io_4iomodule_c5_index: 14gpio_index: 107
-io_4iomodule_a_index: 12gpio_index: 353
-io_4iomodule_c5_index: 45gpio_index: 110
-io_4iomodule_c5_index: 17gpio_index: 115
-io_4iomodule_a_index: 4gpio_index: 349
-io_4iomodule_c5_index: 36gpio_index: 118
-io_4iomodule_a_index: 10gpio_index: 345
-io_4iomodule_a_index: 16gpio_index: 341
-io_4iomodule_c5_index: 15gpio_index: 123
-io_4iomodule_a_index: 14gpio_index: 337
-io_4iomodule_c5_index: 43gpio_index: 126
-io_4iomodule_c5_index: 19gpio_index: 131
-io_4iomodule_a_index: 1gpio_index: 333
-io_4iomodule_c5_index: 59gpio_index: 134
-io_4iomodule_a_index: 2gpio_index: 329
-io_4iomodule_a_index: 9gpio_index: 325
-io_4iomodule_c5_index: 48gpio_index: 139
-io_4iomodule_a_index: 6gpio_index: 321
-io_4iomodule_a_index: 17gpio_index: 317
-io_4iomodule_c5_index: 40gpio_index: 142
-io_4iomodule_c5_index: 11gpio_index: 147
-io_4iomodule_c5_index: 58gpio_index: 150
-io_4iomodule_c5_index: 21gpio_index: 155
-io_4iomodule_c5_index: 49gpio_index: 158
-io_4iomodule_h_c5_index: 0gpio_index: 161
-io_4iomodule_h_c5_index: 6gpio_index: 165
-io_4iomodule_h_c5_index: 10gpio_index: 169
-io_4iomodule_h_c5_index: 3gpio_index: 173
-io_4iomodule_h_c5_index: 8gpio_index: 176
-io_4iomodule_h_c5_index: 11gpio_index: 180
-io_4iomodule_h_c5_index: 7gpio_index: 184
-io_4iomodule_h_c5_index: 5gpio_index: 188
-io_4iomodule_h_c5_index: 1gpio_index: 192
-io_4iomodule_h_c5_index: 2gpio_index: 196
-io_4iomodule_h_c5_index: 9gpio_index: 200
-io_4iomodule_h_c5_index: 4gpio_index: 204
-io_4iomodule_h_index: 15gpio_index: 208
-io_4iomodule_h_index: 1gpio_index: 212
-io_4iomodule_h_index: 3gpio_index: 216
-io_4iomodule_h_index: 2gpio_index: 220
-io_4iomodule_h_index: 11gpio_index: 224
-io_4iomodule_vref_h_index: 1gpio_index: 228
-io_4iomodule_h_index: 20gpio_index: 231
-io_4iomodule_h_index: 8gpio_index: 235
-io_4iomodule_h_index: 6gpio_index: 239
-io_4iomodule_h_index: 10gpio_index: 243
-io_4iomodule_h_index: 23gpio_index: 247
-io_4iomodule_h_index: 7gpio_index: 251
-io_4iomodule_h_index: 22gpio_index: 255
-io_4iomodule_h_index: 5gpio_index: 259
-io_4iomodule_h_index: 24gpio_index: 263
-io_4iomodule_h_index: 0gpio_index: 267
-io_4iomodule_h_index: 13gpio_index: 271
-io_4iomodule_h_index: 21gpio_index: 275
-io_4iomodule_h_index: 16gpio_index: 279
-io_4iomodule_vref_h_index: 0gpio_index: 283
-io_4iomodule_h_index: 12gpio_index: 286
-io_4iomodule_h_index: 4gpio_index: 290
-io_4iomodule_h_index: 19gpio_index: 294
-io_4iomodule_h_index: 18gpio_index: 298
-io_4iomodule_h_index: 17gpio_index: 302
-io_4iomodule_h_index: 25gpio_index: 306
-io_4iomodule_h_index: 14gpio_index: 310
-io_4iomodule_h_index: 9gpio_index: 314
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_2/ex9/db/.cmp.kpt b/part_2/ex9/db/.cmp.kpt
deleted file mode 100644
index 51a51ce..0000000
--- a/part_2/ex9/db/.cmp.kpt
+++ /dev/null
diff --git a/part_2/ex9/db/_cmp.kpt b/part_2/ex9/db/_cmp.kpt
index 1617b0b..1617b0b 100644..100755
--- a/part_2/ex9/db/_cmp.kpt
+++ b/part_2/ex9/db/_cmp.kpt
diff --git a/part_2/ex9/db/ex9.(0).cnf.cdb b/part_2/ex9/db/ex9.(0).cnf.cdb
index 8525cd4..2a49e3b 100644..100755
--- a/part_2/ex9/db/ex9.(0).cnf.cdb
+++ b/part_2/ex9/db/ex9.(0).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(0).cnf.hdb b/part_2/ex9/db/ex9.(0).cnf.hdb
index 4b411ff..f90ac91 100644..100755
--- a/part_2/ex9/db/ex9.(0).cnf.hdb
+++ b/part_2/ex9/db/ex9.(0).cnf.hdb
diff --git a/part_2/ex9/db/ex9.(1).cnf.cdb b/part_2/ex9/db/ex9.(1).cnf.cdb
index 5738c43..6fa5bfa 100644..100755
--- a/part_2/ex9/db/ex9.(1).cnf.cdb
+++ b/part_2/ex9/db/ex9.(1).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(1).cnf.hdb b/part_2/ex9/db/ex9.(1).cnf.hdb
index 74fd96e..829c3df 100644..100755
--- a/part_2/ex9/db/ex9.(1).cnf.hdb
+++ b/part_2/ex9/db/ex9.(1).cnf.hdb
diff --git a/part_2/ex9/db/ex9.(2).cnf.cdb b/part_2/ex9/db/ex9.(2).cnf.cdb
index 1fc3dad..43aabd2 100644..100755
--- a/part_2/ex9/db/ex9.(2).cnf.cdb
+++ b/part_2/ex9/db/ex9.(2).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(2).cnf.hdb b/part_2/ex9/db/ex9.(2).cnf.hdb
index cef343d..a2fe649 100644..100755
--- a/part_2/ex9/db/ex9.(2).cnf.hdb
+++ b/part_2/ex9/db/ex9.(2).cnf.hdb
diff --git a/part_2/ex9/db/ex9.(3).cnf.cdb b/part_2/ex9/db/ex9.(3).cnf.cdb
index f2e3fb4..dbd336f 100644..100755
--- a/part_2/ex9/db/ex9.(3).cnf.cdb
+++ b/part_2/ex9/db/ex9.(3).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(3).cnf.hdb b/part_2/ex9/db/ex9.(3).cnf.hdb
index e0a8e13..ac9f5e9 100644..100755
--- a/part_2/ex9/db/ex9.(3).cnf.hdb
+++ b/part_2/ex9/db/ex9.(3).cnf.hdb
diff --git a/part_2/ex9/db/ex9.(4).cnf.cdb b/part_2/ex9/db/ex9.(4).cnf.cdb
index c07454b..13f6ae2 100644..100755
--- a/part_2/ex9/db/ex9.(4).cnf.cdb
+++ b/part_2/ex9/db/ex9.(4).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(4).cnf.hdb b/part_2/ex9/db/ex9.(4).cnf.hdb
index 79a989e..b7d17a9 100644..100755
--- a/part_2/ex9/db/ex9.(4).cnf.hdb
+++ b/part_2/ex9/db/ex9.(4).cnf.hdb
diff --git a/part_2/ex9/db/ex9.(5).cnf.cdb b/part_2/ex9/db/ex9.(5).cnf.cdb
index 006be23..d06bc36 100644..100755
--- a/part_2/ex9/db/ex9.(5).cnf.cdb
+++ b/part_2/ex9/db/ex9.(5).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(5).cnf.hdb b/part_2/ex9/db/ex9.(5).cnf.hdb
index 5bf565f..d5d29c3 100644..100755
--- a/part_2/ex9/db/ex9.(5).cnf.hdb
+++ b/part_2/ex9/db/ex9.(5).cnf.hdb
diff --git a/part_2/ex9/db/ex9.(6).cnf.cdb b/part_2/ex9/db/ex9.(6).cnf.cdb
index e0f349d..05cba02 100644..100755
--- a/part_2/ex9/db/ex9.(6).cnf.cdb
+++ b/part_2/ex9/db/ex9.(6).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(6).cnf.hdb b/part_2/ex9/db/ex9.(6).cnf.hdb
index 8fd64f2..9cf3763 100644..100755
--- a/part_2/ex9/db/ex9.(6).cnf.hdb
+++ b/part_2/ex9/db/ex9.(6).cnf.hdb
diff --git a/part_2/ex9/db/ex9.(7).cnf.cdb b/part_2/ex9/db/ex9.(7).cnf.cdb
index a0dd9e5..604867e 100644..100755
--- a/part_2/ex9/db/ex9.(7).cnf.cdb
+++ b/part_2/ex9/db/ex9.(7).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(7).cnf.hdb b/part_2/ex9/db/ex9.(7).cnf.hdb
index 422205c..da601fb 100644..100755
--- a/part_2/ex9/db/ex9.(7).cnf.hdb
+++ b/part_2/ex9/db/ex9.(7).cnf.hdb
diff --git a/part_2/ex9/db/ex9.(8).cnf.cdb b/part_2/ex9/db/ex9.(8).cnf.cdb
index 62ff4d4..97e595e 100644..100755
--- a/part_2/ex9/db/ex9.(8).cnf.cdb
+++ b/part_2/ex9/db/ex9.(8).cnf.cdb
diff --git a/part_2/ex9/db/ex9.(8).cnf.hdb b/part_2/ex9/db/ex9.(8).cnf.hdb
index 2ce9333..42ab8b5 100644..100755
--- a/part_2/ex9/db/ex9.(8).cnf.hdb
+++ b/part_2/ex9/db/ex9.(8).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.(9).cnf.cdb b/part_2/ex9/db/ex9.(9).cnf.cdb
index e219d8b..e219d8b 100755
--- a/part_2/ex9_final/db/ex9.(9).cnf.cdb
+++ b/part_2/ex9/db/ex9.(9).cnf.cdb
diff --git a/part_2/ex9_final/db/ex9.(9).cnf.hdb b/part_2/ex9/db/ex9.(9).cnf.hdb
index 0bbfa6a..0bbfa6a 100755
--- a/part_2/ex9_final/db/ex9.(9).cnf.hdb
+++ b/part_2/ex9/db/ex9.(9).cnf.hdb
diff --git a/part_2/ex9/db/ex9.asm.qmsg b/part_2/ex9/db/ex9.asm.qmsg
index 45a240e..c869bf0 100644..100755
--- a/part_2/ex9/db/ex9.asm.qmsg
+++ b/part_2/ex9/db/ex9.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481488253376 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481488253382 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:30:53 2016 " "Processing started: Sun Dec 11 20:30:53 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481488253382 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481488253382 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481488253382 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481488254041 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481488259233 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "979 " "Peak virtual memory: 979 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481488259594 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:30:59 2016 " "Processing ended: Sun Dec 11 20:30:59 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481488259594 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481488259594 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481488259594 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481488259594 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112492741 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112492743 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:08:12 2016 " "Processing started: Wed Dec 07 12:08:12 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112492743 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481112492743 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481112492743 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481112493565 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481112498243 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:20 2016 " "Processing ended: Wed Dec 07 12:08:20 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112500798 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481112500798 ""}
diff --git a/part_2/ex9/db/ex9.asm.rdb b/part_2/ex9/db/ex9.asm.rdb
index 1ffef45..3a4d871 100644..100755
--- a/part_2/ex9/db/ex9.asm.rdb
+++ b/part_2/ex9/db/ex9.asm.rdb
diff --git a/part_2/ex9/db/ex9.cbx.xml b/part_2/ex9/db/ex9.cbx.xml
index 3c357f6..9156ad4 100644..100755
--- a/part_2/ex9/db/ex9.cbx.xml
+++ b/part_2/ex9/db/ex9.cbx.xml
@@ -1,5 +1,5 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
-	<PROJECT NAME="ex9">
-	</PROJECT>
-</LOG_ROOT>
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ex9">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/part_2/ex9_final/db/ex9.cmp.ammdb b/part_2/ex9/db/ex9.cmp.ammdb
index b640a2a..b640a2a 100755
--- a/part_2/ex9_final/db/ex9.cmp.ammdb
+++ b/part_2/ex9/db/ex9.cmp.ammdb
diff --git a/part_2/ex9/db/ex9.cmp.bpm b/part_2/ex9/db/ex9.cmp.bpm
index 822783a..2d49b22 100644..100755
--- a/part_2/ex9/db/ex9.cmp.bpm
+++ b/part_2/ex9/db/ex9.cmp.bpm
diff --git a/part_2/ex9/db/ex9.cmp.cdb b/part_2/ex9/db/ex9.cmp.cdb
index 523adce..3d4dfef 100644..100755
--- a/part_2/ex9/db/ex9.cmp.cdb
+++ b/part_2/ex9/db/ex9.cmp.cdb
diff --git a/part_2/ex9/db/ex9.cmp.hdb b/part_2/ex9/db/ex9.cmp.hdb
index 527505a..3756b65 100644..100755
--- a/part_2/ex9/db/ex9.cmp.hdb
+++ b/part_2/ex9/db/ex9.cmp.hdb
diff --git a/part_2/ex9/db/ex9.cmp.idb b/part_2/ex9/db/ex9.cmp.idb
index a6ead63..5cbf640 100644..100755
--- a/part_2/ex9/db/ex9.cmp.idb
+++ b/part_2/ex9/db/ex9.cmp.idb
diff --git a/part_2/ex9/db/ex9.cmp.logdb b/part_2/ex9/db/ex9.cmp.logdb
index 625b3e6..b4567d7 100644..100755
--- a/part_2/ex9/db/ex9.cmp.logdb
+++ b/part_2/ex9/db/ex9.cmp.logdb
@@ -1,96 +1,96 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000003;IO_000001;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000022;IO_000021;IO_000046;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000047;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
-IO_RULES_MATRIX,Total Pass,0;57;57;0;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;57;57;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,57;0;0;57;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;0;0;57,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX4[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX5[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX5[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX5[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX5[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX5[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX5[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX5[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,57;0;57;0;0;57;57;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;57;0;57;57;0;0;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_2/ex9/db/ex9.cmp.rdb b/part_2/ex9/db/ex9.cmp.rdb
index e9a3bb6..89d655d 100644..100755
--- a/part_2/ex9/db/ex9.cmp.rdb
+++ b/part_2/ex9/db/ex9.cmp.rdb
diff --git a/part_2/ex9/db/ex9.cmp_merge.kpt b/part_2/ex9/db/ex9.cmp_merge.kpt
index a4ff375..fdd3bfe 100644..100755
--- a/part_2/ex9/db/ex9.cmp_merge.kpt
+++ b/part_2/ex9/db/ex9.cmp_merge.kpt
diff --git a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
index 826025e..da61997 100644..100755
--- a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
+++ b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
index 8ebe269..3a7a497 100644..100755
--- a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
+++ b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
index 8d531ee..aa473fa 100644..100755
--- a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
+++ b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
index 1e5e40e..acc52a8 100644..100755
--- a/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
+++ b/part_2/ex9/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex9/db/ex9.db_info b/part_2/ex9/db/ex9.db_info
index 4aad5b9..0319e5b 100644..100755
--- a/part_2/ex9/db/ex9.db_info
+++ b/part_2/ex9/db/ex9.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Version_Index = 419480576
-Creation_Time = Sun Dec 11 20:28:46 2016
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Wed Dec 07 11:55:17 2016
diff --git a/part_2/ex9/db/ex9.fit.qmsg b/part_2/ex9/db/ex9.fit.qmsg
index 9cc49ad..ad91f8e 100644..100755
--- a/part_2/ex9/db/ex9.fit.qmsg
+++ b/part_2/ex9/db/ex9.fit.qmsg
@@ -1,46 +1,45 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481488216378 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481488216378 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481488216384 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481488216418 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481488216418 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481488216800 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1481488216819 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481488216879 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481488228269 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481488228378 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481488228378 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488228378 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481488228383 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481488228383 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481488228385 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481488228386 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481488228386 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481488228386 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481488229012 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481488229013 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481488229013 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481488229018 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481488229018 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481488229019 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481488229026 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481488229027 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481488229027 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/yannherklotz/intelFPGA_lite/16.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481488229081 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481488229081 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:13 " "Fitter preparation operations ending: elapsed time is 00:00:13" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488229082 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481488233823 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481488234092 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488234724 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481488235867 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481488237091 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488237091 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481488238139 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X33_Y0 X44_Y10 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X33_Y0 to location X44_Y10" {  } { { "loc" "" { Generic "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X33_Y0 to location X44_Y10"} { { 12 { 0 ""} 33 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481488243100 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481488243100 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481488246581 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481488246581 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488246583 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.54 " "Total time spent on timing analysis during the Fitter is 0.54 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481488248270 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481488248303 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481488248769 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481488248769 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481488249249 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481488251686 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481488251801 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.fit.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481488251868 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 31 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2145 " "Peak virtual memory: 2145 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481488252290 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:30:52 2016 " "Processing ended: Sun Dec 11 20:30:52 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481488252290 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481488252290 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:04 " "Total CPU time (on all processors): 00:01:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481488252290 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481488252290 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481112453657 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481112453658 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481112453895 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112453945 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481112453945 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481112454353 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481112454715 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481112465342 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481112465453 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481112465453 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112465454 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481112465457 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112465458 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481112465459 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481112465459 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481112465460 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481112465460 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1481112466204 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481112466204 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481112466205 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481112466208 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481112466209 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481112466209 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481112466213 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481112466214 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481112466214 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481112466267 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481112466267 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112466278 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481112471355 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481112471629 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112472386 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481112473242 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481112474189 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112474189 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481112475466 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481112480003 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481112480003 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481112481785 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481112481785 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112481789 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481112483588 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112483629 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112484239 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481112484239 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481112484754 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481112487536 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481112487786 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481112487890 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2593 " "Peak virtual memory: 2593 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:09 2016 " "Processing ended: Wed Dec 07 12:08:09 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:02 " "Total CPU time (on all processors): 00:01:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112489326 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481112489326 ""}
diff --git a/part_2/ex9/db/ex9.hier_info b/part_2/ex9/db/ex9.hier_info
index 1dcb685..2ac051e 100644..100755
--- a/part_2/ex9/db/ex9.hier_info
+++ b/part_2/ex9/db/ex9.hier_info
@@ -1,781 +1,784 @@
-|ex9
-CLOCK_50 => CLOCK_50.IN1
-KEY[0] => _.IN1
-KEY[1] => ~NO_FANOUT~
-KEY[2] => ~NO_FANOUT~
-KEY[3] => _.IN1
-HEX0[0] <= hex_to_7seg:SEG0.port0
-HEX0[1] <= hex_to_7seg:SEG0.port0
-HEX0[2] <= hex_to_7seg:SEG0.port0
-HEX0[3] <= hex_to_7seg:SEG0.port0
-HEX0[4] <= hex_to_7seg:SEG0.port0
-HEX0[5] <= hex_to_7seg:SEG0.port0
-HEX0[6] <= hex_to_7seg:SEG0.port0
-HEX1[0] <= hex_to_7seg:SEG1.port0
-HEX1[1] <= hex_to_7seg:SEG1.port0
-HEX1[2] <= hex_to_7seg:SEG1.port0
-HEX1[3] <= hex_to_7seg:SEG1.port0
-HEX1[4] <= hex_to_7seg:SEG1.port0
-HEX1[5] <= hex_to_7seg:SEG1.port0
-HEX1[6] <= hex_to_7seg:SEG1.port0
-HEX2[0] <= hex_to_7seg:SEG2.port0
-HEX2[1] <= hex_to_7seg:SEG2.port0
-HEX2[2] <= hex_to_7seg:SEG2.port0
-HEX2[3] <= hex_to_7seg:SEG2.port0
-HEX2[4] <= hex_to_7seg:SEG2.port0
-HEX2[5] <= hex_to_7seg:SEG2.port0
-HEX2[6] <= hex_to_7seg:SEG2.port0
-HEX3[0] <= hex_to_7seg:SEG3.port0
-HEX3[1] <= hex_to_7seg:SEG3.port0
-HEX3[2] <= hex_to_7seg:SEG3.port0
-HEX3[3] <= hex_to_7seg:SEG3.port0
-HEX3[4] <= hex_to_7seg:SEG3.port0
-HEX3[5] <= hex_to_7seg:SEG3.port0
-HEX3[6] <= hex_to_7seg:SEG3.port0
-HEX4[0] <= hex_to_7seg:SEG4.port0
-HEX4[1] <= hex_to_7seg:SEG4.port0
-HEX4[2] <= hex_to_7seg:SEG4.port0
-HEX4[3] <= hex_to_7seg:SEG4.port0
-HEX4[4] <= hex_to_7seg:SEG4.port0
-HEX4[5] <= hex_to_7seg:SEG4.port0
-HEX4[6] <= hex_to_7seg:SEG4.port0
-HEX5[0] <= hex_to_7seg:SEG5.port0
-HEX5[1] <= hex_to_7seg:SEG5.port0
-HEX5[2] <= hex_to_7seg:SEG5.port0
-HEX5[3] <= hex_to_7seg:SEG5.port0
-HEX5[4] <= hex_to_7seg:SEG5.port0
-HEX5[5] <= hex_to_7seg:SEG5.port0
-HEX5[6] <= hex_to_7seg:SEG5.port0
-LEDR[0] <= formula_fsm:FSM.port5
-LEDR[1] <= formula_fsm:FSM.port5
-LEDR[2] <= formula_fsm:FSM.port5
-LEDR[3] <= formula_fsm:FSM.port5
-LEDR[4] <= formula_fsm:FSM.port5
-LEDR[5] <= formula_fsm:FSM.port5
-LEDR[6] <= formula_fsm:FSM.port5
-LEDR[7] <= formula_fsm:FSM.port5
-LEDR[8] <= formula_fsm:FSM.port5
-LEDR[9] <= formula_fsm:FSM.port5
-
-
-|ex9|tick_50000:TICK0
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|formula_fsm:FSM
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => ledr[0]~reg0.CLK
-clk => ledr[1]~reg0.CLK
-clk => ledr[2]~reg0.CLK
-clk => ledr[3]~reg0.CLK
-clk => ledr[4]~reg0.CLK
-clk => ledr[5]~reg0.CLK
-clk => ledr[6]~reg0.CLK
-clk => ledr[7]~reg0.CLK
-clk => ledr[8]~reg0.CLK
-clk => ledr[9]~reg0.CLK
-clk => state~3.DATAIN
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
-start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
-ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|LFSR:LFSR0
-CLK => COUNT[1]~reg0.CLK
-CLK => COUNT[2]~reg0.CLK
-CLK => COUNT[3]~reg0.CLK
-CLK => COUNT[4]~reg0.CLK
-CLK => COUNT[5]~reg0.CLK
-CLK => COUNT[6]~reg0.CLK
-CLK => COUNT[7]~reg0.CLK
-en => COUNT[1]~reg0.ENA
-en => COUNT[2]~reg0.ENA
-en => COUNT[3]~reg0.ENA
-en => COUNT[4]~reg0.ENA
-en => COUNT[5]~reg0.ENA
-en => COUNT[6]~reg0.ENA
-en => COUNT[7]~reg0.ENA
-COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|delay:DEL0
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => count[12].CLK
-clk => count[13].CLK
-clk => state~4.DATAIN
-N[0] => count.DATAB
-N[1] => count.DATAB
-N[2] => count.DATAB
-N[3] => count.DATAB
-N[4] => count.DATAB
-N[5] => count.DATAB
-N[6] => count.DATAB
-N[7] => ~NO_FANOUT~
-N[8] => ~NO_FANOUT~
-N[9] => ~NO_FANOUT~
-N[10] => ~NO_FANOUT~
-N[11] => ~NO_FANOUT~
-N[12] => ~NO_FANOUT~
-N[13] => ~NO_FANOUT~
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector17.IN3
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector14.IN2
-time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|counter_16:COUNT0
-clock => count[0]~reg0.CLK
-clock => count[1]~reg0.CLK
-clock => count[2]~reg0.CLK
-clock => count[3]~reg0.CLK
-clock => count[4]~reg0.CLK
-clock => count[5]~reg0.CLK
-clock => count[6]~reg0.CLK
-clock => count[7]~reg0.CLK
-clock => count[8]~reg0.CLK
-clock => count[9]~reg0.CLK
-clock => count[10]~reg0.CLK
-clock => count[11]~reg0.CLK
-clock => count[12]~reg0.CLK
-clock => count[13]~reg0.CLK
-clock => count[14]~reg0.CLK
-clock => count[15]~reg0.CLK
-clock => state.CLK
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => state.OUTPUTSELECT
-stop => state.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD
-B[0] => BCD_0[0].DATAIN
-B[1] => w35[0].IN1
-B[2] => w30[0].IN1
-B[3] => w26[0].IN1
-B[4] => w22[0].IN1
-B[5] => w18[0].IN1
-B[6] => w15[0].IN1
-B[7] => w12[0].IN1
-B[8] => w9[0].IN1
-B[9] => w7[0].IN1
-B[10] => w5[0].IN1
-B[11] => w3[0].IN1
-B[12] => w2[0].IN1
-B[13] => w1[0].IN1
-B[14] => w1[1].IN1
-B[15] => w1[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A35.port1
-BCD_0[2] <= add3_ge5:A35.port1
-BCD_0[3] <= add3_ge5:A35.port1
-BCD_1[0] <= add3_ge5:A35.port1
-BCD_1[1] <= add3_ge5:A34.port1
-BCD_1[2] <= add3_ge5:A34.port1
-BCD_1[3] <= add3_ge5:A34.port1
-BCD_2[0] <= add3_ge5:A34.port1
-BCD_2[1] <= add3_ge5:A33.port1
-BCD_2[2] <= add3_ge5:A33.port1
-BCD_2[3] <= add3_ge5:A33.port1
-BCD_3[0] <= add3_ge5:A33.port1
-BCD_3[1] <= add3_ge5:A32.port1
-BCD_3[2] <= add3_ge5:A32.port1
-BCD_3[3] <= add3_ge5:A32.port1
-BCD_4[0] <= add3_ge5:A32.port1
-BCD_4[1] <= add3_ge5:A31.port1
-BCD_4[2] <= add3_ge5:A31.port1
-BCD_4[3] <= add3_ge5:A31.port1
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A1
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A2
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A3
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A4
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A5
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A6
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A7
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A8
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A9
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A10
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A11
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A12
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A13
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A14
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A15
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A16
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A17
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A18
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A19
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A20
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A21
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A22
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A23
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A24
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A25
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A26
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A27
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A28
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A29
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A30
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A31
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A32
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A33
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A34
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A35
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG3
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG4
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG5
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
+|ex9
+CLOCK_50 => CLOCK_50.IN1
+KEY[0] => _.IN1
+KEY[1] => ~NO_FANOUT~
+KEY[2] => ~NO_FANOUT~
+KEY[3] => _.IN1
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+HEX3[0] << hex_to_7seg:SEG3.port0
+HEX3[1] << hex_to_7seg:SEG3.port0
+HEX3[2] << hex_to_7seg:SEG3.port0
+HEX3[3] << hex_to_7seg:SEG3.port0
+HEX3[4] << hex_to_7seg:SEG3.port0
+HEX3[5] << hex_to_7seg:SEG3.port0
+HEX3[6] << hex_to_7seg:SEG3.port0
+HEX4[0] << hex_to_7seg:SEG4.port0
+HEX4[1] << hex_to_7seg:SEG4.port0
+HEX4[2] << hex_to_7seg:SEG4.port0
+HEX4[3] << hex_to_7seg:SEG4.port0
+HEX4[4] << hex_to_7seg:SEG4.port0
+HEX4[5] << hex_to_7seg:SEG4.port0
+HEX4[6] << hex_to_7seg:SEG4.port0
+HEX5[0] << hex_to_7seg:SEG5.port0
+HEX5[1] << hex_to_7seg:SEG5.port0
+HEX5[2] << hex_to_7seg:SEG5.port0
+HEX5[3] << hex_to_7seg:SEG5.port0
+HEX5[4] << hex_to_7seg:SEG5.port0
+HEX5[5] << hex_to_7seg:SEG5.port0
+HEX5[6] << hex_to_7seg:SEG5.port0
+LEDR[0] << formula_fsm:FSM.port5
+LEDR[1] << formula_fsm:FSM.port5
+LEDR[2] << formula_fsm:FSM.port5
+LEDR[3] << formula_fsm:FSM.port5
+LEDR[4] << formula_fsm:FSM.port5
+LEDR[5] << formula_fsm:FSM.port5
+LEDR[6] << formula_fsm:FSM.port5
+LEDR[7] << formula_fsm:FSM.port5
+LEDR[8] << formula_fsm:FSM.port5
+LEDR[9] << formula_fsm:FSM.port5
+
+
+|ex9|tick_50000:TICK0
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|formula_fsm:FSM
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => count[10].CLK
+clk => count[11].CLK
+clk => ledr[0]~reg0.CLK
+clk => ledr[1]~reg0.CLK
+clk => ledr[2]~reg0.CLK
+clk => ledr[3]~reg0.CLK
+clk => ledr[4]~reg0.CLK
+clk => ledr[5]~reg0.CLK
+clk => ledr[6]~reg0.CLK
+clk => ledr[7]~reg0.CLK
+clk => ledr[8]~reg0.CLK
+clk => ledr[9]~reg0.CLK
+clk => state~3.DATAIN
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+time_out => state.OUTPUTSELECT
+en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
+start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
+ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|LFSR:LFSR0
+CLK => COUNT[1]~reg0.CLK
+CLK => COUNT[2]~reg0.CLK
+CLK => COUNT[3]~reg0.CLK
+CLK => COUNT[4]~reg0.CLK
+CLK => COUNT[5]~reg0.CLK
+CLK => COUNT[6]~reg0.CLK
+CLK => COUNT[7]~reg0.CLK
+en => COUNT[1]~reg0.ENA
+en => COUNT[2]~reg0.ENA
+en => COUNT[3]~reg0.ENA
+en => COUNT[4]~reg0.ENA
+en => COUNT[5]~reg0.ENA
+en => COUNT[6]~reg0.ENA
+en => COUNT[7]~reg0.ENA
+COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|delay:DEL0
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => count[10].CLK
+clk => count[11].CLK
+clk => count[12].CLK
+clk => count[13].CLK
+clk => state~4.DATAIN
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => ~NO_FANOUT~
+N[8] => ~NO_FANOUT~
+N[9] => ~NO_FANOUT~
+N[10] => ~NO_FANOUT~
+N[11] => ~NO_FANOUT~
+N[12] => ~NO_FANOUT~
+N[13] => ~NO_FANOUT~
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => count.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector17.IN3
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => state.OUTPUTSELECT
+trigger => Selector14.IN2
+time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|counter_16:COUNT0
+clock => count[0]~reg0.CLK
+clock => count[1]~reg0.CLK
+clock => count[2]~reg0.CLK
+clock => count[3]~reg0.CLK
+clock => count[4]~reg0.CLK
+clock => count[5]~reg0.CLK
+clock => count[6]~reg0.CLK
+clock => count[7]~reg0.CLK
+clock => count[8]~reg0.CLK
+clock => count[9]~reg0.CLK
+clock => count[10]~reg0.CLK
+clock => count[11]~reg0.CLK
+clock => count[12]~reg0.CLK
+clock => count[13]~reg0.CLK
+clock => count[14]~reg0.CLK
+clock => count[15]~reg0.CLK
+clock => state.CLK
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => count.OUTPUTSELECT
+start => state.OUTPUTSELECT
+stop => state.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+stop => count.OUTPUTSELECT
+count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD
+B[0] => BCD_0[0].DATAIN
+B[1] => w35[0].IN1
+B[2] => w30[0].IN1
+B[3] => w26[0].IN1
+B[4] => w22[0].IN1
+B[5] => w18[0].IN1
+B[6] => w15[0].IN1
+B[7] => w12[0].IN1
+B[8] => w9[0].IN1
+B[9] => w7[0].IN1
+B[10] => w5[0].IN1
+B[11] => w3[0].IN1
+B[12] => w2[0].IN1
+B[13] => w1[0].IN1
+B[14] => w1[1].IN1
+B[15] => w1[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A35.port1
+BCD_0[2] <= add3_ge5:A35.port1
+BCD_0[3] <= add3_ge5:A35.port1
+BCD_1[0] <= add3_ge5:A35.port1
+BCD_1[1] <= add3_ge5:A34.port1
+BCD_1[2] <= add3_ge5:A34.port1
+BCD_1[3] <= add3_ge5:A34.port1
+BCD_2[0] <= add3_ge5:A34.port1
+BCD_2[1] <= add3_ge5:A33.port1
+BCD_2[2] <= add3_ge5:A33.port1
+BCD_2[3] <= add3_ge5:A33.port1
+BCD_3[0] <= add3_ge5:A33.port1
+BCD_3[1] <= add3_ge5:A32.port1
+BCD_3[2] <= add3_ge5:A32.port1
+BCD_3[3] <= add3_ge5:A32.port1
+BCD_4[0] <= add3_ge5:A32.port1
+BCD_4[1] <= add3_ge5:A31.port1
+BCD_4[2] <= add3_ge5:A31.port1
+BCD_4[3] <= add3_ge5:A31.port1
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A1
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A2
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A3
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A4
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A5
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A6
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A7
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A8
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A9
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A10
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A11
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A12
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A13
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A14
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A15
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A16
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A17
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A18
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A19
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A20
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A21
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A22
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A23
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A24
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A25
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A26
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A27
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A28
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A29
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A30
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A31
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A32
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A33
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A34
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|bin2bcd_16:BCD|add3_ge5:A35
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex9|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG3
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG4
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex9|hex_to_7seg:SEG5
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_2/ex9/db/ex9.hif b/part_2/ex9/db/ex9.hif
index 71330c9..72b4f73 100644..100755
--- a/part_2/ex9/db/ex9.hif
+++ b/part_2/ex9/db/ex9.hif
diff --git a/part_2/ex9/db/ex9.lpc.html b/part_2/ex9/db/ex9.lpc.html
index 66398b2..795349d 100644..100755
--- a/part_2/ex9/db/ex9.lpc.html
+++ b/part_2/ex9/db/ex9.lpc.html
@@ -1,770 +1,770 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >SEG5</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >7</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG1</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A35</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A34</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A33</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A32</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A31</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A30</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A29</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A28</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A27</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A26</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A25</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A24</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A23</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A22</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A21</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A20</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A19</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A18</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A17</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A16</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A15</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A14</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A13</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A12</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A11</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A10</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A9</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A8</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A7</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A6</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A5</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A4</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A3</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD</TD>
-<TD >16</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >20</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >COUNT0</TD>
-<TD >3</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >16</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >DEL0</TD>
-<TD >16</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >1</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >LFSR0</TD>
-<TD >2</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >FSM</TD>
-<TD >3</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >12</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >TICK0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG5</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >7</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A35</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A34</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A33</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A32</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A31</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A30</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A29</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A28</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A27</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A26</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A19</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A18</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A10</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A9</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A4</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD|A1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >COUNT0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >DEL0</TD>
+<TD >16</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >1</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >LFSR0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >FSM</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >TICK0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_2/ex9/db/ex9.lpc.rdb b/part_2/ex9/db/ex9.lpc.rdb
index a762277..9db0391 100644..100755
--- a/part_2/ex9/db/ex9.lpc.rdb
+++ b/part_2/ex9/db/ex9.lpc.rdb
diff --git a/part_2/ex9/db/ex9.lpc.txt b/part_2/ex9/db/ex9.lpc.txt
index d85a84b..538b3bf 100644..100755
--- a/part_2/ex9/db/ex9.lpc.txt
+++ b/part_2/ex9/db/ex9.lpc.txt
@@ -1,53 +1,53 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG5      ; 4     ; 4              ; 0            ; 4              ; 7      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD       ; 16    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; COUNT0    ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; FSM       ; 3     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG5      ; 4     ; 4              ; 0            ; 4              ; 7      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD       ; 16    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; COUNT0    ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; FSM       ; 3     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex9/db/ex9.map.ammdb b/part_2/ex9/db/ex9.map.ammdb
index a4afc79..174eb00 100644..100755
--- a/part_2/ex9/db/ex9.map.ammdb
+++ b/part_2/ex9/db/ex9.map.ammdb
diff --git a/part_2/ex9/db/ex9.map.bpm b/part_2/ex9/db/ex9.map.bpm
index bd51c17..1016d90 100644..100755
--- a/part_2/ex9/db/ex9.map.bpm
+++ b/part_2/ex9/db/ex9.map.bpm
diff --git a/part_2/ex9/db/ex9.map.cdb b/part_2/ex9/db/ex9.map.cdb
index 1d4ff12..3bfd4b0 100644..100755
--- a/part_2/ex9/db/ex9.map.cdb
+++ b/part_2/ex9/db/ex9.map.cdb
diff --git a/part_2/ex9/db/ex9.map.hdb b/part_2/ex9/db/ex9.map.hdb
index 180812a..1b64dd1 100644..100755
--- a/part_2/ex9/db/ex9.map.hdb
+++ b/part_2/ex9/db/ex9.map.hdb
diff --git a/part_2/ex9/db/ex9.map.kpt b/part_2/ex9/db/ex9.map.kpt
index 59f8096..537bff0 100644..100755
--- a/part_2/ex9/db/ex9.map.kpt
+++ b/part_2/ex9/db/ex9.map.kpt
diff --git a/part_2/ex9/db/ex9.map.logdb b/part_2/ex9/db/ex9.map.logdb
index 626799f..d45424f 100644..100755
--- a/part_2/ex9/db/ex9.map.logdb
+++ b/part_2/ex9/db/ex9.map.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/db/ex9.map.qmsg b/part_2/ex9/db/ex9.map.qmsg
index 31b3a95..0c6e7c8 100644..100755
--- a/part_2/ex9/db/ex9.map.qmsg
+++ b/part_2/ex9/db/ex9.map.qmsg
@@ -1,73 +1,73 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481488205223 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481488205230 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:30:05 2016 " "Processing started: Sun Dec 11 20:30:05 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481488205230 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488205230 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488205231 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481488205451 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481488205451 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214169 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214169 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/LFSR.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214170 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214170 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214177 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214177 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481488214178 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214178 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214178 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214181 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214181 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214181 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214189 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214189 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214196 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214196 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214197 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214198 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214198 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214204 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214204 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481488214204 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214204 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481488214245 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214253 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214258 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481488214259 "|ex9|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481488214259 "|ex9|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488214259 "|ex9|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214264 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214266 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481488214267 "|ex9|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214272 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214275 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214283 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488214293 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481488214702 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481488214855 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481488214855 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481488214913 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481488215194 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488215217 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481488215297 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481488215297 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481488215352 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "/home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481488215352 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481488215352 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "345 " "Implemented 345 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481488215353 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481488215353 ""} { "Info" "ICUT_CUT_TM_LCELLS" "288 " "Implemented 288 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481488215353 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481488215353 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1067 " "Peak virtual memory: 1067 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481488215362 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:30:15 2016 " "Processing ended: Sun Dec 11 20:30:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481488215362 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481488215362 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481488215362 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481488215362 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112434281 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112434284 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:07:13 2016 " "Processing started: Wed Dec 07 12:07:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112434284 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112434284 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112434284 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481112434902 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481112434902 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443515 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443515 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443519 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443519 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443523 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443523 ""}
+{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1481112443527 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443528 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443528 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443536 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443536 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443536 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443540 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443540 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443543 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443544 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443545 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443546 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443547 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481112443548 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443548 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443548 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443552 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443552 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481112443555 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443555 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481112443627 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443633 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443637 ""}
+{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112443642 "|ex9|formula_fsm:FSM"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443643 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443647 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1481112443648 "|ex9|delay:DEL0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443692 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443714 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443719 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112443728 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481112444476 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481112444661 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481112444661 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481112444740 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481112445211 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg " "Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112445296 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481112445625 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481112445625 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112446084 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481112446084 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481112446084 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "354 " "Implemented 354 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481112446087 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481112446087 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481112446087 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481112446087 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "918 " "Peak virtual memory: 918 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:07:26 2016 " "Processing ended: Wed Dec 07 12:07:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112446141 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481112446141 ""}
diff --git a/part_2/ex9/db/ex9.map.rdb b/part_2/ex9/db/ex9.map.rdb
index c4fa58d..68fd1db 100644..100755
--- a/part_2/ex9/db/ex9.map.rdb
+++ b/part_2/ex9/db/ex9.map.rdb
diff --git a/part_2/ex9/db/ex9.map_bb.cdb b/part_2/ex9/db/ex9.map_bb.cdb
index 18feadc..bf85f94 100644..100755
--- a/part_2/ex9/db/ex9.map_bb.cdb
+++ b/part_2/ex9/db/ex9.map_bb.cdb
diff --git a/part_2/ex9/db/ex9.map_bb.hdb b/part_2/ex9/db/ex9.map_bb.hdb
index d02e0ee..490d26d 100644..100755
--- a/part_2/ex9/db/ex9.map_bb.hdb
+++ b/part_2/ex9/db/ex9.map_bb.hdb
diff --git a/part_2/ex9/db/ex9.map_bb.logdb b/part_2/ex9/db/ex9.map_bb.logdb
index 626799f..d45424f 100644..100755
--- a/part_2/ex9/db/ex9.map_bb.logdb
+++ b/part_2/ex9/db/ex9.map_bb.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/db/ex9.pre_map.hdb b/part_2/ex9/db/ex9.pre_map.hdb
index b18d89e..ee4dd3e 100644..100755
--- a/part_2/ex9/db/ex9.pre_map.hdb
+++ b/part_2/ex9/db/ex9.pre_map.hdb
diff --git a/part_2/ex9/db/ex9.quiproj.2651.rdr.flock b/part_2/ex9/db/ex9.quiproj.2651.rdr.flock
deleted file mode 100644
index e69de29..0000000
--- a/part_2/ex9/db/ex9.quiproj.2651.rdr.flock
+++ /dev/null
diff --git a/part_2/ex9/db/ex9.root_partition.map.reg_db.cdb b/part_2/ex9/db/ex9.root_partition.map.reg_db.cdb
index de4e15b..c515539 100644..100755
--- a/part_2/ex9/db/ex9.root_partition.map.reg_db.cdb
+++ b/part_2/ex9/db/ex9.root_partition.map.reg_db.cdb
diff --git a/part_2/ex9/db/ex9.routing.rdb b/part_2/ex9/db/ex9.routing.rdb
index 6d15c42..e96d120 100644..100755
--- a/part_2/ex9/db/ex9.routing.rdb
+++ b/part_2/ex9/db/ex9.routing.rdb
diff --git a/part_2/ex9/db/ex9.rtlv.hdb b/part_2/ex9/db/ex9.rtlv.hdb
index 1194309..4ef2452 100644..100755
--- a/part_2/ex9/db/ex9.rtlv.hdb
+++ b/part_2/ex9/db/ex9.rtlv.hdb
diff --git a/part_2/ex9/db/ex9.rtlv_sg.cdb b/part_2/ex9/db/ex9.rtlv_sg.cdb
index cda087a..59f14dd 100644..100755
--- a/part_2/ex9/db/ex9.rtlv_sg.cdb
+++ b/part_2/ex9/db/ex9.rtlv_sg.cdb
diff --git a/part_2/ex9/db/ex9.rtlv_sg_swap.cdb b/part_2/ex9/db/ex9.rtlv_sg_swap.cdb
index fab1f8c..b693e9a 100644..100755
--- a/part_2/ex9/db/ex9.rtlv_sg_swap.cdb
+++ b/part_2/ex9/db/ex9.rtlv_sg_swap.cdb
diff --git a/part_2/ex9/db/ex9.sld_design_entry.sci b/part_2/ex9/db/ex9.sld_design_entry.sci
index 03eacdc..92c1102 100644..100755
--- a/part_2/ex9/db/ex9.sld_design_entry.sci
+++ b/part_2/ex9/db/ex9.sld_design_entry.sci
diff --git a/part_2/ex9/db/ex9.sld_design_entry_dsc.sci b/part_2/ex9/db/ex9.sld_design_entry_dsc.sci
index 03eacdc..92c1102 100644..100755
--- a/part_2/ex9/db/ex9.sld_design_entry_dsc.sci
+++ b/part_2/ex9/db/ex9.sld_design_entry_dsc.sci
diff --git a/part_2/ex9/db/ex9.smart_action.txt b/part_2/ex9/db/ex9.smart_action.txt
index c8e8a13..437a63e 100644..100755
--- a/part_2/ex9/db/ex9.smart_action.txt
+++ b/part_2/ex9/db/ex9.smart_action.txt
@@ -1 +1 @@
-DONE
+DONE
diff --git a/part_2/ex9/db/ex9.smp_dump.txt b/part_2/ex9/db/ex9.smp_dump.txt
index bd2b24e..26e74f6 100644..100755
--- a/part_2/ex9/db/ex9.smp_dump.txt
+++ b/part_2/ex9/db/ex9.smp_dump.txt
@@ -1,13 +1,13 @@
-
-State Machine - |ex9|delay:DEL0|state
-Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 
-state.IDLE 0 0 0 0 
-state.COUNTING 0 0 1 1 
-state.TIME_OUT 0 1 0 1 
-state.WAIT_LOW 1 0 0 1 
-
-State Machine - |ex9|formula_fsm:FSM|state
-Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 
-state.WAIT_TRIGGER 0 0 0 
-state.LIGHT_UP_LEDS 1 0 1 
-state.WAIT_FOR_TIMEOUT 1 1 0 
+
+State Machine - |ex9|delay:DEL0|state
+Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 
+state.IDLE 0 0 0 0 
+state.COUNTING 0 0 1 1 
+state.TIME_OUT 0 1 0 1 
+state.WAIT_LOW 1 0 0 1 
+
+State Machine - |ex9|formula_fsm:FSM|state
+Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 
+state.WAIT_TRIGGER 0 0 0 
+state.LIGHT_UP_LEDS 1 0 1 
+state.WAIT_FOR_TIMEOUT 1 1 0 
diff --git a/part_2/ex9/db/ex9.sta.qmsg b/part_2/ex9/db/ex9.sta.qmsg
index 6d964db..aab3a60 100644..100755
--- a/part_2/ex9/db/ex9.sta.qmsg
+++ b/part_2/ex9/db/ex9.sta.qmsg
@@ -1,53 +1,53 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481488260359 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition " "Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481488260364 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 11 20:31:00 2016 " "Processing started: Sun Dec 11 20:31:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481488260364 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260364 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260364 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488260408 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260942 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260942 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260979 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488260979 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261468 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261488 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261488 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481488261490 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481488261490 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481488261490 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261490 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261491 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261500 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488261501 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488261507 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481488261525 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261525 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.933 " "Worst-case setup slack is -3.933" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.933            -177.510 tick_50000:TICK0\|CLK_OUT  " "   -3.933            -177.510 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.353              -2.353 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -2.353              -2.353 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.198             -38.652 CLOCK_50  " "   -2.198             -38.652 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261525 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261525 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.222 " "Worst-case hold slack is 0.222" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.222               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.222               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.381               0.000 CLOCK_50  " "    0.381               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.023               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    1.023               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261527 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261527 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261528 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261528 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.658 " "Worst-case minimum pulse width slack is -0.658" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.658             -17.489 CLOCK_50  " "   -0.658             -17.489 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -41.338 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -41.338 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.439               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.439               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488261528 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261528 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488261535 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488261565 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262445 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262515 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481488262519 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262519 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.867 " "Worst-case setup slack is -3.867" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.867            -173.770 tick_50000:TICK0\|CLK_OUT  " "   -3.867            -173.770 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.391             -39.269 CLOCK_50  " "   -2.391             -39.269 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.208              -2.208 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -2.208              -2.208 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262520 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262520 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.218 " "Worst-case hold slack is 0.218" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.218               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.218               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.401               0.000 CLOCK_50  " "    0.401               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.821               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.821               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262521 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262521 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262522 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262523 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.707 " "Worst-case minimum pulse width slack is -0.707" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.707             -16.083 CLOCK_50  " "   -0.707             -16.083 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -42.153 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -42.153 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.422               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.422               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488262523 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262523 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488262529 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488262660 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263437 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263511 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481488263514 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263514 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.263 " "Worst-case setup slack is -2.263" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.263             -94.992 tick_50000:TICK0\|CLK_OUT  " "   -2.263             -94.992 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.029              -1.029 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.029              -1.029 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.002             -13.129 CLOCK_50  " "   -1.002             -13.129 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263515 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263515 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.065 " "Worst-case hold slack is 0.065" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.065               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.065               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.184               0.000 CLOCK_50  " "    0.184               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.518               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.518               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263517 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263517 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263518 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263518 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.771 " "Worst-case minimum pulse width slack is -0.771" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.771             -12.597 CLOCK_50  " "   -0.771             -12.597 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.035              -1.610 tick_50000:TICK0\|CLK_OUT  " "   -0.035              -1.610 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.481               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.481               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263519 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263519 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481488263526 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263693 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481488263695 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263695 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.967 " "Worst-case setup slack is -1.967" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.967             -82.047 tick_50000:TICK0\|CLK_OUT  " "   -1.967             -82.047 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.958             -11.100 CLOCK_50  " "   -0.958             -11.100 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.846              -0.846 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.846              -0.846 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263695 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263695 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.049 " "Worst-case hold slack is 0.049" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.049               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.049               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.175               0.000 CLOCK_50  " "    0.175               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.366               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.366               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263697 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263697 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263698 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263698 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.807 " "Worst-case minimum pulse width slack is -0.807" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.807             -14.887 CLOCK_50  " "   -0.807             -14.887 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.016              -0.422 tick_50000:TICK0\|CLK_OUT  " "   -0.016              -0.422 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.477               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.477               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481488263699 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488263699 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488265239 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488265240 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1216 " "Peak virtual memory: 1216 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481488265279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 11 20:31:05 2016 " "Processing ended: Sun Dec 11 20:31:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481488265279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481488265279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481488265279 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481488265279 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481112502374 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481112502377 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 07 12:08:21 2016 " "Processing started: Wed Dec 07 12:08:21 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481112502377 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112502377 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112502378 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112502505 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503130 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503130 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503180 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503180 ""}
+{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503779 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503861 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503862 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481112503864 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503864 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503869 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503894 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112503895 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112503939 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112503972 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503972 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.462 " "Worst-case setup slack is -3.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT  " "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.047             -40.775 CLOCK_50  " "   -2.047             -40.775 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112503984 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112503984 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.179               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504002 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504002 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504013 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504023 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.637 " "Worst-case minimum pulse width slack is -0.637" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.637             -18.132 CLOCK_50  " "   -0.637             -18.132 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112504032 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504032 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112504054 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112504090 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505120 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505353 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112505409 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505409 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.416 " "Worst-case setup slack is -3.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT  " "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.323             -41.799 CLOCK_50  " "   -2.323             -41.799 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505436 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505436 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.193               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.405               0.000 CLOCK_50  " "    0.405               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505454 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505454 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505465 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505488 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.689 " "Worst-case minimum pulse width slack is -0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.689             -16.816 CLOCK_50  " "   -0.689             -16.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112505519 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505519 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112505541 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112505804 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506731 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506844 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112506847 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506847 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT  " "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.918             -13.912 CLOCK_50  " "   -0.918             -13.912 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506855 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506855 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.020 " "Worst-case hold slack is -0.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT  " "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 CLOCK_50  " "    0.185               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506866 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506866 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506875 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506884 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.740 " "Worst-case minimum pulse width slack is -0.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.740             -12.957 CLOCK_50  " "   -0.740             -12.957 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT  " "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112506893 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112506893 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481112506923 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507323 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481112507325 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507325 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.581 " "Worst-case setup slack is -1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT  " "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.868             -11.639 CLOCK_50  " "   -0.868             -11.639 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507338 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507338 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.021 " "Worst-case hold slack is -0.021" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT  " "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507349 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507349 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507359 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507368 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.789 " "Worst-case minimum pulse width slack is -0.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.789             -15.486 CLOCK_50  " "   -0.789             -15.486 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.024               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481112507377 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112507377 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112509824 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112509826 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1213 " "Peak virtual memory: 1213 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 07 12:08:30 2016 " "Processing ended: Wed Dec 07 12:08:30 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481112510016 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481112510016 ""}
diff --git a/part_2/ex9/db/ex9.sta.rdb b/part_2/ex9/db/ex9.sta.rdb
index e2677ef..68555e7 100644..100755
--- a/part_2/ex9/db/ex9.sta.rdb
+++ b/part_2/ex9/db/ex9.sta.rdb
diff --git a/part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
index 465cbcd..6b64eb8 100644..100755
--- a/part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
+++ b/part_2/ex9/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex9/db/ex9.tis_db_list.ddb b/part_2/ex9/db/ex9.tis_db_list.ddb
index 2df45d7..88225e8 100644..100755
--- a/part_2/ex9/db/ex9.tis_db_list.ddb
+++ b/part_2/ex9/db/ex9.tis_db_list.ddb
diff --git a/part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddb b/part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddb
index 4719c12..921ec00 100644..100755
--- a/part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddb
+++ b/part_2/ex9/db/ex9.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddb b/part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddb
index f953c78..691218d 100644..100755
--- a/part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddb
+++ b/part_2/ex9/db/ex9.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddb b/part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddb
index 5d1ccd6..fb0a6c4 100644..100755
--- a/part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddb
+++ b/part_2/ex9/db/ex9.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddb b/part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddb
index 137bca4..2e4f8b4 100644..100755
--- a/part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddb
+++ b/part_2/ex9/db/ex9.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex9/db/ex9.tmw_info b/part_2/ex9/db/ex9.tmw_info
index 94024cd..b5caf45 100644..100755
--- a/part_2/ex9/db/ex9.tmw_info
+++ b/part_2/ex9/db/ex9.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:01:01
-start_analysis_synthesis:s:00:00:11-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:37-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
-start_timing_analyzer:s:00:00:06-start_full_compilation
+start_full_compilation:s:00:01:18
+start_analysis_synthesis:s:00:00:19-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:40-start_full_compilation
+start_assembler:s:00:00:09-start_full_compilation
+start_timing_analyzer:s:00:00:10-start_full_compilation
diff --git a/part_2/ex9/db/ex9.vpr.ammdb b/part_2/ex9/db/ex9.vpr.ammdb
index 519893b..51295de 100644..100755
--- a/part_2/ex9/db/ex9.vpr.ammdb
+++ b/part_2/ex9/db/ex9.vpr.ammdb
diff --git a/part_2/ex9/db/ex9_partition_pins.json b/part_2/ex9/db/ex9_partition_pins.json
index f8c0864..701d3b6 100644..100755
--- a/part_2/ex9/db/ex9_partition_pins.json
+++ b/part_2/ex9/db/ex9_partition_pins.json
@@ -1,201 +1,201 @@
-{
-	"partitions" : [
-		{
-			"name" : "Top",
-			"pins" : [
-				{
-					"name" : "HEX0[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX0[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX1[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX2[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX3[6]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[0]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[1]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[2]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[3]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[4]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[5]",
-					"strict" : false
-				},
-				{
-					"name" : "HEX4[6]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[0]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[1]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[2]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[3]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[4]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[5]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[6]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[7]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[8]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[9]",
-					"strict" : false
-				},
-				{
-					"name" : "KEY[0]",
-					"strict" : false
-				},
-				{
-					"name" : "CLOCK_50",
-					"strict" : false
-				},
-				{
-					"name" : "KEY[3]",
-					"strict" : false
-				}
-			]
-		}
-	]
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX4[6]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[0]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[1]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[2]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[3]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[4]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[5]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[6]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[7]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[8]",
+					"strict" : false
+				},
+				{
+					"name" : "LEDR[9]",
+					"strict" : false
+				},
+				{
+					"name" : "KEY[0]",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				},
+				{
+					"name" : "KEY[3]",
+					"strict" : false
+				}
+			]
+		}
+	]
 }
 \ No newline at end of file
diff --git a/part_2/ex9/db/prev_cmp_ex9.qmsg b/part_2/ex9/db/prev_cmp_ex9.qmsg
index 5a19f5a..5a19f5a 100644..100755
--- a/part_2/ex9/db/prev_cmp_ex9.qmsg
+++ b/part_2/ex9/db/prev_cmp_ex9.qmsg
diff --git a/part_2/ex9/ex9.qpf b/part_2/ex9/ex9.qpf
index 28b4ce8..28b4ce8 100644..100755
--- a/part_2/ex9/ex9.qpf
+++ b/part_2/ex9/ex9.qpf
diff --git a/part_2/ex9/ex9.qsf b/part_2/ex9/ex9.qsf
index dab96ce..af789d5 100644..100755
--- a/part_2/ex9/ex9.qsf
+++ b/part_2/ex9/ex9.qsf
@@ -252,7 +252,7 @@ set_global_assignment -name DEVICE 5CSEMA5F31C6
 set_global_assignment -name TOP_LEVEL_ENTITY ex9
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
diff --git a/part_2/ex9/ex9.qsf.bak b/part_2/ex9/ex9.qsf.bak
index d4eef07..d4eef07 100644..100755
--- a/part_2/ex9/ex9.qsf.bak
+++ b/part_2/ex9/ex9.qsf.bak
diff --git a/part_2/ex9/ex9.qws b/part_2/ex9/ex9.qws
new file mode 100755
index 0000000..518237b
--- /dev/null
+++ b/part_2/ex9/ex9.qws
diff --git a/part_2/ex9/ex9_assignment_defaults.qdf b/part_2/ex9/ex9_assignment_defaults.qdf
deleted file mode 100644
index 89a4543..0000000
--- a/part_2/ex9/ex9_assignment_defaults.qdf
+++ /dev/null
@@ -1,795 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2016  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Intel and sold by Intel or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-# Date created = 20:28:46  December 11, 2016
-#
-# -------------------------------------------------------------------------- #
-#
-# Note:
-#
-# 1) Do not modify this file. This file was generated
-#    automatically by the Quartus Prime software and is used
-#    to preserve global assignments across Quartus Prime versions.
-#
-# -------------------------------------------------------------------------- #
-
-set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
-set_global_assignment -name IP_COMPONENT_INTERNAL Off
-set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
-set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
-set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
-set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
-set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
-set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
-set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
-set_global_assignment -name HC_OUTPUT_DIR hc_output
-set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
-set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
-set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
-set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
-set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
-set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
-set_global_assignment -name REVISION_TYPE Base -family "Arria V"
-set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
-set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
-set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
-set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
-set_global_assignment -name DO_COMBINED_ANALYSIS Off
-set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
-set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
-set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
-set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
-set_global_assignment -name OPTIMIZATION_MODE Balanced
-set_global_assignment -name ALLOW_REGISTER_MERGING On
-set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
-set_global_assignment -name MUX_RESTRUCTURE Auto
-set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
-set_global_assignment -name ENABLE_IP_DEBUG Off
-set_global_assignment -name SAVE_DISK_SPACE On
-set_global_assignment -name OCP_HW_EVAL -value OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE Any
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name TRUE_WYSIWYG_FLOW Off
-set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
-set_global_assignment -name STATE_MACHINE_PROCESSING Auto
-set_global_assignment -name SAFE_STATE_MACHINE Off
-set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
-set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
-set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
-set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
-set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
-set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
-set_global_assignment -name PARALLEL_SYNTHESIS On
-set_global_assignment -name DSP_BLOCK_BALANCING Auto
-set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
-set_global_assignment -name NOT_GATE_PUSH_BACK On
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
-set_global_assignment -name IGNORE_CARRY_BUFFERS Off
-set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
-set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_LCELL_BUFFERS Off
-set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
-set_global_assignment -name IGNORE_SOFT_BUFFERS On
-set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
-set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
-set_global_assignment -name AUTO_GLOBAL_OE_MAX On
-set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
-set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
-set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name ALLOW_XOR_GATE_USAGE On
-set_global_assignment -name AUTO_LCELL_INSERTION On
-set_global_assignment -name CARRY_CHAIN_LENGTH 48
-set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
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-set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name CASCADE_CHAIN_LENGTH 2
-set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
-set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
-set_global_assignment -name AUTO_CARRY_CHAINS On
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-set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
-set_global_assignment -name AUTO_ROM_RECOGNITION On
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-set_global_assignment -name AUTO_DSP_RECOGNITION On
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
-set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
-set_global_assignment -name STRICT_RAM_RECOGNITION Off
-set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
-set_global_assignment -name FORCE_SYNCH_CLEAR Off
-set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
-set_global_assignment -name AUTO_RESOURCE_SHARING Off
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name MAX7000_FANIN_PER_CELL 100
-set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
-set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
-set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
-set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
-set_global_assignment -name REPORT_PARAMETER_SETTINGS On
-set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
-set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
-set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
-set_global_assignment -name HDL_MESSAGE_LEVEL Level2
-set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
-set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
-set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
-set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
-set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
-set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
-set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
-set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
-set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
-set_global_assignment -name BLOCK_DESIGN_NAMING Auto
-set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
-set_global_assignment -name SYNTHESIS_EFFORT Auto
-set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
-set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
-set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
-set_global_assignment -name MAX_LABS "-1 (Unlimited)"
-set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
-set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
-set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
-set_global_assignment -name PRPOF_ID Off
-set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
-set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
-set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
-set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
-set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
-set_global_assignment -name AUTO_MERGE_PLLS On
-set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
-set_global_assignment -name TXPMA_SLEW_RATE Low
-set_global_assignment -name ADCE_ENABLED Auto
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
-set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
-set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
-set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
-set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
-set_global_assignment -name ENABLE_NCEO_OUTPUT Off
-set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
-set_global_assignment -name STRATIX_UPDATE_MODE Standard
-set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
-set_global_assignment -name CVP_MODE Off
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
-set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
-set_global_assignment -name USE_CONF_DONE AUTO
-set_global_assignment -name USE_PWRMGT_SCL AUTO
-set_global_assignment -name USE_PWRMGT_SDA AUTO
-set_global_assignment -name USE_PWRMGT_ALERT AUTO
-set_global_assignment -name USE_INIT_DONE AUTO
-set_global_assignment -name USE_CVP_CONFDONE AUTO
-set_global_assignment -name USE_SEU_ERROR AUTO
-set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name USER_START_UP_CLOCK Off
-set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
-set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
-set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
-set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
-set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
-set_global_assignment -name ENABLE_VREFA_PIN Off
-set_global_assignment -name ENABLE_VREFB_PIN Off
-set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
-set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
-set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
-set_global_assignment -name INIT_DONE_OPEN_DRAIN On
-set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name ENABLE_CONFIGURATION_PINS On
-set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
-set_global_assignment -name ENABLE_NCE_PIN Off
-set_global_assignment -name ENABLE_BOOT_SEL_PIN On
-set_global_assignment -name CRC_ERROR_CHECKING Off
-set_global_assignment -name INTERNAL_SCRUBBING Off
-set_global_assignment -name PR_ERROR_OPEN_DRAIN On
-set_global_assignment -name PR_READY_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CVP_CONFDONE Off
-set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
-set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
-set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
-set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
-set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
-set_global_assignment -name OPTIMIZE_SSN Off
-set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
-set_global_assignment -name ECO_OPTIMIZE_TIMING Off
-set_global_assignment -name ECO_REGENERATE_REPORT Off
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
-set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
-set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
-set_global_assignment -name SEED 1
-set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
-set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
-set_global_assignment -name SLOW_SLEW_RATE Off
-set_global_assignment -name PCI_IO Off
-set_global_assignment -name TURBO_BIT On
-set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
-set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
-set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
-set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
-set_global_assignment -name NORMAL_LCELL_INSERT On
-set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
-set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
-set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
-set_global_assignment -name AUTO_TURBO_BIT ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
-set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
-set_global_assignment -name FITTER_EFFORT "Auto Fit"
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
-set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
-set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK On
-set_global_assignment -name AUTO_GLOBAL_OE On
-set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
-set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
-set_global_assignment -name ENABLE_HOLD_BACK_OFF On
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
-set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
-set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
-set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
-set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
-set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
-set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
-set_global_assignment -name PR_DONE_OPEN_DRAIN On
-set_global_assignment -name NCEO_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
-set_global_assignment -name ENABLE_PR_PINS Off
-set_global_assignment -name RESERVE_PR_PINS Off
-set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
-set_global_assignment -name PR_PINS_OPEN_DRAIN Off
-set_global_assignment -name CLAMPING_DIODE Off
-set_global_assignment -name TRI_STATE_SPI_PINS Off
-set_global_assignment -name UNUSED_TSD_PINS_GND Off
-set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
-set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
-set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
-set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
-set_global_assignment -name SEU_FIT_REPORT Off
-set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
-set_global_assignment -name COMPRESSION_MODE Off
-set_global_assignment -name CLOCK_SOURCE Internal
-set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
-set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
-set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
-set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
-set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
-set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
-set_global_assignment -name SECURITY_BIT Off
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
-set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
-set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
-set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
-set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
-set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
-set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
-set_global_assignment -name GENERATE_TTF_FILE Off
-set_global_assignment -name GENERATE_RBF_FILE Off
-set_global_assignment -name GENERATE_HEX_FILE Off
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
-set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
-set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
-set_global_assignment -name AUTO_RESTART_CONFIGURATION On
-set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
-set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
-set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
-set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
-set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
-set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
-set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
-set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
-set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
-set_global_assignment -name POR_SCHEME "Instant ON"
-set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
-set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
-set_global_assignment -name POF_VERIFY_PROTECT Off
-set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
-set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
-set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
-set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
-set_global_assignment -name GENERATE_PMSF_FILES On
-set_global_assignment -name START_TIME 0ns
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
-set_global_assignment -name SETUP_HOLD_DETECTION Off
-set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
-set_global_assignment -name CHECK_OUTPUTS Off
-set_global_assignment -name SIMULATION_COVERAGE On
-set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name GLITCH_DETECTION Off
-set_global_assignment -name GLITCH_INTERVAL 1ns
-set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
-set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
-set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
-set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
-set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
-set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
-set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
-set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
-set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
-set_global_assignment -name DRC_TOP_FANOUT 50
-set_global_assignment -name DRC_FANOUT_EXCEEDING 30
-set_global_assignment -name DRC_GATED_CLOCK_FEED 30
-set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
-set_global_assignment -name ENABLE_DRC_SETTINGS Off
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
-set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
-set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
-set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
-set_global_assignment -name MERGE_HEX_FILE Off
-set_global_assignment -name GENERATE_SVF_FILE Off
-set_global_assignment -name GENERATE_ISC_FILE Off
-set_global_assignment -name GENERATE_JAM_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
-set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
-set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
-set_global_assignment -name HPS_EARLY_IO_RELEASE Off
-set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
-set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
-set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_USE_PVA On
-set_global_assignment -name POWER_USE_INPUT_FILE "No File"
-set_global_assignment -name POWER_USE_INPUT_FILES Off
-set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
-set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
-set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
-set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
-set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
-set_global_assignment -name POWER_TJ_VALUE 25
-set_global_assignment -name POWER_USE_TA_VALUE 25
-set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
-set_global_assignment -name POWER_BOARD_TEMPERATURE 25
-set_global_assignment -name POWER_HPS_ENABLE Off
-set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
-set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
-set_global_assignment -name IGNORE_PARTITIONS Off
-set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
-set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
-set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
-set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
-set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
-set_global_assignment -name RTLV_GROUP_RELATED_NODES On
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
-set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
-set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
-set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
-set_global_assignment -name EQC_BBOX_MERGE On
-set_global_assignment -name EQC_LVDS_MERGE On
-set_global_assignment -name EQC_RAM_UNMERGING On
-set_global_assignment -name EQC_DFF_SS_EMULATION On
-set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
-set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
-set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
-set_global_assignment -name EQC_STRUCTURE_MATCHING On
-set_global_assignment -name EQC_AUTO_BREAK_CONE On
-set_global_assignment -name EQC_POWER_UP_COMPARE Off
-set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
-set_global_assignment -name EQC_AUTO_INVERSION On
-set_global_assignment -name EQC_AUTO_TERMINATE On
-set_global_assignment -name EQC_SUB_CONE_REPORT Off
-set_global_assignment -name EQC_RENAMING_RULES On
-set_global_assignment -name EQC_PARAMETER_CHECK On
-set_global_assignment -name EQC_AUTO_PORTSWAP On
-set_global_assignment -name EQC_DETECT_DONT_CARES On
-set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
-set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
-set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
-set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
-set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
-set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
-set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
-set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
-set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
-set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
-set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
-set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
-set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
-set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
-set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
-set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
-set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
-set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
-set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
-set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
-set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
-set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
-set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
-set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
-set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
-set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
-set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
-set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
-set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
-set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
-set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
-set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
-set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
-set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
-set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
-set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
-set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
-set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
-set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
-set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
-set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
-set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/part_2/ex9/incremental_db/README b/part_2/ex9/incremental_db/README
index 6191fbe..6191fbe 100644..100755
--- a/part_2/ex9/incremental_db/README
+++ b/part_2/ex9/incremental_db/README
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info b/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
index 4aad5b9..f84b742 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.db_info
@@ -1,3 +1,3 @@
-Quartus_Version = Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Version_Index = 419480576
-Creation_Time = Sun Dec 11 20:28:46 2016
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Nov 25 10:41:49 2016
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
index 03f9cd0..5548723 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
index fcfae5a..c0fbf3e 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
index b1c67d6..b1c67d6 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
index 2950f00..926b6ab 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
index 431891a..e9d3716 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
index af9b8e9..af9b8e9 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
index f51c2b8..d0adce8 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
index 626799f..d45424f 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
@@ -1 +1 @@
-v1
+v1
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
index 370a8f5..614de49 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
index 3fbb214..7f6ab88 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpi b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
index e1634ea..ff7d621 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
index 0224820..e4db04f 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
index 8210c55..8210c55 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
index 4615adb..963b5cc 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
index af9b8e9..af9b8e9 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
index bc4d8d2..a65cde8 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kpt b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
index 2944142..7826f1d 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
index 26d62d0..26d62d0 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
new file mode 100755
index 0000000..1b63352
--- /dev/null
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
new file mode 100755
index 0000000..bf98b99
--- /dev/null
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.opi b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.opi
@@ -0,0 +1 @@
+1
+\ No newline at end of file
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
index 26d62d0..26d62d0 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
new file mode 100755
index 0000000..ecc33d2
--- /dev/null
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
new file mode 100755
index 0000000..5b44096
--- /dev/null
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
new file mode 100755
index 0000000..7f6ab88
--- /dev/null
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
index 50abb6e..e4db04f 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.cdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..963b5cc
--- /dev/null
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
new file mode 100755
index 0000000..a65cde8
--- /dev/null
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
index 7826f1d..7826f1d 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdb
index 00b36c3..e0bf383 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.rrp.hdb
diff --git a/part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdb b/part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdb
index 1d9c08e..f715ca1 100644..100755
--- a/part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdb
+++ b/part_2/ex9/incremental_db/compiled_partitions/ex9.rrs.cdb
diff --git a/part_2/ex9/output_files/ex9.asm.rpt b/part_2/ex9/output_files/ex9.asm.rpt
index 1851753..abf1d89 100644..100755
--- a/part_2/ex9/output_files/ex9.asm.rpt
+++ b/part_2/ex9/output_files/ex9.asm.rpt
@@ -1,92 +1,92 @@
-Assembler report for ex9
-Sun Dec 11 20:30:59 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: ex9.sof
-  6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Sun Dec 11 20:30:59 2016 ;
-; Revision Name         ; ex9                                   ;
-; Top-level Entity Name ; ex9                                   ;
-; Family                ; Cyclone V                             ;
-; Device                ; 5CSEMA5F31C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings               ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+---------------------------+
-; Assembler Generated Files ;
-+---------------------------+
-; File Name                 ;
-+---------------------------+
-; ex9.sof                   ;
-+---------------------------+
-
-
-+-----------------------------------+
-; Assembler Device Options: ex9.sof ;
-+----------------+------------------+
-; Option         ; Setting          ;
-+----------------+------------------+
-; Device         ; 5CSEMA5F31C6     ;
-; JTAG usercode  ; 0x00B4AD1F       ;
-; Checksum       ; 0x00B4AD1F       ;
-+----------------+------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 20:30:53 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 979 megabytes
-    Info: Processing ended: Sun Dec 11 20:30:59 2016
-    Info: Elapsed time: 00:00:06
-    Info: Total CPU time (on all processors): 00:00:06
-
-
+Assembler report for ex9
+Wed Dec 07 12:08:20 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Wed Dec 07 12:08:20 2016 ;
+; Revision Name         ; ex9                                   ;
+; Top-level Entity Name ; ex9                                   ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++----------------------------------------------------------------------------+
+; Assembler Generated Files                                                  ;
++----------------------------------------------------------------------------+
+; File Name                                                                  ;
++----------------------------------------------------------------------------+
+; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
++----------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.sof ;
++----------------+-------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                             ;
++----------------+-------------------------------------------------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                                                        ;
+; JTAG usercode  ; 0x00B4D80C                                                                          ;
+; Checksum       ; 0x00B4D80C                                                                          ;
++----------------+-------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:08:12 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 896 megabytes
+    Info: Processing ended: Wed Dec 07 12:08:20 2016
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex9/output_files/ex9.done b/part_2/ex9/output_files/ex9.done
index 3f30efe..2aa652f 100644..100755
--- a/part_2/ex9/output_files/ex9.done
+++ b/part_2/ex9/output_files/ex9.done
@@ -1 +1 @@
-Sun Dec 11 20:31:05 2016
+Wed Dec 07 12:08:31 2016
diff --git a/part_2/ex9/output_files/ex9.fit.rpt b/part_2/ex9/output_files/ex9.fit.rpt
index bc51ba0..90d3227 100644..100755
--- a/part_2/ex9/output_files/ex9.fit.rpt
+++ b/part_2/ex9/output_files/ex9.fit.rpt
@@ -1,2129 +1,2129 @@
-Fitter report for ex9
-Sun Dec 11 20:30:51 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. Fitter Netlist Optimizations
-  6. Ignored Assignments
-  7. Incremental Compilation Preservation Summary
-  8. Incremental Compilation Partition Settings
-  9. Incremental Compilation Placement Preservation
- 10. Pin-Out File
- 11. Fitter Resource Usage Summary
- 12. Fitter Partition Statistics
- 13. Input Pins
- 14. Output Pins
- 15. I/O Bank Usage
- 16. All Package Pins
- 17. I/O Assignment Warnings
- 18. Fitter Resource Utilization by Entity
- 19. Delay Chain Summary
- 20. Pad To Core Delay Chain Fanout
- 21. Control Signals
- 22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. I/O Rules Summary
- 25. I/O Rules Details
- 26. I/O Rules Matrix
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing Summary
- 30. Estimated Delay Added for Hold Timing Details
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Fitter Summary                                                                ;
-+---------------------------------+---------------------------------------------+
-; Fitter Status                   ; Successful - Sun Dec 11 20:30:51 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex9                                         ;
-; Top-level Entity Name           ; ex9                                         ;
-; Family                          ; Cyclone V                                   ;
-; Device                          ; 5CSEMA5F31C6                                ;
-; Timing Models                   ; Final                                       ;
-; Logic utilization (in ALMs)     ; 154 / 32,070 ( < 1 % )                      ;
-; Total registers                 ; 94                                          ;
-; Total pins                      ; 57 / 457 ( 12 % )                           ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                       ;
-; Total RAM Blocks                ; 0 / 397 ( 0 % )                             ;
-; Total DSP Blocks                ; 0 / 87 ( 0 % )                              ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0 / 6 ( 0 % )                               ;
-; Total DLLs                      ; 0 / 4 ( 0 % )                               ;
-+---------------------------------+---------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
-; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
-; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
-; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
-; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
-; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; Clamping Diode                                                             ; Off                                   ; Off                                   ;
-; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
-; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.03        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.9%      ;
-;     Processor 3            ;   0.9%      ;
-;     Processor 4            ;   0.9%      ;
-+----------------------------+-------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations                                                                                                                                                                                                            ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;
-; formula_fsm:FSM|count[1]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[1]~DUPLICATE   ;                  ;                       ;
-; formula_fsm:FSM|count[4]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[4]~DUPLICATE   ;                  ;                       ;
-; formula_fsm:FSM|count[6]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[6]~DUPLICATE   ;                  ;                       ;
-; formula_fsm:FSM|count[8]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[8]~DUPLICATE   ;                  ;                       ;
-; tick_50000:TICK0|count[0]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[0]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[3]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[3]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[9]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[9]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[11]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[13]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Ignored Assignments                                                                        ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
-; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
-; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
-; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
-; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
-+--------------+----------------+--------------+------------+---------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary                                                     ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+--------------------+----------------------------+--------------------------+
-; Placement (by node) ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 477 ) ; 0.00 % ( 0 / 477 )         ; 0.00 % ( 0 / 477 )       ;
-;     -- Achieved     ; 0.00 % ( 0 / 477 ) ; 0.00 % ( 0 / 477 )         ; 0.00 % ( 0 / 477 )       ;
-;                     ;                    ;                            ;                          ;
-; Routing (by net)    ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
-+---------------------+--------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                                                             ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                                                                     ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 477 )    ; N/A                     ; Source File       ; N/A                 ;       ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.pin.
-
-
-+------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                                            ;
-+-------------------------------------------------------------+--------------------+-------+
-; Resource                                                    ; Usage              ; %     ;
-+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 154 / 32,070       ; < 1 % ;
-; ALMs needed [=A-B+C]                                        ; 154                ;       ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 160 / 32,070       ; < 1 % ;
-;         [a] ALMs used for LUT logic and registers           ; 34                 ;       ;
-;         [b] ALMs used for LUT logic                         ; 119                ;       ;
-;         [c] ALMs used for registers                         ; 7                  ;       ;
-;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 6 / 32,070         ; < 1 % ;
-;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
-;         [a] Due to location constrained logic               ; 0                  ;       ;
-;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
-;         [c] Due to LAB input limits                         ; 0                  ;       ;
-;         [d] Due to virtual I/Os                             ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Difficulty packing design                                   ; Low                ;       ;
-;                                                             ;                    ;       ;
-; Total LABs:  partially or completely used                   ; 21 / 3,207         ; < 1 % ;
-;     -- Logic LABs                                           ; 21                 ;       ;
-;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
-;                                                             ;                    ;       ;
-; Combinational ALUT usage for logic                          ; 281                ;       ;
-;     -- 7 input functions                                    ; 2                  ;       ;
-;     -- 6 input functions                                    ; 35                 ;       ;
-;     -- 5 input functions                                    ; 5                  ;       ;
-;     -- 4 input functions                                    ; 154                ;       ;
-;     -- <=3 input functions                                  ; 85                 ;       ;
-; Combinational ALUT usage for route-throughs                 ; 3                  ;       ;
-;                                                             ;                    ;       ;
-; Dedicated logic registers                                   ; 94                 ;       ;
-;     -- By type:                                             ;                    ;       ;
-;         -- Primary logic registers                          ; 81 / 64,140        ; < 1 % ;
-;         -- Secondary logic registers                        ; 13 / 64,140        ; < 1 % ;
-;     -- By function:                                         ;                    ;       ;
-;         -- Design implementation registers                  ; 81                 ;       ;
-;         -- Routing optimization registers                   ; 13                 ;       ;
-;                                                             ;                    ;       ;
-; Virtual pins                                                ; 0                  ;       ;
-; I/O pins                                                    ; 57 / 457           ; 12 %  ;
-;     -- Clock pins                                           ; 4 / 8              ; 50 %  ;
-;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
-;                                                             ;                    ;       ;
-; Hard processor system peripheral utilization                ;                    ;       ;
-;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
-;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
-;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
-;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
-;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
-;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
-;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
-;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
-;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
-;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
-;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
-;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
-;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
-;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
-;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
-;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
-;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
-;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
-;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
-;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
-;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
-;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
-;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
-;                                                             ;                    ;       ;
-; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
-; Total MLAB memory bits                                      ; 0                  ;       ;
-; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
-; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
-;                                                             ;                    ;       ;
-; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
-;                                                             ;                    ;       ;
-; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
-; Global signals                                              ; 1                  ;       ;
-;     -- Global clocks                                        ; 1 / 16             ; 6 %   ;
-;     -- Quadrant clocks                                      ; 0 / 66             ; 0 %   ;
-;     -- Horizontal periphery clocks                          ; 0 / 18             ; 0 %   ;
-; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
-; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
-; JTAGs                                                       ; 0 / 1              ; 0 %   ;
-; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
-; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
-; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
-; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
-; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
-; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
-; Average interconnect usage (total/H/V)                      ; 0.2% / 0.2% / 0.1% ;       ;
-; Peak interconnect usage (total/H/V)                         ; 2.1% / 2.5% / 1.2% ;       ;
-; Maximum fan-out                                             ; 68                 ;       ;
-; Highest non-global fan-out                                  ; 68                 ;       ;
-; Total fan-out                                               ; 1416               ;       ;
-; Average fan-out                                             ; 2.87               ;       ;
-+-------------------------------------------------------------+--------------------+-------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics                                                                                          ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 154 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-; ALMs needed [=A-B+C]                                        ; 154                   ; 0                              ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 160 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-;         [a] ALMs used for LUT logic and registers           ; 34                    ; 0                              ;
-;         [b] ALMs used for LUT logic                         ; 119                   ; 0                              ;
-;         [c] ALMs used for registers                         ; 7                     ; 0                              ;
-;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 6 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
-;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
-;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
-;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
-;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
-;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Difficulty packing design                                   ; Low                   ; Low                            ;
-;                                                             ;                       ;                                ;
-; Total LABs:  partially or completely used                   ; 21 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
-;     -- Logic LABs                                           ; 21                    ; 0                              ;
-;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Combinational ALUT usage for logic                          ; 281                   ; 0                              ;
-;     -- 7 input functions                                    ; 2                     ; 0                              ;
-;     -- 6 input functions                                    ; 35                    ; 0                              ;
-;     -- 5 input functions                                    ; 5                     ; 0                              ;
-;     -- 4 input functions                                    ; 154                   ; 0                              ;
-;     -- <=3 input functions                                  ; 85                    ; 0                              ;
-; Combinational ALUT usage for route-throughs                 ; 3                     ; 0                              ;
-; Memory ALUT usage                                           ; 0                     ; 0                              ;
-;     -- 64-address deep                                      ; 0                     ; 0                              ;
-;     -- 32-address deep                                      ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Dedicated logic registers                                   ; 0                     ; 0                              ;
-;     -- By type:                                             ;                       ;                                ;
-;         -- Primary logic registers                          ; 81 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
-;         -- Secondary logic registers                        ; 13 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
-;     -- By function:                                         ;                       ;                                ;
-;         -- Design implementation registers                  ; 81                    ; 0                              ;
-;         -- Routing optimization registers                   ; 13                    ; 0                              ;
-;                                                             ;                       ;                                ;
-;                                                             ;                       ;                                ;
-; Virtual pins                                                ; 0                     ; 0                              ;
-; I/O pins                                                    ; 57                    ; 0                              ;
-; I/O registers                                               ; 0                     ; 0                              ;
-; Total block memory bits                                     ; 0                     ; 0                              ;
-; Total block memory implementation bits                      ; 0                     ; 0                              ;
-; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
-;                                                             ;                       ;                                ;
-; Connections                                                 ;                       ;                                ;
-;     -- Input Connections                                    ; 0                     ; 0                              ;
-;     -- Registered Input Connections                         ; 0                     ; 0                              ;
-;     -- Output Connections                                   ; 0                     ; 0                              ;
-;     -- Registered Output Connections                        ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Internal Connections                                        ;                       ;                                ;
-;     -- Total Connections                                    ; 1416                  ; 0                              ;
-;     -- Registered Connections                               ; 424                   ; 0                              ;
-;                                                             ;                       ;                                ;
-; External Connections                                        ;                       ;                                ;
-;     -- Top                                                  ; 0                     ; 0                              ;
-;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Partition Interface                                         ;                       ;                                ;
-;     -- Input Ports                                          ; 5                     ; 0                              ;
-;     -- Output Ports                                         ; 52                    ; 0                              ;
-;     -- Bidir Ports                                          ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Registered Ports                                            ;                       ;                                ;
-;     -- Registered Input Ports                               ; 0                     ; 0                              ;
-;     -- Registered Output Ports                              ; 0                     ; 0                              ;
-;                                                             ;                       ;                                ;
-; Port Connectivity                                           ;                       ;                                ;
-;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
-;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
-;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
-;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
-;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
-;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
-;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
-;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                              ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 26                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[0] ; V25   ; 5B       ; 89           ; 20           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[1] ; AA28  ; 5B       ; 89           ; 21           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[2] ; Y27   ; 5B       ; 89           ; 25           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[3] ; AB27  ; 5B       ; 89           ; 23           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[4] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[5] ; AA26  ; 5B       ; 89           ; 23           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[6] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-+---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------+
-; I/O Bank Usage                                                              ;
-+----------+-------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+-------------------+---------------+--------------+---------------+
-; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
-; B1L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
-; 3A       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 3B       ; 5 / 48 ( 10 % )   ; 3.3V          ; --           ; 3.3V          ;
-; 4A       ; 7 / 80 ( 9 % )    ; 3.3V          ; --           ; 3.3V          ;
-; 5A       ; 32 / 32 ( 100 % ) ; 3.3V          ; --           ; 3.3V          ;
-; 5B       ; 13 / 16 ( 81 % )  ; 3.3V          ; --           ; 3.3V          ;
-; 6B       ; 0 / 44 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 6A       ; 0 / 56 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7A       ; 0 / 19 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7B       ; 0 / 22 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7C       ; 0 / 12 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7D       ; 0 / 14 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 8A       ; 0 / 80 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-+----------+-------------------+---------------+--------------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                                  ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA25     ; 224        ; 5A             ; HEX5[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA26     ; 252        ; 5B             ; HEX5[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA28     ; 251        ; 5B             ; HEX5[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB26     ; 226        ; 5A             ; HEX5[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB27     ; 254        ; 5B             ; HEX5[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
-; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
-; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
-; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
-; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
-; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
-; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V25      ; 246        ; 5B             ; HEX5[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y27      ; 258        ; 5B             ; HEX5[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-------------------------------------------------+
-; I/O Assignment Warnings                         ;
-+----------+--------------------------------------+
-; Pin Name ; Reason                               ;
-+----------+--------------------------------------+
-; HEX0[0]  ; Missing drive strength and slew rate ;
-; HEX0[1]  ; Missing drive strength and slew rate ;
-; HEX0[2]  ; Missing drive strength and slew rate ;
-; HEX0[3]  ; Missing drive strength and slew rate ;
-; HEX0[4]  ; Missing drive strength and slew rate ;
-; HEX0[5]  ; Missing drive strength and slew rate ;
-; HEX0[6]  ; Missing drive strength and slew rate ;
-; HEX1[0]  ; Missing drive strength and slew rate ;
-; HEX1[1]  ; Missing drive strength and slew rate ;
-; HEX1[2]  ; Missing drive strength and slew rate ;
-; HEX1[3]  ; Missing drive strength and slew rate ;
-; HEX1[4]  ; Missing drive strength and slew rate ;
-; HEX1[5]  ; Missing drive strength and slew rate ;
-; HEX1[6]  ; Missing drive strength and slew rate ;
-; HEX2[0]  ; Missing drive strength and slew rate ;
-; HEX2[1]  ; Missing drive strength and slew rate ;
-; HEX2[2]  ; Missing drive strength and slew rate ;
-; HEX2[3]  ; Missing drive strength and slew rate ;
-; HEX2[4]  ; Missing drive strength and slew rate ;
-; HEX2[5]  ; Missing drive strength and slew rate ;
-; HEX2[6]  ; Missing drive strength and slew rate ;
-; HEX3[0]  ; Missing drive strength and slew rate ;
-; HEX3[1]  ; Missing drive strength and slew rate ;
-; HEX3[2]  ; Missing drive strength and slew rate ;
-; HEX3[3]  ; Missing drive strength and slew rate ;
-; HEX3[4]  ; Missing drive strength and slew rate ;
-; HEX3[5]  ; Missing drive strength and slew rate ;
-; HEX3[6]  ; Missing drive strength and slew rate ;
-; HEX4[0]  ; Missing drive strength and slew rate ;
-; HEX4[1]  ; Missing drive strength and slew rate ;
-; HEX4[2]  ; Missing drive strength and slew rate ;
-; HEX4[3]  ; Missing drive strength and slew rate ;
-; HEX4[4]  ; Missing drive strength and slew rate ;
-; HEX4[5]  ; Missing drive strength and slew rate ;
-; HEX4[6]  ; Missing drive strength and slew rate ;
-; HEX5[0]  ; Missing drive strength and slew rate ;
-; HEX5[1]  ; Missing drive strength and slew rate ;
-; HEX5[2]  ; Missing drive strength and slew rate ;
-; HEX5[3]  ; Missing drive strength and slew rate ;
-; HEX5[4]  ; Missing drive strength and slew rate ;
-; HEX5[5]  ; Missing drive strength and slew rate ;
-; HEX5[6]  ; Missing drive strength and slew rate ;
-; LEDR[0]  ; Missing drive strength and slew rate ;
-; LEDR[1]  ; Missing drive strength and slew rate ;
-; LEDR[2]  ; Missing drive strength and slew rate ;
-; LEDR[3]  ; Missing drive strength and slew rate ;
-; LEDR[4]  ; Missing drive strength and slew rate ;
-; LEDR[5]  ; Missing drive strength and slew rate ;
-; LEDR[6]  ; Missing drive strength and slew rate ;
-; LEDR[7]  ; Missing drive strength and slew rate ;
-; LEDR[8]  ; Missing drive strength and slew rate ;
-; LEDR[9]  ; Missing drive strength and slew rate ;
-+----------+--------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9                       ; 154.0 (0.5)          ; 159.0 (0.5)                      ; 5.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 281 (1)             ; 94 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
-;    |LFSR:LFSR0|            ; 3.0 (3.0)            ; 3.5 (3.5)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 67.2 (0.0)           ; 67.5 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 123 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A1|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A10|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 1.5 (1.5)            ; 1.5 (1.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A32|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
-;       |add3_ge5:A33|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 3.7 (3.7)            ; 4.0 (4.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:COUNT0|     ; 8.5 (8.5)            ; 9.0 (9.0)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
-;    |delay:DEL0|            ; 13.3 (13.3)          ; 13.8 (13.8)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 23 (23)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 21.5 (21.5)          ; 24.2 (24.2)                      ; 2.7 (2.7)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 37 (37)             ; 26 (26)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
-;    |tick_50000:TICK0|      ; 18.5 (18.5)          ; 19.0 (19.0)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 26 (26)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                                                     ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; KEY[0]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; CLOCK_50 ; Input    ; -- ; (0)  ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[3]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-+----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                                                ;
-+-------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;
-+-------------------------------------------------+-------------------+---------+
-; KEY[1]                                          ;                   ;         ;
-; KEY[2]                                          ;                   ;         ;
-; KEY[0]                                          ;                   ;         ;
-;      - counter_16:COUNT0|count~0                ; 0                 ; 0       ;
-; CLOCK_50                                        ;                   ;         ;
-;      - tick_50000:TICK0|CLK_OUT                 ; 1                 ; 0       ;
-; KEY[3]                                          ;                   ;         ;
-;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~1 ; 1                 ; 0       ;
-;      - formula_fsm:FSM|Selector2~0              ; 1                 ; 0       ;
-;      - formula_fsm:FSM|Selector3~0              ; 1                 ; 0       ;
-+-------------------------------------------------+-------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                                                                                 ;
-+-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; Name                                ; Location            ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50                            ; PIN_AF14            ; 2       ; Clock                      ; no     ; --                   ; --               ; --                        ;
-; CLOCK_50                            ; PIN_AF14            ; 25      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
-; counter_16:COUNT0|count~0           ; LABCELL_X18_Y3_N57  ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; counter_16:COUNT0|state             ; FF_X18_Y3_N53       ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|count[1]~0               ; MLABCELL_X34_Y3_N48 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|state.COUNTING           ; FF_X34_Y3_N5        ; 18      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X34_Y3_N14       ; 22      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.WAIT_TRIGGER  ; FF_X34_Y3_N35       ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; tick_50000:TICK0|CLK_OUT            ; FF_X4_Y3_N23        ; 68      ; Clock                      ; no     ; --                   ; --               ; --                        ;
-+-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals                                                                         ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 25      ; Global Clock         ; GCLK6            ; --                        ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------+
-; Routing Usage Summary                                                 ;
-+---------------------------------------------+-------------------------+
-; Routing Resource Type                       ; Usage                   ;
-+---------------------------------------------+-------------------------+
-; Block interconnects                         ; 366 / 289,320 ( < 1 % ) ;
-; C12 interconnects                           ; 7 / 13,420 ( < 1 % )    ;
-; C2 interconnects                            ; 62 / 119,108 ( < 1 % )  ;
-; C4 interconnects                            ; 96 / 56,300 ( < 1 % )   ;
-; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
-; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
-; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
-; Direct links                                ; 78 / 289,320 ( < 1 % )  ;
-; Global clocks                               ; 1 / 16 ( 6 % )          ;
-; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
-; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
-; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
-; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
-; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
-; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
-; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
-; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
-; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
-; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
-; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
-; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
-; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
-; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
-; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
-; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
-; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
-; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
-; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
-; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
-; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
-; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
-; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
-; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
-; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
-; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
-; Local interconnects                         ; 128 / 84,580 ( < 1 % )  ;
-; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
-; R14 interconnects                           ; 95 / 12,676 ( < 1 % )   ;
-; R14/C12 interconnect drivers                ; 100 / 20,720 ( < 1 % )  ;
-; R3 interconnects                            ; 176 / 130,992 ( < 1 % ) ;
-; R6 interconnects                            ; 289 / 266,960 ( < 1 % ) ;
-; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
-; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
-+---------------------------------------------+-------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 28    ;
-; Number of I/O Rules Passed       ; 6     ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 22    ;
-+----------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                  ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
-; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
-; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
-; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
-; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
-; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Pin/Rules          ; IO_000002    ; IO_000003 ; IO_000001 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000022    ; IO_000021    ; IO_000046    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000047    ; IO_000020    ; IO_000019    ; IO_000018    ; IO_000015    ; IO_000014    ; IO_000013    ; IO_000012    ; IO_000011    ; IO_000010 ; IO_000009 ; IO_000034    ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Total Pass         ; 0            ; 57        ; 57        ; 0            ; 0            ; 57        ; 57        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 57        ; 57        ; 0            ;
-; Total Unchecked    ; 0            ; 0         ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ;
-; Total Inapplicable ; 57           ; 0         ; 0         ; 57           ; 57           ; 0         ; 0         ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 0         ; 0         ; 57           ;
-; Total Fail         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0         ; 0            ;
-; KEY[1]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; KEY[2]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX0[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX1[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX2[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX3[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX4[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX5[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX5[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX5[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX5[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX5[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX5[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; HEX5[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[0]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[1]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[2]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[3]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[4]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[5]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[6]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[7]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[8]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; LEDR[9]            ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; KEY[0]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; CLOCK_50           ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-; KEY[3]             ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ;
-+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Fitter Device Options                                                                          ;
-+------------------------------------------------------------------+-----------------------------+
-; Option                                                           ; Setting                     ;
-+------------------------------------------------------------------+-----------------------------+
-; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
-; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
-; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
-; Enable INIT_DONE output                                          ; Off                         ;
-; Configuration scheme                                             ; Passive Serial              ;
-; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
-; Enable CvP_CONFDONE pin                                          ; Off                         ;
-; Enable open drain on CRC_ERROR pin                               ; On                          ;
-; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
-; Enable open drain on INIT_DONE pin                               ; On                          ;
-; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
-; Enable open drain on nCEO pin                                    ; On                          ;
-; Enable Partial Reconfiguration pins                              ; Off                         ;
-; Enable input tri-state on active configuration pins in user mode ; Off                         ;
-; Enable internal scrubbing                                        ; Off                         ;
-; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
-; Device initialization clock source                               ; Internal Oscillator         ;
-; Configuration via Protocol                                       ; Off                         ;
-; Configuration Voltage Level                                      ; Auto                        ;
-; Force Configuration Voltage Level                                ; Off                         ;
-; Enable nCEO output                                               ; Off                         ;
-; Data[15..8]                                                      ; Unreserved                  ;
-; Data[7..5]                                                       ; Unreserved                  ;
-; Base pin-out file on sameframe device                            ; Off                         ;
-+------------------------------------------------------------------+-----------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.10 V ;
-; Low Junction Temperature  ; 0 �C   ;
-; High Junction Temperature ; 85 �C  ;
-+---------------------------+--------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary                                                               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 89.8              ;
-; CLOCK_50                                                     ; CLOCK_50                 ; 11.0              ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 6.9               ;
-; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.8               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details                                                       ;
-+----------------------------------------+----------------------------------------+-------------------+
-; Source Register                        ; Destination Register                   ; Delay Added in ns ;
-+----------------------------------------+----------------------------------------+-------------------+
-; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; 3.263             ;
-; formula_fsm:FSM|start_delay            ; delay:DEL0|state.COUNTING              ; 3.060             ;
-; formula_fsm:FSM|count[6]               ; formula_fsm:FSM|ledr[8]                ; 1.663             ;
-; formula_fsm:FSM|count[7]               ; formula_fsm:FSM|ledr[8]                ; 1.638             ;
-; formula_fsm:FSM|count[8]               ; formula_fsm:FSM|ledr[8]                ; 1.633             ;
-; delay:DEL0|count[8]                    ; delay:DEL0|state.IDLE                  ; 1.617             ;
-; formula_fsm:FSM|count[1]               ; formula_fsm:FSM|ledr[8]                ; 1.586             ;
-; delay:DEL0|count[6]                    ; delay:DEL0|state.IDLE                  ; 1.573             ;
-; formula_fsm:FSM|count[0]               ; formula_fsm:FSM|ledr[8]                ; 1.564             ;
-; formula_fsm:FSM|count[3]               ; formula_fsm:FSM|ledr[8]                ; 1.562             ;
-; formula_fsm:FSM|count[2]               ; formula_fsm:FSM|ledr[8]                ; 1.560             ;
-; delay:DEL0|count[2]                    ; delay:DEL0|state.IDLE                  ; 1.551             ;
-; delay:DEL0|count[3]                    ; delay:DEL0|state.IDLE                  ; 1.546             ;
-; delay:DEL0|count[13]                   ; delay:DEL0|state.IDLE                  ; 1.535             ;
-; delay:DEL0|count[10]                   ; delay:DEL0|state.IDLE                  ; 1.532             ;
-; formula_fsm:FSM|count[4]               ; formula_fsm:FSM|ledr[8]                ; 1.513             ;
-; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT               ; 1.470             ;
-; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT               ; 1.445             ;
-; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|ledr[8]                ; 1.443             ;
-; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|ledr[8]                ; 1.443             ;
-; formula_fsm:FSM|count[5]               ; formula_fsm:FSM|ledr[8]                ; 1.443             ;
-; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[8]                ; 1.443             ;
-; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|ledr[9]                ; 1.427             ;
-; delay:DEL0|count[7]                    ; delay:DEL0|state.IDLE                  ; 1.419             ;
-; delay:DEL0|count[4]                    ; delay:DEL0|state.IDLE                  ; 1.418             ;
-; delay:DEL0|count[11]                   ; delay:DEL0|state.IDLE                  ; 1.409             ;
-; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT               ; 1.404             ;
-; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT               ; 1.402             ;
-; delay:DEL0|count[9]                    ; delay:DEL0|state.IDLE                  ; 1.381             ;
-; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT               ; 1.365             ;
-; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT               ; 1.364             ;
-; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT               ; 1.361             ;
-; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT               ; 1.355             ;
-; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT               ; 1.349             ;
-; delay:DEL0|count[5]                    ; delay:DEL0|state.IDLE                  ; 1.346             ;
-; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT               ; 1.346             ;
-; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT               ; 1.343             ;
-; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE                  ; 1.332             ;
-; delay:DEL0|count[12]                   ; delay:DEL0|state.IDLE                  ; 1.332             ;
-; delay:DEL0|count[1]                    ; delay:DEL0|state.IDLE                  ; 1.332             ;
-; delay:DEL0|count[0]                    ; delay:DEL0|state.IDLE                  ; 1.332             ;
-; delay:DEL0|state.IDLE                  ; delay:DEL0|state.IDLE                  ; 1.332             ;
-; delay:DEL0|state.COUNTING              ; delay:DEL0|state.IDLE                  ; 1.332             ;
-; delay:DEL0|state.TIME_OUT              ; delay:DEL0|state.IDLE                  ; 1.332             ;
-; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT               ; 1.317             ;
-; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT               ; 1.306             ;
-; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT               ; 1.305             ;
-; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT               ; 1.278             ;
-; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT               ; 1.263             ;
-; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|ledr[0]                ; 1.241             ;
-; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|ledr[7]                ; 1.231             ;
-; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|ledr[3]                ; 1.161             ;
-; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|ledr[3]                ; 1.161             ;
-; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|ledr[6]                ; 1.161             ;
-; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|ledr[4]                ; 1.154             ;
-; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|ledr[1]                ; 1.150             ;
-; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[2]                    ; 1.098             ;
-; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|count[2]               ; 1.077             ;
-; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                    ; 1.044             ;
-; LFSR:LFSR0|COUNT[2]                    ; LFSR:LFSR0|COUNT[3]                    ; 0.755             ;
-; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                    ; 0.755             ;
-; LFSR:LFSR0|COUNT[4]                    ; LFSR:LFSR0|COUNT[5]                    ; 0.755             ;
-; LFSR:LFSR0|COUNT[5]                    ; LFSR:LFSR0|COUNT[6]                    ; 0.755             ;
-; counter_16:COUNT0|state                ; counter_16:COUNT0|state                ; 0.736             ;
-; LFSR:LFSR0|COUNT[6]                    ; LFSR:LFSR0|COUNT[7]                    ; 0.602             ;
-; tick_50000:TICK0|CLK_OUT               ; counter_16:COUNT0|state                ; 0.577             ;
-; counter_16:COUNT0|count[7]             ; counter_16:COUNT0|count[15]            ; 0.354             ;
-; counter_16:COUNT0|count[12]            ; counter_16:COUNT0|count[15]            ; 0.343             ;
-; counter_16:COUNT0|count[1]             ; counter_16:COUNT0|count[15]            ; 0.343             ;
-; counter_16:COUNT0|count[0]             ; counter_16:COUNT0|count[15]            ; 0.342             ;
-; counter_16:COUNT0|count[8]             ; counter_16:COUNT0|count[15]            ; 0.341             ;
-; counter_16:COUNT0|count[5]             ; counter_16:COUNT0|count[15]            ; 0.341             ;
-; counter_16:COUNT0|count[13]            ; counter_16:COUNT0|count[15]            ; 0.337             ;
-; counter_16:COUNT0|count[6]             ; counter_16:COUNT0|count[15]            ; 0.332             ;
-; counter_16:COUNT0|count[9]             ; counter_16:COUNT0|count[15]            ; 0.331             ;
-; counter_16:COUNT0|count[3]             ; counter_16:COUNT0|count[15]            ; 0.328             ;
-; KEY[0]                                 ; counter_16:COUNT0|state                ; 0.308             ;
-; KEY[3]                                 ; formula_fsm:FSM|state.WAIT_TRIGGER     ; 0.226             ;
-; counter_16:COUNT0|count[11]            ; counter_16:COUNT0|count[15]            ; 0.160             ;
-; counter_16:COUNT0|count[14]            ; counter_16:COUNT0|count[15]            ; 0.151             ;
-; counter_16:COUNT0|count[10]            ; counter_16:COUNT0|count[15]            ; 0.147             ;
-; counter_16:COUNT0|count[4]             ; counter_16:COUNT0|count[15]            ; 0.147             ;
-; counter_16:COUNT0|count[2]             ; counter_16:COUNT0|count[15]            ; 0.137             ;
-+----------------------------------------+----------------------------------------+-------------------+
-Note: This table only shows the top 83 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (184020): Starting Fitter periphery placement operations
-Info (11191): Automatically promoted 1 clock (1 global)
-    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
-Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
-Info (176233): Starting register packing
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176235): Finished register packing
-    Extra Info (176219): No registers were packed into other blocks
-Warning (15705): Ignored locations or region assignments to the following nodes
-    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:13
-Info (170189): Fitter placement preparation operations beginning
-Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X33_Y0 to location X44_Y10
-Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
-Info (11888): Total time spent on timing analysis during the Fitter is 0.54 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
-Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 31 warnings
-    Info: Peak virtual memory: 2145 megabytes
-    Info: Processing ended: Sun Dec 11 20:30:52 2016
-    Info: Elapsed time: 00:00:37
-    Info: Total CPU time (on all processors): 00:01:04
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.fit.smsg.
-
-
+Fitter report for ex9
+Wed Dec 07 12:08:07 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Routing Usage Summary
+ 24. I/O Rules Summary
+ 25. I/O Rules Details
+ 26. I/O Rules Matrix
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing Summary
+ 30. Estimated Delay Added for Hold Timing Details
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Wed Dec 07 12:08:07 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex9                                             ;
+; Top-level Entity Name           ; ex9                                             ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 95                                              ;
+; Total pins                      ; 57 / 457 ( 12 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.02        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.8%      ;
+;     Processor 3            ;   0.8%      ;
+;     Processor 4            ;   0.8%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; HEX0[0]  ; Missing drive strength and slew rate ;
+; HEX0[1]  ; Missing drive strength and slew rate ;
+; HEX0[2]  ; Missing drive strength and slew rate ;
+; HEX0[3]  ; Missing drive strength and slew rate ;
+; HEX0[4]  ; Missing drive strength and slew rate ;
+; HEX0[5]  ; Missing drive strength and slew rate ;
+; HEX0[6]  ; Missing drive strength and slew rate ;
+; HEX1[0]  ; Missing drive strength and slew rate ;
+; HEX1[1]  ; Missing drive strength and slew rate ;
+; HEX1[2]  ; Missing drive strength and slew rate ;
+; HEX1[3]  ; Missing drive strength and slew rate ;
+; HEX1[4]  ; Missing drive strength and slew rate ;
+; HEX1[5]  ; Missing drive strength and slew rate ;
+; HEX1[6]  ; Missing drive strength and slew rate ;
+; HEX2[0]  ; Missing drive strength and slew rate ;
+; HEX2[1]  ; Missing drive strength and slew rate ;
+; HEX2[2]  ; Missing drive strength and slew rate ;
+; HEX2[3]  ; Missing drive strength and slew rate ;
+; HEX2[4]  ; Missing drive strength and slew rate ;
+; HEX2[5]  ; Missing drive strength and slew rate ;
+; HEX2[6]  ; Missing drive strength and slew rate ;
+; HEX3[0]  ; Missing drive strength and slew rate ;
+; HEX3[1]  ; Missing drive strength and slew rate ;
+; HEX3[2]  ; Missing drive strength and slew rate ;
+; HEX3[3]  ; Missing drive strength and slew rate ;
+; HEX3[4]  ; Missing drive strength and slew rate ;
+; HEX3[5]  ; Missing drive strength and slew rate ;
+; HEX3[6]  ; Missing drive strength and slew rate ;
+; HEX4[0]  ; Missing drive strength and slew rate ;
+; HEX4[1]  ; Missing drive strength and slew rate ;
+; HEX4[2]  ; Missing drive strength and slew rate ;
+; HEX4[3]  ; Missing drive strength and slew rate ;
+; HEX4[4]  ; Missing drive strength and slew rate ;
+; HEX4[5]  ; Missing drive strength and slew rate ;
+; HEX4[6]  ; Missing drive strength and slew rate ;
+; HEX5[0]  ; Missing drive strength and slew rate ;
+; HEX5[1]  ; Missing drive strength and slew rate ;
+; HEX5[2]  ; Missing drive strength and slew rate ;
+; HEX5[3]  ; Missing drive strength and slew rate ;
+; HEX5[4]  ; Missing drive strength and slew rate ;
+; HEX5[5]  ; Missing drive strength and slew rate ;
+; HEX5[6]  ; Missing drive strength and slew rate ;
+; LEDR[0]  ; Missing drive strength and slew rate ;
+; LEDR[1]  ; Missing drive strength and slew rate ;
+; LEDR[2]  ; Missing drive strength and slew rate ;
+; LEDR[3]  ; Missing drive strength and slew rate ;
+; LEDR[4]  ; Missing drive strength and slew rate ;
+; LEDR[5]  ; Missing drive strength and slew rate ;
+; LEDR[6]  ; Missing drive strength and slew rate ;
+; LEDR[7]  ; Missing drive strength and slew rate ;
+; LEDR[8]  ; Missing drive strength and slew rate ;
+; LEDR[9]  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                            ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;
+; formula_fsm:FSM|count[6]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[6]~DUPLICATE   ;                  ;                       ;
+; tick_50000:TICK0|count[0]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[0]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[2]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;
+; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[11]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[14]~DUPLICATE ;                  ;                       ;
+; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;
++----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                        ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
+; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
+; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
+; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
+; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
+; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
+; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
+; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
+; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
+; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
+; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex9            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 489 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32,070       ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 159                ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32,070       ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 36                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 120                ;       ;
+;         [c] ALMs used for registers                         ; 6                  ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32,070         ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 19 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 19                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 290                ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 41                 ;       ;
+;     -- 5 input functions                                    ; 5                  ;       ;
+;     -- 4 input functions                                    ; 157                ;       ;
+;     -- <=3 input functions                                  ; 87                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;
+; Dedicated logic registers                                   ; 95                 ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 84 / 64,140        ; < 1 % ;
+;         -- Secondary logic registers                        ; 11 / 64,140        ; < 1 % ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 84                 ;       ;
+;         -- Routing optimization registers                   ; 11                 ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 57 / 457           ; 12 %  ;
+;     -- Clock pins                                           ; 4 / 8              ; 50 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
+; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 2.7% / 3.0% / 1.9% ;       ;
+; Maximum fan-out                                             ; 68                 ;       ;
+; Highest non-global fan-out                                  ; 68                 ;       ;
+; Total fan-out                                               ; 1448               ;       ;
+; Average fan-out                                             ; 2.89               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                          ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 159                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 36                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 120                   ; 0                              ;
+;         [c] ALMs used for registers                         ; 6                     ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Difficulty packing design                                   ; Low                   ; Low                            ;
+;                                                             ;                       ;                                ;
+; Total LABs:  partially or completely used                   ; 19 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 19                    ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Combinational ALUT usage for logic                          ; 290                   ; 0                              ;
+;     -- 7 input functions                                    ; 0                     ; 0                              ;
+;     -- 6 input functions                                    ; 41                    ; 0                              ;
+;     -- 5 input functions                                    ; 5                     ; 0                              ;
+;     -- 4 input functions                                    ; 157                   ; 0                              ;
+;     -- <=3 input functions                                  ; 87                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;
+; Memory ALUT usage                                           ; 0                     ; 0                              ;
+;     -- 64-address deep                                      ; 0                     ; 0                              ;
+;     -- 32-address deep                                      ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Dedicated logic registers                                   ; 0                     ; 0                              ;
+;     -- By type:                                             ;                       ;                                ;
+;         -- Primary logic registers                          ; 84 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 11 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                       ;                                ;
+;         -- Design implementation registers                  ; 84                    ; 0                              ;
+;         -- Routing optimization registers                   ; 11                    ; 0                              ;
+;                                                             ;                       ;                                ;
+;                                                             ;                       ;                                ;
+; Virtual pins                                                ; 0                     ; 0                              ;
+; I/O pins                                                    ; 57                    ; 0                              ;
+; I/O registers                                               ; 0                     ; 0                              ;
+; Total block memory bits                                     ; 0                     ; 0                              ;
+; Total block memory implementation bits                      ; 0                     ; 0                              ;
+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
+;                                                             ;                       ;                                ;
+; Connections                                                 ;                       ;                                ;
+;     -- Input Connections                                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections                         ; 0                     ; 0                              ;
+;     -- Output Connections                                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections                        ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Internal Connections                                        ;                       ;                                ;
+;     -- Total Connections                                    ; 1448                  ; 0                              ;
+;     -- Registered Connections                               ; 438                   ; 0                              ;
+;                                                             ;                       ;                                ;
+; External Connections                                        ;                       ;                                ;
+;     -- Top                                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Partition Interface                                         ;                       ;                                ;
+;     -- Input Ports                                          ; 5                     ; 0                              ;
+;     -- Output Ports                                         ; 52                    ; 0                              ;
+;     -- Bidir Ports                                          ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Registered Ports                                            ;                       ;                                ;
+;     -- Registered Input Ports                               ; 0                     ; 0                              ;
+;     -- Registered Output Ports                              ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Port Connectivity                                           ;                       ;                                ;
+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 27                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[0] ; V25   ; 5B       ; 89           ; 20           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[1] ; AA28  ; 5B       ; 89           ; 21           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[2] ; Y27   ; 5B       ; 89           ; 25           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[3] ; AB27  ; 5B       ; 89           ; 23           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[4] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[5] ; AA26  ; 5B       ; 89           ; 23           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX5[6] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------+
+; I/O Bank Usage                                                              ;
++----------+-------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+-------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
+; 3A       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 5 / 48 ( 10 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 7 / 80 ( 9 % )    ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 32 / 32 ( 100 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 13 / 16 ( 81 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
++----------+-------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA25     ; 224        ; 5A             ; HEX5[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA26     ; 252        ; 5B             ; HEX5[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; HEX5[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB26     ; 226        ; 5A             ; HEX5[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB27     ; 254        ; 5B             ; HEX5[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; HEX5[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; HEX5[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex9                       ; 158.5 (0.5)          ; 161.5 (0.5)                      ; 3.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 290 (1)             ; 95 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
+;    |LFSR:LFSR0|            ; 3.0 (3.0)            ; 3.3 (3.3)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
+;    |bin2bcd_16:BCD|        ; 67.7 (0.0)           ; 68.0 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 124 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
+;       |add3_ge5:A1|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
+;       |add3_ge5:A10|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
+;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
+;       |add3_ge5:A12|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
+;       |add3_ge5:A13|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
+;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
+;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
+;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
+;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
+;       |add3_ge5:A18|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
+;       |add3_ge5:A19|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
+;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
+;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
+;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
+;       |add3_ge5:A22|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
+;       |add3_ge5:A23|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
+;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
+;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
+;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
+;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
+;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
+;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
+;       |add3_ge5:A3|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
+;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
+;       |add3_ge5:A32|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
+;       |add3_ge5:A33|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
+;       |add3_ge5:A34|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
+;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
+;       |add3_ge5:A4|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
+;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
+;       |add3_ge5:A6|        ; 3.7 (3.7)            ; 4.0 (4.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
+;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
+;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
+;       |add3_ge5:A9|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
+;    |counter_16:COUNT0|     ; 8.5 (8.5)            ; 8.6 (8.6)                        ; 0.1 (0.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
+;    |delay:DEL0|            ; 14.3 (14.3)          ; 15.4 (15.4)                      ; 1.1 (1.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 25 (25)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
+;    |formula_fsm:FSM|       ; 24.5 (24.5)          ; 25.3 (25.3)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 43 (43)             ; 26 (26)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
+;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG4|      ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
+;    |tick_50000:TICK0|      ; 18.5 (18.5)          ; 18.9 (18.9)                      ; 0.4 (0.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 27 (27)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX5[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; KEY[0]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; KEY[3]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                ;
++-------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;
++-------------------------------------------------+-------------------+---------+
+; KEY[1]                                          ;                   ;         ;
+; KEY[2]                                          ;                   ;         ;
+; KEY[0]                                          ;                   ;         ;
+;      - counter_16:COUNT0|count~0                ; 1                 ; 0       ;
+; CLOCK_50                                        ;                   ;         ;
+;      - tick_50000:TICK0|CLK_OUT                 ; 1                 ; 0       ;
+; KEY[3]                                          ;                   ;         ;
+;      - formula_fsm:FSM|Selector3~0              ; 1                 ; 0       ;
+;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 1                 ; 0       ;
+;      - formula_fsm:FSM|Selector2~0              ; 1                 ; 0       ;
++-------------------------------------------------+-------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                            ; PIN_AF14           ; 2       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                            ; PIN_AF14           ; 26      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; counter_16:COUNT0|count~0           ; LABCELL_X60_Y4_N30 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; counter_16:COUNT0|state             ; FF_X59_Y4_N14      ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; delay:DEL0|count[5]~0               ; LABCELL_X62_Y4_N51 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; delay:DEL0|state.COUNTING           ; FF_X63_Y4_N56      ; 19      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X62_Y4_N56      ; 26      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;
+; formula_fsm:FSM|state.WAIT_TRIGGER  ; FF_X61_Y4_N2       ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; tick_50000:TICK0|CLK_OUT            ; FF_X60_Y4_N2       ; 68      ; Clock                      ; no     ; --                   ; --               ; --                        ;
++-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 26      ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 375 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 2 / 13,420 ( < 1 % )    ;
+; C2 interconnects                            ; 132 / 119,108 ( < 1 % ) ;
+; C4 interconnects                            ; 84 / 56,300 ( < 1 % )   ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 62 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 1 / 16 ( 6 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 147 / 84,580 ( < 1 % )  ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 25 / 12,676 ( < 1 % )   ;
+; R14/C12 interconnect drivers                ; 26 / 20,720 ( < 1 % )   ;
+; R3 interconnects                            ; 160 / 130,992 ( < 1 % ) ;
+; R6 interconnects                            ; 252 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                  ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 57        ; 0            ; 57        ; 0            ; 0            ; 57        ; 57        ; 0            ; 57        ; 57        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 57           ; 0         ; 57           ; 57           ; 0         ; 0         ; 57           ; 0         ; 0         ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX5[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                               ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;
++--------------------------------------------------------------+--------------------------+-------------------+
+; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 62.3              ;
+; CLOCK_50                                                     ; CLOCK_50                 ; 9.8               ;
+; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.7               ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 3.2               ;
+; tick_50000:TICK0|CLK_OUT,I/O                                 ; tick_50000:TICK0|CLK_OUT ; 1.6               ;
++--------------------------------------------------------------+--------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++--------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                    ;
++----------------------------------------+-------------------------------------+-------------------+
+; Source Register                        ; Destination Register                ; Delay Added in ns ;
++----------------------------------------+-------------------------------------+-------------------+
+; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[3]             ; 2.057             ;
+; formula_fsm:FSM|start_delay            ; delay:DEL0|state.IDLE               ; 1.568             ;
+; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT            ; 1.369             ;
+; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT            ; 1.341             ;
+; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;
+; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;
+; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT            ; 1.267             ;
+; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT            ; 1.232             ;
+; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT            ; 1.227             ;
+; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT            ; 1.224             ;
+; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT            ; 1.214             ;
+; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT            ; 1.207             ;
+; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT            ; 1.206             ;
+; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT            ; 1.192             ;
+; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT            ; 1.189             ;
+; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT            ; 1.170             ;
+; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT            ; 1.169             ;
+; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT            ; 1.155             ;
+; delay:DEL0|count[13]                   ; delay:DEL0|count[11]                ; 0.995             ;
+; formula_fsm:FSM|count[1]               ; formula_fsm:FSM|count[1]            ; 0.879             ;
+; formula_fsm:FSM|count[6]               ; formula_fsm:FSM|count[5]            ; 0.876             ;
+; formula_fsm:FSM|count[9]               ; formula_fsm:FSM|count[5]            ; 0.866             ;
+; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[3]             ; 0.865             ;
+; delay:DEL0|state.IDLE                  ; delay:DEL0|state.COUNTING           ; 0.863             ;
+; formula_fsm:FSM|count[0]               ; formula_fsm:FSM|count[1]            ; 0.855             ;
+; formula_fsm:FSM|count[7]               ; formula_fsm:FSM|count[5]            ; 0.852             ;
+; delay:DEL0|count[0]                    ; delay:DEL0|count[11]                ; 0.851             ;
+; delay:DEL0|count[3]                    ; delay:DEL0|count[11]                ; 0.848             ;
+; delay:DEL0|count[9]                    ; delay:DEL0|count[11]                ; 0.836             ;
+; delay:DEL0|count[8]                    ; delay:DEL0|count[11]                ; 0.833             ;
+; delay:DEL0|count[1]                    ; delay:DEL0|count[11]                ; 0.830             ;
+; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; KEY[3]                                 ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; delay:DEL0|state.TIME_OUT              ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
+; delay:DEL0|count[6]                    ; delay:DEL0|count[11]                ; 0.820             ;
+; delay:DEL0|state.COUNTING              ; delay:DEL0|state.IDLE               ; 0.805             ;
+; formula_fsm:FSM|count[4]               ; formula_fsm:FSM|count[1]            ; 0.801             ;
+; delay:DEL0|count[7]                    ; delay:DEL0|count[11]                ; 0.800             ;
+; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE               ; 0.784             ;
+; delay:DEL0|count[4]                    ; delay:DEL0|count[11]                ; 0.779             ;
+; formula_fsm:FSM|count[8]               ; formula_fsm:FSM|count[10]           ; 0.751             ;
+; delay:DEL0|count[10]                   ; delay:DEL0|count[11]                ; 0.743             ;
+; formula_fsm:FSM|count[2]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
+; formula_fsm:FSM|count[3]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
+; formula_fsm:FSM|count[5]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
+; formula_fsm:FSM|count[10]              ; formula_fsm:FSM|count[5]            ; 0.741             ;
+; formula_fsm:FSM|count[11]              ; formula_fsm:FSM|count[5]            ; 0.741             ;
+; delay:DEL0|count[11]                   ; delay:DEL0|count[11]                ; 0.720             ;
+; delay:DEL0|count[12]                   ; delay:DEL0|count[11]                ; 0.714             ;
+; delay:DEL0|count[5]                    ; delay:DEL0|count[11]                ; 0.714             ;
+; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;
+; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;
+; delay:DEL0|count[2]                    ; delay:DEL0|count[11]                ; 0.673             ;
+; LFSR:LFSR0|COUNT[5]                    ; LFSR:LFSR0|COUNT[6]                 ; 0.631             ;
+; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                 ; 0.626             ;
+; LFSR:LFSR0|COUNT[4]                    ; LFSR:LFSR0|COUNT[5]                 ; 0.613             ;
+; LFSR:LFSR0|COUNT[6]                    ; LFSR:LFSR0|COUNT[7]                 ; 0.613             ;
+; LFSR:LFSR0|COUNT[2]                    ; delay:DEL0|count[8]                 ; 0.610             ;
+; counter_16:COUNT0|count[7]             ; counter_16:COUNT0|count[15]         ; 0.249             ;
+; counter_16:COUNT0|count[1]             ; counter_16:COUNT0|count[15]         ; 0.239             ;
+; counter_16:COUNT0|count[12]            ; counter_16:COUNT0|count[15]         ; 0.238             ;
+; counter_16:COUNT0|count[0]             ; counter_16:COUNT0|count[15]         ; 0.237             ;
+; counter_16:COUNT0|count[8]             ; counter_16:COUNT0|count[15]         ; 0.236             ;
+; counter_16:COUNT0|count[5]             ; counter_16:COUNT0|count[15]         ; 0.236             ;
+; counter_16:COUNT0|count[3]             ; counter_16:COUNT0|count[15]         ; 0.232             ;
+; counter_16:COUNT0|count[13]            ; counter_16:COUNT0|count[15]         ; 0.231             ;
+; counter_16:COUNT0|count[6]             ; counter_16:COUNT0|count[15]         ; 0.228             ;
+; counter_16:COUNT0|count[9]             ; counter_16:COUNT0|count[15]         ; 0.227             ;
+; counter_16:COUNT0|state                ; counter_16:COUNT0|state             ; 0.140             ;
+; KEY[0]                                 ; counter_16:COUNT0|state             ; 0.089             ;
+; counter_16:COUNT0|count[11]            ; counter_16:COUNT0|count[15]         ; 0.053             ;
+; counter_16:COUNT0|count[14]            ; counter_16:COUNT0|count[15]         ; 0.047             ;
+; counter_16:COUNT0|count[2]             ; counter_16:COUNT0|count[15]         ; 0.046             ;
+; counter_16:COUNT0|count[10]            ; counter_16:COUNT0|count[15]         ; 0.043             ;
+; counter_16:COUNT0|count[4]             ; counter_16:COUNT0|count[15]         ; 0.043             ;
+; tick_50000:TICK0|CLK_OUT               ; counter_16:COUNT0|state             ; 0.036             ;
++----------------------------------------+-------------------------------------+-------------------+
+Note: This table only shows the top 86 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:12
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
+Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 30 warnings
+    Info: Peak virtual memory: 2593 megabytes
+    Info: Processing ended: Wed Dec 07 12:08:09 2016
+    Info: Elapsed time: 00:00:37
+    Info: Total CPU time (on all processors): 00:01:02
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.fit.smsg.
+
+
diff --git a/part_2/ex9/output_files/ex9.fit.smsg b/part_2/ex9/output_files/ex9.fit.smsg
index 9302919..43eead5 100644..100755
--- a/part_2/ex9/output_files/ex9.fit.smsg
+++ b/part_2/ex9/output_files/ex9.fit.smsg
@@ -1,6 +1,6 @@
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
-Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex9/output_files/ex9.fit.summary b/part_2/ex9/output_files/ex9.fit.summary
index 47aeb86..496001c 100644..100755
--- a/part_2/ex9/output_files/ex9.fit.summary
+++ b/part_2/ex9/output_files/ex9.fit.summary
@@ -1,20 +1,20 @@
-Fitter Status : Successful - Sun Dec 11 20:30:51 2016
-Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
-Family : Cyclone V
-Device : 5CSEMA5F31C6
-Timing Models : Final
-Logic utilization (in ALMs) : 154 / 32,070 ( < 1 % )
-Total registers : 94
-Total pins : 57 / 457 ( 12 % )
-Total virtual pins : 0
-Total block memory bits : 0 / 4,065,280 ( 0 % )
-Total RAM Blocks : 0 / 397 ( 0 % )
-Total DSP Blocks : 0 / 87 ( 0 % )
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0 / 6 ( 0 % )
-Total DLLs : 0 / 4 ( 0 % )
+Fitter Status : Successful - Wed Dec 07 12:08:07 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex9
+Top-level Entity Name : ex9
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 159 / 32,070 ( < 1 % )
+Total registers : 95
+Total pins : 57 / 457 ( 12 % )
+Total virtual pins : 0
+Total block memory bits : 0 / 4,065,280 ( 0 % )
+Total RAM Blocks : 0 / 397 ( 0 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_2/ex9/output_files/ex9.flow.rpt b/part_2/ex9/output_files/ex9.flow.rpt
index f289207..1f2bee6 100644..100755
--- a/part_2/ex9/output_files/ex9.flow.rpt
+++ b/part_2/ex9/output_files/ex9.flow.rpt
@@ -1,128 +1,128 @@
-Flow report for ex9
-Sun Dec 11 20:31:05 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-  8. Flow Messages
-  9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Flow Summary                                                                  ;
-+---------------------------------+---------------------------------------------+
-; Flow Status                     ; Successful - Sun Dec 11 20:30:59 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex9                                         ;
-; Top-level Entity Name           ; ex9                                         ;
-; Family                          ; Cyclone V                                   ;
-; Device                          ; 5CSEMA5F31C6                                ;
-; Timing Models                   ; Final                                       ;
-; Logic utilization (in ALMs)     ; 154 / 32,070 ( < 1 % )                      ;
-; Total registers                 ; 94                                          ;
-; Total pins                      ; 57 / 457 ( 12 % )                           ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                       ;
-; Total DSP Blocks                ; 0 / 87 ( 0 % )                              ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0 / 6 ( 0 % )                               ;
-; Total DLLs                      ; 0 / 4 ( 0 % )                               ;
-+---------------------------------+---------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 12/11/2016 20:30:05 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; ex9                 ;
-+-------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                        ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID               ; 158515234070422.148148820510331        ; --            ; --          ; --         ;
-; MAX_CORE_JUNCTION_TEMP              ; 85                                     ; --            ; --          ; --         ;
-; MIN_CORE_JUNCTION_TEMP              ; 0                                      ; --            ; --          ; --         ;
-; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; --          ; Top        ;
-; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                    ; --            ; --          ; --         ;
-; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW  ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --         ;
-+-------------------------------------+----------------------------------------+---------------+-------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                             ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 1024 MB             ; 00:00:24                           ;
-; Fitter                    ; 00:00:36     ; 1.0                     ; 2145 MB             ; 00:01:04                           ;
-; Assembler                 ; 00:00:06     ; 1.0                     ; 979 MB              ; 00:00:06                           ;
-; TimeQuest Timing Analyzer ; 00:00:05     ; 1.2                     ; 1216 MB             ; 00:00:06                           ;
-; Total                     ; 00:00:57     ; --                      ; --                  ; 00:01:40                           ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                         ;
-+---------------------------+------------------+------------+------------+----------------+
-; Module Name               ; Machine Hostname ; OS Name    ; OS Version ; Processor type ;
-+---------------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis      ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; Fitter                    ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; Assembler                 ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-; TimeQuest Timing Analyzer ; arch-desktop     ; Arch Linux ; Arch Linux ; x86_64         ;
-+---------------------------+------------------+------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_sta ex9 -c ex9
-
-
-
+Flow report for ex9
+Wed Dec 07 12:08:29 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Wed Dec 07 12:08:20 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex9                                             ;
+; Top-level Entity Name           ; ex9                                             ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 95                                              ;
+; Total pins                      ; 57 / 457 ( 12 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 12/07/2016 12:07:14 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex9                 ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564297098.148111243406576       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:12     ; 1.0                     ; 918 MB              ; 00:00:23                           ;
+; Fitter                    ; 00:00:35     ; 1.0                     ; 2593 MB             ; 00:01:01                           ;
+; Assembler                 ; 00:00:08     ; 1.0                     ; 895 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:08     ; 1.1                     ; 1213 MB             ; 00:00:06                           ;
+; Total                     ; 00:01:03     ; --                      ; --                  ; 00:01:36                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-017     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
+quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9
+quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+quartus_sta ex9 -c ex9
+
+
+
diff --git a/part_2/ex9/output_files/ex9.jdi b/part_2/ex9/output_files/ex9.jdi
index 6278af0..63b9c30 100644..100755
--- a/part_2/ex9/output_files/ex9.jdi
+++ b/part_2/ex9/output_files/ex9.jdi
@@ -1,8 +1,8 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="5235bbf031d88b76e07a"/>
-  </project>
-  <file_info>
-    <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="814875341ee80fb3b165"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_2/ex9/output_files/ex9.map.rpt b/part_2/ex9/output_files/ex9.map.rpt
index d47b4f5..c0ed2ee 100644..100755
--- a/part_2/ex9/output_files/ex9.map.rpt
+++ b/part_2/ex9/output_files/ex9.map.rpt
@@ -1,617 +1,615 @@
-Analysis & Synthesis report for ex9
-Sun Dec 11 20:30:15 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. State Machine - |ex9|delay:DEL0|state
-  9. State Machine - |ex9|formula_fsm:FSM|state
- 10. User-Specified and Inferred Latches
- 11. Registers Removed During Synthesis
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
- 16. Parameter Settings for User Entity Instance: formula_fsm:FSM
- 17. Parameter Settings for User Entity Instance: delay:DEL0
- 18. Parameter Settings for User Entity Instance: counter_16:COUNT0
- 19. Port Connectivity Checks: "hex_to_7seg:SEG5"
- 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
- 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
- 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
- 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
- 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
- 25. Port Connectivity Checks: "delay:DEL0"
- 26. Post-Synthesis Netlist Statistics for Top Partition
- 27. Elapsed Time Per Partition
- 28. Analysis & Synthesis Messages
- 29. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                  ;
-+---------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status     ; Successful - Sun Dec 11 20:30:15 2016       ;
-; Quartus Prime Version           ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Revision Name                   ; ex9                                         ;
-; Top-level Entity Name           ; ex9                                         ;
-; Family                          ; Cyclone V                                   ;
-; Logic utilization (in ALMs)     ; N/A                                         ;
-; Total registers                 ; 81                                          ;
-; Total pins                      ; 57                                          ;
-; Total virtual pins              ; 0                                           ;
-; Total block memory bits         ; 0                                           ;
-; Total DSP Blocks                ; 0                                           ;
-; Total HSSI RX PCSs              ; 0                                           ;
-; Total HSSI PMA RX Deserializers ; 0                                           ;
-; Total HSSI TX PCSs              ; 0                                           ;
-; Total HSSI PMA TX Serializers   ; 0                                           ;
-; Total PLLs                      ; 0                                           ;
-; Total DLLs                      ; 0                                           ;
-+---------------------------------+---------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                             ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                          ; Setting            ; Default Value      ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
-; Top-level entity name                                                           ; ex9                ; ex9                ;
-; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
-; Use smart compilation                                                           ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
-; Enable compact report table                                                     ; Off                ; Off                ;
-; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
-; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
-; Preserve fewer node names                                                       ; On                 ; On                 ;
-; OpenCore Plus hardware evaluation                                               ; Enable             ; Enable             ;
-; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                                        ; Auto               ; Auto               ;
-; Safe State Machine                                                              ; Off                ; Off                ;
-; Extract Verilog State Machines                                                  ; On                 ; On                 ;
-; Extract VHDL State Machines                                                     ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
-; Parallel Synthesis                                                              ; On                 ; On                 ;
-; DSP Block Balancing                                                             ; Auto               ; Auto               ;
-; NOT Gate Push-Back                                                              ; On                 ; On                 ;
-; Power-Up Don't Care                                                             ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
-; Remove Duplicate Registers                                                      ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
-; Optimization Technique                                                          ; Balanced           ; Balanced           ;
-; Carry Chain Length                                                              ; 70                 ; 70                 ;
-; Auto Carry Chains                                                               ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
-; Auto ROM Replacement                                                            ; On                 ; On                 ;
-; Auto RAM Replacement                                                            ; On                 ; On                 ;
-; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
-; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
-; Strict RAM Replacement                                                          ; Off                ; Off                ;
-; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
-; Auto Resource Sharing                                                           ; Off                ; Off                ;
-; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
-; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
-; Report Parameter Settings                                                       ; On                 ; On                 ;
-; Report Source Assignments                                                       ; On                 ; On                 ;
-; Report Connectivity Checks                                                      ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
-; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
-; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
-; HDL message level                                                               ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
-; Clock MUX Protection                                                            ; On                 ; On                 ;
-; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
-; Block Design Naming                                                             ; Auto               ; Auto               ;
-; SDC constraint protection                                                       ; Off                ; Off                ;
-; Synthesis Effort                                                                ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
-; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
-; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
-; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
-;     Processors 3-4         ;   0.0%      ;
-+----------------------------+-------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                              ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                                ; Library ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/tick_50000.v  ;         ;
-; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/LFSR.v        ;         ;
-; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/hex_to_7seg.v ;         ;
-; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v ;         ;
-; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v       ;         ;
-; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/counter_16.v  ;         ;
-; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v  ;         ;
-; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/add3_ge5.v    ;         ;
-; verilog_files/ex9.v              ; yes             ; User Verilog HDL File  ; /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v         ;         ;
-+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary                            ;
-+---------------------------------------------+--------------------------+
-; Resource                                    ; Usage                    ;
-+---------------------------------------------+--------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 160                      ;
-;                                             ;                          ;
-; Combinational ALUT usage for logic          ; 281                      ;
-;     -- 7 input functions                    ; 2                        ;
-;     -- 6 input functions                    ; 35                       ;
-;     -- 5 input functions                    ; 5                        ;
-;     -- 4 input functions                    ; 154                      ;
-;     -- <=3 input functions                  ; 85                       ;
-;                                             ;                          ;
-; Dedicated logic registers                   ; 81                       ;
-;                                             ;                          ;
-; I/O pins                                    ; 57                       ;
-;                                             ;                          ;
-; Total DSP Blocks                            ; 0                        ;
-;                                             ;                          ;
-; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;
-; Maximum fan-out                             ; 64                       ;
-; Total fan-out                               ; 1382                     ;
-; Average fan-out                             ; 2.90                     ;
-+---------------------------------------------+--------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                 ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9                       ; 281 (1)             ; 81 (0)                    ; 0                 ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
-;    |LFSR:LFSR0|            ; 3 (3)               ; 7 (7)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 123 (0)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A10|       ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A1|        ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 3 (3)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A32|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
-;       |add3_ge5:A33|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 1 (1)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 4 (4)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:COUNT0|     ; 17 (17)             ; 17 (17)                   ; 0                 ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
-;    |delay:DEL0|            ; 23 (23)             ; 18 (18)                   ; 0                 ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 37 (37)             ; 22 (22)                   ; 0                 ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 7 (7)               ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 13 (13)             ; 0 (0)                     ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
-;    |tick_50000:TICK0|      ; 36 (36)             ; 17 (17)                   ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------+
-; State Machine - |ex9|delay:DEL0|state                                          ;
-+----------------+----------------+----------------+----------------+------------+
-; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
-+----------------+----------------+----------------+----------------+------------+
-; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;
-; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;
-; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;
-; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;
-+----------------+----------------+----------------+----------------+------------+
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------------------+
-; State Machine - |ex9|formula_fsm:FSM|state                                                 ;
-+------------------------+--------------------+------------------------+---------------------+
-; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
-+------------------------+--------------------+------------------------+---------------------+
-; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;
-; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;
-; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;
-+------------------------+--------------------+------------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches                                                                               ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;
-; Number of user-specified and inferred latches = 1  ;                                     ;                        ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------+
-; Registers Removed During Synthesis                         ;
-+---------------------------------------+--------------------+
-; Register name                         ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; delay:DEL0|state~5                    ; Lost fanout        ;
-; delay:DEL0|state~6                    ; Lost fanout        ;
-; Total Number of Removed Registers = 2 ;                    ;
-+---------------------------------------+--------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 81    ;
-; Number of registers using Synchronous Clear  ; 16    ;
-; Number of registers using Synchronous Load   ; 15    ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 43    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+---------------------------------------------------+
-; Inverted Register Statistics                      ;
-+-----------------------------------------+---------+
-; Inverted Register                       ; Fan out ;
-+-----------------------------------------+---------+
-; formula_fsm:FSM|count[1]                ; 2       ;
-; formula_fsm:FSM|count[0]                ; 2       ;
-; formula_fsm:FSM|count[4]                ; 2       ;
-; formula_fsm:FSM|count[5]                ; 2       ;
-; formula_fsm:FSM|count[6]                ; 2       ;
-; formula_fsm:FSM|count[7]                ; 2       ;
-; formula_fsm:FSM|count[8]                ; 2       ;
-; tick_50000:TICK0|count[14]              ; 2       ;
-; tick_50000:TICK0|count[15]              ; 2       ;
-; tick_50000:TICK0|count[0]               ; 2       ;
-; tick_50000:TICK0|count[1]               ; 2       ;
-; tick_50000:TICK0|count[2]               ; 2       ;
-; tick_50000:TICK0|count[3]               ; 2       ;
-; tick_50000:TICK0|count[6]               ; 2       ;
-; tick_50000:TICK0|count[8]               ; 2       ;
-; tick_50000:TICK0|count[9]               ; 2       ;
-; LFSR:LFSR0|COUNT[1]                     ; 3       ;
-; Total number of inverted registers = 17 ;         ;
-+-----------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex9|counter_16:COUNT0|count[7] ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[1]        ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[13]       ;
-; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |ex9|formula_fsm:FSM|count[1]   ;
-; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex9|formula_fsm:FSM|Selector4  ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex9|delay:DEL0|Selector16      ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex9|delay:DEL0|Selector17      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
-+----------------+-------+--------------------------------------+
-; Parameter Name ; Value ; Type                                 ;
-+----------------+-------+--------------------------------------+
-; NBIT           ; 16    ; Signed Integer                       ;
-+----------------+-------+--------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
-+------------------+-------+-----------------------------------+
-; Parameter Name   ; Value ; Type                              ;
-+------------------+-------+-----------------------------------+
-; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;
-; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;
-; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;
-+------------------+-------+-----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------+
-; Parameter Settings for User Entity Instance: delay:DEL0 ;
-+----------------+-------+--------------------------------+
-; Parameter Name ; Value ; Type                           ;
-+----------------+-------+--------------------------------+
-; BIT_SZ         ; 14    ; Signed Integer                 ;
-; IDLE           ; 00    ; Unsigned Binary                ;
-; COUNTING       ; 01    ; Unsigned Binary                ;
-; TIME_OUT       ; 10    ; Unsigned Binary                ;
-; WAIT_LOW       ; 11    ; Unsigned Binary                ;
-+----------------+-------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;
-+----------------+-------+---------------------------------------+
-; Parameter Name ; Value ; Type                                  ;
-+----------------+-------+---------------------------------------+
-; BIT_SZ         ; 16    ; Signed Integer                        ;
-; COUNTING       ; 1     ; Unsigned Binary                       ;
-; IDLE           ; 0     ; Unsigned Binary                       ;
-+----------------+-------+---------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------+
-; Port Connectivity Checks: "hex_to_7seg:SEG5" ;
-+------+-------+----------+--------------------+
-; Port ; Type  ; Severity ; Details            ;
-+------+-------+----------+--------------------+
-; in   ; Input ; Info     ; Stuck at GND       ;
-+------+-------+----------+--------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; Port  ; Type   ; Severity ; Details                                                                             ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
-; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type  ; Severity ; Details                                                                                                                                     ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type                  ; Count                       ;
-+-----------------------+-----------------------------+
-; arriav_ff             ; 81                          ;
-;     ENA               ; 13                          ;
-;     ENA SCLR          ; 16                          ;
-;     ENA SLD           ; 14                          ;
-;     SLD               ; 1                           ;
-;     plain             ; 37                          ;
-; arriav_lcell_comb     ; 299                         ;
-;     arith             ; 55                          ;
-;         1 data inputs ; 55                          ;
-;     extend            ; 2                           ;
-;         7 data inputs ; 2                           ;
-;     normal            ; 242                         ;
-;         0 data inputs ; 2                           ;
-;         1 data inputs ; 28                          ;
-;         2 data inputs ; 7                           ;
-;         3 data inputs ; 11                          ;
-;         4 data inputs ; 154                         ;
-;         5 data inputs ; 5                           ;
-;         6 data inputs ; 35                          ;
-; boundary_port         ; 57                          ;
-;                       ;                             ;
-; Max LUT depth         ; 15.00                       ;
-; Average LUT depth     ; 7.46                        ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:00     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 20:30:05 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
-    Info (12023): Found entity 1: tick_50000 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/tick_50000.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/LFSR.v
-    Info (12023): Found entity 1: LFSR File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/LFSR.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
-    Info (12023): Found entity 1: hex_to_7seg File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
-    Info (12023): Found entity 1: formula_fsm File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
-    Info (12023): Found entity 1: delay File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
-    Info (12023): Found entity 1: counter_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/counter_16.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
-    Info (12023): Found entity 1: bin2bcd_16 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
-    Info (12023): Found entity 1: add3_ge5 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/add3_ge5.v Line: 9
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v
-    Info (12023): Found entity 1: ex9 File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 1
-Info (12127): Elaborating entity "ex9" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 14
-Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 16
-Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 39
-Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 58
-Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 58
-Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 18
-Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 20
-Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v Line: 24
-Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 22
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 24
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 26
-Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
-    Warning (13410): Pin "HEX5[0]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[1]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[2]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[3]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[4]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[5]" is stuck at GND File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[6]" is stuck at VCC File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 6
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 2 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 2 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "KEY[1]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 4
-    Warning (15610): No output dependent on input pin "KEY[2]" File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/ex9.v Line: 4
-Info (21057): Implemented 345 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 5 input pins
-    Info (21059): Implemented 52 output pins
-    Info (21061): Implemented 288 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
-    Info: Peak virtual memory: 1067 megabytes
-    Info: Processing ended: Sun Dec 11 20:30:15 2016
-    Info: Elapsed time: 00:00:10
-    Info: Total CPU time (on all processors): 00:00:25
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/output_files/ex9.map.smsg.
-
-
+Analysis & Synthesis report for ex9
+Wed Dec 07 12:07:26 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. State Machine - |ex9|delay:DEL0|state
+  9. State Machine - |ex9|formula_fsm:FSM|state
+ 10. User-Specified and Inferred Latches
+ 11. Registers Removed During Synthesis
+ 12. General Register Statistics
+ 13. Inverted Register Statistics
+ 14. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
+ 16. Parameter Settings for User Entity Instance: formula_fsm:FSM
+ 17. Parameter Settings for User Entity Instance: delay:DEL0
+ 18. Parameter Settings for User Entity Instance: counter_16:COUNT0
+ 19. Port Connectivity Checks: "hex_to_7seg:SEG5"
+ 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
+ 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
+ 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
+ 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
+ 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
+ 25. Port Connectivity Checks: "delay:DEL0"
+ 26. Post-Synthesis Netlist Statistics for Top Partition
+ 27. Elapsed Time Per Partition
+ 28. Analysis & Synthesis Messages
+ 29. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Wed Dec 07 12:07:26 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex9                                             ;
+; Top-level Entity Name           ; ex9                                             ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 84                                              ;
+; Total pins                      ; 57                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0                                               ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex9                ; ex9                ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.0%      ;
+;     Processors 3-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                    ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                      ; Library ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
+; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v  ;         ;
+; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v        ;         ;
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v ;         ;
+; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v ;         ;
+; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v       ;         ;
+; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v  ;         ;
+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v  ;         ;
+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v    ;         ;
+; verilog_files/ex9.v              ; yes             ; User Verilog HDL File  ; H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v         ;         ;
++----------------------------------+-----------------+------------------------+-----------------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                            ;
++---------------------------------------------+--------------------------+
+; Resource                                    ; Usage                    ;
++---------------------------------------------+--------------------------+
+; Estimate of Logic utilization (ALMs needed) ; 166                      ;
+;                                             ;                          ;
+; Combinational ALUT usage for logic          ; 290                      ;
+;     -- 7 input functions                    ; 0                        ;
+;     -- 6 input functions                    ; 41                       ;
+;     -- 5 input functions                    ; 5                        ;
+;     -- 4 input functions                    ; 157                      ;
+;     -- <=3 input functions                  ; 87                       ;
+;                                             ;                          ;
+; Dedicated logic registers                   ; 84                       ;
+;                                             ;                          ;
+; I/O pins                                    ; 57                       ;
+;                                             ;                          ;
+; Total DSP Blocks                            ; 0                        ;
+;                                             ;                          ;
+; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;
+; Maximum fan-out                             ; 67                       ;
+; Total fan-out                               ; 1423                     ;
+; Average fan-out                             ; 2.92                     ;
++---------------------------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+; |ex9                       ; 290 (1)           ; 84 (0)       ; 0                 ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
+;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
+;    |bin2bcd_16:BCD|        ; 124 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
+;       |add3_ge5:A10|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
+;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
+;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
+;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
+;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
+;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
+;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
+;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
+;       |add3_ge5:A18|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
+;       |add3_ge5:A19|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
+;       |add3_ge5:A1|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
+;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
+;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
+;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
+;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
+;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
+;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
+;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
+;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
+;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
+;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
+;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
+;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
+;       |add3_ge5:A32|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
+;       |add3_ge5:A33|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
+;       |add3_ge5:A34|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
+;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
+;       |add3_ge5:A3|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
+;       |add3_ge5:A4|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
+;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
+;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
+;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
+;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
+;       |add3_ge5:A9|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
+;    |counter_16:COUNT0|     ; 17 (17)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
+;    |delay:DEL0|            ; 25 (25)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
+;    |formula_fsm:FSM|       ; 43 (43)           ; 25 (25)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG4|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
+;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |ex9|delay:DEL0|state                                          ;
++----------------+----------------+----------------+----------------+------------+
+; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
++----------------+----------------+----------------+----------------+------------+
+; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;
+; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;
+; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;
+; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;
++----------------+----------------+----------------+----------------+------------+
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------------------+
+; State Machine - |ex9|formula_fsm:FSM|state                                                 ;
++------------------------+--------------------+------------------------+---------------------+
+; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
++------------------------+--------------------+------------------------+---------------------+
+; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;
+; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;
+; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;
++------------------------+--------------------+------------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches                                                                               ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;
++----------------------------------------------------+-------------------------------------+------------------------+
+; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;
+; Number of user-specified and inferred latches = 1  ;                                     ;                        ;
++----------------------------------------------------+-------------------------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------------+
+; Registers Removed During Synthesis                         ;
++---------------------------------------+--------------------+
+; Register name                         ; Reason for Removal ;
++---------------------------------------+--------------------+
+; delay:DEL0|state~5                    ; Lost fanout        ;
+; delay:DEL0|state~6                    ; Lost fanout        ;
+; Total Number of Removed Registers = 2 ;                    ;
++---------------------------------------+--------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 84    ;
+; Number of registers using Synchronous Clear  ; 16    ;
+; Number of registers using Synchronous Load   ; 15    ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 42    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------+
+; Inverted Register Statistics                      ;
++-----------------------------------------+---------+
+; Inverted Register                       ; Fan out ;
++-----------------------------------------+---------+
+; formula_fsm:FSM|count[1]                ; 2       ;
+; formula_fsm:FSM|count[0]                ; 2       ;
+; formula_fsm:FSM|count[6]                ; 2       ;
+; formula_fsm:FSM|count[7]                ; 2       ;
+; formula_fsm:FSM|count[8]                ; 2       ;
+; formula_fsm:FSM|count[11]               ; 2       ;
+; tick_50000:TICK0|count[14]              ; 2       ;
+; tick_50000:TICK0|count[15]              ; 2       ;
+; tick_50000:TICK0|count[0]               ; 2       ;
+; tick_50000:TICK0|count[1]               ; 2       ;
+; tick_50000:TICK0|count[2]               ; 2       ;
+; tick_50000:TICK0|count[3]               ; 2       ;
+; tick_50000:TICK0|count[6]               ; 2       ;
+; tick_50000:TICK0|count[8]               ; 2       ;
+; tick_50000:TICK0|count[9]               ; 2       ;
+; LFSR:LFSR0|COUNT[1]                     ; 3       ;
+; Total number of inverted registers = 16 ;         ;
++-----------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex9|counter_16:COUNT0|count[0] ;
+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[5]        ;
+; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[13]       ;
+; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |ex9|formula_fsm:FSM|count[0]   ;
+; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex9|formula_fsm:FSM|Selector3  ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex9|delay:DEL0|Selector16      ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex9|delay:DEL0|Selector17      ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
+
+
++---------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
++----------------+-------+--------------------------------------+
+; Parameter Name ; Value ; Type                                 ;
++----------------+-------+--------------------------------------+
+; NBIT           ; 16    ; Signed Integer                       ;
++----------------+-------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
++------------------+-------+-----------------------------------+
+; Parameter Name   ; Value ; Type                              ;
++------------------+-------+-----------------------------------+
+; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;
+; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;
+; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;
++------------------+-------+-----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------+
+; Parameter Settings for User Entity Instance: delay:DEL0 ;
++----------------+-------+--------------------------------+
+; Parameter Name ; Value ; Type                           ;
++----------------+-------+--------------------------------+
+; BIT_SZ         ; 14    ; Signed Integer                 ;
+; IDLE           ; 00    ; Unsigned Binary                ;
+; COUNTING       ; 01    ; Unsigned Binary                ;
+; TIME_OUT       ; 10    ; Unsigned Binary                ;
+; WAIT_LOW       ; 11    ; Unsigned Binary                ;
++----------------+-------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;
++----------------+-------+---------------------------------------+
+; Parameter Name ; Value ; Type                                  ;
++----------------+-------+---------------------------------------+
+; BIT_SZ         ; 16    ; Signed Integer                        ;
+; COUNTING       ; 1     ; Unsigned Binary                       ;
+; IDLE           ; 0     ; Unsigned Binary                       ;
++----------------+-------+---------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------+
+; Port Connectivity Checks: "hex_to_7seg:SEG5" ;
++------+-------+----------+--------------------+
+; Port ; Type  ; Severity ; Details            ;
++------+-------+----------+--------------------+
+; in   ; Input ; Info     ; Stuck at GND       ;
++------+-------+----------+--------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; Port  ; Type   ; Severity ; Details                                                                             ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
+; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
++-------+-------+----------+------------------------------+
+; Port  ; Type  ; Severity ; Details                      ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                 ;
++-------+-------+----------+------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
++-------+-------+----------+------------------------------+
+; Port  ; Type  ; Severity ; Details                      ;
++-------+-------+----------+------------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                 ;
++-------+-------+----------+------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
++-------+-------+----------+-----------------------------+
+; Port  ; Type  ; Severity ; Details                     ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                ;
++-------+-------+----------+-----------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
++-------+-------+----------+-----------------------------+
+; Port  ; Type  ; Severity ; Details                     ;
++-------+-------+----------+-----------------------------+
+; iW[3] ; Input ; Info     ; Stuck at GND                ;
++-------+-------+----------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                                                                                                     ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;
++------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 84                          ;
+;     ENA               ; 12                          ;
+;     ENA SCLR          ; 16                          ;
+;     ENA SLD           ; 14                          ;
+;     SLD               ; 1                           ;
+;     plain             ; 41                          ;
+; arriav_lcell_comb     ; 308                         ;
+;     arith             ; 58                          ;
+;         1 data inputs ; 58                          ;
+;     normal            ; 250                         ;
+;         0 data inputs ; 2                           ;
+;         1 data inputs ; 28                          ;
+;         2 data inputs ; 8                           ;
+;         3 data inputs ; 9                           ;
+;         4 data inputs ; 157                         ;
+;         5 data inputs ; 5                           ;
+;         6 data inputs ; 41                          ;
+; boundary_port         ; 57                          ;
+;                       ;                             ;
+; Max LUT depth         ; 15.00                       ;
+; Average LUT depth     ; 7.32                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:07:13 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
+    Info (12023): Found entity 1: tick_50000 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/tick_50000.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
+    Info (12023): Found entity 1: LFSR File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/LFSR.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
+    Info (12023): Found entity 1: formula_fsm File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
+    Info (12023): Found entity 1: delay File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
+    Info (12023): Found entity 1: counter_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/counter_16.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v
+    Info (12023): Found entity 1: ex9 File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 1
+Info (12127): Elaborating entity "ex9" for the top level hierarchy
+Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 14
+Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 16
+Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 39
+Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 58
+Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 58
+Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 18
+Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 20
+Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 24
+Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 22
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 24
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 26
+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX5[0]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[1]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[2]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[3]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[4]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[5]" is stuck at GND File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+    Warning (13410): Pin "HEX5[6]" is stuck at VCC File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 6
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 2 registers lost all their fanouts during netlist optimizations.
+Info (144001): Generated suppressed messages file H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 2 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "KEY[1]" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 4
+    Warning (15610): No output dependent on input pin "KEY[2]" File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/ex9.v Line: 4
+Info (21057): Implemented 354 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 5 input pins
+    Info (21059): Implemented 52 output pins
+    Info (21061): Implemented 297 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
+    Info: Peak virtual memory: 918 megabytes
+    Info: Processing ended: Wed Dec 07 12:07:26 2016
+    Info: Elapsed time: 00:00:13
+    Info: Total CPU time (on all processors): 00:00:23
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in H:/GitHub/digital_verilog_coursework/part_2/ex9_final/output_files/ex9.map.smsg.
+
+
diff --git a/part_2/ex9/output_files/ex9.map.smsg b/part_2/ex9/output_files/ex9.map.smsg
index d9920c4..f6657db 100644..100755
--- a/part_2/ex9/output_files/ex9.map.smsg
+++ b/part_2/ex9/output_files/ex9.map.smsg
@@ -1,37 +1,37 @@
-Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/formula_fsm.v Line: 38
-Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/delay.v Line: 7
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: /home/yannherklotz/Github/digital_verilog_coursework/part_2/ex9/verilog_files/bin2bcd_16.v Line: 22
+Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/formula_fsm.v Line: 38
+Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/delay.v Line: 7
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: H:/GitHub/digital_verilog_coursework/part_2/ex9_final/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_2/ex9/output_files/ex9.map.summary b/part_2/ex9/output_files/ex9.map.summary
index 0cf8b66..e668523 100644..100755
--- a/part_2/ex9/output_files/ex9.map.summary
+++ b/part_2/ex9/output_files/ex9.map.summary
@@ -1,17 +1,17 @@
-Analysis & Synthesis Status : Successful - Sun Dec 11 20:30:15 2016
-Quartus Prime Version : 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
-Family : Cyclone V
-Logic utilization (in ALMs) : N/A
-Total registers : 81
-Total pins : 57
-Total virtual pins : 0
-Total block memory bits : 0
-Total DSP Blocks : 0
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0
-Total DLLs : 0
+Analysis & Synthesis Status : Successful - Wed Dec 07 12:07:26 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex9
+Top-level Entity Name : ex9
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 84
+Total pins : 57
+Total virtual pins : 0
+Total block memory bits : 0
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_2/ex9/output_files/ex9.pin b/part_2/ex9/output_files/ex9.pin
index 2ad3820..6b2c6db 100644..100755
--- a/part_2/ex9/output_files/ex9.pin
+++ b/part_2/ex9/output_files/ex9.pin
@@ -1,977 +1,976 @@
- -- Copyright (C) 2016  Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Intel Program License 
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel MegaCore Function License Agreement, or other 
- -- applicable license agreement, including, without limitation, 
- -- that your use is for the sole purpose of programming logic 
- -- devices manufactured by Intel and sold by Intel or its 
- -- authorized distributors.  Please refer to the applicable 
- -- agreement for further details.
- -- 
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --                  Bank 3A:       2.5V
- --                  Bank 3B:       3.3V
- --                  Bank 4A:       3.3V
- --                  Bank 5A:       3.3V
- --                  Bank 5B:       3.3V
- --                  Bank 6B:       2.5V
- --                  Bank 6A:  2.5V
- --                  Bank 7A:  2.5V
- --                  Bank 7B:  2.5V
- --                  Bank 7C:  2.5V
- --                  Bank 7D:  2.5V
- --                  Bank 8A:  2.5V
- --                  Bank 9A:  Dedicated configuration pins only, no VCCIO required.
- -- RREF          : External reference resistor for the quad, MUST be connected to
- --                 GND via a 2k Ohm resistor.
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --                  It can also be used to report unused dedicated pins. The connection
- --                  on the board for unused dedicated pins depends on whether this will
- --                  be used in a future design. One example is device migration. When
- --                  using device migration, refer to the device pin-tables. If it is a
- --                  GND pin in the pin table or if it will not be used in a future design
- --                  for another purpose the it MUST be connected to GND. If it is an unused
- --                  dedicated pin, then it can be connected to a valid signal on the board
- --                  (low, high, or toggling) if that signal is required for a different
- --                  revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --                  This pin should be connected to GND. It may also be connected  to a
- --                  valid signal  on the board  (low, high, or toggling)  if that signal
- --                  is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
- --                  or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
- --                 must not be connected.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-CHIP  "ex9"  ASSIGNED TO AN: 5CSEMA5F31C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A2        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
-VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
-GND                          : A12       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
-GND                          : A17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
-GND                          : A22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
-GND                          : A26       :        :                   :         : 7A        :                
-GND                          : A27       : gnd    :                   :         :           :                
-HPS_TRST                     : A28       :        :                   :         : 7A        :                
-HPS_TMS                      : A29       :        :                   :         : 7A        :                
-GND                          : AA1       : gnd    :                   :         :           :                
-GND                          : AA2       : gnd    :                   :         :           :                
-GND                          : AA3       : gnd    :                   :         :           :                
-GND                          : AA4       : gnd    :                   :         :           :                
-VCC                          : AA5       : power  :                   : 1.1V    :           :                
-GND                          : AA6       : gnd    :                   :         :           :                
-DNU                          : AA7       :        :                   :         :           :                
-VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
-GND                          : AA9       : gnd    :                   :         :           :                
-VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
-GND                          : AA11      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
-KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
-VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
-GND                          : AA22      : gnd    :                   :         :           :                
-VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[6]                      : AA25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[5]                      : AA26      : output : 3.3-V LVTTL       :         : 5B        : Y              
-VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
-HEX5[1]                      : AA28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
-GND                          : AB1       : gnd    :                   :         :           :                
-GND                          : AB2       : gnd    :                   :         :           :                
-DNU                          : AB3       :        :                   :         :           :                
-DNU                          : AB4       :        :                   :         :           :                
-GND                          : AB5       : gnd    :                   :         :           :                
-VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
-GND                          : AB7       : gnd    :                   :         :           :                
-nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
-TDO                          : AB9       : output :                   :         : 3A        :                
-VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
-VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
-VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
-VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
-GND                          : AB19      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
-HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
-HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[4]                      : AB26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[3]                      : AB27      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AB29      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
-GND                          : AC1       : gnd    :                   :         :           :                
-GND                          : AC2       : gnd    :                   :         :           :                
-GND                          : AC3       : gnd    :                   :         :           :                
-GND                          : AC4       : gnd    :                   :         :           :                
-TCK                          : AC5       : input  :                   :         : 3A        :                
-GND                          : AC6       : gnd    :                   :         :           :                
-AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
-GND                          : AC8       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
-VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
-VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
-VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
-VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
-GND                          : AC16      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
-VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
-VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
-VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
-HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AC26      : gnd    :                   :         :           :                
-HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AD1       : gnd    :                   :         :           :                
-GND                          : AD2       : gnd    :                   :         :           :                
-DNU                          : AD3       :        :                   :         :           :                
-DNU                          : AD4       :        :                   :         :           :                
-GND                          : AD5       : gnd    :                   :         :           :                
-VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
-VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
-VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
-DNU                          : AD15      :        :                   :         :           :                
-VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
-VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
-VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
-GND                          : AD23      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
-HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
-HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
-GND                          : AE1       : gnd    :                   :         :           :                
-GND                          : AE2       : gnd    :                   :         :           :                
-GND                          : AE3       : gnd    :                   :         :           :                
-GND                          : AE4       : gnd    :                   :         :           :                
-AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
-AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
-AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
-GND                          : AE10      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
-VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
-GND                          : AE20      : gnd    :                   :         :           :                
-VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
-VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
-HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
-VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
-GND                          : AF1       : gnd    :                   :         :           :                
-GND                          : AF2       : gnd    :                   :         :           :                
-GND                          : AF3       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
-VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
-GND                          : AF12      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
-CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
-GND                          : AF17      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
-VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
-GND                          : AF27      : gnd    :                   :         :           :                
-HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
-VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
-GND                          : AG9       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
-GND                          : AG14      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
-VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
-GND                          : AG24      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
-HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
-HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AH1       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
-GND                          : AH6       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
-GND                          : AH11      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
-VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
-GND                          : AH21      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
-VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
-HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
-GND                          : AJ3       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
-VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
-VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
-VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
-GND                          : AJ18      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
-VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
-GND                          : AJ28      : gnd    :                   :         :           :                
-HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : AJ30      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
-GND                          : AK5       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
-VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
-GND                          : AK15      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
-VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
-VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
-GND                          : AK25      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
-VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
-GND                          : B9        : gnd    :                   :         :           :                
-VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
-GND                          : B14       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
-GND                          : B19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
-GND                          : B24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
-HPS_TDI                      : B27       :        :                   :         : 7A        :                
-HPS_TDO                      : B28       :        :                   :         : 7A        :                
-GND                          : B29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
-GND                          : C1        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
-GND                          : C6        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
-VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
-GND                          : C16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
-GND                          : C21       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
-GND                          : C26       : gnd    :                   :         :           :                
-HPS_nRST                     : C27       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
-GND                          : D3        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
-VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
-GND                          : D13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
-VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
-GND                          : D23       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
-HPS_CLK1                     : D25       :        :                   :         : 7A        :                
-GND                          : D26       :        :                   :         : 7A        :                
-HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
-VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
-GND                          : E10       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
-VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
-VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
-VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
-GND                          : E25       : gnd    :                   :         :           :                
-DNU                          : E26       :        :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
-GND                          : E30       : gnd    :                   :         :           :                
-DNU                          : F1        :        :                   :         :           :                
-GND                          : F2        : gnd    :                   :         :           :                
-CONF_DONE                    : F3        :        :                   :         : 9A        :                
-nSTATUS                      : F4        :        :                   :         : 9A        :                
-GND                          : F5        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
-GND                          : F7        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
-VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
-GND                          : F17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
-VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
-HPS_nPOR                     : F23       :        :                   :         : 7A        :                
-HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
-HPS_CLK2                     : F25       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
-GND                          : F27       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
-GND                          : G1        :        :                   :         :           :                
-DNU                          : G2        :        :                   :         :           :                
-GND                          : G3        : gnd    :                   :         :           :                
-GND                          : G4        : gnd    :                   :         :           :                
-nCE                          : G5        :        :                   :         : 9A        :                
-MSEL2                        : G6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
-VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
-VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
-VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
-VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
-GND                          : G24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
-GND                          : H1        : gnd    :                   :         :           :                
-GND                          : H2        : gnd    :                   :         :           :                
-DNU                          : H3        :        :                   :         :           :                
-DNU                          : H4        :        :                   :         :           :                
-GND                          : H5        : gnd    :                   :         :           :                
-VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
-VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
-VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
-GND                          : H11       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
-VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
-VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
-HPS_TCK                      : H22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
-GND                          : J1        : gnd    :                   :         :           :                
-GND                          : J2        : gnd    :                   :         :           :                
-GND                          : J3        : gnd    :                   :         :           :                
-GND                          : J4        : gnd    :                   :         :           :                
-nCONFIG                      : J5        :        :                   :         : 9A        :                
-GND                          : J6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
-GND                          : J8        : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
-VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
-VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
-DNU                          : J15       :        :                   :         :           :                
-VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
-VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
-GND                          : J18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
-VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
-VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
-GND                          : J22       :        :                   :         : 7A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
-GND                          : J28       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
-GND                          : K1        : gnd    :                   :         :           :                
-GND                          : K2        : gnd    :                   :         :           :                
-DNU                          : K3        :        :                   :         :           :                
-DNU                          : K4        :        :                   :         :           :                
-GND                          : K5        : gnd    :                   :         :           :                
-MSEL1                        : K6        :        :                   :         : 9A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
-VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
-VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
-GND                          : K15       : gnd    :                   :         :           :                
-VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
-VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
-VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
-GND                          : K20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
-GND                          : K25       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
-GND                          : L1        : gnd    :                   :         :           :                
-GND                          : L2        : gnd    :                   :         :           :                
-GND                          : L3        : gnd    :                   :         :           :                
-GND                          : L4        : gnd    :                   :         :           :                
-VCC                          : L5        : power  :                   : 1.1V    :           :                
-GND                          : L6        : gnd    :                   :         :           :                
-MSEL3                        : L7        :        :                   :         : 9A        :                
-MSEL0                        : L8        :        :                   :         : 9A        :                
-MSEL4                        : L9        :        :                   :         : 9A        :                
-VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
-GND                          : L11       : gnd    :                   :         :           :                
-VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
-GND                          : L15       : gnd    :                   :         :           :                
-VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
-GND                          : L17       : gnd    :                   :         :           :                
-VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
-GND                          : L19       : gnd    :                   :         :           :                
-VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
-VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
-GND                          : L22       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
-GND                          : M1        : gnd    :                   :         :           :                
-GND                          : M2        : gnd    :                   :         :           :                
-DNU                          : M3        :        :                   :         :           :                
-DNU                          : M4        :        :                   :         :           :                
-GND                          : M5        : gnd    :                   :         :           :                
-VCC                          : M6        : power  :                   : 1.1V    :           :                
-GND                          : M7        : gnd    :                   :         :           :                
-GND                          : M8        : gnd    :                   :         :           :                
-VCC                          : M9        : power  :                   : 1.1V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-VCC                          : M11       : power  :                   : 1.1V    :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-VCC                          : M13       : power  :                   : 1.1V    :           :                
-GND                          : M14       : gnd    :                   :         :           :                
-VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
-GND                          : M16       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
-GND                          : M18       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
-GND                          : M20       : gnd    :                   :         :           :                
-VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
-VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
-GND                          : M29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
-GND                          : N1        : gnd    :                   :         :           :                
-GND                          : N2        : gnd    :                   :         :           :                
-GND                          : N3        : gnd    :                   :         :           :                
-GND                          : N4        : gnd    :                   :         :           :                
-VCC                          : N5        : power  :                   : 1.1V    :           :                
-GND                          : N6        : gnd    :                   :         :           :                
-VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
-GND                          : N8        : gnd    :                   :         :           :                
-GND                          : N9        : gnd    :                   :         :           :                
-VCC                          : N10       : power  :                   : 1.1V    :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-VCC                          : N12       : power  :                   : 1.1V    :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-VCC                          : N14       : power  :                   : 1.1V    :           :                
-GND                          : N15       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
-GND                          : N17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
-GND                          : N19       : gnd    :                   :         :           :                
-VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
-VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
-VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
-GND                          : N26       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
-GND                          : P1        : gnd    :                   :         :           :                
-GND                          : P2        : gnd    :                   :         :           :                
-DNU                          : P3        :        :                   :         :           :                
-DNU                          : P4        :        :                   :         :           :                
-GND                          : P5        : gnd    :                   :         :           :                
-VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
-GND                          : P7        : gnd    :                   :         :           :                
-GND                          : P8        : gnd    :                   :         :           :                
-GND                          : P9        : gnd    :                   :         :           :                
-GND                          : P10       : gnd    :                   :         :           :                
-VCC                          : P11       : power  :                   : 1.1V    :           :                
-GND                          : P12       : gnd    :                   :         :           :                
-VCC                          : P13       : power  :                   : 1.1V    :           :                
-GND                          : P14       : gnd    :                   :         :           :                
-VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
-GND                          : P16       : gnd    :                   :         :           :                
-VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
-GND                          : P18       : gnd    :                   :         :           :                
-VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
-GND                          : P20       : gnd    :                   :         :           :                
-VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
-GND                          : R1        : gnd    :                   :         :           :                
-GND                          : R2        : gnd    :                   :         :           :                
-GND                          : R3        : gnd    :                   :         :           :                
-GND                          : R4        : gnd    :                   :         :           :                
-VCC                          : R5        : power  :                   : 1.1V    :           :                
-GND                          : R6        : gnd    :                   :         :           :                
-VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
-GND                          : R8        : gnd    :                   :         :           :                
-GND                          : R9        : gnd    :                   :         :           :                
-VCC                          : R10       : power  :                   : 1.1V    :           :                
-GND                          : R11       : gnd    :                   :         :           :                
-VCC                          : R12       : power  :                   : 1.1V    :           :                
-GND                          : R13       : gnd    :                   :         :           :                
-VCC                          : R14       : power  :                   : 1.1V    :           :                
-GND                          : R15       : gnd    :                   :         :           :                
-VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
-GND                          : R17       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
-VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
-VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
-GND                          : R30       : gnd    :                   :         :           :                
-GND                          : T1        : gnd    :                   :         :           :                
-GND                          : T2        : gnd    :                   :         :           :                
-DNU                          : T3        :        :                   :         :           :                
-DNU                          : T4        :        :                   :         :           :                
-GND                          : T5        : gnd    :                   :         :           :                
-VCC                          : T6        : power  :                   : 1.1V    :           :                
-GND                          : T7        : gnd    :                   :         :           :                
-GND                          : T8        : gnd    :                   :         :           :                
-GND                          : T9        : gnd    :                   :         :           :                
-GND                          : T10       : gnd    :                   :         :           :                
-VCC                          : T11       : power  :                   : 1.1V    :           :                
-GND                          : T12       : gnd    :                   :         :           :                
-VCC                          : T13       : power  :                   : 1.1V    :           :                
-GND                          : T14       : gnd    :                   :         :           :                
-GND                          : T15       : gnd    :                   :         :           :                
-GND                          : T16       : gnd    :                   :         :           :                
-VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
-GND                          : T18       : gnd    :                   :         :           :                
-VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
-GND                          : T20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
-VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
-GND                          : T27       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
-GND                          : U1        : gnd    :                   :         :           :                
-GND                          : U2        : gnd    :                   :         :           :                
-GND                          : U3        : gnd    :                   :         :           :                
-GND                          : U4        : gnd    :                   :         :           :                
-VCC                          : U5        : power  :                   : 1.1V    :           :                
-GND                          : U6        : gnd    :                   :         :           :                
-DCLK                         : U7        :        :                   :         : 3A        :                
-TDI                          : U8        : input  :                   :         : 3A        :                
-GND                          : U9        : gnd    :                   :         :           :                
-VCC                          : U10       : power  :                   : 1.1V    :           :                
-GND                          : U11       : gnd    :                   :         :           :                
-VCC                          : U12       : power  :                   : 1.1V    :           :                
-GND                          : U13       : gnd    :                   :         :           :                
-VCC                          : U14       : power  :                   : 1.1V    :           :                
-GND                          : U15       : gnd    :                   :         :           :                
-VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
-GND                          : U17       : gnd    :                   :         :           :                
-VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
-VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
-VCC                          : U21       : power  :                   : 1.1V    :           :                
-GND                          : U22       : gnd    :                   :         :           :                
-VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
-GND                          : U24       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
-GND                          : U29       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
-GND                          : V1        : gnd    :                   :         :           :                
-GND                          : V2        : gnd    :                   :         :           :                
-DNU                          : V3        :        :                   :         :           :                
-DNU                          : V4        :        :                   :         :           :                
-GND                          : V5        : gnd    :                   :         :           :                
-VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
-GND                          : V7        : gnd    :                   :         :           :                
-VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
-TMS                          : V9        : input  :                   :         : 3A        :                
-GND                          : V10       : gnd    :                   :         :           :                
-VCC                          : V11       : power  :                   : 1.1V    :           :                
-GND                          : V12       : gnd    :                   :         :           :                
-VCC                          : V13       : power  :                   : 1.1V    :           :                
-GND                          : V14       : gnd    :                   :         :           :                
-VCC                          : V15       : power  :                   : 1.1V    :           :                
-LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : V19       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
-GND                          : V21       : gnd    :                   :         :           :                
-VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
-HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
-HEX5[0]                      : V25       : output : 3.3-V LVTTL       :         : 5B        : Y              
-VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
-GND                          : W1        : gnd    :                   :         :           :                
-GND                          : W2        : gnd    :                   :         :           :                
-GND                          : W3        : gnd    :                   :         :           :                
-GND                          : W4        : gnd    :                   :         :           :                
-VCC                          : W5        : power  :                   : 1.1V    :           :                
-GND                          : W6        : gnd    :                   :         :           :                
-GND                          : W7        : gnd    :                   :         :           :                
-GND                          : W8        : gnd    :                   :         :           :                
-GND                          : W9        : gnd    :                   :         :           :                
-VCC                          : W10       : power  :                   : 1.1V    :           :                
-GND                          : W11       : gnd    :                   :         :           :                
-VCC                          : W12       : power  :                   : 1.1V    :           :                
-GND                          : W13       : gnd    :                   :         :           :                
-VCC                          : W14       : power  :                   : 1.1V    :           :                
-KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              
-LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : W18       : gnd    :                   :         :           :                
-LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              
-LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
-HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
-GND                          : W28       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
-GND                          : Y1        : gnd    :                   :         :           :                
-GND                          : Y2        : gnd    :                   :         :           :                
-DNU                          : Y3        :        :                   :         :           :                
-DNU                          : Y4        :        :                   :         :           :                
-GND                          : Y5        : gnd    :                   :         :           :                
-VCC                          : Y6        : power  :                   : 1.1V    :           :                
-GND                          : Y7        : gnd    :                   :         :           :                
-GND                          : Y8        : gnd    :                   :         :           :                
-VCC                          : Y9        : power  :                   : 1.1V    :           :                
-GND                          : Y10       : gnd    :                   :         :           :                
-VCC                          : Y11       : power  :                   : 1.1V    :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-VCC                          : Y13       : power  :                   : 1.1V    :           :                
-GND                          : Y14       : gnd    :                   :         :           :                
-GND                          : Y15       : gnd    :                   :         :           :                
-KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
-LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              
-GND                          : Y20       : gnd    :                   :         :           :                
-LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              
-VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
-HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
-GND                          : Y25       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
-HEX5[2]                      : Y27       : output : 3.3-V LVTTL       :         : 5B        : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
-GND                          : Y30       : gnd    :                   :         :           :                
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       2.5V
+ --                  Bank 3B:       3.3V
+ --                  Bank 4A:       3.3V
+ --                  Bank 5A:       3.3V
+ --                  Bank 5B:       3.3V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex9"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX5[6]                      : AA25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX5[5]                      : AA26      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
+HEX5[1]                      : AA28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
+HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX5[4]                      : AB26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX5[3]                      : AB27      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
+VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AC26      : gnd    :                   :         :           :                
+HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
+HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
+HEX5[0]                      : V25       : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              
+LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : W18       : gnd    :                   :         :           :                
+LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              
+LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              
+LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
+HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              
+GND                          : Y20       : gnd    :                   :         :           :                
+LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+HEX5[2]                      : Y27       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_2/ex9/output_files/ex9.sld b/part_2/ex9/output_files/ex9.sld
index f7d3ed7..41a6030 100644..100755
--- a/part_2/ex9/output_files/ex9.sld
+++ b/part_2/ex9/output_files/ex9.sld
@@ -1 +1 @@
-<sld_project_info/>
+<sld_project_info/>
diff --git a/part_2/ex9/output_files/ex9.sof b/part_2/ex9/output_files/ex9.sof
index 227b29f..8d40e59 100644..100755
--- a/part_2/ex9/output_files/ex9.sof
+++ b/part_2/ex9/output_files/ex9.sof
diff --git a/part_2/ex9/output_files/ex9.sta.rpt b/part_2/ex9/output_files/ex9.sta.rpt
index 8331403..1c3b355 100644..100755
--- a/part_2/ex9/output_files/ex9.sta.rpt
+++ b/part_2/ex9/output_files/ex9.sta.rpt
@@ -1,1005 +1,1005 @@
-TimeQuest Timing Analyzer report for ex9
-Sun Dec 11 20:31:05 2016
-Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. TimeQuest Timing Analyzer Summary
-  3. Parallel Compilation
-  4. Clocks
-  5. Slow 1100mV 85C Model Fmax Summary
-  6. Timing Closure Recommendations
-  7. Slow 1100mV 85C Model Setup Summary
-  8. Slow 1100mV 85C Model Hold Summary
-  9. Slow 1100mV 85C Model Recovery Summary
- 10. Slow 1100mV 85C Model Removal Summary
- 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1100mV 85C Model Metastability Summary
- 13. Slow 1100mV 0C Model Fmax Summary
- 14. Slow 1100mV 0C Model Setup Summary
- 15. Slow 1100mV 0C Model Hold Summary
- 16. Slow 1100mV 0C Model Recovery Summary
- 17. Slow 1100mV 0C Model Removal Summary
- 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1100mV 0C Model Metastability Summary
- 20. Fast 1100mV 85C Model Setup Summary
- 21. Fast 1100mV 85C Model Hold Summary
- 22. Fast 1100mV 85C Model Recovery Summary
- 23. Fast 1100mV 85C Model Removal Summary
- 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
- 25. Fast 1100mV 85C Model Metastability Summary
- 26. Fast 1100mV 0C Model Setup Summary
- 27. Fast 1100mV 0C Model Hold Summary
- 28. Fast 1100mV 0C Model Recovery Summary
- 29. Fast 1100mV 0C Model Removal Summary
- 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
- 31. Fast 1100mV 0C Model Metastability Summary
- 32. Multicorner Timing Analysis Summary
- 33. Board Trace Model Assignments
- 34. Input Transition Times
- 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
- 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
- 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
- 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
- 39. Setup Transfers
- 40. Hold Transfers
- 41. Report TCCS
- 42. Report RSKM
- 43. Unconstrained Paths Summary
- 44. Clock Status Summary
- 45. Unconstrained Input Ports
- 46. Unconstrained Output Ports
- 47. Unconstrained Input Ports
- 48. Unconstrained Output Ports
- 49. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2016  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary                                           ;
-+-----------------------+-----------------------------------------------------+
-; Quartus Prime Version ; Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
-; Timing Analyzer       ; TimeQuest                                           ;
-; Revision Name         ; ex9                                                 ;
-; Device Family         ; Cyclone V                                           ;
-; Device Name           ; 5CSEMA5F31C6                                        ;
-; Timing Models         ; Final                                               ;
-; Delay Model           ; Combined                                            ;
-; Rise/Fall Delays      ; Enabled                                             ;
-+-----------------------+-----------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.19        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   6.2%      ;
-;     Processor 3            ;   6.2%      ;
-;     Processor 4            ;   6.1%      ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                                                                                   ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
-; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 85C Model Fmax Summary                             ;
-+------------+-----------------+--------------------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
-+------------+-----------------+--------------------------+------+
-; 202.72 MHz ; 202.72 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 312.7 MHz  ; 312.7 MHz       ; CLOCK_50                 ;      ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -3.933 ; -177.510      ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -2.353 ; -2.353        ;
-; CLOCK_50                            ; -2.198 ; -38.652       ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 85C Model Hold Summary                          ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.222 ; 0.000         ;
-; CLOCK_50                            ; 0.381 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1.023 ; 0.000         ;
-+-------------------------------------+-------+---------------+
-
-
-------------------------------------------
-; Slow 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.658 ; -17.489       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -41.338       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.439  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Slow 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary                              ;
-+------------+-----------------+--------------------------+------+
-; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
-+------------+-----------------+--------------------------+------+
-; 205.47 MHz ; 205.47 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 294.9 MHz  ; 294.9 MHz       ; CLOCK_50                 ;      ;
-+------------+-----------------+--------------------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -3.867 ; -173.770      ;
-; CLOCK_50                            ; -2.391 ; -39.269       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -2.208 ; -2.208        ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Slow 1100mV 0C Model Hold Summary                           ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.218 ; 0.000         ;
-; CLOCK_50                            ; 0.401 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.821 ; 0.000         ;
-+-------------------------------------+-------+---------------+
-
-
------------------------------------------
-; Slow 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.707 ; -16.083       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -42.153       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.422  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Slow 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -2.263 ; -94.992       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.029 ; -1.029        ;
-; CLOCK_50                            ; -1.002 ; -13.129       ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Fast 1100mV 85C Model Hold Summary                          ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.065 ; 0.000         ;
-; CLOCK_50                            ; 0.184 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.518 ; 0.000         ;
-+-------------------------------------+-------+---------------+
-
-
-------------------------------------------
-; Fast 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.771 ; -12.597       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.035 ; -1.610        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.481  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
------------------------------------------------
-; Fast 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -1.967 ; -82.047       ;
-; CLOCK_50                            ; -0.958 ; -11.100       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.846 ; -0.846        ;
-+-------------------------------------+--------+---------------+
-
-
-+-------------------------------------------------------------+
-; Fast 1100mV 0C Model Hold Summary                           ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.049 ; 0.000         ;
-; CLOCK_50                            ; 0.175 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.366 ; 0.000         ;
-+-------------------------------------+-------+---------------+
-
-
------------------------------------------
-; Fast 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.807 ; -14.887       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.016 ; -0.422        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.477  ; 0.000         ;
-+-------------------------------------+--------+---------------+
-
-
-----------------------------------------------
-; Fast 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+----------------------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                                                ;
-+--------------------------------------+----------+-------+----------+---------+---------------------+
-; Clock                                ; Setup    ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
-+--------------------------------------+----------+-------+----------+---------+---------------------+
-; Worst-case Slack                     ; -3.933   ; 0.049 ; N/A      ; N/A     ; -0.807              ;
-;  CLOCK_50                            ; -2.391   ; 0.175 ; N/A      ; N/A     ; -0.807              ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -2.353   ; 0.366 ; N/A      ; N/A     ; 0.422               ;
-;  tick_50000:TICK0|CLK_OUT            ; -3.933   ; 0.049 ; N/A      ; N/A     ; -0.394              ;
-; Design-wide TNS                      ; -218.515 ; 0.0   ; 0.0      ; 0.0     ; -58.827             ;
-;  CLOCK_50                            ; -39.269  ; 0.000 ; N/A      ; N/A     ; -17.489             ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -2.353   ; 0.000 ; N/A      ; N/A     ; 0.000               ;
-;  tick_50000:TICK0|CLK_OUT            ; -177.510 ; 0.000 ; N/A      ; N/A     ; -42.153             ;
-+--------------------------------------+----------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-+---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+-------------------------------------------------------------+
-; Input Transition Times                                      ;
-+----------+--------------+-----------------+-----------------+
-; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+----------+--------------+-----------------+-----------------+
-; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-+----------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-+---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Setup Transfers                                                                                                       ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 386      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 38       ; 21       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 955      ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Hold Transfers                                                                                                        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 386      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 38       ; 21       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 955      ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary                    ;
-+---------------------------------+-------+------+
-; Property                        ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks                  ; 0     ; 0    ;
-; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 2     ; 2    ;
-; Unconstrained Input Port Paths  ; 20    ; 20   ;
-; Unconstrained Output Ports      ; 45    ; 45   ;
-; Unconstrained Output Port Paths ; 500   ; 500  ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Clock Status Summary                                                                           ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; Target                              ; Clock                               ; Type ; Status      ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;
-+-------------------------------------+-------------------------------------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports                                                                         ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment                                                                              ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports                                                                          ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment                                                                               ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime TimeQuest Timing Analyzer
-    Info: Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-    Info: Processing started: Sun Dec 11 20:31:00 2016
-Info: Command: quartus_sta ex9 -c ex9
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
-    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
-    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
-    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1100mV 85C Model
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.933
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -3.933            -177.510 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -2.353              -2.353 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-    Info (332119):    -2.198             -38.652 CLOCK_50 
-Info (332146): Worst-case hold slack is 0.222
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.222               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.381               0.000 CLOCK_50 
-    Info (332119):     1.023               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.658
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.658             -17.489 CLOCK_50 
-    Info (332119):    -0.394             -41.338 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.439               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Slow 1100mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.867
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -3.867            -173.770 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -2.391             -39.269 CLOCK_50 
-    Info (332119):    -2.208              -2.208 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is 0.218
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.218               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.401               0.000 CLOCK_50 
-    Info (332119):     0.821               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.707
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.707             -16.083 CLOCK_50 
-    Info (332119):    -0.394             -42.153 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.422               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Fast 1100mV 85C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -2.263
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -2.263             -94.992 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -1.029              -1.029 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-    Info (332119):    -1.002             -13.129 CLOCK_50 
-Info (332146): Worst-case hold slack is 0.065
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.065               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.184               0.000 CLOCK_50 
-    Info (332119):     0.518               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.771
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.771             -12.597 CLOCK_50 
-    Info (332119):    -0.035              -1.610 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.481               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info: Analyzing Fast 1100mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
-    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.967
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -1.967             -82.047 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.958             -11.100 CLOCK_50 
-    Info (332119):    -0.846              -0.846 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is 0.049
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):     0.049               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.175               0.000 CLOCK_50 
-    Info (332119):     0.366               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.807
-    Info (332119):     Slack       End Point TNS Clock 
-    Info (332119): ========= =================== =====================
-    Info (332119):    -0.807             -14.887 CLOCK_50 
-    Info (332119):    -0.016              -0.422 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.477               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
-    Info: Peak virtual memory: 1216 megabytes
-    Info: Processing ended: Sun Dec 11 20:31:05 2016
-    Info: Elapsed time: 00:00:05
-    Info: Total CPU time (on all processors): 00:00:06
-
-
+TimeQuest Timing Analyzer report for ex9
+Wed Dec 07 12:08:30 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex9                                                     ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CSEMA5F31C6                                            ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.10        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   3.3%      ;
+;     Processor 3            ;   3.3%      ;
+;     Processor 4            ;   3.2%      ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                   ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
+; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;
++-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary                             ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 224.11 MHz ; 224.11 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
+; 328.19 MHz ; 328.19 MHz      ; CLOCK_50                 ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary                          ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -3.462 ; -161.413      ;
+; CLOCK_50                            ; -2.047 ; -40.775       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675 ; -1.675        ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary                          ;
++-------------------------------------+-------+---------------+
+; Clock                               ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; 0.179 ; 0.000         ;
+; CLOCK_50                            ; 0.385 ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.629 ; 0.000         ;
++-------------------------------------+-------+---------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.637 ; -18.132       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.762       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.459  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                              ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 226.45 MHz ; 226.45 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
+; 300.93 MHz ; 300.93 MHz      ; CLOCK_50                 ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary                           ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -3.416 ; -157.230      ;
+; CLOCK_50                            ; -2.323 ; -41.799       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.568 ; -1.568        ;
++-------------------------------------+--------+---------------+
+
+
++-------------------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary                           ;
++-------------------------------------+-------+---------------+
+; Clock                               ; Slack ; End Point TNS ;
++-------------------------------------+-------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; 0.193 ; 0.000         ;
+; CLOCK_50                            ; 0.405 ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.501 ; 0.000         ;
++-------------------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.689 ; -16.816       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.286       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.412  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary                          ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -1.794 ; -79.872       ;
+; CLOCK_50                            ; -0.918 ; -13.912       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.572 ; -0.572        ;
++-------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary                           ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -0.020 ; -0.037        ;
+; CLOCK_50                            ; 0.185  ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.202  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.740 ; -12.957       ;
+; tick_50000:TICK0|CLK_OUT            ; -0.012 ; -0.190        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.478  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary                           ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -1.581 ; -69.264       ;
+; CLOCK_50                            ; -0.868 ; -11.639       ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.462 ; -0.462        ;
++-------------------------------------+--------+---------------+
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary                            ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; tick_50000:TICK0|CLK_OUT            ; -0.021 ; -0.052        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.122  ; 0.000         ;
+; CLOCK_50                            ; 0.177  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;
++-------------------------------------+--------+---------------+
+; Clock                               ; Slack  ; End Point TNS ;
++-------------------------------------+--------+---------------+
+; CLOCK_50                            ; -0.789 ; -15.486       ;
+; tick_50000:TICK0|CLK_OUT            ; 0.024  ; 0.000         ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.468  ; 0.000         ;
++-------------------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-----------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                 ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+; Clock                                ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+; Worst-case Slack                     ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.789              ;
+;  CLOCK_50                            ; -2.323   ; 0.177  ; N/A      ; N/A     ; -0.789              ;
+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.122  ; N/A      ; N/A     ; 0.412               ;
+;  tick_50000:TICK0|CLK_OUT            ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.394              ;
+; Design-wide TNS                      ; -203.863 ; -0.052 ; 0.0      ; 0.0     ; -56.894             ;
+;  CLOCK_50                            ; -41.799  ; 0.000  ; N/A      ; N/A     ; -18.132             ;
+;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
+;  tick_50000:TICK0|CLK_OUT            ; -161.413 ; -0.052 ; N/A      ; N/A     ; -38.762             ;
++--------------------------------------+----------+--------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                       ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;
++-------------------------------------+-------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 2     ; 2    ;
+; Unconstrained Input Port Paths  ; 20    ; 20   ;
+; Unconstrained Output Ports      ; 45    ; 45   ;
+; Unconstrained Output Port Paths ; 500   ; 500  ;
++---------------------------------+-------+------+
+
+
++------------------------------------------------------------------------------------------------+
+; Clock Status Summary                                                                           ;
++-------------------------------------+-------------------------------------+------+-------------+
+; Target                              ; Clock                               ; Type ; Status      ;
++-------------------------------------+-------------------------------------+------+-------------+
+; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;
+; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
+; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;
++-------------------------------------+-------------------------------------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Wed Dec 07 12:08:21 2016
+Info: Command: quartus_sta ex9 -c ex9
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.462
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.462            -161.413 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -2.047             -40.775 CLOCK_50 
+    Info (332119):    -1.675              -1.675 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is 0.179
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.179               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.385               0.000 CLOCK_50 
+    Info (332119):     0.629               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.637
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.637             -18.132 CLOCK_50 
+    Info (332119):    -0.394             -38.762 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.459               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.416
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.416            -157.230 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -2.323             -41.799 CLOCK_50 
+    Info (332119):    -1.568              -1.568 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is 0.193
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.193               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.405               0.000 CLOCK_50 
+    Info (332119):     0.501               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.689
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.689             -16.816 CLOCK_50 
+    Info (332119):    -0.394             -38.286 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.412               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.794
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.794             -79.872 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -0.918             -13.912 CLOCK_50 
+    Info (332119):    -0.572              -0.572 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is -0.020
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.020              -0.037 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.185               0.000 CLOCK_50 
+    Info (332119):     0.202               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.740
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.740             -12.957 CLOCK_50 
+    Info (332119):    -0.012              -0.190 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.478               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.581
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.581             -69.264 tick_50000:TICK0|CLK_OUT 
+    Info (332119):    -0.868             -11.639 CLOCK_50 
+    Info (332119):    -0.462              -0.462 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332146): Worst-case hold slack is -0.021
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.021              -0.052 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.122               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):     0.177               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -0.789
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.789             -15.486 CLOCK_50 
+    Info (332119):     0.024               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.468               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
+    Info: Peak virtual memory: 1213 megabytes
+    Info: Processing ended: Wed Dec 07 12:08:30 2016
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_2/ex9/output_files/ex9.sta.summary b/part_2/ex9/output_files/ex9.sta.summary
index b1a6e61..87e925d 100644..100755
--- a/part_2/ex9/output_files/ex9.sta.summary
+++ b/part_2/ex9/output_files/ex9.sta.summary
@@ -1,149 +1,149 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.933
-TNS   : -177.510
-
-Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -2.353
-TNS   : -2.353
-
-Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -2.198
-TNS   : -38.652
-
-Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.222
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.381
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 1.023
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.658
-TNS   : -17.489
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -41.338
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.439
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.867
-TNS   : -173.770
-
-Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -2.391
-TNS   : -39.269
-
-Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -2.208
-TNS   : -2.208
-
-Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.218
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.401
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.821
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.707
-TNS   : -16.083
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -42.153
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.422
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -2.263
-TNS   : -94.992
-
-Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.029
-TNS   : -1.029
-
-Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -1.002
-TNS   : -13.129
-
-Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.065
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.184
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.518
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.771
-TNS   : -12.597
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.035
-TNS   : -1.610
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.481
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.967
-TNS   : -82.047
-
-Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -0.958
-TNS   : -11.100
-
-Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.846
-TNS   : -0.846
-
-Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.049
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.175
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.366
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.807
-TNS   : -14.887
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.016
-TNS   : -0.422
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.477
-TNS   : 0.000
-
-------------------------------------------------------------
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -3.462
+TNS   : -161.413
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -2.047
+TNS   : -40.775
+
+Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.675
+TNS   : -1.675
+
+Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.179
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.385
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.629
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.637
+TNS   : -18.132
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS   : -38.762
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.459
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -3.416
+TNS   : -157.230
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.323
+TNS   : -41.799
+
+Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -1.568
+TNS   : -1.568
+
+Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.193
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.405
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.501
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.689
+TNS   : -16.816
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.394
+TNS   : -38.286
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.412
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.794
+TNS   : -79.872
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -0.918
+TNS   : -13.912
+
+Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.572
+TNS   : -0.572
+
+Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.020
+TNS   : -0.037
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.185
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.202
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.740
+TNS   : -12.957
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.012
+TNS   : -0.190
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.478
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
+Slack : -1.581
+TNS   : -69.264
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -0.868
+TNS   : -11.639
+
+Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : -0.462
+TNS   : -0.462
+
+Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
+Slack : -0.021
+TNS   : -0.052
+
+Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.122
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.177
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -0.789
+TNS   : -15.486
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
+Slack : 0.024
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
+Slack : 0.468
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_2/ex9/verilog_files/LFSR.v b/part_2/ex9/verilog_files/LFSR.v
index 46140b2..46140b2 100644..100755
--- a/part_2/ex9/verilog_files/LFSR.v
+++ b/part_2/ex9/verilog_files/LFSR.v
diff --git a/part_2/ex9/verilog_files/LFSR.v.bak b/part_2/ex9/verilog_files/LFSR.v.bak
index 89ec82a..89ec82a 100644..100755
--- a/part_2/ex9/verilog_files/LFSR.v.bak
+++ b/part_2/ex9/verilog_files/LFSR.v.bak
diff --git a/part_2/ex9/verilog_files/add3_ge5.v b/part_2/ex9/verilog_files/add3_ge5.v
index a3cd6a9..a3cd6a9 100644..100755
--- a/part_2/ex9/verilog_files/add3_ge5.v
+++ b/part_2/ex9/verilog_files/add3_ge5.v
diff --git a/part_2/ex9/verilog_files/bin2bcd_16.v b/part_2/ex9/verilog_files/bin2bcd_16.v
index b25d0bd..b25d0bd 100644..100755
--- a/part_2/ex9/verilog_files/bin2bcd_16.v
+++ b/part_2/ex9/verilog_files/bin2bcd_16.v
diff --git a/part_2/ex9/verilog_files/counter_16.v b/part_2/ex9/verilog_files/counter_16.v
index 9c194bb..9c194bb 100644..100755
--- a/part_2/ex9/verilog_files/counter_16.v
+++ b/part_2/ex9/verilog_files/counter_16.v
diff --git a/part_2/ex9/verilog_files/counter_16.v.bak b/part_2/ex9/verilog_files/counter_16.v.bak
index c0ec549..c0ec549 100644..100755
--- a/part_2/ex9/verilog_files/counter_16.v.bak
+++ b/part_2/ex9/verilog_files/counter_16.v.bak
diff --git a/part_2/ex9/verilog_files/delay.v b/part_2/ex9/verilog_files/delay.v
index 63455d7..63455d7 100644..100755
--- a/part_2/ex9/verilog_files/delay.v
+++ b/part_2/ex9/verilog_files/delay.v
diff --git a/part_2/ex9/verilog_files/delay.v.bak b/part_2/ex9/verilog_files/delay.v.bak
index 7b79342..7b79342 100644..100755
--- a/part_2/ex9/verilog_files/delay.v.bak
+++ b/part_2/ex9/verilog_files/delay.v.bak
diff --git a/part_2/ex9/verilog_files/ex8.v b/part_2/ex9/verilog_files/ex8.v
deleted file mode 100644
index 6ca51d6..0000000
--- a/part_2/ex9/verilog_files/ex8.v
+++ /dev/null
@@ -1,23 +0,0 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
-	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9/verilog_files/ex8.v.bak b/part_2/ex9/verilog_files/ex8.v.bak
deleted file mode 100644
index ac293e7..0000000
--- a/part_2/ex9/verilog_files/ex8.v.bak
+++ /dev/null
@@ -1 +0,0 @@
-module ex8(
-\ No newline at end of file
diff --git a/part_2/ex9/verilog_files/ex9.v b/part_2/ex9/verilog_files/ex9.v
index 15446c2..15446c2 100644..100755
--- a/part_2/ex9/verilog_files/ex9.v
+++ b/part_2/ex9/verilog_files/ex9.v
diff --git a/part_2/ex9/verilog_files/ex9.v.bak b/part_2/ex9/verilog_files/ex9.v.bak
index 6ca51d6..6ca51d6 100644..100755
--- a/part_2/ex9/verilog_files/ex9.v.bak
+++ b/part_2/ex9/verilog_files/ex9.v.bak
diff --git a/part_2/ex9/verilog_files/formula_fsm.v b/part_2/ex9/verilog_files/formula_fsm.v
index 67ad1ee..5e4a40b 100644..100755
--- a/part_2/ex9/verilog_files/formula_fsm.v
+++ b/part_2/ex9/verilog_files/formula_fsm.v
@@ -1,39 +1,39 @@
 module formula_fsm(clk, trigger, time_out, en_lfsr, start_delay, ledr);
 
-	input clk, time_out, trigger;
-	output en_lfsr, start_delay;
-	output [9:0] ledr;
+input clk, time_out, trigger;
+output en_lfsr, start_delay;
+output [9:0] ledr;
 
-	reg [1:0] state;
-	reg led_on, en_lfsr, start_delay;
-	reg [9:0] ledr;
-	reg [8:0] count;
+reg [1:0] state;
+reg led_on, en_lfsr, start_delay;
+reg [9:0] ledr;
+reg [8:0] count;
 
-	parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
+parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
 
-	initial 
-		begin
-			state = WAIT_TRIGGER;
-			en_lfsr = 1'b0;
-			start_delay = 1'b0;
-			count = 9'd499;
-		end
+initial
+	begin
+		state = WAIT_TRIGGER;
+		en_lfsr = 1'b0;
+		start_delay = 1'b0;
+		count = 9'd499;
+	end
 
-	always @ (posedge clk)
-		case(state)
-			WAIT_TRIGGER: 
-				begin
-					if(trigger == 1'b1)
-						state <= LIGHT_UP_LEDS;
-				end
-			LIGHT_UP_LEDS:
-					if(ledr == 10'h3ff)
-						state <= WAIT_FOR_TIMEOUT;
-			WAIT_FOR_TIMEOUT:
-					if(time_out == 1'b1)
-						 state <= WAIT_TRIGGER;
-			default: ;
-		endcase
+always @ (posedge clk)
+	case(state)
+		WAIT_TRIGGER:
+			begin
+				if(trigger == 1'b1)
+					state <= LIGHT_UP_LEDS;
+			end
+		LIGHT_UP_LEDS:
+				if(ledr == 10'h3ff)
+					state <= WAIT_FOR_TIMEOUT;
+		WAIT_FOR_TIMEOUT:
+				if(time_out == 1'b1)
+					 state <= WAIT_TRIGGER;
+		default: ;
+	endcase
 
 always @ (posedge clk)
 	case(state)
@@ -41,7 +41,7 @@ always @ (posedge clk)
 			ledr = 0;
 		LIGHT_UP_LEDS:
 			begin
-				if(count == 9'b0)
+				if(count == 1'b0)
 					begin
 						ledr <= {ledr[8:0], 1'b1};
 						count <= 9'd499;
@@ -53,24 +53,24 @@ always @ (posedge clk)
 			end
 		default: count <= 9'd499;
 	endcase
-		
-	always @ (*)
-		case(state)
-			WAIT_TRIGGER:
-				begin
-					en_lfsr = 1'b0;
-					start_delay = 1'b0;
-				end
-			LIGHT_UP_LEDS:
-				begin
-					en_lfsr = 1'b1;
-				end
-			WAIT_FOR_TIMEOUT:
-				begin
-					start_delay = 1'b1;
-					en_lfsr = 1'b0;
-				end
-			default: ;
-		endcase
 
-endmodule
-\ No newline at end of file
+always @ (*)
+	case(state)
+		WAIT_TRIGGER:
+			begin
+				en_lfsr = 1'b0;
+				start_delay = 1'b0;
+			end
+		LIGHT_UP_LEDS:
+			begin
+				en_lfsr = 1'b1;
+			end
+		WAIT_FOR_TIMEOUT:
+			begin
+				start_delay = 1'b1;
+				en_lfsr = 1'b0;
+			end
+		default: ;
+	endcase
+
+endmodule
diff --git a/part_2/ex9/verilog_files/formula_fsm.v.bak b/part_2/ex9/verilog_files/formula_fsm.v.bak
index e69de29..e69de29 100644..100755
--- a/part_2/ex9/verilog_files/formula_fsm.v.bak
+++ b/part_2/ex9/verilog_files/formula_fsm.v.bak
diff --git a/part_2/ex9/verilog_files/hex_to_7seg.v b/part_2/ex9/verilog_files/hex_to_7seg.v
index 82aa9a5..82aa9a5 100644..100755
--- a/part_2/ex9/verilog_files/hex_to_7seg.v
+++ b/part_2/ex9/verilog_files/hex_to_7seg.v
diff --git a/part_2/ex9/verilog_files/tick_2500.v b/part_2/ex9/verilog_files/tick_2500.v
index e75a131..e75a131 100644..100755
--- a/part_2/ex9/verilog_files/tick_2500.v
+++ b/part_2/ex9/verilog_files/tick_2500.v
diff --git a/part_2/ex9/verilog_files/tick_2500.v.bak b/part_2/ex9/verilog_files/tick_2500.v.bak
index e69de29..e69de29 100644..100755
--- a/part_2/ex9/verilog_files/tick_2500.v.bak
+++ b/part_2/ex9/verilog_files/tick_2500.v.bak
diff --git a/part_2/ex9/verilog_files/tick_50000.v b/part_2/ex9/verilog_files/tick_50000.v
index 7ccc81b..7ccc81b 100644..100755
--- a/part_2/ex9/verilog_files/tick_50000.v
+++ b/part_2/ex9/verilog_files/tick_50000.v
diff --git a/part_2/ex9/verilog_files/tick_50000.v.bak b/part_2/ex9/verilog_files/tick_50000.v.bak
index 45c4166..45c4166 100644..100755
--- a/part_2/ex9/verilog_files/tick_50000.v.bak
+++ b/part_2/ex9/verilog_files/tick_50000.v.bak
diff --git a/part_2/ex9_final/db/.cmp.kpt b/part_2/ex9_final/db/.cmp.kpt
deleted file mode 100755
index a67a742..0000000
--- a/part_2/ex9_final/db/.cmp.kpt
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(0).cnf.cdb b/part_2/ex9_final/db/ex9.(0).cnf.cdb
deleted file mode 100755
index 2a49e3b..0000000
--- a/part_2/ex9_final/db/ex9.(0).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(0).cnf.hdb b/part_2/ex9_final/db/ex9.(0).cnf.hdb
deleted file mode 100755
index f90ac91..0000000
--- a/part_2/ex9_final/db/ex9.(0).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(1).cnf.cdb b/part_2/ex9_final/db/ex9.(1).cnf.cdb
deleted file mode 100755
index 6fa5bfa..0000000
--- a/part_2/ex9_final/db/ex9.(1).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(1).cnf.hdb b/part_2/ex9_final/db/ex9.(1).cnf.hdb
deleted file mode 100755
index 829c3df..0000000
--- a/part_2/ex9_final/db/ex9.(1).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(2).cnf.cdb b/part_2/ex9_final/db/ex9.(2).cnf.cdb
deleted file mode 100755
index 43aabd2..0000000
--- a/part_2/ex9_final/db/ex9.(2).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(2).cnf.hdb b/part_2/ex9_final/db/ex9.(2).cnf.hdb
deleted file mode 100755
index a2fe649..0000000
--- a/part_2/ex9_final/db/ex9.(2).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(3).cnf.cdb b/part_2/ex9_final/db/ex9.(3).cnf.cdb
deleted file mode 100755
index dbd336f..0000000
--- a/part_2/ex9_final/db/ex9.(3).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(3).cnf.hdb b/part_2/ex9_final/db/ex9.(3).cnf.hdb
deleted file mode 100755
index ac9f5e9..0000000
--- a/part_2/ex9_final/db/ex9.(3).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(4).cnf.cdb b/part_2/ex9_final/db/ex9.(4).cnf.cdb
deleted file mode 100755
index 13f6ae2..0000000
--- a/part_2/ex9_final/db/ex9.(4).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(4).cnf.hdb b/part_2/ex9_final/db/ex9.(4).cnf.hdb
deleted file mode 100755
index b7d17a9..0000000
--- a/part_2/ex9_final/db/ex9.(4).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(5).cnf.cdb b/part_2/ex9_final/db/ex9.(5).cnf.cdb
deleted file mode 100755
index 53d103c..0000000
--- a/part_2/ex9_final/db/ex9.(5).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(5).cnf.hdb b/part_2/ex9_final/db/ex9.(5).cnf.hdb
deleted file mode 100755
index 01910af..0000000
--- a/part_2/ex9_final/db/ex9.(5).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(6).cnf.cdb b/part_2/ex9_final/db/ex9.(6).cnf.cdb
deleted file mode 100755
index 3c6c09e..0000000
--- a/part_2/ex9_final/db/ex9.(6).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(6).cnf.hdb b/part_2/ex9_final/db/ex9.(6).cnf.hdb
deleted file mode 100755
index 1c167a7..0000000
--- a/part_2/ex9_final/db/ex9.(6).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(7).cnf.cdb b/part_2/ex9_final/db/ex9.(7).cnf.cdb
deleted file mode 100755
index 604867e..0000000
--- a/part_2/ex9_final/db/ex9.(7).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(7).cnf.hdb b/part_2/ex9_final/db/ex9.(7).cnf.hdb
deleted file mode 100755
index da601fb..0000000
--- a/part_2/ex9_final/db/ex9.(7).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(8).cnf.cdb b/part_2/ex9_final/db/ex9.(8).cnf.cdb
deleted file mode 100755
index 97e595e..0000000
--- a/part_2/ex9_final/db/ex9.(8).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.(8).cnf.hdb b/part_2/ex9_final/db/ex9.(8).cnf.hdb
deleted file mode 100755
index 42ab8b5..0000000
--- a/part_2/ex9_final/db/ex9.(8).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.asm.rdb b/part_2/ex9_final/db/ex9.asm.rdb
deleted file mode 100755
index ece1ac9..0000000
--- a/part_2/ex9_final/db/ex9.asm.rdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.cmp.bpm b/part_2/ex9_final/db/ex9.cmp.bpm
deleted file mode 100755
index 3cb4242..0000000
--- a/part_2/ex9_final/db/ex9.cmp.bpm
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.cmp.cdb b/part_2/ex9_final/db/ex9.cmp.cdb
deleted file mode 100755
index 5e2cdbb..0000000
--- a/part_2/ex9_final/db/ex9.cmp.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.cmp.hdb b/part_2/ex9_final/db/ex9.cmp.hdb
deleted file mode 100755
index 3baae81..0000000
--- a/part_2/ex9_final/db/ex9.cmp.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.cmp.idb b/part_2/ex9_final/db/ex9.cmp.idb
deleted file mode 100755
index 5cbf640..0000000
--- a/part_2/ex9_final/db/ex9.cmp.idb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.cmp.rdb b/part_2/ex9_final/db/ex9.cmp.rdb
deleted file mode 100755
index 7298c0d..0000000
--- a/part_2/ex9_final/db/ex9.cmp.rdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.cmp_merge.kpt b/part_2/ex9_final/db/ex9.cmp_merge.kpt
deleted file mode 100755
index fdd3bfe..0000000
--- a/part_2/ex9_final/db/ex9.cmp_merge.kpt
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.fit.qmsg b/part_2/ex9_final/db/ex9.fit.qmsg
deleted file mode 100755
index c1dd335..0000000
--- a/part_2/ex9_final/db/ex9.fit.qmsg
+++ /dev/null
@@ -1,45 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480075828268 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480075828268 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480075828528 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480075828590 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480075828590 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480075828981 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480075829117 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480075839247 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480075839355 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480075839355 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075839355 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480075839359 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480075839359 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480075839360 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480075839361 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480075839361 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480075839361 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480075839990 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480075839991 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480075839991 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480075839995 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480075839995 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480075839996 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480075839999 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480075840000 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480075840000 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075840050 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480075840050 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075840051 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480075845081 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480075845350 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075846139 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480075847006 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480075847947 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075847947 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480075849115 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex9/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480075853750 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480075853750 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480075855521 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480075855521 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075855525 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480075857019 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480075857059 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480075857529 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480075857530 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480075857977 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075860733 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480075860987 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.fit.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480075861050 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2592 " "Peak virtual memory: 2592 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075861521 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:11:01 2016 " "Processing ended: Fri Nov 25 12:11:01 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075861521 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075861521 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:01 " "Total CPU time (on all processors): 00:01:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075861521 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480075861521 ""}
diff --git a/part_2/ex9_final/db/ex9.hier_info b/part_2/ex9_final/db/ex9.hier_info
deleted file mode 100755
index 2ac051e..0000000
--- a/part_2/ex9_final/db/ex9.hier_info
+++ /dev/null
@@ -1,784 +0,0 @@
-|ex9
-CLOCK_50 => CLOCK_50.IN1
-KEY[0] => _.IN1
-KEY[1] => ~NO_FANOUT~
-KEY[2] => ~NO_FANOUT~
-KEY[3] => _.IN1
-HEX0[0] << hex_to_7seg:SEG0.port0
-HEX0[1] << hex_to_7seg:SEG0.port0
-HEX0[2] << hex_to_7seg:SEG0.port0
-HEX0[3] << hex_to_7seg:SEG0.port0
-HEX0[4] << hex_to_7seg:SEG0.port0
-HEX0[5] << hex_to_7seg:SEG0.port0
-HEX0[6] << hex_to_7seg:SEG0.port0
-HEX1[0] << hex_to_7seg:SEG1.port0
-HEX1[1] << hex_to_7seg:SEG1.port0
-HEX1[2] << hex_to_7seg:SEG1.port0
-HEX1[3] << hex_to_7seg:SEG1.port0
-HEX1[4] << hex_to_7seg:SEG1.port0
-HEX1[5] << hex_to_7seg:SEG1.port0
-HEX1[6] << hex_to_7seg:SEG1.port0
-HEX2[0] << hex_to_7seg:SEG2.port0
-HEX2[1] << hex_to_7seg:SEG2.port0
-HEX2[2] << hex_to_7seg:SEG2.port0
-HEX2[3] << hex_to_7seg:SEG2.port0
-HEX2[4] << hex_to_7seg:SEG2.port0
-HEX2[5] << hex_to_7seg:SEG2.port0
-HEX2[6] << hex_to_7seg:SEG2.port0
-HEX3[0] << hex_to_7seg:SEG3.port0
-HEX3[1] << hex_to_7seg:SEG3.port0
-HEX3[2] << hex_to_7seg:SEG3.port0
-HEX3[3] << hex_to_7seg:SEG3.port0
-HEX3[4] << hex_to_7seg:SEG3.port0
-HEX3[5] << hex_to_7seg:SEG3.port0
-HEX3[6] << hex_to_7seg:SEG3.port0
-HEX4[0] << hex_to_7seg:SEG4.port0
-HEX4[1] << hex_to_7seg:SEG4.port0
-HEX4[2] << hex_to_7seg:SEG4.port0
-HEX4[3] << hex_to_7seg:SEG4.port0
-HEX4[4] << hex_to_7seg:SEG4.port0
-HEX4[5] << hex_to_7seg:SEG4.port0
-HEX4[6] << hex_to_7seg:SEG4.port0
-HEX5[0] << hex_to_7seg:SEG5.port0
-HEX5[1] << hex_to_7seg:SEG5.port0
-HEX5[2] << hex_to_7seg:SEG5.port0
-HEX5[3] << hex_to_7seg:SEG5.port0
-HEX5[4] << hex_to_7seg:SEG5.port0
-HEX5[5] << hex_to_7seg:SEG5.port0
-HEX5[6] << hex_to_7seg:SEG5.port0
-LEDR[0] << formula_fsm:FSM.port5
-LEDR[1] << formula_fsm:FSM.port5
-LEDR[2] << formula_fsm:FSM.port5
-LEDR[3] << formula_fsm:FSM.port5
-LEDR[4] << formula_fsm:FSM.port5
-LEDR[5] << formula_fsm:FSM.port5
-LEDR[6] << formula_fsm:FSM.port5
-LEDR[7] << formula_fsm:FSM.port5
-LEDR[8] << formula_fsm:FSM.port5
-LEDR[9] << formula_fsm:FSM.port5
-
-
-|ex9|tick_50000:TICK0
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|formula_fsm:FSM
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => ledr[0]~reg0.CLK
-clk => ledr[1]~reg0.CLK
-clk => ledr[2]~reg0.CLK
-clk => ledr[3]~reg0.CLK
-clk => ledr[4]~reg0.CLK
-clk => ledr[5]~reg0.CLK
-clk => ledr[6]~reg0.CLK
-clk => ledr[7]~reg0.CLK
-clk => ledr[8]~reg0.CLK
-clk => ledr[9]~reg0.CLK
-clk => state~3.DATAIN
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
-start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
-ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|LFSR:LFSR0
-CLK => COUNT[1]~reg0.CLK
-CLK => COUNT[2]~reg0.CLK
-CLK => COUNT[3]~reg0.CLK
-CLK => COUNT[4]~reg0.CLK
-CLK => COUNT[5]~reg0.CLK
-CLK => COUNT[6]~reg0.CLK
-CLK => COUNT[7]~reg0.CLK
-en => COUNT[1]~reg0.ENA
-en => COUNT[2]~reg0.ENA
-en => COUNT[3]~reg0.ENA
-en => COUNT[4]~reg0.ENA
-en => COUNT[5]~reg0.ENA
-en => COUNT[6]~reg0.ENA
-en => COUNT[7]~reg0.ENA
-COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|delay:DEL0
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => count[12].CLK
-clk => count[13].CLK
-clk => state~4.DATAIN
-N[0] => count.DATAB
-N[1] => count.DATAB
-N[2] => count.DATAB
-N[3] => count.DATAB
-N[4] => count.DATAB
-N[5] => count.DATAB
-N[6] => count.DATAB
-N[7] => ~NO_FANOUT~
-N[8] => ~NO_FANOUT~
-N[9] => ~NO_FANOUT~
-N[10] => ~NO_FANOUT~
-N[11] => ~NO_FANOUT~
-N[12] => ~NO_FANOUT~
-N[13] => ~NO_FANOUT~
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector17.IN3
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector14.IN2
-time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|counter_16:COUNT0
-clock => count[0]~reg0.CLK
-clock => count[1]~reg0.CLK
-clock => count[2]~reg0.CLK
-clock => count[3]~reg0.CLK
-clock => count[4]~reg0.CLK
-clock => count[5]~reg0.CLK
-clock => count[6]~reg0.CLK
-clock => count[7]~reg0.CLK
-clock => count[8]~reg0.CLK
-clock => count[9]~reg0.CLK
-clock => count[10]~reg0.CLK
-clock => count[11]~reg0.CLK
-clock => count[12]~reg0.CLK
-clock => count[13]~reg0.CLK
-clock => count[14]~reg0.CLK
-clock => count[15]~reg0.CLK
-clock => state.CLK
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => state.OUTPUTSELECT
-stop => state.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD
-B[0] => BCD_0[0].DATAIN
-B[1] => w35[0].IN1
-B[2] => w30[0].IN1
-B[3] => w26[0].IN1
-B[4] => w22[0].IN1
-B[5] => w18[0].IN1
-B[6] => w15[0].IN1
-B[7] => w12[0].IN1
-B[8] => w9[0].IN1
-B[9] => w7[0].IN1
-B[10] => w5[0].IN1
-B[11] => w3[0].IN1
-B[12] => w2[0].IN1
-B[13] => w1[0].IN1
-B[14] => w1[1].IN1
-B[15] => w1[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A35.port1
-BCD_0[2] <= add3_ge5:A35.port1
-BCD_0[3] <= add3_ge5:A35.port1
-BCD_1[0] <= add3_ge5:A35.port1
-BCD_1[1] <= add3_ge5:A34.port1
-BCD_1[2] <= add3_ge5:A34.port1
-BCD_1[3] <= add3_ge5:A34.port1
-BCD_2[0] <= add3_ge5:A34.port1
-BCD_2[1] <= add3_ge5:A33.port1
-BCD_2[2] <= add3_ge5:A33.port1
-BCD_2[3] <= add3_ge5:A33.port1
-BCD_3[0] <= add3_ge5:A33.port1
-BCD_3[1] <= add3_ge5:A32.port1
-BCD_3[2] <= add3_ge5:A32.port1
-BCD_3[3] <= add3_ge5:A32.port1
-BCD_4[0] <= add3_ge5:A32.port1
-BCD_4[1] <= add3_ge5:A31.port1
-BCD_4[2] <= add3_ge5:A31.port1
-BCD_4[3] <= add3_ge5:A31.port1
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A1
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A2
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A3
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A4
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A5
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A6
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A7
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A8
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A9
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A10
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A11
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A12
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A13
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A14
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A15
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A16
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A17
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A18
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A19
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A20
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A21
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A22
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A23
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A24
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A25
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A26
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A27
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A28
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A29
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A30
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A31
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A32
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A33
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A34
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A35
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG3
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG4
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG5
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
diff --git a/part_2/ex9_final/db/ex9.hif b/part_2/ex9_final/db/ex9.hif
deleted file mode 100755
index 928d6f7..0000000
--- a/part_2/ex9_final/db/ex9.hif
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.lpc.rdb b/part_2/ex9_final/db/ex9.lpc.rdb
deleted file mode 100755
index 9db0391..0000000
--- a/part_2/ex9_final/db/ex9.lpc.rdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.lpc.txt b/part_2/ex9_final/db/ex9.lpc.txt
deleted file mode 100755
index 538b3bf..0000000
--- a/part_2/ex9_final/db/ex9.lpc.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG5      ; 4     ; 4              ; 0            ; 4              ; 7      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD       ; 16    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; COUNT0    ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; FSM       ; 3     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex9_final/db/ex9.map.bpm b/part_2/ex9_final/db/ex9.map.bpm
deleted file mode 100755
index 6ecfd55..0000000
--- a/part_2/ex9_final/db/ex9.map.bpm
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.map.cdb b/part_2/ex9_final/db/ex9.map.cdb
deleted file mode 100755
index 61f1857..0000000
--- a/part_2/ex9_final/db/ex9.map.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.map.hdb b/part_2/ex9_final/db/ex9.map.hdb
deleted file mode 100755
index de65f19..0000000
--- a/part_2/ex9_final/db/ex9.map.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.map.kpt b/part_2/ex9_final/db/ex9.map.kpt
deleted file mode 100755
index dc1f7e5..0000000
--- a/part_2/ex9_final/db/ex9.map.kpt
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.map.qmsg b/part_2/ex9_final/db/ex9.map.qmsg
deleted file mode 100755
index 9efa221..0000000
--- a/part_2/ex9_final/db/ex9.map.qmsg
+++ /dev/null
@@ -1,74 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480075816461 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075816463 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:10:16 2016 " "Processing started: Fri Nov 25 12:10:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075816463 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075816463 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075816464 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480075816957 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480075816958 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825232 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825232 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825233 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825233 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825234 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825234 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480075825237 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825238 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825238 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825239 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825239 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825239 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter_16.v(16) " "Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480075825241 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825241 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825241 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825242 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075825243 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825244 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825244 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825245 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825245 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075825246 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825246 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480075825275 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825276 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "C:/New folder/ex9/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825277 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480075825278 "|ex9|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480075825278 "|ex9|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075825278 "|ex9|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825285 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825286 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480075825286 "|ex9|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825287 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "C:/New folder/ex9/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825288 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825289 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075825294 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480075825850 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075826014 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480075826014 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480075826091 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480075826405 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075826430 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480075826519 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075826519 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480075826562 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480075826562 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480075826562 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "354 " "Implemented 354 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480075826563 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480075826563 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480075826563 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480075826563 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "898 " "Peak virtual memory: 898 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075826577 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:10:26 2016 " "Processing ended: Fri Nov 25 12:10:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075826577 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075826577 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075826577 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075826577 ""}
diff --git a/part_2/ex9_final/db/ex9.map.rdb b/part_2/ex9_final/db/ex9.map.rdb
deleted file mode 100755
index 7d9ef6e..0000000
--- a/part_2/ex9_final/db/ex9.map.rdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.map_bb.cdb b/part_2/ex9_final/db/ex9.map_bb.cdb
deleted file mode 100755
index a961dfd..0000000
--- a/part_2/ex9_final/db/ex9.map_bb.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.map_bb.hdb b/part_2/ex9_final/db/ex9.map_bb.hdb
deleted file mode 100755
index d42ddcf..0000000
--- a/part_2/ex9_final/db/ex9.map_bb.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.pre_map.hdb b/part_2/ex9_final/db/ex9.pre_map.hdb
deleted file mode 100755
index b01e48d..0000000
--- a/part_2/ex9_final/db/ex9.pre_map.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.root_partition.map.reg_db.cdb b/part_2/ex9_final/db/ex9.root_partition.map.reg_db.cdb
deleted file mode 100755
index c515539..0000000
--- a/part_2/ex9_final/db/ex9.root_partition.map.reg_db.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.routing.rdb b/part_2/ex9_final/db/ex9.routing.rdb
deleted file mode 100755
index e96d120..0000000
--- a/part_2/ex9_final/db/ex9.routing.rdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.rtlv.hdb b/part_2/ex9_final/db/ex9.rtlv.hdb
deleted file mode 100755
index 210b835..0000000
--- a/part_2/ex9_final/db/ex9.rtlv.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.rtlv_sg.cdb b/part_2/ex9_final/db/ex9.rtlv_sg.cdb
deleted file mode 100755
index bdf2cf1..0000000
--- a/part_2/ex9_final/db/ex9.rtlv_sg.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.rtlv_sg_swap.cdb b/part_2/ex9_final/db/ex9.rtlv_sg_swap.cdb
deleted file mode 100755
index b2375d1..0000000
--- a/part_2/ex9_final/db/ex9.rtlv_sg_swap.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.smp_dump.txt b/part_2/ex9_final/db/ex9.smp_dump.txt
deleted file mode 100755
index 26e74f6..0000000
--- a/part_2/ex9_final/db/ex9.smp_dump.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-
-State Machine - |ex9|delay:DEL0|state
-Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 
-state.IDLE 0 0 0 0 
-state.COUNTING 0 0 1 1 
-state.TIME_OUT 0 1 0 1 
-state.WAIT_LOW 1 0 0 1 
-
-State Machine - |ex9|formula_fsm:FSM|state
-Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 
-state.WAIT_TRIGGER 0 0 0 
-state.LIGHT_UP_LEDS 1 0 1 
-state.WAIT_FOR_TIMEOUT 1 1 0 
diff --git a/part_2/ex9_final/db/ex9.sta.qmsg b/part_2/ex9_final/db/ex9.sta.qmsg
deleted file mode 100755
index d471141..0000000
--- a/part_2/ex9_final/db/ex9.sta.qmsg
+++ /dev/null
@@ -1,53 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480075870370 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075870371 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:11:09 2016 " "Processing started: Fri Nov 25 12:11:09 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075870371 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075870371 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075870371 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075870501 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871062 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871062 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871118 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871118 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871628 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871651 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871651 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075871652 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075871652 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075871652 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871652 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871654 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871669 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075871670 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075871678 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075871702 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871702 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.462 " "Worst-case setup slack is -3.462" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT  " "   -3.462            -161.413 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.047             -40.775 CLOCK_50  " "   -2.047             -40.775 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.675              -1.675 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871704 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871704 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.179               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.179               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.385               0.000 CLOCK_50  " "    0.385               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.629               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871707 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871707 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871709 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871710 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.637 " "Worst-case minimum pulse width slack is -0.637" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.637             -18.132 CLOCK_50  " "   -0.637             -18.132 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.762 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.459               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075871712 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871712 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075871723 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075871759 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872664 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872745 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075872753 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872753 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.416 " "Worst-case setup slack is -3.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT  " "   -3.416            -157.230 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.323             -41.799 CLOCK_50  " "   -2.323             -41.799 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.568              -1.568 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872755 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872755 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.193               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.405               0.000 CLOCK_50  " "    0.405               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.501               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872759 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872759 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872761 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872762 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.689 " "Worst-case minimum pulse width slack is -0.689" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.689             -16.816 CLOCK_50  " "   -0.689             -16.816 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -38.286 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.412               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075872764 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872764 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075872775 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075872921 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873695 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873765 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075873769 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873769 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT  " "   -1.794             -79.872 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.918             -13.912 CLOCK_50  " "   -0.918             -13.912 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.572              -0.572 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873771 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873771 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.020 " "Worst-case hold slack is -0.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT  " "   -0.020              -0.037 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.185               0.000 CLOCK_50  " "    0.185               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.202               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873775 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873775 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873776 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873778 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.740 " "Worst-case minimum pulse width slack is -0.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.740             -12.957 CLOCK_50  " "   -0.740             -12.957 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT  " "   -0.012              -0.190 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.478               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873779 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873779 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075873791 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873956 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075873959 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873959 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.581 " "Worst-case setup slack is -1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT  " "   -1.581             -69.264 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.868             -11.639 CLOCK_50  " "   -0.868             -11.639 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.462              -0.462 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873960 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873960 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.021 " "Worst-case hold slack is -0.021" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT  " "   -0.021              -0.052 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.122               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873964 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873964 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873965 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873967 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.789 " "Worst-case minimum pulse width slack is -0.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.789             -15.486 CLOCK_50  " "   -0.789             -15.486 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.024               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.468               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075873968 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075873968 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075875504 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075875506 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1213 " "Peak virtual memory: 1213 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075875553 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:11:15 2016 " "Processing ended: Fri Nov 25 12:11:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075875553 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075875553 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075875553 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075875553 ""}
diff --git a/part_2/ex9_final/db/ex9.sta.rdb b/part_2/ex9_final/db/ex9.sta.rdb
deleted file mode 100755
index 4e60cb5..0000000
--- a/part_2/ex9_final/db/ex9.sta.rdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex9_final/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
deleted file mode 100755
index 6b64eb8..0000000
--- a/part_2/ex9_final/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_0c.ddb b/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_0c.ddb
deleted file mode 100755
index 8021c27..0000000
--- a/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_0c.ddb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_85c.ddb b/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_85c.ddb
deleted file mode 100755
index f050a53..0000000
--- a/part_2/ex9_final/db/ex9.tiscmp.fast_1100mv_85c.ddb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_0c.ddb b/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_0c.ddb
deleted file mode 100755
index 820cefc..0000000
--- a/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_0c.ddb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_85c.ddb b/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_85c.ddb
deleted file mode 100755
index 8f07a04..0000000
--- a/part_2/ex9_final/db/ex9.tiscmp.slow_1100mv_85c.ddb
+++ /dev/null
diff --git a/part_2/ex9_final/db/ex9.vpr.ammdb b/part_2/ex9_final/db/ex9.vpr.ammdb
deleted file mode 100755
index 51295de..0000000
--- a/part_2/ex9_final/db/ex9.vpr.ammdb
+++ /dev/null
diff --git a/part_2/ex9_final/db/prev_cmp_ex9.qmsg b/part_2/ex9_final/db/prev_cmp_ex9.qmsg
deleted file mode 100755
index ba5a172..0000000
--- a/part_2/ex9_final/db/prev_cmp_ex9.qmsg
+++ /dev/null
@@ -1,186 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480075580936 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075580938 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:06:20 2016 " "Processing started: Fri Nov 25 12:06:20 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075580938 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075580938 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075580938 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480075581376 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480075581377 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590051 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590051 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590053 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590053 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590054 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590054 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(38) " "Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480075590057 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590057 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590057 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590059 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590059 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590059 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter_16.v(16) " "Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480075590060 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590061 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590061 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590063 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590065 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590065 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480075590066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590066 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480075590096 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590103 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "C:/New folder/ex9/verilog_files/ex9.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590104 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(39) " "Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 39 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480075590105 "|ex9|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(58) " "Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480075590105 "|ex9|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(58) " "Inferred latch for \"start_delay\" at formula_fsm.v(58)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 58 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075590105 "|ex9|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590111 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590112 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480075590112 "|ex9|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 22 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590113 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "C:/New folder/ex9/verilog_files/ex9.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590113 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590115 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075590120 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480075590684 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480075590850 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480075590850 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480075590927 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480075591254 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075591280 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480075591369 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480075591369 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480075591413 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480075591413 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480075591413 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "350 " "Implemented 350 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480075591414 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480075591414 ""} { "Info" "ICUT_CUT_TM_LCELLS" "293 " "Implemented 293 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480075591414 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480075591414 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "897 " "Peak virtual memory: 897 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075591427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:06:31 2016 " "Processing ended: Fri Nov 25 12:06:31 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075591427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075591427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075591427 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480075591427 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1480075593013 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075593013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:06:32 2016 " "Processing started: Fri Nov 25 12:06:32 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075593013 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480075593013 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480075593014 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480075593132 ""}
-{ "Info" "0" "" "Project  = ex9" {  } {  } 0 0 "Project  = ex9" 0 0 "Fitter" 0 0 1480075593133 ""}
-{ "Info" "0" "" "Revision = ex9" {  } {  } 0 0 "Revision = ex9" 0 0 "Fitter" 0 0 1480075593133 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480075593245 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480075593245 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480075593510 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480075593600 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480075593600 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480075593986 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480075594120 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480075604181 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 16 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480075604289 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480075604289 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075604289 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480075604293 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480075604294 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480075604295 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480075604295 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480075604295 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480075604296 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480075604931 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480075604932 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480075604932 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480075604936 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480075604936 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480075604937 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480075604941 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480075604942 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480075604942 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480075604990 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480075604990 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075604991 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480075610020 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480075610281 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075611109 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480075611804 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480075612838 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075612839 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480075614028 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex9/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480075618515 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480075618515 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480075620193 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480075620193 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075620197 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.54 " "Total time spent on timing analysis during the Fitter is 0.54 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480075621681 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480075621719 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480075622162 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480075622162 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480075622601 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480075625362 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480075625612 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.fit.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480075625677 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2607 " "Peak virtual memory: 2607 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075626138 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:07:06 2016 " "Processing ended: Fri Nov 25 12:07:06 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075626138 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075626138 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:59 " "Total CPU time (on all processors): 00:00:59" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075626138 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480075626138 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480075627439 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075627441 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:07:07 2016 " "Processing started: Fri Nov 25 12:07:07 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075627441 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480075627441 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480075627442 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480075628223 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480075632816 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "894 " "Peak virtual memory: 894 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075633154 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:07:13 2016 " "Processing ended: Fri Nov 25 12:07:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075633154 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075633154 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075633154 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480075633154 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480075633850 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480075634664 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075634665 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:07:14 2016 " "Processing started: Fri Nov 25 12:07:14 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075634665 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075634665 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075634665 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075634795 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635355 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635356 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635402 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635403 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635903 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635926 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635927 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075635928 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075635928 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480075635928 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635928 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635930 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635943 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075635944 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075635952 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075635977 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635977 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.283 " "Worst-case setup slack is -3.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.283            -151.754 tick_50000:TICK0\|CLK_OUT  " "   -3.283            -151.754 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.079             -36.052 CLOCK_50  " "   -2.079             -36.052 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.282              -1.282 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.282              -1.282 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635979 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635979 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.277 " "Worst-case hold slack is 0.277" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.277               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.277               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.373               0.000 CLOCK_50  " "    0.373               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.487               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.487               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635983 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635983 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635985 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635986 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.616 " "Worst-case minimum pulse width slack is -0.616" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.616             -16.865 CLOCK_50  " "   -0.616             -16.865 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -36.356 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -36.356 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.359               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.359               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075635988 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075635988 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075635999 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075636036 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075636936 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637008 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075637015 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637015 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.254 " "Worst-case setup slack is -3.254" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.254            -146.749 tick_50000:TICK0\|CLK_OUT  " "   -3.254            -146.749 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.349             -36.643 CLOCK_50  " "   -2.349             -36.643 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.195              -1.195 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.195              -1.195 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637016 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637016 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.280 " "Worst-case hold slack is 0.280" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.280               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.280               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.388               0.000 CLOCK_50  " "    0.388               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.418               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.418               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637020 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637020 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637022 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637023 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.666 " "Worst-case minimum pulse width slack is -0.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.666             -15.553 CLOCK_50  " "   -0.666             -15.553 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -35.612 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -35.612 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.378               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.378               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075637025 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637025 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075637036 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637177 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075637956 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638023 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075638026 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638026 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.803 " "Worst-case setup slack is -1.803" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.803             -80.359 tick_50000:TICK0\|CLK_OUT  " "   -1.803             -80.359 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.941             -12.107 CLOCK_50  " "   -0.941             -12.107 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.396              -0.396 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.396              -0.396 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638028 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638028 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.069 " "Worst-case hold slack is 0.069" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.069               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.069               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.104               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.104               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.180               0.000 CLOCK_50  " "    0.180               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638032 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638032 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638034 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638035 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.749 " "Worst-case minimum pulse width slack is -0.749" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.749             -12.120 CLOCK_50  " "   -0.749             -12.120 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.047               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.047               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.348               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.348               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638037 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638037 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480075638049 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638209 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480075638212 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638212 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.560 " "Worst-case setup slack is -1.560" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.560             -68.840 tick_50000:TICK0\|CLK_OUT  " "   -1.560             -68.840 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.917              -9.973 CLOCK_50  " "   -0.917              -9.973 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.288              -0.288 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.288              -0.288 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638213 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638213 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.046 " "Worst-case hold slack is 0.046" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.046               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.046               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.065               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.065               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.174               0.000 CLOCK_50  " "    0.174               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638217 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638217 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638219 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638220 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.797 " "Worst-case minimum pulse width slack is -0.797" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.797             -14.383 CLOCK_50  " "   -0.797             -14.383 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.077               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.077               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.383               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.383               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480075638222 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075638222 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075639780 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075639782 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1211 " "Peak virtual memory: 1211 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075639829 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:07:19 2016 " "Processing ended: Fri Nov 25 12:07:19 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075639829 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075639829 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075639829 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075639829 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 53 s " "Quartus Prime Full Compilation was successful. 0 errors, 53 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480075640590 ""}
diff --git a/part_2/ex9_final/ex9.qws b/part_2/ex9_final/ex9.qws
deleted file mode 100755
index 5ba0123..0000000
--- a/part_2/ex9_final/ex9.qws
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
deleted file mode 100755
index 5548723..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
deleted file mode 100755
index f0b13b5..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
deleted file mode 100755
index ab08a4f..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
deleted file mode 100755
index 45da527..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
deleted file mode 100755
index d5fd8e6..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
deleted file mode 100755
index 614de49..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
deleted file mode 100755
index 658e9a5..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.dpi b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
deleted file mode 100755
index 604edf2..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
deleted file mode 100755
index cbb0e03..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
deleted file mode 100755
index 4ce95ae..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.kpt b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
deleted file mode 100755
index 0fd0d41..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
deleted file mode 100755
index b6b0e17..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
deleted file mode 100755
index 5bc7cd4..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
deleted file mode 100755
index c171a97..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
deleted file mode 100755
index a55899b..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
deleted file mode 100755
index 658e9a5..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
deleted file mode 100755
index cbb0e03..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
deleted file mode 100755
index 4ce95ae..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
deleted file mode 100755
index 0fd0d41..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrp.hdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrp.hdb
deleted file mode 100755
index 093f3cf..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrp.hdb
+++ /dev/null
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrs.cdb b/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrs.cdb
deleted file mode 100755
index f715ca1..0000000
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.rrs.cdb
+++ /dev/null
diff --git a/part_2/ex9_final/output_files/ex9.done b/part_2/ex9_final/output_files/ex9.done
deleted file mode 100755
index 42f2bb6..0000000
--- a/part_2/ex9_final/output_files/ex9.done
+++ /dev/null
@@ -1 +0,0 @@
-Fri Nov 25 12:11:16 2016
diff --git a/part_2/ex9_final/output_files/ex9.jdi b/part_2/ex9_final/output_files/ex9.jdi
deleted file mode 100755
index 98be503..0000000
--- a/part_2/ex9_final/output_files/ex9.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="a5a1d44468e3c5ecef42"/>
-  </project>
-  <file_info>
-    <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
diff --git a/part_2/ex9_final/output_files/ex9.map.rpt b/part_2/ex9_final/output_files/ex9.map.rpt
deleted file mode 100755
index 363df6b..0000000
--- a/part_2/ex9_final/output_files/ex9.map.rpt
+++ /dev/null
@@ -1,615 +0,0 @@
-Analysis & Synthesis report for ex9
-Fri Nov 25 12:10:26 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. State Machine - |ex9|delay:DEL0|state
-  9. State Machine - |ex9|formula_fsm:FSM|state
- 10. User-Specified and Inferred Latches
- 11. Registers Removed During Synthesis
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
- 16. Parameter Settings for User Entity Instance: formula_fsm:FSM
- 17. Parameter Settings for User Entity Instance: delay:DEL0
- 18. Parameter Settings for User Entity Instance: counter_16:COUNT0
- 19. Port Connectivity Checks: "hex_to_7seg:SEG5"
- 20. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
- 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
- 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
- 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
- 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
- 25. Port Connectivity Checks: "delay:DEL0"
- 26. Post-Synthesis Netlist Statistics for Top Partition
- 27. Elapsed Time Per Partition
- 28. Analysis & Synthesis Messages
- 29. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Altera and sold by Altera or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                      ;
-+---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status     ; Successful - Fri Nov 25 12:10:26 2016           ;
-; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
-; Family                          ; Cyclone V                                       ;
-; Logic utilization (in ALMs)     ; N/A                                             ;
-; Total registers                 ; 84                                              ;
-; Total pins                      ; 57                                              ;
-; Total virtual pins              ; 0                                               ;
-; Total block memory bits         ; 0                                               ;
-; Total DSP Blocks                ; 0                                               ;
-; Total HSSI RX PCSs              ; 0                                               ;
-; Total HSSI PMA RX Deserializers ; 0                                               ;
-; Total HSSI TX PCSs              ; 0                                               ;
-; Total HSSI PMA TX Serializers   ; 0                                               ;
-; Total PLLs                      ; 0                                               ;
-; Total DLLs                      ; 0                                               ;
-+---------------------------------+-------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                             ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                          ; Setting            ; Default Value      ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
-; Top-level entity name                                                           ; ex9                ; ex9                ;
-; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
-; Use smart compilation                                                           ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
-; Enable compact report table                                                     ; Off                ; Off                ;
-; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
-; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
-; Preserve fewer node names                                                       ; On                 ; On                 ;
-; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
-; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                                        ; Auto               ; Auto               ;
-; Safe State Machine                                                              ; Off                ; Off                ;
-; Extract Verilog State Machines                                                  ; On                 ; On                 ;
-; Extract VHDL State Machines                                                     ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
-; Parallel Synthesis                                                              ; On                 ; On                 ;
-; DSP Block Balancing                                                             ; Auto               ; Auto               ;
-; NOT Gate Push-Back                                                              ; On                 ; On                 ;
-; Power-Up Don't Care                                                             ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
-; Remove Duplicate Registers                                                      ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
-; Optimization Technique                                                          ; Balanced           ; Balanced           ;
-; Carry Chain Length                                                              ; 70                 ; 70                 ;
-; Auto Carry Chains                                                               ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
-; Auto ROM Replacement                                                            ; On                 ; On                 ;
-; Auto RAM Replacement                                                            ; On                 ; On                 ;
-; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
-; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
-; Strict RAM Replacement                                                          ; Off                ; Off                ;
-; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
-; Auto Resource Sharing                                                           ; Off                ; Off                ;
-; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
-; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
-; Report Parameter Settings                                                       ; On                 ; On                 ;
-; Report Source Assignments                                                       ; On                 ; On                 ;
-; Report Connectivity Checks                                                      ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
-; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
-; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
-; HDL message level                                                               ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
-; Clock MUX Protection                                                            ; On                 ; On                 ;
-; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
-; Block Design Naming                                                             ; Auto               ; Auto               ;
-; SDC constraint protection                                                       ; Off                ; Off                ;
-; Synthesis Effort                                                                ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
-; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
-; Synthesis Seed                                                                  ; 1                  ; 1                  ;
-; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
-; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.0%      ;
-;     Processors 3-4         ;   0.0%      ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ; Library ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/tick_50000.v  ;         ;
-; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/LFSR.v        ;         ;
-; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/hex_to_7seg.v ;         ;
-; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/formula_fsm.v ;         ;
-; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/delay.v       ;         ;
-; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/counter_16.v  ;         ;
-; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/bin2bcd_16.v  ;         ;
-; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/add3_ge5.v    ;         ;
-; verilog_files/ex9.v              ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/ex9.v         ;         ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary                            ;
-+---------------------------------------------+--------------------------+
-; Resource                                    ; Usage                    ;
-+---------------------------------------------+--------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 166                      ;
-;                                             ;                          ;
-; Combinational ALUT usage for logic          ; 290                      ;
-;     -- 7 input functions                    ; 0                        ;
-;     -- 6 input functions                    ; 41                       ;
-;     -- 5 input functions                    ; 5                        ;
-;     -- 4 input functions                    ; 157                      ;
-;     -- <=3 input functions                  ; 87                       ;
-;                                             ;                          ;
-; Dedicated logic registers                   ; 84                       ;
-;                                             ;                          ;
-; I/O pins                                    ; 57                       ;
-;                                             ;                          ;
-; Total DSP Blocks                            ; 0                        ;
-;                                             ;                          ;
-; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;
-; Maximum fan-out                             ; 67                       ;
-; Total fan-out                               ; 1423                     ;
-; Average fan-out                             ; 2.92                     ;
-+---------------------------------------------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9                       ; 290 (1)           ; 84 (0)       ; 0                 ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
-;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 124 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A10|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A1|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A32|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
-;       |add3_ge5:A33|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:COUNT0|     ; 17 (17)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
-;    |delay:DEL0|            ; 25 (25)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 43 (43)           ; 25 (25)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
-;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------+
-; State Machine - |ex9|delay:DEL0|state                                          ;
-+----------------+----------------+----------------+----------------+------------+
-; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
-+----------------+----------------+----------------+----------------+------------+
-; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;
-; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;
-; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;
-; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;
-+----------------+----------------+----------------+----------------+------------+
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------------------+
-; State Machine - |ex9|formula_fsm:FSM|state                                                 ;
-+------------------------+--------------------+------------------------+---------------------+
-; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
-+------------------------+--------------------+------------------------+---------------------+
-; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;
-; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;
-; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;
-+------------------------+--------------------+------------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches                                                                               ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;
-; Number of user-specified and inferred latches = 1  ;                                     ;                        ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------+
-; Registers Removed During Synthesis                         ;
-+---------------------------------------+--------------------+
-; Register name                         ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; delay:DEL0|state~5                    ; Lost fanout        ;
-; delay:DEL0|state~6                    ; Lost fanout        ;
-; Total Number of Removed Registers = 2 ;                    ;
-+---------------------------------------+--------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 84    ;
-; Number of registers using Synchronous Clear  ; 16    ;
-; Number of registers using Synchronous Load   ; 15    ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 42    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+---------------------------------------------------+
-; Inverted Register Statistics                      ;
-+-----------------------------------------+---------+
-; Inverted Register                       ; Fan out ;
-+-----------------------------------------+---------+
-; formula_fsm:FSM|count[1]                ; 2       ;
-; formula_fsm:FSM|count[0]                ; 2       ;
-; formula_fsm:FSM|count[6]                ; 2       ;
-; formula_fsm:FSM|count[7]                ; 2       ;
-; formula_fsm:FSM|count[8]                ; 2       ;
-; formula_fsm:FSM|count[11]               ; 2       ;
-; tick_50000:TICK0|count[14]              ; 2       ;
-; tick_50000:TICK0|count[15]              ; 2       ;
-; tick_50000:TICK0|count[0]               ; 2       ;
-; tick_50000:TICK0|count[1]               ; 2       ;
-; tick_50000:TICK0|count[2]               ; 2       ;
-; tick_50000:TICK0|count[3]               ; 2       ;
-; tick_50000:TICK0|count[6]               ; 2       ;
-; tick_50000:TICK0|count[8]               ; 2       ;
-; tick_50000:TICK0|count[9]               ; 2       ;
-; LFSR:LFSR0|COUNT[1]                     ; 3       ;
-; Total number of inverted registers = 16 ;         ;
-+-----------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex9|counter_16:COUNT0|count[0] ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[5]        ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[13]       ;
-; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |ex9|formula_fsm:FSM|count[0]   ;
-; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex9|formula_fsm:FSM|Selector3  ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex9|delay:DEL0|Selector16      ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex9|delay:DEL0|Selector17      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
-+----------------+-------+--------------------------------------+
-; Parameter Name ; Value ; Type                                 ;
-+----------------+-------+--------------------------------------+
-; NBIT           ; 16    ; Signed Integer                       ;
-+----------------+-------+--------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
-+------------------+-------+-----------------------------------+
-; Parameter Name   ; Value ; Type                              ;
-+------------------+-------+-----------------------------------+
-; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;
-; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;
-; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;
-+------------------+-------+-----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------+
-; Parameter Settings for User Entity Instance: delay:DEL0 ;
-+----------------+-------+--------------------------------+
-; Parameter Name ; Value ; Type                           ;
-+----------------+-------+--------------------------------+
-; BIT_SZ         ; 14    ; Signed Integer                 ;
-; IDLE           ; 00    ; Unsigned Binary                ;
-; COUNTING       ; 01    ; Unsigned Binary                ;
-; TIME_OUT       ; 10    ; Unsigned Binary                ;
-; WAIT_LOW       ; 11    ; Unsigned Binary                ;
-+----------------+-------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;
-+----------------+-------+---------------------------------------+
-; Parameter Name ; Value ; Type                                  ;
-+----------------+-------+---------------------------------------+
-; BIT_SZ         ; 16    ; Signed Integer                        ;
-; COUNTING       ; 1     ; Unsigned Binary                       ;
-; IDLE           ; 0     ; Unsigned Binary                       ;
-+----------------+-------+---------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------+
-; Port Connectivity Checks: "hex_to_7seg:SEG5" ;
-+------+-------+----------+--------------------+
-; Port ; Type  ; Severity ; Details            ;
-+------+-------+----------+--------------------+
-; in   ; Input ; Info     ; Stuck at GND       ;
-+------+-------+----------+--------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; Port  ; Type   ; Severity ; Details                                                                             ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
-; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type  ; Severity ; Details                                                                                                                                     ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type                  ; Count                       ;
-+-----------------------+-----------------------------+
-; arriav_ff             ; 84                          ;
-;     ENA               ; 12                          ;
-;     ENA SCLR          ; 16                          ;
-;     ENA SLD           ; 14                          ;
-;     SLD               ; 1                           ;
-;     plain             ; 41                          ;
-; arriav_lcell_comb     ; 308                         ;
-;     arith             ; 58                          ;
-;         1 data inputs ; 58                          ;
-;     normal            ; 250                         ;
-;         0 data inputs ; 2                           ;
-;         1 data inputs ; 28                          ;
-;         2 data inputs ; 8                           ;
-;         3 data inputs ; 9                           ;
-;         4 data inputs ; 157                         ;
-;         5 data inputs ; 5                           ;
-;         6 data inputs ; 41                          ;
-; boundary_port         ; 57                          ;
-;                       ;                             ;
-; Max LUT depth         ; 15.00                       ;
-; Average LUT depth     ; 7.32                        ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:00     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Fri Nov 25 12:10:16 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
-    Info (12023): Found entity 1: tick_50000 File: C:/New folder/ex9/verilog_files/tick_50000.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
-    Info (12023): Found entity 1: LFSR File: C:/New folder/ex9/verilog_files/LFSR.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
-    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex9/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
-    Info (12023): Found entity 1: formula_fsm File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
-    Info (12023): Found entity 1: delay File: C:/New folder/ex9/verilog_files/delay.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
-    Info (12023): Found entity 1: counter_16 File: C:/New folder/ex9/verilog_files/counter_16.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
-    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
-    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex9/verilog_files/add3_ge5.v Line: 9
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v
-    Info (12023): Found entity 1: ex9 File: C:/New folder/ex9/verilog_files/ex9.v Line: 1
-Info (12127): Elaborating entity "ex9" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 14
-Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: C:/New folder/ex9/verilog_files/ex9.v Line: 16
-Info (10264): Verilog HDL Case Statement information at formula_fsm.v(39): all case item expressions in this case statement are onehot File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 39
-Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(58): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 58
-Info (10041): Inferred latch for "start_delay" at formula_fsm.v(58) File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 58
-Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 18
-Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 20
-Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: C:/New folder/ex9/verilog_files/delay.v Line: 24
-Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 22
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: C:/New folder/ex9/verilog_files/ex9.v Line: 24
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 26
-Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
-    Warning (13410): Pin "HEX5[0]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[1]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[2]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[3]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[4]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[5]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[6]" is stuck at VCC File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 2 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 2 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "KEY[1]" File: C:/New folder/ex9/verilog_files/ex9.v Line: 4
-    Warning (15610): No output dependent on input pin "KEY[2]" File: C:/New folder/ex9/verilog_files/ex9.v Line: 4
-Info (21057): Implemented 354 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 5 input pins
-    Info (21059): Implemented 52 output pins
-    Info (21061): Implemented 297 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
-    Info: Peak virtual memory: 898 megabytes
-    Info: Processing ended: Fri Nov 25 12:10:26 2016
-    Info: Elapsed time: 00:00:10
-    Info: Total CPU time (on all processors): 00:00:22
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in C:/New folder/ex9/output_files/ex9.map.smsg.
-
-
diff --git a/part_2/ex9_final/output_files/ex9.sta.summary b/part_2/ex9_final/output_files/ex9.sta.summary
deleted file mode 100755
index 87e925d..0000000
--- a/part_2/ex9_final/output_files/ex9.sta.summary
+++ /dev/null
@@ -1,149 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.462
-TNS   : -161.413
-
-Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -2.047
-TNS   : -40.775
-
-Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.675
-TNS   : -1.675
-
-Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.179
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.385
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.629
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.637
-TNS   : -18.132
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -38.762
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.459
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.416
-TNS   : -157.230
-
-Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -2.323
-TNS   : -41.799
-
-Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.568
-TNS   : -1.568
-
-Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.193
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.405
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.501
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.689
-TNS   : -16.816
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -38.286
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.412
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.794
-TNS   : -79.872
-
-Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -0.918
-TNS   : -13.912
-
-Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.572
-TNS   : -0.572
-
-Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.020
-TNS   : -0.037
-
-Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.185
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.202
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.740
-TNS   : -12.957
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.012
-TNS   : -0.190
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.478
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.581
-TNS   : -69.264
-
-Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -0.868
-TNS   : -11.639
-
-Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.462
-TNS   : -0.462
-
-Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.021
-TNS   : -0.052
-
-Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.122
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.177
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.789
-TNS   : -15.486
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.024
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.468
-TNS   : 0.000
-
-------------------------------------------------------------
diff --git a/part_2/ex9_final/verilog_files/LFSR.v b/part_2/ex9_final/verilog_files/LFSR.v
deleted file mode 100755
index 46140b2..0000000
--- a/part_2/ex9_final/verilog_files/LFSR.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module LFSR(CLK, en, COUNT);
-
-	input CLK;
-	input en;
-	
-	output [7:1] COUNT;
-	
-	reg [7:1] COUNT;
-	initial COUNT = 7'd1;
-		
-	always @ (posedge CLK)
-		if(en == 1'b1)
-			COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
-		else
-			COUNT <= COUNT;
-		
-endmodule
-	
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/LFSR.v.bak b/part_2/ex9_final/verilog_files/LFSR.v.bak
deleted file mode 100755
index 89ec82a..0000000
--- a/part_2/ex9_final/verilog_files/LFSR.v.bak
+++ /dev/null
@@ -1,11 +0,0 @@
-module LFSR(CLK, COUNT);
-	input CLK;
-	output[7:1] COUNT;
-	reg[7:1] COUNT;
-	initial COUNT = 7'd1;
-		
-	always @ (posedge CLK)
-		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
-		
-endmodule
-	
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/add3_ge5.v b/part_2/ex9_final/verilog_files/add3_ge5.v
deleted file mode 100755
index a3cd6a9..0000000
--- a/part_2/ex9_final/verilog_files/add3_ge5.v
+++ /dev/null
@@ -1,34 +0,0 @@
-//------------------------------
-// Module name: add3_ge5
-// Function: Add 3 to input if it is 5 or above
-// Creator:  Peter Cheung
-// Version:  1.0
-// Date:     21 Jan 2014
-//------------------------------
-
-module add3_ge5(iW,oA);
-
- input [3:0] iW; 
- output reg [3:0] oA;  
- 
-	always @ (iW)
-		case (iW) 
-		//****** input <5, pass to output unchanged ******
-			4'b0000: oA <= 4'b0000; 
-			4'b0001: oA <= 4'b0001; 
-			4'b0010: oA <= 4'b0010; 
-			4'b0011: oA <= 4'b0011; 
-			4'b0100: oA <= 4'b0100;
-			
-		//****** input >=5, output = input + 3	******	
-			4'b0101: oA <= 4'b1000; 
-			4'b0110: oA <= 4'b1001; 
-			4'b0111: oA <= 4'b1010; 
-			4'b1000: oA <= 4'b1011; 
-			4'b1001: oA <= 4'b1100;
-			4'b1010: oA <= 4'b1101;	
-			4'b1011: oA <= 4'b1110;	
-			4'b1100: oA <= 4'b1111;	
-			default: oA <= 4'b0000; // oA cannot be 13 or larger, else overflow
-		endcase 
-endmodule
diff --git a/part_2/ex9_final/verilog_files/counter_16.v b/part_2/ex9_final/verilog_files/counter_16.v
deleted file mode 100755
index 79c144c..0000000
--- a/part_2/ex9_final/verilog_files/counter_16.v
+++ /dev/null
@@ -1,31 +0,0 @@
-module counter_16(clock, start, stop, count);
-
-	parameter BIT_SZ = 16;
-	input clock, start, stop;
-	output [BIT_SZ-1:0] count;
-	
-	reg [BIT_SZ-1:0] count;
-	
-	reg state;
-	
-	parameter COUNTING = 1'b1, IDLE = 1'b0;
-	
-	initial count = 0;
-	initial state = IDLE;
-	
-	always @ (posedge clock)
-		case(state)
-			IDLE:
-				if(start == 1'b1)
-					begin
-						count = 0;
-						state = COUNTING;
-					end
-			COUNTING:
-				if(stop == 1'b1)
-					state <= IDLE;
-				else
-					count <= count + 1'b1;
-		endcase
-			
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/counter_16.v.bak b/part_2/ex9_final/verilog_files/counter_16.v.bak
deleted file mode 100755
index c0ec549..0000000
--- a/part_2/ex9_final/verilog_files/counter_16.v.bak
+++ /dev/null
@@ -1,21 +0,0 @@
-`timescale 1ns / 100ps
-
-module counter_16(clock,enable,reset,count);
-
-	parameter BIT_SZ = 16;
-	input clock, enable, reset;
-	output [BIT_SZ-1:0] count;
-	
-	reg [BIT_SZ-1:0] count;
-	
-	initial count = 0;
-	
-	always @ (posedge clock)
-		begin
-			if(enable == 1'b1)
-				count <= count + 1'b1;
-			if(reset == 1'b1)
-				count <= 16'b0;
-		end
-			
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/delay.v b/part_2/ex9_final/verilog_files/delay.v
deleted file mode 100755
index a983085..0000000
--- a/part_2/ex9_final/verilog_files/delay.v
+++ /dev/null
@@ -1,60 +0,0 @@
-module delay(clk, N, trigger, time_out);
-
-	parameter BIT_SZ = 14;
-
-	input clk, trigger;
-	input [BIT_SZ-1:0] N;
-	output time_out;
-
-	reg[BIT_SZ-1:0] count;
-	reg time_out;
-
-	reg [1:0] state;
-
-	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
-
-	initial begin
-		state = IDLE;
-	end
-	
-	always @ (posedge clk)
-		case(state)
-			IDLE: if(trigger == 1'b1)
-				begin
-					count <= N*128;
-					state <= COUNTING;
-				end
-			COUNTING: 
-				begin
-					if(count == 1'b0)
-						begin
-							state <= TIME_OUT;
-						end
-					else 
-						count <= count - 1'b1;
-				end
-			TIME_OUT: 
-				begin
-					if(trigger == 1'b0)
-						state <= IDLE;
-					else
-						state <= WAIT_LOW;
-				end
-			WAIT_LOW: 
-				if(trigger == 1'b0)
-					state <= IDLE;
-			default: ;
-		endcase
-		
-	always @ (*)
-		case(state)
-			IDLE:
-					time_out = 1'b0;
-			COUNTING: 
-					time_out = 1'b0;
-			TIME_OUT: time_out = 1'b1;
-			WAIT_LOW: time_out = 1'b0;
-			default: ;
-		endcase
-
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/delay.v.bak b/part_2/ex9_final/verilog_files/delay.v.bak
deleted file mode 100755
index 7b79342..0000000
--- a/part_2/ex9_final/verilog_files/delay.v.bak
+++ /dev/null
@@ -1,47 +0,0 @@
-module delay(clk, N, trigger, time_out);
-
-	parameter BIT_SZ = 7
-
-	input clk, trigger;
-	input [BIT_SZ-1:0] N;
-	output time_out;
-
-	reg[BIT_SZ-1:0] count;
-	reg time_out;
-
-	reg [1:0] state;
-
-	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
-
-	initial begin
-		state = IDLE;
-		count = N-1'b1;
-	end
-	
-	always @ (posedge clk)
-		case(state)
-			IDLE: if(trigger == 1'b1)
-					state <= COUNTING;
-			COUNTING: if(count == 1'b0) begin
-					count <= n - 1'b1;
-					state <= TIME_OUT;
-				end
-			TIME_OUT: if(trigger == 1'b0)
-					state <= IDLE;
-				else
-					state <= WAIT_LOW;
-			WAIT_LOW: if(trigger == 1'b0)
-					state <= IDLE;
-			defualt: ;
-		endcase
-		
-	always @ (*)
-		case(state)
-			IDLE: time_out = 1'b0;
-			COUNTING: time_out = 1'b0;
-			TIME_OUT: time_out = 1'b1;
-			WAIT_LOW: time_out = 1'b0;
-			default: ;
-		endcase
-
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex8.v b/part_2/ex9_final/verilog_files/ex8.v
deleted file mode 100755
index 6ca51d6..0000000
--- a/part_2/ex9_final/verilog_files/ex8.v
+++ /dev/null
@@ -1,23 +0,0 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
-	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex8.v.bak b/part_2/ex9_final/verilog_files/ex8.v.bak
deleted file mode 100755
index ac293e7..0000000
--- a/part_2/ex9_final/verilog_files/ex8.v.bak
+++ /dev/null
@@ -1 +0,0 @@
-module ex8(
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex9.v b/part_2/ex9_final/verilog_files/ex9.v
deleted file mode 100755
index 15446c2..0000000
--- a/part_2/ex9_final/verilog_files/ex9.v
+++ /dev/null
@@ -1,33 +0,0 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	wire [15:0] count_out;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	
-	formula_fsm FSM(tick_ms, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	
-	counter_16 COUNT0(tick_ms, time_out, ~KEY[0], count_out);
-	
-	bin2bcd_16 BCD(count_out, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	hex_to_7seg SEG3(HEX3, BCD_3);
-	hex_to_7seg SEG4(HEX4, BCD_4);
-	hex_to_7seg SEG5(HEX5, 4'b0);
-	
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/ex9.v.bak b/part_2/ex9_final/verilog_files/ex9.v.bak
deleted file mode 100755
index 6ca51d6..0000000
--- a/part_2/ex9_final/verilog_files/ex9.v.bak
+++ /dev/null
@@ -1,23 +0,0 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
-	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/formula_fsm.v b/part_2/ex9_final/verilog_files/formula_fsm.v
deleted file mode 100755
index 2a79785..0000000
--- a/part_2/ex9_final/verilog_files/formula_fsm.v
+++ /dev/null
@@ -1,76 +0,0 @@
-module formula_fsm(clk, trigger, time_out, en_lfsr, start_delay, ledr);
-
-input clk, time_out, trigger;
-output en_lfsr, start_delay;
-output [9:0] ledr;
-
-reg [1:0] state;
-reg led_on, en_lfsr, start_delay;
-reg [9:0] ledr;
-reg [11:0] count;
-
-parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
-
-initial 
-	begin
-		state = WAIT_TRIGGER;
-		en_lfsr = 1'b0;
-		start_delay = 1'b0;
-		count = 12'd2499;
-	end
-
-always @ (posedge clk)
-	case(state)
-		WAIT_TRIGGER: 
-			begin
-				if(trigger == 1'b1)
-					state <= LIGHT_UP_LEDS;
-			end
-		LIGHT_UP_LEDS:
-				if(ledr == 10'h3ff)
-					state <= WAIT_FOR_TIMEOUT;
-		WAIT_FOR_TIMEOUT:
-				if(time_out == 1'b1)
-					 state <= WAIT_TRIGGER;
-		default: ;
-	endcase
-
-always @ (posedge clk)
-	case(state)
-		WAIT_TRIGGER:
-			ledr = 0;
-		LIGHT_UP_LEDS:
-			begin
-				if(count == 1'b0)
-					begin
-						ledr <= {ledr[8:0], 1'b1};
-						count <= 12'd2499;
-					end
-				else
-					begin
-						count <= count - 1'b1;
-					end
-			end
-		default: count <= 12'd2499;
-	endcase
-	
-always @ (*)
-	case(state)
-		WAIT_TRIGGER:
-			begin
-				en_lfsr = 1'b0;
-				start_delay = 1'b0;
-			end
-		LIGHT_UP_LEDS:
-			begin
-				en_lfsr = 1'b1;
-			end
-		WAIT_FOR_TIMEOUT:
-			begin
-				start_delay = 1'b1;
-				en_lfsr = 1'b0;
-			end
-		default: ;
-	endcase
-
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/formula_fsm.v.bak b/part_2/ex9_final/verilog_files/formula_fsm.v.bak
deleted file mode 100755
index e69de29..0000000
--- a/part_2/ex9_final/verilog_files/formula_fsm.v.bak
+++ /dev/null
diff --git a/part_2/ex9_final/verilog_files/tick_2500.v b/part_2/ex9_final/verilog_files/tick_2500.v
deleted file mode 100755
index e75a131..0000000
--- a/part_2/ex9_final/verilog_files/tick_2500.v
+++ /dev/null
@@ -1,35 +0,0 @@
-module tick_2500(CLOCK_IN, en, CLK_OUT);
-
-	parameter NBIT = 12;
-	
-	input CLOCK_IN, en;
-	output CLK_OUT;
-	
-	reg [NBIT-1:0] count;
-	
-	reg CLK_OUT;
-	
-	initial 
-		begin
-			count = 12'd2499;
-			CLK_OUT = 1'b0;
-		end
-	
-	always @ (posedge CLOCK_IN)
-		if(en == 1'b1)
-			begin
-				if(count == 1'b0)
-					begin
-						CLK_OUT <= 1'b1;
-						count <= 12'd2499;
-					end
-				else
-					begin
-						count <= count - 1'b1;
-						CLK_OUT <= 1'b0;
-					end
-			end
-		else 
-			CLK_OUT <= 1'b0;
-
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/tick_2500.v.bak b/part_2/ex9_final/verilog_files/tick_2500.v.bak
deleted file mode 100755
index e69de29..0000000
--- a/part_2/ex9_final/verilog_files/tick_2500.v.bak
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/.cmp.kpt b/part_2/ex9_partially_working/db/.cmp.kpt
deleted file mode 100755
index 65813d1..0000000
--- a/part_2/ex9_partially_working/db/.cmp.kpt
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(0).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(0).cnf.cdb
deleted file mode 100755
index 94e08e0..0000000
--- a/part_2/ex9_partially_working/db/ex9.(0).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(0).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(0).cnf.hdb
deleted file mode 100755
index d744dd2..0000000
--- a/part_2/ex9_partially_working/db/ex9.(0).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(1).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(1).cnf.cdb
deleted file mode 100755
index 6fa5bfa..0000000
--- a/part_2/ex9_partially_working/db/ex9.(1).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(1).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(1).cnf.hdb
deleted file mode 100755
index 829c3df..0000000
--- a/part_2/ex9_partially_working/db/ex9.(1).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(2).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(2).cnf.cdb
deleted file mode 100755
index 43aabd2..0000000
--- a/part_2/ex9_partially_working/db/ex9.(2).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(2).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(2).cnf.hdb
deleted file mode 100755
index a2fe649..0000000
--- a/part_2/ex9_partially_working/db/ex9.(2).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(3).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(3).cnf.cdb
deleted file mode 100755
index 47115a1..0000000
--- a/part_2/ex9_partially_working/db/ex9.(3).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(3).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(3).cnf.hdb
deleted file mode 100755
index ef27b03..0000000
--- a/part_2/ex9_partially_working/db/ex9.(3).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(4).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(4).cnf.cdb
deleted file mode 100755
index 13f6ae2..0000000
--- a/part_2/ex9_partially_working/db/ex9.(4).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(4).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(4).cnf.hdb
deleted file mode 100755
index b7d17a9..0000000
--- a/part_2/ex9_partially_working/db/ex9.(4).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(5).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(5).cnf.cdb
deleted file mode 100755
index 53d103c..0000000
--- a/part_2/ex9_partially_working/db/ex9.(5).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(5).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(5).cnf.hdb
deleted file mode 100755
index 01910af..0000000
--- a/part_2/ex9_partially_working/db/ex9.(5).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(6).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(6).cnf.cdb
deleted file mode 100755
index 3c6c09e..0000000
--- a/part_2/ex9_partially_working/db/ex9.(6).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(6).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(6).cnf.hdb
deleted file mode 100755
index 1c167a7..0000000
--- a/part_2/ex9_partially_working/db/ex9.(6).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(7).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(7).cnf.cdb
deleted file mode 100755
index 604867e..0000000
--- a/part_2/ex9_partially_working/db/ex9.(7).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(7).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(7).cnf.hdb
deleted file mode 100755
index da601fb..0000000
--- a/part_2/ex9_partially_working/db/ex9.(7).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(8).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(8).cnf.cdb
deleted file mode 100755
index 97e595e..0000000
--- a/part_2/ex9_partially_working/db/ex9.(8).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(8).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(8).cnf.hdb
deleted file mode 100755
index 42ab8b5..0000000
--- a/part_2/ex9_partially_working/db/ex9.(8).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(9).cnf.cdb b/part_2/ex9_partially_working/db/ex9.(9).cnf.cdb
deleted file mode 100755
index e219d8b..0000000
--- a/part_2/ex9_partially_working/db/ex9.(9).cnf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.(9).cnf.hdb b/part_2/ex9_partially_working/db/ex9.(9).cnf.hdb
deleted file mode 100755
index 0bbfa6a..0000000
--- a/part_2/ex9_partially_working/db/ex9.(9).cnf.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.asm.rdb b/part_2/ex9_partially_working/db/ex9.asm.rdb
deleted file mode 100755
index fbc9bdf..0000000
--- a/part_2/ex9_partially_working/db/ex9.asm.rdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.ammdb b/part_2/ex9_partially_working/db/ex9.cmp.ammdb
deleted file mode 100755
index 70f3c8b..0000000
--- a/part_2/ex9_partially_working/db/ex9.cmp.ammdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.bpm b/part_2/ex9_partially_working/db/ex9.cmp.bpm
deleted file mode 100755
index d55aa16..0000000
--- a/part_2/ex9_partially_working/db/ex9.cmp.bpm
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.cdb b/part_2/ex9_partially_working/db/ex9.cmp.cdb
deleted file mode 100755
index 82368ee..0000000
--- a/part_2/ex9_partially_working/db/ex9.cmp.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.hdb b/part_2/ex9_partially_working/db/ex9.cmp.hdb
deleted file mode 100755
index 2dfdacd..0000000
--- a/part_2/ex9_partially_working/db/ex9.cmp.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.idb b/part_2/ex9_partially_working/db/ex9.cmp.idb
deleted file mode 100755
index 79dee8d..0000000
--- a/part_2/ex9_partially_working/db/ex9.cmp.idb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.rdb b/part_2/ex9_partially_working/db/ex9.cmp.rdb
deleted file mode 100755
index 44b0f39..0000000
--- a/part_2/ex9_partially_working/db/ex9.cmp.rdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.cmp_merge.kpt b/part_2/ex9_partially_working/db/ex9.cmp_merge.kpt
deleted file mode 100755
index fdd3bfe..0000000
--- a/part_2/ex9_partially_working/db/ex9.cmp_merge.kpt
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.fit.qmsg b/part_2/ex9_partially_working/db/ex9.fit.qmsg
deleted file mode 100755
index 1ec4c4f..0000000
--- a/part_2/ex9_partially_working/db/ex9.fit.qmsg
+++ /dev/null
@@ -1,45 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480073240104 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480073240104 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "ex9 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex9\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480073240361 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480073240426 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480073240426 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480073240809 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480073240945 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480073251057 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 28 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480073251162 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480073251162 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073251163 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480073251166 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480073251167 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480073251168 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480073251168 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480073251168 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480073251169 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1480073251795 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480073251796 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480073251796 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480073251800 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480073251800 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480073251801 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480073251804 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480073251805 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480073251805 ""}
-{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_CS " "Node \"DAC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_LD " "Node \"DAC_LD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_LD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SCK " "Node \"DAC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DAC_SDI " "Node \"DAC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DAC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PWM_OUT " "Node \"PWM_OUT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PWM_OUT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480073251852 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480073251852 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073251853 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480073256842 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480073257105 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073257935 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480073258972 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480073259841 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073259841 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480073261018 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex9/" { { 1 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480073265606 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480073265606 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480073268941 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480073268941 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073268945 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480073270428 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480073270467 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480073270913 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480073270913 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480073271356 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480073274070 ""}
-{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480073274322 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.fit.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480073274384 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 30 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2617 " "Peak virtual memory: 2617 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073274841 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 11:27:54 2016 " "Processing ended: Fri Nov 25 11:27:54 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073274841 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:35 " "Elapsed time: 00:00:35" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073274841 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:03 " "Total CPU time (on all processors): 00:01:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073274841 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480073274841 ""}
diff --git a/part_2/ex9_partially_working/db/ex9.hier_info b/part_2/ex9_partially_working/db/ex9.hier_info
deleted file mode 100755
index c903416..0000000
--- a/part_2/ex9_partially_working/db/ex9.hier_info
+++ /dev/null
@@ -1,802 +0,0 @@
-|ex9
-CLOCK_50 => CLOCK_50.IN2
-KEY[0] => _.IN1
-KEY[1] => ~NO_FANOUT~
-KEY[2] => ~NO_FANOUT~
-KEY[3] => _.IN1
-HEX0[0] <= hex_to_7seg:SEG0.port0
-HEX0[1] <= hex_to_7seg:SEG0.port0
-HEX0[2] <= hex_to_7seg:SEG0.port0
-HEX0[3] <= hex_to_7seg:SEG0.port0
-HEX0[4] <= hex_to_7seg:SEG0.port0
-HEX0[5] <= hex_to_7seg:SEG0.port0
-HEX0[6] <= hex_to_7seg:SEG0.port0
-HEX1[0] <= hex_to_7seg:SEG1.port0
-HEX1[1] <= hex_to_7seg:SEG1.port0
-HEX1[2] <= hex_to_7seg:SEG1.port0
-HEX1[3] <= hex_to_7seg:SEG1.port0
-HEX1[4] <= hex_to_7seg:SEG1.port0
-HEX1[5] <= hex_to_7seg:SEG1.port0
-HEX1[6] <= hex_to_7seg:SEG1.port0
-HEX2[0] <= hex_to_7seg:SEG2.port0
-HEX2[1] <= hex_to_7seg:SEG2.port0
-HEX2[2] <= hex_to_7seg:SEG2.port0
-HEX2[3] <= hex_to_7seg:SEG2.port0
-HEX2[4] <= hex_to_7seg:SEG2.port0
-HEX2[5] <= hex_to_7seg:SEG2.port0
-HEX2[6] <= hex_to_7seg:SEG2.port0
-HEX3[0] <= hex_to_7seg:SEG3.port0
-HEX3[1] <= hex_to_7seg:SEG3.port0
-HEX3[2] <= hex_to_7seg:SEG3.port0
-HEX3[3] <= hex_to_7seg:SEG3.port0
-HEX3[4] <= hex_to_7seg:SEG3.port0
-HEX3[5] <= hex_to_7seg:SEG3.port0
-HEX3[6] <= hex_to_7seg:SEG3.port0
-HEX4[0] <= hex_to_7seg:SEG4.port0
-HEX4[1] <= hex_to_7seg:SEG4.port0
-HEX4[2] <= hex_to_7seg:SEG4.port0
-HEX4[3] <= hex_to_7seg:SEG4.port0
-HEX4[4] <= hex_to_7seg:SEG4.port0
-HEX4[5] <= hex_to_7seg:SEG4.port0
-HEX4[6] <= hex_to_7seg:SEG4.port0
-HEX5[0] <= hex_to_7seg:SEG5.port0
-HEX5[1] <= hex_to_7seg:SEG5.port0
-HEX5[2] <= hex_to_7seg:SEG5.port0
-HEX5[3] <= hex_to_7seg:SEG5.port0
-HEX5[4] <= hex_to_7seg:SEG5.port0
-HEX5[5] <= hex_to_7seg:SEG5.port0
-HEX5[6] <= hex_to_7seg:SEG5.port0
-LEDR[0] <= formula_fsm:FSM.port6
-LEDR[1] <= formula_fsm:FSM.port6
-LEDR[2] <= formula_fsm:FSM.port6
-LEDR[3] <= formula_fsm:FSM.port6
-LEDR[4] <= formula_fsm:FSM.port6
-LEDR[5] <= formula_fsm:FSM.port6
-LEDR[6] <= formula_fsm:FSM.port6
-LEDR[7] <= formula_fsm:FSM.port6
-LEDR[8] <= formula_fsm:FSM.port6
-LEDR[9] <= formula_fsm:FSM.port6
-
-
-|ex9|tick_50000:TICK0
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => count[12].CLK
-CLOCK_IN => count[13].CLK
-CLOCK_IN => count[14].CLK
-CLOCK_IN => count[15].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|tick_2500:TICK1
-CLOCK_IN => count[0].CLK
-CLOCK_IN => count[1].CLK
-CLOCK_IN => count[2].CLK
-CLOCK_IN => count[3].CLK
-CLOCK_IN => count[4].CLK
-CLOCK_IN => count[5].CLK
-CLOCK_IN => count[6].CLK
-CLOCK_IN => count[7].CLK
-CLOCK_IN => count[8].CLK
-CLOCK_IN => count[9].CLK
-CLOCK_IN => count[10].CLK
-CLOCK_IN => count[11].CLK
-CLOCK_IN => CLK_OUT~reg0.CLK
-en => CLK_OUT.OUTPUTSELECT
-en => count[0].ENA
-en => count[1].ENA
-en => count[2].ENA
-en => count[3].ENA
-en => count[4].ENA
-en => count[5].ENA
-en => count[6].ENA
-en => count[7].ENA
-en => count[8].ENA
-en => count[9].ENA
-en => count[10].ENA
-en => count[11].ENA
-CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|formula_fsm:FSM
-clk => state~3.DATAIN
-tick => ledr[0]~reg0.CLK
-tick => ledr[1]~reg0.CLK
-tick => ledr[2]~reg0.CLK
-tick => ledr[3]~reg0.CLK
-tick => ledr[4]~reg0.CLK
-tick => ledr[5]~reg0.CLK
-tick => ledr[6]~reg0.CLK
-tick => ledr[7]~reg0.CLK
-tick => ledr[8]~reg0.CLK
-tick => ledr[9]~reg0.CLK
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-time_out => state.OUTPUTSELECT
-en_lfsr <= en_lfsr.DB_MAX_OUTPUT_PORT_TYPE
-start_delay <= start_delay$latch.DB_MAX_OUTPUT_PORT_TYPE
-ledr[0] <= ledr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[1] <= ledr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[2] <= ledr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[3] <= ledr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[4] <= ledr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[5] <= ledr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[6] <= ledr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[7] <= ledr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[8] <= ledr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-ledr[9] <= ledr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|LFSR:LFSR0
-CLK => COUNT[1]~reg0.CLK
-CLK => COUNT[2]~reg0.CLK
-CLK => COUNT[3]~reg0.CLK
-CLK => COUNT[4]~reg0.CLK
-CLK => COUNT[5]~reg0.CLK
-CLK => COUNT[6]~reg0.CLK
-CLK => COUNT[7]~reg0.CLK
-en => COUNT[1]~reg0.ENA
-en => COUNT[2]~reg0.ENA
-en => COUNT[3]~reg0.ENA
-en => COUNT[4]~reg0.ENA
-en => COUNT[5]~reg0.ENA
-en => COUNT[6]~reg0.ENA
-en => COUNT[7]~reg0.ENA
-COUNT[1] <= COUNT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[2] <= COUNT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[3] <= COUNT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[4] <= COUNT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[5] <= COUNT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[6] <= COUNT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-COUNT[7] <= COUNT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|delay:DEL0
-clk => count[0].CLK
-clk => count[1].CLK
-clk => count[2].CLK
-clk => count[3].CLK
-clk => count[4].CLK
-clk => count[5].CLK
-clk => count[6].CLK
-clk => count[7].CLK
-clk => count[8].CLK
-clk => count[9].CLK
-clk => count[10].CLK
-clk => count[11].CLK
-clk => count[12].CLK
-clk => count[13].CLK
-clk => state~4.DATAIN
-N[0] => count.DATAB
-N[1] => count.DATAB
-N[2] => count.DATAB
-N[3] => count.DATAB
-N[4] => count.DATAB
-N[5] => count.DATAB
-N[6] => count.DATAB
-N[7] => ~NO_FANOUT~
-N[8] => ~NO_FANOUT~
-N[9] => ~NO_FANOUT~
-N[10] => ~NO_FANOUT~
-N[11] => ~NO_FANOUT~
-N[12] => ~NO_FANOUT~
-N[13] => ~NO_FANOUT~
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => count.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector17.IN3
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => state.OUTPUTSELECT
-trigger => Selector14.IN2
-time_out <= time_out.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|counter_16:COUNT0
-clock => count[0]~reg0.CLK
-clock => count[1]~reg0.CLK
-clock => count[2]~reg0.CLK
-clock => count[3]~reg0.CLK
-clock => count[4]~reg0.CLK
-clock => count[5]~reg0.CLK
-clock => count[6]~reg0.CLK
-clock => count[7]~reg0.CLK
-clock => count[8]~reg0.CLK
-clock => count[9]~reg0.CLK
-clock => count[10]~reg0.CLK
-clock => count[11]~reg0.CLK
-clock => count[12]~reg0.CLK
-clock => count[13]~reg0.CLK
-clock => count[14]~reg0.CLK
-clock => count[15]~reg0.CLK
-clock => state.CLK
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => count.OUTPUTSELECT
-start => state.OUTPUTSELECT
-stop => state.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-stop => count.OUTPUTSELECT
-count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[13] <= count[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[14] <= count[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-count[15] <= count[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD
-B[0] => BCD_0[0].DATAIN
-B[1] => w35[0].IN1
-B[2] => w30[0].IN1
-B[3] => w26[0].IN1
-B[4] => w22[0].IN1
-B[5] => w18[0].IN1
-B[6] => w15[0].IN1
-B[7] => w12[0].IN1
-B[8] => w9[0].IN1
-B[9] => w7[0].IN1
-B[10] => w5[0].IN1
-B[11] => w3[0].IN1
-B[12] => w2[0].IN1
-B[13] => w1[0].IN1
-B[14] => w1[1].IN1
-B[15] => w1[2].IN1
-BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
-BCD_0[1] <= add3_ge5:A35.port1
-BCD_0[2] <= add3_ge5:A35.port1
-BCD_0[3] <= add3_ge5:A35.port1
-BCD_1[0] <= add3_ge5:A35.port1
-BCD_1[1] <= add3_ge5:A34.port1
-BCD_1[2] <= add3_ge5:A34.port1
-BCD_1[3] <= add3_ge5:A34.port1
-BCD_2[0] <= add3_ge5:A34.port1
-BCD_2[1] <= add3_ge5:A33.port1
-BCD_2[2] <= add3_ge5:A33.port1
-BCD_2[3] <= add3_ge5:A33.port1
-BCD_3[0] <= add3_ge5:A33.port1
-BCD_3[1] <= add3_ge5:A32.port1
-BCD_3[2] <= add3_ge5:A32.port1
-BCD_3[3] <= add3_ge5:A32.port1
-BCD_4[0] <= add3_ge5:A32.port1
-BCD_4[1] <= add3_ge5:A31.port1
-BCD_4[2] <= add3_ge5:A31.port1
-BCD_4[3] <= add3_ge5:A31.port1
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A1
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A2
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A3
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A4
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A5
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A6
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A7
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A8
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A9
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A10
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A11
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A12
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A13
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A14
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A15
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A16
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A17
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A18
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A19
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A20
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A21
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A22
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A23
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A24
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A25
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A26
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A27
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A28
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A29
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A30
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A31
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A32
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A33
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A34
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|bin2bcd_16:BCD|add3_ge5:A35
-iW[0] => Decoder0.IN3
-iW[1] => Decoder0.IN2
-iW[2] => Decoder0.IN1
-iW[3] => Decoder0.IN0
-oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|ex9|hex_to_7seg:SEG0
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG1
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG2
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG3
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG4
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
-|ex9|hex_to_7seg:SEG5
-out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
-out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
-out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
-out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
-out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
-out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
-out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
-in[0] => Decoder0.IN3
-in[1] => Decoder0.IN2
-in[2] => Decoder0.IN1
-in[3] => Decoder0.IN0
-
-
diff --git a/part_2/ex9_partially_working/db/ex9.hif b/part_2/ex9_partially_working/db/ex9.hif
deleted file mode 100755
index ae8cd2b..0000000
--- a/part_2/ex9_partially_working/db/ex9.hif
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.lpc.rdb b/part_2/ex9_partially_working/db/ex9.lpc.rdb
deleted file mode 100755
index fb83048..0000000
--- a/part_2/ex9_partially_working/db/ex9.lpc.rdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.lpc.txt b/part_2/ex9_partially_working/db/ex9.lpc.txt
deleted file mode 100755
index faa2fa4..0000000
--- a/part_2/ex9_partially_working/db/ex9.lpc.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; SEG5      ; 4     ; 4              ; 0            ; 4              ; 7      ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG4      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG3      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG2      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A35   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A34   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A33   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A32   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A31   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A30   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A29   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A28   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A27   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A26   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A25   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A24   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A23   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A22   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A21   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A20   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A19   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A18   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A17   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A16   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A15   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A14   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A13   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A12   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A11   ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A10   ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A9    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A8    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A7    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A6    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A5    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A4    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A3    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A2    ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD|A1    ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; BCD       ; 16    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; COUNT0    ; 3     ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; DEL0      ; 16    ; 7              ; 0            ; 7              ; 1      ; 7               ; 7             ; 7               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; LFSR0     ; 2     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; FSM       ; 4     ; 0              ; 0            ; 0              ; 12     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; TICK1     ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-; TICK0     ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex9_partially_working/db/ex9.map.bpm b/part_2/ex9_partially_working/db/ex9.map.bpm
deleted file mode 100755
index d385b51..0000000
--- a/part_2/ex9_partially_working/db/ex9.map.bpm
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.map.cdb b/part_2/ex9_partially_working/db/ex9.map.cdb
deleted file mode 100755
index 5f3c85f..0000000
--- a/part_2/ex9_partially_working/db/ex9.map.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.map.hdb b/part_2/ex9_partially_working/db/ex9.map.hdb
deleted file mode 100755
index 36281c7..0000000
--- a/part_2/ex9_partially_working/db/ex9.map.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.map.kpt b/part_2/ex9_partially_working/db/ex9.map.kpt
deleted file mode 100755
index c47755c..0000000
--- a/part_2/ex9_partially_working/db/ex9.map.kpt
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.map.qmsg b/part_2/ex9_partially_working/db/ex9.map.qmsg
deleted file mode 100755
index 8989391..0000000
--- a/part_2/ex9_partially_working/db/ex9.map.qmsg
+++ /dev/null
@@ -1,76 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480073228337 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480073228339 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 11:27:07 2016 " "Processing started: Fri Nov 25 11:27:07 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480073228339 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073228339 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073228339 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480073228782 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480073228783 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237056 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237056 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "C:/New folder/ex9/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237058 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237058 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237059 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237059 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237061 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237061 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480073237062 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237062 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237062 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237064 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237064 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237064 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter_16.v(16) " "Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480073237067 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237067 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237067 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237068 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237068 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237069 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237070 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237070 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237071 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237071 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073237073 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237073 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "ex9 " "Elaborating entity \"ex9\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480073237102 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_50000 tick_50000:TICK0 " "Elaborating entity \"tick_50000\" for hierarchy \"tick_50000:TICK0\"" {  } { { "verilog_files/ex9.v" "TICK0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237110 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_2500 tick_2500:TICK1 " "Elaborating entity \"tick_2500\" for hierarchy \"tick_2500:TICK1\"" {  } { { "verilog_files/ex9.v" "TICK1" { Text "C:/New folder/ex9/verilog_files/ex9.v" 15 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237111 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "formula_fsm formula_fsm:FSM " "Elaborating entity \"formula_fsm\" for hierarchy \"formula_fsm:FSM\"" {  } { { "verilog_files/ex9.v" "FSM" { Text "C:/New folder/ex9/verilog_files/ex9.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237111 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "formula_fsm.v(37) " "Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 37 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1480073237112 "|ex9|formula_fsm:FSM"}
-{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "start_delay formula_fsm.v(47) " "Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable \"start_delay\", which holds its previous value in one or more paths through the always construct" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1480073237112 "|ex9|formula_fsm:FSM"}
-{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "start_delay formula_fsm.v(47) " "Inferred latch for \"start_delay\" at formula_fsm.v(47)" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 47 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073237112 "|ex9|formula_fsm:FSM"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LFSR LFSR:LFSR0 " "Elaborating entity \"LFSR\" for hierarchy \"LFSR:LFSR0\"" {  } { { "verilog_files/ex9.v" "LFSR0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237113 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay delay:DEL0 " "Elaborating entity \"delay\" for hierarchy \"delay:DEL0\"" {  } { { "verilog_files/ex9.v" "DEL0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 21 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237113 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 delay.v(24) " "Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14)" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1480073237114 "|ex9|delay:DEL0"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_16 counter_16:COUNT0 " "Elaborating entity \"counter_16\" for hierarchy \"counter_16:COUNT0\"" {  } { { "verilog_files/ex9.v" "COUNT0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 23 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237114 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:BCD " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:BCD\"" {  } { { "verilog_files/ex9.v" "BCD" { Text "C:/New folder/ex9/verilog_files/ex9.v" 25 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237120 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:BCD\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:BCD\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237121 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "verilog_files/ex9.v" "SEG0" { Text "C:/New folder/ex9/verilog_files/ex9.v" 27 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073237126 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480073237674 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[0\] GND " "Pin \"HEX5\[0\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[1\] GND " "Pin \"HEX5\[1\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[2\] GND " "Pin \"HEX5\[2\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[3\] GND " "Pin \"HEX5\[3\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[4\] GND " "Pin \"HEX5\[4\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[5\] GND " "Pin \"HEX5\[5\]\" is stuck at GND" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Pin \"HEX5\[6\]\" is stuck at VCC" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480073237828 "|ex9|HEX5[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480073237828 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480073237906 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1480073238213 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073238238 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480073238326 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480073238326 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480073238368 "|ex9|KEY[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "No output dependent on input pin \"KEY\[2\]\"" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 4 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480073238368 "|ex9|KEY[2]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480073238368 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "353 " "Implemented 353 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480073238369 ""} { "Info" "ICUT_CUT_TM_OPINS" "52 " "Implemented 52 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480073238369 ""} { "Info" "ICUT_CUT_TM_LCELLS" "296 " "Implemented 296 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480073238369 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480073238369 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073238382 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 11:27:18 2016 " "Processing ended: Fri Nov 25 11:27:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073238382 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073238382 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073238382 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073238382 ""}
diff --git a/part_2/ex9_partially_working/db/ex9.map.rdb b/part_2/ex9_partially_working/db/ex9.map.rdb
deleted file mode 100755
index 1f899bf..0000000
--- a/part_2/ex9_partially_working/db/ex9.map.rdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.map_bb.cdb b/part_2/ex9_partially_working/db/ex9.map_bb.cdb
deleted file mode 100755
index 3e660c7..0000000
--- a/part_2/ex9_partially_working/db/ex9.map_bb.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.map_bb.hdb b/part_2/ex9_partially_working/db/ex9.map_bb.hdb
deleted file mode 100755
index cc66873..0000000
--- a/part_2/ex9_partially_working/db/ex9.map_bb.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.pre_map.hdb b/part_2/ex9_partially_working/db/ex9.pre_map.hdb
deleted file mode 100755
index 951dff6..0000000
--- a/part_2/ex9_partially_working/db/ex9.pre_map.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.root_partition.map.reg_db.cdb b/part_2/ex9_partially_working/db/ex9.root_partition.map.reg_db.cdb
deleted file mode 100755
index 3bf7dd7..0000000
--- a/part_2/ex9_partially_working/db/ex9.root_partition.map.reg_db.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.routing.rdb b/part_2/ex9_partially_working/db/ex9.routing.rdb
deleted file mode 100755
index 0d9ff39..0000000
--- a/part_2/ex9_partially_working/db/ex9.routing.rdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.rtlv.hdb b/part_2/ex9_partially_working/db/ex9.rtlv.hdb
deleted file mode 100755
index 921d905..0000000
--- a/part_2/ex9_partially_working/db/ex9.rtlv.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.rtlv_sg.cdb b/part_2/ex9_partially_working/db/ex9.rtlv_sg.cdb
deleted file mode 100755
index 5c35259..0000000
--- a/part_2/ex9_partially_working/db/ex9.rtlv_sg.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.rtlv_sg_swap.cdb b/part_2/ex9_partially_working/db/ex9.rtlv_sg_swap.cdb
deleted file mode 100755
index 67d09aa..0000000
--- a/part_2/ex9_partially_working/db/ex9.rtlv_sg_swap.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.smp_dump.txt b/part_2/ex9_partially_working/db/ex9.smp_dump.txt
deleted file mode 100755
index 26e74f6..0000000
--- a/part_2/ex9_partially_working/db/ex9.smp_dump.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-
-State Machine - |ex9|delay:DEL0|state
-Name state.WAIT_LOW state.TIME_OUT state.COUNTING state.IDLE 
-state.IDLE 0 0 0 0 
-state.COUNTING 0 0 1 1 
-state.TIME_OUT 0 1 0 1 
-state.WAIT_LOW 1 0 0 1 
-
-State Machine - |ex9|formula_fsm:FSM|state
-Name state.WAIT_TRIGGER state.WAIT_FOR_TIMEOUT state.LIGHT_UP_LEDS 
-state.WAIT_TRIGGER 0 0 0 
-state.LIGHT_UP_LEDS 1 0 1 
-state.WAIT_FOR_TIMEOUT 1 1 0 
diff --git a/part_2/ex9_partially_working/db/ex9.sta.qmsg b/part_2/ex9_partially_working/db/ex9.sta.qmsg
deleted file mode 100755
index 9b5916c..0000000
--- a/part_2/ex9_partially_working/db/ex9.sta.qmsg
+++ /dev/null
@@ -1,53 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480073283247 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480073283248 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 11:28:02 2016 " "Processing started: Fri Nov 25 11:28:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480073283248 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283248 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex9 -c ex9 " "Command: quartus_sta ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283248 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073283369 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283915 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283915 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283963 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073283963 ""}
-{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284462 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex9.sdc " "Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284484 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284484 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT " "create_clock -period 1.000 -name tick_50000:TICK0\|CLK_OUT tick_50000:TICK0\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480073284486 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480073284486 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_2500:TICK1\|CLK_OUT tick_2500:TICK1\|CLK_OUT " "create_clock -period 1.000 -name tick_2500:TICK1\|CLK_OUT tick_2500:TICK1\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480073284486 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS " "create_clock -period 1.000 -name formula_fsm:FSM\|state.LIGHT_UP_LEDS formula_fsm:FSM\|state.LIGHT_UP_LEDS" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480073284486 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284486 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284488 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284498 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073284499 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073284507 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480073284527 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284527 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.063 " "Worst-case setup slack is -4.063" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.063             -92.490 CLOCK_50  " "   -4.063             -92.490 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.170            -100.678 tick_50000:TICK0\|CLK_OUT  " "   -3.170            -100.678 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.647             -14.530 tick_2500:TICK1\|CLK_OUT  " "   -1.647             -14.530 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.569              -1.569 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.569              -1.569 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284529 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284529 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -2.594 " "Worst-case hold slack is -2.594" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.594              -2.594 CLOCK_50  " "   -2.594              -2.594 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.279               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.279               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.351               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.351               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.556               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.556               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284532 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284532 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284534 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284535 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.746 " "Worst-case minimum pulse width slack is -0.746" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.746             -27.464 CLOCK_50  " "   -0.746             -27.464 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -24.429 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -24.429 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.270 tick_2500:TICK1\|CLK_OUT  " "   -0.394              -5.270 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.461               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.461               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073284537 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284537 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073284549 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073284584 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285483 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285543 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480073285550 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285550 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.620 " "Worst-case setup slack is -3.620" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.620             -88.501 CLOCK_50  " "   -3.620             -88.501 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.082             -96.216 tick_50000:TICK0\|CLK_OUT  " "   -3.082             -96.216 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.680             -14.714 tick_2500:TICK1\|CLK_OUT  " "   -1.680             -14.714 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.485              -1.485 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -1.485              -1.485 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285551 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285551 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -2.768 " "Worst-case hold slack is -2.768" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.768              -2.768 CLOCK_50  " "   -2.768              -2.768 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.282               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.282               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.351               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.351               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.430               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.430               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285554 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285554 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285556 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285557 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.788 " "Worst-case minimum pulse width slack is -0.788" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.788             -25.568 CLOCK_50  " "   -0.788             -25.568 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -24.417 tick_50000:TICK0\|CLK_OUT  " "   -0.394             -24.417 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.220 tick_2500:TICK1\|CLK_OUT  " "   -0.394              -5.220 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.471               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.471               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073285559 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285559 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073285570 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073285715 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286487 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286548 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480073286550 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286550 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.305 " "Worst-case setup slack is -3.305" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.305             -54.566 CLOCK_50  " "   -3.305             -54.566 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.630             -50.049 tick_50000:TICK0\|CLK_OUT  " "   -1.630             -50.049 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.087              -9.482 tick_2500:TICK1\|CLK_OUT  " "   -1.087              -9.482 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.488              -0.488 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.488              -0.488 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286552 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286552 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.523 " "Worst-case hold slack is -1.523" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.523              -1.523 CLOCK_50  " "   -1.523              -1.523 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.071              -0.328 tick_2500:TICK1\|CLK_OUT  " "   -0.071              -0.328 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.094               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.094               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.134               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.134               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286555 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286555 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286556 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286558 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.856 " "Worst-case minimum pulse width slack is -0.856" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.856             -19.710 CLOCK_50  " "   -0.856             -19.710 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.062               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.062               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.127               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.127               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.480               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.480               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286559 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286559 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480073286571 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286732 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480073286734 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286734 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.694 " "Worst-case setup slack is -2.694" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.694             -44.892 CLOCK_50  " "   -2.694             -44.892 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.427             -42.012 tick_50000:TICK0\|CLK_OUT  " "   -1.427             -42.012 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.980              -8.435 tick_2500:TICK1\|CLK_OUT  " "   -0.980              -8.435 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.386              -0.386 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "   -0.386              -0.386 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286736 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286736 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.553 " "Worst-case hold slack is -1.553" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.553              -1.553 CLOCK_50  " "   -1.553              -1.553 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.102              -0.665 tick_2500:TICK1\|CLK_OUT  " "   -0.102              -0.665 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.064               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.064               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.081               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.081               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286740 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286740 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286741 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286743 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.880 " "Worst-case minimum pulse width slack is -0.880" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.880             -23.155 CLOCK_50  " "   -0.880             -23.155 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.079               0.000 tick_50000:TICK0\|CLK_OUT  " "    0.079               0.000 tick_50000:TICK0\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135               0.000 tick_2500:TICK1\|CLK_OUT  " "    0.135               0.000 tick_2500:TICK1\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.483               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS  " "    0.483               0.000 formula_fsm:FSM\|state.LIGHT_UP_LEDS " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480073286744 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073286744 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073288288 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073288290 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1211 " "Peak virtual memory: 1211 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073288337 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 11:28:08 2016 " "Processing ended: Fri Nov 25 11:28:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073288337 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073288337 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073288337 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480073288337 ""}
diff --git a/part_2/ex9_partially_working/db/ex9.sta.rdb b/part_2/ex9_partially_working/db/ex9.sta.rdb
deleted file mode 100755
index ac225df..0000000
--- a/part_2/ex9_partially_working/db/ex9.sta.rdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb b/part_2/ex9_partially_working/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
deleted file mode 100755
index 0d0089d..0000000
--- a/part_2/ex9_partially_working/db/ex9.sta_cmp.6_slow_1100mv_85c.tdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_0c.ddb b/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_0c.ddb
deleted file mode 100755
index cdd150e..0000000
--- a/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_0c.ddb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_85c.ddb b/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_85c.ddb
deleted file mode 100755
index 416a1c9..0000000
--- a/part_2/ex9_partially_working/db/ex9.tiscmp.fast_1100mv_85c.ddb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_0c.ddb b/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_0c.ddb
deleted file mode 100755
index d97542e..0000000
--- a/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_0c.ddb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_85c.ddb b/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_85c.ddb
deleted file mode 100755
index f99fa51..0000000
--- a/part_2/ex9_partially_working/db/ex9.tiscmp.slow_1100mv_85c.ddb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/ex9.tmw_info b/part_2/ex9_partially_working/db/ex9.tmw_info
deleted file mode 100755
index 43e342c..0000000
--- a/part_2/ex9_partially_working/db/ex9.tmw_info
+++ /dev/null
@@ -1,6 +0,0 @@
-start_full_compilation:s:00:01:01
-start_analysis_synthesis:s:00:00:11-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:37-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
-start_timing_analyzer:s:00:00:06-start_full_compilation
diff --git a/part_2/ex9_partially_working/db/ex9.vpr.ammdb b/part_2/ex9_partially_working/db/ex9.vpr.ammdb
deleted file mode 100755
index b4a4021..0000000
--- a/part_2/ex9_partially_working/db/ex9.vpr.ammdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/db/prev_cmp_ex9.qmsg b/part_2/ex9_partially_working/db/prev_cmp_ex9.qmsg
deleted file mode 100755
index b29fc79..0000000
--- a/part_2/ex9_partially_working/db/prev_cmp_ex9.qmsg
+++ /dev/null
@@ -1,57 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480073206376 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480073206377 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 11:26:46 2016 " "Processing started: Fri Nov 25 11:26:46 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480073206377 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073206377 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073206378 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480073206841 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480073206841 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_50000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_50000 " "Found entity 1: tick_50000" {  } { { "verilog_files/tick_50000.v" "" { Text "C:/New folder/ex9/verilog_files/tick_50000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215181 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215181 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_2500.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_2500 " "Found entity 1: tick_2500" {  } { { "verilog_files/tick_2500.v" "" { Text "C:/New folder/ex9/verilog_files/tick_2500.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215183 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215183 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/lfsr.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v" { { "Info" "ISGN_ENTITY_NAME" "1 LFSR " "Found entity 1: LFSR" {  } { { "verilog_files/LFSR.v" "" { Text "C:/New folder/ex9/verilog_files/LFSR.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215184 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215184 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex9/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215186 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215186 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "formula_fsm.v(36) " "Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 36 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480073215187 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/formula_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 formula_fsm " "Found entity 1: formula_fsm" {  } { { "verilog_files/formula_fsm.v" "" { Text "C:/New folder/ex9/verilog_files/formula_fsm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215188 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215188 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "time_out TIME_OUT delay.v(7) " "Verilog HDL Declaration information at delay.v(7): object \"time_out\" differs only in case from object \"TIME_OUT\" in the same scope" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 7 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215189 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay " "Found entity 1: delay" {  } { { "verilog_files/delay.v" "" { Text "C:/New folder/ex9/verilog_files/delay.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215189 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215189 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "counter_16.v(16) " "Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 16 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1480073215191 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/counter_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_16 " "Found entity 1: counter_16" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215191 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215191 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215192 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215192 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215193 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215194 ""}
-{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480073215194 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex9/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215194 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215194 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex9/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215195 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215195 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ex9.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ex9.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex9 " "Found entity 1: ex9" {  } { { "verilog_files/ex9.v" "" { Text "C:/New folder/ex9/verilog_files/ex9.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480073215198 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215198 ""}
-{ "Error" "EVRFX_VERI_UNDEF_TOP_PORT" "reset counter_16.v(4) " "Verilog HDL Module Declaration error at counter_16.v(4): top module port \"reset\" is not found in the port list" {  } { { "verilog_files/counter_16.v" "" { Text "C:/New folder/ex9/verilog_files/counter_16.v" 4 0 0 } }  } 0 10206 "Verilog HDL Module Declaration error at %2!s!: top module port \"%1!s!\" is not found in the port list" 0 0 "Analysis & Synthesis" 0 -1 1480073215199 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex9/output_files/ex9.map.smsg " "Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215215 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "836 " "Peak virtual memory: 836 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073215249 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Nov 25 11:26:55 2016 " "Processing ended: Fri Nov 25 11:26:55 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073215249 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073215249 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073215249 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215249 ""}
-{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1  " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480073215850 ""}
diff --git a/part_2/ex9_partially_working/ex9.qws b/part_2/ex9_partially_working/ex9.qws
deleted file mode 100755
index 3d39dd3..0000000
--- a/part_2/ex9_partially_working/ex9.qws
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
deleted file mode 100755
index 84e2e20..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.ammdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
deleted file mode 100755
index b342ddc..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
deleted file mode 100755
index 7c6e4c6..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
deleted file mode 100755
index 91157f9..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
deleted file mode 100755
index c6a91c8..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
deleted file mode 100755
index 36c8945..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.rcfdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
deleted file mode 100755
index d39bf4a..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.dpi b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
deleted file mode 100755
index 6e90988..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.dpi
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
deleted file mode 100755
index b94502f..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
deleted file mode 100755
index ef311d3..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.kpt b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
deleted file mode 100755
index 0ea1881..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.kpt
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
deleted file mode 100755
index 59e07ca..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
deleted file mode 100755
index aec68a5..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.olm.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
deleted file mode 100755
index 84a30b9..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.oln.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
deleted file mode 100755
index 59e07ca..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orf.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
deleted file mode 100755
index 1490a08..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orm.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
deleted file mode 100755
index 3d14455..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.orn.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
deleted file mode 100755
index d39bf4a..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
deleted file mode 100755
index b94502f..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hbdb.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
deleted file mode 100755
index ef311d3..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
deleted file mode 100755
index 0ea1881..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.rrp.kpt
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrp.hdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrp.hdb
deleted file mode 100755
index 4ff0730..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrp.hdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrs.cdb b/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrs.cdb
deleted file mode 100755
index 7c2db17..0000000
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.rrs.cdb
+++ /dev/null
diff --git a/part_2/ex9_partially_working/output_files/ex9.done b/part_2/ex9_partially_working/output_files/ex9.done
deleted file mode 100755
index 893cd81..0000000
--- a/part_2/ex9_partially_working/output_files/ex9.done
+++ /dev/null
@@ -1 +0,0 @@
-Fri Nov 25 11:28:09 2016
diff --git a/part_2/ex9_partially_working/output_files/ex9.jdi b/part_2/ex9_partially_working/output_files/ex9.jdi
deleted file mode 100755
index 98be503..0000000
--- a/part_2/ex9_partially_working/output_files/ex9.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="a5a1d44468e3c5ecef42"/>
-  </project>
-  <file_info>
-    <file device="5CSEMA5F31C6" path="ex9.sof" usercode="0xFFFFFFFF"/>
-  </file_info>
-</sld_project_info>
diff --git a/part_2/ex9_partially_working/output_files/ex9.map.rpt b/part_2/ex9_partially_working/output_files/ex9.map.rpt
deleted file mode 100755
index ce355a7..0000000
--- a/part_2/ex9_partially_working/output_files/ex9.map.rpt
+++ /dev/null
@@ -1,629 +0,0 @@
-Analysis & Synthesis report for ex9
-Fri Nov 25 11:27:18 2016
-Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. State Machine - |ex9|delay:DEL0|state
-  9. State Machine - |ex9|formula_fsm:FSM|state
- 10. User-Specified and Inferred Latches
- 11. Registers Removed During Synthesis
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: tick_50000:TICK0
- 16. Parameter Settings for User Entity Instance: tick_2500:TICK1
- 17. Parameter Settings for User Entity Instance: formula_fsm:FSM
- 18. Parameter Settings for User Entity Instance: delay:DEL0
- 19. Parameter Settings for User Entity Instance: counter_16:COUNT0
- 20. Port Connectivity Checks: "hex_to_7seg:SEG5"
- 21. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"
- 22. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19"
- 23. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10"
- 24. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4"
- 25. Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1"
- 26. Port Connectivity Checks: "delay:DEL0"
- 27. Post-Synthesis Netlist Statistics for Top Partition
- 28. Elapsed Time Per Partition
- 29. Analysis & Synthesis Messages
- 30. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Altera and sold by Altera or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                      ;
-+---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status     ; Successful - Fri Nov 25 11:27:18 2016           ;
-; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
-; Family                          ; Cyclone V                                       ;
-; Logic utilization (in ALMs)     ; N/A                                             ;
-; Total registers                 ; 85                                              ;
-; Total pins                      ; 57                                              ;
-; Total virtual pins              ; 0                                               ;
-; Total block memory bits         ; 0                                               ;
-; Total DSP Blocks                ; 0                                               ;
-; Total HSSI RX PCSs              ; 0                                               ;
-; Total HSSI PMA RX Deserializers ; 0                                               ;
-; Total HSSI TX PCSs              ; 0                                               ;
-; Total HSSI PMA TX Serializers   ; 0                                               ;
-; Total PLLs                      ; 0                                               ;
-; Total DLLs                      ; 0                                               ;
-+---------------------------------+-------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                             ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                          ; Setting            ; Default Value      ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
-; Top-level entity name                                                           ; ex9                ; ex9                ;
-; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
-; Use smart compilation                                                           ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
-; Enable compact report table                                                     ; Off                ; Off                ;
-; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
-; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
-; Preserve fewer node names                                                       ; On                 ; On                 ;
-; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
-; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
-; State Machine Processing                                                        ; Auto               ; Auto               ;
-; Safe State Machine                                                              ; Off                ; Off                ;
-; Extract Verilog State Machines                                                  ; On                 ; On                 ;
-; Extract VHDL State Machines                                                     ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
-; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
-; Parallel Synthesis                                                              ; On                 ; On                 ;
-; DSP Block Balancing                                                             ; Auto               ; Auto               ;
-; NOT Gate Push-Back                                                              ; On                 ; On                 ;
-; Power-Up Don't Care                                                             ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
-; Remove Duplicate Registers                                                      ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
-; Optimization Technique                                                          ; Balanced           ; Balanced           ;
-; Carry Chain Length                                                              ; 70                 ; 70                 ;
-; Auto Carry Chains                                                               ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
-; Auto ROM Replacement                                                            ; On                 ; On                 ;
-; Auto RAM Replacement                                                            ; On                 ; On                 ;
-; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
-; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
-; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
-; Strict RAM Replacement                                                          ; Off                ; Off                ;
-; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
-; Auto Resource Sharing                                                           ; Off                ; Off                ;
-; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
-; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
-; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
-; Report Parameter Settings                                                       ; On                 ; On                 ;
-; Report Source Assignments                                                       ; On                 ; On                 ;
-; Report Connectivity Checks                                                      ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
-; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
-; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
-; HDL message level                                                               ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
-; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
-; Clock MUX Protection                                                            ; On                 ; On                 ;
-; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
-; Block Design Naming                                                             ; Auto               ; Auto               ;
-; SDC constraint protection                                                       ; Off                ; Off                ;
-; Synthesis Effort                                                                ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
-; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
-; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
-; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
-; Synthesis Seed                                                                  ; 1                  ; 1                  ;
-; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
-; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation                     ;
-+----------------------------+-------------+
-; Processors                 ; Number      ;
-+----------------------------+-------------+
-; Number detected on machine ; 8           ;
-; Maximum allowed            ; 4           ;
-;                            ;             ;
-; Average used               ; 1.00        ;
-; Maximum used               ; 4           ;
-;                            ;             ;
-; Usage by Processor         ; % Time Used ;
-;     Processor 1            ; 100.0%      ;
-;     Processors 2-4         ;   0.0%      ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ; Library ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-; verilog_files/tick_50000.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/tick_50000.v  ;         ;
-; verilog_files/tick_2500.v        ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/tick_2500.v   ;         ;
-; verilog_files/LFSR.v             ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/LFSR.v        ;         ;
-; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/hex_to_7seg.v ;         ;
-; verilog_files/formula_fsm.v      ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/formula_fsm.v ;         ;
-; verilog_files/delay.v            ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/delay.v       ;         ;
-; verilog_files/counter_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/counter_16.v  ;         ;
-; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/bin2bcd_16.v  ;         ;
-; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/add3_ge5.v    ;         ;
-; verilog_files/ex9.v              ; yes             ; User Verilog HDL File  ; C:/New folder/ex9/verilog_files/ex9.v         ;         ;
-+----------------------------------+-----------------+------------------------+-----------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary                            ;
-+---------------------------------------------+--------------------------+
-; Resource                                    ; Usage                    ;
-+---------------------------------------------+--------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 156                      ;
-;                                             ;                          ;
-; Combinational ALUT usage for logic          ; 287                      ;
-;     -- 7 input functions                    ; 0                        ;
-;     -- 6 input functions                    ; 23                       ;
-;     -- 5 input functions                    ; 14                       ;
-;     -- 4 input functions                    ; 150                      ;
-;     -- <=3 input functions                  ; 100                      ;
-;                                             ;                          ;
-; Dedicated logic registers                   ; 85                       ;
-;                                             ;                          ;
-; I/O pins                                    ; 57                       ;
-;                                             ;                          ;
-; Total DSP Blocks                            ; 0                        ;
-;                                             ;                          ;
-; Maximum fan-out node                        ; tick_50000:TICK0|CLK_OUT ;
-; Maximum fan-out                             ; 58                       ;
-; Total fan-out                               ; 1369                     ;
-; Average fan-out                             ; 2.82                     ;
-+---------------------------------------------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                  ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9                       ; 287 (1)           ; 85 (0)       ; 0                 ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
-;    |LFSR:LFSR0|            ; 3 (3)             ; 7 (7)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 124 (0)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A10|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A1|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A32|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
-;       |add3_ge5:A33|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:COUNT0|     ; 17 (17)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
-;    |delay:DEL0|            ; 22 (22)           ; 18 (18)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 16 (16)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
-;    |tick_2500:TICK1|       ; 27 (27)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_2500:TICK1             ; tick_2500   ; work         ;
-;    |tick_50000:TICK0|      ; 36 (36)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+-------------------+--------------+-------------------+------------+------+--------------+----------------------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------+
-; State Machine - |ex9|delay:DEL0|state                                          ;
-+----------------+----------------+----------------+----------------+------------+
-; Name           ; state.WAIT_LOW ; state.TIME_OUT ; state.COUNTING ; state.IDLE ;
-+----------------+----------------+----------------+----------------+------------+
-; state.IDLE     ; 0              ; 0              ; 0              ; 0          ;
-; state.COUNTING ; 0              ; 0              ; 1              ; 1          ;
-; state.TIME_OUT ; 0              ; 1              ; 0              ; 1          ;
-; state.WAIT_LOW ; 1              ; 0              ; 0              ; 1          ;
-+----------------+----------------+----------------+----------------+------------+
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------------------+
-; State Machine - |ex9|formula_fsm:FSM|state                                                 ;
-+------------------------+--------------------+------------------------+---------------------+
-; Name                   ; state.WAIT_TRIGGER ; state.WAIT_FOR_TIMEOUT ; state.LIGHT_UP_LEDS ;
-+------------------------+--------------------+------------------------+---------------------+
-; state.WAIT_TRIGGER     ; 0                  ; 0                      ; 0                   ;
-; state.LIGHT_UP_LEDS    ; 1                  ; 0                      ; 1                   ;
-; state.WAIT_FOR_TIMEOUT ; 1                  ; 1                      ; 0                   ;
-+------------------------+--------------------+------------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches                                                                               ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; Latch Name                                         ; Latch Enable Signal                 ; Free of Timing Hazards ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-; formula_fsm:FSM|start_delay                        ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; yes                    ;
-; Number of user-specified and inferred latches = 1  ;                                     ;                        ;
-+----------------------------------------------------+-------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------+
-; Registers Removed During Synthesis                         ;
-+---------------------------------------+--------------------+
-; Register name                         ; Reason for Removal ;
-+---------------------------------------+--------------------+
-; delay:DEL0|state~5                    ; Lost fanout        ;
-; delay:DEL0|state~6                    ; Lost fanout        ;
-; Total Number of Removed Registers = 2 ;                    ;
-+---------------------------------------+--------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 85    ;
-; Number of registers using Synchronous Clear  ; 16    ;
-; Number of registers using Synchronous Load   ; 15    ;
-; Number of registers using Asynchronous Clear ; 0     ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 48    ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+---------------------------------------------------+
-; Inverted Register Statistics                      ;
-+-----------------------------------------+---------+
-; Inverted Register                       ; Fan out ;
-+-----------------------------------------+---------+
-; tick_50000:TICK0|count[14]              ; 2       ;
-; tick_50000:TICK0|count[15]              ; 2       ;
-; tick_50000:TICK0|count[0]               ; 2       ;
-; tick_50000:TICK0|count[1]               ; 2       ;
-; tick_50000:TICK0|count[2]               ; 2       ;
-; tick_50000:TICK0|count[3]               ; 2       ;
-; tick_50000:TICK0|count[6]               ; 2       ;
-; tick_50000:TICK0|count[8]               ; 2       ;
-; tick_50000:TICK0|count[9]               ; 2       ;
-; tick_2500:TICK1|count[11]               ; 8       ;
-; tick_2500:TICK1|count[0]                ; 2       ;
-; tick_2500:TICK1|count[1]                ; 2       ;
-; tick_2500:TICK1|count[6]                ; 2       ;
-; tick_2500:TICK1|count[7]                ; 2       ;
-; tick_2500:TICK1|count[8]                ; 2       ;
-; LFSR:LFSR0|COUNT[1]                     ; 3       ;
-; Total number of inverted registers = 16 ;         ;
-+-----------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-; 3:1                ; 16 bits   ; 32 LEs        ; 0 LEs                ; 32 LEs                 ; Yes        ; |ex9|counter_16:COUNT0|count[1] ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[1]        ;
-; 5:1                ; 7 bits    ; 21 LEs        ; 7 LEs                ; 14 LEs                 ; Yes        ; |ex9|delay:DEL0|count[11]       ;
-; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex9|formula_fsm:FSM|Selector4  ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; No         ; |ex9|delay:DEL0|Selector16      ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |ex9|delay:DEL0|Selector17      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_50000:TICK0 ;
-+----------------+-------+--------------------------------------+
-; Parameter Name ; Value ; Type                                 ;
-+----------------+-------+--------------------------------------+
-; NBIT           ; 16    ; Signed Integer                       ;
-+----------------+-------+--------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: tick_2500:TICK1 ;
-+----------------+-------+-------------------------------------+
-; Parameter Name ; Value ; Type                                ;
-+----------------+-------+-------------------------------------+
-; NBIT           ; 12    ; Signed Integer                      ;
-+----------------+-------+-------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: formula_fsm:FSM ;
-+------------------+-------+-----------------------------------+
-; Parameter Name   ; Value ; Type                              ;
-+------------------+-------+-----------------------------------+
-; WAIT_TRIGGER     ; 00    ; Unsigned Binary                   ;
-; LIGHT_UP_LEDS    ; 01    ; Unsigned Binary                   ;
-; WAIT_FOR_TIMEOUT ; 10    ; Unsigned Binary                   ;
-+------------------+-------+-----------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------+
-; Parameter Settings for User Entity Instance: delay:DEL0 ;
-+----------------+-------+--------------------------------+
-; Parameter Name ; Value ; Type                           ;
-+----------------+-------+--------------------------------+
-; BIT_SZ         ; 14    ; Signed Integer                 ;
-; IDLE           ; 00    ; Unsigned Binary                ;
-; COUNTING       ; 01    ; Unsigned Binary                ;
-; TIME_OUT       ; 10    ; Unsigned Binary                ;
-; WAIT_LOW       ; 11    ; Unsigned Binary                ;
-+----------------+-------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: counter_16:COUNT0 ;
-+----------------+-------+---------------------------------------+
-; Parameter Name ; Value ; Type                                  ;
-+----------------+-------+---------------------------------------+
-; BIT_SZ         ; 16    ; Signed Integer                        ;
-; COUNTING       ; 1     ; Unsigned Binary                       ;
-; IDLE           ; 0     ; Unsigned Binary                       ;
-+----------------+-------+---------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------+
-; Port Connectivity Checks: "hex_to_7seg:SEG5" ;
-+------+-------+----------+--------------------+
-; Port ; Type  ; Severity ; Details            ;
-+------+-------+----------+--------------------+
-; in   ; Input ; Info     ; Stuck at GND       ;
-+------+-------+----------+--------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A31"                                                         ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; Port  ; Type   ; Severity ; Details                                                                             ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-; iW[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
-; oA[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A19" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+---------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A10" ;
-+-------+-------+----------+------------------------------+
-; Port  ; Type  ; Severity ; Details                      ;
-+-------+-------+----------+------------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                 ;
-+-------+-------+----------+------------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A4" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+--------------------------------------------------------+
-; Port Connectivity Checks: "bin2bcd_16:BCD|add3_ge5:A1" ;
-+-------+-------+----------+-----------------------------+
-; Port  ; Type  ; Severity ; Details                     ;
-+-------+-------+----------+-----------------------------+
-; iW[3] ; Input ; Info     ; Stuck at GND                ;
-+-------+-------+----------+-----------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "delay:DEL0"                                                                                                                                ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type  ; Severity ; Details                                                                                                                                     ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; N    ; Input ; Warning  ; Input port expression (7 bits) is smaller than the input port (14 bits) it drives.  Extra input bit(s) "N[13..7]" will be connected to GND. ;
-+------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type                  ; Count                       ;
-+-----------------------+-----------------------------+
-; arriav_ff             ; 85                          ;
-;     ENA               ; 18                          ;
-;     ENA SCLR          ; 16                          ;
-;     ENA SLD           ; 14                          ;
-;     SLD               ; 1                           ;
-;     plain             ; 36                          ;
-; arriav_lcell_comb     ; 305                         ;
-;     arith             ; 58                          ;
-;         1 data inputs ; 58                          ;
-;     normal            ; 247                         ;
-;         0 data inputs ; 2                           ;
-;         1 data inputs ; 34                          ;
-;         2 data inputs ; 6                           ;
-;         3 data inputs ; 18                          ;
-;         4 data inputs ; 150                         ;
-;         5 data inputs ; 14                          ;
-;         6 data inputs ; 23                          ;
-; boundary_port         ; 57                          ;
-;                       ;                             ;
-; Max LUT depth         ; 15.00                       ;
-; Average LUT depth     ; 7.36                        ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition    ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top            ; 00:00:00     ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
-    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Fri Nov 25 11:27:07 2016
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_50000.v
-    Info (12023): Found entity 1: tick_50000 File: C:/New folder/ex9/verilog_files/tick_50000.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_2500.v
-    Info (12023): Found entity 1: tick_2500 File: C:/New folder/ex9/verilog_files/tick_2500.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/lfsr.v
-    Info (12023): Found entity 1: LFSR File: C:/New folder/ex9/verilog_files/LFSR.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
-    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex9/verilog_files/hex_to_7seg.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/formula_fsm.v
-    Info (12023): Found entity 1: formula_fsm File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay.v
-    Info (12023): Found entity 1: delay File: C:/New folder/ex9/verilog_files/delay.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/counter_16.v
-    Info (12023): Found entity 1: counter_16 File: C:/New folder/ex9/verilog_files/counter_16.v Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
-    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 12
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
-    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex9/verilog_files/add3_ge5.v Line: 9
-Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ex9.v
-    Info (12023): Found entity 1: ex9 File: C:/New folder/ex9/verilog_files/ex9.v Line: 1
-Info (12127): Elaborating entity "ex9" for the top level hierarchy
-Info (12128): Elaborating entity "tick_50000" for hierarchy "tick_50000:TICK0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 14
-Info (12128): Elaborating entity "tick_2500" for hierarchy "tick_2500:TICK1" File: C:/New folder/ex9/verilog_files/ex9.v Line: 15
-Info (12128): Elaborating entity "formula_fsm" for hierarchy "formula_fsm:FSM" File: C:/New folder/ex9/verilog_files/ex9.v Line: 17
-Info (10264): Verilog HDL Case Statement information at formula_fsm.v(37): all case item expressions in this case statement are onehot File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 37
-Warning (10240): Verilog HDL Always Construct warning at formula_fsm.v(47): inferring latch(es) for variable "start_delay", which holds its previous value in one or more paths through the always construct File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 47
-Info (10041): Inferred latch for "start_delay" at formula_fsm.v(47) File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 47
-Info (12128): Elaborating entity "LFSR" for hierarchy "LFSR:LFSR0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 19
-Info (12128): Elaborating entity "delay" for hierarchy "delay:DEL0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 21
-Warning (10230): Verilog HDL assignment warning at delay.v(24): truncated value with size 32 to match size of target (14) File: C:/New folder/ex9/verilog_files/delay.v Line: 24
-Info (12128): Elaborating entity "counter_16" for hierarchy "counter_16:COUNT0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 23
-Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:BCD" File: C:/New folder/ex9/verilog_files/ex9.v Line: 25
-Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:BCD|add3_ge5:A1" File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 26
-Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex9/verilog_files/ex9.v Line: 27
-Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
-    Warning (13410): Pin "HEX5[0]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[1]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[2]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[3]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[4]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[5]" is stuck at GND File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-    Warning (13410): Pin "HEX5[6]" is stuck at VCC File: C:/New folder/ex9/verilog_files/ex9.v Line: 6
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 2 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file C:/New folder/ex9/output_files/ex9.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
-    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 2 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "KEY[1]" File: C:/New folder/ex9/verilog_files/ex9.v Line: 4
-    Warning (15610): No output dependent on input pin "KEY[2]" File: C:/New folder/ex9/verilog_files/ex9.v Line: 4
-Info (21057): Implemented 353 device resources after synthesis - the final resource count might be different
-    Info (21058): Implemented 5 input pins
-    Info (21059): Implemented 52 output pins
-    Info (21061): Implemented 296 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 15 warnings
-    Info: Peak virtual memory: 896 megabytes
-    Info: Processing ended: Fri Nov 25 11:27:18 2016
-    Info: Elapsed time: 00:00:11
-    Info: Total CPU time (on all processors): 00:00:21
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in C:/New folder/ex9/output_files/ex9.map.smsg.
-
-
diff --git a/part_2/ex9_partially_working/output_files/ex9.sta.summary b/part_2/ex9_partially_working/output_files/ex9.sta.summary
deleted file mode 100755
index 18cd1d8..0000000
--- a/part_2/ex9_partially_working/output_files/ex9.sta.summary
+++ /dev/null
@@ -1,197 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -4.063
-TNS   : -92.490
-
-Type  : Slow 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.170
-TNS   : -100.678
-
-Type  : Slow 1100mV 85C Model Setup 'tick_2500:TICK1|CLK_OUT'
-Slack : -1.647
-TNS   : -14.530
-
-Type  : Slow 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.569
-TNS   : -1.569
-
-Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : -2.594
-TNS   : -2.594
-
-Type  : Slow 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.279
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'tick_2500:TICK1|CLK_OUT'
-Slack : 0.351
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.556
-TNS   : 0.000
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.746
-TNS   : -27.464
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -24.429
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'
-Slack : -0.394
-TNS   : -5.270
-
-Type  : Slow 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.461
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -3.620
-TNS   : -88.501
-
-Type  : Slow 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -3.082
-TNS   : -96.216
-
-Type  : Slow 1100mV 0C Model Setup 'tick_2500:TICK1|CLK_OUT'
-Slack : -1.680
-TNS   : -14.714
-
-Type  : Slow 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -1.485
-TNS   : -1.485
-
-Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : -2.768
-TNS   : -2.768
-
-Type  : Slow 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.282
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'tick_2500:TICK1|CLK_OUT'
-Slack : 0.351
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.430
-TNS   : 0.000
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.788
-TNS   : -25.568
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : -0.394
-TNS   : -24.417
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'
-Slack : -0.394
-TNS   : -5.220
-
-Type  : Slow 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.471
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -3.305
-TNS   : -54.566
-
-Type  : Fast 1100mV 85C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.630
-TNS   : -50.049
-
-Type  : Fast 1100mV 85C Model Setup 'tick_2500:TICK1|CLK_OUT'
-Slack : -1.087
-TNS   : -9.482
-
-Type  : Fast 1100mV 85C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.488
-TNS   : -0.488
-
-Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : -1.523
-TNS   : -1.523
-
-Type  : Fast 1100mV 85C Model Hold 'tick_2500:TICK1|CLK_OUT'
-Slack : -0.071
-TNS   : -0.328
-
-Type  : Fast 1100mV 85C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.094
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.134
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.856
-TNS   : -19.710
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.062
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'
-Slack : 0.127
-TNS   : 0.000
-
-Type  : Fast 1100mV 85C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.480
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -2.694
-TNS   : -44.892
-
-Type  : Fast 1100mV 0C Model Setup 'tick_50000:TICK0|CLK_OUT'
-Slack : -1.427
-TNS   : -42.012
-
-Type  : Fast 1100mV 0C Model Setup 'tick_2500:TICK1|CLK_OUT'
-Slack : -0.980
-TNS   : -8.435
-
-Type  : Fast 1100mV 0C Model Setup 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : -0.386
-TNS   : -0.386
-
-Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : -1.553
-TNS   : -1.553
-
-Type  : Fast 1100mV 0C Model Hold 'tick_2500:TICK1|CLK_OUT'
-Slack : -0.102
-TNS   : -0.665
-
-Type  : Fast 1100mV 0C Model Hold 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.064
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Hold 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.081
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -0.880
-TNS   : -23.155
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_50000:TICK0|CLK_OUT'
-Slack : 0.079
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_2500:TICK1|CLK_OUT'
-Slack : 0.135
-TNS   : 0.000
-
-Type  : Fast 1100mV 0C Model Minimum Pulse Width 'formula_fsm:FSM|state.LIGHT_UP_LEDS'
-Slack : 0.483
-TNS   : 0.000
-
-------------------------------------------------------------
diff --git a/part_2/ex9_partially_working/verilog_files/LFSR.v b/part_2/ex9_partially_working/verilog_files/LFSR.v
deleted file mode 100755
index 46140b2..0000000
--- a/part_2/ex9_partially_working/verilog_files/LFSR.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module LFSR(CLK, en, COUNT);
-
-	input CLK;
-	input en;
-	
-	output [7:1] COUNT;
-	
-	reg [7:1] COUNT;
-	initial COUNT = 7'd1;
-		
-	always @ (posedge CLK)
-		if(en == 1'b1)
-			COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
-		else
-			COUNT <= COUNT;
-		
-endmodule
-	
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/LFSR.v.bak b/part_2/ex9_partially_working/verilog_files/LFSR.v.bak
deleted file mode 100755
index 89ec82a..0000000
--- a/part_2/ex9_partially_working/verilog_files/LFSR.v.bak
+++ /dev/null
@@ -1,11 +0,0 @@
-module LFSR(CLK, COUNT);
-	input CLK;
-	output[7:1] COUNT;
-	reg[7:1] COUNT;
-	initial COUNT = 7'd1;
-		
-	always @ (posedge CLK)
-		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
-		
-endmodule
-	
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/add3_ge5.v b/part_2/ex9_partially_working/verilog_files/add3_ge5.v
deleted file mode 100755
index a3cd6a9..0000000
--- a/part_2/ex9_partially_working/verilog_files/add3_ge5.v
+++ /dev/null
@@ -1,34 +0,0 @@
-//------------------------------
-// Module name: add3_ge5
-// Function: Add 3 to input if it is 5 or above
-// Creator:  Peter Cheung
-// Version:  1.0
-// Date:     21 Jan 2014
-//------------------------------
-
-module add3_ge5(iW,oA);
-
- input [3:0] iW; 
- output reg [3:0] oA;  
- 
-	always @ (iW)
-		case (iW) 
-		//****** input <5, pass to output unchanged ******
-			4'b0000: oA <= 4'b0000; 
-			4'b0001: oA <= 4'b0001; 
-			4'b0010: oA <= 4'b0010; 
-			4'b0011: oA <= 4'b0011; 
-			4'b0100: oA <= 4'b0100;
-			
-		//****** input >=5, output = input + 3	******	
-			4'b0101: oA <= 4'b1000; 
-			4'b0110: oA <= 4'b1001; 
-			4'b0111: oA <= 4'b1010; 
-			4'b1000: oA <= 4'b1011; 
-			4'b1001: oA <= 4'b1100;
-			4'b1010: oA <= 4'b1101;	
-			4'b1011: oA <= 4'b1110;	
-			4'b1100: oA <= 4'b1111;	
-			default: oA <= 4'b0000; // oA cannot be 13 or larger, else overflow
-		endcase 
-endmodule
diff --git a/part_2/ex9_partially_working/verilog_files/counter_16.v b/part_2/ex9_partially_working/verilog_files/counter_16.v
deleted file mode 100755
index 79c144c..0000000
--- a/part_2/ex9_partially_working/verilog_files/counter_16.v
+++ /dev/null
@@ -1,31 +0,0 @@
-module counter_16(clock, start, stop, count);
-
-	parameter BIT_SZ = 16;
-	input clock, start, stop;
-	output [BIT_SZ-1:0] count;
-	
-	reg [BIT_SZ-1:0] count;
-	
-	reg state;
-	
-	parameter COUNTING = 1'b1, IDLE = 1'b0;
-	
-	initial count = 0;
-	initial state = IDLE;
-	
-	always @ (posedge clock)
-		case(state)
-			IDLE:
-				if(start == 1'b1)
-					begin
-						count = 0;
-						state = COUNTING;
-					end
-			COUNTING:
-				if(stop == 1'b1)
-					state <= IDLE;
-				else
-					count <= count + 1'b1;
-		endcase
-			
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/counter_16.v.bak b/part_2/ex9_partially_working/verilog_files/counter_16.v.bak
deleted file mode 100755
index c0ec549..0000000
--- a/part_2/ex9_partially_working/verilog_files/counter_16.v.bak
+++ /dev/null
@@ -1,21 +0,0 @@
-`timescale 1ns / 100ps
-
-module counter_16(clock,enable,reset,count);
-
-	parameter BIT_SZ = 16;
-	input clock, enable, reset;
-	output [BIT_SZ-1:0] count;
-	
-	reg [BIT_SZ-1:0] count;
-	
-	initial count = 0;
-	
-	always @ (posedge clock)
-		begin
-			if(enable == 1'b1)
-				count <= count + 1'b1;
-			if(reset == 1'b1)
-				count <= 16'b0;
-		end
-			
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/delay.v b/part_2/ex9_partially_working/verilog_files/delay.v
deleted file mode 100755
index a983085..0000000
--- a/part_2/ex9_partially_working/verilog_files/delay.v
+++ /dev/null
@@ -1,60 +0,0 @@
-module delay(clk, N, trigger, time_out);
-
-	parameter BIT_SZ = 14;
-
-	input clk, trigger;
-	input [BIT_SZ-1:0] N;
-	output time_out;
-
-	reg[BIT_SZ-1:0] count;
-	reg time_out;
-
-	reg [1:0] state;
-
-	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
-
-	initial begin
-		state = IDLE;
-	end
-	
-	always @ (posedge clk)
-		case(state)
-			IDLE: if(trigger == 1'b1)
-				begin
-					count <= N*128;
-					state <= COUNTING;
-				end
-			COUNTING: 
-				begin
-					if(count == 1'b0)
-						begin
-							state <= TIME_OUT;
-						end
-					else 
-						count <= count - 1'b1;
-				end
-			TIME_OUT: 
-				begin
-					if(trigger == 1'b0)
-						state <= IDLE;
-					else
-						state <= WAIT_LOW;
-				end
-			WAIT_LOW: 
-				if(trigger == 1'b0)
-					state <= IDLE;
-			default: ;
-		endcase
-		
-	always @ (*)
-		case(state)
-			IDLE:
-					time_out = 1'b0;
-			COUNTING: 
-					time_out = 1'b0;
-			TIME_OUT: time_out = 1'b1;
-			WAIT_LOW: time_out = 1'b0;
-			default: ;
-		endcase
-
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/delay.v.bak b/part_2/ex9_partially_working/verilog_files/delay.v.bak
deleted file mode 100755
index 7b79342..0000000
--- a/part_2/ex9_partially_working/verilog_files/delay.v.bak
+++ /dev/null
@@ -1,47 +0,0 @@
-module delay(clk, N, trigger, time_out);
-
-	parameter BIT_SZ = 7
-
-	input clk, trigger;
-	input [BIT_SZ-1:0] N;
-	output time_out;
-
-	reg[BIT_SZ-1:0] count;
-	reg time_out;
-
-	reg [1:0] state;
-
-	parameter IDLE = 2'b0, COUNTING = 2'b1, TIME_OUT = 2'b10, WAIT_LOW = 2'b11;
-
-	initial begin
-		state = IDLE;
-		count = N-1'b1;
-	end
-	
-	always @ (posedge clk)
-		case(state)
-			IDLE: if(trigger == 1'b1)
-					state <= COUNTING;
-			COUNTING: if(count == 1'b0) begin
-					count <= n - 1'b1;
-					state <= TIME_OUT;
-				end
-			TIME_OUT: if(trigger == 1'b0)
-					state <= IDLE;
-				else
-					state <= WAIT_LOW;
-			WAIT_LOW: if(trigger == 1'b0)
-					state <= IDLE;
-			defualt: ;
-		endcase
-		
-	always @ (*)
-		case(state)
-			IDLE: time_out = 1'b0;
-			COUNTING: time_out = 1'b0;
-			TIME_OUT: time_out = 1'b1;
-			WAIT_LOW: time_out = 1'b0;
-			default: ;
-		endcase
-
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/ex8.v b/part_2/ex9_partially_working/verilog_files/ex8.v
deleted file mode 100755
index 6ca51d6..0000000
--- a/part_2/ex9_partially_working/verilog_files/ex8.v
+++ /dev/null
@@ -1,23 +0,0 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
-	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/ex8.v.bak b/part_2/ex9_partially_working/verilog_files/ex8.v.bak
deleted file mode 100755
index ac293e7..0000000
--- a/part_2/ex9_partially_working/verilog_files/ex8.v.bak
+++ /dev/null
@@ -1 +0,0 @@
-module ex8(
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/ex9.v b/part_2/ex9_partially_working/verilog_files/ex9.v
deleted file mode 100755
index 81aa0f9..0000000
--- a/part_2/ex9_partially_working/verilog_files/ex9.v
+++ /dev/null
@@ -1,34 +0,0 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire [3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	wire [15:0] count_out;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
-	
-	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	
-	counter_16 COUNT0(tick_ms, time_out, ~KEY[0], count_out);
-	
-	bin2bcd_16 BCD(count_out, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	hex_to_7seg SEG3(HEX3, BCD_3);
-	hex_to_7seg SEG4(HEX4, BCD_4);
-	hex_to_7seg SEG5(HEX5, 4'b0);
-	
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/ex9.v.bak b/part_2/ex9_partially_working/verilog_files/ex9.v.bak
deleted file mode 100755
index 6ca51d6..0000000
--- a/part_2/ex9_partially_working/verilog_files/ex9.v.bak
+++ /dev/null
@@ -1,23 +0,0 @@
-module ex9(CLOCK_50, KEY, HEX0, HEX1, HEX2, LEDR);
-	
-	input CLOCK_50;
-	input [3:0] KEY;
-	output [9:0] LEDR;
-	output [6:0] HEX0, HEX1, HEX2;
-	
-	wire tick_ms, tick_hs, time_out, start_delay, en_lfsr;
-	wire [6:0] N;
-	wire [6:0] bcd_to_hex;
-	wire[3:0] BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;
-	
-	tick_50000 TICK0(CLOCK_50, tick_ms);
-	tick_2500 TICK1(CLOCK_50, tick_ms, tick_hs);
-	formula_fsm FSM(tick_ms, tick_hs, ~KEY[3], time_out, en_lfsr, start_delay, LEDR);
-	LFSR LFSR0(tick_ms, en_lfsr, N);
-	delay DEL0(tick_ms, N, start_delay, time_out);
-	bin2bcd_16 BCD(N, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
-	hex_to_7seg SEG0(HEX0, BCD_0);
-	hex_to_7seg SEG1(HEX1, BCD_1);
-	hex_to_7seg SEG2(HEX2, BCD_2);
-	
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/formula_fsm.v b/part_2/ex9_partially_working/verilog_files/formula_fsm.v
deleted file mode 100755
index 90daa0c..0000000
--- a/part_2/ex9_partially_working/verilog_files/formula_fsm.v
+++ /dev/null
@@ -1,66 +0,0 @@
-module formula_fsm(clk, tick, trigger, time_out, en_lfsr, start_delay, ledr);
-
-input clk, tick, trigger, time_out;
-output en_lfsr, start_delay;
-output [9:0] ledr;
-
-reg [1:0] state;
-reg led_on, en_lfsr, start_delay;
-reg [9:0] ledr;
-
-parameter WAIT_TRIGGER = 2'd0, LIGHT_UP_LEDS = 2'd1, WAIT_FOR_TIMEOUT = 2'd2;
-
-initial 
-	begin
-		state = WAIT_TRIGGER;
-		en_lfsr = 1'b0;
-		start_delay = 1'b0;
-	end
-
-always @ (posedge clk)
-	case(state)
-		WAIT_TRIGGER: 
-			begin
-				if(trigger == 1'b1)
-					state <= LIGHT_UP_LEDS;
-			end
-		LIGHT_UP_LEDS:
-				if(ledr == 10'h3ff)
-					state <= WAIT_FOR_TIMEOUT;
-		WAIT_FOR_TIMEOUT:
-				if(time_out == 1'b1)
-					 state <= WAIT_TRIGGER;
-		default: ;
-	endcase
-
-always @ (posedge tick)
-	case(state)
-		WAIT_TRIGGER:
-			ledr = 10'b0;
-		LIGHT_UP_LEDS:
-			ledr <= {ledr[8:0], 1'b1};
-		default:
-			ledr <= 10'h3ff;
-	endcase
-	
-always @ (*)
-	case(state)
-		WAIT_TRIGGER:
-			begin
-
-				en_lfsr = 1'b0;
-				start_delay = 1'b0;
-			end
-		LIGHT_UP_LEDS:
-			begin
-				en_lfsr = 1'b1;
-			end
-		WAIT_FOR_TIMEOUT:
-			begin
-				start_delay = 1'b1;
-				en_lfsr = 1'b0;
-			end
-		default: ;
-	endcase
-
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/formula_fsm.v.bak b/part_2/ex9_partially_working/verilog_files/formula_fsm.v.bak
deleted file mode 100755
index e69de29..0000000
--- a/part_2/ex9_partially_working/verilog_files/formula_fsm.v.bak
+++ /dev/null
diff --git a/part_2/ex9_partially_working/verilog_files/tick_2500.v b/part_2/ex9_partially_working/verilog_files/tick_2500.v
deleted file mode 100755
index e75a131..0000000
--- a/part_2/ex9_partially_working/verilog_files/tick_2500.v
+++ /dev/null
@@ -1,35 +0,0 @@
-module tick_2500(CLOCK_IN, en, CLK_OUT);
-
-	parameter NBIT = 12;
-	
-	input CLOCK_IN, en;
-	output CLK_OUT;
-	
-	reg [NBIT-1:0] count;
-	
-	reg CLK_OUT;
-	
-	initial 
-		begin
-			count = 12'd2499;
-			CLK_OUT = 1'b0;
-		end
-	
-	always @ (posedge CLOCK_IN)
-		if(en == 1'b1)
-			begin
-				if(count == 1'b0)
-					begin
-						CLK_OUT <= 1'b1;
-						count <= 12'd2499;
-					end
-				else
-					begin
-						count <= count - 1'b1;
-						CLK_OUT <= 1'b0;
-					end
-			end
-		else 
-			CLK_OUT <= 1'b0;
-
-endmodule
-\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/tick_2500.v.bak b/part_2/ex9_partially_working/verilog_files/tick_2500.v.bak
deleted file mode 100755
index e69de29..0000000
--- a/part_2/ex9_partially_working/verilog_files/tick_2500.v.bak
+++ /dev/null
diff --git a/part_3/ex10/db/_cmp.kpt b/part_3/ex10/db/_cmp.kpt
deleted file mode 100644
index 1a52cce..0000000
--- a/part_3/ex10/db/_cmp.kpt
+++ /dev/null
diff --git a/part_3/ex10/ex10.v.bak b/part_3/ex10/ex10.v.bak
index d3f5a12..8b13789 100755
--- a/part_3/ex10/ex10.v.bak
+++ b/part_3/ex10/ex10.v.bak
@@ -1 +1 @@
-
+
diff --git a/part_3/ex10/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex10/simulation/modelsim/do_files/tb_spi2dac.do
index 52dd5a2..b12a7d7 100755
--- a/part_3/ex10/simulation/modelsim/do_files/tb_spi2dac.do
+++ b/part_3/ex10/simulation/modelsim/do_files/tb_spi2dac.do
@@ -1,17 +1,17 @@
-add wave -position end  sysclk
-add wave -position end -hexadecimal data_in
-add wave -position end load
-add wave -position end  dac_sdi
-add wave -position end  dac_cs
-add wave -position end  dac_sck
-add wave -position end  dac_ld
-force sysclk 1 0, 0 10ns -r 20ns
-force data_in 10'h23b
-force load 0
-run 200ns
-force load 1
-run 400ns
-force load 0
-run 20us
-
-
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex10/simulation/modelsim/rtl_work/_info b/part_3/ex10/simulation/modelsim/rtl_work/_info
index 63648ac..499bdd4 100755
--- a/part_3/ex10/simulation/modelsim/rtl_work/_info
+++ b/part_3/ex10/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\ex10\simulation\modelsim
-vspi2dac
-!i10b 1
-!s100 Yc_:?1WP<4LKj7cQXiUbl1
-IzTNjHgWKkeSFYc0]WM5Gm2
-VFNOGDa=aYhJTn=76LYB@A2
-Z1 dC:\New folder\ex10\simulation\modelsim
-w1478805578
-8C:/New folder/ex10/verilog_files/spi2dac.v
-FC:/New folder/ex10/verilog_files/spi2dac.v
-L0 9
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1480413939.783000
-!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex10/simulation/modelsim/rtl_work/_vmake b/part_3/ex10/simulation/modelsim/rtl_work/_vmake
index b51b305..2f7e729 100755
--- a/part_3/ex10/simulation/modelsim/rtl_work/_vmake
+++ b/part_3/ex10/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_3/ex10/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex10/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
index 2a503c0..e874ed3 100755
--- a/part_3/ex10/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
+++ b/part_3/ex10/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -1,30 +1,30 @@
-library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
-    generic(
-        BUF             : vl_logic := Hi1;
-        GA_N            : vl_logic := Hi1;
-        SHDN_N          : vl_logic := Hi1;
-        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
-        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
-        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
-        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
-    );
-    port(
-        sysclk          : in     vl_logic;
-        data_in         : in     vl_logic_vector(9 downto 0);
-        load            : in     vl_logic;
-        dac_sdi         : out    vl_logic;
-        dac_cs          : out    vl_logic;
-        dac_sck         : out    vl_logic;
-        dac_ld          : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of BUF : constant is 1;
-    attribute mti_svvh_generic_type of GA_N : constant is 1;
-    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
-    attribute mti_svvh_generic_type of TC : constant is 1;
-    attribute mti_svvh_generic_type of IDLE : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+    generic(
+        BUF             : vl_logic := Hi1;
+        GA_N            : vl_logic := Hi1;
+        SHDN_N          : vl_logic := Hi1;
+        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        data_in         : in     vl_logic_vector(9 downto 0);
+        load            : in     vl_logic;
+        dac_sdi         : out    vl_logic;
+        dac_cs          : out    vl_logic;
+        dac_sck         : out    vl_logic;
+        dac_ld          : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BUF : constant is 1;
+    attribute mti_svvh_generic_type of GA_N : constant is 1;
+    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+    attribute mti_svvh_generic_type of TC : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
diff --git a/part_3/ex11/.qsys_edit/filters.xml b/part_3/ex11/.qsys_edit/filters.xml
index 25484e0..2c6ab93 100755
--- a/part_3/ex11/.qsys_edit/filters.xml
+++ b/part_3/ex11/.qsys_edit/filters.xml
@@ -1,2 +1,2 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<filters version="16.0" />
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="16.0" />
diff --git a/part_3/ex11/.qsys_edit/preferences.xml b/part_3/ex11/.qsys_edit/preferences.xml
index ea0fb24..c5b7680 100755
--- a/part_3/ex11/.qsys_edit/preferences.xml
+++ b/part_3/ex11/.qsys_edit/preferences.xml
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<preferences>
- <debug showDebugMenu="0" />
- <systemtable filter="All Interfaces">
-  <columns>
-   <connections preferredWidth="47" />
-   <irq preferredWidth="34" />
-  </columns>
- </systemtable>
- <library expandedCategories="Project,Library" />
- <window width="1100" height="800" x="0" y="0" />
-</preferences>
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="47" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1100" height="800" x="0" y="0" />
+</preferences>
diff --git a/part_3/ex11/db/_cmp.kpt b/part_3/ex11/db/_cmp.kpt
deleted file mode 100644
index bd9e7c9..0000000
--- a/part_3/ex11/db/_cmp.kpt
+++ /dev/null
diff --git a/part_3/ex11/ex10.v.bak b/part_3/ex11/ex10.v.bak
index d3f5a12..8b13789 100755
--- a/part_3/ex11/ex10.v.bak
+++ b/part_3/ex11/ex10.v.bak
@@ -1 +1 @@
-
+
diff --git a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
index 52dd5a2..b12a7d7 100755
--- a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
+++ b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
@@ -1,17 +1,17 @@
-add wave -position end  sysclk
-add wave -position end -hexadecimal data_in
-add wave -position end load
-add wave -position end  dac_sdi
-add wave -position end  dac_cs
-add wave -position end  dac_sck
-add wave -position end  dac_ld
-force sysclk 1 0, 0 10ns -r 20ns
-force data_in 10'h23b
-force load 0
-run 200ns
-force load 1
-run 400ns
-force load 0
-run 20us
-
-
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_info b/part_3/ex11/simulation/modelsim/rtl_work/_info
index 63648ac..499bdd4 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/_info
+++ b/part_3/ex11/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\ex10\simulation\modelsim
-vspi2dac
-!i10b 1
-!s100 Yc_:?1WP<4LKj7cQXiUbl1
-IzTNjHgWKkeSFYc0]WM5Gm2
-VFNOGDa=aYhJTn=76LYB@A2
-Z1 dC:\New folder\ex10\simulation\modelsim
-w1478805578
-8C:/New folder/ex10/verilog_files/spi2dac.v
-FC:/New folder/ex10/verilog_files/spi2dac.v
-L0 9
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1480413939.783000
-!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_vmake b/part_3/ex11/simulation/modelsim/rtl_work/_vmake
index b51b305..2f7e729 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/_vmake
+++ b/part_3/ex11/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
index 2a503c0..e874ed3 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
+++ b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -1,30 +1,30 @@
-library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
-    generic(
-        BUF             : vl_logic := Hi1;
-        GA_N            : vl_logic := Hi1;
-        SHDN_N          : vl_logic := Hi1;
-        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
-        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
-        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
-        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
-    );
-    port(
-        sysclk          : in     vl_logic;
-        data_in         : in     vl_logic_vector(9 downto 0);
-        load            : in     vl_logic;
-        dac_sdi         : out    vl_logic;
-        dac_cs          : out    vl_logic;
-        dac_sck         : out    vl_logic;
-        dac_ld          : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of BUF : constant is 1;
-    attribute mti_svvh_generic_type of GA_N : constant is 1;
-    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
-    attribute mti_svvh_generic_type of TC : constant is 1;
-    attribute mti_svvh_generic_type of IDLE : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+    generic(
+        BUF             : vl_logic := Hi1;
+        GA_N            : vl_logic := Hi1;
+        SHDN_N          : vl_logic := Hi1;
+        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        data_in         : in     vl_logic_vector(9 downto 0);
+        load            : in     vl_logic;
+        dac_sdi         : out    vl_logic;
+        dac_cs          : out    vl_logic;
+        dac_sck         : out    vl_logic;
+        dac_ld          : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BUF : constant is 1;
+    attribute mti_svvh_generic_type of GA_N : constant is 1;
+    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+    attribute mti_svvh_generic_type of TC : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
diff --git a/part_3/ex12/db/_cmp.kpt b/part_3/ex12/db/_cmp.kpt
deleted file mode 100644
index fa3c9a7..0000000
--- a/part_3/ex12/db/_cmp.kpt
+++ /dev/null
diff --git a/part_3/ex12/rom_data/rom_data.mif b/part_3/ex12/rom_data/rom_data.mif
index 45464a9..a688b6f 100755
--- a/part_3/ex12/rom_data/rom_data.mif
+++ b/part_3/ex12/rom_data/rom_data.mif
@@ -1,1032 +1,1032 @@
--- ROM Initialization file
-WIDTH = 10;
-DEPTH = 1024;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
-BEGIN
-   0 :  200;
-   1 :  203;
-   2 :  206;
-   3 :  209;
-   4 :  20C;
-   5 :  20F;
-   6 :  212;
-   7 :  215;
-   8 :  219;
-   9 :  21C;
-   A :  21F;
-   B :  222;
-   C :  225;
-   D :  228;
-   E :  22B;
-   F :  22F;
-  10 :  232;
-  11 :  235;
-  12 :  238;
-  13 :  23B;
-  14 :  23E;
-  15 :  241;
-  16 :  244;
-  17 :  247;
-  18 :  24B;
-  19 :  24E;
-  1A :  251;
-  1B :  254;
-  1C :  257;
-  1D :  25A;
-  1E :  25D;
-  1F :  260;
-  20 :  263;
-  21 :  266;
-  22 :  269;
-  23 :  26D;
-  24 :  270;
-  25 :  273;
-  26 :  276;
-  27 :  279;
-  28 :  27C;
-  29 :  27F;
-  2A :  282;
-  2B :  285;
-  2C :  288;
-  2D :  28B;
-  2E :  28E;
-  2F :  291;
-  30 :  294;
-  31 :  297;
-  32 :  29A;
-  33 :  29D;
-  34 :  2A0;
-  35 :  2A3;
-  36 :  2A6;
-  37 :  2A9;
-  38 :  2AC;
-  39 :  2AF;
-  3A :  2B2;
-  3B :  2B5;
-  3C :  2B8;
-  3D :  2BB;
-  3E :  2BD;
-  3F :  2C0;
-  40 :  2C3;
-  41 :  2C6;
-  42 :  2C9;
-  43 :  2CC;
-  44 :  2CF;
-  45 :  2D2;
-  46 :  2D5;
-  47 :  2D7;
-  48 :  2DA;
-  49 :  2DD;
-  4A :  2E0;
-  4B :  2E3;
-  4C :  2E5;
-  4D :  2E8;
-  4E :  2EB;
-  4F :  2EE;
-  50 :  2F1;
-  51 :  2F3;
-  52 :  2F6;
-  53 :  2F9;
-  54 :  2FC;
-  55 :  2FE;
-  56 :  301;
-  57 :  304;
-  58 :  306;
-  59 :  309;
-  5A :  30C;
-  5B :  30E;
-  5C :  311;
-  5D :  314;
-  5E :  316;
-  5F :  319;
-  60 :  31C;
-  61 :  31E;
-  62 :  321;
-  63 :  323;
-  64 :  326;
-  65 :  329;
-  66 :  32B;
-  67 :  32E;
-  68 :  330;
-  69 :  333;
-  6A :  335;
-  6B :  338;
-  6C :  33A;
-  6D :  33D;
-  6E :  33F;
-  6F :  342;
-  70 :  344;
-  71 :  346;
-  72 :  349;
-  73 :  34B;
-  74 :  34E;
-  75 :  350;
-  76 :  352;
-  77 :  355;
-  78 :  357;
-  79 :  359;
-  7A :  35C;
-  7B :  35E;
-  7C :  360;
-  7D :  362;
-  7E :  365;
-  7F :  367;
-  80 :  369;
-  81 :  36B;
-  82 :  36E;
-  83 :  370;
-  84 :  372;
-  85 :  374;
-  86 :  376;
-  87 :  378;
-  88 :  37A;
-  89 :  37D;
-  8A :  37F;
-  8B :  381;
-  8C :  383;
-  8D :  385;
-  8E :  387;
-  8F :  389;
-  90 :  38B;
-  91 :  38D;
-  92 :  38F;
-  93 :  391;
-  94 :  393;
-  95 :  395;
-  96 :  397;
-  97 :  398;
-  98 :  39A;
-  99 :  39C;
-  9A :  39E;
-  9B :  3A0;
-  9C :  3A2;
-  9D :  3A3;
-  9E :  3A5;
-  9F :  3A7;
-  A0 :  3A9;
-  A1 :  3AB;
-  A2 :  3AC;
-  A3 :  3AE;
-  A4 :  3B0;
-  A5 :  3B1;
-  A6 :  3B3;
-  A7 :  3B5;
-  A8 :  3B6;
-  A9 :  3B8;
-  AA :  3B9;
-  AB :  3BB;
-  AC :  3BD;
-  AD :  3BE;
-  AE :  3C0;
-  AF :  3C1;
-  B0 :  3C3;
-  B1 :  3C4;
-  B2 :  3C6;
-  B3 :  3C7;
-  B4 :  3C8;
-  B5 :  3CA;
-  B6 :  3CB;
-  B7 :  3CD;
-  B8 :  3CE;
-  B9 :  3CF;
-  BA :  3D1;
-  BB :  3D2;
-  BC :  3D3;
-  BD :  3D4;
-  BE :  3D6;
-  BF :  3D7;
-  C0 :  3D8;
-  C1 :  3D9;
-  C2 :  3DA;
-  C3 :  3DC;
-  C4 :  3DD;
-  C5 :  3DE;
-  C6 :  3DF;
-  C7 :  3E0;
-  C8 :  3E1;
-  C9 :  3E2;
-  CA :  3E3;
-  CB :  3E4;
-  CC :  3E5;
-  CD :  3E6;
-  CE :  3E7;
-  CF :  3E8;
-  D0 :  3E9;
-  D1 :  3EA;
-  D2 :  3EB;
-  D3 :  3EC;
-  D4 :  3EC;
-  D5 :  3ED;
-  D6 :  3EE;
-  D7 :  3EF;
-  D8 :  3F0;
-  D9 :  3F0;
-  DA :  3F1;
-  DB :  3F2;
-  DC :  3F3;
-  DD :  3F3;
-  DE :  3F4;
-  DF :  3F5;
-  E0 :  3F5;
-  E1 :  3F6;
-  E2 :  3F6;
-  E3 :  3F7;
-  E4 :  3F7;
-  E5 :  3F8;
-  E6 :  3F9;
-  E7 :  3F9;
-  E8 :  3F9;
-  E9 :  3FA;
-  EA :  3FA;
-  EB :  3FB;
-  EC :  3FB;
-  ED :  3FC;
-  EE :  3FC;
-  EF :  3FC;
-  F0 :  3FD;
-  F1 :  3FD;
-  F2 :  3FD;
-  F3 :  3FD;
-  F4 :  3FE;
-  F5 :  3FE;
-  F6 :  3FE;
-  F7 :  3FE;
-  F8 :  3FE;
-  F9 :  3FF;
-  FA :  3FF;
-  FB :  3FF;
-  FC :  3FF;
-  FD :  3FF;
-  FE :  3FF;
-  FF :  3FF;
- 100 :  3FF;
- 101 :  3FF;
- 102 :  3FF;
- 103 :  3FF;
- 104 :  3FF;
- 105 :  3FF;
- 106 :  3FF;
- 107 :  3FF;
- 108 :  3FE;
- 109 :  3FE;
- 10A :  3FE;
- 10B :  3FE;
- 10C :  3FE;
- 10D :  3FD;
- 10E :  3FD;
- 10F :  3FD;
- 110 :  3FD;
- 111 :  3FC;
- 112 :  3FC;
- 113 :  3FC;
- 114 :  3FB;
- 115 :  3FB;
- 116 :  3FA;
- 117 :  3FA;
- 118 :  3F9;
- 119 :  3F9;
- 11A :  3F9;
- 11B :  3F8;
- 11C :  3F7;
- 11D :  3F7;
- 11E :  3F6;
- 11F :  3F6;
- 120 :  3F5;
- 121 :  3F5;
- 122 :  3F4;
- 123 :  3F3;
- 124 :  3F3;
- 125 :  3F2;
- 126 :  3F1;
- 127 :  3F0;
- 128 :  3F0;
- 129 :  3EF;
- 12A :  3EE;
- 12B :  3ED;
- 12C :  3EC;
- 12D :  3EC;
- 12E :  3EB;
- 12F :  3EA;
- 130 :  3E9;
- 131 :  3E8;
- 132 :  3E7;
- 133 :  3E6;
- 134 :  3E5;
- 135 :  3E4;
- 136 :  3E3;
- 137 :  3E2;
- 138 :  3E1;
- 139 :  3E0;
- 13A :  3DF;
- 13B :  3DE;
- 13C :  3DD;
- 13D :  3DC;
- 13E :  3DA;
- 13F :  3D9;
- 140 :  3D8;
- 141 :  3D7;
- 142 :  3D6;
- 143 :  3D4;
- 144 :  3D3;
- 145 :  3D2;
- 146 :  3D1;
- 147 :  3CF;
- 148 :  3CE;
- 149 :  3CD;
- 14A :  3CB;
- 14B :  3CA;
- 14C :  3C8;
- 14D :  3C7;
- 14E :  3C6;
- 14F :  3C4;
- 150 :  3C3;
- 151 :  3C1;
- 152 :  3C0;
- 153 :  3BE;
- 154 :  3BD;
- 155 :  3BB;
- 156 :  3B9;
- 157 :  3B8;
- 158 :  3B6;
- 159 :  3B5;
- 15A :  3B3;
- 15B :  3B1;
- 15C :  3B0;
- 15D :  3AE;
- 15E :  3AC;
- 15F :  3AB;
- 160 :  3A9;
- 161 :  3A7;
- 162 :  3A5;
- 163 :  3A3;
- 164 :  3A2;
- 165 :  3A0;
- 166 :  39E;
- 167 :  39C;
- 168 :  39A;
- 169 :  398;
- 16A :  397;
- 16B :  395;
- 16C :  393;
- 16D :  391;
- 16E :  38F;
- 16F :  38D;
- 170 :  38B;
- 171 :  389;
- 172 :  387;
- 173 :  385;
- 174 :  383;
- 175 :  381;
- 176 :  37F;
- 177 :  37D;
- 178 :  37A;
- 179 :  378;
- 17A :  376;
- 17B :  374;
- 17C :  372;
- 17D :  370;
- 17E :  36E;
- 17F :  36B;
- 180 :  369;
- 181 :  367;
- 182 :  365;
- 183 :  362;
- 184 :  360;
- 185 :  35E;
- 186 :  35C;
- 187 :  359;
- 188 :  357;
- 189 :  355;
- 18A :  352;
- 18B :  350;
- 18C :  34E;
- 18D :  34B;
- 18E :  349;
- 18F :  346;
- 190 :  344;
- 191 :  342;
- 192 :  33F;
- 193 :  33D;
- 194 :  33A;
- 195 :  338;
- 196 :  335;
- 197 :  333;
- 198 :  330;
- 199 :  32E;
- 19A :  32B;
- 19B :  329;
- 19C :  326;
- 19D :  323;
- 19E :  321;
- 19F :  31E;
- 1A0 :  31C;
- 1A1 :  319;
- 1A2 :  316;
- 1A3 :  314;
- 1A4 :  311;
- 1A5 :  30E;
- 1A6 :  30C;
- 1A7 :  309;
- 1A8 :  306;
- 1A9 :  304;
- 1AA :  301;
- 1AB :  2FE;
- 1AC :  2FC;
- 1AD :  2F9;
- 1AE :  2F6;
- 1AF :  2F3;
- 1B0 :  2F1;
- 1B1 :  2EE;
- 1B2 :  2EB;
- 1B3 :  2E8;
- 1B4 :  2E5;
- 1B5 :  2E3;
- 1B6 :  2E0;
- 1B7 :  2DD;
- 1B8 :  2DA;
- 1B9 :  2D7;
- 1BA :  2D5;
- 1BB :  2D2;
- 1BC :  2CF;
- 1BD :  2CC;
- 1BE :  2C9;
- 1BF :  2C6;
- 1C0 :  2C3;
- 1C1 :  2C0;
- 1C2 :  2BD;
- 1C3 :  2BB;
- 1C4 :  2B8;
- 1C5 :  2B5;
- 1C6 :  2B2;
- 1C7 :  2AF;
- 1C8 :  2AC;
- 1C9 :  2A9;
- 1CA :  2A6;
- 1CB :  2A3;
- 1CC :  2A0;
- 1CD :  29D;
- 1CE :  29A;
- 1CF :  297;
- 1D0 :  294;
- 1D1 :  291;
- 1D2 :  28E;
- 1D3 :  28B;
- 1D4 :  288;
- 1D5 :  285;
- 1D6 :  282;
- 1D7 :  27F;
- 1D8 :  27C;
- 1D9 :  279;
- 1DA :  276;
- 1DB :  273;
- 1DC :  270;
- 1DD :  26D;
- 1DE :  269;
- 1DF :  266;
- 1E0 :  263;
- 1E1 :  260;
- 1E2 :  25D;
- 1E3 :  25A;
- 1E4 :  257;
- 1E5 :  254;
- 1E6 :  251;
- 1E7 :  24E;
- 1E8 :  24B;
- 1E9 :  247;
- 1EA :  244;
- 1EB :  241;
- 1EC :  23E;
- 1ED :  23B;
- 1EE :  238;
- 1EF :  235;
- 1F0 :  232;
- 1F1 :  22F;
- 1F2 :  22B;
- 1F3 :  228;
- 1F4 :  225;
- 1F5 :  222;
- 1F6 :  21F;
- 1F7 :  21C;
- 1F8 :  219;
- 1F9 :  215;
- 1FA :  212;
- 1FB :  20F;
- 1FC :  20C;
- 1FD :  209;
- 1FE :  206;
- 1FF :  203;
- 200 :  200;
- 201 :  1FC;
- 202 :  1F9;
- 203 :  1F6;
- 204 :  1F3;
- 205 :  1F0;
- 206 :  1ED;
- 207 :  1EA;
- 208 :  1E6;
- 209 :  1E3;
- 20A :  1E0;
- 20B :  1DD;
- 20C :  1DA;
- 20D :  1D7;
- 20E :  1D4;
- 20F :  1D0;
- 210 :  1CD;
- 211 :  1CA;
- 212 :  1C7;
- 213 :  1C4;
- 214 :  1C1;
- 215 :  1BE;
- 216 :  1BB;
- 217 :  1B8;
- 218 :  1B4;
- 219 :  1B1;
- 21A :  1AE;
- 21B :  1AB;
- 21C :  1A8;
- 21D :  1A5;
- 21E :  1A2;
- 21F :  19F;
- 220 :  19C;
- 221 :  199;
- 222 :  196;
- 223 :  192;
- 224 :  18F;
- 225 :  18C;
- 226 :  189;
- 227 :  186;
- 228 :  183;
- 229 :  180;
- 22A :  17D;
- 22B :  17A;
- 22C :  177;
- 22D :  174;
- 22E :  171;
- 22F :  16E;
- 230 :  16B;
- 231 :  168;
- 232 :  165;
- 233 :  162;
- 234 :  15F;
- 235 :  15C;
- 236 :  159;
- 237 :  156;
- 238 :  153;
- 239 :  150;
- 23A :  14D;
- 23B :  14A;
- 23C :  147;
- 23D :  144;
- 23E :  142;
- 23F :  13F;
- 240 :  13C;
- 241 :  139;
- 242 :  136;
- 243 :  133;
- 244 :  130;
- 245 :  12D;
- 246 :  12A;
- 247 :  128;
- 248 :  125;
- 249 :  122;
- 24A :  11F;
- 24B :  11C;
- 24C :  11A;
- 24D :  117;
- 24E :  114;
- 24F :  111;
- 250 :  10E;
- 251 :  10C;
- 252 :  109;
- 253 :  106;
- 254 :  103;
- 255 :  101;
- 256 :   FE;
- 257 :   FB;
- 258 :   F9;
- 259 :   F6;
- 25A :   F3;
- 25B :   F1;
- 25C :   EE;
- 25D :   EB;
- 25E :   E9;
- 25F :   E6;
- 260 :   E3;
- 261 :   E1;
- 262 :   DE;
- 263 :   DC;
- 264 :   D9;
- 265 :   D6;
- 266 :   D4;
- 267 :   D1;
- 268 :   CF;
- 269 :   CC;
- 26A :   CA;
- 26B :   C7;
- 26C :   C5;
- 26D :   C2;
- 26E :   C0;
- 26F :   BD;
- 270 :   BB;
- 271 :   B9;
- 272 :   B6;
- 273 :   B4;
- 274 :   B1;
- 275 :   AF;
- 276 :   AD;
- 277 :   AA;
- 278 :   A8;
- 279 :   A6;
- 27A :   A3;
- 27B :   A1;
- 27C :   9F;
- 27D :   9D;
- 27E :   9A;
- 27F :   98;
- 280 :   96;
- 281 :   94;
- 282 :   91;
- 283 :   8F;
- 284 :   8D;
- 285 :   8B;
- 286 :   89;
- 287 :   87;
- 288 :   85;
- 289 :   82;
- 28A :   80;
- 28B :   7E;
- 28C :   7C;
- 28D :   7A;
- 28E :   78;
- 28F :   76;
- 290 :   74;
- 291 :   72;
- 292 :   70;
- 293 :   6E;
- 294 :   6C;
- 295 :   6A;
- 296 :   68;
- 297 :   67;
- 298 :   65;
- 299 :   63;
- 29A :   61;
- 29B :   5F;
- 29C :   5D;
- 29D :   5C;
- 29E :   5A;
- 29F :   58;
- 2A0 :   56;
- 2A1 :   54;
- 2A2 :   53;
- 2A3 :   51;
- 2A4 :   4F;
- 2A5 :   4E;
- 2A6 :   4C;
- 2A7 :   4A;
- 2A8 :   49;
- 2A9 :   47;
- 2AA :   46;
- 2AB :   44;
- 2AC :   42;
- 2AD :   41;
- 2AE :   3F;
- 2AF :   3E;
- 2B0 :   3C;
- 2B1 :   3B;
- 2B2 :   39;
- 2B3 :   38;
- 2B4 :   37;
- 2B5 :   35;
- 2B6 :   34;
- 2B7 :   32;
- 2B8 :   31;
- 2B9 :   30;
- 2BA :   2E;
- 2BB :   2D;
- 2BC :   2C;
- 2BD :   2B;
- 2BE :   29;
- 2BF :   28;
- 2C0 :   27;
- 2C1 :   26;
- 2C2 :   25;
- 2C3 :   23;
- 2C4 :   22;
- 2C5 :   21;
- 2C6 :   20;
- 2C7 :   1F;
- 2C8 :   1E;
- 2C9 :   1D;
- 2CA :   1C;
- 2CB :   1B;
- 2CC :   1A;
- 2CD :   19;
- 2CE :   18;
- 2CF :   17;
- 2D0 :   16;
- 2D1 :   15;
- 2D2 :   14;
- 2D3 :   13;
- 2D4 :   13;
- 2D5 :   12;
- 2D6 :   11;
- 2D7 :   10;
- 2D8 :    F;
- 2D9 :    F;
- 2DA :    E;
- 2DB :    D;
- 2DC :    C;
- 2DD :    C;
- 2DE :    B;
- 2DF :    A;
- 2E0 :    A;
- 2E1 :    9;
- 2E2 :    9;
- 2E3 :    8;
- 2E4 :    8;
- 2E5 :    7;
- 2E6 :    6;
- 2E7 :    6;
- 2E8 :    6;
- 2E9 :    5;
- 2EA :    5;
- 2EB :    4;
- 2EC :    4;
- 2ED :    3;
- 2EE :    3;
- 2EF :    3;
- 2F0 :    2;
- 2F1 :    2;
- 2F2 :    2;
- 2F3 :    2;
- 2F4 :    1;
- 2F5 :    1;
- 2F6 :    1;
- 2F7 :    1;
- 2F8 :    1;
- 2F9 :    0;
- 2FA :    0;
- 2FB :    0;
- 2FC :    0;
- 2FD :    0;
- 2FE :    0;
- 2FF :    0;
- 300 :    0;
- 301 :    0;
- 302 :    0;
- 303 :    0;
- 304 :    0;
- 305 :    0;
- 306 :    0;
- 307 :    0;
- 308 :    1;
- 309 :    1;
- 30A :    1;
- 30B :    1;
- 30C :    1;
- 30D :    2;
- 30E :    2;
- 30F :    2;
- 310 :    2;
- 311 :    3;
- 312 :    3;
- 313 :    3;
- 314 :    4;
- 315 :    4;
- 316 :    5;
- 317 :    5;
- 318 :    6;
- 319 :    6;
- 31A :    6;
- 31B :    7;
- 31C :    8;
- 31D :    8;
- 31E :    9;
- 31F :    9;
- 320 :    A;
- 321 :    A;
- 322 :    B;
- 323 :    C;
- 324 :    C;
- 325 :    D;
- 326 :    E;
- 327 :    F;
- 328 :    F;
- 329 :   10;
- 32A :   11;
- 32B :   12;
- 32C :   13;
- 32D :   13;
- 32E :   14;
- 32F :   15;
- 330 :   16;
- 331 :   17;
- 332 :   18;
- 333 :   19;
- 334 :   1A;
- 335 :   1B;
- 336 :   1C;
- 337 :   1D;
- 338 :   1E;
- 339 :   1F;
- 33A :   20;
- 33B :   21;
- 33C :   22;
- 33D :   23;
- 33E :   25;
- 33F :   26;
- 340 :   27;
- 341 :   28;
- 342 :   29;
- 343 :   2B;
- 344 :   2C;
- 345 :   2D;
- 346 :   2E;
- 347 :   30;
- 348 :   31;
- 349 :   32;
- 34A :   34;
- 34B :   35;
- 34C :   37;
- 34D :   38;
- 34E :   39;
- 34F :   3B;
- 350 :   3C;
- 351 :   3E;
- 352 :   3F;
- 353 :   41;
- 354 :   42;
- 355 :   44;
- 356 :   46;
- 357 :   47;
- 358 :   49;
- 359 :   4A;
- 35A :   4C;
- 35B :   4E;
- 35C :   4F;
- 35D :   51;
- 35E :   53;
- 35F :   54;
- 360 :   56;
- 361 :   58;
- 362 :   5A;
- 363 :   5C;
- 364 :   5D;
- 365 :   5F;
- 366 :   61;
- 367 :   63;
- 368 :   65;
- 369 :   67;
- 36A :   68;
- 36B :   6A;
- 36C :   6C;
- 36D :   6E;
- 36E :   70;
- 36F :   72;
- 370 :   74;
- 371 :   76;
- 372 :   78;
- 373 :   7A;
- 374 :   7C;
- 375 :   7E;
- 376 :   80;
- 377 :   82;
- 378 :   85;
- 379 :   87;
- 37A :   89;
- 37B :   8B;
- 37C :   8D;
- 37D :   8F;
- 37E :   91;
- 37F :   94;
- 380 :   96;
- 381 :   98;
- 382 :   9A;
- 383 :   9D;
- 384 :   9F;
- 385 :   A1;
- 386 :   A3;
- 387 :   A6;
- 388 :   A8;
- 389 :   AA;
- 38A :   AD;
- 38B :   AF;
- 38C :   B1;
- 38D :   B4;
- 38E :   B6;
- 38F :   B9;
- 390 :   BB;
- 391 :   BD;
- 392 :   C0;
- 393 :   C2;
- 394 :   C5;
- 395 :   C7;
- 396 :   CA;
- 397 :   CC;
- 398 :   CF;
- 399 :   D1;
- 39A :   D4;
- 39B :   D6;
- 39C :   D9;
- 39D :   DC;
- 39E :   DE;
- 39F :   E1;
- 3A0 :   E3;
- 3A1 :   E6;
- 3A2 :   E9;
- 3A3 :   EB;
- 3A4 :   EE;
- 3A5 :   F1;
- 3A6 :   F3;
- 3A7 :   F6;
- 3A8 :   F9;
- 3A9 :   FB;
- 3AA :   FE;
- 3AB :  101;
- 3AC :  103;
- 3AD :  106;
- 3AE :  109;
- 3AF :  10C;
- 3B0 :  10E;
- 3B1 :  111;
- 3B2 :  114;
- 3B3 :  117;
- 3B4 :  11A;
- 3B5 :  11C;
- 3B6 :  11F;
- 3B7 :  122;
- 3B8 :  125;
- 3B9 :  128;
- 3BA :  12A;
- 3BB :  12D;
- 3BC :  130;
- 3BD :  133;
- 3BE :  136;
- 3BF :  139;
- 3C0 :  13C;
- 3C1 :  13F;
- 3C2 :  142;
- 3C3 :  144;
- 3C4 :  147;
- 3C5 :  14A;
- 3C6 :  14D;
- 3C7 :  150;
- 3C8 :  153;
- 3C9 :  156;
- 3CA :  159;
- 3CB :  15C;
- 3CC :  15F;
- 3CD :  162;
- 3CE :  165;
- 3CF :  168;
- 3D0 :  16B;
- 3D1 :  16E;
- 3D2 :  171;
- 3D3 :  174;
- 3D4 :  177;
- 3D5 :  17A;
- 3D6 :  17D;
- 3D7 :  180;
- 3D8 :  183;
- 3D9 :  186;
- 3DA :  189;
- 3DB :  18C;
- 3DC :  18F;
- 3DD :  192;
- 3DE :  196;
- 3DF :  199;
- 3E0 :  19C;
- 3E1 :  19F;
- 3E2 :  1A2;
- 3E3 :  1A5;
- 3E4 :  1A8;
- 3E5 :  1AB;
- 3E6 :  1AE;
- 3E7 :  1B1;
- 3E8 :  1B4;
- 3E9 :  1B8;
- 3EA :  1BB;
- 3EB :  1BE;
- 3EC :  1C1;
- 3ED :  1C4;
- 3EE :  1C7;
- 3EF :  1CA;
- 3F0 :  1CD;
- 3F1 :  1D0;
- 3F2 :  1D4;
- 3F3 :  1D7;
- 3F4 :  1DA;
- 3F5 :  1DD;
- 3F6 :  1E0;
- 3F7 :  1E3;
- 3F8 :  1E6;
- 3F9 :  1EA;
- 3FA :  1ED;
- 3FB :  1F0;
- 3FC :  1F3;
- 3FD :  1F6;
- 3FE :  1F9;
- 3FF :  1FC;
-END
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
+  61 :  31E;
+  62 :  321;
+  63 :  323;
+  64 :  326;
+  65 :  329;
+  66 :  32B;
+  67 :  32E;
+  68 :  330;
+  69 :  333;
+  6A :  335;
+  6B :  338;
+  6C :  33A;
+  6D :  33D;
+  6E :  33F;
+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
+  97 :  398;
+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
+  9E :  3A5;
+  9F :  3A7;
+  A0 :  3A9;
+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
+  CF :  3E8;
+  D0 :  3E9;
+  D1 :  3EA;
+  D2 :  3EB;
+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
+  D6 :  3EE;
+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
+  DB :  3F2;
+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
+  E0 :  3F5;
+  E1 :  3F6;
+  E2 :  3F6;
+  E3 :  3F7;
+  E4 :  3F7;
+  E5 :  3F8;
+  E6 :  3F9;
+  E7 :  3F9;
+  E8 :  3F9;
+  E9 :  3FA;
+  EA :  3FA;
+  EB :  3FB;
+  EC :  3FB;
+  ED :  3FC;
+  EE :  3FC;
+  EF :  3FC;
+  F0 :  3FD;
+  F1 :  3FD;
+  F2 :  3FD;
+  F3 :  3FD;
+  F4 :  3FE;
+  F5 :  3FE;
+  F6 :  3FE;
+  F7 :  3FE;
+  F8 :  3FE;
+  F9 :  3FF;
+  FA :  3FF;
+  FB :  3FF;
+  FC :  3FF;
+  FD :  3FF;
+  FE :  3FF;
+  FF :  3FF;
+ 100 :  3FF;
+ 101 :  3FF;
+ 102 :  3FF;
+ 103 :  3FF;
+ 104 :  3FF;
+ 105 :  3FF;
+ 106 :  3FF;
+ 107 :  3FF;
+ 108 :  3FE;
+ 109 :  3FE;
+ 10A :  3FE;
+ 10B :  3FE;
+ 10C :  3FE;
+ 10D :  3FD;
+ 10E :  3FD;
+ 10F :  3FD;
+ 110 :  3FD;
+ 111 :  3FC;
+ 112 :  3FC;
+ 113 :  3FC;
+ 114 :  3FB;
+ 115 :  3FB;
+ 116 :  3FA;
+ 117 :  3FA;
+ 118 :  3F9;
+ 119 :  3F9;
+ 11A :  3F9;
+ 11B :  3F8;
+ 11C :  3F7;
+ 11D :  3F7;
+ 11E :  3F6;
+ 11F :  3F6;
+ 120 :  3F5;
+ 121 :  3F5;
+ 122 :  3F4;
+ 123 :  3F3;
+ 124 :  3F3;
+ 125 :  3F2;
+ 126 :  3F1;
+ 127 :  3F0;
+ 128 :  3F0;
+ 129 :  3EF;
+ 12A :  3EE;
+ 12B :  3ED;
+ 12C :  3EC;
+ 12D :  3EC;
+ 12E :  3EB;
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+ 22A :  17D;
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+ 230 :  16B;
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+ 23A :  14D;
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+ 250 :  10E;
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+ 256 :   FE;
+ 257 :   FB;
+ 258 :   F9;
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+ 25A :   F3;
+ 25B :   F1;
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+ 25D :   EB;
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+ 3A0 :   E3;
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+ 3A5 :   F1;
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+ 3A7 :   F6;
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+ 3A9 :   FB;
+ 3AA :   FE;
+ 3AB :  101;
+ 3AC :  103;
+ 3AD :  106;
+ 3AE :  109;
+ 3AF :  10C;
+ 3B0 :  10E;
+ 3B1 :  111;
+ 3B2 :  114;
+ 3B3 :  117;
+ 3B4 :  11A;
+ 3B5 :  11C;
+ 3B6 :  11F;
+ 3B7 :  122;
+ 3B8 :  125;
+ 3B9 :  128;
+ 3BA :  12A;
+ 3BB :  12D;
+ 3BC :  130;
+ 3BD :  133;
+ 3BE :  136;
+ 3BF :  139;
+ 3C0 :  13C;
+ 3C1 :  13F;
+ 3C2 :  142;
+ 3C3 :  144;
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+ 3C7 :  150;
+ 3C8 :  153;
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+ 3CA :  159;
+ 3CB :  15C;
+ 3CC :  15F;
+ 3CD :  162;
+ 3CE :  165;
+ 3CF :  168;
+ 3D0 :  16B;
+ 3D1 :  16E;
+ 3D2 :  171;
+ 3D3 :  174;
+ 3D4 :  177;
+ 3D5 :  17A;
+ 3D6 :  17D;
+ 3D7 :  180;
+ 3D8 :  183;
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+ 3DA :  189;
+ 3DB :  18C;
+ 3DC :  18F;
+ 3DD :  192;
+ 3DE :  196;
+ 3DF :  199;
+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex12/sin_gen_scripts/rom_data.mif b/part_3/ex12/sin_gen_scripts/rom_data.mif
index 45464a9..a688b6f 100755
--- a/part_3/ex12/sin_gen_scripts/rom_data.mif
+++ b/part_3/ex12/sin_gen_scripts/rom_data.mif
@@ -1,1032 +1,1032 @@
--- ROM Initialization file
-WIDTH = 10;
-DEPTH = 1024;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
-BEGIN
-   0 :  200;
-   1 :  203;
-   2 :  206;
-   3 :  209;
-   4 :  20C;
-   5 :  20F;
-   6 :  212;
-   7 :  215;
-   8 :  219;
-   9 :  21C;
-   A :  21F;
-   B :  222;
-   C :  225;
-   D :  228;
-   E :  22B;
-   F :  22F;
-  10 :  232;
-  11 :  235;
-  12 :  238;
-  13 :  23B;
-  14 :  23E;
-  15 :  241;
-  16 :  244;
-  17 :  247;
-  18 :  24B;
-  19 :  24E;
-  1A :  251;
-  1B :  254;
-  1C :  257;
-  1D :  25A;
-  1E :  25D;
-  1F :  260;
-  20 :  263;
-  21 :  266;
-  22 :  269;
-  23 :  26D;
-  24 :  270;
-  25 :  273;
-  26 :  276;
-  27 :  279;
-  28 :  27C;
-  29 :  27F;
-  2A :  282;
-  2B :  285;
-  2C :  288;
-  2D :  28B;
-  2E :  28E;
-  2F :  291;
-  30 :  294;
-  31 :  297;
-  32 :  29A;
-  33 :  29D;
-  34 :  2A0;
-  35 :  2A3;
-  36 :  2A6;
-  37 :  2A9;
-  38 :  2AC;
-  39 :  2AF;
-  3A :  2B2;
-  3B :  2B5;
-  3C :  2B8;
-  3D :  2BB;
-  3E :  2BD;
-  3F :  2C0;
-  40 :  2C3;
-  41 :  2C6;
-  42 :  2C9;
-  43 :  2CC;
-  44 :  2CF;
-  45 :  2D2;
-  46 :  2D5;
-  47 :  2D7;
-  48 :  2DA;
-  49 :  2DD;
-  4A :  2E0;
-  4B :  2E3;
-  4C :  2E5;
-  4D :  2E8;
-  4E :  2EB;
-  4F :  2EE;
-  50 :  2F1;
-  51 :  2F3;
-  52 :  2F6;
-  53 :  2F9;
-  54 :  2FC;
-  55 :  2FE;
-  56 :  301;
-  57 :  304;
-  58 :  306;
-  59 :  309;
-  5A :  30C;
-  5B :  30E;
-  5C :  311;
-  5D :  314;
-  5E :  316;
-  5F :  319;
-  60 :  31C;
-  61 :  31E;
-  62 :  321;
-  63 :  323;
-  64 :  326;
-  65 :  329;
-  66 :  32B;
-  67 :  32E;
-  68 :  330;
-  69 :  333;
-  6A :  335;
-  6B :  338;
-  6C :  33A;
-  6D :  33D;
-  6E :  33F;
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- 3C0 :  13C;
- 3C1 :  13F;
- 3C2 :  142;
- 3C3 :  144;
- 3C4 :  147;
- 3C5 :  14A;
- 3C6 :  14D;
- 3C7 :  150;
- 3C8 :  153;
- 3C9 :  156;
- 3CA :  159;
- 3CB :  15C;
- 3CC :  15F;
- 3CD :  162;
- 3CE :  165;
- 3CF :  168;
- 3D0 :  16B;
- 3D1 :  16E;
- 3D2 :  171;
- 3D3 :  174;
- 3D4 :  177;
- 3D5 :  17A;
- 3D6 :  17D;
- 3D7 :  180;
- 3D8 :  183;
- 3D9 :  186;
- 3DA :  189;
- 3DB :  18C;
- 3DC :  18F;
- 3DD :  192;
- 3DE :  196;
- 3DF :  199;
- 3E0 :  19C;
- 3E1 :  19F;
- 3E2 :  1A2;
- 3E3 :  1A5;
- 3E4 :  1A8;
- 3E5 :  1AB;
- 3E6 :  1AE;
- 3E7 :  1B1;
- 3E8 :  1B4;
- 3E9 :  1B8;
- 3EA :  1BB;
- 3EB :  1BE;
- 3EC :  1C1;
- 3ED :  1C4;
- 3EE :  1C7;
- 3EF :  1CA;
- 3F0 :  1CD;
- 3F1 :  1D0;
- 3F2 :  1D4;
- 3F3 :  1D7;
- 3F4 :  1DA;
- 3F5 :  1DD;
- 3F6 :  1E0;
- 3F7 :  1E3;
- 3F8 :  1E6;
- 3F9 :  1EA;
- 3FA :  1ED;
- 3FB :  1F0;
- 3FC :  1F3;
- 3FD :  1F6;
- 3FE :  1F9;
- 3FF :  1FC;
-END
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
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+  4A :  2E0;
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+  4C :  2E5;
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+  50 :  2F1;
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+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
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+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
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+  62 :  321;
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+  64 :  326;
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+  6C :  33A;
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+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
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+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
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+  9F :  3A7;
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+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
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+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
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+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
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+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
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+  E9 :  3FA;
+  EA :  3FA;
+  EB :  3FB;
+  EC :  3FB;
+  ED :  3FC;
+  EE :  3FC;
+  EF :  3FC;
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+  F2 :  3FD;
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+  F4 :  3FE;
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+ 10A :  3FE;
+ 10B :  3FE;
+ 10C :  3FE;
+ 10D :  3FD;
+ 10E :  3FD;
+ 10F :  3FD;
+ 110 :  3FD;
+ 111 :  3FC;
+ 112 :  3FC;
+ 113 :  3FC;
+ 114 :  3FB;
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+ 118 :  3F9;
+ 119 :  3F9;
+ 11A :  3F9;
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+ 11C :  3F7;
+ 11D :  3F7;
+ 11E :  3F6;
+ 11F :  3F6;
+ 120 :  3F5;
+ 121 :  3F5;
+ 122 :  3F4;
+ 123 :  3F3;
+ 124 :  3F3;
+ 125 :  3F2;
+ 126 :  3F1;
+ 127 :  3F0;
+ 128 :  3F0;
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+ 12A :  3EE;
+ 12B :  3ED;
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+ 130 :  3E9;
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+ 13A :  3DF;
+ 13B :  3DE;
+ 13C :  3DD;
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+ 13E :  3DA;
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+ 140 :  3D8;
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+ 144 :  3D3;
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+ 14A :  3CB;
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+ 14C :  3C8;
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+ 150 :  3C3;
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+ 154 :  3BD;
+ 155 :  3BB;
+ 156 :  3B9;
+ 157 :  3B8;
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+ 15A :  3B3;
+ 15B :  3B1;
+ 15C :  3B0;
+ 15D :  3AE;
+ 15E :  3AC;
+ 15F :  3AB;
+ 160 :  3A9;
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+ 165 :  3A0;
+ 166 :  39E;
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+ 16A :  397;
+ 16B :  395;
+ 16C :  393;
+ 16D :  391;
+ 16E :  38F;
+ 16F :  38D;
+ 170 :  38B;
+ 171 :  389;
+ 172 :  387;
+ 173 :  385;
+ 174 :  383;
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+ 180 :  369;
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+ 18E :  349;
+ 18F :  346;
+ 190 :  344;
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+ 193 :  33D;
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+ 195 :  338;
+ 196 :  335;
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+ 198 :  330;
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+ 1C7 :  2AF;
+ 1C8 :  2AC;
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+ 1CD :  29D;
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+ 1D7 :  27F;
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+ 1DA :  276;
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+ 1FA :  212;
+ 1FB :  20F;
+ 1FC :  20C;
+ 1FD :  209;
+ 1FE :  206;
+ 1FF :  203;
+ 200 :  200;
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+ 203 :  1F6;
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+ 2D8 :    F;
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+ 2DA :    E;
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+ 2E1 :    9;
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+ 2E3 :    8;
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+ 2E9 :    5;
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+ 2EB :    4;
+ 2EC :    4;
+ 2ED :    3;
+ 2EE :    3;
+ 2EF :    3;
+ 2F0 :    2;
+ 2F1 :    2;
+ 2F2 :    2;
+ 2F3 :    2;
+ 2F4 :    1;
+ 2F5 :    1;
+ 2F6 :    1;
+ 2F7 :    1;
+ 2F8 :    1;
+ 2F9 :    0;
+ 2FA :    0;
+ 2FB :    0;
+ 2FC :    0;
+ 2FD :    0;
+ 2FE :    0;
+ 2FF :    0;
+ 300 :    0;
+ 301 :    0;
+ 302 :    0;
+ 303 :    0;
+ 304 :    0;
+ 305 :    0;
+ 306 :    0;
+ 307 :    0;
+ 308 :    1;
+ 309 :    1;
+ 30A :    1;
+ 30B :    1;
+ 30C :    1;
+ 30D :    2;
+ 30E :    2;
+ 30F :    2;
+ 310 :    2;
+ 311 :    3;
+ 312 :    3;
+ 313 :    3;
+ 314 :    4;
+ 315 :    4;
+ 316 :    5;
+ 317 :    5;
+ 318 :    6;
+ 319 :    6;
+ 31A :    6;
+ 31B :    7;
+ 31C :    8;
+ 31D :    8;
+ 31E :    9;
+ 31F :    9;
+ 320 :    A;
+ 321 :    A;
+ 322 :    B;
+ 323 :    C;
+ 324 :    C;
+ 325 :    D;
+ 326 :    E;
+ 327 :    F;
+ 328 :    F;
+ 329 :   10;
+ 32A :   11;
+ 32B :   12;
+ 32C :   13;
+ 32D :   13;
+ 32E :   14;
+ 32F :   15;
+ 330 :   16;
+ 331 :   17;
+ 332 :   18;
+ 333 :   19;
+ 334 :   1A;
+ 335 :   1B;
+ 336 :   1C;
+ 337 :   1D;
+ 338 :   1E;
+ 339 :   1F;
+ 33A :   20;
+ 33B :   21;
+ 33C :   22;
+ 33D :   23;
+ 33E :   25;
+ 33F :   26;
+ 340 :   27;
+ 341 :   28;
+ 342 :   29;
+ 343 :   2B;
+ 344 :   2C;
+ 345 :   2D;
+ 346 :   2E;
+ 347 :   30;
+ 348 :   31;
+ 349 :   32;
+ 34A :   34;
+ 34B :   35;
+ 34C :   37;
+ 34D :   38;
+ 34E :   39;
+ 34F :   3B;
+ 350 :   3C;
+ 351 :   3E;
+ 352 :   3F;
+ 353 :   41;
+ 354 :   42;
+ 355 :   44;
+ 356 :   46;
+ 357 :   47;
+ 358 :   49;
+ 359 :   4A;
+ 35A :   4C;
+ 35B :   4E;
+ 35C :   4F;
+ 35D :   51;
+ 35E :   53;
+ 35F :   54;
+ 360 :   56;
+ 361 :   58;
+ 362 :   5A;
+ 363 :   5C;
+ 364 :   5D;
+ 365 :   5F;
+ 366 :   61;
+ 367 :   63;
+ 368 :   65;
+ 369 :   67;
+ 36A :   68;
+ 36B :   6A;
+ 36C :   6C;
+ 36D :   6E;
+ 36E :   70;
+ 36F :   72;
+ 370 :   74;
+ 371 :   76;
+ 372 :   78;
+ 373 :   7A;
+ 374 :   7C;
+ 375 :   7E;
+ 376 :   80;
+ 377 :   82;
+ 378 :   85;
+ 379 :   87;
+ 37A :   89;
+ 37B :   8B;
+ 37C :   8D;
+ 37D :   8F;
+ 37E :   91;
+ 37F :   94;
+ 380 :   96;
+ 381 :   98;
+ 382 :   9A;
+ 383 :   9D;
+ 384 :   9F;
+ 385 :   A1;
+ 386 :   A3;
+ 387 :   A6;
+ 388 :   A8;
+ 389 :   AA;
+ 38A :   AD;
+ 38B :   AF;
+ 38C :   B1;
+ 38D :   B4;
+ 38E :   B6;
+ 38F :   B9;
+ 390 :   BB;
+ 391 :   BD;
+ 392 :   C0;
+ 393 :   C2;
+ 394 :   C5;
+ 395 :   C7;
+ 396 :   CA;
+ 397 :   CC;
+ 398 :   CF;
+ 399 :   D1;
+ 39A :   D4;
+ 39B :   D6;
+ 39C :   D9;
+ 39D :   DC;
+ 39E :   DE;
+ 39F :   E1;
+ 3A0 :   E3;
+ 3A1 :   E6;
+ 3A2 :   E9;
+ 3A3 :   EB;
+ 3A4 :   EE;
+ 3A5 :   F1;
+ 3A6 :   F3;
+ 3A7 :   F6;
+ 3A8 :   F9;
+ 3A9 :   FB;
+ 3AA :   FE;
+ 3AB :  101;
+ 3AC :  103;
+ 3AD :  106;
+ 3AE :  109;
+ 3AF :  10C;
+ 3B0 :  10E;
+ 3B1 :  111;
+ 3B2 :  114;
+ 3B3 :  117;
+ 3B4 :  11A;
+ 3B5 :  11C;
+ 3B6 :  11F;
+ 3B7 :  122;
+ 3B8 :  125;
+ 3B9 :  128;
+ 3BA :  12A;
+ 3BB :  12D;
+ 3BC :  130;
+ 3BD :  133;
+ 3BE :  136;
+ 3BF :  139;
+ 3C0 :  13C;
+ 3C1 :  13F;
+ 3C2 :  142;
+ 3C3 :  144;
+ 3C4 :  147;
+ 3C5 :  14A;
+ 3C6 :  14D;
+ 3C7 :  150;
+ 3C8 :  153;
+ 3C9 :  156;
+ 3CA :  159;
+ 3CB :  15C;
+ 3CC :  15F;
+ 3CD :  162;
+ 3CE :  165;
+ 3CF :  168;
+ 3D0 :  16B;
+ 3D1 :  16E;
+ 3D2 :  171;
+ 3D3 :  174;
+ 3D4 :  177;
+ 3D5 :  17A;
+ 3D6 :  17D;
+ 3D7 :  180;
+ 3D8 :  183;
+ 3D9 :  186;
+ 3DA :  189;
+ 3DB :  18C;
+ 3DC :  18F;
+ 3DD :  192;
+ 3DE :  196;
+ 3DF :  199;
+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex12/sin_gen_scripts/sinegen.m b/part_3/ex12/sin_gen_scripts/sinegen.m
index f459f5c..1c0f400 100755
--- a/part_3/ex12/sin_gen_scripts/sinegen.m
+++ b/part_3/ex12/sin_gen_scripts/sinegen.m
@@ -1,43 +1,43 @@
-% Purpose:  MATLAB script to produce contents of a ROM that stores
-%           one cycle of sinewave
-% Inputs:   None
-% Outputs:  rom_data.mif file
-% Author:   Peter Cheung
-% Version: 	1.0
-% Date:			20 Nov 2011
-	
-DEPTH = 1024;		% Size of ROM
-WIDTH = 10;			% Size of data in bits
-OUTMAX = 2^WIDTH - 1;	% Amplitude of sinewave
-
-filename = 'rom_data.mif';
-fid = fopen(filename,'w');
-
-fprintf(fid,'-- ROM Initialization file\n');
-fprintf(fid,'WIDTH = %d;\n',WIDTH);
-fprintf(fid,'DEPTH = %d;\n',DEPTH);
-fprintf(fid,'ADDRESS_RADIX = HEX;\n');
-fprintf(fid,'DATA_RADIX = HEX;\n');
-fprintf(fid,'CONTENT\nBEGIN\n');
-
-for address = 0:1023
-	angle = (address*2*pi)/DEPTH;
-	sine_value = sin(angle);
-	data = (sine_value*0.5*OUTMAX) + OUTMAX*0.5;
-	
-	fprintf(fid,'%4X : %4X;\n',address,int16(data));
-end
-
-fprintf(fid,'END\n');
-fclose(fid);
-disp('Finished');
-
-
-
-
-
-
-
-
-
-
+% Purpose:  MATLAB script to produce contents of a ROM that stores
+%           one cycle of sinewave
+% Inputs:   None
+% Outputs:  rom_data.mif file
+% Author:   Peter Cheung
+% Version: 	1.0
+% Date:			20 Nov 2011
+	
+DEPTH = 1024;		% Size of ROM
+WIDTH = 10;			% Size of data in bits
+OUTMAX = 2^WIDTH - 1;	% Amplitude of sinewave
+
+filename = 'rom_data.mif';
+fid = fopen(filename,'w');
+
+fprintf(fid,'-- ROM Initialization file\n');
+fprintf(fid,'WIDTH = %d;\n',WIDTH);
+fprintf(fid,'DEPTH = %d;\n',DEPTH);
+fprintf(fid,'ADDRESS_RADIX = HEX;\n');
+fprintf(fid,'DATA_RADIX = HEX;\n');
+fprintf(fid,'CONTENT\nBEGIN\n');
+
+for address = 0:1023
+	angle = (address*2*pi)/DEPTH;
+	sine_value = sin(angle);
+	data = (sine_value*0.5*OUTMAX) + OUTMAX*0.5;
+	
+	fprintf(fid,'%4X : %4X;\n',address,int16(data));
+end
+
+fprintf(fid,'END\n');
+fclose(fid);
+disp('Finished');
+
+
+
+
+
+
+
+
+
+
diff --git a/part_3/ex12/sin_gen_scripts/sinegen.py b/part_3/ex12/sin_gen_scripts/sinegen.py
index f0318d8..9dba855 100755
--- a/part_3/ex12/sin_gen_scripts/sinegen.py
+++ b/part_3/ex12/sin_gen_scripts/sinegen.py
@@ -1,33 +1,33 @@
-# sinegen.py - Generate sinewave table
-#  ... for use with Altera ROMs
-# 
-from math import sin, cos, radians
-
-DEPTH = 1024  # Size of ROM
-WIDTH = 10   # Size of data in bits
-OUTMAX = 2**WIDTH - 1   # Amplitude of sinewave
-
-filename = "rom_data.mif"
-f = open(filename,'w')
-
-#  Header for the .mif file
-print >> f, "-- ROM Initialization file\n"
-print >> f, "DEPTH = %d;" % DEPTH
-print >> f, "WIDTH = %d;" % WIDTH
-print >> f, "ADDRESS_RADIX = HEX;"
-print >> f, "DATA_RADIX = HEX;\n"
-print >> f, "CONTENT\nBEGIN\n"
-
-for address in range(DEPTH):
-	angle = (address*2*pi)/DEPTH
-	sine_value = sin(angle)
-	data = int((sine_value)*0.5*OUTMAX)+OUTMAX/2
-	
-	print "%4x : %4x;" % (address, data)
-	print >> f, "%4x : %4x;" % (address, data)
-
-print >> f, "END;\n"
-
-f.close()
-
-
+# sinegen.py - Generate sinewave table
+#  ... for use with Altera ROMs
+# 
+from math import sin, cos, radians
+
+DEPTH = 1024  # Size of ROM
+WIDTH = 10   # Size of data in bits
+OUTMAX = 2**WIDTH - 1   # Amplitude of sinewave
+
+filename = "rom_data.mif"
+f = open(filename,'w')
+
+#  Header for the .mif file
+print >> f, "-- ROM Initialization file\n"
+print >> f, "DEPTH = %d;" % DEPTH
+print >> f, "WIDTH = %d;" % WIDTH
+print >> f, "ADDRESS_RADIX = HEX;"
+print >> f, "DATA_RADIX = HEX;\n"
+print >> f, "CONTENT\nBEGIN\n"
+
+for address in range(DEPTH):
+	angle = (address*2*pi)/DEPTH
+	sine_value = sin(angle)
+	data = int((sine_value)*0.5*OUTMAX)+OUTMAX/2
+	
+	print "%4x : %4x;" % (address, data)
+	print >> f, "%4x : %4x;" % (address, data)
+
+print >> f, "END;\n"
+
+f.close()
+
+
diff --git a/part_3/ex13/.qsys_edit/filters.xml b/part_3/ex13/.qsys_edit/filters.xml
index 25484e0..2c6ab93 100755
--- a/part_3/ex13/.qsys_edit/filters.xml
+++ b/part_3/ex13/.qsys_edit/filters.xml
@@ -1,2 +1,2 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<filters version="16.0" />
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="16.0" />
diff --git a/part_3/ex13/.qsys_edit/preferences.xml b/part_3/ex13/.qsys_edit/preferences.xml
index ea0fb24..c5b7680 100755
--- a/part_3/ex13/.qsys_edit/preferences.xml
+++ b/part_3/ex13/.qsys_edit/preferences.xml
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<preferences>
- <debug showDebugMenu="0" />
- <systemtable filter="All Interfaces">
-  <columns>
-   <connections preferredWidth="47" />
-   <irq preferredWidth="34" />
-  </columns>
- </systemtable>
- <library expandedCategories="Project,Library" />
- <window width="1100" height="800" x="0" y="0" />
-</preferences>
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="47" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1100" height="800" x="0" y="0" />
+</preferences>
diff --git a/part_3/ex13/db/_cmp.kpt b/part_3/ex13/db/_cmp.kpt
deleted file mode 100644
index 957fbc6..0000000
--- a/part_3/ex13/db/_cmp.kpt
+++ /dev/null
diff --git a/part_3/ex13/ex10.v.bak b/part_3/ex13/ex10.v.bak
index d3f5a12..8b13789 100755
--- a/part_3/ex13/ex10.v.bak
+++ b/part_3/ex13/ex10.v.bak
@@ -1 +1 @@
-
+
diff --git a/part_3/ex13/rom_data/rom_data.mif b/part_3/ex13/rom_data/rom_data.mif
index 45464a9..a688b6f 100755
--- a/part_3/ex13/rom_data/rom_data.mif
+++ b/part_3/ex13/rom_data/rom_data.mif
@@ -1,1032 +1,1032 @@
--- ROM Initialization file
-WIDTH = 10;
-DEPTH = 1024;
-ADDRESS_RADIX = HEX;
-DATA_RADIX = HEX;
-CONTENT
-BEGIN
-   0 :  200;
-   1 :  203;
-   2 :  206;
-   3 :  209;
-   4 :  20C;
-   5 :  20F;
-   6 :  212;
-   7 :  215;
-   8 :  219;
-   9 :  21C;
-   A :  21F;
-   B :  222;
-   C :  225;
-   D :  228;
-   E :  22B;
-   F :  22F;
-  10 :  232;
-  11 :  235;
-  12 :  238;
-  13 :  23B;
-  14 :  23E;
-  15 :  241;
-  16 :  244;
-  17 :  247;
-  18 :  24B;
-  19 :  24E;
-  1A :  251;
-  1B :  254;
-  1C :  257;
-  1D :  25A;
-  1E :  25D;
-  1F :  260;
-  20 :  263;
-  21 :  266;
-  22 :  269;
-  23 :  26D;
-  24 :  270;
-  25 :  273;
-  26 :  276;
-  27 :  279;
-  28 :  27C;
-  29 :  27F;
-  2A :  282;
-  2B :  285;
-  2C :  288;
-  2D :  28B;
-  2E :  28E;
-  2F :  291;
-  30 :  294;
-  31 :  297;
-  32 :  29A;
-  33 :  29D;
-  34 :  2A0;
-  35 :  2A3;
-  36 :  2A6;
-  37 :  2A9;
-  38 :  2AC;
-  39 :  2AF;
-  3A :  2B2;
-  3B :  2B5;
-  3C :  2B8;
-  3D :  2BB;
-  3E :  2BD;
-  3F :  2C0;
-  40 :  2C3;
-  41 :  2C6;
-  42 :  2C9;
-  43 :  2CC;
-  44 :  2CF;
-  45 :  2D2;
-  46 :  2D5;
-  47 :  2D7;
-  48 :  2DA;
-  49 :  2DD;
-  4A :  2E0;
-  4B :  2E3;
-  4C :  2E5;
-  4D :  2E8;
-  4E :  2EB;
-  4F :  2EE;
-  50 :  2F1;
-  51 :  2F3;
-  52 :  2F6;
-  53 :  2F9;
-  54 :  2FC;
-  55 :  2FE;
-  56 :  301;
-  57 :  304;
-  58 :  306;
-  59 :  309;
-  5A :  30C;
-  5B :  30E;
-  5C :  311;
-  5D :  314;
-  5E :  316;
-  5F :  319;
-  60 :  31C;
-  61 :  31E;
-  62 :  321;
-  63 :  323;
-  64 :  326;
-  65 :  329;
-  66 :  32B;
-  67 :  32E;
-  68 :  330;
-  69 :  333;
-  6A :  335;
-  6B :  338;
-  6C :  33A;
-  6D :  33D;
-  6E :  33F;
-  6F :  342;
-  70 :  344;
-  71 :  346;
-  72 :  349;
-  73 :  34B;
-  74 :  34E;
-  75 :  350;
-  76 :  352;
-  77 :  355;
-  78 :  357;
-  79 :  359;
-  7A :  35C;
-  7B :  35E;
-  7C :  360;
-  7D :  362;
-  7E :  365;
-  7F :  367;
-  80 :  369;
-  81 :  36B;
-  82 :  36E;
-  83 :  370;
-  84 :  372;
-  85 :  374;
-  86 :  376;
-  87 :  378;
-  88 :  37A;
-  89 :  37D;
-  8A :  37F;
-  8B :  381;
-  8C :  383;
-  8D :  385;
-  8E :  387;
-  8F :  389;
-  90 :  38B;
-  91 :  38D;
-  92 :  38F;
-  93 :  391;
-  94 :  393;
-  95 :  395;
-  96 :  397;
-  97 :  398;
-  98 :  39A;
-  99 :  39C;
-  9A :  39E;
-  9B :  3A0;
-  9C :  3A2;
-  9D :  3A3;
-  9E :  3A5;
-  9F :  3A7;
-  A0 :  3A9;
-  A1 :  3AB;
-  A2 :  3AC;
-  A3 :  3AE;
-  A4 :  3B0;
-  A5 :  3B1;
-  A6 :  3B3;
-  A7 :  3B5;
-  A8 :  3B6;
-  A9 :  3B8;
-  AA :  3B9;
-  AB :  3BB;
-  AC :  3BD;
-  AD :  3BE;
-  AE :  3C0;
-  AF :  3C1;
-  B0 :  3C3;
-  B1 :  3C4;
-  B2 :  3C6;
-  B3 :  3C7;
-  B4 :  3C8;
-  B5 :  3CA;
-  B6 :  3CB;
-  B7 :  3CD;
-  B8 :  3CE;
-  B9 :  3CF;
-  BA :  3D1;
-  BB :  3D2;
-  BC :  3D3;
-  BD :  3D4;
-  BE :  3D6;
-  BF :  3D7;
-  C0 :  3D8;
-  C1 :  3D9;
-  C2 :  3DA;
-  C3 :  3DC;
-  C4 :  3DD;
-  C5 :  3DE;
-  C6 :  3DF;
-  C7 :  3E0;
-  C8 :  3E1;
-  C9 :  3E2;
-  CA :  3E3;
-  CB :  3E4;
-  CC :  3E5;
-  CD :  3E6;
-  CE :  3E7;
-  CF :  3E8;
-  D0 :  3E9;
-  D1 :  3EA;
-  D2 :  3EB;
-  D3 :  3EC;
-  D4 :  3EC;
-  D5 :  3ED;
-  D6 :  3EE;
-  D7 :  3EF;
-  D8 :  3F0;
-  D9 :  3F0;
-  DA :  3F1;
-  DB :  3F2;
-  DC :  3F3;
-  DD :  3F3;
-  DE :  3F4;
-  DF :  3F5;
-  E0 :  3F5;
-  E1 :  3F6;
-  E2 :  3F6;
-  E3 :  3F7;
-  E4 :  3F7;
-  E5 :  3F8;
-  E6 :  3F9;
-  E7 :  3F9;
-  E8 :  3F9;
-  E9 :  3FA;
-  EA :  3FA;
-  EB :  3FB;
-  EC :  3FB;
-  ED :  3FC;
-  EE :  3FC;
-  EF :  3FC;
-  F0 :  3FD;
-  F1 :  3FD;
-  F2 :  3FD;
-  F3 :  3FD;
-  F4 :  3FE;
-  F5 :  3FE;
-  F6 :  3FE;
-  F7 :  3FE;
-  F8 :  3FE;
-  F9 :  3FF;
-  FA :  3FF;
-  FB :  3FF;
-  FC :  3FF;
-  FD :  3FF;
-  FE :  3FF;
-  FF :  3FF;
- 100 :  3FF;
- 101 :  3FF;
- 102 :  3FF;
- 103 :  3FF;
- 104 :  3FF;
- 105 :  3FF;
- 106 :  3FF;
- 107 :  3FF;
- 108 :  3FE;
- 109 :  3FE;
- 10A :  3FE;
- 10B :  3FE;
- 10C :  3FE;
- 10D :  3FD;
- 10E :  3FD;
- 10F :  3FD;
- 110 :  3FD;
- 111 :  3FC;
- 112 :  3FC;
- 113 :  3FC;
- 114 :  3FB;
- 115 :  3FB;
- 116 :  3FA;
- 117 :  3FA;
- 118 :  3F9;
- 119 :  3F9;
- 11A :  3F9;
- 11B :  3F8;
- 11C :  3F7;
- 11D :  3F7;
- 11E :  3F6;
- 11F :  3F6;
- 120 :  3F5;
- 121 :  3F5;
- 122 :  3F4;
- 123 :  3F3;
- 124 :  3F3;
- 125 :  3F2;
- 126 :  3F1;
- 127 :  3F0;
- 128 :  3F0;
- 129 :  3EF;
- 12A :  3EE;
- 12B :  3ED;
- 12C :  3EC;
- 12D :  3EC;
- 12E :  3EB;
- 12F :  3EA;
- 130 :  3E9;
- 131 :  3E8;
- 132 :  3E7;
- 133 :  3E6;
- 134 :  3E5;
- 135 :  3E4;
- 136 :  3E3;
- 137 :  3E2;
- 138 :  3E1;
- 139 :  3E0;
- 13A :  3DF;
- 13B :  3DE;
- 13C :  3DD;
- 13D :  3DC;
- 13E :  3DA;
- 13F :  3D9;
- 140 :  3D8;
- 141 :  3D7;
- 142 :  3D6;
- 143 :  3D4;
- 144 :  3D3;
- 145 :  3D2;
- 146 :  3D1;
- 147 :  3CF;
- 148 :  3CE;
- 149 :  3CD;
- 14A :  3CB;
- 14B :  3CA;
- 14C :  3C8;
- 14D :  3C7;
- 14E :  3C6;
- 14F :  3C4;
- 150 :  3C3;
- 151 :  3C1;
- 152 :  3C0;
- 153 :  3BE;
- 154 :  3BD;
- 155 :  3BB;
- 156 :  3B9;
- 157 :  3B8;
- 158 :  3B6;
- 159 :  3B5;
- 15A :  3B3;
- 15B :  3B1;
- 15C :  3B0;
- 15D :  3AE;
- 15E :  3AC;
- 15F :  3AB;
- 160 :  3A9;
- 161 :  3A7;
- 162 :  3A5;
- 163 :  3A3;
- 164 :  3A2;
- 165 :  3A0;
- 166 :  39E;
- 167 :  39C;
- 168 :  39A;
- 169 :  398;
- 16A :  397;
- 16B :  395;
- 16C :  393;
- 16D :  391;
- 16E :  38F;
- 16F :  38D;
- 170 :  38B;
- 171 :  389;
- 172 :  387;
- 173 :  385;
- 174 :  383;
- 175 :  381;
- 176 :  37F;
- 177 :  37D;
- 178 :  37A;
- 179 :  378;
- 17A :  376;
- 17B :  374;
- 17C :  372;
- 17D :  370;
- 17E :  36E;
- 17F :  36B;
- 180 :  369;
- 181 :  367;
- 182 :  365;
- 183 :  362;
- 184 :  360;
- 185 :  35E;
- 186 :  35C;
- 187 :  359;
- 188 :  357;
- 189 :  355;
- 18A :  352;
- 18B :  350;
- 18C :  34E;
- 18D :  34B;
- 18E :  349;
- 18F :  346;
- 190 :  344;
- 191 :  342;
- 192 :  33F;
- 193 :  33D;
- 194 :  33A;
- 195 :  338;
- 196 :  335;
- 197 :  333;
- 198 :  330;
- 199 :  32E;
- 19A :  32B;
- 19B :  329;
- 19C :  326;
- 19D :  323;
- 19E :  321;
- 19F :  31E;
- 1A0 :  31C;
- 1A1 :  319;
- 1A2 :  316;
- 1A3 :  314;
- 1A4 :  311;
- 1A5 :  30E;
- 1A6 :  30C;
- 1A7 :  309;
- 1A8 :  306;
- 1A9 :  304;
- 1AA :  301;
- 1AB :  2FE;
- 1AC :  2FC;
- 1AD :  2F9;
- 1AE :  2F6;
- 1AF :  2F3;
- 1B0 :  2F1;
- 1B1 :  2EE;
- 1B2 :  2EB;
- 1B3 :  2E8;
- 1B4 :  2E5;
- 1B5 :  2E3;
- 1B6 :  2E0;
- 1B7 :  2DD;
- 1B8 :  2DA;
- 1B9 :  2D7;
- 1BA :  2D5;
- 1BB :  2D2;
- 1BC :  2CF;
- 1BD :  2CC;
- 1BE :  2C9;
- 1BF :  2C6;
- 1C0 :  2C3;
- 1C1 :  2C0;
- 1C2 :  2BD;
- 1C3 :  2BB;
- 1C4 :  2B8;
- 1C5 :  2B5;
- 1C6 :  2B2;
- 1C7 :  2AF;
- 1C8 :  2AC;
- 1C9 :  2A9;
- 1CA :  2A6;
- 1CB :  2A3;
- 1CC :  2A0;
- 1CD :  29D;
- 1CE :  29A;
- 1CF :  297;
- 1D0 :  294;
- 1D1 :  291;
- 1D2 :  28E;
- 1D3 :  28B;
- 1D4 :  288;
- 1D5 :  285;
- 1D6 :  282;
- 1D7 :  27F;
- 1D8 :  27C;
- 1D9 :  279;
- 1DA :  276;
- 1DB :  273;
- 1DC :  270;
- 1DD :  26D;
- 1DE :  269;
- 1DF :  266;
- 1E0 :  263;
- 1E1 :  260;
- 1E2 :  25D;
- 1E3 :  25A;
- 1E4 :  257;
- 1E5 :  254;
- 1E6 :  251;
- 1E7 :  24E;
- 1E8 :  24B;
- 1E9 :  247;
- 1EA :  244;
- 1EB :  241;
- 1EC :  23E;
- 1ED :  23B;
- 1EE :  238;
- 1EF :  235;
- 1F0 :  232;
- 1F1 :  22F;
- 1F2 :  22B;
- 1F3 :  228;
- 1F4 :  225;
- 1F5 :  222;
- 1F6 :  21F;
- 1F7 :  21C;
- 1F8 :  219;
- 1F9 :  215;
- 1FA :  212;
- 1FB :  20F;
- 1FC :  20C;
- 1FD :  209;
- 1FE :  206;
- 1FF :  203;
- 200 :  200;
- 201 :  1FC;
- 202 :  1F9;
- 203 :  1F6;
- 204 :  1F3;
- 205 :  1F0;
- 206 :  1ED;
- 207 :  1EA;
- 208 :  1E6;
- 209 :  1E3;
- 20A :  1E0;
- 20B :  1DD;
- 20C :  1DA;
- 20D :  1D7;
- 20E :  1D4;
- 20F :  1D0;
- 210 :  1CD;
- 211 :  1CA;
- 212 :  1C7;
- 213 :  1C4;
- 214 :  1C1;
- 215 :  1BE;
- 216 :  1BB;
- 217 :  1B8;
- 218 :  1B4;
- 219 :  1B1;
- 21A :  1AE;
- 21B :  1AB;
- 21C :  1A8;
- 21D :  1A5;
- 21E :  1A2;
- 21F :  19F;
- 220 :  19C;
- 221 :  199;
- 222 :  196;
- 223 :  192;
- 224 :  18F;
- 225 :  18C;
- 226 :  189;
- 227 :  186;
- 228 :  183;
- 229 :  180;
- 22A :  17D;
- 22B :  17A;
- 22C :  177;
- 22D :  174;
- 22E :  171;
- 22F :  16E;
- 230 :  16B;
- 231 :  168;
- 232 :  165;
- 233 :  162;
- 234 :  15F;
- 235 :  15C;
- 236 :  159;
- 237 :  156;
- 238 :  153;
- 239 :  150;
- 23A :  14D;
- 23B :  14A;
- 23C :  147;
- 23D :  144;
- 23E :  142;
- 23F :  13F;
- 240 :  13C;
- 241 :  139;
- 242 :  136;
- 243 :  133;
- 244 :  130;
- 245 :  12D;
- 246 :  12A;
- 247 :  128;
- 248 :  125;
- 249 :  122;
- 24A :  11F;
- 24B :  11C;
- 24C :  11A;
- 24D :  117;
- 24E :  114;
- 24F :  111;
- 250 :  10E;
- 251 :  10C;
- 252 :  109;
- 253 :  106;
- 254 :  103;
- 255 :  101;
- 256 :   FE;
- 257 :   FB;
- 258 :   F9;
- 259 :   F6;
- 25A :   F3;
- 25B :   F1;
- 25C :   EE;
- 25D :   EB;
- 25E :   E9;
- 25F :   E6;
- 260 :   E3;
- 261 :   E1;
- 262 :   DE;
- 263 :   DC;
- 264 :   D9;
- 265 :   D6;
- 266 :   D4;
- 267 :   D1;
- 268 :   CF;
- 269 :   CC;
- 26A :   CA;
- 26B :   C7;
- 26C :   C5;
- 26D :   C2;
- 26E :   C0;
- 26F :   BD;
- 270 :   BB;
- 271 :   B9;
- 272 :   B6;
- 273 :   B4;
- 274 :   B1;
- 275 :   AF;
- 276 :   AD;
- 277 :   AA;
- 278 :   A8;
- 279 :   A6;
- 27A :   A3;
- 27B :   A1;
- 27C :   9F;
- 27D :   9D;
- 27E :   9A;
- 27F :   98;
- 280 :   96;
- 281 :   94;
- 282 :   91;
- 283 :   8F;
- 284 :   8D;
- 285 :   8B;
- 286 :   89;
- 287 :   87;
- 288 :   85;
- 289 :   82;
- 28A :   80;
- 28B :   7E;
- 28C :   7C;
- 28D :   7A;
- 28E :   78;
- 28F :   76;
- 290 :   74;
- 291 :   72;
- 292 :   70;
- 293 :   6E;
- 294 :   6C;
- 295 :   6A;
- 296 :   68;
- 297 :   67;
- 298 :   65;
- 299 :   63;
- 29A :   61;
- 29B :   5F;
- 29C :   5D;
- 29D :   5C;
- 29E :   5A;
- 29F :   58;
- 2A0 :   56;
- 2A1 :   54;
- 2A2 :   53;
- 2A3 :   51;
- 2A4 :   4F;
- 2A5 :   4E;
- 2A6 :   4C;
- 2A7 :   4A;
- 2A8 :   49;
- 2A9 :   47;
- 2AA :   46;
- 2AB :   44;
- 2AC :   42;
- 2AD :   41;
- 2AE :   3F;
- 2AF :   3E;
- 2B0 :   3C;
- 2B1 :   3B;
- 2B2 :   39;
- 2B3 :   38;
- 2B4 :   37;
- 2B5 :   35;
- 2B6 :   34;
- 2B7 :   32;
- 2B8 :   31;
- 2B9 :   30;
- 2BA :   2E;
- 2BB :   2D;
- 2BC :   2C;
- 2BD :   2B;
- 2BE :   29;
- 2BF :   28;
- 2C0 :   27;
- 2C1 :   26;
- 2C2 :   25;
- 2C3 :   23;
- 2C4 :   22;
- 2C5 :   21;
- 2C6 :   20;
- 2C7 :   1F;
- 2C8 :   1E;
- 2C9 :   1D;
- 2CA :   1C;
- 2CB :   1B;
- 2CC :   1A;
- 2CD :   19;
- 2CE :   18;
- 2CF :   17;
- 2D0 :   16;
- 2D1 :   15;
- 2D2 :   14;
- 2D3 :   13;
- 2D4 :   13;
- 2D5 :   12;
- 2D6 :   11;
- 2D7 :   10;
- 2D8 :    F;
- 2D9 :    F;
- 2DA :    E;
- 2DB :    D;
- 2DC :    C;
- 2DD :    C;
- 2DE :    B;
- 2DF :    A;
- 2E0 :    A;
- 2E1 :    9;
- 2E2 :    9;
- 2E3 :    8;
- 2E4 :    8;
- 2E5 :    7;
- 2E6 :    6;
- 2E7 :    6;
- 2E8 :    6;
- 2E9 :    5;
- 2EA :    5;
- 2EB :    4;
- 2EC :    4;
- 2ED :    3;
- 2EE :    3;
- 2EF :    3;
- 2F0 :    2;
- 2F1 :    2;
- 2F2 :    2;
- 2F3 :    2;
- 2F4 :    1;
- 2F5 :    1;
- 2F6 :    1;
- 2F7 :    1;
- 2F8 :    1;
- 2F9 :    0;
- 2FA :    0;
- 2FB :    0;
- 2FC :    0;
- 2FD :    0;
- 2FE :    0;
- 2FF :    0;
- 300 :    0;
- 301 :    0;
- 302 :    0;
- 303 :    0;
- 304 :    0;
- 305 :    0;
- 306 :    0;
- 307 :    0;
- 308 :    1;
- 309 :    1;
- 30A :    1;
- 30B :    1;
- 30C :    1;
- 30D :    2;
- 30E :    2;
- 30F :    2;
- 310 :    2;
- 311 :    3;
- 312 :    3;
- 313 :    3;
- 314 :    4;
- 315 :    4;
- 316 :    5;
- 317 :    5;
- 318 :    6;
- 319 :    6;
- 31A :    6;
- 31B :    7;
- 31C :    8;
- 31D :    8;
- 31E :    9;
- 31F :    9;
- 320 :    A;
- 321 :    A;
- 322 :    B;
- 323 :    C;
- 324 :    C;
- 325 :    D;
- 326 :    E;
- 327 :    F;
- 328 :    F;
- 329 :   10;
- 32A :   11;
- 32B :   12;
- 32C :   13;
- 32D :   13;
- 32E :   14;
- 32F :   15;
- 330 :   16;
- 331 :   17;
- 332 :   18;
- 333 :   19;
- 334 :   1A;
- 335 :   1B;
- 336 :   1C;
- 337 :   1D;
- 338 :   1E;
- 339 :   1F;
- 33A :   20;
- 33B :   21;
- 33C :   22;
- 33D :   23;
- 33E :   25;
- 33F :   26;
- 340 :   27;
- 341 :   28;
- 342 :   29;
- 343 :   2B;
- 344 :   2C;
- 345 :   2D;
- 346 :   2E;
- 347 :   30;
- 348 :   31;
- 349 :   32;
- 34A :   34;
- 34B :   35;
- 34C :   37;
- 34D :   38;
- 34E :   39;
- 34F :   3B;
- 350 :   3C;
- 351 :   3E;
- 352 :   3F;
- 353 :   41;
- 354 :   42;
- 355 :   44;
- 356 :   46;
- 357 :   47;
- 358 :   49;
- 359 :   4A;
- 35A :   4C;
- 35B :   4E;
- 35C :   4F;
- 35D :   51;
- 35E :   53;
- 35F :   54;
- 360 :   56;
- 361 :   58;
- 362 :   5A;
- 363 :   5C;
- 364 :   5D;
- 365 :   5F;
- 366 :   61;
- 367 :   63;
- 368 :   65;
- 369 :   67;
- 36A :   68;
- 36B :   6A;
- 36C :   6C;
- 36D :   6E;
- 36E :   70;
- 36F :   72;
- 370 :   74;
- 371 :   76;
- 372 :   78;
- 373 :   7A;
- 374 :   7C;
- 375 :   7E;
- 376 :   80;
- 377 :   82;
- 378 :   85;
- 379 :   87;
- 37A :   89;
- 37B :   8B;
- 37C :   8D;
- 37D :   8F;
- 37E :   91;
- 37F :   94;
- 380 :   96;
- 381 :   98;
- 382 :   9A;
- 383 :   9D;
- 384 :   9F;
- 385 :   A1;
- 386 :   A3;
- 387 :   A6;
- 388 :   A8;
- 389 :   AA;
- 38A :   AD;
- 38B :   AF;
- 38C :   B1;
- 38D :   B4;
- 38E :   B6;
- 38F :   B9;
- 390 :   BB;
- 391 :   BD;
- 392 :   C0;
- 393 :   C2;
- 394 :   C5;
- 395 :   C7;
- 396 :   CA;
- 397 :   CC;
- 398 :   CF;
- 399 :   D1;
- 39A :   D4;
- 39B :   D6;
- 39C :   D9;
- 39D :   DC;
- 39E :   DE;
- 39F :   E1;
- 3A0 :   E3;
- 3A1 :   E6;
- 3A2 :   E9;
- 3A3 :   EB;
- 3A4 :   EE;
- 3A5 :   F1;
- 3A6 :   F3;
- 3A7 :   F6;
- 3A8 :   F9;
- 3A9 :   FB;
- 3AA :   FE;
- 3AB :  101;
- 3AC :  103;
- 3AD :  106;
- 3AE :  109;
- 3AF :  10C;
- 3B0 :  10E;
- 3B1 :  111;
- 3B2 :  114;
- 3B3 :  117;
- 3B4 :  11A;
- 3B5 :  11C;
- 3B6 :  11F;
- 3B7 :  122;
- 3B8 :  125;
- 3B9 :  128;
- 3BA :  12A;
- 3BB :  12D;
- 3BC :  130;
- 3BD :  133;
- 3BE :  136;
- 3BF :  139;
- 3C0 :  13C;
- 3C1 :  13F;
- 3C2 :  142;
- 3C3 :  144;
- 3C4 :  147;
- 3C5 :  14A;
- 3C6 :  14D;
- 3C7 :  150;
- 3C8 :  153;
- 3C9 :  156;
- 3CA :  159;
- 3CB :  15C;
- 3CC :  15F;
- 3CD :  162;
- 3CE :  165;
- 3CF :  168;
- 3D0 :  16B;
- 3D1 :  16E;
- 3D2 :  171;
- 3D3 :  174;
- 3D4 :  177;
- 3D5 :  17A;
- 3D6 :  17D;
- 3D7 :  180;
- 3D8 :  183;
- 3D9 :  186;
- 3DA :  189;
- 3DB :  18C;
- 3DC :  18F;
- 3DD :  192;
- 3DE :  196;
- 3DF :  199;
- 3E0 :  19C;
- 3E1 :  19F;
- 3E2 :  1A2;
- 3E3 :  1A5;
- 3E4 :  1A8;
- 3E5 :  1AB;
- 3E6 :  1AE;
- 3E7 :  1B1;
- 3E8 :  1B4;
- 3E9 :  1B8;
- 3EA :  1BB;
- 3EB :  1BE;
- 3EC :  1C1;
- 3ED :  1C4;
- 3EE :  1C7;
- 3EF :  1CA;
- 3F0 :  1CD;
- 3F1 :  1D0;
- 3F2 :  1D4;
- 3F3 :  1D7;
- 3F4 :  1DA;
- 3F5 :  1DD;
- 3F6 :  1E0;
- 3F7 :  1E3;
- 3F8 :  1E6;
- 3F9 :  1EA;
- 3FA :  1ED;
- 3FB :  1F0;
- 3FC :  1F3;
- 3FD :  1F6;
- 3FE :  1F9;
- 3FF :  1FC;
-END
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
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+ 3AF :  10C;
+ 3B0 :  10E;
+ 3B1 :  111;
+ 3B2 :  114;
+ 3B3 :  117;
+ 3B4 :  11A;
+ 3B5 :  11C;
+ 3B6 :  11F;
+ 3B7 :  122;
+ 3B8 :  125;
+ 3B9 :  128;
+ 3BA :  12A;
+ 3BB :  12D;
+ 3BC :  130;
+ 3BD :  133;
+ 3BE :  136;
+ 3BF :  139;
+ 3C0 :  13C;
+ 3C1 :  13F;
+ 3C2 :  142;
+ 3C3 :  144;
+ 3C4 :  147;
+ 3C5 :  14A;
+ 3C6 :  14D;
+ 3C7 :  150;
+ 3C8 :  153;
+ 3C9 :  156;
+ 3CA :  159;
+ 3CB :  15C;
+ 3CC :  15F;
+ 3CD :  162;
+ 3CE :  165;
+ 3CF :  168;
+ 3D0 :  16B;
+ 3D1 :  16E;
+ 3D2 :  171;
+ 3D3 :  174;
+ 3D4 :  177;
+ 3D5 :  17A;
+ 3D6 :  17D;
+ 3D7 :  180;
+ 3D8 :  183;
+ 3D9 :  186;
+ 3DA :  189;
+ 3DB :  18C;
+ 3DC :  18F;
+ 3DD :  192;
+ 3DE :  196;
+ 3DF :  199;
+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex13/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex13/simulation/modelsim/do_files/tb_spi2dac.do
index 52dd5a2..b12a7d7 100755
--- a/part_3/ex13/simulation/modelsim/do_files/tb_spi2dac.do
+++ b/part_3/ex13/simulation/modelsim/do_files/tb_spi2dac.do
@@ -1,17 +1,17 @@
-add wave -position end  sysclk
-add wave -position end -hexadecimal data_in
-add wave -position end load
-add wave -position end  dac_sdi
-add wave -position end  dac_cs
-add wave -position end  dac_sck
-add wave -position end  dac_ld
-force sysclk 1 0, 0 10ns -r 20ns
-force data_in 10'h23b
-force load 0
-run 200ns
-force load 1
-run 400ns
-force load 0
-run 20us
-
-
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex13/simulation/modelsim/rtl_work/_info b/part_3/ex13/simulation/modelsim/rtl_work/_info
index 63648ac..499bdd4 100755
--- a/part_3/ex13/simulation/modelsim/rtl_work/_info
+++ b/part_3/ex13/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\ex10\simulation\modelsim
-vspi2dac
-!i10b 1
-!s100 Yc_:?1WP<4LKj7cQXiUbl1
-IzTNjHgWKkeSFYc0]WM5Gm2
-VFNOGDa=aYhJTn=76LYB@A2
-Z1 dC:\New folder\ex10\simulation\modelsim
-w1478805578
-8C:/New folder/ex10/verilog_files/spi2dac.v
-FC:/New folder/ex10/verilog_files/spi2dac.v
-L0 9
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1480413939.783000
-!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex13/simulation/modelsim/rtl_work/_vmake b/part_3/ex13/simulation/modelsim/rtl_work/_vmake
index b51b305..2f7e729 100755
--- a/part_3/ex13/simulation/modelsim/rtl_work/_vmake
+++ b/part_3/ex13/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
index 2a503c0..e874ed3 100755
--- a/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
+++ b/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -1,30 +1,30 @@
-library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
-    generic(
-        BUF             : vl_logic := Hi1;
-        GA_N            : vl_logic := Hi1;
-        SHDN_N          : vl_logic := Hi1;
-        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
-        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
-        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
-        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
-    );
-    port(
-        sysclk          : in     vl_logic;
-        data_in         : in     vl_logic_vector(9 downto 0);
-        load            : in     vl_logic;
-        dac_sdi         : out    vl_logic;
-        dac_cs          : out    vl_logic;
-        dac_sck         : out    vl_logic;
-        dac_ld          : out    vl_logic
-    );
-    attribute mti_svvh_generic_type : integer;
-    attribute mti_svvh_generic_type of BUF : constant is 1;
-    attribute mti_svvh_generic_type of GA_N : constant is 1;
-    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
-    attribute mti_svvh_generic_type of TC : constant is 1;
-    attribute mti_svvh_generic_type of IDLE : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
-    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+    generic(
+        BUF             : vl_logic := Hi1;
+        GA_N            : vl_logic := Hi1;
+        SHDN_N          : vl_logic := Hi1;
+        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        data_in         : in     vl_logic_vector(9 downto 0);
+        load            : in     vl_logic;
+        dac_sdi         : out    vl_logic;
+        dac_cs          : out    vl_logic;
+        dac_sck         : out    vl_logic;
+        dac_ld          : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BUF : constant is 1;
+    attribute mti_svvh_generic_type of GA_N : constant is 1;
+    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+    attribute mti_svvh_generic_type of TC : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
diff --git a/part_3/ex14/.qsys_edit/filters.xml b/part_3/ex14/.qsys_edit/filters.xml
new file mode 100755
index 0000000..2c6ab93
--- /dev/null
+++ b/part_3/ex14/.qsys_edit/filters.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="16.0" />
diff --git a/part_3/ex14/.qsys_edit/preferences.xml b/part_3/ex14/.qsys_edit/preferences.xml
new file mode 100755
index 0000000..c5b7680
--- /dev/null
+++ b/part_3/ex14/.qsys_edit/preferences.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="47" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1100" height="800" x="0" y="0" />
+</preferences>
diff --git a/part_3/ex14/add_offset.v b/part_3/ex14/add_offset.v
new file mode 100755
index 0000000..02882fb
--- /dev/null
+++ b/part_3/ex14/add_offset.v
@@ -0,0 +1,14 @@
+module add_offset(keys, tick, address);
+
+	input [9:0] keys;
+	input tick;
+	output [9:0] address;
+	
+	reg [9:0] address;
+	
+	initial address = 10'b0;
+
+	always @ (posedge tick)
+		address = keys + address;
+
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex14/add_offset.v.bak b/part_3/ex14/add_offset.v.bak
new file mode 100755
index 0000000..fb7bf2f
--- /dev/null
+++ b/part_3/ex14/add_offset.v.bak
@@ -0,0 +1,16 @@
+module add_offset(keys, tick, address);
+
+	input [9:0] key;
+	input tick;
+	output [9:0] address;
+	
+	reg [9:0] address;
+	
+	initial address = 10'b0;
+
+	always @ (posedge tick)
+		address = key + address;
+
+
+
+endmodule
+\ No newline at end of file
diff --git a/part_2/ex9_final/c5_pin_model_dump.txt b/part_3/ex14/c5_pin_model_dump.txt
index a895a64..a895a64 100755
--- a/part_2/ex9_final/c5_pin_model_dump.txt
+++ b/part_3/ex14/c5_pin_model_dump.txt
diff --git a/part_3/ex14/const_mult.qip b/part_3/ex14/const_mult.qip
new file mode 100755
index 0000000..c806a73
--- /dev/null
+++ b/part_3/ex14/const_mult.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "const_mult.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "const_mult_bb.v"]
diff --git a/part_3/ex14/const_mult.v b/part_3/ex14/const_mult.v
new file mode 100755
index 0000000..e4b9ece
--- /dev/null
+++ b/part_3/ex14/const_mult.v
@@ -0,0 +1,109 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: const_mult.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Intel and sold by Intel or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module const_mult (
+	dataa,
+	result);
+
+	input	[9:0]  dataa;
+	output	[23:0]  result;
+
+	wire [13:0] sub_wire0 = 14'h2710;
+	wire [23:0] sub_wire1;
+	wire [23:0] result = sub_wire1[23:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (sub_wire0),
+				.result (sub_wire1),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sclr (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 10,
+		lpm_mult_component.lpm_widthb = 14,
+		lpm_mult_component.lpm_widthp = 24;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "10000"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "10"
+// Retrieval info: PRIVATE: WidthB NUMERIC "14"
+// Retrieval info: PRIVATE: WidthP NUMERIC "24"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "14"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "24"
+// Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
+// Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]"
+// Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
+// Retrieval info: CONNECT: @datab 0 0 14 0 10000 0 0 14 0
+// Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_3/ex14/const_mult_bb.v b/part_3/ex14/const_mult_bb.v
new file mode 100755
index 0000000..3cc17fb
--- /dev/null
+++ b/part_3/ex14/const_mult_bb.v
@@ -0,0 +1,82 @@
+// megafunction wizard: %LPM_MULT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: const_mult.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Intel and sold by Intel or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module const_mult (
+	dataa,
+	result);
+
+	input	[9:0]  dataa;
+	output	[23:0]  result;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "10000"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "10"
+// Retrieval info: PRIVATE: WidthB NUMERIC "14"
+// Retrieval info: PRIVATE: WidthP NUMERIC "24"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "14"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "24"
+// Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
+// Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]"
+// Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
+// Retrieval info: CONNECT: @datab 0 0 14 0 10000 0 0 14 0
+// Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_3/ex14/db/.cmp.kpt b/part_3/ex14/db/.cmp.kpt
new file mode 100755
index 0000000..e6e868b
--- /dev/null
+++ b/part_3/ex14/db/.cmp.kpt
diff --git a/part_3/ex14/db/add_sub_89h.tdf b/part_3/ex14/db/add_sub_89h.tdf
new file mode 100755
index 0000000..f2e4477
--- /dev/null
+++ b/part_3/ex14/db/add_sub_89h.tdf
@@ -0,0 +1,32 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=22 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+
+--synthesis_resources = lut 22 
+SUBDESIGN add_sub_89h
+( 
+	dataa[21..0]	:	input;
+	datab[21..0]	:	input;
+	result[21..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_3/ex14/db/add_sub_d9h.tdf b/part_3/ex14/db/add_sub_d9h.tdf
new file mode 100755
index 0000000..856ca69
--- /dev/null
+++ b/part_3/ex14/db/add_sub_d9h.tdf
@@ -0,0 +1,32 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=18 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+
+--synthesis_resources = lut 18 
+SUBDESIGN add_sub_d9h
+( 
+	dataa[17..0]	:	input;
+	datab[17..0]	:	input;
+	result[17..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_3/ex14/db/altsyncram_6ng1.tdf b/part_3/ex14/db/altsyncram_6ng1.tdf
new file mode 100755
index 0000000..e896d11
--- /dev/null
+++ b/part_3/ex14/db/altsyncram_6ng1.tdf
@@ -0,0 +1,264 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rom_data/rom_data.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=10 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 1 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_6ng1
+( 
+	address_a[9..0]	:	input;
+	clock0	:	input;
+	q_a[9..0]	:	output;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[9..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[9..0].clk0 = clock0;
+	ram_block1a[9..0].portaaddr[] = ( address_a_wire[9..0]);
+	ram_block1a[9..0].portare = B"1111111111";
+	address_a_wire[] = address_a[];
+	q_a[] = ( ram_block1a[9..0].portadataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_3/ex14/db/ex10.(0).cnf.cdb b/part_3/ex14/db/ex10.(0).cnf.cdb
new file mode 100755
index 0000000..120b3ec
--- /dev/null
+++ b/part_3/ex14/db/ex10.(0).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(0).cnf.hdb b/part_3/ex14/db/ex10.(0).cnf.hdb
new file mode 100755
index 0000000..2cd5ba1
--- /dev/null
+++ b/part_3/ex14/db/ex10.(0).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(1).cnf.cdb b/part_3/ex14/db/ex10.(1).cnf.cdb
new file mode 100755
index 0000000..1fae20c
--- /dev/null
+++ b/part_3/ex14/db/ex10.(1).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(1).cnf.hdb b/part_3/ex14/db/ex10.(1).cnf.hdb
new file mode 100755
index 0000000..6b05c48
--- /dev/null
+++ b/part_3/ex14/db/ex10.(1).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(10).cnf.cdb b/part_3/ex14/db/ex10.(10).cnf.cdb
new file mode 100755
index 0000000..61b41bc
--- /dev/null
+++ b/part_3/ex14/db/ex10.(10).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(10).cnf.hdb b/part_3/ex14/db/ex10.(10).cnf.hdb
new file mode 100755
index 0000000..36dfe60
--- /dev/null
+++ b/part_3/ex14/db/ex10.(10).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(11).cnf.cdb b/part_3/ex14/db/ex10.(11).cnf.cdb
new file mode 100755
index 0000000..393fe12
--- /dev/null
+++ b/part_3/ex14/db/ex10.(11).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(11).cnf.hdb b/part_3/ex14/db/ex10.(11).cnf.hdb
new file mode 100755
index 0000000..a00d33f
--- /dev/null
+++ b/part_3/ex14/db/ex10.(11).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(12).cnf.cdb b/part_3/ex14/db/ex10.(12).cnf.cdb
new file mode 100755
index 0000000..f0523ce
--- /dev/null
+++ b/part_3/ex14/db/ex10.(12).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(12).cnf.hdb b/part_3/ex14/db/ex10.(12).cnf.hdb
new file mode 100755
index 0000000..1de0a69
--- /dev/null
+++ b/part_3/ex14/db/ex10.(12).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(13).cnf.cdb b/part_3/ex14/db/ex10.(13).cnf.cdb
new file mode 100755
index 0000000..407b009
--- /dev/null
+++ b/part_3/ex14/db/ex10.(13).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(13).cnf.hdb b/part_3/ex14/db/ex10.(13).cnf.hdb
new file mode 100755
index 0000000..c1d581a
--- /dev/null
+++ b/part_3/ex14/db/ex10.(13).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(14).cnf.cdb b/part_3/ex14/db/ex10.(14).cnf.cdb
new file mode 100755
index 0000000..851bfcf
--- /dev/null
+++ b/part_3/ex14/db/ex10.(14).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(14).cnf.hdb b/part_3/ex14/db/ex10.(14).cnf.hdb
new file mode 100755
index 0000000..d912045
--- /dev/null
+++ b/part_3/ex14/db/ex10.(14).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(15).cnf.cdb b/part_3/ex14/db/ex10.(15).cnf.cdb
new file mode 100755
index 0000000..4b1c002
--- /dev/null
+++ b/part_3/ex14/db/ex10.(15).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(15).cnf.hdb b/part_3/ex14/db/ex10.(15).cnf.hdb
new file mode 100755
index 0000000..9d67b24
--- /dev/null
+++ b/part_3/ex14/db/ex10.(15).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(16).cnf.cdb b/part_3/ex14/db/ex10.(16).cnf.cdb
new file mode 100755
index 0000000..fb92522
--- /dev/null
+++ b/part_3/ex14/db/ex10.(16).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(16).cnf.hdb b/part_3/ex14/db/ex10.(16).cnf.hdb
new file mode 100755
index 0000000..d5f088a
--- /dev/null
+++ b/part_3/ex14/db/ex10.(16).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(17).cnf.cdb b/part_3/ex14/db/ex10.(17).cnf.cdb
new file mode 100755
index 0000000..6e08b89
--- /dev/null
+++ b/part_3/ex14/db/ex10.(17).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(17).cnf.hdb b/part_3/ex14/db/ex10.(17).cnf.hdb
new file mode 100755
index 0000000..692f4af
--- /dev/null
+++ b/part_3/ex14/db/ex10.(17).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(18).cnf.cdb b/part_3/ex14/db/ex10.(18).cnf.cdb
new file mode 100755
index 0000000..54f5d08
--- /dev/null
+++ b/part_3/ex14/db/ex10.(18).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(18).cnf.hdb b/part_3/ex14/db/ex10.(18).cnf.hdb
new file mode 100755
index 0000000..57267e9
--- /dev/null
+++ b/part_3/ex14/db/ex10.(18).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(19).cnf.cdb b/part_3/ex14/db/ex10.(19).cnf.cdb
new file mode 100755
index 0000000..ae7bc50
--- /dev/null
+++ b/part_3/ex14/db/ex10.(19).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(19).cnf.hdb b/part_3/ex14/db/ex10.(19).cnf.hdb
new file mode 100755
index 0000000..88032e3
--- /dev/null
+++ b/part_3/ex14/db/ex10.(19).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(2).cnf.cdb b/part_3/ex14/db/ex10.(2).cnf.cdb
new file mode 100755
index 0000000..ec6fd7c
--- /dev/null
+++ b/part_3/ex14/db/ex10.(2).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(2).cnf.hdb b/part_3/ex14/db/ex10.(2).cnf.hdb
new file mode 100755
index 0000000..b5f7a93
--- /dev/null
+++ b/part_3/ex14/db/ex10.(2).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(20).cnf.cdb b/part_3/ex14/db/ex10.(20).cnf.cdb
new file mode 100755
index 0000000..4fe41d3
--- /dev/null
+++ b/part_3/ex14/db/ex10.(20).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(20).cnf.hdb b/part_3/ex14/db/ex10.(20).cnf.hdb
new file mode 100755
index 0000000..3cf5996
--- /dev/null
+++ b/part_3/ex14/db/ex10.(20).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(3).cnf.cdb b/part_3/ex14/db/ex10.(3).cnf.cdb
new file mode 100755
index 0000000..717a7a3
--- /dev/null
+++ b/part_3/ex14/db/ex10.(3).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(3).cnf.hdb b/part_3/ex14/db/ex10.(3).cnf.hdb
new file mode 100755
index 0000000..c3d2402
--- /dev/null
+++ b/part_3/ex14/db/ex10.(3).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(4).cnf.cdb b/part_3/ex14/db/ex10.(4).cnf.cdb
new file mode 100755
index 0000000..a548da9
--- /dev/null
+++ b/part_3/ex14/db/ex10.(4).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(4).cnf.hdb b/part_3/ex14/db/ex10.(4).cnf.hdb
new file mode 100755
index 0000000..6368acc
--- /dev/null
+++ b/part_3/ex14/db/ex10.(4).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(5).cnf.cdb b/part_3/ex14/db/ex10.(5).cnf.cdb
new file mode 100755
index 0000000..259cd1f
--- /dev/null
+++ b/part_3/ex14/db/ex10.(5).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(5).cnf.hdb b/part_3/ex14/db/ex10.(5).cnf.hdb
new file mode 100755
index 0000000..e63e3bb
--- /dev/null
+++ b/part_3/ex14/db/ex10.(5).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(6).cnf.cdb b/part_3/ex14/db/ex10.(6).cnf.cdb
new file mode 100755
index 0000000..64c167b
--- /dev/null
+++ b/part_3/ex14/db/ex10.(6).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(6).cnf.hdb b/part_3/ex14/db/ex10.(6).cnf.hdb
new file mode 100755
index 0000000..840adf7
--- /dev/null
+++ b/part_3/ex14/db/ex10.(6).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(7).cnf.cdb b/part_3/ex14/db/ex10.(7).cnf.cdb
new file mode 100755
index 0000000..4af6386
--- /dev/null
+++ b/part_3/ex14/db/ex10.(7).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(7).cnf.hdb b/part_3/ex14/db/ex10.(7).cnf.hdb
new file mode 100755
index 0000000..96769c8
--- /dev/null
+++ b/part_3/ex14/db/ex10.(7).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(8).cnf.cdb b/part_3/ex14/db/ex10.(8).cnf.cdb
new file mode 100755
index 0000000..26c8612
--- /dev/null
+++ b/part_3/ex14/db/ex10.(8).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(8).cnf.hdb b/part_3/ex14/db/ex10.(8).cnf.hdb
new file mode 100755
index 0000000..28c8367
--- /dev/null
+++ b/part_3/ex14/db/ex10.(8).cnf.hdb
diff --git a/part_3/ex14/db/ex10.(9).cnf.cdb b/part_3/ex14/db/ex10.(9).cnf.cdb
new file mode 100755
index 0000000..8e35326
--- /dev/null
+++ b/part_3/ex14/db/ex10.(9).cnf.cdb
diff --git a/part_3/ex14/db/ex10.(9).cnf.hdb b/part_3/ex14/db/ex10.(9).cnf.hdb
new file mode 100755
index 0000000..ed34964
--- /dev/null
+++ b/part_3/ex14/db/ex10.(9).cnf.hdb
diff --git a/part_3/ex14/db/ex10.asm.qmsg b/part_3/ex14/db/ex10.asm.qmsg
new file mode 100755
index 0000000..16926a5
--- /dev/null
+++ b/part_3/ex14/db/ex10.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480700324403 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480700324406 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 17:38:44 2016 " "Processing started: Fri Dec 02 17:38:44 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480700324406 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480700324406 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480700324407 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480700325333 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480700330156 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "902 " "Peak virtual memory: 902 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480700333598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 17:38:53 2016 " "Processing ended: Fri Dec 02 17:38:53 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480700333598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480700333598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480700333598 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480700333598 ""}
diff --git a/part_3/ex14/db/ex10.asm.rdb b/part_3/ex14/db/ex10.asm.rdb
new file mode 100755
index 0000000..570fab0
--- /dev/null
+++ b/part_3/ex14/db/ex10.asm.rdb
diff --git a/part_2/ex9_final/db/ex9.cbx.xml b/part_3/ex14/db/ex10.cbx.xml
index 9156ad4..6012e60 100755
--- a/part_2/ex9_final/db/ex9.cbx.xml
+++ b/part_3/ex14/db/ex10.cbx.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" ?>
 <LOG_ROOT>
-	<PROJECT NAME="ex9">
+	<PROJECT NAME="ex10">
 	</PROJECT>
 </LOG_ROOT>
diff --git a/part_3/ex14/db/ex10.cmp.ammdb b/part_3/ex14/db/ex10.cmp.ammdb
new file mode 100755
index 0000000..8d2d1cd
--- /dev/null
+++ b/part_3/ex14/db/ex10.cmp.ammdb
diff --git a/part_3/ex14/db/ex10.cmp.bpm b/part_3/ex14/db/ex10.cmp.bpm
new file mode 100755
index 0000000..efc7715
--- /dev/null
+++ b/part_3/ex14/db/ex10.cmp.bpm
diff --git a/part_3/ex14/db/ex10.cmp.cdb b/part_3/ex14/db/ex10.cmp.cdb
new file mode 100755
index 0000000..296046d
--- /dev/null
+++ b/part_3/ex14/db/ex10.cmp.cdb
diff --git a/part_3/ex14/db/ex10.cmp.hdb b/part_3/ex14/db/ex10.cmp.hdb
new file mode 100755
index 0000000..b76dab6
--- /dev/null
+++ b/part_3/ex14/db/ex10.cmp.hdb
diff --git a/part_3/ex14/db/ex10.cmp.idb b/part_3/ex14/db/ex10.cmp.idb
new file mode 100755
index 0000000..2d6112c
--- /dev/null
+++ b/part_3/ex14/db/ex10.cmp.idb
diff --git a/part_3/ex14/db/ex10.cmp.logdb b/part_3/ex14/db/ex10.cmp.logdb
new file mode 100755
index 0000000..6d2de2c
--- /dev/null
+++ b/part_3/ex14/db/ex10.cmp.logdb
@@ -0,0 +1,90 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,51;0;51;0;0;51;51;0;51;51;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;51;0;51;51;0;0;51;0;0;51;51;51;51;51;51;51;51;51;51;51;51;51;51;51;51;51;51,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,DAC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_LD,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PWM_OUT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_3/ex14/db/ex10.cmp.rdb b/part_3/ex14/db/ex10.cmp.rdb
new file mode 100755
index 0000000..4b5a979
--- /dev/null
+++ b/part_3/ex14/db/ex10.cmp.rdb
diff --git a/part_3/ex14/db/ex10.cmp_merge.kpt b/part_3/ex14/db/ex10.cmp_merge.kpt
new file mode 100755
index 0000000..f13b219
--- /dev/null
+++ b/part_3/ex14/db/ex10.cmp_merge.kpt
diff --git a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_3/ex14/db/ex10.cyclonev_io_sim_cache.ff_0c_fast.hsd
index 5b115d6..5b115d6 100755
--- a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
+++ b/part_3/ex14/db/ex10.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_3/ex14/db/ex10.cyclonev_io_sim_cache.ff_85c_fast.hsd
index 3a7a497..3a7a497 100755
--- a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
+++ b/part_3/ex14/db/ex10.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_3/ex14/db/ex10.cyclonev_io_sim_cache.tt_0c_slow.hsd
index aa473fa..aa473fa 100755
--- a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
+++ b/part_3/ex14/db/ex10.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_3/ex14/db/ex10.cyclonev_io_sim_cache.tt_85c_slow.hsd
index dce4f6b..dce4f6b 100755
--- a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
+++ b/part_3/ex14/db/ex10.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex9_final/db/ex9.db_info b/part_3/ex14/db/ex10.db_info
index 1ce7f97..7cc01ec 100755
--- a/part_2/ex9_final/db/ex9.db_info
+++ b/part_3/ex14/db/ex10.db_info
@@ -1,3 +1,3 @@
 Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 Version_Index = 402707200
-Creation_Time = Fri Nov 25 11:34:26 2016
+Creation_Time = Fri Dec 02 17:08:23 2016
diff --git a/part_3/ex14/db/ex10.eda.qmsg b/part_3/ex14/db/ex10.eda.qmsg
new file mode 100755
index 0000000..d11984f
--- /dev/null
+++ b/part_3/ex14/db/ex10.eda.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480700347471 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480700347474 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 17:39:07 2016 " "Processing started: Fri Dec 02 17:39:07 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480700347474 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480700347474 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480700347474 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1480700348536 ""}
+{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1480700348584 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ex10.vo /Desktop/ex14/simulation/modelsim/ simulation " "Generated file ex10.vo in folder \"/Desktop/ex14/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1480700348996 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "816 " "Peak virtual memory: 816 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480700349147 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 17:39:09 2016 " "Processing ended: Fri Dec 02 17:39:09 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480700349147 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480700349147 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480700349147 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1480700349147 ""}
diff --git a/part_3/ex14/db/ex10.fit.qmsg b/part_3/ex14/db/ex10.fit.qmsg
new file mode 100755
index 0000000..77c9fe9
--- /dev/null
+++ b/part_3/ex14/db/ex10.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480700281592 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480700281594 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex10 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex10\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480700281840 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480700281896 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480700281896 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480700282298 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480700282469 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480700282474 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480700292395 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 55 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 55 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480700292494 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480700292494 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480700292494 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480700292499 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480700292499 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480700292501 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480700292503 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480700292503 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480700292503 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex10.sdc " "Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480700293432 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480700293433 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480700293437 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480700293437 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480700293438 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480700293453 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480700293453 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480700293453 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS " "Node \"ADC_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCK " "Node \"ADC_SCK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDI " "Node \"ADC_SDI\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDI" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDO " "Node \"ADC_SDO\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480700293499 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480700293499 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480700293505 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480700298418 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480700298663 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480700299357 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480700300147 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480700301042 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480700301043 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480700302484 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/" { { 1 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480700307048 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480700307048 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480700311473 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480700311473 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480700311477 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.46 " "Total time spent on timing analysis during the Fitter is 0.46 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480700313258 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480700313296 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480700313789 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480700313790 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480700314279 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480700316952 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480700317198 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Desktop/ex14/output_files/ex10.fit.smsg " "Generated suppressed messages file /Desktop/ex14/output_files/ex10.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480700317323 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 35 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2728 " "Peak virtual memory: 2728 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480700319556 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 17:38:39 2016 " "Processing ended: Fri Dec 02 17:38:39 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480700319556 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Elapsed time: 00:00:39" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480700319556 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:02 " "Total CPU time (on all processors): 00:01:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480700319556 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480700319556 ""}
diff --git a/part_3/ex14/db/ex10.hier_info b/part_3/ex14/db/ex10.hier_info
new file mode 100755
index 0000000..e8d9353
--- /dev/null
+++ b/part_3/ex14/db/ex10.hier_info
@@ -0,0 +1,1954 @@
+|ex14
+CLOCK_50 => CLOCK_50.IN4
+SW[0] => SW[0].IN2
+SW[1] => SW[1].IN2
+SW[2] => SW[2].IN2
+SW[3] => SW[3].IN2
+SW[4] => SW[4].IN2
+SW[5] => SW[5].IN2
+SW[6] => SW[6].IN2
+SW[7] => SW[7].IN2
+SW[8] => SW[8].IN2
+SW[9] => SW[9].IN2
+DAC_CS <= spi2dac:dac.port4
+DAC_SDI <= spi2dac:dac.port3
+DAC_LD <= spi2dac:dac.port6
+DAC_SCK <= spi2dac:dac.port5
+PWM_OUT <= pwm:p.port3
+HEX0[0] <= hex_to_7seg:h0.port0
+HEX0[1] <= hex_to_7seg:h0.port0
+HEX0[2] <= hex_to_7seg:h0.port0
+HEX0[3] <= hex_to_7seg:h0.port0
+HEX0[4] <= hex_to_7seg:h0.port0
+HEX0[5] <= hex_to_7seg:h0.port0
+HEX0[6] <= hex_to_7seg:h0.port0
+HEX1[0] <= hex_to_7seg:h1.port0
+HEX1[1] <= hex_to_7seg:h1.port0
+HEX1[2] <= hex_to_7seg:h1.port0
+HEX1[3] <= hex_to_7seg:h1.port0
+HEX1[4] <= hex_to_7seg:h1.port0
+HEX1[5] <= hex_to_7seg:h1.port0
+HEX1[6] <= hex_to_7seg:h1.port0
+HEX2[0] <= hex_to_7seg:h2.port0
+HEX2[1] <= hex_to_7seg:h2.port0
+HEX2[2] <= hex_to_7seg:h2.port0
+HEX2[3] <= hex_to_7seg:h2.port0
+HEX2[4] <= hex_to_7seg:h2.port0
+HEX2[5] <= hex_to_7seg:h2.port0
+HEX2[6] <= hex_to_7seg:h2.port0
+HEX3[0] <= hex_to_7seg:h3.port0
+HEX3[1] <= hex_to_7seg:h3.port0
+HEX3[2] <= hex_to_7seg:h3.port0
+HEX3[3] <= hex_to_7seg:h3.port0
+HEX3[4] <= hex_to_7seg:h3.port0
+HEX3[5] <= hex_to_7seg:h3.port0
+HEX3[6] <= hex_to_7seg:h3.port0
+HEX4[0] <= hex_to_7seg:h4.port0
+HEX4[1] <= hex_to_7seg:h4.port0
+HEX4[2] <= hex_to_7seg:h4.port0
+HEX4[3] <= hex_to_7seg:h4.port0
+HEX4[4] <= hex_to_7seg:h4.port0
+HEX4[5] <= hex_to_7seg:h4.port0
+HEX4[6] <= hex_to_7seg:h4.port0
+
+
+|ex14|tick_5000:tick
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|add_offset:fin_address
+keys[0] => Add0.IN10
+keys[1] => Add0.IN9
+keys[2] => Add0.IN8
+keys[3] => Add0.IN7
+keys[4] => Add0.IN6
+keys[5] => Add0.IN5
+keys[6] => Add0.IN4
+keys[7] => Add0.IN3
+keys[8] => Add0.IN2
+keys[9] => Add0.IN1
+tick => address[0]~reg0.CLK
+tick => address[1]~reg0.CLK
+tick => address[2]~reg0.CLK
+tick => address[3]~reg0.CLK
+tick => address[4]~reg0.CLK
+tick => address[5]~reg0.CLK
+tick => address[6]~reg0.CLK
+tick => address[7]~reg0.CLK
+tick => address[8]~reg0.CLK
+tick => address[9]~reg0.CLK
+address[0] <= address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[1] <= address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[2] <= address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[3] <= address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[4] <= address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[5] <= address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[6] <= address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[7] <= address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[8] <= address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[9] <= address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|ROM:rom
+address[0] => address[0].IN1
+address[1] => address[1].IN1
+address[2] => address[2].IN1
+address[3] => address[3].IN1
+address[4] => address[4].IN1
+address[5] => address[5].IN1
+address[6] => address[6].IN1
+address[7] => address[7].IN1
+address[8] => address[8].IN1
+address[9] => address[9].IN1
+clock => clock.IN1
+q[0] <= altsyncram:altsyncram_component.q_a
+q[1] <= altsyncram:altsyncram_component.q_a
+q[2] <= altsyncram:altsyncram_component.q_a
+q[3] <= altsyncram:altsyncram_component.q_a
+q[4] <= altsyncram:altsyncram_component.q_a
+q[5] <= altsyncram:altsyncram_component.q_a
+q[6] <= altsyncram:altsyncram_component.q_a
+q[7] <= altsyncram:altsyncram_component.q_a
+q[8] <= altsyncram:altsyncram_component.q_a
+q[9] <= altsyncram:altsyncram_component.q_a
+
+
+|ex14|ROM:rom|altsyncram:altsyncram_component
+wren_a => ~NO_FANOUT~
+rden_a => ~NO_FANOUT~
+wren_b => ~NO_FANOUT~
+rden_b => ~NO_FANOUT~
+data_a[0] => ~NO_FANOUT~
+data_a[1] => ~NO_FANOUT~
+data_a[2] => ~NO_FANOUT~
+data_a[3] => ~NO_FANOUT~
+data_a[4] => ~NO_FANOUT~
+data_a[5] => ~NO_FANOUT~
+data_a[6] => ~NO_FANOUT~
+data_a[7] => ~NO_FANOUT~
+data_a[8] => ~NO_FANOUT~
+data_a[9] => ~NO_FANOUT~
+data_b[0] => ~NO_FANOUT~
+address_a[0] => altsyncram_6ng1:auto_generated.address_a[0]
+address_a[1] => altsyncram_6ng1:auto_generated.address_a[1]
+address_a[2] => altsyncram_6ng1:auto_generated.address_a[2]
+address_a[3] => altsyncram_6ng1:auto_generated.address_a[3]
+address_a[4] => altsyncram_6ng1:auto_generated.address_a[4]
+address_a[5] => altsyncram_6ng1:auto_generated.address_a[5]
+address_a[6] => altsyncram_6ng1:auto_generated.address_a[6]
+address_a[7] => altsyncram_6ng1:auto_generated.address_a[7]
+address_a[8] => altsyncram_6ng1:auto_generated.address_a[8]
+address_a[9] => altsyncram_6ng1:auto_generated.address_a[9]
+address_b[0] => ~NO_FANOUT~
+addressstall_a => ~NO_FANOUT~
+addressstall_b => ~NO_FANOUT~
+clock0 => altsyncram_6ng1:auto_generated.clock0
+clock1 => ~NO_FANOUT~
+clocken0 => ~NO_FANOUT~
+clocken1 => ~NO_FANOUT~
+clocken2 => ~NO_FANOUT~
+clocken3 => ~NO_FANOUT~
+aclr0 => ~NO_FANOUT~
+aclr1 => ~NO_FANOUT~
+byteena_a[0] => ~NO_FANOUT~
+byteena_b[0] => ~NO_FANOUT~
+q_a[0] <= altsyncram_6ng1:auto_generated.q_a[0]
+q_a[1] <= altsyncram_6ng1:auto_generated.q_a[1]
+q_a[2] <= altsyncram_6ng1:auto_generated.q_a[2]
+q_a[3] <= altsyncram_6ng1:auto_generated.q_a[3]
+q_a[4] <= altsyncram_6ng1:auto_generated.q_a[4]
+q_a[5] <= altsyncram_6ng1:auto_generated.q_a[5]
+q_a[6] <= altsyncram_6ng1:auto_generated.q_a[6]
+q_a[7] <= altsyncram_6ng1:auto_generated.q_a[7]
+q_a[8] <= altsyncram_6ng1:auto_generated.q_a[8]
+q_a[9] <= altsyncram_6ng1:auto_generated.q_a[9]
+q_b[0] <= <GND>
+eccstatus[0] <= <GND>
+eccstatus[1] <= <GND>
+eccstatus[2] <= <GND>
+
+
+|ex14|ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated
+address_a[0] => ram_block1a0.PORTAADDR
+address_a[0] => ram_block1a1.PORTAADDR
+address_a[0] => ram_block1a2.PORTAADDR
+address_a[0] => ram_block1a3.PORTAADDR
+address_a[0] => ram_block1a4.PORTAADDR
+address_a[0] => ram_block1a5.PORTAADDR
+address_a[0] => ram_block1a6.PORTAADDR
+address_a[0] => ram_block1a7.PORTAADDR
+address_a[0] => ram_block1a8.PORTAADDR
+address_a[0] => ram_block1a9.PORTAADDR
+address_a[1] => ram_block1a0.PORTAADDR1
+address_a[1] => ram_block1a1.PORTAADDR1
+address_a[1] => ram_block1a2.PORTAADDR1
+address_a[1] => ram_block1a3.PORTAADDR1
+address_a[1] => ram_block1a4.PORTAADDR1
+address_a[1] => ram_block1a5.PORTAADDR1
+address_a[1] => ram_block1a6.PORTAADDR1
+address_a[1] => ram_block1a7.PORTAADDR1
+address_a[1] => ram_block1a8.PORTAADDR1
+address_a[1] => ram_block1a9.PORTAADDR1
+address_a[2] => ram_block1a0.PORTAADDR2
+address_a[2] => ram_block1a1.PORTAADDR2
+address_a[2] => ram_block1a2.PORTAADDR2
+address_a[2] => ram_block1a3.PORTAADDR2
+address_a[2] => ram_block1a4.PORTAADDR2
+address_a[2] => ram_block1a5.PORTAADDR2
+address_a[2] => ram_block1a6.PORTAADDR2
+address_a[2] => ram_block1a7.PORTAADDR2
+address_a[2] => ram_block1a8.PORTAADDR2
+address_a[2] => ram_block1a9.PORTAADDR2
+address_a[3] => ram_block1a0.PORTAADDR3
+address_a[3] => ram_block1a1.PORTAADDR3
+address_a[3] => ram_block1a2.PORTAADDR3
+address_a[3] => ram_block1a3.PORTAADDR3
+address_a[3] => ram_block1a4.PORTAADDR3
+address_a[3] => ram_block1a5.PORTAADDR3
+address_a[3] => ram_block1a6.PORTAADDR3
+address_a[3] => ram_block1a7.PORTAADDR3
+address_a[3] => ram_block1a8.PORTAADDR3
+address_a[3] => ram_block1a9.PORTAADDR3
+address_a[4] => ram_block1a0.PORTAADDR4
+address_a[4] => ram_block1a1.PORTAADDR4
+address_a[4] => ram_block1a2.PORTAADDR4
+address_a[4] => ram_block1a3.PORTAADDR4
+address_a[4] => ram_block1a4.PORTAADDR4
+address_a[4] => ram_block1a5.PORTAADDR4
+address_a[4] => ram_block1a6.PORTAADDR4
+address_a[4] => ram_block1a7.PORTAADDR4
+address_a[4] => ram_block1a8.PORTAADDR4
+address_a[4] => ram_block1a9.PORTAADDR4
+address_a[5] => ram_block1a0.PORTAADDR5
+address_a[5] => ram_block1a1.PORTAADDR5
+address_a[5] => ram_block1a2.PORTAADDR5
+address_a[5] => ram_block1a3.PORTAADDR5
+address_a[5] => ram_block1a4.PORTAADDR5
+address_a[5] => ram_block1a5.PORTAADDR5
+address_a[5] => ram_block1a6.PORTAADDR5
+address_a[5] => ram_block1a7.PORTAADDR5
+address_a[5] => ram_block1a8.PORTAADDR5
+address_a[5] => ram_block1a9.PORTAADDR5
+address_a[6] => ram_block1a0.PORTAADDR6
+address_a[6] => ram_block1a1.PORTAADDR6
+address_a[6] => ram_block1a2.PORTAADDR6
+address_a[6] => ram_block1a3.PORTAADDR6
+address_a[6] => ram_block1a4.PORTAADDR6
+address_a[6] => ram_block1a5.PORTAADDR6
+address_a[6] => ram_block1a6.PORTAADDR6
+address_a[6] => ram_block1a7.PORTAADDR6
+address_a[6] => ram_block1a8.PORTAADDR6
+address_a[6] => ram_block1a9.PORTAADDR6
+address_a[7] => ram_block1a0.PORTAADDR7
+address_a[7] => ram_block1a1.PORTAADDR7
+address_a[7] => ram_block1a2.PORTAADDR7
+address_a[7] => ram_block1a3.PORTAADDR7
+address_a[7] => ram_block1a4.PORTAADDR7
+address_a[7] => ram_block1a5.PORTAADDR7
+address_a[7] => ram_block1a6.PORTAADDR7
+address_a[7] => ram_block1a7.PORTAADDR7
+address_a[7] => ram_block1a8.PORTAADDR7
+address_a[7] => ram_block1a9.PORTAADDR7
+address_a[8] => ram_block1a0.PORTAADDR8
+address_a[8] => ram_block1a1.PORTAADDR8
+address_a[8] => ram_block1a2.PORTAADDR8
+address_a[8] => ram_block1a3.PORTAADDR8
+address_a[8] => ram_block1a4.PORTAADDR8
+address_a[8] => ram_block1a5.PORTAADDR8
+address_a[8] => ram_block1a6.PORTAADDR8
+address_a[8] => ram_block1a7.PORTAADDR8
+address_a[8] => ram_block1a8.PORTAADDR8
+address_a[8] => ram_block1a9.PORTAADDR8
+address_a[9] => ram_block1a0.PORTAADDR9
+address_a[9] => ram_block1a1.PORTAADDR9
+address_a[9] => ram_block1a2.PORTAADDR9
+address_a[9] => ram_block1a3.PORTAADDR9
+address_a[9] => ram_block1a4.PORTAADDR9
+address_a[9] => ram_block1a5.PORTAADDR9
+address_a[9] => ram_block1a6.PORTAADDR9
+address_a[9] => ram_block1a7.PORTAADDR9
+address_a[9] => ram_block1a8.PORTAADDR9
+address_a[9] => ram_block1a9.PORTAADDR9
+clock0 => ram_block1a0.CLK0
+clock0 => ram_block1a1.CLK0
+clock0 => ram_block1a2.CLK0
+clock0 => ram_block1a3.CLK0
+clock0 => ram_block1a4.CLK0
+clock0 => ram_block1a5.CLK0
+clock0 => ram_block1a6.CLK0
+clock0 => ram_block1a7.CLK0
+clock0 => ram_block1a8.CLK0
+clock0 => ram_block1a9.CLK0
+q_a[0] <= ram_block1a0.PORTADATAOUT
+q_a[1] <= ram_block1a1.PORTADATAOUT
+q_a[2] <= ram_block1a2.PORTADATAOUT
+q_a[3] <= ram_block1a3.PORTADATAOUT
+q_a[4] <= ram_block1a4.PORTADATAOUT
+q_a[5] <= ram_block1a5.PORTADATAOUT
+q_a[6] <= ram_block1a6.PORTADATAOUT
+q_a[7] <= ram_block1a7.PORTADATAOUT
+q_a[8] <= ram_block1a8.PORTADATAOUT
+q_a[9] <= ram_block1a9.PORTADATAOUT
+
+
+|ex14|spi2dac:dac
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~4.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => sr_state.OUTPUTSELECT
+load => sr_state.OUTPUTSELECT
+load => sr_state.OUTPUTSELECT
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= WideNor0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= Equal2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|pwm:p
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|const_mult:mult
+dataa[0] => dataa[0].IN1
+dataa[1] => dataa[1].IN1
+dataa[2] => dataa[2].IN1
+dataa[3] => dataa[3].IN1
+dataa[4] => dataa[4].IN1
+dataa[5] => dataa[5].IN1
+dataa[6] => dataa[6].IN1
+dataa[7] => dataa[7].IN1
+dataa[8] => dataa[8].IN1
+dataa[9] => dataa[9].IN1
+result[0] <= lpm_mult:lpm_mult_component.result
+result[1] <= lpm_mult:lpm_mult_component.result
+result[2] <= lpm_mult:lpm_mult_component.result
+result[3] <= lpm_mult:lpm_mult_component.result
+result[4] <= lpm_mult:lpm_mult_component.result
+result[5] <= lpm_mult:lpm_mult_component.result
+result[6] <= lpm_mult:lpm_mult_component.result
+result[7] <= lpm_mult:lpm_mult_component.result
+result[8] <= lpm_mult:lpm_mult_component.result
+result[9] <= lpm_mult:lpm_mult_component.result
+result[10] <= lpm_mult:lpm_mult_component.result
+result[11] <= lpm_mult:lpm_mult_component.result
+result[12] <= lpm_mult:lpm_mult_component.result
+result[13] <= lpm_mult:lpm_mult_component.result
+result[14] <= lpm_mult:lpm_mult_component.result
+result[15] <= lpm_mult:lpm_mult_component.result
+result[16] <= lpm_mult:lpm_mult_component.result
+result[17] <= lpm_mult:lpm_mult_component.result
+result[18] <= lpm_mult:lpm_mult_component.result
+result[19] <= lpm_mult:lpm_mult_component.result
+result[20] <= lpm_mult:lpm_mult_component.result
+result[21] <= lpm_mult:lpm_mult_component.result
+result[22] <= lpm_mult:lpm_mult_component.result
+result[23] <= lpm_mult:lpm_mult_component.result
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component
+dataa[0] => multcore:mult_core.dataa[0]
+dataa[1] => multcore:mult_core.dataa[1]
+dataa[2] => multcore:mult_core.dataa[2]
+dataa[3] => multcore:mult_core.dataa[3]
+dataa[4] => multcore:mult_core.dataa[4]
+dataa[5] => multcore:mult_core.dataa[5]
+dataa[6] => multcore:mult_core.dataa[6]
+dataa[7] => multcore:mult_core.dataa[7]
+dataa[8] => multcore:mult_core.dataa[8]
+dataa[9] => multcore:mult_core.dataa[9]
+datab[0] => multcore:mult_core.datab[0]
+datab[1] => multcore:mult_core.datab[1]
+datab[2] => multcore:mult_core.datab[2]
+datab[3] => multcore:mult_core.datab[3]
+datab[4] => multcore:mult_core.datab[4]
+datab[5] => multcore:mult_core.datab[5]
+datab[6] => multcore:mult_core.datab[6]
+datab[7] => multcore:mult_core.datab[7]
+datab[8] => multcore:mult_core.datab[8]
+datab[9] => multcore:mult_core.datab[9]
+datab[10] => multcore:mult_core.datab[10]
+datab[11] => multcore:mult_core.datab[11]
+datab[12] => multcore:mult_core.datab[12]
+datab[13] => multcore:mult_core.datab[13]
+sum[0] => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+sclr => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= altshift:external_latency_ffs.result[0]
+result[1] <= altshift:external_latency_ffs.result[1]
+result[2] <= altshift:external_latency_ffs.result[2]
+result[3] <= altshift:external_latency_ffs.result[3]
+result[4] <= altshift:external_latency_ffs.result[4]
+result[5] <= altshift:external_latency_ffs.result[5]
+result[6] <= altshift:external_latency_ffs.result[6]
+result[7] <= altshift:external_latency_ffs.result[7]
+result[8] <= altshift:external_latency_ffs.result[8]
+result[9] <= altshift:external_latency_ffs.result[9]
+result[10] <= altshift:external_latency_ffs.result[10]
+result[11] <= altshift:external_latency_ffs.result[11]
+result[12] <= altshift:external_latency_ffs.result[12]
+result[13] <= altshift:external_latency_ffs.result[13]
+result[14] <= altshift:external_latency_ffs.result[14]
+result[15] <= altshift:external_latency_ffs.result[15]
+result[16] <= altshift:external_latency_ffs.result[16]
+result[17] <= altshift:external_latency_ffs.result[17]
+result[18] <= altshift:external_latency_ffs.result[18]
+result[19] <= altshift:external_latency_ffs.result[19]
+result[20] <= altshift:external_latency_ffs.result[20]
+result[21] <= altshift:external_latency_ffs.result[21]
+result[22] <= altshift:external_latency_ffs.result[22]
+result[23] <= altshift:external_latency_ffs.result[23]
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[9] => ina_reg_clkd[1].IN0
+datab[0] => op_1.IN34
+datab[0] => op_2.IN35
+datab[0] => op_4.IN35
+datab[0] => op_5.IN35
+datab[0] => op_6.IN35
+datab[0] => op_7.IN35
+datab[0] => op_8.IN35
+datab[0] => op_9.IN35
+datab[0] => op_10.IN35
+datab[0] => op_11.IN35
+datab[0] => romout[0][0].IN1
+datab[0] => romout[1][0].IN1
+datab[0] => op_1.IN33
+datab[0] => op_3.IN33
+datab[0] => romout[0][1].IN1
+datab[0] => romout[1][1].IN1
+datab[0] => op_2.IN30
+datab[0] => op_3.IN30
+datab[0] => romout[0][2].IN1
+datab[0] => romout[1][2].IN1
+datab[0] => op_5.IN28
+datab[0] => romout[0][3].IN1
+datab[0] => romout[1][3].IN1
+datab[0] => romout[2][0].IN1
+datab[0] => romout[2][1].IN1
+datab[0] => romout[2][2].IN1
+datab[0] => romout[2][3].IN1
+datab[1] => op_1.IN32
+datab[1] => op_2.IN33
+datab[1] => op_4.IN33
+datab[1] => op_5.IN33
+datab[1] => op_6.IN33
+datab[1] => op_7.IN33
+datab[1] => op_8.IN33
+datab[1] => op_9.IN33
+datab[1] => op_10.IN33
+datab[1] => op_11.IN33
+datab[1] => romout[0][1].IN1
+datab[1] => romout[1][1].IN1
+datab[1] => op_1.IN31
+datab[1] => op_3.IN31
+datab[1] => romout[0][2].IN1
+datab[1] => romout[1][2].IN1
+datab[1] => op_2.IN28
+datab[1] => op_3.IN28
+datab[1] => romout[0][3].IN1
+datab[1] => romout[1][3].IN1
+datab[1] => op_5.IN26
+datab[1] => romout[0][4].IN1
+datab[1] => romout[1][4].IN1
+datab[1] => romout[2][1].IN1
+datab[1] => romout[2][2].IN1
+datab[1] => romout[2][3].IN1
+datab[1] => romout[2][4].IN1
+datab[2] => op_1.IN30
+datab[2] => op_2.IN31
+datab[2] => op_4.IN31
+datab[2] => op_5.IN31
+datab[2] => op_6.IN31
+datab[2] => op_7.IN31
+datab[2] => op_8.IN31
+datab[2] => op_9.IN31
+datab[2] => op_10.IN31
+datab[2] => op_11.IN31
+datab[2] => romout[0][2].IN1
+datab[2] => romout[1][2].IN1
+datab[2] => op_1.IN29
+datab[2] => op_3.IN29
+datab[2] => romout[0][3].IN1
+datab[2] => romout[1][3].IN1
+datab[2] => op_2.IN26
+datab[2] => op_3.IN26
+datab[2] => romout[0][4].IN1
+datab[2] => romout[1][4].IN1
+datab[2] => op_5.IN24
+datab[2] => romout[0][5].IN1
+datab[2] => romout[1][5].IN1
+datab[2] => romout[2][2].IN1
+datab[2] => romout[2][3].IN1
+datab[2] => romout[2][4].IN1
+datab[2] => romout[2][5].IN1
+datab[3] => op_1.IN28
+datab[3] => op_2.IN29
+datab[3] => op_4.IN29
+datab[3] => op_5.IN29
+datab[3] => op_6.IN29
+datab[3] => op_7.IN29
+datab[3] => op_8.IN29
+datab[3] => op_9.IN29
+datab[3] => op_10.IN29
+datab[3] => op_11.IN29
+datab[3] => romout[0][3].IN1
+datab[3] => romout[1][3].IN1
+datab[3] => op_1.IN27
+datab[3] => op_3.IN27
+datab[3] => romout[0][4].IN1
+datab[3] => romout[1][4].IN1
+datab[3] => op_2.IN24
+datab[3] => op_3.IN24
+datab[3] => romout[0][5].IN1
+datab[3] => romout[1][5].IN1
+datab[3] => op_5.IN22
+datab[3] => romout[0][6].IN1
+datab[3] => romout[1][6].IN1
+datab[3] => romout[2][3].IN1
+datab[3] => romout[2][4].IN1
+datab[3] => romout[2][5].IN1
+datab[3] => romout[2][6].IN1
+datab[4] => op_1.IN26
+datab[4] => op_2.IN27
+datab[4] => op_4.IN27
+datab[4] => op_5.IN27
+datab[4] => op_6.IN27
+datab[4] => op_7.IN27
+datab[4] => op_8.IN27
+datab[4] => op_9.IN27
+datab[4] => op_10.IN27
+datab[4] => op_11.IN27
+datab[4] => romout[0][4].IN1
+datab[4] => romout[1][4].IN1
+datab[4] => op_1.IN25
+datab[4] => op_3.IN25
+datab[4] => romout[0][5].IN1
+datab[4] => romout[1][5].IN1
+datab[4] => op_2.IN22
+datab[4] => op_3.IN22
+datab[4] => romout[0][6].IN1
+datab[4] => romout[1][6].IN1
+datab[4] => op_5.IN20
+datab[4] => romout[0][7].IN1
+datab[4] => romout[1][7].IN1
+datab[4] => romout[2][4].IN1
+datab[4] => romout[2][5].IN1
+datab[4] => romout[2][6].IN1
+datab[4] => romout[2][7].IN1
+datab[5] => op_1.IN24
+datab[5] => op_2.IN25
+datab[5] => op_4.IN25
+datab[5] => op_5.IN25
+datab[5] => op_6.IN25
+datab[5] => op_7.IN25
+datab[5] => op_8.IN25
+datab[5] => op_9.IN25
+datab[5] => op_10.IN25
+datab[5] => op_11.IN25
+datab[5] => romout[0][5].IN1
+datab[5] => romout[1][5].IN1
+datab[5] => op_1.IN23
+datab[5] => op_3.IN23
+datab[5] => romout[0][6].IN1
+datab[5] => romout[1][6].IN1
+datab[5] => op_2.IN20
+datab[5] => op_3.IN20
+datab[5] => romout[0][7].IN1
+datab[5] => romout[1][7].IN1
+datab[5] => op_5.IN18
+datab[5] => romout[0][8].IN1
+datab[5] => romout[1][8].IN1
+datab[5] => romout[2][5].IN1
+datab[5] => romout[2][6].IN1
+datab[5] => romout[2][7].IN1
+datab[5] => romout[2][8].IN1
+datab[6] => op_1.IN22
+datab[6] => op_2.IN23
+datab[6] => op_4.IN23
+datab[6] => op_5.IN23
+datab[6] => op_6.IN23
+datab[6] => op_7.IN23
+datab[6] => op_8.IN23
+datab[6] => op_9.IN23
+datab[6] => op_10.IN23
+datab[6] => op_11.IN23
+datab[6] => romout[0][6].IN1
+datab[6] => romout[1][6].IN1
+datab[6] => op_1.IN21
+datab[6] => op_3.IN21
+datab[6] => romout[0][7].IN1
+datab[6] => romout[1][7].IN1
+datab[6] => op_2.IN18
+datab[6] => op_3.IN18
+datab[6] => romout[0][8].IN1
+datab[6] => romout[1][8].IN1
+datab[6] => op_5.IN16
+datab[6] => romout[0][9].IN1
+datab[6] => romout[1][9].IN1
+datab[6] => romout[2][6].IN1
+datab[6] => romout[2][7].IN1
+datab[6] => romout[2][8].IN1
+datab[6] => romout[2][9].IN1
+datab[7] => op_1.IN20
+datab[7] => op_2.IN21
+datab[7] => op_4.IN21
+datab[7] => op_5.IN21
+datab[7] => op_6.IN21
+datab[7] => op_7.IN21
+datab[7] => op_8.IN21
+datab[7] => op_9.IN21
+datab[7] => op_10.IN21
+datab[7] => op_11.IN21
+datab[7] => romout[0][7].IN1
+datab[7] => romout[1][7].IN1
+datab[7] => op_1.IN19
+datab[7] => op_3.IN19
+datab[7] => romout[0][8].IN1
+datab[7] => romout[1][8].IN1
+datab[7] => op_2.IN16
+datab[7] => op_3.IN16
+datab[7] => romout[0][9].IN1
+datab[7] => romout[1][9].IN1
+datab[7] => op_5.IN14
+datab[7] => romout[0][10].IN1
+datab[7] => romout[1][10].IN1
+datab[7] => romout[2][7].IN1
+datab[7] => romout[2][8].IN1
+datab[7] => romout[2][9].IN1
+datab[7] => romout[2][10].IN1
+datab[8] => op_1.IN18
+datab[8] => op_2.IN19
+datab[8] => op_4.IN19
+datab[8] => op_5.IN19
+datab[8] => op_6.IN19
+datab[8] => op_7.IN19
+datab[8] => op_8.IN19
+datab[8] => op_9.IN19
+datab[8] => op_10.IN19
+datab[8] => op_11.IN19
+datab[8] => romout[0][8].IN1
+datab[8] => romout[1][8].IN1
+datab[8] => op_1.IN17
+datab[8] => op_3.IN17
+datab[8] => romout[0][9].IN1
+datab[8] => romout[1][9].IN1
+datab[8] => op_2.IN14
+datab[8] => op_3.IN14
+datab[8] => romout[0][10].IN1
+datab[8] => romout[1][10].IN1
+datab[8] => op_5.IN12
+datab[8] => romout[0][11].IN1
+datab[8] => romout[1][11].IN1
+datab[8] => romout[2][8].IN1
+datab[8] => romout[2][9].IN1
+datab[8] => romout[2][10].IN1
+datab[8] => romout[2][11].IN1
+datab[9] => op_1.IN16
+datab[9] => op_2.IN17
+datab[9] => op_4.IN17
+datab[9] => op_5.IN17
+datab[9] => op_6.IN17
+datab[9] => op_7.IN17
+datab[9] => op_8.IN17
+datab[9] => op_9.IN17
+datab[9] => op_10.IN17
+datab[9] => op_11.IN17
+datab[9] => romout[0][9].IN1
+datab[9] => romout[1][9].IN1
+datab[9] => op_1.IN15
+datab[9] => op_3.IN15
+datab[9] => romout[0][10].IN1
+datab[9] => romout[1][10].IN1
+datab[9] => op_2.IN12
+datab[9] => op_3.IN12
+datab[9] => romout[0][11].IN1
+datab[9] => romout[1][11].IN1
+datab[9] => op_5.IN10
+datab[9] => romout[0][12].IN1
+datab[9] => romout[1][12].IN1
+datab[9] => romout[2][9].IN1
+datab[9] => romout[2][10].IN1
+datab[9] => romout[2][11].IN1
+datab[9] => romout[2][12].IN1
+datab[10] => op_1.IN14
+datab[10] => op_2.IN15
+datab[10] => op_4.IN15
+datab[10] => op_5.IN15
+datab[10] => op_6.IN15
+datab[10] => op_7.IN15
+datab[10] => op_8.IN15
+datab[10] => op_9.IN15
+datab[10] => op_10.IN15
+datab[10] => op_11.IN15
+datab[10] => romout[0][10].IN1
+datab[10] => romout[1][10].IN1
+datab[10] => op_1.IN13
+datab[10] => op_3.IN13
+datab[10] => romout[0][11].IN1
+datab[10] => romout[1][11].IN1
+datab[10] => op_2.IN10
+datab[10] => op_3.IN10
+datab[10] => romout[0][12].IN1
+datab[10] => romout[1][12].IN1
+datab[10] => op_5.IN8
+datab[10] => romout[0][13].IN1
+datab[10] => romout[1][13].IN1
+datab[10] => romout[2][10].IN1
+datab[10] => romout[2][11].IN1
+datab[10] => romout[2][12].IN1
+datab[10] => romout[2][13].IN1
+datab[11] => op_1.IN12
+datab[11] => op_2.IN13
+datab[11] => op_4.IN13
+datab[11] => op_5.IN13
+datab[11] => op_6.IN13
+datab[11] => op_7.IN13
+datab[11] => op_8.IN13
+datab[11] => op_9.IN13
+datab[11] => op_10.IN13
+datab[11] => op_11.IN13
+datab[11] => romout[0][11].IN1
+datab[11] => romout[1][11].IN1
+datab[11] => op_1.IN11
+datab[11] => op_3.IN11
+datab[11] => romout[0][12].IN1
+datab[11] => romout[1][12].IN1
+datab[11] => op_2.IN8
+datab[11] => op_3.IN8
+datab[11] => romout[0][13].IN1
+datab[11] => romout[1][13].IN1
+datab[11] => op_5.IN6
+datab[11] => romout[0][14].IN1
+datab[11] => romout[1][14].IN1
+datab[11] => romout[2][11].IN1
+datab[11] => romout[2][12].IN1
+datab[11] => romout[2][13].IN1
+datab[11] => romout[2][14].IN1
+datab[12] => op_1.IN10
+datab[12] => op_2.IN11
+datab[12] => op_4.IN11
+datab[12] => op_5.IN11
+datab[12] => op_6.IN11
+datab[12] => op_7.IN11
+datab[12] => op_8.IN11
+datab[12] => op_9.IN11
+datab[12] => op_10.IN11
+datab[12] => op_11.IN11
+datab[12] => romout[0][12].IN1
+datab[12] => romout[1][12].IN1
+datab[12] => op_1.IN9
+datab[12] => op_3.IN9
+datab[12] => romout[0][13].IN1
+datab[12] => romout[1][13].IN1
+datab[12] => op_2.IN6
+datab[12] => op_3.IN6
+datab[12] => romout[0][14].IN1
+datab[12] => romout[1][14].IN1
+datab[12] => op_5.IN4
+datab[12] => romout[0][15].IN1
+datab[12] => romout[1][15].IN1
+datab[12] => romout[2][12].IN1
+datab[12] => romout[2][13].IN1
+datab[12] => romout[2][14].IN1
+datab[12] => romout[2][15].IN1
+datab[13] => op_1.IN8
+datab[13] => op_2.IN9
+datab[13] => op_4.IN9
+datab[13] => op_5.IN9
+datab[13] => op_6.IN9
+datab[13] => op_7.IN9
+datab[13] => op_8.IN9
+datab[13] => op_9.IN9
+datab[13] => op_10.IN9
+datab[13] => op_11.IN9
+datab[13] => romout[0][13].IN1
+datab[13] => romout[1][13].IN1
+datab[13] => op_1.IN7
+datab[13] => op_3.IN7
+datab[13] => romout[0][14].IN1
+datab[13] => romout[1][14].IN1
+datab[13] => op_2.IN4
+datab[13] => op_3.IN4
+datab[13] => romout[0][15].IN1
+datab[13] => romout[1][15].IN1
+datab[13] => op_5.IN2
+datab[13] => romout[0][16].IN1
+datab[13] => romout[1][16].IN1
+datab[13] => romout[2][13].IN1
+datab[13] => romout[2][14].IN1
+datab[13] => romout[2][15].IN1
+datab[13] => romout[2][16].IN1
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mpar_add:padder.result[0]
+result[1] <= mpar_add:padder.result[1]
+result[2] <= mpar_add:padder.result[2]
+result[3] <= mpar_add:padder.result[3]
+result[4] <= mpar_add:padder.result[4]
+result[5] <= mpar_add:padder.result[5]
+result[6] <= mpar_add:padder.result[6]
+result[7] <= mpar_add:padder.result[7]
+result[8] <= mpar_add:padder.result[8]
+result[9] <= mpar_add:padder.result[9]
+result[10] <= mpar_add:padder.result[10]
+result[11] <= mpar_add:padder.result[11]
+result[12] <= mpar_add:padder.result[12]
+result[13] <= mpar_add:padder.result[13]
+result[14] <= mpar_add:padder.result[14]
+result[15] <= mpar_add:padder.result[15]
+result[16] <= mpar_add:padder.result[16]
+result[17] <= mpar_add:padder.result[17]
+result[18] <= mpar_add:padder.result[18]
+result[19] <= mpar_add:padder.result[19]
+result[20] <= mpar_add:padder.result[20]
+result[21] <= mpar_add:padder.result[21]
+result[22] <= mpar_add:padder.result[22]
+result[23] <= mpar_add:padder.result[23]
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder
+data[0][0] => mpar_add:sub_par_add.data[0][0]
+data[0][1] => mpar_add:sub_par_add.data[0][1]
+data[0][2] => mpar_add:sub_par_add.data[0][2]
+data[0][3] => mpar_add:sub_par_add.data[0][3]
+data[0][4] => lpm_add_sub:adder[0].dataa[0]
+data[0][5] => lpm_add_sub:adder[0].dataa[1]
+data[0][6] => lpm_add_sub:adder[0].dataa[2]
+data[0][7] => lpm_add_sub:adder[0].dataa[3]
+data[0][8] => lpm_add_sub:adder[0].dataa[4]
+data[0][9] => lpm_add_sub:adder[0].dataa[5]
+data[0][10] => lpm_add_sub:adder[0].dataa[6]
+data[0][11] => lpm_add_sub:adder[0].dataa[7]
+data[0][12] => lpm_add_sub:adder[0].dataa[8]
+data[0][13] => lpm_add_sub:adder[0].dataa[9]
+data[0][14] => lpm_add_sub:adder[0].dataa[10]
+data[0][15] => lpm_add_sub:adder[0].dataa[11]
+data[0][16] => lpm_add_sub:adder[0].dataa[12]
+data[0][17] => lpm_add_sub:adder[0].dataa[13]
+data[1][0] => lpm_add_sub:adder[0].datab[0]
+data[1][1] => lpm_add_sub:adder[0].datab[1]
+data[1][2] => lpm_add_sub:adder[0].datab[2]
+data[1][3] => lpm_add_sub:adder[0].datab[3]
+data[1][4] => lpm_add_sub:adder[0].datab[4]
+data[1][5] => lpm_add_sub:adder[0].datab[5]
+data[1][6] => lpm_add_sub:adder[0].datab[6]
+data[1][7] => lpm_add_sub:adder[0].datab[7]
+data[1][8] => lpm_add_sub:adder[0].datab[8]
+data[1][9] => lpm_add_sub:adder[0].datab[9]
+data[1][10] => lpm_add_sub:adder[0].datab[10]
+data[1][11] => lpm_add_sub:adder[0].datab[11]
+data[1][12] => lpm_add_sub:adder[0].datab[12]
+data[1][13] => lpm_add_sub:adder[0].datab[13]
+data[1][14] => lpm_add_sub:adder[0].datab[14]
+data[1][15] => lpm_add_sub:adder[0].datab[15]
+data[1][16] => lpm_add_sub:adder[0].datab[16]
+data[1][17] => lpm_add_sub:adder[0].datab[17]
+data[2][0] => mpar_add:sub_par_add.data[1][0]
+data[2][1] => mpar_add:sub_par_add.data[1][1]
+data[2][2] => mpar_add:sub_par_add.data[1][2]
+data[2][3] => mpar_add:sub_par_add.data[1][3]
+data[2][4] => mpar_add:sub_par_add.data[1][4]
+data[2][5] => mpar_add:sub_par_add.data[1][5]
+data[2][6] => mpar_add:sub_par_add.data[1][6]
+data[2][7] => mpar_add:sub_par_add.data[1][7]
+data[2][8] => mpar_add:sub_par_add.data[1][8]
+data[2][9] => mpar_add:sub_par_add.data[1][9]
+data[2][10] => mpar_add:sub_par_add.data[1][10]
+data[2][11] => mpar_add:sub_par_add.data[1][11]
+data[2][12] => mpar_add:sub_par_add.data[1][12]
+data[2][13] => mpar_add:sub_par_add.data[1][13]
+data[2][14] => mpar_add:sub_par_add.data[1][14]
+data[2][15] => mpar_add:sub_par_add.data[1][15]
+data[2][16] => mpar_add:sub_par_add.data[1][16]
+data[2][17] => mpar_add:sub_par_add.data[1][17]
+cin => ~NO_FANOUT~
+clk => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mpar_add:sub_par_add.result[0]
+result[1] <= mpar_add:sub_par_add.result[1]
+result[2] <= mpar_add:sub_par_add.result[2]
+result[3] <= mpar_add:sub_par_add.result[3]
+result[4] <= mpar_add:sub_par_add.result[4]
+result[5] <= mpar_add:sub_par_add.result[5]
+result[6] <= mpar_add:sub_par_add.result[6]
+result[7] <= mpar_add:sub_par_add.result[7]
+result[8] <= mpar_add:sub_par_add.result[8]
+result[9] <= mpar_add:sub_par_add.result[9]
+result[10] <= mpar_add:sub_par_add.result[10]
+result[11] <= mpar_add:sub_par_add.result[11]
+result[12] <= mpar_add:sub_par_add.result[12]
+result[13] <= mpar_add:sub_par_add.result[13]
+result[14] <= mpar_add:sub_par_add.result[14]
+result[15] <= mpar_add:sub_par_add.result[15]
+result[16] <= mpar_add:sub_par_add.result[16]
+result[17] <= mpar_add:sub_par_add.result[17]
+result[18] <= mpar_add:sub_par_add.result[18]
+result[19] <= mpar_add:sub_par_add.result[19]
+result[20] <= mpar_add:sub_par_add.result[20]
+result[21] <= mpar_add:sub_par_add.result[21]
+result[22] <= mpar_add:sub_par_add.result[22]
+result[23] <= mpar_add:sub_par_add.result[23]
+result[24] <= mpar_add:sub_par_add.result[24]
+result[25] <= mpar_add:sub_par_add.result[25]
+result[26] <= mpar_add:sub_par_add.result[26]
+result[27] <= mpar_add:sub_par_add.result[27]
+result[28] <= mpar_add:sub_par_add.result[28]
+result[29] <= mpar_add:sub_par_add.result[29]
+clk_out <= <GND>
+aclr_out <= <GND>
+clken_out <= <GND>
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]
+dataa[0] => add_sub_d9h:auto_generated.dataa[0]
+dataa[1] => add_sub_d9h:auto_generated.dataa[1]
+dataa[2] => add_sub_d9h:auto_generated.dataa[2]
+dataa[3] => add_sub_d9h:auto_generated.dataa[3]
+dataa[4] => add_sub_d9h:auto_generated.dataa[4]
+dataa[5] => add_sub_d9h:auto_generated.dataa[5]
+dataa[6] => add_sub_d9h:auto_generated.dataa[6]
+dataa[7] => add_sub_d9h:auto_generated.dataa[7]
+dataa[8] => add_sub_d9h:auto_generated.dataa[8]
+dataa[9] => add_sub_d9h:auto_generated.dataa[9]
+dataa[10] => add_sub_d9h:auto_generated.dataa[10]
+dataa[11] => add_sub_d9h:auto_generated.dataa[11]
+dataa[12] => add_sub_d9h:auto_generated.dataa[12]
+dataa[13] => add_sub_d9h:auto_generated.dataa[13]
+dataa[14] => add_sub_d9h:auto_generated.dataa[14]
+dataa[15] => add_sub_d9h:auto_generated.dataa[15]
+dataa[16] => add_sub_d9h:auto_generated.dataa[16]
+dataa[17] => add_sub_d9h:auto_generated.dataa[17]
+datab[0] => add_sub_d9h:auto_generated.datab[0]
+datab[1] => add_sub_d9h:auto_generated.datab[1]
+datab[2] => add_sub_d9h:auto_generated.datab[2]
+datab[3] => add_sub_d9h:auto_generated.datab[3]
+datab[4] => add_sub_d9h:auto_generated.datab[4]
+datab[5] => add_sub_d9h:auto_generated.datab[5]
+datab[6] => add_sub_d9h:auto_generated.datab[6]
+datab[7] => add_sub_d9h:auto_generated.datab[7]
+datab[8] => add_sub_d9h:auto_generated.datab[8]
+datab[9] => add_sub_d9h:auto_generated.datab[9]
+datab[10] => add_sub_d9h:auto_generated.datab[10]
+datab[11] => add_sub_d9h:auto_generated.datab[11]
+datab[12] => add_sub_d9h:auto_generated.datab[12]
+datab[13] => add_sub_d9h:auto_generated.datab[13]
+datab[14] => add_sub_d9h:auto_generated.datab[14]
+datab[15] => add_sub_d9h:auto_generated.datab[15]
+datab[16] => add_sub_d9h:auto_generated.datab[16]
+datab[17] => add_sub_d9h:auto_generated.datab[17]
+cin => ~NO_FANOUT~
+add_sub => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= add_sub_d9h:auto_generated.result[0]
+result[1] <= add_sub_d9h:auto_generated.result[1]
+result[2] <= add_sub_d9h:auto_generated.result[2]
+result[3] <= add_sub_d9h:auto_generated.result[3]
+result[4] <= add_sub_d9h:auto_generated.result[4]
+result[5] <= add_sub_d9h:auto_generated.result[5]
+result[6] <= add_sub_d9h:auto_generated.result[6]
+result[7] <= add_sub_d9h:auto_generated.result[7]
+result[8] <= add_sub_d9h:auto_generated.result[8]
+result[9] <= add_sub_d9h:auto_generated.result[9]
+result[10] <= add_sub_d9h:auto_generated.result[10]
+result[11] <= add_sub_d9h:auto_generated.result[11]
+result[12] <= add_sub_d9h:auto_generated.result[12]
+result[13] <= add_sub_d9h:auto_generated.result[13]
+result[14] <= add_sub_d9h:auto_generated.result[14]
+result[15] <= add_sub_d9h:auto_generated.result[15]
+result[16] <= add_sub_d9h:auto_generated.result[16]
+result[17] <= add_sub_d9h:auto_generated.result[17]
+cout <= <GND>
+overflow <= <GND>
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated
+dataa[0] => op_1.IN34
+dataa[1] => op_1.IN32
+dataa[2] => op_1.IN30
+dataa[3] => op_1.IN28
+dataa[4] => op_1.IN26
+dataa[5] => op_1.IN24
+dataa[6] => op_1.IN22
+dataa[7] => op_1.IN20
+dataa[8] => op_1.IN18
+dataa[9] => op_1.IN16
+dataa[10] => op_1.IN14
+dataa[11] => op_1.IN12
+dataa[12] => op_1.IN10
+dataa[13] => op_1.IN8
+dataa[14] => op_1.IN6
+dataa[15] => op_1.IN4
+dataa[16] => op_1.IN2
+dataa[17] => op_1.IN0
+datab[0] => op_1.IN35
+datab[1] => op_1.IN33
+datab[2] => op_1.IN31
+datab[3] => op_1.IN29
+datab[4] => op_1.IN27
+datab[5] => op_1.IN25
+datab[6] => op_1.IN23
+datab[7] => op_1.IN21
+datab[8] => op_1.IN19
+datab[9] => op_1.IN17
+datab[10] => op_1.IN15
+datab[11] => op_1.IN13
+datab[12] => op_1.IN11
+datab[13] => op_1.IN9
+datab[14] => op_1.IN7
+datab[15] => op_1.IN5
+datab[16] => op_1.IN3
+datab[17] => op_1.IN1
+result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add
+data[0][0] => result[0].DATAIN
+data[0][1] => result[1].DATAIN
+data[0][2] => result[2].DATAIN
+data[0][3] => result[3].DATAIN
+data[0][4] => result[4].DATAIN
+data[0][5] => result[5].DATAIN
+data[0][6] => result[6].DATAIN
+data[0][7] => result[7].DATAIN
+data[0][8] => lpm_add_sub:adder[0].dataa[0]
+data[0][9] => lpm_add_sub:adder[0].dataa[1]
+data[0][10] => lpm_add_sub:adder[0].dataa[2]
+data[0][11] => lpm_add_sub:adder[0].dataa[3]
+data[0][12] => lpm_add_sub:adder[0].dataa[4]
+data[0][13] => lpm_add_sub:adder[0].dataa[5]
+data[0][14] => lpm_add_sub:adder[0].dataa[6]
+data[0][15] => lpm_add_sub:adder[0].dataa[7]
+data[0][16] => lpm_add_sub:adder[0].dataa[8]
+data[0][17] => lpm_add_sub:adder[0].dataa[9]
+data[0][18] => lpm_add_sub:adder[0].dataa[10]
+data[0][19] => lpm_add_sub:adder[0].dataa[11]
+data[0][20] => lpm_add_sub:adder[0].dataa[12]
+data[0][21] => lpm_add_sub:adder[0].dataa[13]
+data[1][0] => lpm_add_sub:adder[0].datab[0]
+data[1][1] => lpm_add_sub:adder[0].datab[1]
+data[1][2] => lpm_add_sub:adder[0].datab[2]
+data[1][3] => lpm_add_sub:adder[0].datab[3]
+data[1][4] => lpm_add_sub:adder[0].datab[4]
+data[1][5] => lpm_add_sub:adder[0].datab[5]
+data[1][6] => lpm_add_sub:adder[0].datab[6]
+data[1][7] => lpm_add_sub:adder[0].datab[7]
+data[1][8] => lpm_add_sub:adder[0].datab[8]
+data[1][9] => lpm_add_sub:adder[0].datab[9]
+data[1][10] => lpm_add_sub:adder[0].datab[10]
+data[1][11] => lpm_add_sub:adder[0].datab[11]
+data[1][12] => lpm_add_sub:adder[0].datab[12]
+data[1][13] => lpm_add_sub:adder[0].datab[13]
+data[1][14] => lpm_add_sub:adder[0].datab[14]
+data[1][15] => lpm_add_sub:adder[0].datab[15]
+data[1][16] => lpm_add_sub:adder[0].datab[16]
+data[1][17] => lpm_add_sub:adder[0].datab[17]
+data[1][18] => ~NO_FANOUT~
+data[1][19] => ~NO_FANOUT~
+data[1][20] => ~NO_FANOUT~
+data[1][21] => ~NO_FANOUT~
+cin => ~NO_FANOUT~
+clk => clk_out.IN0
+aclr => aclr_out.IN0
+clken => clken_out.IN0
+result[0] <= data[0][0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= data[0][1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= data[0][2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= data[0][3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= data[0][4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= data[0][5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= data[0][6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= data[0][7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= level_result_node[0][0].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= level_result_node[0][1].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= level_result_node[0][2].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= level_result_node[0][3].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= level_result_node[0][4].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= level_result_node[0][5].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= level_result_node[0][6].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= level_result_node[0][7].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= level_result_node[0][8].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= level_result_node[0][9].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= level_result_node[0][10].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= level_result_node[0][11].DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= level_result_node[0][12].DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= level_result_node[0][13].DB_MAX_OUTPUT_PORT_TYPE
+result[22] <= level_result_node[0][14].DB_MAX_OUTPUT_PORT_TYPE
+result[23] <= level_result_node[0][15].DB_MAX_OUTPUT_PORT_TYPE
+result[24] <= level_result_node[0][16].DB_MAX_OUTPUT_PORT_TYPE
+result[25] <= level_result_node[0][17].DB_MAX_OUTPUT_PORT_TYPE
+result[26] <= level_result_node[0][18].DB_MAX_OUTPUT_PORT_TYPE
+result[27] <= level_result_node[0][19].DB_MAX_OUTPUT_PORT_TYPE
+result[28] <= level_result_node[0][20].DB_MAX_OUTPUT_PORT_TYPE
+result[29] <= level_result_node[0][21].DB_MAX_OUTPUT_PORT_TYPE
+clk_out <= clk_out.DB_MAX_OUTPUT_PORT_TYPE
+aclr_out <= aclr_out.DB_MAX_OUTPUT_PORT_TYPE
+clken_out <= clken_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]
+dataa[0] => add_sub_89h:auto_generated.dataa[0]
+dataa[1] => add_sub_89h:auto_generated.dataa[1]
+dataa[2] => add_sub_89h:auto_generated.dataa[2]
+dataa[3] => add_sub_89h:auto_generated.dataa[3]
+dataa[4] => add_sub_89h:auto_generated.dataa[4]
+dataa[5] => add_sub_89h:auto_generated.dataa[5]
+dataa[6] => add_sub_89h:auto_generated.dataa[6]
+dataa[7] => add_sub_89h:auto_generated.dataa[7]
+dataa[8] => add_sub_89h:auto_generated.dataa[8]
+dataa[9] => add_sub_89h:auto_generated.dataa[9]
+dataa[10] => add_sub_89h:auto_generated.dataa[10]
+dataa[11] => add_sub_89h:auto_generated.dataa[11]
+dataa[12] => add_sub_89h:auto_generated.dataa[12]
+dataa[13] => add_sub_89h:auto_generated.dataa[13]
+dataa[14] => add_sub_89h:auto_generated.dataa[14]
+dataa[15] => add_sub_89h:auto_generated.dataa[15]
+dataa[16] => add_sub_89h:auto_generated.dataa[16]
+dataa[17] => add_sub_89h:auto_generated.dataa[17]
+dataa[18] => add_sub_89h:auto_generated.dataa[18]
+dataa[19] => add_sub_89h:auto_generated.dataa[19]
+dataa[20] => add_sub_89h:auto_generated.dataa[20]
+dataa[21] => add_sub_89h:auto_generated.dataa[21]
+datab[0] => add_sub_89h:auto_generated.datab[0]
+datab[1] => add_sub_89h:auto_generated.datab[1]
+datab[2] => add_sub_89h:auto_generated.datab[2]
+datab[3] => add_sub_89h:auto_generated.datab[3]
+datab[4] => add_sub_89h:auto_generated.datab[4]
+datab[5] => add_sub_89h:auto_generated.datab[5]
+datab[6] => add_sub_89h:auto_generated.datab[6]
+datab[7] => add_sub_89h:auto_generated.datab[7]
+datab[8] => add_sub_89h:auto_generated.datab[8]
+datab[9] => add_sub_89h:auto_generated.datab[9]
+datab[10] => add_sub_89h:auto_generated.datab[10]
+datab[11] => add_sub_89h:auto_generated.datab[11]
+datab[12] => add_sub_89h:auto_generated.datab[12]
+datab[13] => add_sub_89h:auto_generated.datab[13]
+datab[14] => add_sub_89h:auto_generated.datab[14]
+datab[15] => add_sub_89h:auto_generated.datab[15]
+datab[16] => add_sub_89h:auto_generated.datab[16]
+datab[17] => add_sub_89h:auto_generated.datab[17]
+datab[18] => add_sub_89h:auto_generated.datab[18]
+datab[19] => add_sub_89h:auto_generated.datab[19]
+datab[20] => add_sub_89h:auto_generated.datab[20]
+datab[21] => add_sub_89h:auto_generated.datab[21]
+cin => ~NO_FANOUT~
+add_sub => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= add_sub_89h:auto_generated.result[0]
+result[1] <= add_sub_89h:auto_generated.result[1]
+result[2] <= add_sub_89h:auto_generated.result[2]
+result[3] <= add_sub_89h:auto_generated.result[3]
+result[4] <= add_sub_89h:auto_generated.result[4]
+result[5] <= add_sub_89h:auto_generated.result[5]
+result[6] <= add_sub_89h:auto_generated.result[6]
+result[7] <= add_sub_89h:auto_generated.result[7]
+result[8] <= add_sub_89h:auto_generated.result[8]
+result[9] <= add_sub_89h:auto_generated.result[9]
+result[10] <= add_sub_89h:auto_generated.result[10]
+result[11] <= add_sub_89h:auto_generated.result[11]
+result[12] <= add_sub_89h:auto_generated.result[12]
+result[13] <= add_sub_89h:auto_generated.result[13]
+result[14] <= add_sub_89h:auto_generated.result[14]
+result[15] <= add_sub_89h:auto_generated.result[15]
+result[16] <= add_sub_89h:auto_generated.result[16]
+result[17] <= add_sub_89h:auto_generated.result[17]
+result[18] <= add_sub_89h:auto_generated.result[18]
+result[19] <= add_sub_89h:auto_generated.result[19]
+result[20] <= add_sub_89h:auto_generated.result[20]
+result[21] <= add_sub_89h:auto_generated.result[21]
+cout <= <GND>
+overflow <= <GND>
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated
+dataa[0] => op_1.IN42
+dataa[1] => op_1.IN40
+dataa[2] => op_1.IN38
+dataa[3] => op_1.IN36
+dataa[4] => op_1.IN34
+dataa[5] => op_1.IN32
+dataa[6] => op_1.IN30
+dataa[7] => op_1.IN28
+dataa[8] => op_1.IN26
+dataa[9] => op_1.IN24
+dataa[10] => op_1.IN22
+dataa[11] => op_1.IN20
+dataa[12] => op_1.IN18
+dataa[13] => op_1.IN16
+dataa[14] => op_1.IN14
+dataa[15] => op_1.IN12
+dataa[16] => op_1.IN10
+dataa[17] => op_1.IN8
+dataa[18] => op_1.IN6
+dataa[19] => op_1.IN4
+dataa[20] => op_1.IN2
+dataa[21] => op_1.IN0
+datab[0] => op_1.IN43
+datab[1] => op_1.IN41
+datab[2] => op_1.IN39
+datab[3] => op_1.IN37
+datab[4] => op_1.IN35
+datab[5] => op_1.IN33
+datab[6] => op_1.IN31
+datab[7] => op_1.IN29
+datab[8] => op_1.IN27
+datab[9] => op_1.IN25
+datab[10] => op_1.IN23
+datab[11] => op_1.IN21
+datab[12] => op_1.IN19
+datab[13] => op_1.IN17
+datab[14] => op_1.IN15
+datab[15] => op_1.IN13
+datab[16] => op_1.IN11
+datab[17] => op_1.IN9
+datab[18] => op_1.IN7
+datab[19] => op_1.IN5
+datab[20] => op_1.IN3
+datab[21] => op_1.IN1
+result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|const_mult:mult|lpm_mult:lpm_mult_component|altshift:external_latency_ffs
+data[0] => result[0].DATAIN
+data[1] => result[1].DATAIN
+data[2] => result[2].DATAIN
+data[3] => result[3].DATAIN
+data[4] => result[4].DATAIN
+data[5] => result[5].DATAIN
+data[6] => result[6].DATAIN
+data[7] => result[7].DATAIN
+data[8] => result[8].DATAIN
+data[9] => result[9].DATAIN
+data[10] => result[10].DATAIN
+data[11] => result[11].DATAIN
+data[12] => result[12].DATAIN
+data[13] => result[13].DATAIN
+data[14] => result[14].DATAIN
+data[15] => result[15].DATAIN
+data[16] => result[16].DATAIN
+data[17] => result[17].DATAIN
+data[18] => result[18].DATAIN
+data[19] => result[19].DATAIN
+data[20] => result[20].DATAIN
+data[21] => result[21].DATAIN
+data[22] => result[22].DATAIN
+data[23] => result[23].DATAIN
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= data[12].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= data[13].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= data[14].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= data[15].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= data[16].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= data[17].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= data[18].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= data[19].DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= data[20].DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= data[21].DB_MAX_OUTPUT_PORT_TYPE
+result[22] <= data[22].DB_MAX_OUTPUT_PORT_TYPE
+result[23] <= data[23].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd
+B[0] => BCD_0[0].DATAIN
+B[1] => w29[0].IN1
+B[2] => w25[0].IN1
+B[3] => w21[0].IN1
+B[4] => w17[0].IN1
+B[5] => w14[0].IN1
+B[6] => w11[0].IN1
+B[7] => w8[0].IN1
+B[8] => w6[0].IN1
+B[9] => w4[0].IN1
+B[10] => w2[0].IN1
+B[11] => w1[0].IN1
+B[12] => w1[1].IN1
+B[13] => w1[2].IN1
+B[14] => w1[3].IN1
+B[15] => w3[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A29.port1
+BCD_0[2] <= add3_ge5:A29.port1
+BCD_0[3] <= add3_ge5:A29.port1
+BCD_1[0] <= add3_ge5:A29.port1
+BCD_1[1] <= add3_ge5:A28.port1
+BCD_1[2] <= add3_ge5:A28.port1
+BCD_1[3] <= add3_ge5:A28.port1
+BCD_2[0] <= add3_ge5:A28.port1
+BCD_2[1] <= add3_ge5:A27.port1
+BCD_2[2] <= add3_ge5:A27.port1
+BCD_2[3] <= add3_ge5:A27.port1
+BCD_3[0] <= add3_ge5:A27.port1
+BCD_3[1] <= add3_ge5:A26.port1
+BCD_3[2] <= add3_ge5:A26.port1
+BCD_3[3] <= add3_ge5:A26.port1
+BCD_4[0] <= add3_ge5:A26.port1
+BCD_4[1] <= add3_ge5:A22.port1
+BCD_4[2] <= add3_ge5:A18.port1
+BCD_4[3] <= <GND>
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A1
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A2
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A3
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A4
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A5
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A6
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A7
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A8
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A9
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A10
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A11
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A12
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A13
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A14
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A15
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A16
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A17
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A18
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A19
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A20
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A21
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A22
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A23
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A24
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A25
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A26
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A27
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A28
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|bin2bcd_16:bcd|add3_ge5:A29
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex14|hex_to_7seg:h0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex14|hex_to_7seg:h1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex14|hex_to_7seg:h2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex14|hex_to_7seg:h3
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex14|hex_to_7seg:h4
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_3/ex14/db/ex10.hif b/part_3/ex14/db/ex10.hif
new file mode 100755
index 0000000..78628d9
--- /dev/null
+++ b/part_3/ex14/db/ex10.hif
diff --git a/part_2/ex9_partially_working/db/ex9.lpc.html b/part_3/ex14/db/ex10.lpc.html
index 58bcaf3..80d0672 100755
--- a/part_2/ex9_partially_working/db/ex9.lpc.html
+++ b/part_3/ex14/db/ex10.lpc.html
@@ -16,23 +16,7 @@
 <TH>Output only Bidir</TH>
 </TR>
 <TR >
-<TD >SEG5</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >7</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >SEG4</TD>
+<TD >h4</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -48,7 +32,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG3</TD>
+<TD >h3</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -64,7 +48,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG2</TD>
+<TD >h2</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -80,7 +64,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG1</TD>
+<TD >h1</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -96,7 +80,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG0</TD>
+<TD >h0</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -112,7 +96,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A35</TD>
+<TD >bcd|A29</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -128,7 +112,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A34</TD>
+<TD >bcd|A28</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -144,7 +128,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A33</TD>
+<TD >bcd|A27</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -160,7 +144,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A32</TD>
+<TD >bcd|A26</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -176,23 +160,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A31</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A30</TD>
+<TD >bcd|A25</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -208,7 +176,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A29</TD>
+<TD >bcd|A24</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -224,7 +192,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A28</TD>
+<TD >bcd|A23</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -240,7 +208,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A27</TD>
+<TD >bcd|A22</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -256,7 +224,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A26</TD>
+<TD >bcd|A21</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -272,7 +240,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A25</TD>
+<TD >bcd|A20</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -288,7 +256,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A24</TD>
+<TD >bcd|A19</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -304,15 +272,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A23</TD>
+<TD >bcd|A18</TD>
 <TD >4</TD>
+<TD >1</TD>
 <TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
 <TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -320,7 +288,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A22</TD>
+<TD >bcd|A17</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -336,7 +304,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A21</TD>
+<TD >bcd|A16</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -352,7 +320,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A20</TD>
+<TD >bcd|A15</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -368,23 +336,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A19</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A18</TD>
+<TD >bcd|A14</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -400,7 +352,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A17</TD>
+<TD >bcd|A13</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -416,7 +368,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A16</TD>
+<TD >bcd|A12</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -432,7 +384,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A15</TD>
+<TD >bcd|A11</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -448,7 +400,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A14</TD>
+<TD >bcd|A10</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -464,15 +416,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A13</TD>
+<TD >bcd|A9</TD>
 <TD >4</TD>
+<TD >1</TD>
 <TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
 <TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -480,7 +432,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A12</TD>
+<TD >bcd|A8</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -496,7 +448,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A11</TD>
+<TD >bcd|A7</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -512,15 +464,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A10</TD>
+<TD >bcd|A6</TD>
 <TD >4</TD>
-<TD >1</TD>
 <TD >0</TD>
-<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
 <TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -528,7 +480,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A9</TD>
+<TD >bcd|A5</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -544,7 +496,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A8</TD>
+<TD >bcd|A4</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -560,15 +512,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A7</TD>
+<TD >bcd|A3</TD>
 <TD >4</TD>
+<TD >1</TD>
 <TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
 <TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -576,7 +528,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A6</TD>
+<TD >bcd|A2</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -592,7 +544,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A5</TD>
+<TD >bcd|A1</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -608,15 +560,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A4</TD>
-<TD >4</TD>
-<TD >1</TD>
+<TD >bcd</TD>
+<TD >16</TD>
+<TD >3</TD>
 <TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
+<TD >3</TD>
+<TD >20</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >3</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -624,12 +576,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A3</TD>
-<TD >4</TD>
+<TD >mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated</TD>
+<TD >44</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >4</TD>
+<TD >22</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -640,12 +592,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A2</TD>
-<TD >4</TD>
+<TD >mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated</TD>
+<TD >36</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >4</TD>
+<TD >18</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -656,63 +608,47 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A1</TD>
-<TD >4</TD>
-<TD >1</TD>
+<TD >mult</TD>
+<TD >10</TD>
 <TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
+<TD >24</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-</TR>
-<TR >
-<TD >BCD</TD>
-<TD >16</TD>
-<TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >20</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
+</TR>
+<TR >
+<TD >p</TD>
+<TD >12</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
+<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
-</TR>
-<TR >
-<TD >COUNT0</TD>
-<TD >3</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >16</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
+</TR>
+<TR >
+<TD >dac</TD>
+<TD >12</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
+<TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
-</TR>
-<TR >
-<TD >DEL0</TD>
-<TD >16</TD>
-<TD >7</TD>
 <TD >0</TD>
-<TD >7</TD>
-<TD >1</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >7</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -720,12 +656,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >LFSR0</TD>
-<TD >2</TD>
+<TD >rom|altsyncram_component|auto_generated</TD>
+<TD >11</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >7</TD>
+<TD >10</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -736,12 +672,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >FSM</TD>
-<TD >4</TD>
+<TD >rom</TD>
+<TD >11</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >12</TD>
+<TD >10</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -752,12 +688,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >TICK1</TD>
-<TD >2</TD>
+<TD >fin_address</TD>
+<TD >11</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >1</TD>
+<TD >10</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -768,7 +704,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >TICK0</TD>
+<TD >tick</TD>
 <TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
diff --git a/part_3/ex14/db/ex10.lpc.rdb b/part_3/ex14/db/ex10.lpc.rdb
new file mode 100755
index 0000000..45f9272
--- /dev/null
+++ b/part_3/ex14/db/ex10.lpc.rdb
diff --git a/part_3/ex14/db/ex10.lpc.txt b/part_3/ex14/db/ex10.lpc.txt
new file mode 100755
index 0000000..b37bd19
--- /dev/null
+++ b/part_3/ex14/db/ex10.lpc.txt
@@ -0,0 +1,50 @@
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                                                        ;
++------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                                                    ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; h4                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h3                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h2                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h1                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h0                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A29                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A28                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A27                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A26                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A25                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A24                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A23                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A22                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A21                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A20                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A19                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A18                                                                      ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A17                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A16                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A15                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A14                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A13                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A12                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A11                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A10                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A9                                                                       ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A8                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A7                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A6                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A5                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A4                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A3                                                                       ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A2                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A1                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd                                                                          ; 16    ; 3              ; 0            ; 3              ; 20     ; 3               ; 3             ; 3               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated ; 44    ; 0              ; 0            ; 0              ; 22     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated             ; 36    ; 0              ; 0            ; 0              ; 18     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; mult                                                                         ; 10    ; 0              ; 0            ; 0              ; 24     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; p                                                                            ; 12    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dac                                                                          ; 12    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; rom|altsyncram_component|auto_generated                                      ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; rom                                                                          ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; fin_address                                                                  ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; tick                                                                         ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex9_final/db/ex9.map.ammdb b/part_3/ex14/db/ex10.map.ammdb
index 174eb00..174eb00 100755
--- a/part_2/ex9_final/db/ex9.map.ammdb
+++ b/part_3/ex14/db/ex10.map.ammdb
diff --git a/part_3/ex14/db/ex10.map.bpm b/part_3/ex14/db/ex10.map.bpm
new file mode 100755
index 0000000..4069b6b
--- /dev/null
+++ b/part_3/ex14/db/ex10.map.bpm
diff --git a/part_3/ex14/db/ex10.map.cdb b/part_3/ex14/db/ex10.map.cdb
new file mode 100755
index 0000000..6c9a5fa
--- /dev/null
+++ b/part_3/ex14/db/ex10.map.cdb
diff --git a/part_3/ex14/db/ex10.map.hdb b/part_3/ex14/db/ex10.map.hdb
new file mode 100755
index 0000000..140aa11
--- /dev/null
+++ b/part_3/ex14/db/ex10.map.hdb
diff --git a/part_3/ex14/db/ex10.map.kpt b/part_3/ex14/db/ex10.map.kpt
new file mode 100755
index 0000000..c2cc3eb
--- /dev/null
+++ b/part_3/ex14/db/ex10.map.kpt
diff --git a/part_2/ex9_final/db/ex9.map.logdb b/part_3/ex14/db/ex10.map.logdb
index d45424f..d45424f 100755
--- a/part_2/ex9_final/db/ex9.map.logdb
+++ b/part_3/ex14/db/ex10.map.logdb
diff --git a/part_3/ex14/db/ex10.map.qmsg b/part_3/ex14/db/ex10.map.qmsg
new file mode 100755
index 0000000..e3a44bb
--- /dev/null
+++ b/part_3/ex14/db/ex10.map.qmsg
@@ -0,0 +1,87 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480700265802 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480700265806 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 17:37:45 2016 " "Processing started: Fri Dec 02 17:37:45 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480700265806 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700265806 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700265806 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700266119 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700266157 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480700266478 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480700266478 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700274981 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700274981 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700274986 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700274986 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274991 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274992 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274992 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274992 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274992 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274993 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274993 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274993 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274994 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274994 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274994 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274994 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274994 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274994 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274994 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274994 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274995 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274995 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274995 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274995 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274995 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274995 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274995 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274995 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274997 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274997 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274998 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274998 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700274998 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700274998 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700274998 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex14.v 1 1 " "Found 1 design units, including 1 entities, in source file ex14.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex14 " "Found entity 1: ex14" {  } { { "ex14.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275010 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275010 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/rom.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "verilog_files/ROM.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275014 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275014 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_5000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_5000 " "Found entity 1: tick_5000" {  } { { "verilog_files/tick_5000.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/tick_5000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275020 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275020 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275027 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275027 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275032 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275032 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "const_mult.v 1 1 " "Found 1 design units, including 1 entities, in source file const_mult.v" { { "Info" "ISGN_ENTITY_NAME" "1 const_mult " "Found entity 1: const_mult" {  } { { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275035 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275035 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_offset.v 1 1 " "Found 1 design units, including 1 entities, in source file add_offset.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_offset " "Found entity 1: add_offset" {  } { { "add_offset.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/add_offset.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275041 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275041 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex14 " "Elaborating entity \"ex14\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480700275268 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_5000 tick_5000:tick " "Elaborating entity \"tick_5000\" for hierarchy \"tick_5000:tick\"" {  } { { "ex14.v" "tick" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 14 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275312 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_offset add_offset:fin_address " "Elaborating entity \"add_offset\" for hierarchy \"add_offset:fin_address\"" {  } { { "ex14.v" "fin_address" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 16 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275319 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:rom " "Elaborating entity \"ROM\" for hierarchy \"ROM:rom\"" {  } { { "ex14.v" "rom" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 18 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275329 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:rom\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/ROM.v" "altsyncram_component" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v" 82 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275383 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "ROM:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:rom\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/ROM.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v" 82 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275390 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom_data/rom_data.mif " "Parameter \"init_file\" = \"./rom_data/rom_data.mif\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 10 " "Parameter \"width_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275390 ""}  } { { "verilog_files/ROM.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v" 82 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480700275390 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6ng1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6ng1 " "Found entity 1: altsyncram_6ng1" {  } { { "db/altsyncram_6ng1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/altsyncram_6ng1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275441 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275441 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_6ng1 ROM:rom\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated " "Elaborating entity \"altsyncram_6ng1\" for hierarchy \"ROM:rom\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275442 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:dac " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:dac\"" {  } { { "ex14.v" "dac" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 20 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275455 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:p " "Elaborating entity \"pwm\" for hierarchy \"pwm:p\"" {  } { { "ex14.v" "p" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 21 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275464 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "const_mult const_mult:mult " "Elaborating entity \"const_mult\" for hierarchy \"const_mult:mult\"" {  } { { "ex14.v" "mult" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 23 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275477 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "const_mult.v" "lpm_mult_component" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275522 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275529 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "const_mult:mult\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"const_mult:mult\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275529 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275529 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275529 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 10 " "Parameter \"lpm_widtha\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275529 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 14 " "Parameter \"lpm_widthb\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275529 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 24 " "Parameter \"lpm_widthp\" = \"24\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480700275529 ""}  } { { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480700275529 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multcore const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core " "Elaborating entity \"multcore\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\"" {  } { { "lpm_mult.tdf" "mult_core" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275565 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275578 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder " "Elaborating entity \"mpar_add\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\"" {  } { { "multcore.tdf" "padder" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275598 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "multcore.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275606 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275633 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275640 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_d9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_d9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_d9h " "Found entity 1: add_sub_d9h" {  } { { "db/add_sub_d9h.tdf" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_d9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275688 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275688 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_d9h const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_d9h:auto_generated " "Elaborating entity \"add_sub_d9h\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_d9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275689 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add " "Elaborating entity \"mpar_add\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\"" {  } { { "mpar_add.tdf" "sub_par_add" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275700 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275707 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275711 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275717 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_89h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_89h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_89h " "Found entity 1: add_sub_89h" {  } { { "db/add_sub_89h.tdf" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_89h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700275765 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700275765 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_89h const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_89h:auto_generated " "Elaborating entity \"add_sub_89h\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_89h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275765 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift const_mult:mult\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs " "Elaborating entity \"altshift\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\"" {  } { { "lpm_mult.tdf" "external_latency_ffs" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275793 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275800 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:bcd " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:bcd\"" {  } { { "ex14.v" "bcd" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 25 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275803 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:bcd\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:bcd\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275811 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:h0\"" {  } { { "ex14.v" "h0" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 27 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700275823 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480700276788 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[1\] GND " "Pin \"HEX4\[1\]\" is stuck at GND" {  } { { "ex14.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 6 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480700276943 "|ex14|HEX4[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480700276943 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480700277020 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Desktop/ex14/output_files/ex10.map.smsg " "Generated suppressed messages file /Desktop/ex14/output_files/ex10.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700277490 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480700277775 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700277775 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480700278342 ""} { "Info" "ICUT_CUT_TM_OPINS" "40 " "Implemented 40 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480700278342 ""} { "Info" "ICUT_CUT_TM_LCELLS" "260 " "Implemented 260 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480700278342 ""} { "Info" "ICUT_CUT_TM_RAMS" "10 " "Implemented 10 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1480700278342 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480700278342 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "915 " "Peak virtual memory: 915 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480700278442 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 17:37:58 2016 " "Processing ended: Fri Dec 02 17:37:58 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480700278442 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480700278442 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480700278442 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700278442 ""}
diff --git a/part_3/ex14/db/ex10.map.rdb b/part_3/ex14/db/ex10.map.rdb
new file mode 100755
index 0000000..ad5d549
--- /dev/null
+++ b/part_3/ex14/db/ex10.map.rdb
diff --git a/part_3/ex14/db/ex10.map_bb.cdb b/part_3/ex14/db/ex10.map_bb.cdb
new file mode 100755
index 0000000..5d6d99b
--- /dev/null
+++ b/part_3/ex14/db/ex10.map_bb.cdb
diff --git a/part_3/ex14/db/ex10.map_bb.hdb b/part_3/ex14/db/ex10.map_bb.hdb
new file mode 100755
index 0000000..10c1ebc
--- /dev/null
+++ b/part_3/ex14/db/ex10.map_bb.hdb
diff --git a/part_2/ex9_final/db/ex9.map_bb.logdb b/part_3/ex14/db/ex10.map_bb.logdb
index d45424f..d45424f 100755
--- a/part_2/ex9_final/db/ex9.map_bb.logdb
+++ b/part_3/ex14/db/ex10.map_bb.logdb
diff --git a/part_3/ex14/db/ex10.pre_map.hdb b/part_3/ex14/db/ex10.pre_map.hdb
new file mode 100755
index 0000000..a3cbef4
--- /dev/null
+++ b/part_3/ex14/db/ex10.pre_map.hdb
diff --git a/part_3/ex14/db/ex10.root_partition.map.reg_db.cdb b/part_3/ex14/db/ex10.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..f882f60
--- /dev/null
+++ b/part_3/ex14/db/ex10.root_partition.map.reg_db.cdb
diff --git a/part_3/ex14/db/ex10.routing.rdb b/part_3/ex14/db/ex10.routing.rdb
new file mode 100755
index 0000000..5f0321a
--- /dev/null
+++ b/part_3/ex14/db/ex10.routing.rdb
diff --git a/part_3/ex14/db/ex10.rtlv.hdb b/part_3/ex14/db/ex10.rtlv.hdb
new file mode 100755
index 0000000..97b384c
--- /dev/null
+++ b/part_3/ex14/db/ex10.rtlv.hdb
diff --git a/part_3/ex14/db/ex10.rtlv_sg.cdb b/part_3/ex14/db/ex10.rtlv_sg.cdb
new file mode 100755
index 0000000..3964e7e
--- /dev/null
+++ b/part_3/ex14/db/ex10.rtlv_sg.cdb
diff --git a/part_3/ex14/db/ex10.rtlv_sg_swap.cdb b/part_3/ex14/db/ex10.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..b2d6537
--- /dev/null
+++ b/part_3/ex14/db/ex10.rtlv_sg_swap.cdb
diff --git a/part_2/ex9_final/db/ex9.sld_design_entry.sci b/part_3/ex14/db/ex10.sld_design_entry.sci
index 92c1102..92c1102 100755
--- a/part_2/ex9_final/db/ex9.sld_design_entry.sci
+++ b/part_3/ex14/db/ex10.sld_design_entry.sci
diff --git a/part_2/ex9_final/db/ex9.sld_design_entry_dsc.sci b/part_3/ex14/db/ex10.sld_design_entry_dsc.sci
index 92c1102..92c1102 100755
--- a/part_2/ex9_final/db/ex9.sld_design_entry_dsc.sci
+++ b/part_3/ex14/db/ex10.sld_design_entry_dsc.sci
diff --git a/part_2/ex9_final/db/ex9.smart_action.txt b/part_3/ex14/db/ex10.smart_action.txt
index 437a63e..437a63e 100755
--- a/part_2/ex9_final/db/ex9.smart_action.txt
+++ b/part_3/ex14/db/ex10.smart_action.txt
diff --git a/part_3/ex14/db/ex10.smp_dump.txt b/part_3/ex14/db/ex10.smp_dump.txt
new file mode 100755
index 0000000..99ebdc8
--- /dev/null
+++ b/part_3/ex14/db/ex10.smp_dump.txt
@@ -0,0 +1,6 @@
+
+State Machine - |ex14|spi2dac:dac|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
diff --git a/part_3/ex14/db/ex10.sta.qmsg b/part_3/ex14/db/ex10.sta.qmsg
new file mode 100755
index 0000000..4bd064d
--- /dev/null
+++ b/part_3/ex14/db/ex10.sta.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480700335510 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480700335514 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 17:38:54 2016 " "Processing started: Fri Dec 02 17:38:54 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480700335514 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700335514 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex10 -c ex10 " "Command: quartus_sta ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700335514 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480700335664 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700336126 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700336355 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700336356 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700336403 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700336403 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex10.sdc " "Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337125 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337127 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480700337133 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_5000:tick\|CLK_OUT tick_5000:tick\|CLK_OUT " "create_clock -period 1.000 -name tick_5000:tick\|CLK_OUT tick_5000:tick\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480700337133 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2dac:dac\|clk_1MHz spi2dac:dac\|clk_1MHz " "create_clock -period 1.000 -name spi2dac:dac\|clk_1MHz spi2dac:dac\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480700337133 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337133 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337143 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337148 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480700337150 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480700337197 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480700337243 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337243 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.834 " "Worst-case setup slack is -3.834" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337260 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337260 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.834             -62.108 spi2dac:dac\|clk_1MHz  " "   -3.834             -62.108 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337260 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.572            -126.378 CLOCK_50  " "   -3.572            -126.378 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337260 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.476             -13.479 tick_5000:tick\|CLK_OUT  " "   -1.476             -13.479 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337260 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337260 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.212 " "Worst-case hold slack is 0.212" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337281 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337281 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.212               0.000 CLOCK_50  " "    0.212               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337281 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.528               0.000 tick_5000:tick\|CLK_OUT  " "    0.528               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337281 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.731               0.000 spi2dac:dac\|clk_1MHz  " "    0.731               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337281 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337281 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337312 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337331 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337351 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337351 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -104.886 CLOCK_50  " "   -2.174            -104.886 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337351 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -10.637 spi2dac:dac\|clk_1MHz  " "   -0.394             -10.637 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337351 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.320 tick_5000:tick\|CLK_OUT  " "   -0.394              -5.320 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700337351 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337351 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480700337386 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700337433 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700338665 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700338822 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480700338852 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700338852 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.877 " "Worst-case setup slack is -3.877" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.877             -63.295 spi2dac:dac\|clk_1MHz  " "   -3.877             -63.295 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.664            -119.563 CLOCK_50  " "   -3.664            -119.563 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338875 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.546             -13.976 tick_5000:tick\|CLK_OUT  " "   -1.546             -13.976 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338875 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700338875 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.131 " "Worst-case hold slack is -0.131" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.131              -1.428 CLOCK_50  " "   -0.131              -1.428 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.507               0.000 tick_5000:tick\|CLK_OUT  " "    0.507               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.718               0.000 spi2dac:dac\|clk_1MHz  " "    0.718               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338899 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700338899 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700338918 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700338939 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338959 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338959 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -101.938 CLOCK_50  " "   -2.174            -101.938 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338959 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -10.531 spi2dac:dac\|clk_1MHz  " "   -0.394             -10.531 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338959 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.266 tick_5000:tick\|CLK_OUT  " "   -0.394              -5.266 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700338959 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700338959 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480700339004 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700339338 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700340490 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700340668 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480700340670 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700340670 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.907 " "Worst-case setup slack is -2.907" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.907             -69.680 CLOCK_50  " "   -2.907             -69.680 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.889             -28.963 spi2dac:dac\|clk_1MHz  " "   -1.889             -28.963 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.574              -4.704 tick_5000:tick\|CLK_OUT  " "   -0.574              -4.704 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340691 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700340691 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.184 " "Worst-case hold slack is 0.184" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.184               0.000 CLOCK_50  " "    0.184               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.239               0.000 tick_5000:tick\|CLK_OUT  " "    0.239               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340728 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.304               0.000 spi2dac:dac\|clk_1MHz  " "    0.304               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340728 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700340728 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700340769 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700340797 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340825 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340825 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174             -95.017 CLOCK_50  " "   -2.174             -95.017 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340825 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.089               0.000 tick_5000:tick\|CLK_OUT  " "    0.089               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340825 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.099               0.000 spi2dac:dac\|clk_1MHz  " "    0.099               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700340825 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700340825 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480700340854 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700341184 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480700341186 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700341186 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.457 " "Worst-case setup slack is -2.457" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341209 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341209 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.457             -55.444 CLOCK_50  " "   -2.457             -55.444 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341209 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.822             -27.647 spi2dac:dac\|clk_1MHz  " "   -1.822             -27.647 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341209 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.536              -4.307 tick_5000:tick\|CLK_OUT  " "   -0.536              -4.307 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341209 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700341209 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.029 " "Worst-case hold slack is -0.029" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341228 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341228 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.029              -0.033 CLOCK_50  " "   -0.029              -0.033 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341228 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.210               0.000 tick_5000:tick\|CLK_OUT  " "    0.210               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341228 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.275               0.000 spi2dac:dac\|clk_1MHz  " "    0.275               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341228 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700341228 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700341249 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700341272 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -100.860 CLOCK_50  " "   -2.174            -100.860 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.101               0.000 tick_5000:tick\|CLK_OUT  " "    0.101               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.112               0.000 spi2dac:dac\|clk_1MHz  " "    0.112               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480700341297 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700341297 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700343770 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700343774 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1246 " "Peak virtual memory: 1246 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480700344098 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 17:39:04 2016 " "Processing ended: Fri Dec 02 17:39:04 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480700344098 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480700344098 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480700344098 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480700344098 ""}
diff --git a/part_3/ex14/db/ex10.sta.rdb b/part_3/ex14/db/ex10.sta.rdb
new file mode 100755
index 0000000..18305b5
--- /dev/null
+++ b/part_3/ex14/db/ex10.sta.rdb
diff --git a/part_3/ex14/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb b/part_3/ex14/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..97ab615
--- /dev/null
+++ b/part_3/ex14/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex9_final/db/ex9.tis_db_list.ddb b/part_3/ex14/db/ex10.tis_db_list.ddb
index 88225e8..88225e8 100755
--- a/part_2/ex9_final/db/ex9.tis_db_list.ddb
+++ b/part_3/ex14/db/ex10.tis_db_list.ddb
diff --git a/part_3/ex14/db/ex10.tiscmp.fast_1100mv_0c.ddb b/part_3/ex14/db/ex10.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..7abc119
--- /dev/null
+++ b/part_3/ex14/db/ex10.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_3/ex14/db/ex10.tiscmp.fast_1100mv_85c.ddb b/part_3/ex14/db/ex10.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..c6c2231
--- /dev/null
+++ b/part_3/ex14/db/ex10.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_3/ex14/db/ex10.tiscmp.slow_1100mv_0c.ddb b/part_3/ex14/db/ex10.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..800620f
--- /dev/null
+++ b/part_3/ex14/db/ex10.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_3/ex14/db/ex10.tiscmp.slow_1100mv_85c.ddb b/part_3/ex14/db/ex10.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..7a43a55
--- /dev/null
+++ b/part_3/ex14/db/ex10.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_3/ex14/db/ex10.tmw_info b/part_3/ex14/db/ex10.tmw_info
new file mode 100755
index 0000000..44ba137
--- /dev/null
+++ b/part_3/ex14/db/ex10.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:01:25
+start_analysis_synthesis:s:00:00:16-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:43-start_full_compilation
+start_assembler:s:00:00:11-start_full_compilation
+start_timing_analyzer:s:00:00:12-start_full_compilation
+start_eda_netlist_writer:s:00:00:03-start_full_compilation
diff --git a/part_3/ex14/db/ex10.vpr.ammdb b/part_3/ex14/db/ex10.vpr.ammdb
new file mode 100755
index 0000000..6313c3b
--- /dev/null
+++ b/part_3/ex14/db/ex10.vpr.ammdb
diff --git a/part_3/ex14/db/ex10_1.cmp.bpm b/part_3/ex14/db/ex10_1.cmp.bpm
new file mode 100755
index 0000000..283688a
--- /dev/null
+++ b/part_3/ex14/db/ex10_1.cmp.bpm
diff --git a/part_2/ex9_final/db/ex9_partition_pins.json b/part_3/ex14/db/ex10_partition_pins.json
index 701d3b6..93dd4f8 100755
--- a/part_2/ex9_final/db/ex9_partition_pins.json
+++ b/part_3/ex14/db/ex10_partition_pins.json
@@ -4,6 +4,26 @@
 			"name" : "Top",
 			"pins" : [
 				{
+					"name" : "DAC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_LD",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "PWM_OUT",
+					"strict" : false
+				},
+				{
 					"name" : "HEX0[0]",
 					"strict" : false
 				},
@@ -120,10 +140,6 @@
 					"strict" : false
 				},
 				{
-					"name" : "HEX4[1]",
-					"strict" : false
-				},
-				{
 					"name" : "HEX4[2]",
 					"strict" : false
 				},
@@ -144,55 +160,47 @@
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[0]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[1]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[2]",
+					"name" : "CLOCK_50",
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[3]",
+					"name" : "SW[2]",
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[4]",
+					"name" : "SW[1]",
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[5]",
+					"name" : "SW[0]",
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[6]",
+					"name" : "SW[6]",
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[7]",
+					"name" : "SW[3]",
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[8]",
+					"name" : "SW[7]",
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[9]",
+					"name" : "SW[8]",
 					"strict" : false
 				},
 				{
-					"name" : "KEY[0]",
+					"name" : "SW[9]",
 					"strict" : false
 				},
 				{
-					"name" : "CLOCK_50",
+					"name" : "SW[5]",
 					"strict" : false
 				},
 				{
-					"name" : "KEY[3]",
+					"name" : "SW[4]",
 					"strict" : false
 				}
 			]
diff --git a/part_3/ex14/db/prev_cmp_ex10.qmsg b/part_3/ex14/db/prev_cmp_ex10.qmsg
new file mode 100755
index 0000000..9de86d1
--- /dev/null
+++ b/part_3/ex14/db/prev_cmp_ex10.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480700193472 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480700193476 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 17:36:33 2016 " "Processing started: Fri Dec 02 17:36:33 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480700193476 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700193476 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700193476 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700193815 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700193853 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480700194236 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480700194237 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202865 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202865 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202870 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202870 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202875 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202877 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202877 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202877 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202877 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202877 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202877 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202877 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202879 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202879 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202879 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202879 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202879 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202879 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202879 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202879 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202880 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202880 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202880 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202880 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202880 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202880 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202880 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202880 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202881 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202881 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202881 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202881 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480700202882 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202882 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202882 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex14.v 1 1 " "Found 1 design units, including 1 entities, in source file ex14.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex14 " "Found entity 1: ex14" {  } { { "ex14.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202892 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202892 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/rom.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "verilog_files/ROM.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202896 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202896 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_5000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_5000 " "Found entity 1: tick_5000" {  } { { "verilog_files/tick_5000.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/tick_5000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202902 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202902 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202908 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202908 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202913 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202913 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "const_mult.v 1 1 " "Found 1 design units, including 1 entities, in source file const_mult.v" { { "Info" "ISGN_ENTITY_NAME" "1 const_mult " "Found entity 1: const_mult" {  } { { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202916 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202916 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_offset.v 1 1 " "Found 1 design units, including 1 entities, in source file add_offset.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_offset " "Found entity 1: add_offset" {  } { { "add_offset.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/add_offset.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480700202920 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700202920 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex14 " "Elaborating entity \"ex14\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480700203259 ""}
+{ "Error" "EVRFX_VERI_OPPOSITE_DIRECTION" "ex14.v(25) " "Verilog HDL error at ex14.v(25): part-select direction is opposite from prefix index direction" {  } { { "ex14.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 25 0 0 } }  } 0 10198 "Verilog HDL error at %1!s!: part-select direction is opposite from prefix index direction" 0 0 "Analysis & Synthesis" 0 -1 1480700203262 ""}
+{ "Error" "EVRFX_HDL_SEE_DECLARATION" "freq_fin ex14.v(12) " "HDL error at ex14.v(12): see declaration for object \"freq_fin\"" {  } { { "ex14.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v" 12 0 0 } }  } 0 10784 "HDL error at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480700203269 ""}
+{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" {  } {  } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480700203270 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Desktop/ex14/output_files/ex10.map.smsg " "Generated suppressed messages file /Desktop/ex14/output_files/ex10.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700203358 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 3 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "839 " "Peak virtual memory: 839 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480700203697 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Dec 02 17:36:43 2016 " "Processing ended: Fri Dec 02 17:36:43 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480700203697 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480700203697 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480700203697 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700203697 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 3 s " "Quartus Prime Full Compilation was unsuccessful. 5 errors, 3 warnings" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480700204883 ""}
diff --git a/part_2/ex9_partially_working/ex9.qpf b/part_3/ex14/ex10.qpf
index 28b4ce8..e7dc424 100755
--- a/part_2/ex9_partially_working/ex9.qpf
+++ b/part_3/ex14/ex10.qpf
@@ -19,13 +19,13 @@
 #
 # Quartus Prime
 # Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
+# Date created = 09:17:00  November 29, 2016
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "16.0"
-DATE = "10:28:00  November 25, 2016"
+DATE = "09:17:00  November 29, 2016"
 
 # Revisions
 
-PROJECT_REVISION = "ex9"
+PROJECT_REVISION = "ex10"
diff --git a/part_3/ex14/ex10.qsf b/part_3/ex14/ex10.qsf
new file mode 100755
index 0000000..96c1b31
--- /dev/null
+++ b/part_3/ex14/ex10.qsf
@@ -0,0 +1,327 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition#============================================================
+# CLOCK
+#============================================================
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+
+
+
+#============================================================
+# HEX0
+#============================================================
+
+#============================================================
+# HEX1
+#============================================================
+
+#============================================================
+# HEX2
+#============================================================
+
+#============================================================
+# HEX3
+#============================================================
+
+#============================================================
+# HEX4
+#============================================================
+
+#============================================================
+# HEX5
+#============================================================
+
+#============================================================
+# KEY
+#============================================================
+
+#============================================================
+# LEDR
+#============================================================
+
+#============================================================
+# SW
+#============================================================
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
+# Date created = 09:17:00  November 29, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ex10_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex14
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:17:00  NOVEMBER 29, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to "LEDR[3]#============================================================"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
+set_global_assignment -name VERILOG_FILE ex14.v
+set_global_assignment -name QIP_FILE verilog_files/ROM.qip
+set_global_assignment -name VERILOG_FILE verilog_files/ROM.v
+set_global_assignment -name VERILOG_FILE verilog_files/tick_5000.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2dac.v
+set_global_assignment -name VERILOG_FILE verilog_files/pwm.v
+set_global_assignment -name QIP_FILE const_mult.qip
+set_global_assignment -name VERILOG_FILE add_offset.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/part_3/ex14/ex10.qws b/part_3/ex14/ex10.qws
new file mode 100755
index 0000000..b8e57c1
--- /dev/null
+++ b/part_3/ex14/ex10.qws
diff --git a/part_3/ex14/ex10.v.bak b/part_3/ex14/ex10.v.bak
new file mode 100755
index 0000000..8b13789
--- /dev/null
+++ b/part_3/ex14/ex10.v.bak
@@ -0,0 +1 @@
+
diff --git a/part_2/ex6/ex6_assignment_defaults.qdf b/part_3/ex14/ex10_assignment_defaults.qdf
index 71af25e..7f6e4ac 100644..100755
--- a/part_2/ex6/ex6_assignment_defaults.qdf
+++ b/part_3/ex14/ex10_assignment_defaults.qdf
@@ -1,795 +1,799 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2016  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Intel and sold by Intel or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-# Date created = 17:54:40  December 11, 2016
-#
-# -------------------------------------------------------------------------- #
-#
-# Note:
-#
-# 1) Do not modify this file. This file was generated
-#    automatically by the Quartus Prime software and is used
-#    to preserve global assignments across Quartus Prime versions.
-#
-# -------------------------------------------------------------------------- #
-
-set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
-set_global_assignment -name IP_COMPONENT_INTERNAL Off
-set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
-set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
-set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
-set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
-set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
-set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
-set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
-set_global_assignment -name HC_OUTPUT_DIR hc_output
-set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
-set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
-set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
-set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
-set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
-set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
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-set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
-set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
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-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
-set_global_assignment -name DO_COMBINED_ANALYSIS Off
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-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
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-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
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-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
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-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
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-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
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-set_global_assignment -name OCP_HW_EVAL -value OFF
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-set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
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-set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
-set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
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-set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
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-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
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-set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
-set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_LCELL_BUFFERS Off
-set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
-set_global_assignment -name IGNORE_SOFT_BUFFERS On
-set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
-set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
-set_global_assignment -name AUTO_GLOBAL_OE_MAX On
-set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
-set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
-set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
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-set_global_assignment -name CARRY_CHAIN_LENGTH 48
-set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
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-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
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-set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
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-set_global_assignment -name BLOCK_DESIGN_NAMING Auto
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-set_global_assignment -name ADCE_ENABLED Auto
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
-set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
-set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
-set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
-set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
-set_global_assignment -name ENABLE_NCEO_OUTPUT Off
-set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
-set_global_assignment -name STRATIX_UPDATE_MODE Standard
-set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
-set_global_assignment -name CVP_MODE Off
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
-set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
-set_global_assignment -name USE_CONF_DONE AUTO
-set_global_assignment -name USE_PWRMGT_SCL AUTO
-set_global_assignment -name USE_PWRMGT_SDA AUTO
-set_global_assignment -name USE_PWRMGT_ALERT AUTO
-set_global_assignment -name USE_INIT_DONE AUTO
-set_global_assignment -name USE_CVP_CONFDONE AUTO
-set_global_assignment -name USE_SEU_ERROR AUTO
-set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name USER_START_UP_CLOCK Off
-set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
-set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
-set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
-set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
-set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
-set_global_assignment -name ENABLE_VREFA_PIN Off
-set_global_assignment -name ENABLE_VREFB_PIN Off
-set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
-set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
-set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
-set_global_assignment -name INIT_DONE_OPEN_DRAIN On
-set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name ENABLE_CONFIGURATION_PINS On
-set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
-set_global_assignment -name ENABLE_NCE_PIN Off
-set_global_assignment -name ENABLE_BOOT_SEL_PIN On
-set_global_assignment -name CRC_ERROR_CHECKING Off
-set_global_assignment -name INTERNAL_SCRUBBING Off
-set_global_assignment -name PR_ERROR_OPEN_DRAIN On
-set_global_assignment -name PR_READY_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CVP_CONFDONE Off
-set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
-set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
-set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
-set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
-set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
-set_global_assignment -name OPTIMIZE_SSN Off
-set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
-set_global_assignment -name ECO_OPTIMIZE_TIMING Off
-set_global_assignment -name ECO_REGENERATE_REPORT Off
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
-set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
-set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
-set_global_assignment -name SEED 1
-set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
-set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
-set_global_assignment -name SLOW_SLEW_RATE Off
-set_global_assignment -name PCI_IO Off
-set_global_assignment -name TURBO_BIT On
-set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
-set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
-set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
-set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
-set_global_assignment -name NORMAL_LCELL_INSERT On
-set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
-set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
-set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
-set_global_assignment -name AUTO_TURBO_BIT ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
-set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
-set_global_assignment -name FITTER_EFFORT "Auto Fit"
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
-set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
-set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK On
-set_global_assignment -name AUTO_GLOBAL_OE On
-set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
-set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
-set_global_assignment -name ENABLE_HOLD_BACK_OFF On
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
-set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
-set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
-set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
-set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
-set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
-set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
-set_global_assignment -name PR_DONE_OPEN_DRAIN On
-set_global_assignment -name NCEO_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
-set_global_assignment -name ENABLE_PR_PINS Off
-set_global_assignment -name RESERVE_PR_PINS Off
-set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
-set_global_assignment -name PR_PINS_OPEN_DRAIN Off
-set_global_assignment -name CLAMPING_DIODE Off
-set_global_assignment -name TRI_STATE_SPI_PINS Off
-set_global_assignment -name UNUSED_TSD_PINS_GND Off
-set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
-set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
-set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
-set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
-set_global_assignment -name SEU_FIT_REPORT Off
-set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
-set_global_assignment -name COMPRESSION_MODE Off
-set_global_assignment -name CLOCK_SOURCE Internal
-set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
-set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
-set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
-set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
-set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
-set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
-set_global_assignment -name SECURITY_BIT Off
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
-set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:58:36  November 29, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
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+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Stratix 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY -value "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x1" -family "Stratix 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS Off -family "Stratix 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Stratix 10"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Stratix 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off
+set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS OFF -family "Stratix 10"
+set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS ON -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000001
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000010
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000100
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0001000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0010000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/part_3/ex14/ex10_nativelink_simulation.rpt b/part_3/ex14/ex10_nativelink_simulation.rpt
new file mode 100755
index 0000000..91c988e
--- /dev/null
+++ b/part_3/ex14/ex10_nativelink_simulation.rpt
@@ -0,0 +1,22 @@
+Info: Start Nativelink Simulation process
+Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
+
+========= EDA Simulation Settings =====================
+
+Sim Mode              :  RTL
+Family                :  cyclonev
+Quartus root          :  c:/altera/16.0/quartus/bin64/
+Quartus sim root      :  c:/altera/16.0/quartus/eda/sim_lib
+Simulation Tool       :  modelsim-altera
+Simulation Language   :  verilog
+Simulation Mode       :  GUI
+Sim Output File       :  
+Sim SDF file          :  
+Sim dir               :  simulation\modelsim
+
+=======================================================
+
+Info: Starting NativeLink simulation with ModelSim-Altera software
+Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
+Warning: File ex10_run_msim_rtl_verilog.do already exists - backing up current file as ex10_run_msim_rtl_verilog.do.bak
+Info: Spawning ModelSim-Altera Simulation software 
diff --git a/part_3/ex14/ex14.v b/part_3/ex14/ex14.v
new file mode 100755
index 0000000..32c01d2
--- /dev/null
+++ b/part_3/ex14/ex14.v
@@ -0,0 +1,33 @@
+module ex14(CLOCK_50, SW, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT, HEX0, HEX1, HEX2, HEX3, HEX4);
+
+	input CLOCK_50;
+	input [9:0] SW;
+	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT;
+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
+	
+	wire load;
+	wire [9:0] data;
+	wire [9:0] address;
+	wire [23:0] freq_tmp;
+	wire [19:0] freq_fin;
+	
+	tick_5000 tick(CLOCK_50, load);
+	
+	add_offset fin_address(SW, load, address);
+	
+	ROM rom(address, CLOCK_50, data);
+	
+	spi2dac dac(CLOCK_50, data, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
+	pwm p(CLOCK_50, data, load, PWM_OUT);
+	
+	const_mult mult(SW, freq_tmp);
+	
+	bin2bcd_16 bcd(freq_tmp[23:10], freq_fin[3:0], freq_fin[7:4], freq_fin[11:8], freq_fin[15:12], freq_fin[19:16]);
+	
+	hex_to_7seg h0(HEX0, freq_fin[3:0]);	
+	hex_to_7seg h1(HEX1, freq_fin[7:4]);
+	hex_to_7seg h2(HEX2, freq_fin[11:8]);
+	hex_to_7seg h3(HEX3, freq_fin[15:12]);
+	hex_to_7seg h4(HEX4, freq_fin[19:16]);
+	
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex14/ex14.v.bak b/part_3/ex14/ex14.v.bak
new file mode 100755
index 0000000..eaec90d
--- /dev/null
+++ b/part_3/ex14/ex14.v.bak
@@ -0,0 +1,18 @@
+module ex13(CLOCK_50, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT);
+
+	input CLOCK_50;
+	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT;
+	
+	wire load;
+	wire [9:0] data, count;
+	
+	tick_5000 t(CLOCK_50, load);
+	
+	counter_10 c(CLOCK_50, load, count);
+	
+	ROM r(count, CLOCK_50, data);
+	
+	spi2dac s(CLOCK_50, data, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
+	pwm p(CLOCK_50, data, load, PWM_OUT);
+	
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex14/greybox_tmp/cbx_args.txt b/part_3/ex14/greybox_tmp/cbx_args.txt
new file mode 100755
index 0000000..0525819
--- /dev/null
+++ b/part_3/ex14/greybox_tmp/cbx_args.txt
@@ -0,0 +1,10 @@
+LPM_HINT=INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5
+LPM_REPRESENTATION=UNSIGNED
+LPM_TYPE=LPM_MULT
+LPM_WIDTHA=10
+LPM_WIDTHB=14
+LPM_WIDTHP=24
+DEVICE_FAMILY="Cyclone V"
+dataa
+datab
+result
diff --git a/part_3/ex14/greybox_tmp/greybox_tmp/mg1tj.v b/part_3/ex14/greybox_tmp/greybox_tmp/mg1tj.v
new file mode 100755
index 0000000..c7690aa
--- /dev/null
+++ b/part_3/ex14/greybox_tmp/greybox_tmp/mg1tj.v
@@ -0,0 +1,56 @@
+//lpm_mult CBX_SINGLE_OUTPUT_FILE="ON" LPM_HINT="INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5" LPM_REPRESENTATION="UNSIGNED" LPM_TYPE="LPM_MULT" LPM_WIDTHA=10 LPM_WIDTHB=14 LPM_WIDTHP=24 LPM_WIDTHS=1 dataa datab result
+//VERSION_BEGIN 16.1 cbx_mgl 2016:10:24:15:05:03:SJ cbx_stratixii 2016:10:24:15:04:16:SJ cbx_util_mgl 2016:10:24:15:04:16:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2016  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel MegaCore Function License Agreement, or other 
+//  applicable license agreement, including, without limitation, 
+//  that your use is for the sole purpose of programming logic 
+//  devices manufactured by Intel and sold by Intel or its 
+//  authorized distributors.  Please refer to the applicable 
+//  agreement for further details.
+
+
+
+//synthesis_resources = lpm_mult 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  mg1tj
+	( 
+	dataa,
+	datab,
+	result) /* synthesis synthesis_clearbox=1 */;
+	input   [9:0]  dataa;
+	input   [13:0]  datab;
+	output   [23:0]  result;
+
+	wire  [23:0]   wire_mgl_prim1_result;
+
+	lpm_mult   mgl_prim1
+	( 
+	.dataa(dataa),
+	.datab(datab),
+	.result(wire_mgl_prim1_result));
+	defparam
+		mgl_prim1.lpm_representation = "UNSIGNED",
+		mgl_prim1.lpm_type = "LPM_MULT",
+		mgl_prim1.lpm_widtha = 10,
+		mgl_prim1.lpm_widthb = 14,
+		mgl_prim1.lpm_widthp = 24,
+		mgl_prim1.lpm_widths = 1,
+		mgl_prim1.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
+	assign
+		result = wire_mgl_prim1_result;
+endmodule //mg1tj
+//VALID FILE
diff --git a/part_2/ex9_final/incremental_db/README b/part_3/ex14/incremental_db/README
index 6191fbe..6191fbe 100755
--- a/part_2/ex9_final/incremental_db/README
+++ b/part_3/ex14/incremental_db/README
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.db_info b/part_3/ex14/incremental_db/compiled_partitions/ex10.db_info
index f84b742..0ede8e0 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.db_info
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.db_info
@@ -1,3 +1,3 @@
 Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 Version_Index = 402707200
-Creation_Time = Fri Nov 25 10:41:49 2016
+Creation_Time = Fri Dec 02 17:08:24 2016
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.ammdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.ammdb
new file mode 100755
index 0000000..2edccae
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.ammdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.cdb
new file mode 100755
index 0000000..eb37a0d
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.dfp
index b1c67d6..b1c67d6 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.dfp
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..e073a4b
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.hdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..57c3597
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.sig
index af9b8e9..af9b8e9 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.sig
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hdb
new file mode 100755
index 0000000..3d7d976
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.logdb
index d45424f..d45424f 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.logdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.rcfdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..3e1a968
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.cmp.rcfdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.cdb
new file mode 100755
index 0000000..4c2dd14
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.dpi b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.dpi
new file mode 100755
index 0000000..6324099
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.dpi
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..4ed1db4
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.cdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hb_info
index 8210c55..8210c55 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hb_info
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..f7839fa
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hdb
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.sig
index af9b8e9..af9b8e9 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.sig
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hdb
new file mode 100755
index 0000000..7434435
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.hdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.kpt b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.kpt
new file mode 100755
index 0000000..adf3d4c
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.kpt
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.olf.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.olf.cdb
new file mode 100755
index 0000000..65a0978
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.olf.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.olm.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.olm.cdb
new file mode 100755
index 0000000..5bbe4fc
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.olm.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.oln.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.oln.cdb
new file mode 100755
index 0000000..67f8d00
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.oln.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.opi b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.opi
@@ -0,0 +1 @@
+1
+\ No newline at end of file
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orf.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orf.cdb
new file mode 100755
index 0000000..b577dca
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orf.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orm.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orm.cdb
new file mode 100755
index 0000000..112519f
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orm.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orn.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orn.cdb
new file mode 100755
index 0000000..f602f5e
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.map.orn.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.cdb
new file mode 100755
index 0000000..4c2dd14
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..4ed1db4
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.cdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.hdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..f7839fa
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.hdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hdb
new file mode 100755
index 0000000..7434435
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.hdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.kpt b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.kpt
new file mode 100755
index 0000000..adf3d4c
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.root_partition.rrp.kpt
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.rrp.hdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.rrp.hdb
new file mode 100755
index 0000000..34f3597
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.rrp.hdb
diff --git a/part_3/ex14/incremental_db/compiled_partitions/ex10.rrs.cdb b/part_3/ex14/incremental_db/compiled_partitions/ex10.rrs.cdb
new file mode 100755
index 0000000..ab186a9
--- /dev/null
+++ b/part_3/ex14/incremental_db/compiled_partitions/ex10.rrs.cdb
diff --git a/part_3/ex14/output_files/ex10.asm.rpt b/part_3/ex14/output_files/ex10.asm.rpt
new file mode 100755
index 0000000..4962545
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex10
+Fri Dec 02 17:38:53 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: /Desktop/ex14/output_files/ex10.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Dec 02 17:38:53 2016 ;
+; Revision Name         ; ex10                                  ;
+; Top-level Entity Name ; ex14                                  ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-------------------------------------+
+; Assembler Generated Files           ;
++-------------------------------------+
+; File Name                           ;
++-------------------------------------+
+; /Desktop/ex14/output_files/ex10.sof ;
++-------------------------------------+
+
+
++---------------------------------------------------------------+
+; Assembler Device Options: /Desktop/ex14/output_files/ex10.sof ;
++----------------+----------------------------------------------+
+; Option         ; Setting                                      ;
++----------------+----------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                 ;
+; JTAG usercode  ; 0x00B68C02                                   ;
+; Checksum       ; 0x00B68C02                                   ;
++----------------+----------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 17:38:44 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 902 megabytes
+    Info: Processing ended: Fri Dec 02 17:38:53 2016
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:07
+
+
diff --git a/part_3/ex14/output_files/ex10.done b/part_3/ex14/output_files/ex10.done
new file mode 100755
index 0000000..dba06d9
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.done
@@ -0,0 +1 @@
+Fri Dec 02 17:39:10 2016
diff --git a/part_3/ex14/output_files/ex10.eda.rpt b/part_3/ex14/output_files/ex10.eda.rpt
new file mode 100755
index 0000000..c064b97
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.eda.rpt
@@ -0,0 +1,96 @@
+EDA Netlist Writer report for ex10
+Fri Dec 02 17:39:09 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Dec 02 17:39:09 2016 ;
+; Revision Name             ; ex10                                  ;
+; Top-level Entity Name     ; ex14                                  ;
+; Family                    ; Cyclone V                             ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                           ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option                                                                                            ; Setting                   ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
+; Generate functional simulation netlist                                                            ; Off                       ;
+; Time scale                                                                                        ; 1 ps                      ;
+; Truncate long hierarchy paths                                                                     ; Off                       ;
+; Map illegal HDL characters                                                                        ; Off                       ;
+; Flatten buses into individual nodes                                                               ; Off                       ;
+; Maintain hierarchy                                                                                ; Off                       ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
+; Enable glitch filtering                                                                           ; Off                       ;
+; Do not write top level VHDL entity                                                                ; Off                       ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
+; Architecture name in VHDL output netlist                                                          ; structure                 ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++-------------------------------------------+
+; Simulation Generated Files                ;
++-------------------------------------------+
+; Generated Files                           ;
++-------------------------------------------+
+; /Desktop/ex14/simulation/modelsim/ex10.vo ;
++-------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 17:39:07 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
+Info (204019): Generated file ex10.vo in folder "/Desktop/ex14/simulation/modelsim/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
+    Info: Peak virtual memory: 816 megabytes
+    Info: Processing ended: Fri Dec 02 17:39:09 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/part_3/ex14/output_files/ex10.fit.rpt b/part_3/ex14/output_files/ex10.fit.rpt
new file mode 100755
index 0000000..e023b2a
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.fit.rpt
@@ -0,0 +1,2213 @@
+Fitter report for ex10
+Fri Dec 02 17:38:37 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Fitter RAM Summary
+ 24. Routing Usage Summary
+ 25. I/O Rules Summary
+ 26. I/O Rules Details
+ 27. I/O Rules Matrix
+ 28. Fitter Device Options
+ 29. Operating Settings and Conditions
+ 30. Estimated Delay Added for Hold Timing Summary
+ 31. Estimated Delay Added for Hold Timing Details
+ 32. Fitter Messages
+ 33. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Fri Dec 02 17:38:37 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex10                                            ;
+; Top-level Entity Name           ; ex14                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 136 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 84                                              ;
+; Total pins                      ; 51 / 457 ( 11 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 10,240 / 4,065,280 ( < 1 % )                    ;
+; Total RAM Blocks                ; 1 / 397 ( < 1 % )                               ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.02        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   0.7%      ;
+;     Processor 3            ;   0.7%      ;
+;     Processor 4            ;   0.6%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; DAC_CS   ; Missing drive strength and slew rate ;
+; DAC_SDI  ; Missing drive strength and slew rate ;
+; DAC_LD   ; Missing drive strength and slew rate ;
+; DAC_SCK  ; Missing drive strength and slew rate ;
+; PWM_OUT  ; Missing drive strength and slew rate ;
+; HEX0[0]  ; Missing drive strength and slew rate ;
+; HEX0[1]  ; Missing drive strength and slew rate ;
+; HEX0[2]  ; Missing drive strength and slew rate ;
+; HEX0[3]  ; Missing drive strength and slew rate ;
+; HEX0[4]  ; Missing drive strength and slew rate ;
+; HEX0[5]  ; Missing drive strength and slew rate ;
+; HEX0[6]  ; Missing drive strength and slew rate ;
+; HEX1[0]  ; Missing drive strength and slew rate ;
+; HEX1[1]  ; Missing drive strength and slew rate ;
+; HEX1[2]  ; Missing drive strength and slew rate ;
+; HEX1[3]  ; Missing drive strength and slew rate ;
+; HEX1[4]  ; Missing drive strength and slew rate ;
+; HEX1[5]  ; Missing drive strength and slew rate ;
+; HEX1[6]  ; Missing drive strength and slew rate ;
+; HEX2[0]  ; Missing drive strength and slew rate ;
+; HEX2[1]  ; Missing drive strength and slew rate ;
+; HEX2[2]  ; Missing drive strength and slew rate ;
+; HEX2[3]  ; Missing drive strength and slew rate ;
+; HEX2[4]  ; Missing drive strength and slew rate ;
+; HEX2[5]  ; Missing drive strength and slew rate ;
+; HEX2[6]  ; Missing drive strength and slew rate ;
+; HEX3[0]  ; Missing drive strength and slew rate ;
+; HEX3[1]  ; Missing drive strength and slew rate ;
+; HEX3[2]  ; Missing drive strength and slew rate ;
+; HEX3[3]  ; Missing drive strength and slew rate ;
+; HEX3[4]  ; Missing drive strength and slew rate ;
+; HEX3[5]  ; Missing drive strength and slew rate ;
+; HEX3[6]  ; Missing drive strength and slew rate ;
+; HEX4[0]  ; Missing drive strength and slew rate ;
+; HEX4[1]  ; Missing drive strength and slew rate ;
+; HEX4[2]  ; Missing drive strength and slew rate ;
+; HEX4[3]  ; Missing drive strength and slew rate ;
+; HEX4[4]  ; Missing drive strength and slew rate ;
+; HEX4[5]  ; Missing drive strength and slew rate ;
+; HEX4[6]  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                        ;
++--------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------+------------------+-----------------------+
+; Node                     ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                   ; Destination Port ; Destination Port Name ;
++--------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0    ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                    ;                  ;                       ;
+; pwm:p|count[0]           ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; pwm:p|count[0]~DUPLICATE           ;                  ;                       ;
+; spi2dac:dac|ctr[0]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:dac|ctr[0]~DUPLICATE       ;                  ;                       ;
+; spi2dac:dac|ctr[2]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:dac|ctr[2]~DUPLICATE       ;                  ;                       ;
+; spi2dac:dac|ctr[3]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:dac|ctr[3]~DUPLICATE       ;                  ;                       ;
+; spi2dac:dac|state[3]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:dac|state[3]~DUPLICATE     ;                  ;                       ;
+; tick_5000:tick|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[5]~DUPLICATE  ;                  ;                       ;
+; tick_5000:tick|count[7]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[7]~DUPLICATE  ;                  ;                       ;
+; tick_5000:tick|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[15]~DUPLICATE ;                  ;                       ;
++--------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                        ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
+; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[0]     ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]     ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; KEY[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; KEY[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex14           ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 430 ) ; 0.00 % ( 0 / 430 )         ; 0.00 % ( 0 / 430 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 430 ) ; 0.00 % ( 0 / 430 )         ; 0.00 % ( 0 / 430 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 430 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /Desktop/ex14/output_files/ex10.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 136 / 32,070       ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 136                ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 147 / 32,070       ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 23                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 109                ;       ;
+;         [c] ALMs used for registers                         ; 15                 ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 11 / 32,070        ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 21 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 21                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 241                ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 20                 ;       ;
+;     -- 5 input functions                                    ; 23                 ;       ;
+;     -- 4 input functions                                    ; 120                ;       ;
+;     -- <=3 input functions                                  ; 78                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 21                 ;       ;
+; Dedicated logic registers                                   ; 84                 ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 75 / 64,140        ; < 1 % ;
+;         -- Secondary logic registers                        ; 9 / 64,140         ; < 1 % ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 76                 ;       ;
+;         -- Routing optimization registers                   ; 8                  ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 51 / 457           ; 11 %  ;
+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 1 / 397            ; < 1 % ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 10,240 / 4,065,280 ; < 1 % ;
+; Total block memory implementation bits                      ; 10,240 / 4,065,280 ; < 1 % ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.2% / 0.2% / 0.1% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 3.1% / 3.6% / 1.8% ;       ;
+; Maximum fan-out                                             ; 53                 ;       ;
+; Highest non-global fan-out                                  ; 22                 ;       ;
+; Total fan-out                                               ; 1233               ;       ;
+; Average fan-out                                             ; 2.74               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                          ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 136 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 136                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 147 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 23                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 109                   ; 0                              ;
+;         [c] ALMs used for registers                         ; 15                    ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 11 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Difficulty packing design                                   ; Low                   ; Low                            ;
+;                                                             ;                       ;                                ;
+; Total LABs:  partially or completely used                   ; 21 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 21                    ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Combinational ALUT usage for logic                          ; 241                   ; 0                              ;
+;     -- 7 input functions                                    ; 0                     ; 0                              ;
+;     -- 6 input functions                                    ; 20                    ; 0                              ;
+;     -- 5 input functions                                    ; 23                    ; 0                              ;
+;     -- 4 input functions                                    ; 120                   ; 0                              ;
+;     -- <=3 input functions                                  ; 78                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 21                    ; 0                              ;
+; Memory ALUT usage                                           ; 0                     ; 0                              ;
+;     -- 64-address deep                                      ; 0                     ; 0                              ;
+;     -- 32-address deep                                      ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Dedicated logic registers                                   ; 0                     ; 0                              ;
+;     -- By type:                                             ;                       ;                                ;
+;         -- Primary logic registers                          ; 75 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 9 / 64140 ( < 1 % )   ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                       ;                                ;
+;         -- Design implementation registers                  ; 76                    ; 0                              ;
+;         -- Routing optimization registers                   ; 8                     ; 0                              ;
+;                                                             ;                       ;                                ;
+;                                                             ;                       ;                                ;
+; Virtual pins                                                ; 0                     ; 0                              ;
+; I/O pins                                                    ; 51                    ; 0                              ;
+; I/O registers                                               ; 0                     ; 0                              ;
+; Total block memory bits                                     ; 10240                 ; 0                              ;
+; Total block memory implementation bits                      ; 10240                 ; 0                              ;
+; M10K block                                                  ; 1 / 397 ( < 1 % )     ; 0 / 397 ( 0 % )                ;
+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
+;                                                             ;                       ;                                ;
+; Connections                                                 ;                       ;                                ;
+;     -- Input Connections                                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections                         ; 0                     ; 0                              ;
+;     -- Output Connections                                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections                        ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Internal Connections                                        ;                       ;                                ;
+;     -- Total Connections                                    ; 1233                  ; 0                              ;
+;     -- Registered Connections                               ; 254                   ; 0                              ;
+;                                                             ;                       ;                                ;
+; External Connections                                        ;                       ;                                ;
+;     -- Top                                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Partition Interface                                         ;                       ;                                ;
+;     -- Input Ports                                          ; 11                    ; 0                              ;
+;     -- Output Ports                                         ; 40                    ; 0                              ;
+;     -- Bidir Ports                                          ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Registered Ports                                            ;                       ;                                ;
+;     -- Registered Input Ports                               ; 0                     ; 0                              ;
+;     -- Registered Output Ports                              ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Port Connectivity                                           ;                       ;                                ;
+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 55                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[0]    ; AB12  ; 3A       ; 12           ; 0            ; 17           ; 10                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[1]    ; AC12  ; 3A       ; 16           ; 0            ; 0            ; 11                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[2]    ; AF9   ; 3A       ; 8            ; 0            ; 34           ; 10                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[3]    ; AF10  ; 3A       ; 4            ; 0            ; 51           ; 9                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[4]    ; AD11  ; 3A       ; 2            ; 0            ; 40           ; 11                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[5]    ; AD12  ; 3A       ; 16           ; 0            ; 17           ; 11                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[6]    ; AE11  ; 3A       ; 4            ; 0            ; 34           ; 10                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[7]    ; AC9   ; 3A       ; 4            ; 0            ; 0            ; 9                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[8]    ; AD10  ; 3A       ; 4            ; 0            ; 17           ; 8                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[9]    ; AE12  ; 3A       ; 2            ; 0            ; 57           ; 7                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DAC_CS  ; AD20  ; 4A       ; 82           ; 0            ; 40           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_LD  ; AK21  ; 4A       ; 68           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SCK ; AF20  ; 4A       ; 70           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SDI ; AG18  ; 4A       ; 58           ; 0            ; 74           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; PWM_OUT ; AJ20  ; 4A       ; 62           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 10 / 32 ( 31 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 3B       ; 1 / 48 ( 2 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 5 / 80 ( 6 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 27 / 32 ( 84 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 8 / 16 ( 50 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; SW[0]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; SW[7]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; SW[1]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; SW[8]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD11     ; 54         ; 3A             ; SW[4]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD12     ; 80         ; 3A             ; SW[5]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; DAC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; SW[6]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE12     ; 52         ; 3A             ; SW[9]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; SW[2]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF10     ; 57         ; 3A             ; SW[3]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; DAC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; DAC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; PWM_OUT                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; DAC_LD                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++---------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                        ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                       ; Entity Name     ; Library Name ;
++---------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex14                                             ; 135.5 (0.5)          ; 146.5 (0.5)                      ; 11.0 (0.0)                                        ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 241 (1)             ; 84 (0)                    ; 0 (0)         ; 10240             ; 1     ; 0          ; 51   ; 0            ; |ex14                                                                                                                                                     ; ex14            ; work         ;
+;    |ROM:rom|                                      ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex14|ROM:rom                                                                                                                                             ; ROM             ; work         ;
+;       |altsyncram:altsyncram_component|           ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex14|ROM:rom|altsyncram:altsyncram_component                                                                                                             ; altsyncram      ; work         ;
+;          |altsyncram_6ng1:auto_generated|         ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex14|ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated                                                                              ; altsyncram_6ng1 ; work         ;
+;    |add_offset:fin_address|                       ; 5.0 (5.0)            ; 10.0 (10.0)                      ; 5.0 (5.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 10 (10)             ; 10 (10)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|add_offset:fin_address                                                                                                                              ; add_offset      ; work         ;
+;    |bin2bcd_16:bcd|                               ; 53.5 (0.0)           ; 54.0 (0.0)                       ; 0.5 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 97 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd                                                                                                                                      ; bin2bcd_16      ; work         ;
+;       |add3_ge5:A1|                               ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A1                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A10|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A10                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A11|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A11                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A12|                              ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A12                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A13|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A13                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A14|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A14                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A15|                              ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A15                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A16|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A16                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A17|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A17                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A19|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A19                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A2|                               ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A2                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A20|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A20                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A21|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A21                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A22|                              ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A22                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A23|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A23                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A24|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A24                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A25|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A25                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A26|                              ; 5.5 (5.5)            ; 6.0 (6.0)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 9 (9)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A26                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A27|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A27                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A28|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A28                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A29|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A29                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A4|                               ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A4                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A5|                               ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A5                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A6|                               ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A6                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A7|                               ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A7                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A8|                               ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A8                                                                                                                          ; add3_ge5        ; work         ;
+;    |const_mult:mult|                              ; 18.0 (0.0)           ; 18.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult                                                                                                                                     ; const_mult      ; work         ;
+;       |lpm_mult:lpm_mult_component|               ; 18.0 (0.0)           ; 18.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component                                                                                                         ; lpm_mult        ; work         ;
+;          |multcore:mult_core|                     ; 18.0 (3.0)           ; 18.0 (3.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (6)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core                                                                                      ; multcore        ; work         ;
+;             |mpar_add:padder|                     ; 15.0 (0.0)           ; 15.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 30 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder                                                                      ; mpar_add        ; work         ;
+;                |lpm_add_sub:adder[0]|             ; 9.0 (0.0)            ; 9.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; lpm_add_sub     ; work         ;
+;                   |add_sub_d9h:auto_generated|    ; 9.0 (9.0)            ; 9.0 (9.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (18)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated                      ; add_sub_d9h     ; work         ;
+;                |mpar_add:sub_par_add|             ; 6.0 (0.0)            ; 6.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 12 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; mpar_add        ; work         ;
+;                   |lpm_add_sub:adder[0]|          ; 6.0 (0.0)            ; 6.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 12 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; lpm_add_sub     ; work         ;
+;                      |add_sub_89h:auto_generated| ; 6.0 (6.0)            ; 6.0 (6.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 12 (12)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated ; add_sub_89h     ; work         ;
+;    |hex_to_7seg:h0|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h0                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h1|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h1                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h2|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h2                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h3|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h3                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h4|                               ; 2.5 (2.5)            ; 3.0 (3.0)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h4                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |pwm:p|                                        ; 9.8 (9.8)            ; 10.7 (10.7)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (16)             ; 22 (22)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|pwm:p                                                                                                                                               ; pwm             ; work         ;
+;    |spi2dac:dac|                                  ; 18.7 (18.7)          ; 19.8 (19.8)                      ; 1.2 (1.2)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 23 (23)             ; 32 (32)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|spi2dac:dac                                                                                                                                         ; spi2dac         ; work         ;
+;    |tick_5000:tick|                               ; 13.5 (13.5)          ; 16.5 (16.5)                      ; 3.0 (3.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 27 (27)             ; 20 (20)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex14|tick_5000:tick                                                                                                                                      ; tick_5000       ; work         ;
++---------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; DAC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_LD   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; PWM_OUT  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[2]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[1]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[0]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[6]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[3]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[7]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[8]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[9]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[5]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[4]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                                                                                                                   ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                                                                                                                ; Pad To Core Index ; Setting ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; CLOCK_50                                                                                                                                                           ;                   ;         ;
+;      - spi2dac:dac|clk_1MHz                                                                                                                                        ; 0                 ; 0       ;
+;      - tick_5000:tick|CLK_OUT                                                                                                                                      ; 0                 ; 0       ;
+; SW[2]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~62                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~1                       ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~5                       ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~13                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~17                      ; 0                 ; 0       ;
+;      - add_offset:fin_address|Add0~9                                                                                                                               ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~1                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][15]~2                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][16]~3                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][17]~4                                                                              ; 0                 ; 0       ;
+; SW[1]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~66                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~10                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~1                       ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~5                       ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~13                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~17                      ; 0                 ; 0       ;
+;      - add_offset:fin_address|Add0~5                                                                                                                               ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~1                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][15]~2                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][16]~3                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][17]~4                                                                              ; 0                 ; 0       ;
+; SW[0]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~54                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~10                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~1                       ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~5                       ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~13                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~17                      ; 0                 ; 0       ;
+;      - add_offset:fin_address|Add0~1                                                                                                                               ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~1                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][15]~2                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][16]~3                                                                              ; 0                 ; 0       ;
+; SW[6]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~1                       ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~21                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~25                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~29                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~33                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~37                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~41                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~45                      ; 1                 ; 0       ;
+;      - add_offset:fin_address|Add0~25                                                                                                                              ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][17]~5                                                                              ; 1                 ; 0       ;
+; SW[3]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~58                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~5                       ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~13                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~17                      ; 1                 ; 0       ;
+;      - add_offset:fin_address|Add0~13                                                                                                                              ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~1                                                                              ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][15]~2                                                                              ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][16]~3                                                                              ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][17]~4                                                                              ; 1                 ; 0       ;
+; SW[7]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~5                       ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~25                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~29                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~33                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~37                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~41                      ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~45                      ; 0                 ; 0       ;
+;      - add_offset:fin_address|Add0~29                                                                                                                              ; 0                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][17]~5                                                                              ; 0                 ; 0       ;
+; SW[8]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~1  ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~17 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~21 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~25 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~29 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~33 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~37 ; 1                 ; 0       ;
+;      - add_offset:fin_address|Add0~33                                                                                                                              ; 1                 ; 0       ;
+; SW[9]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~5  ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~21 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~25 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~29 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~33 ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated|op_1~41 ; 1                 ; 0       ;
+;      - add_offset:fin_address|Add0~37                                                                                                                              ; 1                 ; 0       ;
+; SW[5]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~10                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~21                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~25                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~29                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~33                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~37                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~41                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~45                      ; 1                 ; 0       ;
+;      - add_offset:fin_address|Add0~21                                                                                                                              ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~0                                                                               ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][17]~5                                                                              ; 1                 ; 0       ;
+; SW[4]                                                                                                                                                              ;                   ;         ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~54                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~13                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~21                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~25                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~29                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~33                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~37                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~41                      ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated|op_1~45                      ; 1                 ; 0       ;
+;      - add_offset:fin_address|Add0~17                                                                                                                              ; 1                 ; 0       ;
+;      - const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~0                                                                               ; 1                 ; 0       ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                             ;
++-------------------------+--------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
+; Name                    ; Location           ; Fan-Out ; Usage               ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------+--------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                ; PIN_AF14           ; 3       ; Clock               ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                ; PIN_AF14           ; 53      ; Clock               ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; spi2dac:dac|always5~0   ; LABCELL_X62_Y2_N39 ; 9       ; Sync. load          ; no     ; --                   ; --               ; --                        ;
+; spi2dac:dac|clk_1MHz    ; FF_X63_Y2_N23      ; 22      ; Clock               ; no     ; --                   ; --               ; --                        ;
+; tick_5000:tick|CLK_OUT  ; FF_X60_Y2_N23      ; 22      ; Clock, Clock enable ; no     ; --                   ; --               ; --                        ;
+; tick_5000:tick|Equal0~3 ; LABCELL_X60_Y2_N30 ; 12      ; Sync. clear         ; no     ; --                   ; --               ; --                        ;
++-------------------------+--------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 53      ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; Name                                                                              ; Type ; Mode ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF                     ; Location       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs         ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; Single Clock ; 1024         ; 10           ; --           ; --           ; yes                    ; yes                     ; --                     ; --                      ; 10240 ; 1024                        ; 10                          ; --                          ; --                          ; 10240               ; 1           ; 0          ; ./rom_data/rom_data.mif ; M10K_X58_Y2_N0 ; Don't care           ; New data        ; New data        ; Off      ; No                     ; No - Address Too Wide ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 313 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 24 / 13,420 ( < 1 % )   ;
+; C2 interconnects                            ; 98 / 119,108 ( < 1 % )  ;
+; C4 interconnects                            ; 108 / 56,300 ( < 1 % )  ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 69 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 1 / 16 ( 6 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 108 / 84,580 ( < 1 % )  ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 132 / 12,676 ( 1 % )    ;
+; R14/C12 interconnect drivers                ; 145 / 20,720 ( < 1 % )  ;
+; R3 interconnects                            ; 169 / 130,992 ( < 1 % ) ;
+; R6 interconnects                            ; 288 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                  ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 51        ; 0            ; 51        ; 0            ; 0            ; 51        ; 51        ; 0            ; 51        ; 51        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 51           ; 0         ; 51           ; 51           ; 0         ; 0         ; 51           ; 0         ; 0         ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ; 51           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; DAC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_LD             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; PWM_OUT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++--------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                  ;
++------------------------+-----------------------------------+-------------------+
+; Source Clock(s)        ; Destination Clock(s)              ; Delay Added in ns ;
++------------------------+-----------------------------------+-------------------+
+; CLOCK_50               ; CLOCK_50                          ; 44.3              ;
+; tick_5000:tick|CLK_OUT ; CLOCK_50                          ; 35.9              ;
+; spi2dac:dac|clk_1MHz   ; CLOCK_50                          ; 24.6              ;
+; spi2dac:dac|clk_1MHz   ; spi2dac:dac|clk_1MHz              ; 14.3              ;
+; spi2dac:dac|clk_1MHz   ; CLOCK_50,spi2dac:dac|clk_1MHz,I/O ; 8.4               ;
++------------------------+-----------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                   ;
++------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                    ; Destination Register                                                                                   ; Delay Added in ns ;
++------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------+
+; spi2dac:dac|clk_1MHz               ; spi2dac:dac|clk_1MHz                                                                                   ; 5.831             ;
+; tick_5000:tick|CLK_OUT             ; spi2dac:dac|sr_state.WAIT_CSB_FALL                                                                     ; 4.708             ;
+; spi2dac:dac|state[3]               ; spi2dac:dac|sr_state.WAIT_CSB_HIGH                                                                     ; 4.104             ;
+; spi2dac:dac|state[0]               ; spi2dac:dac|sr_state.IDLE                                                                              ; 4.008             ;
+; spi2dac:dac|state[2]               ; spi2dac:dac|sr_state.WAIT_CSB_HIGH                                                                     ; 4.006             ;
+; spi2dac:dac|state[1]               ; spi2dac:dac|sr_state.WAIT_CSB_HIGH                                                                     ; 4.004             ;
+; spi2dac:dac|state[4]               ; spi2dac:dac|sr_state.IDLE                                                                              ; 3.993             ;
+; add_offset:fin_address|address[8]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[7]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[6]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[5]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[4]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[3]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[2]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[1]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[0]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; add_offset:fin_address|address[9]  ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.595             ;
+; spi2dac:dac|ctr[4]                 ; spi2dac:dac|clk_1MHz                                                                                   ; 2.669             ;
+; spi2dac:dac|ctr[3]                 ; spi2dac:dac|clk_1MHz                                                                                   ; 2.669             ;
+; spi2dac:dac|ctr[2]                 ; spi2dac:dac|clk_1MHz                                                                                   ; 2.669             ;
+; spi2dac:dac|ctr[0]                 ; spi2dac:dac|clk_1MHz                                                                                   ; 2.669             ;
+; spi2dac:dac|ctr[1]                 ; spi2dac:dac|clk_1MHz                                                                                   ; 2.669             ;
+; tick_5000:tick|count[7]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.509             ;
+; tick_5000:tick|count[0]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.495             ;
+; tick_5000:tick|count[12]           ; tick_5000:tick|CLK_OUT                                                                                 ; 1.489             ;
+; tick_5000:tick|count[1]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.447             ;
+; tick_5000:tick|count[4]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.440             ;
+; tick_5000:tick|count[2]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.432             ;
+; tick_5000:tick|count[9]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.426             ;
+; tick_5000:tick|count[8]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.401             ;
+; tick_5000:tick|count[6]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.378             ;
+; tick_5000:tick|count[3]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.363             ;
+; tick_5000:tick|count[5]            ; tick_5000:tick|CLK_OUT                                                                                 ; 1.353             ;
+; tick_5000:tick|count[15]           ; tick_5000:tick|CLK_OUT                                                                                 ; 1.329             ;
+; tick_5000:tick|count[10]           ; tick_5000:tick|CLK_OUT                                                                                 ; 1.239             ;
+; tick_5000:tick|count[13]           ; tick_5000:tick|CLK_OUT                                                                                 ; 1.225             ;
+; tick_5000:tick|count[11]           ; tick_5000:tick|CLK_OUT                                                                                 ; 1.217             ;
+; tick_5000:tick|count[14]           ; tick_5000:tick|CLK_OUT                                                                                 ; 1.214             ;
+; spi2dac:dac|shift_reg[14]          ; spi2dac:dac|shift_reg[15]                                                                              ; 0.996             ;
+; spi2dac:dac|shift_reg[13]          ; spi2dac:dac|shift_reg[14]                                                                              ; 0.981             ;
+; spi2dac:dac|shift_reg[11]          ; spi2dac:dac|shift_reg[12]                                                                              ; 0.912             ;
+; spi2dac:dac|shift_reg[12]          ; spi2dac:dac|shift_reg[13]                                                                              ; 0.870             ;
+; spi2dac:dac|shift_reg[3]           ; spi2dac:dac|shift_reg[4]                                                                               ; 0.571             ;
+; spi2dac:dac|shift_reg[5]           ; spi2dac:dac|shift_reg[6]                                                                               ; 0.571             ;
+; spi2dac:dac|shift_reg[7]           ; spi2dac:dac|shift_reg[8]                                                                               ; 0.571             ;
+; spi2dac:dac|shift_reg[9]           ; spi2dac:dac|shift_reg[10]                                                                              ; 0.571             ;
+; spi2dac:dac|shift_reg[4]           ; spi2dac:dac|shift_reg[5]                                                                               ; 0.566             ;
+; spi2dac:dac|shift_reg[6]           ; spi2dac:dac|shift_reg[7]                                                                               ; 0.566             ;
+; spi2dac:dac|shift_reg[8]           ; spi2dac:dac|shift_reg[9]                                                                               ; 0.566             ;
+; spi2dac:dac|shift_reg[10]          ; spi2dac:dac|shift_reg[11]                                                                              ; 0.566             ;
+; spi2dac:dac|shift_reg[2]           ; spi2dac:dac|shift_reg[3]                                                                               ; 0.534             ;
+; pwm:p|count[0]                     ; pwm:p|count[9]                                                                                         ; 0.517             ;
+; pwm:p|count[9]                     ; pwm:p|pwm_out                                                                                          ; 0.428             ;
+; spi2dac:dac|sr_state.IDLE          ; spi2dac:dac|sr_state.WAIT_CSB_FALL                                                                     ; 0.377             ;
+; pwm:p|d[8]                         ; pwm:p|pwm_out                                                                                          ; 0.365             ;
+; spi2dac:dac|sr_state.WAIT_CSB_FALL ; spi2dac:dac|sr_state.IDLE                                                                              ; 0.361             ;
+; pwm:p|d[9]                         ; pwm:p|pwm_out                                                                                          ; 0.304             ;
+; pwm:p|count[8]                     ; pwm:p|pwm_out                                                                                          ; 0.274             ;
+; spi2dac:dac|sr_state.WAIT_CSB_HIGH ; spi2dac:dac|sr_state.WAIT_CSB_FALL                                                                     ; 0.227             ;
+; pwm:p|count[5]                     ; pwm:p|pwm_out                                                                                          ; 0.216             ;
+; pwm:p|d[6]                         ; pwm:p|pwm_out                                                                                          ; 0.157             ;
+; pwm:p|d[7]                         ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|d[5]                         ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|d[4]                         ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|d[3]                         ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|d[2]                         ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|d[1]                         ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|d[0]                         ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|count[7]                     ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|count[6]                     ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|count[4]                     ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|count[3]                     ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|count[2]                     ; pwm:p|pwm_out                                                                                          ; 0.146             ;
+; pwm:p|count[1]                     ; pwm:p|pwm_out                                                                                          ; 0.146             ;
++------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 74 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex10"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 55 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:05
+Info (11888): Total time spent on timing analysis during the Fitter is 0.46 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file /Desktop/ex14/output_files/ex10.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 35 warnings
+    Info: Peak virtual memory: 2728 megabytes
+    Info: Processing ended: Fri Dec 02 17:38:39 2016
+    Info: Elapsed time: 00:00:39
+    Info: Total CPU time (on all processors): 00:01:02
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /Desktop/ex14/output_files/ex10.fit.smsg.
+
+
diff --git a/part_2/ex9_final/output_files/ex9.fit.smsg b/part_3/ex14/output_files/ex10.fit.smsg
index 43eead5..43eead5 100755
--- a/part_2/ex9_final/output_files/ex9.fit.smsg
+++ b/part_3/ex14/output_files/ex10.fit.smsg
diff --git a/part_3/ex14/output_files/ex10.fit.summary b/part_3/ex14/output_files/ex10.fit.summary
new file mode 100755
index 0000000..5484074
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Fri Dec 02 17:38:37 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex10
+Top-level Entity Name : ex14
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 136 / 32,070 ( < 1 % )
+Total registers : 84
+Total pins : 51 / 457 ( 11 % )
+Total virtual pins : 0
+Total block memory bits : 10,240 / 4,065,280 ( < 1 % )
+Total RAM Blocks : 1 / 397 ( < 1 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_3/ex14/output_files/ex10.flow.rpt b/part_3/ex14/output_files/ex10.flow.rpt
new file mode 100755
index 0000000..f1d6231
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.flow.rpt
@@ -0,0 +1,136 @@
+Flow report for ex10
+Fri Dec 02 17:39:09 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Fri Dec 02 17:39:09 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex10                                            ;
+; Top-level Entity Name           ; ex14                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 136 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 84                                              ;
+; Total pins                      ; 51 / 457 ( 11 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 10,240 / 4,065,280 ( < 1 % )                    ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 12/02/2016 17:37:46 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex10                ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                           ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 260248564477497.148070026608824       ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                           ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)             ; <None>        ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --             ;
+; MISC_FILE                           ; verilog_files/ROM_bb.v                ; --            ; --          ; --             ;
+; MISC_FILE                           ; const_mult_bb.v                       ; --            ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; ex14        ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; ex14        ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; ex14        ; Top            ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --             ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --             ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --             ;
+; TOP_LEVEL_ENTITY                    ; ex14                                  ; ex10          ; --          ; --             ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:12     ; 1.0                     ; 915 MB              ; 00:00:22                           ;
+; Fitter                    ; 00:00:37     ; 1.0                     ; 2728 MB             ; 00:01:01                           ;
+; Assembler                 ; 00:00:09     ; 1.0                     ; 901 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:09     ; 1.1                     ; 1246 MB             ; 00:00:07                           ;
+; EDA Netlist Writer        ; 00:00:02     ; 1.0                     ; 816 MB              ; 00:00:01                           ;
+; Total                     ; 00:01:09     ; --                      ; --                  ; 00:01:37                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
+; EDA Netlist Writer        ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10
+quartus_fit --read_settings_files=off --write_settings_files=off ex10 -c ex10
+quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10
+quartus_sta ex10 -c ex10
+quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10
+
+
+
diff --git a/part_3/ex14/output_files/ex10.jdi b/part_3/ex14/output_files/ex10.jdi
new file mode 100755
index 0000000..6eee4a9
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="d33b9c5382cfe5ea4b74"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex10.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_3/ex14/output_files/ex10.map.rpt b/part_3/ex14/output_files/ex10.map.rpt
new file mode 100755
index 0000000..05807e6
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.map.rpt
@@ -0,0 +1,791 @@
+Analysis & Synthesis report for ex10
+Fri Dec 02 17:37:58 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |ex14|spi2dac:dac|sr_state
+ 11. Registers Removed During Synthesis
+ 12. Removed Registers Triggering Further Register Optimizations
+ 13. General Register Statistics
+ 14. Inverted Register Statistics
+ 15. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 16. Source assignments for ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated
+ 17. Parameter Settings for User Entity Instance: tick_5000:tick
+ 18. Parameter Settings for User Entity Instance: ROM:rom|altsyncram:altsyncram_component
+ 19. Parameter Settings for User Entity Instance: spi2dac:dac
+ 20. Parameter Settings for User Entity Instance: const_mult:mult|lpm_mult:lpm_mult_component
+ 21. altsyncram Parameter Settings by Entity Instance
+ 22. lpm_mult Parameter Settings by Entity Instance
+ 23. Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A18"
+ 24. Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A9"
+ 25. Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A3"
+ 26. Port Connectivity Checks: "bin2bcd_16:bcd"
+ 27. Port Connectivity Checks: "const_mult:mult"
+ 28. Post-Synthesis Netlist Statistics for Top Partition
+ 29. Elapsed Time Per Partition
+ 30. Analysis & Synthesis Messages
+ 31. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Fri Dec 02 17:37:58 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex10                                            ;
+; Top-level Entity Name           ; ex14                                            ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 76                                              ;
+; Total pins                      ; 51                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 10,240                                          ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex14               ; ex10               ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                         ;
++----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                              ; File Name with Absolute Path                                           ; Library ;
++----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+
+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/add3_ge5.v      ;         ;
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/hex_to_7seg.v   ;         ;
+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v    ;         ;
+; ex14.v                           ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v                        ;         ;
+; verilog_files/ROM.v              ; yes             ; User Wizard-Generated File             ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v           ;         ;
+; verilog_files/tick_5000.v        ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/tick_5000.v     ;         ;
+; verilog_files/spi2dac.v          ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/spi2dac.v       ;         ;
+; verilog_files/pwm.v              ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/pwm.v           ;         ;
+; const_mult.v                     ; yes             ; User Wizard-Generated File             ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v                  ;         ;
+; add_offset.v                     ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/add_offset.v                  ;         ;
+; altsyncram.tdf                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf          ;         ;
+; stratix_ram_block.inc            ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/stratix_ram_block.inc   ;         ;
+; lpm_mux.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_mux.inc             ;         ;
+; lpm_decode.inc                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_decode.inc          ;         ;
+; aglobal160.inc                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc          ;         ;
+; a_rdenreg.inc                    ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/a_rdenreg.inc           ;         ;
+; altrom.inc                       ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altrom.inc              ;         ;
+; altram.inc                       ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altram.inc              ;         ;
+; altdpram.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altdpram.inc            ;         ;
+; db/altsyncram_6ng1.tdf           ; yes             ; Auto-Generated Megafunction            ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/altsyncram_6ng1.tdf        ;         ;
+; rom_data/rom_data.mif            ; yes             ; Auto-Found Memory Initialization File  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/rom_data/rom_data.mif         ;         ;
+; lpm_mult.tdf                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf            ;         ;
+; lpm_add_sub.inc                  ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.inc         ;         ;
+; multcore.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/multcore.inc            ;         ;
+; bypassff.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/bypassff.inc            ;         ;
+; altshift.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altshift.inc            ;         ;
+; multcore.tdf                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf            ;         ;
+; csa_add.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/csa_add.inc             ;         ;
+; mpar_add.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.inc            ;         ;
+; muleabz.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/muleabz.inc             ;         ;
+; mul_lfrg.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/mul_lfrg.inc            ;         ;
+; mul_boothc.inc                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/mul_boothc.inc          ;         ;
+; alt_ded_mult.inc                 ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult.inc        ;         ;
+; alt_ded_mult_y.inc               ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult_y.inc      ;         ;
+; dffpipe.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/dffpipe.inc             ;         ;
+; mpar_add.tdf                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf            ;         ;
+; lpm_add_sub.tdf                  ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;         ;
+; addcore.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/addcore.inc             ;         ;
+; look_add.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/look_add.inc            ;         ;
+; alt_stratix_add_sub.inc          ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;         ;
+; db/add_sub_d9h.tdf               ; yes             ; Auto-Generated Megafunction            ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_d9h.tdf            ;         ;
+; db/add_sub_89h.tdf               ; yes             ; Auto-Generated Megafunction            ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_89h.tdf            ;         ;
+; altshift.tdf                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altshift.tdf            ;         ;
++----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimate of Logic utilization (ALMs needed) ; 136            ;
+;                                             ;                ;
+; Combinational ALUT usage for logic          ; 240            ;
+;     -- 7 input functions                    ; 0              ;
+;     -- 6 input functions                    ; 20             ;
+;     -- 5 input functions                    ; 23             ;
+;     -- 4 input functions                    ; 120            ;
+;     -- <=3 input functions                  ; 77             ;
+;                                             ;                ;
+; Dedicated logic registers                   ; 76             ;
+;                                             ;                ;
+; I/O pins                                    ; 51             ;
+; Total MLAB memory bits                      ; 0              ;
+; Total block memory bits                     ; 10240          ;
+;                                             ;                ;
+; Total DSP Blocks                            ; 0              ;
+;                                             ;                ;
+; Maximum fan-out node                        ; CLOCK_50~input ;
+; Maximum fan-out                             ; 57             ;
+; Total fan-out                               ; 1292           ;
+; Average fan-out                             ; 3.02           ;
++---------------------------------------------+----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                      ;
++---------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                        ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                       ; Entity Name     ; Library Name ;
++---------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex14                                             ; 240 (0)           ; 76 (0)       ; 10240             ; 0          ; 51   ; 0            ; |ex14                                                                                                                                                     ; ex14            ; work         ;
+;    |ROM:rom|                                      ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex14|ROM:rom                                                                                                                                             ; ROM             ; work         ;
+;       |altsyncram:altsyncram_component|           ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex14|ROM:rom|altsyncram:altsyncram_component                                                                                                             ; altsyncram      ; work         ;
+;          |altsyncram_6ng1:auto_generated|         ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex14|ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated                                                                              ; altsyncram_6ng1 ; work         ;
+;    |add_offset:fin_address|                       ; 10 (10)           ; 10 (10)      ; 0                 ; 0          ; 0    ; 0            ; |ex14|add_offset:fin_address                                                                                                                              ; add_offset      ; work         ;
+;    |bin2bcd_16:bcd|                               ; 97 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd                                                                                                                                      ; bin2bcd_16      ; work         ;
+;       |add3_ge5:A10|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A10                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A11|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A11                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A12|                              ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A12                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A13|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A13                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A14|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A14                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A15|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A15                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A16|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A16                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A17|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A17                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A19|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A19                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A1|                               ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A1                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A20|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A20                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A21|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A21                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A22|                              ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A22                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A23|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A23                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A24|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A24                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A25|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A25                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A26|                              ; 9 (9)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A26                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A27|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A27                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A28|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A28                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A29|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A29                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A2|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A2                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A4|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A4                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A5|                               ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A5                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A6|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A6                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A7|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A7                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A8|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|bin2bcd_16:bcd|add3_ge5:A8                                                                                                                          ; add3_ge5        ; work         ;
+;    |const_mult:mult|                              ; 36 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult                                                                                                                                     ; const_mult      ; work         ;
+;       |lpm_mult:lpm_mult_component|               ; 36 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component                                                                                                         ; lpm_mult        ; work         ;
+;          |multcore:mult_core|                     ; 36 (6)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core                                                                                      ; multcore        ; work         ;
+;             |mpar_add:padder|                     ; 30 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder                                                                      ; mpar_add        ; work         ;
+;                |lpm_add_sub:adder[0]|             ; 18 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; lpm_add_sub     ; work         ;
+;                   |add_sub_d9h:auto_generated|    ; 18 (18)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated                      ; add_sub_d9h     ; work         ;
+;                |mpar_add:sub_par_add|             ; 12 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; mpar_add        ; work         ;
+;                   |lpm_add_sub:adder[0]|          ; 12 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; lpm_add_sub     ; work         ;
+;                      |add_sub_89h:auto_generated| ; 12 (12)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated ; add_sub_89h     ; work         ;
+;    |hex_to_7seg:h0|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h0                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h1|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h1                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h2|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h2                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h3|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h3                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h4|                               ; 3 (3)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex14|hex_to_7seg:h4                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |pwm:p|                                        ; 16 (16)           ; 21 (21)      ; 0                 ; 0          ; 0    ; 0            ; |ex14|pwm:p                                                                                                                                               ; pwm             ; work         ;
+;    |spi2dac:dac|                                  ; 23 (23)           ; 28 (28)      ; 0                 ; 0          ; 0    ; 0            ; |ex14|spi2dac:dac                                                                                                                                         ; spi2dac         ; work         ;
+;    |tick_5000:tick|                               ; 27 (27)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex14|tick_5000:tick                                                                                                                                      ; tick_5000       ; work         ;
++---------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                              ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+; Name                                                                              ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                     ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 1024         ; 10           ; --           ; --           ; 10240 ; ./rom_data/rom_data.mif ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                   ;
++--------+--------------+---------+--------------+--------------+-----------------------+-----------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance       ; IP Include File ;
++--------+--------------+---------+--------------+--------------+-----------------------+-----------------+
+; Altera ; LPM_MULT     ; 16.1    ; N/A          ; N/A          ; |ex14|const_mult:mult ; const_mult.v    ;
++--------+--------------+---------+--------------+--------------+-----------------------+-----------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex14|spi2dac:dac|sr_state                                               ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                             ;
++---------------------------------------+----------------------------------------+
+; Register name                         ; Reason for Removal                     ;
++---------------------------------------+----------------------------------------+
+; spi2dac:dac|shift_reg[0,1]            ; Stuck at GND due to stuck port data_in ;
+; Total Number of Removed Registers = 2 ;                                        ;
++---------------------------------------+----------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                   ;
++--------------------------+---------------------------+----------------------------------------+
+; Register name            ; Reason for Removal        ; Registers Removed due to This Register ;
++--------------------------+---------------------------+----------------------------------------+
+; spi2dac:dac|shift_reg[0] ; Stuck at GND              ; spi2dac:dac|shift_reg[1]               ;
+;                          ; due to stuck port data_in ;                                        ;
++--------------------------+---------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 76    ;
+; Number of registers using Synchronous Clear  ; 9     ;
+; Number of registers using Synchronous Load   ; 9     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 10    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; tick_5000:tick|count[9]                ; 2       ;
+; tick_5000:tick|count[0]                ; 2       ;
+; tick_5000:tick|count[1]                ; 2       ;
+; tick_5000:tick|count[2]                ; 2       ;
+; tick_5000:tick|count[7]                ; 2       ;
+; tick_5000:tick|count[8]                ; 2       ;
+; tick_5000:tick|count[12]               ; 2       ;
+; Total number of inverted registers = 7 ;         ;
++----------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex14|spi2dac:dac|Selector0 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Source assignments for ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated ;
++---------------------------------+--------------------+------+---------------------------------+
+; Assignment                      ; Value              ; From ; To                              ;
++---------------------------------+--------------------+------+---------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                               ;
++---------------------------------+--------------------+------+---------------------------------+
+
+
++-------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_5000:tick ;
++----------------+-------+------------------------------------+
+; Parameter Name ; Value ; Type                               ;
++----------------+-------+------------------------------------+
+; NBIT           ; 16    ; Signed Integer                     ;
++----------------+-------+------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: ROM:rom|altsyncram:altsyncram_component ;
++------------------------------------+-------------------------+-----------------------+
+; Parameter Name                     ; Value                   ; Type                  ;
++------------------------------------+-------------------------+-----------------------+
+; BYTE_SIZE_BLOCK                    ; 8                       ; Untyped               ;
+; AUTO_CARRY_CHAINS                  ; ON                      ; AUTO_CARRY            ;
+; IGNORE_CARRY_BUFFERS               ; OFF                     ; IGNORE_CARRY          ;
+; AUTO_CASCADE_CHAINS                ; ON                      ; AUTO_CASCADE          ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                     ; IGNORE_CASCADE        ;
+; WIDTH_BYTEENA                      ; 1                       ; Untyped               ;
+; OPERATION_MODE                     ; ROM                     ; Untyped               ;
+; WIDTH_A                            ; 10                      ; Signed Integer        ;
+; WIDTHAD_A                          ; 10                      ; Signed Integer        ;
+; NUMWORDS_A                         ; 1024                    ; Signed Integer        ;
+; OUTDATA_REG_A                      ; CLOCK0                  ; Untyped               ;
+; ADDRESS_ACLR_A                     ; NONE                    ; Untyped               ;
+; OUTDATA_ACLR_A                     ; NONE                    ; Untyped               ;
+; WRCONTROL_ACLR_A                   ; NONE                    ; Untyped               ;
+; INDATA_ACLR_A                      ; NONE                    ; Untyped               ;
+; BYTEENA_ACLR_A                     ; NONE                    ; Untyped               ;
+; WIDTH_B                            ; 1                       ; Untyped               ;
+; WIDTHAD_B                          ; 1                       ; Untyped               ;
+; NUMWORDS_B                         ; 1                       ; Untyped               ;
+; INDATA_REG_B                       ; CLOCK1                  ; Untyped               ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                  ; Untyped               ;
+; RDCONTROL_REG_B                    ; CLOCK1                  ; Untyped               ;
+; ADDRESS_REG_B                      ; CLOCK1                  ; Untyped               ;
+; OUTDATA_REG_B                      ; UNREGISTERED            ; Untyped               ;
+; BYTEENA_REG_B                      ; CLOCK1                  ; Untyped               ;
+; INDATA_ACLR_B                      ; NONE                    ; Untyped               ;
+; WRCONTROL_ACLR_B                   ; NONE                    ; Untyped               ;
+; ADDRESS_ACLR_B                     ; NONE                    ; Untyped               ;
+; OUTDATA_ACLR_B                     ; NONE                    ; Untyped               ;
+; RDCONTROL_ACLR_B                   ; NONE                    ; Untyped               ;
+; BYTEENA_ACLR_B                     ; NONE                    ; Untyped               ;
+; WIDTH_BYTEENA_A                    ; 1                       ; Signed Integer        ;
+; WIDTH_BYTEENA_B                    ; 1                       ; Untyped               ;
+; RAM_BLOCK_TYPE                     ; AUTO                    ; Untyped               ;
+; BYTE_SIZE                          ; 8                       ; Untyped               ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE               ; Untyped               ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ    ; Untyped               ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ    ; Untyped               ;
+; INIT_FILE                          ; ./rom_data/rom_data.mif ; Untyped               ;
+; INIT_FILE_LAYOUT                   ; PORT_A                  ; Untyped               ;
+; MAXIMUM_DEPTH                      ; 0                       ; Untyped               ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS                  ; Untyped               ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL                  ; Untyped               ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS                  ; Untyped               ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                  ; Untyped               ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN         ; Untyped               ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN         ; Untyped               ;
+; ENABLE_ECC                         ; FALSE                   ; Untyped               ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                   ; Untyped               ;
+; WIDTH_ECCSTATUS                    ; 3                       ; Untyped               ;
+; DEVICE_FAMILY                      ; Cyclone V               ; Untyped               ;
+; CBXI_PARAMETER                     ; altsyncram_6ng1         ; Untyped               ;
++------------------------------------+-------------------------+-----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2dac:dac ;
++----------------+-------+---------------------------------+
+; Parameter Name ; Value ; Type                            ;
++----------------+-------+---------------------------------+
+; BUF            ; 1     ; Unsigned Binary                 ;
+; GA_N           ; 1     ; Unsigned Binary                 ;
+; SHDN_N         ; 1     ; Unsigned Binary                 ;
+; TC             ; 11000 ; Unsigned Binary                 ;
+; IDLE           ; 00    ; Unsigned Binary                 ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                 ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                 ;
++----------------+-------+---------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: const_mult:mult|lpm_mult:lpm_mult_component ;
++------------------------------------------------+-----------+-----------------------------+
+; Parameter Name                                 ; Value     ; Type                        ;
++------------------------------------------------+-----------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON        ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF       ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON        ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF       ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 10        ; Signed Integer              ;
+; LPM_WIDTHB                                     ; 14        ; Signed Integer              ;
+; LPM_WIDTHP                                     ; 24        ; Signed Integer              ;
+; LPM_WIDTHR                                     ; 0         ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1         ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED  ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0         ; Untyped                     ;
+; LATENCY                                        ; 0         ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO        ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES       ; Untyped                     ;
+; USE_EAB                                        ; OFF       ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5         ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone V ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL    ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT       ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO      ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0         ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0         ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING   ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx        ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx        ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF       ; Untyped                     ;
++------------------------------------------------+-----------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance                                    ;
++-------------------------------------------+-----------------------------------------+
+; Name                                      ; Value                                   ;
++-------------------------------------------+-----------------------------------------+
+; Number of entity instances                ; 1                                       ;
+; Entity Instance                           ; ROM:rom|altsyncram:altsyncram_component ;
+;     -- OPERATION_MODE                     ; ROM                                     ;
+;     -- WIDTH_A                            ; 10                                      ;
+;     -- NUMWORDS_A                         ; 1024                                    ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                  ;
+;     -- WIDTH_B                            ; 1                                       ;
+;     -- NUMWORDS_B                         ; 1                                       ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                  ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                    ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                               ;
++-------------------------------------------+-----------------------------------------+
+
+
++-------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                      ;
++---------------------------------------+---------------------------------------------+
+; Name                                  ; Value                                       ;
++---------------------------------------+---------------------------------------------+
+; Number of entity instances            ; 1                                           ;
+; Entity Instance                       ; const_mult:mult|lpm_mult:lpm_mult_component ;
+;     -- LPM_WIDTHA                     ; 10                                          ;
+;     -- LPM_WIDTHB                     ; 14                                          ;
+;     -- LPM_WIDTHP                     ; 24                                          ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                    ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                          ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                         ;
+;     -- USE_EAB                        ; OFF                                         ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                        ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                          ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                          ;
++---------------------------------------+---------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A18" ;
++------+-------+----------+-------------------------------+
+; Port ; Type  ; Severity ; Details                       ;
++------+-------+----------+-------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                  ;
++------+-------+----------+-------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A9" ;
++------+-------+----------+------------------------------+
+; Port ; Type  ; Severity ; Details                      ;
++------+-------+----------+------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                 ;
++------+-------+----------+------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A3" ;
++------+-------+----------+------------------------------+
+; Port ; Type  ; Severity ; Details                      ;
++------+-------+----------+------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                 ;
++------+-------+----------+------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:bcd"                                                                                                                              ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                                                                                                       ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; B    ; Input ; Warning  ; Input port expression (14 bits) is smaller than the input port (16 bits) it drives.  Extra input bit(s) "B[15..14]" will be connected to GND. ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "const_mult:mult"                                                                            ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                             ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+; result[9..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 76                          ;
+;     ENA               ; 10                          ;
+;     SCLR              ; 9                           ;
+;     SLD               ; 9                           ;
+;     plain             ; 48                          ;
+; arriav_lcell_comb     ; 261                         ;
+;     arith             ; 65                          ;
+;         0 data inputs ; 2                           ;
+;         1 data inputs ; 31                          ;
+;         2 data inputs ; 16                          ;
+;         3 data inputs ; 5                           ;
+;         4 data inputs ; 5                           ;
+;         5 data inputs ; 6                           ;
+;     normal            ; 196                         ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 28                          ;
+;         2 data inputs ; 3                           ;
+;         3 data inputs ; 12                          ;
+;         4 data inputs ; 115                         ;
+;         5 data inputs ; 17                          ;
+;         6 data inputs ; 20                          ;
+; boundary_port         ; 51                          ;
+; stratixv_ram_block    ; 10                          ;
+;                       ;                             ;
+; Max LUT depth         ; 17.00                       ;
+; Average LUT depth     ; 9.14                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 17:37:45 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10
+Critical Warning (136021): Ignored assignment IO_STANDARD which contains an invalid node name "LEDR[3]#============================================================"
+Critical Warning (136021): Ignored assignment IO_STANDARD which contains an invalid node name "LEDR[3]#============================================================"
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/add3_ge5.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file ex14.v
+    Info (12023): Found entity 1: ex14 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/rom.v
+    Info (12023): Found entity 1: ROM File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v
+    Info (12023): Found entity 1: tick_5000 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/tick_5000.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v
+    Info (12023): Found entity 1: spi2dac File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/spi2dac.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/pwm.v
+    Info (12023): Found entity 1: pwm File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/pwm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file const_mult.v
+    Info (12023): Found entity 1: const_mult File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file add_offset.v
+    Info (12023): Found entity 1: add_offset File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/add_offset.v Line: 1
+Info (12127): Elaborating entity "ex14" for the top level hierarchy
+Info (12128): Elaborating entity "tick_5000" for hierarchy "tick_5000:tick" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 14
+Info (12128): Elaborating entity "add_offset" for hierarchy "add_offset:fin_address" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 16
+Info (12128): Elaborating entity "ROM" for hierarchy "ROM:rom" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 18
+Info (12128): Elaborating entity "altsyncram" for hierarchy "ROM:rom|altsyncram:altsyncram_component" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v Line: 82
+Info (12130): Elaborated megafunction instantiation "ROM:rom|altsyncram:altsyncram_component" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v Line: 82
+Info (12133): Instantiated megafunction "ROM:rom|altsyncram:altsyncram_component" with the following parameter: File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v Line: 82
+    Info (12134): Parameter "address_aclr_a" = "NONE"
+    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
+    Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
+    Info (12134): Parameter "init_file" = "./rom_data/rom_data.mif"
+    Info (12134): Parameter "intended_device_family" = "Cyclone V"
+    Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
+    Info (12134): Parameter "lpm_type" = "altsyncram"
+    Info (12134): Parameter "numwords_a" = "1024"
+    Info (12134): Parameter "operation_mode" = "ROM"
+    Info (12134): Parameter "outdata_aclr_a" = "NONE"
+    Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
+    Info (12134): Parameter "widthad_a" = "10"
+    Info (12134): Parameter "width_a" = "10"
+    Info (12134): Parameter "width_byteena_a" = "1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf
+    Info (12023): Found entity 1: altsyncram_6ng1 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/altsyncram_6ng1.tdf Line: 28
+Info (12128): Elaborating entity "altsyncram_6ng1" for hierarchy "ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 792
+Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:dac" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 20
+Info (12128): Elaborating entity "pwm" for hierarchy "pwm:p" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 21
+Info (12128): Elaborating entity "const_mult" for hierarchy "const_mult:mult" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 23
+Info (12128): Elaborating entity "lpm_mult" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v Line: 59
+Info (12130): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v Line: 59
+Info (12133): Instantiated megafunction "const_mult:mult|lpm_mult:lpm_mult_component" with the following parameter: File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v Line: 59
+    Info (12134): Parameter "lpm_hint" = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+    Info (12134): Parameter "lpm_representation" = "UNSIGNED"
+    Info (12134): Parameter "lpm_type" = "LPM_MULT"
+    Info (12134): Parameter "lpm_widtha" = "10"
+    Info (12134): Parameter "lpm_widthb" = "14"
+    Info (12134): Parameter "lpm_widthp" = "24"
+Info (12128): Elaborating entity "multcore" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309
+Info (12128): Elaborating entity "mpar_add" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder" File: c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf Line: 229
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf Line: 229
+Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_d9h.tdf
+    Info (12023): Found entity 1: add_sub_d9h File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_d9h.tdf Line: 23
+Info (12128): Elaborating entity "add_sub_d9h" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119
+Info (12128): Elaborating entity "mpar_add" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
+Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_89h.tdf
+    Info (12023): Found entity 1: add_sub_89h File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_89h.tdf Line: 23
+Info (12128): Elaborating entity "add_sub_89h" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119
+Info (12128): Elaborating entity "altshift" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|altshift:external_latency_ffs" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|altshift:external_latency_ffs", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:bcd" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 25
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:bcd|add3_ge5:A1" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:h0" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 27
+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX4[1]" is stuck at GND File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v Line: 6
+Info (286030): Timing-Driven Synthesis is running
+Info (144001): Generated suppressed messages file /Desktop/ex14/output_files/ex10.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 321 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 11 input pins
+    Info (21059): Implemented 40 output pins
+    Info (21061): Implemented 260 logic cells
+    Info (21064): Implemented 10 RAM segments
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 915 megabytes
+    Info: Processing ended: Fri Dec 02 17:37:58 2016
+    Info: Elapsed time: 00:00:13
+    Info: Total CPU time (on all processors): 00:00:23
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in /Desktop/ex14/output_files/ex10.map.smsg.
+
+
diff --git a/part_3/ex14/output_files/ex10.map.smsg b/part_3/ex14/output_files/ex10.map.smsg
new file mode 100755
index 0000000..aa9dd5c
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.map.smsg
@@ -0,0 +1,29 @@
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_2/ex9_partially_working/output_files/ex9.map.summary b/part_3/ex14/output_files/ex10.map.summary
index b9abbcf..4afb858 100755
--- a/part_2/ex9_partially_working/output_files/ex9.map.summary
+++ b/part_3/ex14/output_files/ex10.map.summary
@@ -1,13 +1,13 @@
-Analysis & Synthesis Status : Successful - Fri Nov 25 11:27:18 2016
+Analysis & Synthesis Status : Successful - Fri Dec 02 17:37:58 2016
 Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
+Revision Name : ex10
+Top-level Entity Name : ex14
 Family : Cyclone V
 Logic utilization (in ALMs) : N/A
-Total registers : 85
-Total pins : 57
+Total registers : 76
+Total pins : 51
 Total virtual pins : 0
-Total block memory bits : 0
+Total block memory bits : 10,240
 Total DSP Blocks : 0
 Total HSSI RX PCSs : 0
 Total HSSI PMA RX Deserializers : 0
diff --git a/part_2/ex9_partially_working/output_files/ex9.pin b/part_3/ex14/output_files/ex10.pin
index 6b2c6db..52ee778 100755
--- a/part_2/ex9_partially_working/output_files/ex9.pin
+++ b/part_3/ex14/output_files/ex10.pin
@@ -28,7 +28,7 @@
  -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
  -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
  --                 of its bank.
- --                  Bank 3A:       2.5V
+ --                  Bank 3A:       3.3V
  --                  Bank 3B:       3.3V
  --                  Bank 4A:       3.3V
  --                  Bank 5A:       3.3V
@@ -74,7 +74,7 @@
  ---------------------------------------------------------------------------------
 
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-CHIP  "ex9"  ASSIGNED TO AN: 5CSEMA5F31C6
+CHIP  "ex10"  ASSIGNED TO AN: 5CSEMA5F31C6
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
 -------------------------------------------------------------------------------------------------------------
@@ -115,12 +115,12 @@ GND                          : AA6       : gnd    :                   :
 DNU                          : AA7       :        :                   :         :           :                
 VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
 GND                          : AA9       : gnd    :                   :         :           :                
-VCCPD3A                      : AA10      : power  :                   : 2.5V    : 3A        :                
+VCCPD3A                      : AA10      : power  :                   : 3.3V    : 3A        :                
 GND                          : AA11      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
-KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
 VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
@@ -130,10 +130,10 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :
 GND                          : AA22      : gnd    :                   :         :           :                
 VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
 HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[6]                      : AA25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[5]                      : AA26      : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
 VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
-HEX5[1]                      : AA28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
 VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
 GND                          : AB1       : gnd    :                   :         :           :                
@@ -147,7 +147,7 @@ nCSO, DATA4                  : AB8       :        :                   :
 TDO                          : AB9       : output :                   :         : 3A        :                
 VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
 VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 3A        :                
+SW[0]                        : AB12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
 VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
@@ -161,8 +161,8 @@ HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :
 HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
 VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
 HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[4]                      : AB26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[3]                      : AB27      : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
 HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
 GND                          : AB29      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
@@ -174,10 +174,10 @@ TCK                          : AC5       : input  :                   :
 GND                          : AC6       : gnd    :                   :         :           :                
 AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
 GND                          : AC8       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9       :        :                   :         : 3A        :                
-VCCPD3A                      : AC10      : power  :                   : 2.5V    : 3A        :                
-VCCIO3A                      : AC11      : power  :                   : 2.5V    : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC12      :        :                   :         : 3A        :                
+SW[7]                        : AC9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3A                      : AC10      : power  :                   : 3.3V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 3.3V    : 3A        :                
+SW[1]                        : AC12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
 VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
 VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
@@ -203,11 +203,11 @@ DNU                          : AD4       :        :                   :
 GND                          : AD5       : gnd    :                   :         :           :                
 VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
-VCCIO3A                      : AD8       : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 3.3V    : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD12      :        :                   :         : 3A        :                
+SW[8]                        : AD10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[4]                        : AD11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[5]                        : AD12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
 VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
 DNU                          : AD15      :        :                   :         :           :                
@@ -215,7 +215,7 @@ VCCPD3B4A                    : AD16      : power  :                   : 3.3V
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
 VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+DAC_CS                       : AD20      : output : 3.3-V LVTTL       :         : 4A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
 VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
 GND                          : AD23      : gnd    :                   :         :           :                
@@ -236,8 +236,8 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :
 AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
 GND                          : AE10      : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11      :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12      :        :                   :         : 3A        :                
+SW[6]                        : AE11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[9]                        : AE12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
 VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
@@ -262,10 +262,10 @@ GND                          : AF3       : gnd    :                   :
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
-VCCIO3A                      : AF7       : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 3.3V    : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9       :        :                   :         : 3A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10      :        :                   :         : 3A        :                
+SW[2]                        : AF9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[3]                        : AF10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
 GND                          : AF12      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
@@ -275,7 +275,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :
 GND                          : AF17      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
+DAC_SCK                      : AF20      : output : 3.3-V LVTTL       :         : 4A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
 VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
@@ -289,7 +289,7 @@ HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
-VCCIO3A                      : AG4       : power  :                   : 2.5V    : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 3.3V    : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
@@ -303,7 +303,7 @@ GND                          : AG14      : gnd    :                   :
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+DAC_SDI                      : AG18      : output : 3.3-V LVTTL       :         : 4A        : Y              
 VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
@@ -365,7 +365,7 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :
 RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
 GND                          : AJ18      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
+PWM_OUT                      : AJ20      : output : 3.3-V LVTTL       :         : 4A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
 VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
@@ -395,7 +395,7 @@ VREFB4AN0                    : AK17      : power  :                   :
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
 VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+DAC_LD                       : AK21      : output : 3.3-V LVTTL       :         : 4A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
@@ -899,16 +899,16 @@ GND                          : V12       : gnd    :                   :
 VCC                          : V13       : power  :                   : 1.1V    :           :                
 GND                          : V14       : gnd    :                   :         :           :                
 VCC                          : V15       : power  :                   : 1.1V    :           :                
-LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
 GND                          : V19       : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
 GND                          : V21       : gnd    :                   :         :           :                
 VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
 HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
 VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
-HEX5[0]                      : V25       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
 VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
@@ -928,13 +928,13 @@ GND                          : W11       : gnd    :                   :
 VCC                          : W12       : power  :                   : 1.1V    :           :                
 GND                          : W13       : gnd    :                   :         :           :                
 VCC                          : W14       : power  :                   : 1.1V    :           :                
-KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              
-LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
 GND                          : W18       : gnd    :                   :         :           :                
-LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              
-LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                
 HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
 VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
 HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
@@ -959,18 +959,18 @@ GND                          : Y12       : gnd    :                   :
 VCC                          : Y13       : power  :                   : 1.1V    :           :                
 GND                          : Y14       : gnd    :                   :         :           :                
 GND                          : Y15       : gnd    :                   :         :           :                
-KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
-LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
 GND                          : Y20       : gnd    :                   :         :           :                
-LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
 VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
 HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
 HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
 GND                          : Y25       : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
-HEX5[2]                      : Y27       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
 GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_2/ex9_final/output_files/ex9.sld b/part_3/ex14/output_files/ex10.sld
index 41a6030..41a6030 100755
--- a/part_2/ex9_final/output_files/ex9.sld
+++ b/part_3/ex14/output_files/ex10.sld
diff --git a/part_2/ex9_partially_working/output_files/ex9.sof b/part_3/ex14/output_files/ex10.sof
index 7a37fc1..2e5de3b 100755
--- a/part_2/ex9_partially_working/output_files/ex9.sof
+++ b/part_3/ex14/output_files/ex10.sof
diff --git a/part_3/ex14/output_files/ex10.sta.rpt b/part_3/ex14/output_files/ex10.sta.rpt
new file mode 100755
index 0000000..5743b14
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.sta.rpt
@@ -0,0 +1,961 @@
+TimeQuest Timing Analyzer report for ex10
+Fri Dec 02 17:39:04 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex10                                                    ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CSEMA5F31C6                                            ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.09        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   3.0%      ;
+;     Processor 3            ;   2.9%      ;
+;     Processor 4            ;   2.8%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                         ;
++------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
+; Clock Name             ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                    ;
++------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
+; CLOCK_50               ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }               ;
+; spi2dac:dac|clk_1MHz   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2dac:dac|clk_1MHz }   ;
+; tick_5000:tick|CLK_OUT ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_5000:tick|CLK_OUT } ;
++------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary                           ;
++------------+-----------------+------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name             ; Note ;
++------------+-----------------+------------------------+------+
+; 218.72 MHz ; 218.72 MHz      ; CLOCK_50               ;      ;
+; 281.69 MHz ; 281.69 MHz      ; spi2dac:dac|clk_1MHz   ;      ;
+; 403.88 MHz ; 403.88 MHz      ; tick_5000:tick|CLK_OUT ;      ;
++------------+-----------------+------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary             ;
++------------------------+--------+---------------+
+; Clock                  ; Slack  ; End Point TNS ;
++------------------------+--------+---------------+
+; spi2dac:dac|clk_1MHz   ; -3.834 ; -62.108       ;
+; CLOCK_50               ; -3.572 ; -126.378      ;
+; tick_5000:tick|CLK_OUT ; -1.476 ; -13.479       ;
++------------------------+--------+---------------+
+
+
++------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary             ;
++------------------------+-------+---------------+
+; Clock                  ; Slack ; End Point TNS ;
++------------------------+-------+---------------+
+; CLOCK_50               ; 0.212 ; 0.000         ;
+; tick_5000:tick|CLK_OUT ; 0.528 ; 0.000         ;
+; spi2dac:dac|clk_1MHz   ; 0.731 ; 0.000         ;
++------------------------+-------+---------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++------------------------+--------+-----------------+
+; Clock                  ; Slack  ; End Point TNS   ;
++------------------------+--------+-----------------+
+; CLOCK_50               ; -2.174 ; -104.886        ;
+; spi2dac:dac|clk_1MHz   ; -0.394 ; -10.637         ;
+; tick_5000:tick|CLK_OUT ; -0.394 ; -5.320          ;
++------------------------+--------+-----------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                            ;
++------------+-----------------+------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name             ; Note ;
++------------+-----------------+------------------------+------+
+; 214.41 MHz ; 214.41 MHz      ; CLOCK_50               ;      ;
+; 287.19 MHz ; 287.19 MHz      ; spi2dac:dac|clk_1MHz   ;      ;
+; 392.77 MHz ; 392.77 MHz      ; tick_5000:tick|CLK_OUT ;      ;
++------------+-----------------+------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++-------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary              ;
++------------------------+--------+---------------+
+; Clock                  ; Slack  ; End Point TNS ;
++------------------------+--------+---------------+
+; spi2dac:dac|clk_1MHz   ; -3.877 ; -63.295       ;
+; CLOCK_50               ; -3.664 ; -119.563      ;
+; tick_5000:tick|CLK_OUT ; -1.546 ; -13.976       ;
++------------------------+--------+---------------+
+
+
++-------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary               ;
++------------------------+--------+---------------+
+; Clock                  ; Slack  ; End Point TNS ;
++------------------------+--------+---------------+
+; CLOCK_50               ; -0.131 ; -1.428        ;
+; tick_5000:tick|CLK_OUT ; 0.507  ; 0.000         ;
+; spi2dac:dac|clk_1MHz   ; 0.718  ; 0.000         ;
++------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
++------------------------+--------+----------------+
+; Clock                  ; Slack  ; End Point TNS  ;
++------------------------+--------+----------------+
+; CLOCK_50               ; -2.174 ; -101.938       ;
+; spi2dac:dac|clk_1MHz   ; -0.394 ; -10.531        ;
+; tick_5000:tick|CLK_OUT ; -0.394 ; -5.266         ;
++------------------------+--------+----------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary             ;
++------------------------+--------+---------------+
+; Clock                  ; Slack  ; End Point TNS ;
++------------------------+--------+---------------+
+; CLOCK_50               ; -2.907 ; -69.680       ;
+; spi2dac:dac|clk_1MHz   ; -1.889 ; -28.963       ;
+; tick_5000:tick|CLK_OUT ; -0.574 ; -4.704        ;
++------------------------+--------+---------------+
+
+
++------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary             ;
++------------------------+-------+---------------+
+; Clock                  ; Slack ; End Point TNS ;
++------------------------+-------+---------------+
+; CLOCK_50               ; 0.184 ; 0.000         ;
+; tick_5000:tick|CLK_OUT ; 0.239 ; 0.000         ;
+; spi2dac:dac|clk_1MHz   ; 0.304 ; 0.000         ;
++------------------------+-------+---------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++------------------------+--------+-----------------+
+; Clock                  ; Slack  ; End Point TNS   ;
++------------------------+--------+-----------------+
+; CLOCK_50               ; -2.174 ; -95.017         ;
+; tick_5000:tick|CLK_OUT ; 0.089  ; 0.000           ;
+; spi2dac:dac|clk_1MHz   ; 0.099  ; 0.000           ;
++------------------------+--------+-----------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary              ;
++------------------------+--------+---------------+
+; Clock                  ; Slack  ; End Point TNS ;
++------------------------+--------+---------------+
+; CLOCK_50               ; -2.457 ; -55.444       ;
+; spi2dac:dac|clk_1MHz   ; -1.822 ; -27.647       ;
+; tick_5000:tick|CLK_OUT ; -0.536 ; -4.307        ;
++------------------------+--------+---------------+
+
+
++-------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary               ;
++------------------------+--------+---------------+
+; Clock                  ; Slack  ; End Point TNS ;
++------------------------+--------+---------------+
+; CLOCK_50               ; -0.029 ; -0.033        ;
+; tick_5000:tick|CLK_OUT ; 0.210  ; 0.000         ;
+; spi2dac:dac|clk_1MHz   ; 0.275  ; 0.000         ;
++------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
++------------------------+--------+----------------+
+; Clock                  ; Slack  ; End Point TNS  ;
++------------------------+--------+----------------+
+; CLOCK_50               ; -2.174 ; -100.860       ;
+; tick_5000:tick|CLK_OUT ; 0.101  ; 0.000          ;
+; spi2dac:dac|clk_1MHz   ; 0.112  ; 0.000          ;
++------------------------+--------+----------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                    ;
++-------------------------+----------+--------+----------+---------+---------------------+
+; Clock                   ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
++-------------------------+----------+--------+----------+---------+---------------------+
+; Worst-case Slack        ; -3.877   ; -0.131 ; N/A      ; N/A     ; -2.174              ;
+;  CLOCK_50               ; -3.664   ; -0.131 ; N/A      ; N/A     ; -2.174              ;
+;  spi2dac:dac|clk_1MHz   ; -3.877   ; 0.275  ; N/A      ; N/A     ; -0.394              ;
+;  tick_5000:tick|CLK_OUT ; -1.546   ; 0.210  ; N/A      ; N/A     ; -0.394              ;
+; Design-wide TNS         ; -201.965 ; -1.428 ; 0.0      ; 0.0     ; -120.843            ;
+;  CLOCK_50               ; -126.378 ; -1.428 ; N/A      ; N/A     ; -104.886            ;
+;  spi2dac:dac|clk_1MHz   ; -63.295  ; 0.000  ; N/A      ; N/A     ; -10.637             ;
+;  tick_5000:tick|CLK_OUT ; -13.976  ; 0.000  ; N/A      ; N/A     ; -5.320              ;
++-------------------------+----------+--------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX3[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX3[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX3[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX3[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX3[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                             ;
++------------------------+------------------------+----------+----------+----------+----------+
+; From Clock             ; To Clock               ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------------------+------------------------+----------+----------+----------+----------+
+; CLOCK_50               ; CLOCK_50               ; 506      ; 0        ; 0        ; 0        ;
+; spi2dac:dac|clk_1MHz   ; CLOCK_50               ; 16       ; 1        ; 0        ; 0        ;
+; tick_5000:tick|CLK_OUT ; CLOCK_50               ; 22       ; 12       ; 0        ; 0        ;
+; CLOCK_50               ; spi2dac:dac|clk_1MHz   ; 25       ; 0        ; 0        ; 0        ;
+; spi2dac:dac|clk_1MHz   ; spi2dac:dac|clk_1MHz   ; 109      ; 0        ; 0        ; 0        ;
+; tick_5000:tick|CLK_OUT ; tick_5000:tick|CLK_OUT ; 55       ; 0        ; 0        ; 0        ;
++------------------------+------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++---------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                              ;
++------------------------+------------------------+----------+----------+----------+----------+
+; From Clock             ; To Clock               ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------------------+------------------------+----------+----------+----------+----------+
+; CLOCK_50               ; CLOCK_50               ; 506      ; 0        ; 0        ; 0        ;
+; spi2dac:dac|clk_1MHz   ; CLOCK_50               ; 16       ; 1        ; 0        ; 0        ;
+; tick_5000:tick|CLK_OUT ; CLOCK_50               ; 22       ; 12       ; 0        ; 0        ;
+; CLOCK_50               ; spi2dac:dac|clk_1MHz   ; 25       ; 0        ; 0        ; 0        ;
+; spi2dac:dac|clk_1MHz   ; spi2dac:dac|clk_1MHz   ; 109      ; 0        ; 0        ; 0        ;
+; tick_5000:tick|CLK_OUT ; tick_5000:tick|CLK_OUT ; 55       ; 0        ; 0        ; 0        ;
++------------------------+------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 10    ; 10   ;
+; Unconstrained Input Port Paths  ; 395   ; 395  ;
+; Unconstrained Output Ports      ; 39    ; 39   ;
+; Unconstrained Output Port Paths ; 358   ; 358  ;
++---------------------------------+-------+------+
+
+
++----------------------------------------------------------------------+
+; Clock Status Summary                                                 ;
++------------------------+------------------------+------+-------------+
+; Target                 ; Clock                  ; Type ; Status      ;
++------------------------+------------------------+------+-------------+
+; CLOCK_50               ; CLOCK_50               ; Base ; Constrained ;
+; spi2dac:dac|clk_1MHz   ; spi2dac:dac|clk_1MHz   ; Base ; Constrained ;
+; tick_5000:tick|CLK_OUT ; tick_5000:tick|CLK_OUT ; Base ; Constrained ;
++------------------------+------------------------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[9]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[9]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 17:38:54 2016
+Info: Command: quartus_sta ex10 -c ex10
+Info: qsta_default_script.tcl version: #1
+Critical Warning (136021): Ignored assignment IO_STANDARD which contains an invalid node name "LEDR[3]#============================================================"
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+    Info (332105): create_clock -period 1.000 -name tick_5000:tick|CLK_OUT tick_5000:tick|CLK_OUT
+    Info (332105): create_clock -period 1.000 -name spi2dac:dac|clk_1MHz spi2dac:dac|clk_1MHz
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.834
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.834             -62.108 spi2dac:dac|clk_1MHz 
+    Info (332119):    -3.572            -126.378 CLOCK_50 
+    Info (332119):    -1.476             -13.479 tick_5000:tick|CLK_OUT 
+Info (332146): Worst-case hold slack is 0.212
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.212               0.000 CLOCK_50 
+    Info (332119):     0.528               0.000 tick_5000:tick|CLK_OUT 
+    Info (332119):     0.731               0.000 spi2dac:dac|clk_1MHz 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174            -104.886 CLOCK_50 
+    Info (332119):    -0.394             -10.637 spi2dac:dac|clk_1MHz 
+    Info (332119):    -0.394              -5.320 tick_5000:tick|CLK_OUT 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.877
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.877             -63.295 spi2dac:dac|clk_1MHz 
+    Info (332119):    -3.664            -119.563 CLOCK_50 
+    Info (332119):    -1.546             -13.976 tick_5000:tick|CLK_OUT 
+Info (332146): Worst-case hold slack is -0.131
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.131              -1.428 CLOCK_50 
+    Info (332119):     0.507               0.000 tick_5000:tick|CLK_OUT 
+    Info (332119):     0.718               0.000 spi2dac:dac|clk_1MHz 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174            -101.938 CLOCK_50 
+    Info (332119):    -0.394             -10.531 spi2dac:dac|clk_1MHz 
+    Info (332119):    -0.394              -5.266 tick_5000:tick|CLK_OUT 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.907
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.907             -69.680 CLOCK_50 
+    Info (332119):    -1.889             -28.963 spi2dac:dac|clk_1MHz 
+    Info (332119):    -0.574              -4.704 tick_5000:tick|CLK_OUT 
+Info (332146): Worst-case hold slack is 0.184
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.184               0.000 CLOCK_50 
+    Info (332119):     0.239               0.000 tick_5000:tick|CLK_OUT 
+    Info (332119):     0.304               0.000 spi2dac:dac|clk_1MHz 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174             -95.017 CLOCK_50 
+    Info (332119):     0.089               0.000 tick_5000:tick|CLK_OUT 
+    Info (332119):     0.099               0.000 spi2dac:dac|clk_1MHz 
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.457
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.457             -55.444 CLOCK_50 
+    Info (332119):    -1.822             -27.647 spi2dac:dac|clk_1MHz 
+    Info (332119):    -0.536              -4.307 tick_5000:tick|CLK_OUT 
+Info (332146): Worst-case hold slack is -0.029
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.029              -0.033 CLOCK_50 
+    Info (332119):     0.210               0.000 tick_5000:tick|CLK_OUT 
+    Info (332119):     0.275               0.000 spi2dac:dac|clk_1MHz 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174            -100.860 CLOCK_50 
+    Info (332119):     0.101               0.000 tick_5000:tick|CLK_OUT 
+    Info (332119):     0.112               0.000 spi2dac:dac|clk_1MHz 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
+    Info: Peak virtual memory: 1246 megabytes
+    Info: Processing ended: Fri Dec 02 17:39:04 2016
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:07
+
+
diff --git a/part_3/ex14/output_files/ex10.sta.summary b/part_3/ex14/output_files/ex10.sta.summary
new file mode 100755
index 0000000..858029e
--- /dev/null
+++ b/part_3/ex14/output_files/ex10.sta.summary
@@ -0,0 +1,149 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'spi2dac:dac|clk_1MHz'
+Slack : -3.834
+TNS   : -62.108
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -3.572
+TNS   : -126.378
+
+Type  : Slow 1100mV 85C Model Setup 'tick_5000:tick|CLK_OUT'
+Slack : -1.476
+TNS   : -13.479
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.212
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'tick_5000:tick|CLK_OUT'
+Slack : 0.528
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'spi2dac:dac|clk_1MHz'
+Slack : 0.731
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -104.886
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2dac:dac|clk_1MHz'
+Slack : -0.394
+TNS   : -10.637
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_5000:tick|CLK_OUT'
+Slack : -0.394
+TNS   : -5.320
+
+Type  : Slow 1100mV 0C Model Setup 'spi2dac:dac|clk_1MHz'
+Slack : -3.877
+TNS   : -63.295
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -3.664
+TNS   : -119.563
+
+Type  : Slow 1100mV 0C Model Setup 'tick_5000:tick|CLK_OUT'
+Slack : -1.546
+TNS   : -13.976
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : -0.131
+TNS   : -1.428
+
+Type  : Slow 1100mV 0C Model Hold 'tick_5000:tick|CLK_OUT'
+Slack : 0.507
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'spi2dac:dac|clk_1MHz'
+Slack : 0.718
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -101.938
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2dac:dac|clk_1MHz'
+Slack : -0.394
+TNS   : -10.531
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_5000:tick|CLK_OUT'
+Slack : -0.394
+TNS   : -5.266
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -2.907
+TNS   : -69.680
+
+Type  : Fast 1100mV 85C Model Setup 'spi2dac:dac|clk_1MHz'
+Slack : -1.889
+TNS   : -28.963
+
+Type  : Fast 1100mV 85C Model Setup 'tick_5000:tick|CLK_OUT'
+Slack : -0.574
+TNS   : -4.704
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.184
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'tick_5000:tick|CLK_OUT'
+Slack : 0.239
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'spi2dac:dac|clk_1MHz'
+Slack : 0.304
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -95.017
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_5000:tick|CLK_OUT'
+Slack : 0.089
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2dac:dac|clk_1MHz'
+Slack : 0.099
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.457
+TNS   : -55.444
+
+Type  : Fast 1100mV 0C Model Setup 'spi2dac:dac|clk_1MHz'
+Slack : -1.822
+TNS   : -27.647
+
+Type  : Fast 1100mV 0C Model Setup 'tick_5000:tick|CLK_OUT'
+Slack : -0.536
+TNS   : -4.307
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : -0.029
+TNS   : -0.033
+
+Type  : Fast 1100mV 0C Model Hold 'tick_5000:tick|CLK_OUT'
+Slack : 0.210
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'spi2dac:dac|clk_1MHz'
+Slack : 0.275
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -100.860
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_5000:tick|CLK_OUT'
+Slack : 0.101
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2dac:dac|clk_1MHz'
+Slack : 0.112
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_3/ex14/rom_data/rom_data.mif b/part_3/ex14/rom_data/rom_data.mif
new file mode 100755
index 0000000..a688b6f
--- /dev/null
+++ b/part_3/ex14/rom_data/rom_data.mif
@@ -0,0 +1,1032 @@
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
+  61 :  31E;
+  62 :  321;
+  63 :  323;
+  64 :  326;
+  65 :  329;
+  66 :  32B;
+  67 :  32E;
+  68 :  330;
+  69 :  333;
+  6A :  335;
+  6B :  338;
+  6C :  33A;
+  6D :  33D;
+  6E :  33F;
+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
+  97 :  398;
+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
+  9E :  3A5;
+  9F :  3A7;
+  A0 :  3A9;
+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
+  CF :  3E8;
+  D0 :  3E9;
+  D1 :  3EA;
+  D2 :  3EB;
+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
+  D6 :  3EE;
+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
+  DB :  3F2;
+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
+  E0 :  3F5;
+  E1 :  3F6;
+  E2 :  3F6;
+  E3 :  3F7;
+  E4 :  3F7;
+  E5 :  3F8;
+  E6 :  3F9;
+  E7 :  3F9;
+  E8 :  3F9;
+  E9 :  3FA;
+  EA :  3FA;
+  EB :  3FB;
+  EC :  3FB;
+  ED :  3FC;
+  EE :  3FC;
+  EF :  3FC;
+  F0 :  3FD;
+  F1 :  3FD;
+  F2 :  3FD;
+  F3 :  3FD;
+  F4 :  3FE;
+  F5 :  3FE;
+  F6 :  3FE;
+  F7 :  3FE;
+  F8 :  3FE;
+  F9 :  3FF;
+  FA :  3FF;
+  FB :  3FF;
+  FC :  3FF;
+  FD :  3FF;
+  FE :  3FF;
+  FF :  3FF;
+ 100 :  3FF;
+ 101 :  3FF;
+ 102 :  3FF;
+ 103 :  3FF;
+ 104 :  3FF;
+ 105 :  3FF;
+ 106 :  3FF;
+ 107 :  3FF;
+ 108 :  3FE;
+ 109 :  3FE;
+ 10A :  3FE;
+ 10B :  3FE;
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+ 3D6 :  17D;
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+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex14/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex14/simulation/modelsim/do_files/tb_spi2dac.do
new file mode 100755
index 0000000..b12a7d7
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/do_files/tb_spi2dac.do
@@ -0,0 +1,17 @@
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex14/simulation/modelsim/ex10.sft b/part_3/ex14/simulation/modelsim/ex10.sft
new file mode 100755
index 0000000..f324fea
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/ex10.sft
@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (Verilog)"
diff --git a/part_3/ex14/simulation/modelsim/ex10.vo b/part_3/ex14/simulation/modelsim/ex10.vo
new file mode 100755
index 0000000..e6d1b12
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/ex10.vo
@@ -0,0 +1,9545 @@
+// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, the Altera Quartus Prime License Agreement,
+// the Altera MegaCore Function License Agreement, or other 
+// applicable license agreement, including, without limitation, 
+// that your use is for the sole purpose of programming logic 
+// devices manufactured by Altera and sold by Altera or its 
+// authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition"
+
+// DATE "12/02/2016 17:39:08"
+
+// 
+// Device: Altera 5CSEMA5F31C6 Package FBGA896
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module ex14 (
+	CLOCK_50,
+	SW,
+	DAC_CS,
+	DAC_SDI,
+	DAC_LD,
+	DAC_SCK,
+	PWM_OUT,
+	HEX0,
+	HEX1,
+	HEX2,
+	HEX3,
+	HEX4);
+input 	CLOCK_50;
+input 	[9:0] SW;
+output 	DAC_CS;
+output 	DAC_SDI;
+output 	DAC_LD;
+output 	DAC_SCK;
+output 	PWM_OUT;
+output 	[6:0] HEX0;
+output 	[6:0] HEX1;
+output 	[6:0] HEX2;
+output 	[6:0] HEX3;
+output 	[6:0] HEX4;
+
+// Design Ports Information
+// DAC_CS	=>  Location: PIN_AD20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_SDI	=>  Location: PIN_AG18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_LD	=>  Location: PIN_AK21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_SCK	=>  Location: PIN_AF20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// PWM_OUT	=>  Location: PIN_AJ20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[0]	=>  Location: PIN_AE26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[1]	=>  Location: PIN_AE27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[2]	=>  Location: PIN_AE28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[3]	=>  Location: PIN_AG27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[4]	=>  Location: PIN_AF28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[5]	=>  Location: PIN_AG28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[6]	=>  Location: PIN_AH28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[0]	=>  Location: PIN_AJ29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[1]	=>  Location: PIN_AH29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[2]	=>  Location: PIN_AH30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[3]	=>  Location: PIN_AG30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[4]	=>  Location: PIN_AF29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[5]	=>  Location: PIN_AF30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[6]	=>  Location: PIN_AD27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[0]	=>  Location: PIN_AB23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[1]	=>  Location: PIN_AE29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[2]	=>  Location: PIN_AD29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[3]	=>  Location: PIN_AC28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[4]	=>  Location: PIN_AD30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[5]	=>  Location: PIN_AC29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[6]	=>  Location: PIN_AC30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[0]	=>  Location: PIN_AD26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[1]	=>  Location: PIN_AC27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[2]	=>  Location: PIN_AD25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[3]	=>  Location: PIN_AC25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[4]	=>  Location: PIN_AB28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[5]	=>  Location: PIN_AB25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[6]	=>  Location: PIN_AB22,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[0]	=>  Location: PIN_AA24,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[1]	=>  Location: PIN_Y23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[2]	=>  Location: PIN_Y24,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[3]	=>  Location: PIN_W22,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[4]	=>  Location: PIN_W24,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[5]	=>  Location: PIN_V23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[6]	=>  Location: PIN_W25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// CLOCK_50	=>  Location: PIN_AF14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[2]	=>  Location: PIN_AF9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[1]	=>  Location: PIN_AC12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[0]	=>  Location: PIN_AB12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[6]	=>  Location: PIN_AE11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[3]	=>  Location: PIN_AF10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[7]	=>  Location: PIN_AC9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[8]	=>  Location: PIN_AD10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[9]	=>  Location: PIN_AE12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[5]	=>  Location: PIN_AD12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[4]	=>  Location: PIN_AD11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \CLOCK_50~input_o ;
+wire \CLOCK_50~inputCLKENA0_outclk ;
+wire \dac|ctr~1_combout ;
+wire \dac|Add0~1_combout ;
+wire \dac|ctr[0]~DUPLICATE_q ;
+wire \dac|Add0~0_combout ;
+wire \dac|ctr[3]~DUPLICATE_q ;
+wire \dac|ctr~0_combout ;
+wire \dac|ctr[2]~DUPLICATE_q ;
+wire \dac|ctr~2_combout ;
+wire \dac|clk_1MHz~0_combout ;
+wire \dac|clk_1MHz~feeder_combout ;
+wire \dac|clk_1MHz~q ;
+wire \dac|state~0_combout ;
+wire \tick|count[15]~DUPLICATE_q ;
+wire \tick|Add0~9_sumout ;
+wire \tick|count[0]~1_combout ;
+wire \tick|Add0~10 ;
+wire \tick|Add0~13_sumout ;
+wire \tick|count[1]~2_combout ;
+wire \tick|Add0~14 ;
+wire \tick|Add0~17_sumout ;
+wire \tick|count[2]~3_combout ;
+wire \tick|Add0~18 ;
+wire \tick|Add0~37_sumout ;
+wire \tick|Add0~38 ;
+wire \tick|Add0~41_sumout ;
+wire \tick|Add0~42 ;
+wire \tick|Add0~45_sumout ;
+wire \tick|count[5]~feeder_combout ;
+wire \tick|count[5]~DUPLICATE_q ;
+wire \tick|Add0~46 ;
+wire \tick|Add0~5_sumout ;
+wire \tick|Add0~6 ;
+wire \tick|Add0~21_sumout ;
+wire \tick|count[7]~4_combout ;
+wire \tick|count[7]~DUPLICATE_q ;
+wire \tick|Add0~22 ;
+wire \tick|Add0~25_sumout ;
+wire \tick|count[8]~5_combout ;
+wire \tick|Add0~26 ;
+wire \tick|Add0~1_sumout ;
+wire \tick|count[9]~0_combout ;
+wire \tick|Add0~2 ;
+wire \tick|Add0~49_sumout ;
+wire \tick|Add0~50 ;
+wire \tick|Add0~53_sumout ;
+wire \tick|Add0~54 ;
+wire \tick|Add0~29_sumout ;
+wire \tick|count[12]~6_combout ;
+wire \tick|Add0~30 ;
+wire \tick|Add0~57_sumout ;
+wire \tick|Add0~58 ;
+wire \tick|Add0~61_sumout ;
+wire \tick|Add0~62 ;
+wire \tick|Add0~33_sumout ;
+wire \tick|Equal0~1_combout ;
+wire \tick|Equal0~0_combout ;
+wire \tick|Equal0~2_combout ;
+wire \tick|Equal0~3_combout ;
+wire \tick|CLK_OUT~feeder_combout ;
+wire \tick|CLK_OUT~q ;
+wire \dac|sr_state.IDLE~0_combout ;
+wire \dac|sr_state.IDLE~q ;
+wire \dac|Selector2~0_combout ;
+wire \dac|sr_state.WAIT_CSB_HIGH~q ;
+wire \dac|sr_state.WAIT_CSB_FALL~0_combout ;
+wire \dac|sr_state.WAIT_CSB_FALL~q ;
+wire \dac|Selector3~0_combout ;
+wire \dac|state~2_combout ;
+wire \dac|state~3_combout ;
+wire \dac|state[3]~DUPLICATE_q ;
+wire \dac|state~1_combout ;
+wire \dac|WideNor0~combout ;
+wire \SW[0]~input_o ;
+wire \fin_address|Add0~1_sumout ;
+wire \SW[1]~input_o ;
+wire \fin_address|Add0~2 ;
+wire \fin_address|Add0~5_sumout ;
+wire \SW[2]~input_o ;
+wire \fin_address|Add0~6 ;
+wire \fin_address|Add0~9_sumout ;
+wire \fin_address|address[2]~feeder_combout ;
+wire \SW[3]~input_o ;
+wire \fin_address|Add0~10 ;
+wire \fin_address|Add0~13_sumout ;
+wire \fin_address|address[3]~feeder_combout ;
+wire \SW[4]~input_o ;
+wire \fin_address|Add0~14 ;
+wire \fin_address|Add0~17_sumout ;
+wire \fin_address|address[4]~feeder_combout ;
+wire \SW[5]~input_o ;
+wire \fin_address|Add0~18 ;
+wire \fin_address|Add0~21_sumout ;
+wire \fin_address|address[5]~feeder_combout ;
+wire \SW[6]~input_o ;
+wire \fin_address|Add0~22 ;
+wire \fin_address|Add0~25_sumout ;
+wire \fin_address|address[6]~feeder_combout ;
+wire \SW[7]~input_o ;
+wire \fin_address|Add0~26 ;
+wire \fin_address|Add0~29_sumout ;
+wire \fin_address|address[7]~feeder_combout ;
+wire \SW[8]~input_o ;
+wire \fin_address|Add0~30 ;
+wire \fin_address|Add0~33_sumout ;
+wire \fin_address|address[8]~feeder_combout ;
+wire \SW[9]~input_o ;
+wire \fin_address|Add0~34 ;
+wire \fin_address|Add0~37_sumout ;
+wire \fin_address|address[9]~feeder_combout ;
+wire \dac|shift_reg[11]~feeder_combout ;
+wire \dac|shift_reg[10]~feeder_combout ;
+wire \dac|shift_reg[9]~feeder_combout ;
+wire \dac|shift_reg[8]~feeder_combout ;
+wire \dac|shift_reg[7]~feeder_combout ;
+wire \dac|shift_reg[6]~feeder_combout ;
+wire \dac|shift_reg[5]~feeder_combout ;
+wire \dac|shift_reg[4]~feeder_combout ;
+wire \dac|shift_reg[3]~feeder_combout ;
+wire \dac|shift_reg~4_combout ;
+wire \dac|always5~0_combout ;
+wire \dac|shift_reg~3_combout ;
+wire \dac|shift_reg~2_combout ;
+wire \dac|shift_reg~1_combout ;
+wire \dac|shift_reg~0_combout ;
+wire \dac|Equal2~0_combout ;
+wire \dac|dac_sck~combout ;
+wire \p|count[0]~0_combout ;
+wire \p|Add0~33_sumout ;
+wire \p|Add0~34 ;
+wire \p|Add0~29_sumout ;
+wire \p|Add0~30 ;
+wire \p|Add0~25_sumout ;
+wire \p|Add0~26 ;
+wire \p|Add0~21_sumout ;
+wire \p|Add0~22 ;
+wire \p|Add0~17_sumout ;
+wire \p|Add0~18 ;
+wire \p|Add0~13_sumout ;
+wire \p|Add0~14 ;
+wire \p|Add0~9_sumout ;
+wire \p|Add0~10 ;
+wire \p|Add0~5_sumout ;
+wire \p|Add0~6 ;
+wire \p|Add0~1_sumout ;
+wire \p|LessThan0~0_combout ;
+wire \p|d[6]~feeder_combout ;
+wire \p|count[0]~DUPLICATE_q ;
+wire \p|LessThan0~2_combout ;
+wire \p|LessThan0~3_combout ;
+wire \p|LessThan0~1_combout ;
+wire \p|LessThan0~4_combout ;
+wire \p|LessThan0~5_combout ;
+wire \p|pwm_out~q ;
+wire \mult|lpm_mult_component|mult_core|romout[1][17]~5_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[0][17]~4_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[0][16]~3_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[0][15]~2_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[0][14]~1_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[1][9]~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ;
+wire \bcd|A2|WideOr3~0_combout ;
+wire \bcd|A2|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ;
+wire \bcd|A2|WideOr1~0_combout ;
+wire \bcd|A4|WideOr1~0_combout ;
+wire \bcd|A4|WideOr3~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ;
+wire \bcd|A4|WideOr2~0_combout ;
+wire \bcd|A6|WideOr3~0_combout ;
+wire \bcd|A6|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ;
+wire \bcd|A6|WideOr1~0_combout ;
+wire \bcd|A8|WideOr2~0_combout ;
+wire \bcd|A8|WideOr3~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ;
+wire \bcd|A8|WideOr1~0_combout ;
+wire \bcd|A11|WideOr1~0_combout ;
+wire \bcd|A11|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ;
+wire \bcd|A11|WideOr3~0_combout ;
+wire \bcd|A14|WideOr3~0_combout ;
+wire \bcd|A14|WideOr2~0_combout ;
+wire \bcd|A14|WideOr1~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ;
+wire \bcd|A17|WideOr2~0_combout ;
+wire \bcd|A17|WideOr3~0_combout ;
+wire \bcd|A17|WideOr1~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ;
+wire \bcd|A21|WideOr1~0_combout ;
+wire \bcd|A21|WideOr3~0_combout ;
+wire \bcd|A21|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ;
+wire \bcd|A25|WideOr1~0_combout ;
+wire \bcd|A25|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ;
+wire \bcd|A25|WideOr3~0_combout ;
+wire \bcd|A29|WideOr3~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ;
+wire \bcd|A29|WideOr2~0_combout ;
+wire \bcd|A29|WideOr1~0_combout ;
+wire \h0|WideOr6~0_combout ;
+wire \h0|WideOr5~0_combout ;
+wire \h0|WideOr4~0_combout ;
+wire \h0|WideOr3~0_combout ;
+wire \h0|WideOr2~0_combout ;
+wire \h0|WideOr1~0_combout ;
+wire \h0|WideOr0~0_combout ;
+wire \bcd|A7|WideOr2~0_combout ;
+wire \bcd|A7|WideOr3~0_combout ;
+wire \bcd|A8|WideOr0~0_combout ;
+wire \bcd|A7|WideOr1~0_combout ;
+wire \bcd|A10|WideOr1~0_combout ;
+wire \bcd|A11|WideOr0~0_combout ;
+wire \bcd|A10|WideOr3~0_combout ;
+wire \bcd|A10|WideOr2~0_combout ;
+wire \bcd|A13|WideOr3~0_combout ;
+wire \bcd|A13|WideOr1~0_combout ;
+wire \bcd|A13|WideOr2~0_combout ;
+wire \bcd|A14|WideOr0~0_combout ;
+wire \bcd|A16|WideOr3~0_combout ;
+wire \bcd|A16|WideOr1~0_combout ;
+wire \bcd|A16|WideOr2~0_combout ;
+wire \bcd|A17|WideOr0~0_combout ;
+wire \bcd|A20|WideOr3~0_combout ;
+wire \bcd|A20|WideOr2~0_combout ;
+wire \bcd|A20|WideOr1~0_combout ;
+wire \bcd|A21|WideOr0~0_combout ;
+wire \bcd|A24|WideOr3~0_combout ;
+wire \bcd|A25|WideOr0~0_combout ;
+wire \bcd|A24|WideOr1~0_combout ;
+wire \bcd|A24|WideOr2~0_combout ;
+wire \bcd|A28|WideOr1~0_combout ;
+wire \bcd|A28|WideOr3~0_combout ;
+wire \bcd|A29|WideOr0~0_combout ;
+wire \bcd|A28|WideOr2~0_combout ;
+wire \h1|WideOr6~0_combout ;
+wire \h1|WideOr5~0_combout ;
+wire \h1|WideOr4~0_combout ;
+wire \h1|WideOr3~0_combout ;
+wire \h1|WideOr2~0_combout ;
+wire \h1|WideOr1~0_combout ;
+wire \h1|WideOr0~0_combout ;
+wire \bcd|A1|WideOr0~0_combout ;
+wire \bcd|A2|WideOr0~0_combout ;
+wire \bcd|A6|WideOr0~0_combout ;
+wire \bcd|A4|WideOr0~0_combout ;
+wire \bcd|A15|WideOr2~0_combout ;
+wire \bcd|A16|WideOr0~0_combout ;
+wire \bcd|A15|WideOr3~0_combout ;
+wire \bcd|A15|WideOr1~0_combout ;
+wire \bcd|A19|WideOr1~0_combout ;
+wire \bcd|A19|WideOr3~0_combout ;
+wire \bcd|A19|WideOr2~0_combout ;
+wire \bcd|A20|WideOr0~0_combout ;
+wire \bcd|A23|WideOr2~0_combout ;
+wire \bcd|A23|WideOr3~0_combout ;
+wire \bcd|A24|WideOr0~0_combout ;
+wire \bcd|A23|WideOr1~0_combout ;
+wire \bcd|A27|WideOr1~0_combout ;
+wire \bcd|A28|WideOr0~0_combout ;
+wire \bcd|A27|WideOr2~0_combout ;
+wire \bcd|A27|WideOr3~0_combout ;
+wire \h2|WideOr6~0_combout ;
+wire \h2|WideOr5~0_combout ;
+wire \h2|WideOr4~0_combout ;
+wire \h2|WideOr3~0_combout ;
+wire \h2|WideOr2~0_combout ;
+wire \h2|WideOr1~0_combout ;
+wire \h2|WideOr0~0_combout ;
+wire \bcd|A7|WideOr0~0_combout ;
+wire \bcd|A5|WideOr0~0_combout ;
+wire \bcd|A10|WideOr0~0_combout ;
+wire \bcd|A12|WideOr0~0_combout ;
+wire \bcd|A15|WideOr0~0_combout ;
+wire \bcd|A23|WideOr0~0_combout ;
+wire \bcd|A19|WideOr0~0_combout ;
+wire \bcd|A26|Decoder0~2_combout ;
+wire \bcd|A26|Decoder0~0_combout ;
+wire \bcd|A26|WideOr2~combout ;
+wire \bcd|A27|WideOr0~0_combout ;
+wire \bcd|A26|Decoder0~3_combout ;
+wire \bcd|A26|WideOr1~combout ;
+wire \bcd|A26|Decoder0~1_combout ;
+wire \bcd|A26|WideOr3~0_combout ;
+wire \h3|WideOr6~0_combout ;
+wire \h3|WideOr5~0_combout ;
+wire \h3|WideOr4~0_combout ;
+wire \h3|WideOr3~0_combout ;
+wire \h3|WideOr2~0_combout ;
+wire \h3|WideOr1~0_combout ;
+wire \h3|WideOr0~0_combout ;
+wire \bcd|A26|Decoder0~4_combout ;
+wire \bcd|A22|WideOr0~0_combout ;
+wire \h4|Decoder0~0_combout ;
+wire \bcd|A13|WideOr0~0_combout ;
+wire \h4|Decoder0~2_combout ;
+wire \bcd|A26|WideOr0~combout ;
+wire \h4|Decoder0~1_combout ;
+wire [9:0] \p|count ;
+wire [9:0] \rom|altsyncram_component|auto_generated|q_a ;
+wire [15:0] \dac|shift_reg ;
+wire [15:0] \tick|count ;
+wire [4:0] \dac|state ;
+wire [9:0] \p|d ;
+wire [4:0] \dac|ctr ;
+wire [9:0] \fin_address|address ;
+
+wire [9:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
+
+assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
+assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
+assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
+assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
+assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
+assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
+assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
+assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];
+assign \rom|altsyncram_component|auto_generated|q_a [8] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8];
+assign \rom|altsyncram_component|auto_generated|q_a [9] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [9];
+
+// Location: IOOBUF_X82_Y0_N42
+cyclonev_io_obuf \DAC_CS~output (
+	.i(\dac|WideNor0~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_CS),
+	.obar());
+// synopsys translate_off
+defparam \DAC_CS~output .bus_hold = "false";
+defparam \DAC_CS~output .open_drain_output = "false";
+defparam \DAC_CS~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X58_Y0_N76
+cyclonev_io_obuf \DAC_SDI~output (
+	.i(\dac|shift_reg [15]),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_SDI),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SDI~output .bus_hold = "false";
+defparam \DAC_SDI~output .open_drain_output = "false";
+defparam \DAC_SDI~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X68_Y0_N36
+cyclonev_io_obuf \DAC_LD~output (
+	.i(!\dac|Equal2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_LD),
+	.obar());
+// synopsys translate_off
+defparam \DAC_LD~output .bus_hold = "false";
+defparam \DAC_LD~output .open_drain_output = "false";
+defparam \DAC_LD~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N2
+cyclonev_io_obuf \DAC_SCK~output (
+	.i(!\dac|dac_sck~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_SCK),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SCK~output .bus_hold = "false";
+defparam \DAC_SCK~output .open_drain_output = "false";
+defparam \DAC_SCK~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N36
+cyclonev_io_obuf \PWM_OUT~output (
+	.i(\p|pwm_out~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(PWM_OUT),
+	.obar());
+// synopsys translate_off
+defparam \PWM_OUT~output .bus_hold = "false";
+defparam \PWM_OUT~output .open_drain_output = "false";
+defparam \PWM_OUT~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N39
+cyclonev_io_obuf \HEX0[0]~output (
+	.i(\h0|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[0]~output .bus_hold = "false";
+defparam \HEX0[0]~output .open_drain_output = "false";
+defparam \HEX0[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N79
+cyclonev_io_obuf \HEX0[1]~output (
+	.i(\h0|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[1]~output .bus_hold = "false";
+defparam \HEX0[1]~output .open_drain_output = "false";
+defparam \HEX0[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N96
+cyclonev_io_obuf \HEX0[2]~output (
+	.i(\h0|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[2]~output .bus_hold = "false";
+defparam \HEX0[2]~output .open_drain_output = "false";
+defparam \HEX0[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N79
+cyclonev_io_obuf \HEX0[3]~output (
+	.i(\h0|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[3]~output .bus_hold = "false";
+defparam \HEX0[3]~output .open_drain_output = "false";
+defparam \HEX0[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N56
+cyclonev_io_obuf \HEX0[4]~output (
+	.i(\h0|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[4]~output .bus_hold = "false";
+defparam \HEX0[4]~output .open_drain_output = "false";
+defparam \HEX0[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N39
+cyclonev_io_obuf \HEX0[5]~output (
+	.i(\h0|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[5]~output .bus_hold = "false";
+defparam \HEX0[5]~output .open_drain_output = "false";
+defparam \HEX0[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N96
+cyclonev_io_obuf \HEX0[6]~output (
+	.i(!\h0|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[6]~output .bus_hold = "false";
+defparam \HEX0[6]~output .open_drain_output = "false";
+defparam \HEX0[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y6_N39
+cyclonev_io_obuf \HEX1[0]~output (
+	.i(!\h1|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[0]~output .bus_hold = "false";
+defparam \HEX1[0]~output .open_drain_output = "false";
+defparam \HEX1[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y6_N56
+cyclonev_io_obuf \HEX1[1]~output (
+	.i(\h1|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[1]~output .bus_hold = "false";
+defparam \HEX1[1]~output .open_drain_output = "false";
+defparam \HEX1[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N39
+cyclonev_io_obuf \HEX1[2]~output (
+	.i(\h1|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[2]~output .bus_hold = "false";
+defparam \HEX1[2]~output .open_drain_output = "false";
+defparam \HEX1[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N56
+cyclonev_io_obuf \HEX1[3]~output (
+	.i(!\h1|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[3]~output .bus_hold = "false";
+defparam \HEX1[3]~output .open_drain_output = "false";
+defparam \HEX1[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N39
+cyclonev_io_obuf \HEX1[4]~output (
+	.i(!\h1|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[4]~output .bus_hold = "false";
+defparam \HEX1[4]~output .open_drain_output = "false";
+defparam \HEX1[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N56
+cyclonev_io_obuf \HEX1[5]~output (
+	.i(!\h1|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[5]~output .bus_hold = "false";
+defparam \HEX1[5]~output .open_drain_output = "false";
+defparam \HEX1[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N56
+cyclonev_io_obuf \HEX1[6]~output (
+	.i(!\h1|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[6]~output .bus_hold = "false";
+defparam \HEX1[6]~output .open_drain_output = "false";
+defparam \HEX1[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N22
+cyclonev_io_obuf \HEX2[0]~output (
+	.i(!\h2|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[0]~output .bus_hold = "false";
+defparam \HEX2[0]~output .open_drain_output = "false";
+defparam \HEX2[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y23_N39
+cyclonev_io_obuf \HEX2[1]~output (
+	.i(\h2|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[1]~output .bus_hold = "false";
+defparam \HEX2[1]~output .open_drain_output = "false";
+defparam \HEX2[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y23_N56
+cyclonev_io_obuf \HEX2[2]~output (
+	.i(\h2|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[2]~output .bus_hold = "false";
+defparam \HEX2[2]~output .open_drain_output = "false";
+defparam \HEX2[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N79
+cyclonev_io_obuf \HEX2[3]~output (
+	.i(!\h2|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[3]~output .bus_hold = "false";
+defparam \HEX2[3]~output .open_drain_output = "false";
+defparam \HEX2[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y25_N39
+cyclonev_io_obuf \HEX2[4]~output (
+	.i(!\h2|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[4]~output .bus_hold = "false";
+defparam \HEX2[4]~output .open_drain_output = "false";
+defparam \HEX2[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N96
+cyclonev_io_obuf \HEX2[5]~output (
+	.i(!\h2|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[5]~output .bus_hold = "false";
+defparam \HEX2[5]~output .open_drain_output = "false";
+defparam \HEX2[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y25_N56
+cyclonev_io_obuf \HEX2[6]~output (
+	.i(!\h2|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[6]~output .bus_hold = "false";
+defparam \HEX2[6]~output .open_drain_output = "false";
+defparam \HEX2[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N5
+cyclonev_io_obuf \HEX3[0]~output (
+	.i(!\h3|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[0]~output .bus_hold = "false";
+defparam \HEX3[0]~output .open_drain_output = "false";
+defparam \HEX3[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N22
+cyclonev_io_obuf \HEX3[1]~output (
+	.i(\h3|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[1]~output .bus_hold = "false";
+defparam \HEX3[1]~output .open_drain_output = "false";
+defparam \HEX3[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N45
+cyclonev_io_obuf \HEX3[2]~output (
+	.i(\h3|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[2]~output .bus_hold = "false";
+defparam \HEX3[2]~output .open_drain_output = "false";
+defparam \HEX3[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N62
+cyclonev_io_obuf \HEX3[3]~output (
+	.i(!\h3|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[3]~output .bus_hold = "false";
+defparam \HEX3[3]~output .open_drain_output = "false";
+defparam \HEX3[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y21_N39
+cyclonev_io_obuf \HEX3[4]~output (
+	.i(!\h3|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[4]~output .bus_hold = "false";
+defparam \HEX3[4]~output .open_drain_output = "false";
+defparam \HEX3[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N62
+cyclonev_io_obuf \HEX3[5]~output (
+	.i(!\h3|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[5]~output .bus_hold = "false";
+defparam \HEX3[5]~output .open_drain_output = "false";
+defparam \HEX3[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N5
+cyclonev_io_obuf \HEX3[6]~output (
+	.i(!\h3|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[6]~output .bus_hold = "false";
+defparam \HEX3[6]~output .open_drain_output = "false";
+defparam \HEX3[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N45
+cyclonev_io_obuf \HEX4[0]~output (
+	.i(\h4|Decoder0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[0]~output .bus_hold = "false";
+defparam \HEX4[0]~output .open_drain_output = "false";
+defparam \HEX4[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N5
+cyclonev_io_obuf \HEX4[1]~output (
+	.i(gnd),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[1]~output .bus_hold = "false";
+defparam \HEX4[1]~output .open_drain_output = "false";
+defparam \HEX4[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N22
+cyclonev_io_obuf \HEX4[2]~output (
+	.i(\h4|Decoder0~2_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[2]~output .bus_hold = "false";
+defparam \HEX4[2]~output .open_drain_output = "false";
+defparam \HEX4[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N22
+cyclonev_io_obuf \HEX4[3]~output (
+	.i(\h4|Decoder0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[3]~output .bus_hold = "false";
+defparam \HEX4[3]~output .open_drain_output = "false";
+defparam \HEX4[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N22
+cyclonev_io_obuf \HEX4[4]~output (
+	.i(!\bcd|A26|WideOr0~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[4]~output .bus_hold = "false";
+defparam \HEX4[4]~output .open_drain_output = "false";
+defparam \HEX4[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N5
+cyclonev_io_obuf \HEX4[5]~output (
+	.i(!\h4|Decoder0~1_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[5]~output .bus_hold = "false";
+defparam \HEX4[5]~output .open_drain_output = "false";
+defparam \HEX4[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N45
+cyclonev_io_obuf \HEX4[6]~output (
+	.i(\bcd|A22|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[6]~output .bus_hold = "false";
+defparam \HEX4[6]~output .open_drain_output = "false";
+defparam \HEX4[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X32_Y0_N1
+cyclonev_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G6
+cyclonev_clkena \CLOCK_50~inputCLKENA0 (
+	.inclk(\CLOCK_50~input_o ),
+	.ena(vcc),
+	.outclk(\CLOCK_50~inputCLKENA0_outclk ),
+	.enaout());
+// synopsys translate_off
+defparam \CLOCK_50~inputCLKENA0 .clock_type = "global clock";
+defparam \CLOCK_50~inputCLKENA0 .disable_mode = "low";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_mode = "always enabled";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_power_up = "high";
+defparam \CLOCK_50~inputCLKENA0 .test_syn = "high";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N25
+dffeas \dac|ctr[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|ctr[2] .is_wysiwyg = "true";
+defparam \dac|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N45
+cyclonev_lcell_comb \dac|ctr~1 (
+// Equation(s):
+// \dac|ctr~1_combout  = ( \dac|ctr [1] & ( !\dac|ctr [0] ) ) # ( !\dac|ctr [1] & ( (!\dac|ctr [0] & (((\dac|ctr [4]) # (\dac|ctr [2])) # (\dac|ctr [3]))) ) )
+
+	.dataa(!\dac|ctr [3]),
+	.datab(!\dac|ctr [2]),
+	.datac(!\dac|ctr [4]),
+	.datad(!\dac|ctr [0]),
+	.datae(gnd),
+	.dataf(!\dac|ctr [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|ctr~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|ctr~1 .extended_lut = "off";
+defparam \dac|ctr~1 .lut_mask = 64'h7F007F00FF00FF00;
+defparam \dac|ctr~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N46
+dffeas \dac|ctr[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|ctr[0] .is_wysiwyg = "true";
+defparam \dac|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N51
+cyclonev_lcell_comb \dac|Add0~1 (
+// Equation(s):
+// \dac|Add0~1_combout  = ( \dac|ctr [1] & ( \dac|ctr [3] ) ) # ( !\dac|ctr [1] & ( !\dac|ctr [3] $ (((\dac|ctr [0]) # (\dac|ctr[2]~DUPLICATE_q ))) ) )
+
+	.dataa(!\dac|ctr[2]~DUPLICATE_q ),
+	.datab(gnd),
+	.datac(!\dac|ctr [0]),
+	.datad(!\dac|ctr [3]),
+	.datae(gnd),
+	.dataf(!\dac|ctr [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Add0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Add0~1 .extended_lut = "off";
+defparam \dac|Add0~1 .lut_mask = 64'hA05FA05F00FF00FF;
+defparam \dac|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N53
+dffeas \dac|ctr[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|Add0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|ctr[3] .is_wysiwyg = "true";
+defparam \dac|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N47
+dffeas \dac|ctr[0]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|ctr[0]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|ctr[0]~DUPLICATE .is_wysiwyg = "true";
+defparam \dac|ctr[0]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N42
+cyclonev_lcell_comb \dac|Add0~0 (
+// Equation(s):
+// \dac|Add0~0_combout  = ( \dac|ctr[0]~DUPLICATE_q  & ( \dac|ctr [4] ) ) # ( !\dac|ctr[0]~DUPLICATE_q  & ( !\dac|ctr [4] $ ((((\dac|ctr [1]) # (\dac|ctr [2])) # (\dac|ctr [3]))) ) )
+
+	.dataa(!\dac|ctr [3]),
+	.datab(!\dac|ctr [2]),
+	.datac(!\dac|ctr [1]),
+	.datad(!\dac|ctr [4]),
+	.datae(gnd),
+	.dataf(!\dac|ctr[0]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Add0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Add0~0 .extended_lut = "off";
+defparam \dac|Add0~0 .lut_mask = 64'h807F807F00FF00FF;
+defparam \dac|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N44
+dffeas \dac|ctr[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|ctr[4] .is_wysiwyg = "true";
+defparam \dac|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N52
+dffeas \dac|ctr[3]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|Add0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|ctr[3]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|ctr[3]~DUPLICATE .is_wysiwyg = "true";
+defparam \dac|ctr[3]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N24
+cyclonev_lcell_comb \dac|ctr~0 (
+// Equation(s):
+// \dac|ctr~0_combout  = ( \dac|ctr [2] & ( \dac|ctr[0]~DUPLICATE_q  ) ) # ( \dac|ctr [2] & ( !\dac|ctr[0]~DUPLICATE_q  & ( \dac|ctr [1] ) ) ) # ( !\dac|ctr [2] & ( !\dac|ctr[0]~DUPLICATE_q  & ( (!\dac|ctr [1] & ((\dac|ctr[3]~DUPLICATE_q ) # (\dac|ctr [4]))) 
+// ) ) )
+
+	.dataa(gnd),
+	.datab(!\dac|ctr [4]),
+	.datac(!\dac|ctr [1]),
+	.datad(!\dac|ctr[3]~DUPLICATE_q ),
+	.datae(!\dac|ctr [2]),
+	.dataf(!\dac|ctr[0]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|ctr~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|ctr~0 .extended_lut = "off";
+defparam \dac|ctr~0 .lut_mask = 64'h30F00F0F0000FFFF;
+defparam \dac|ctr~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N26
+dffeas \dac|ctr[2]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|ctr[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|ctr[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \dac|ctr[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N48
+cyclonev_lcell_comb \dac|ctr~2 (
+// Equation(s):
+// \dac|ctr~2_combout  = ( \dac|ctr[0]~DUPLICATE_q  & ( \dac|ctr [1] ) ) # ( !\dac|ctr[0]~DUPLICATE_q  & ( (!\dac|ctr [1] & (((\dac|ctr [3]) # (\dac|ctr [4])) # (\dac|ctr[2]~DUPLICATE_q ))) ) )
+
+	.dataa(!\dac|ctr[2]~DUPLICATE_q ),
+	.datab(!\dac|ctr [4]),
+	.datac(!\dac|ctr [3]),
+	.datad(!\dac|ctr [1]),
+	.datae(gnd),
+	.dataf(!\dac|ctr[0]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|ctr~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|ctr~2 .extended_lut = "off";
+defparam \dac|ctr~2 .lut_mask = 64'h7F007F0000FF00FF;
+defparam \dac|ctr~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N50
+dffeas \dac|ctr[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|ctr[1] .is_wysiwyg = "true";
+defparam \dac|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N12
+cyclonev_lcell_comb \dac|clk_1MHz~0 (
+// Equation(s):
+// \dac|clk_1MHz~0_combout  = ( \dac|ctr[3]~DUPLICATE_q  & ( \dac|clk_1MHz~q  ) ) # ( !\dac|ctr[3]~DUPLICATE_q  & ( \dac|clk_1MHz~q  & ( (((\dac|ctr[0]~DUPLICATE_q ) # (\dac|ctr[2]~DUPLICATE_q )) # (\dac|ctr [4])) # (\dac|ctr [1]) ) ) ) # ( 
+// !\dac|ctr[3]~DUPLICATE_q  & ( !\dac|clk_1MHz~q  & ( (!\dac|ctr [1] & (!\dac|ctr [4] & (!\dac|ctr[2]~DUPLICATE_q  & !\dac|ctr[0]~DUPLICATE_q ))) ) ) )
+
+	.dataa(!\dac|ctr [1]),
+	.datab(!\dac|ctr [4]),
+	.datac(!\dac|ctr[2]~DUPLICATE_q ),
+	.datad(!\dac|ctr[0]~DUPLICATE_q ),
+	.datae(!\dac|ctr[3]~DUPLICATE_q ),
+	.dataf(!\dac|clk_1MHz~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|clk_1MHz~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|clk_1MHz~0 .extended_lut = "off";
+defparam \dac|clk_1MHz~0 .lut_mask = 64'h800000007FFFFFFF;
+defparam \dac|clk_1MHz~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N21
+cyclonev_lcell_comb \dac|clk_1MHz~feeder (
+// Equation(s):
+// \dac|clk_1MHz~feeder_combout  = ( \dac|clk_1MHz~0_combout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dac|clk_1MHz~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|clk_1MHz~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|clk_1MHz~feeder .extended_lut = "off";
+defparam \dac|clk_1MHz~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|clk_1MHz~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N23
+dffeas \dac|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\dac|clk_1MHz~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|clk_1MHz .is_wysiwyg = "true";
+defparam \dac|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N21
+cyclonev_lcell_comb \dac|state~0 (
+// Equation(s):
+// \dac|state~0_combout  = ( \dac|state [0] & ( (!\dac|state[3]~DUPLICATE_q  & (\dac|state [4] & ((\dac|state [2]) # (\dac|state [1])))) # (\dac|state[3]~DUPLICATE_q  & (!\dac|state [4] $ (((!\dac|state [1]) # (!\dac|state [2]))))) ) ) # ( !\dac|state [0] & 
+// ( \dac|state [4] ) )
+
+	.dataa(!\dac|state [4]),
+	.datab(!\dac|state[3]~DUPLICATE_q ),
+	.datac(!\dac|state [1]),
+	.datad(!\dac|state [2]),
+	.datae(gnd),
+	.dataf(!\dac|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state~0 .extended_lut = "off";
+defparam \dac|state~0 .lut_mask = 64'h5555555515561556;
+defparam \dac|state~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N50
+dffeas \dac|state[4] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[4] .is_wysiwyg = "true";
+defparam \dac|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N47
+dffeas \tick|count[15]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[15]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[15]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[15]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N0
+cyclonev_lcell_comb \tick|Add0~9 (
+// Equation(s):
+// \tick|Add0~9_sumout  = SUM(( !\tick|count [0] ) + ( VCC ) + ( !VCC ))
+// \tick|Add0~10  = CARRY(( !\tick|count [0] ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [0]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~9_sumout ),
+	.cout(\tick|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~9 .extended_lut = "off";
+defparam \tick|Add0~9 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N3
+cyclonev_lcell_comb \tick|count[0]~1 (
+// Equation(s):
+// \tick|count[0]~1_combout  = ( !\tick|Add0~9_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[0]~1 .extended_lut = "off";
+defparam \tick|count[0]~1 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N5
+dffeas \tick|count[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[0]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[0] .is_wysiwyg = "true";
+defparam \tick|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N3
+cyclonev_lcell_comb \tick|Add0~13 (
+// Equation(s):
+// \tick|Add0~13_sumout  = SUM(( !\tick|count [1] ) + ( VCC ) + ( \tick|Add0~10  ))
+// \tick|Add0~14  = CARRY(( !\tick|count [1] ) + ( VCC ) + ( \tick|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [1]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~13_sumout ),
+	.cout(\tick|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~13 .extended_lut = "off";
+defparam \tick|Add0~13 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N15
+cyclonev_lcell_comb \tick|count[1]~2 (
+// Equation(s):
+// \tick|count[1]~2_combout  = ( !\tick|Add0~13_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[1]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[1]~2 .extended_lut = "off";
+defparam \tick|count[1]~2 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[1]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N17
+dffeas \tick|count[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[1]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[1] .is_wysiwyg = "true";
+defparam \tick|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N6
+cyclonev_lcell_comb \tick|Add0~17 (
+// Equation(s):
+// \tick|Add0~17_sumout  = SUM(( !\tick|count [2] ) + ( VCC ) + ( \tick|Add0~14  ))
+// \tick|Add0~18  = CARRY(( !\tick|count [2] ) + ( VCC ) + ( \tick|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\tick|count [2]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~17_sumout ),
+	.cout(\tick|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~17 .extended_lut = "off";
+defparam \tick|Add0~17 .lut_mask = 64'h000000000000F0F0;
+defparam \tick|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N48
+cyclonev_lcell_comb \tick|count[2]~3 (
+// Equation(s):
+// \tick|count[2]~3_combout  = ( !\tick|Add0~17_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[2]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[2]~3 .extended_lut = "off";
+defparam \tick|count[2]~3 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[2]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N50
+dffeas \tick|count[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[2]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[2] .is_wysiwyg = "true";
+defparam \tick|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N9
+cyclonev_lcell_comb \tick|Add0~37 (
+// Equation(s):
+// \tick|Add0~37_sumout  = SUM(( \tick|count [3] ) + ( VCC ) + ( \tick|Add0~18  ))
+// \tick|Add0~38  = CARRY(( \tick|count [3] ) + ( VCC ) + ( \tick|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~37_sumout ),
+	.cout(\tick|Add0~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~37 .extended_lut = "off";
+defparam \tick|Add0~37 .lut_mask = 64'h00000000000000FF;
+defparam \tick|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N10
+dffeas \tick|count[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~37_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[3] .is_wysiwyg = "true";
+defparam \tick|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N12
+cyclonev_lcell_comb \tick|Add0~41 (
+// Equation(s):
+// \tick|Add0~41_sumout  = SUM(( \tick|count [4] ) + ( VCC ) + ( \tick|Add0~38  ))
+// \tick|Add0~42  = CARRY(( \tick|count [4] ) + ( VCC ) + ( \tick|Add0~38  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [4]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~41_sumout ),
+	.cout(\tick|Add0~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~41 .extended_lut = "off";
+defparam \tick|Add0~41 .lut_mask = 64'h00000000000000FF;
+defparam \tick|Add0~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N50
+dffeas \tick|count[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\tick|Add0~41_sumout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[4] .is_wysiwyg = "true";
+defparam \tick|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N15
+cyclonev_lcell_comb \tick|Add0~45 (
+// Equation(s):
+// \tick|Add0~45_sumout  = SUM(( \tick|count[5]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~42  ))
+// \tick|Add0~46  = CARRY(( \tick|count[5]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~42  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count[5]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~45_sumout ),
+	.cout(\tick|Add0~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~45 .extended_lut = "off";
+defparam \tick|Add0~45 .lut_mask = 64'h00000000000000FF;
+defparam \tick|Add0~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N9
+cyclonev_lcell_comb \tick|count[5]~feeder (
+// Equation(s):
+// \tick|count[5]~feeder_combout  = ( \tick|Add0~45_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[5]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[5]~feeder .extended_lut = "off";
+defparam \tick|count[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \tick|count[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N11
+dffeas \tick|count[5]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[5]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[5]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[5]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N18
+cyclonev_lcell_comb \tick|Add0~5 (
+// Equation(s):
+// \tick|Add0~5_sumout  = SUM(( \tick|count [6] ) + ( VCC ) + ( \tick|Add0~46  ))
+// \tick|Add0~6  = CARRY(( \tick|count [6] ) + ( VCC ) + ( \tick|Add0~46  ))
+
+	.dataa(gnd),
+	.datab(!\tick|count [6]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~5_sumout ),
+	.cout(\tick|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~5 .extended_lut = "off";
+defparam \tick|Add0~5 .lut_mask = 64'h0000000000003333;
+defparam \tick|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N19
+dffeas \tick|count[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[6] .is_wysiwyg = "true";
+defparam \tick|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N21
+cyclonev_lcell_comb \tick|Add0~21 (
+// Equation(s):
+// \tick|Add0~21_sumout  = SUM(( !\tick|count[7]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~6  ))
+// \tick|Add0~22  = CARRY(( !\tick|count[7]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count[7]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~21_sumout ),
+	.cout(\tick|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~21 .extended_lut = "off";
+defparam \tick|Add0~21 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N57
+cyclonev_lcell_comb \tick|count[7]~4 (
+// Equation(s):
+// \tick|count[7]~4_combout  = ( !\tick|Add0~21_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\tick|Add0~21_sumout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[7]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[7]~4 .extended_lut = "off";
+defparam \tick|count[7]~4 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \tick|count[7]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N59
+dffeas \tick|count[7]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[7]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[7]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[7]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[7]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N24
+cyclonev_lcell_comb \tick|Add0~25 (
+// Equation(s):
+// \tick|Add0~25_sumout  = SUM(( !\tick|count [8] ) + ( VCC ) + ( \tick|Add0~22  ))
+// \tick|Add0~26  = CARRY(( !\tick|count [8] ) + ( VCC ) + ( \tick|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(!\tick|count [8]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~25_sumout ),
+	.cout(\tick|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~25 .extended_lut = "off";
+defparam \tick|Add0~25 .lut_mask = 64'h000000000000CCCC;
+defparam \tick|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N12
+cyclonev_lcell_comb \tick|count[8]~5 (
+// Equation(s):
+// \tick|count[8]~5_combout  = ( !\tick|Add0~25_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[8]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[8]~5 .extended_lut = "off";
+defparam \tick|count[8]~5 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[8]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N14
+dffeas \tick|count[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[8]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[8] .is_wysiwyg = "true";
+defparam \tick|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N27
+cyclonev_lcell_comb \tick|Add0~1 (
+// Equation(s):
+// \tick|Add0~1_sumout  = SUM(( !\tick|count [9] ) + ( VCC ) + ( \tick|Add0~26  ))
+// \tick|Add0~2  = CARRY(( !\tick|count [9] ) + ( VCC ) + ( \tick|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [9]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~1_sumout ),
+	.cout(\tick|Add0~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~1 .extended_lut = "off";
+defparam \tick|Add0~1 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N54
+cyclonev_lcell_comb \tick|count[9]~0 (
+// Equation(s):
+// \tick|count[9]~0_combout  = ( !\tick|Add0~1_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[9]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[9]~0 .extended_lut = "off";
+defparam \tick|count[9]~0 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[9]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N56
+dffeas \tick|count[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[9]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[9] .is_wysiwyg = "true";
+defparam \tick|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N30
+cyclonev_lcell_comb \tick|Add0~49 (
+// Equation(s):
+// \tick|Add0~49_sumout  = SUM(( \tick|count [10] ) + ( VCC ) + ( \tick|Add0~2  ))
+// \tick|Add0~50  = CARRY(( \tick|count [10] ) + ( VCC ) + ( \tick|Add0~2  ))
+
+	.dataa(gnd),
+	.datab(!\tick|count [10]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~49_sumout ),
+	.cout(\tick|Add0~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~49 .extended_lut = "off";
+defparam \tick|Add0~49 .lut_mask = 64'h0000000000003333;
+defparam \tick|Add0~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N32
+dffeas \tick|count[10] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~49_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[10] .is_wysiwyg = "true";
+defparam \tick|count[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N33
+cyclonev_lcell_comb \tick|Add0~53 (
+// Equation(s):
+// \tick|Add0~53_sumout  = SUM(( \tick|count [11] ) + ( VCC ) + ( \tick|Add0~50  ))
+// \tick|Add0~54  = CARRY(( \tick|count [11] ) + ( VCC ) + ( \tick|Add0~50  ))
+
+	.dataa(!\tick|count [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~53_sumout ),
+	.cout(\tick|Add0~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~53 .extended_lut = "off";
+defparam \tick|Add0~53 .lut_mask = 64'h0000000000005555;
+defparam \tick|Add0~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N35
+dffeas \tick|count[11] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~53_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[11] .is_wysiwyg = "true";
+defparam \tick|count[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N36
+cyclonev_lcell_comb \tick|Add0~29 (
+// Equation(s):
+// \tick|Add0~29_sumout  = SUM(( !\tick|count [12] ) + ( VCC ) + ( \tick|Add0~54  ))
+// \tick|Add0~30  = CARRY(( !\tick|count [12] ) + ( VCC ) + ( \tick|Add0~54  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\tick|count [12]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~29_sumout ),
+	.cout(\tick|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~29 .extended_lut = "off";
+defparam \tick|Add0~29 .lut_mask = 64'h000000000000F0F0;
+defparam \tick|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N27
+cyclonev_lcell_comb \tick|count[12]~6 (
+// Equation(s):
+// \tick|count[12]~6_combout  = ( !\tick|Add0~29_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[12]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[12]~6 .extended_lut = "off";
+defparam \tick|count[12]~6 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[12]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N28
+dffeas \tick|count[12] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[12]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[12] .is_wysiwyg = "true";
+defparam \tick|count[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N39
+cyclonev_lcell_comb \tick|Add0~57 (
+// Equation(s):
+// \tick|Add0~57_sumout  = SUM(( \tick|count [13] ) + ( VCC ) + ( \tick|Add0~30  ))
+// \tick|Add0~58  = CARRY(( \tick|count [13] ) + ( VCC ) + ( \tick|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(!\tick|count [13]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~57_sumout ),
+	.cout(\tick|Add0~58 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~57 .extended_lut = "off";
+defparam \tick|Add0~57 .lut_mask = 64'h0000000000003333;
+defparam \tick|Add0~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N41
+dffeas \tick|count[13] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~57_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[13] .is_wysiwyg = "true";
+defparam \tick|count[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N42
+cyclonev_lcell_comb \tick|Add0~61 (
+// Equation(s):
+// \tick|Add0~61_sumout  = SUM(( \tick|count [14] ) + ( VCC ) + ( \tick|Add0~58  ))
+// \tick|Add0~62  = CARRY(( \tick|count [14] ) + ( VCC ) + ( \tick|Add0~58  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [14]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~58 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~61_sumout ),
+	.cout(\tick|Add0~62 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~61 .extended_lut = "off";
+defparam \tick|Add0~61 .lut_mask = 64'h00000000000000FF;
+defparam \tick|Add0~61 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N43
+dffeas \tick|count[14] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~61_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[14] .is_wysiwyg = "true";
+defparam \tick|count[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N45
+cyclonev_lcell_comb \tick|Add0~33 (
+// Equation(s):
+// \tick|Add0~33_sumout  = SUM(( \tick|count[15]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~62  ))
+
+	.dataa(gnd),
+	.datab(!\tick|count[15]~DUPLICATE_q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~62 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~33_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~33 .extended_lut = "off";
+defparam \tick|Add0~33 .lut_mask = 64'h0000000000003333;
+defparam \tick|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N46
+dffeas \tick|count[15] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[15] .is_wysiwyg = "true";
+defparam \tick|count[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N10
+dffeas \tick|count[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[5] .is_wysiwyg = "true";
+defparam \tick|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N36
+cyclonev_lcell_comb \tick|Equal0~1 (
+// Equation(s):
+// \tick|Equal0~1_combout  = ( !\tick|count [5] & ( !\tick|count [4] & ( (!\tick|count [15] & (\tick|count [12] & !\tick|count [3])) ) ) )
+
+	.dataa(!\tick|count [15]),
+	.datab(!\tick|count [12]),
+	.datac(gnd),
+	.datad(!\tick|count [3]),
+	.datae(!\tick|count [5]),
+	.dataf(!\tick|count [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|Equal0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Equal0~1 .extended_lut = "off";
+defparam \tick|Equal0~1 .lut_mask = 64'h2200000000000000;
+defparam \tick|Equal0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N58
+dffeas \tick|count[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[7]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[7] .is_wysiwyg = "true";
+defparam \tick|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N42
+cyclonev_lcell_comb \tick|Equal0~0 (
+// Equation(s):
+// \tick|Equal0~0_combout  = ( \tick|count [8] & ( \tick|count [2] & ( (\tick|count [0] & (\tick|count [1] & \tick|count [7])) ) ) )
+
+	.dataa(!\tick|count [0]),
+	.datab(!\tick|count [1]),
+	.datac(!\tick|count [7]),
+	.datad(gnd),
+	.datae(!\tick|count [8]),
+	.dataf(!\tick|count [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|Equal0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Equal0~0 .extended_lut = "off";
+defparam \tick|Equal0~0 .lut_mask = 64'h0000000000000101;
+defparam \tick|Equal0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N51
+cyclonev_lcell_comb \tick|Equal0~2 (
+// Equation(s):
+// \tick|Equal0~2_combout  = ( !\tick|count [11] & ( (!\tick|count [10] & (!\tick|count [13] & !\tick|count [14])) ) )
+
+	.dataa(gnd),
+	.datab(!\tick|count [10]),
+	.datac(!\tick|count [13]),
+	.datad(!\tick|count [14]),
+	.datae(gnd),
+	.dataf(!\tick|count [11]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|Equal0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Equal0~2 .extended_lut = "off";
+defparam \tick|Equal0~2 .lut_mask = 64'hC000C00000000000;
+defparam \tick|Equal0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N30
+cyclonev_lcell_comb \tick|Equal0~3 (
+// Equation(s):
+// \tick|Equal0~3_combout  = ( \tick|count [9] & ( !\tick|count [6] & ( (\tick|Equal0~1_combout  & (\tick|Equal0~0_combout  & \tick|Equal0~2_combout )) ) ) )
+
+	.dataa(!\tick|Equal0~1_combout ),
+	.datab(!\tick|Equal0~0_combout ),
+	.datac(!\tick|Equal0~2_combout ),
+	.datad(gnd),
+	.datae(!\tick|count [9]),
+	.dataf(!\tick|count [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|Equal0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Equal0~3 .extended_lut = "off";
+defparam \tick|Equal0~3 .lut_mask = 64'h0000010100000000;
+defparam \tick|Equal0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y2_N21
+cyclonev_lcell_comb \tick|CLK_OUT~feeder (
+// Equation(s):
+// \tick|CLK_OUT~feeder_combout  = \tick|Equal0~3_combout 
+
+	.dataa(!\tick|Equal0~3_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|CLK_OUT~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|CLK_OUT~feeder .extended_lut = "off";
+defparam \tick|CLK_OUT~feeder .lut_mask = 64'h5555555555555555;
+defparam \tick|CLK_OUT~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N23
+dffeas \tick|CLK_OUT (
+	.clk(\CLOCK_50~input_o ),
+	.d(\tick|CLK_OUT~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|CLK_OUT~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|CLK_OUT .is_wysiwyg = "true";
+defparam \tick|CLK_OUT .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N27
+cyclonev_lcell_comb \dac|sr_state.IDLE~0 (
+// Equation(s):
+// \dac|sr_state.IDLE~0_combout  = ( \tick|CLK_OUT~q  & ( (!\dac|sr_state.WAIT_CSB_HIGH~q ) # (!\dac|WideNor0~combout ) ) ) # ( !\tick|CLK_OUT~q  & ( (!\dac|WideNor0~combout  & (((\dac|sr_state.IDLE~q ) # (\dac|sr_state.WAIT_CSB_FALL~q )))) # 
+// (\dac|WideNor0~combout  & (!\dac|sr_state.WAIT_CSB_HIGH~q  & ((\dac|sr_state.IDLE~q )))) ) )
+
+	.dataa(!\dac|sr_state.WAIT_CSB_HIGH~q ),
+	.datab(!\dac|WideNor0~combout ),
+	.datac(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datad(!\dac|sr_state.IDLE~q ),
+	.datae(gnd),
+	.dataf(!\tick|CLK_OUT~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|sr_state.IDLE~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|sr_state.IDLE~0 .extended_lut = "off";
+defparam \dac|sr_state.IDLE~0 .lut_mask = 64'h0CEE0CEEEEEEEEEE;
+defparam \dac|sr_state.IDLE~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N29
+dffeas \dac|sr_state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|sr_state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|sr_state.IDLE .is_wysiwyg = "true";
+defparam \dac|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N30
+cyclonev_lcell_comb \dac|Selector2~0 (
+// Equation(s):
+// \dac|Selector2~0_combout  = ( \dac|state [1] & ( \dac|state[3]~DUPLICATE_q  & ( \dac|sr_state.IDLE~q  ) ) ) # ( !\dac|state [1] & ( \dac|state[3]~DUPLICATE_q  & ( \dac|sr_state.IDLE~q  ) ) ) # ( \dac|state [1] & ( !\dac|state[3]~DUPLICATE_q  & ( 
+// \dac|sr_state.IDLE~q  ) ) ) # ( !\dac|state [1] & ( !\dac|state[3]~DUPLICATE_q  & ( (\dac|sr_state.IDLE~q  & ((!\dac|state [0] $ (!\dac|state [4])) # (\dac|state [2]))) ) ) )
+
+	.dataa(!\dac|state [0]),
+	.datab(!\dac|state [4]),
+	.datac(!\dac|sr_state.IDLE~q ),
+	.datad(!\dac|state [2]),
+	.datae(!\dac|state [1]),
+	.dataf(!\dac|state[3]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Selector2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Selector2~0 .extended_lut = "off";
+defparam \dac|Selector2~0 .lut_mask = 64'h060F0F0F0F0F0F0F;
+defparam \dac|Selector2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N32
+dffeas \dac|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \dac|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N24
+cyclonev_lcell_comb \dac|sr_state.WAIT_CSB_FALL~0 (
+// Equation(s):
+// \dac|sr_state.WAIT_CSB_FALL~0_combout  = ( \tick|CLK_OUT~q  & ( (!\dac|WideNor0~combout  & (((!\dac|sr_state.IDLE~q  & !\dac|sr_state.WAIT_CSB_FALL~q )))) # (\dac|WideNor0~combout  & (!\dac|sr_state.WAIT_CSB_HIGH~q  & ((!\dac|sr_state.IDLE~q ) # 
+// (\dac|sr_state.WAIT_CSB_FALL~q )))) ) ) # ( !\tick|CLK_OUT~q  & ( (!\dac|sr_state.WAIT_CSB_HIGH~q  & (\dac|WideNor0~combout  & \dac|sr_state.WAIT_CSB_FALL~q )) ) )
+
+	.dataa(!\dac|sr_state.WAIT_CSB_HIGH~q ),
+	.datab(!\dac|WideNor0~combout ),
+	.datac(!\dac|sr_state.IDLE~q ),
+	.datad(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datae(gnd),
+	.dataf(!\tick|CLK_OUT~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|sr_state.WAIT_CSB_FALL~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|sr_state.WAIT_CSB_FALL~0 .extended_lut = "off";
+defparam \dac|sr_state.WAIT_CSB_FALL~0 .lut_mask = 64'h00220022E022E022;
+defparam \dac|sr_state.WAIT_CSB_FALL~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N26
+dffeas \dac|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|sr_state.WAIT_CSB_FALL~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \dac|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N57
+cyclonev_lcell_comb \dac|Selector3~0 (
+// Equation(s):
+// \dac|Selector3~0_combout  = ( \dac|state [2] & ( \dac|sr_state.WAIT_CSB_FALL~q  & ( !\dac|state [0] ) ) ) # ( !\dac|state [2] & ( \dac|sr_state.WAIT_CSB_FALL~q  & ( !\dac|state [0] ) ) ) # ( \dac|state [2] & ( !\dac|sr_state.WAIT_CSB_FALL~q  & ( 
+// !\dac|state [0] ) ) ) # ( !\dac|state [2] & ( !\dac|sr_state.WAIT_CSB_FALL~q  & ( (!\dac|state [0] & (((\dac|state [4]) # (\dac|state [1])) # (\dac|state[3]~DUPLICATE_q ))) ) ) )
+
+	.dataa(!\dac|state[3]~DUPLICATE_q ),
+	.datab(!\dac|state [1]),
+	.datac(!\dac|state [0]),
+	.datad(!\dac|state [4]),
+	.datae(!\dac|state [2]),
+	.dataf(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Selector3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Selector3~0 .extended_lut = "off";
+defparam \dac|Selector3~0 .lut_mask = 64'h70F0F0F0F0F0F0F0;
+defparam \dac|Selector3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N38
+dffeas \dac|state[0] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|Selector3~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[0] .is_wysiwyg = "true";
+defparam \dac|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N15
+cyclonev_lcell_comb \dac|state~2 (
+// Equation(s):
+// \dac|state~2_combout  = ( \dac|state [0] & ( !\dac|state [2] $ (!\dac|state [1]) ) ) # ( !\dac|state [0] & ( \dac|state [2] ) )
+
+	.dataa(!\dac|state [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\dac|state [1]),
+	.datae(gnd),
+	.dataf(!\dac|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state~2 .extended_lut = "off";
+defparam \dac|state~2 .lut_mask = 64'h5555555555AA55AA;
+defparam \dac|state~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N2
+dffeas \dac|state[2] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~2_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[2] .is_wysiwyg = "true";
+defparam \dac|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N31
+dffeas \dac|state[3] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~3_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[3] .is_wysiwyg = "true";
+defparam \dac|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N48
+cyclonev_lcell_comb \dac|state~3 (
+// Equation(s):
+// \dac|state~3_combout  = ( \dac|state [0] & ( !\dac|state [3] $ (((!\dac|state [2]) # (!\dac|state [1]))) ) ) # ( !\dac|state [0] & ( \dac|state [3] ) )
+
+	.dataa(!\dac|state [2]),
+	.datab(!\dac|state [1]),
+	.datac(!\dac|state [3]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\dac|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state~3 .extended_lut = "off";
+defparam \dac|state~3 .lut_mask = 64'h0F0F0F0F1E1E1E1E;
+defparam \dac|state~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N32
+dffeas \dac|state[3]~DUPLICATE (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~3_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state[3]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[3]~DUPLICATE .is_wysiwyg = "true";
+defparam \dac|state[3]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N0
+cyclonev_lcell_comb \dac|state~1 (
+// Equation(s):
+// \dac|state~1_combout  = ( \dac|state [4] & ( (!\dac|state [1] & (\dac|state [0] & ((\dac|state [2]) # (\dac|state[3]~DUPLICATE_q )))) # (\dac|state [1] & (((!\dac|state [0])))) ) ) # ( !\dac|state [4] & ( !\dac|state [1] $ (!\dac|state [0]) ) )
+
+	.dataa(!\dac|state [1]),
+	.datab(!\dac|state[3]~DUPLICATE_q ),
+	.datac(!\dac|state [0]),
+	.datad(!\dac|state [2]),
+	.datae(gnd),
+	.dataf(!\dac|state [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state~1 .extended_lut = "off";
+defparam \dac|state~1 .lut_mask = 64'h5A5A5A5A525A525A;
+defparam \dac|state~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N17
+dffeas \dac|state[1] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~1_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[1] .is_wysiwyg = "true";
+defparam \dac|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N57
+cyclonev_lcell_comb \dac|WideNor0 (
+// Equation(s):
+// \dac|WideNor0~combout  = ( \dac|state [4] & ( (!\dac|state [1] & (\dac|state [0] & (!\dac|state[3]~DUPLICATE_q  & !\dac|state [2]))) ) ) # ( !\dac|state [4] & ( (!\dac|state [1] & (!\dac|state [0] & (!\dac|state[3]~DUPLICATE_q  & !\dac|state [2]))) ) )
+
+	.dataa(!\dac|state [1]),
+	.datab(!\dac|state [0]),
+	.datac(!\dac|state[3]~DUPLICATE_q ),
+	.datad(!\dac|state [2]),
+	.datae(gnd),
+	.dataf(!\dac|state [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|WideNor0~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|WideNor0 .extended_lut = "off";
+defparam \dac|WideNor0 .lut_mask = 64'h8000800020002000;
+defparam \dac|WideNor0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X12_Y0_N18
+cyclonev_io_ibuf \SW[0]~input (
+	.i(SW[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[0]~input_o ));
+// synopsys translate_off
+defparam \SW[0]~input .bus_hold = "false";
+defparam \SW[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N0
+cyclonev_lcell_comb \fin_address|Add0~1 (
+// Equation(s):
+// \fin_address|Add0~1_sumout  = SUM(( \fin_address|address [0] ) + ( \SW[0]~input_o  ) + ( !VCC ))
+// \fin_address|Add0~2  = CARRY(( \fin_address|address [0] ) + ( \SW[0]~input_o  ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SW[0]~input_o ),
+	.datad(!\fin_address|address [0]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~1_sumout ),
+	.cout(\fin_address|Add0~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~1 .extended_lut = "off";
+defparam \fin_address|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N59
+dffeas \fin_address|address[0] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(gnd),
+	.asdata(\fin_address|Add0~1_sumout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[0] .is_wysiwyg = "true";
+defparam \fin_address|address[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X16_Y0_N1
+cyclonev_io_ibuf \SW[1]~input (
+	.i(SW[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[1]~input_o ));
+// synopsys translate_off
+defparam \SW[1]~input .bus_hold = "false";
+defparam \SW[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N3
+cyclonev_lcell_comb \fin_address|Add0~5 (
+// Equation(s):
+// \fin_address|Add0~5_sumout  = SUM(( \fin_address|address [1] ) + ( \SW[1]~input_o  ) + ( \fin_address|Add0~2  ))
+// \fin_address|Add0~6  = CARRY(( \fin_address|address [1] ) + ( \SW[1]~input_o  ) + ( \fin_address|Add0~2  ))
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\fin_address|address [1]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~5_sumout ),
+	.cout(\fin_address|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~5 .extended_lut = "off";
+defparam \fin_address|Add0~5 .lut_mask = 64'h0000AAAA000000FF;
+defparam \fin_address|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N47
+dffeas \fin_address|address[1] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(gnd),
+	.asdata(\fin_address|Add0~5_sumout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[1] .is_wysiwyg = "true";
+defparam \fin_address|address[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X8_Y0_N35
+cyclonev_io_ibuf \SW[2]~input (
+	.i(SW[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[2]~input_o ));
+// synopsys translate_off
+defparam \SW[2]~input .bus_hold = "false";
+defparam \SW[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N6
+cyclonev_lcell_comb \fin_address|Add0~9 (
+// Equation(s):
+// \fin_address|Add0~9_sumout  = SUM(( \fin_address|address [2] ) + ( \SW[2]~input_o  ) + ( \fin_address|Add0~6  ))
+// \fin_address|Add0~10  = CARRY(( \fin_address|address [2] ) + ( \SW[2]~input_o  ) + ( \fin_address|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(!\SW[2]~input_o ),
+	.datac(!\fin_address|address [2]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~9_sumout ),
+	.cout(\fin_address|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~9 .extended_lut = "off";
+defparam \fin_address|Add0~9 .lut_mask = 64'h0000CCCC00000F0F;
+defparam \fin_address|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N51
+cyclonev_lcell_comb \fin_address|address[2]~feeder (
+// Equation(s):
+// \fin_address|address[2]~feeder_combout  = ( \fin_address|Add0~9_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[2]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[2]~feeder .extended_lut = "off";
+defparam \fin_address|address[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[2]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N53
+dffeas \fin_address|address[2] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[2] .is_wysiwyg = "true";
+defparam \fin_address|address[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N52
+cyclonev_io_ibuf \SW[3]~input (
+	.i(SW[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[3]~input_o ));
+// synopsys translate_off
+defparam \SW[3]~input .bus_hold = "false";
+defparam \SW[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N9
+cyclonev_lcell_comb \fin_address|Add0~13 (
+// Equation(s):
+// \fin_address|Add0~13_sumout  = SUM(( \SW[3]~input_o  ) + ( \fin_address|address [3] ) + ( \fin_address|Add0~10  ))
+// \fin_address|Add0~14  = CARRY(( \SW[3]~input_o  ) + ( \fin_address|address [3] ) + ( \fin_address|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [3]),
+	.datad(!\SW[3]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~13_sumout ),
+	.cout(\fin_address|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~13 .extended_lut = "off";
+defparam \fin_address|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N30
+cyclonev_lcell_comb \fin_address|address[3]~feeder (
+// Equation(s):
+// \fin_address|address[3]~feeder_combout  = ( \fin_address|Add0~13_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[3]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[3]~feeder .extended_lut = "off";
+defparam \fin_address|address[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N32
+dffeas \fin_address|address[3] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[3] .is_wysiwyg = "true";
+defparam \fin_address|address[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X2_Y0_N41
+cyclonev_io_ibuf \SW[4]~input (
+	.i(SW[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[4]~input_o ));
+// synopsys translate_off
+defparam \SW[4]~input .bus_hold = "false";
+defparam \SW[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N12
+cyclonev_lcell_comb \fin_address|Add0~17 (
+// Equation(s):
+// \fin_address|Add0~17_sumout  = SUM(( \fin_address|address [4] ) + ( \SW[4]~input_o  ) + ( \fin_address|Add0~14  ))
+// \fin_address|Add0~18  = CARRY(( \fin_address|address [4] ) + ( \SW[4]~input_o  ) + ( \fin_address|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SW[4]~input_o ),
+	.datad(!\fin_address|address [4]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~17_sumout ),
+	.cout(\fin_address|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~17 .extended_lut = "off";
+defparam \fin_address|Add0~17 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N36
+cyclonev_lcell_comb \fin_address|address[4]~feeder (
+// Equation(s):
+// \fin_address|address[4]~feeder_combout  = ( \fin_address|Add0~17_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[4]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[4]~feeder .extended_lut = "off";
+defparam \fin_address|address[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N38
+dffeas \fin_address|address[4] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[4] .is_wysiwyg = "true";
+defparam \fin_address|address[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X16_Y0_N18
+cyclonev_io_ibuf \SW[5]~input (
+	.i(SW[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[5]~input_o ));
+// synopsys translate_off
+defparam \SW[5]~input .bus_hold = "false";
+defparam \SW[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N15
+cyclonev_lcell_comb \fin_address|Add0~21 (
+// Equation(s):
+// \fin_address|Add0~21_sumout  = SUM(( \fin_address|address [5] ) + ( \SW[5]~input_o  ) + ( \fin_address|Add0~18  ))
+// \fin_address|Add0~22  = CARRY(( \fin_address|address [5] ) + ( \SW[5]~input_o  ) + ( \fin_address|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\fin_address|address [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~21_sumout ),
+	.cout(\fin_address|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~21 .extended_lut = "off";
+defparam \fin_address|Add0~21 .lut_mask = 64'h0000CCCC00000F0F;
+defparam \fin_address|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N39
+cyclonev_lcell_comb \fin_address|address[5]~feeder (
+// Equation(s):
+// \fin_address|address[5]~feeder_combout  = ( \fin_address|Add0~21_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[5]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[5]~feeder .extended_lut = "off";
+defparam \fin_address|address[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N41
+dffeas \fin_address|address[5] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[5] .is_wysiwyg = "true";
+defparam \fin_address|address[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N35
+cyclonev_io_ibuf \SW[6]~input (
+	.i(SW[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[6]~input_o ));
+// synopsys translate_off
+defparam \SW[6]~input .bus_hold = "false";
+defparam \SW[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N18
+cyclonev_lcell_comb \fin_address|Add0~25 (
+// Equation(s):
+// \fin_address|Add0~25_sumout  = SUM(( \fin_address|address [6] ) + ( \SW[6]~input_o  ) + ( \fin_address|Add0~22  ))
+// \fin_address|Add0~26  = CARRY(( \fin_address|address [6] ) + ( \SW[6]~input_o  ) + ( \fin_address|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [6]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[6]~input_o ),
+	.datag(gnd),
+	.cin(\fin_address|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~25_sumout ),
+	.cout(\fin_address|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~25 .extended_lut = "off";
+defparam \fin_address|Add0~25 .lut_mask = 64'h0000FF0000000F0F;
+defparam \fin_address|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N48
+cyclonev_lcell_comb \fin_address|address[6]~feeder (
+// Equation(s):
+// \fin_address|address[6]~feeder_combout  = ( \fin_address|Add0~25_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[6]~feeder .extended_lut = "off";
+defparam \fin_address|address[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N50
+dffeas \fin_address|address[6] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[6] .is_wysiwyg = "true";
+defparam \fin_address|address[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N1
+cyclonev_io_ibuf \SW[7]~input (
+	.i(SW[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[7]~input_o ));
+// synopsys translate_off
+defparam \SW[7]~input .bus_hold = "false";
+defparam \SW[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N21
+cyclonev_lcell_comb \fin_address|Add0~29 (
+// Equation(s):
+// \fin_address|Add0~29_sumout  = SUM(( \fin_address|address [7] ) + ( \SW[7]~input_o  ) + ( \fin_address|Add0~26  ))
+// \fin_address|Add0~30  = CARRY(( \fin_address|address [7] ) + ( \SW[7]~input_o  ) + ( \fin_address|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SW[7]~input_o ),
+	.datad(!\fin_address|address [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~29_sumout ),
+	.cout(\fin_address|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~29 .extended_lut = "off";
+defparam \fin_address|Add0~29 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N54
+cyclonev_lcell_comb \fin_address|address[7]~feeder (
+// Equation(s):
+// \fin_address|address[7]~feeder_combout  = ( \fin_address|Add0~29_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[7]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[7]~feeder .extended_lut = "off";
+defparam \fin_address|address[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N56
+dffeas \fin_address|address[7] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[7] .is_wysiwyg = "true";
+defparam \fin_address|address[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N18
+cyclonev_io_ibuf \SW[8]~input (
+	.i(SW[8]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[8]~input_o ));
+// synopsys translate_off
+defparam \SW[8]~input .bus_hold = "false";
+defparam \SW[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N24
+cyclonev_lcell_comb \fin_address|Add0~33 (
+// Equation(s):
+// \fin_address|Add0~33_sumout  = SUM(( \fin_address|address [8] ) + ( \SW[8]~input_o  ) + ( \fin_address|Add0~30  ))
+// \fin_address|Add0~34  = CARRY(( \fin_address|address [8] ) + ( \SW[8]~input_o  ) + ( \fin_address|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [8]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[8]~input_o ),
+	.datag(gnd),
+	.cin(\fin_address|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~33_sumout ),
+	.cout(\fin_address|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~33 .extended_lut = "off";
+defparam \fin_address|Add0~33 .lut_mask = 64'h0000FF0000000F0F;
+defparam \fin_address|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N33
+cyclonev_lcell_comb \fin_address|address[8]~feeder (
+// Equation(s):
+// \fin_address|address[8]~feeder_combout  = ( \fin_address|Add0~33_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[8]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[8]~feeder .extended_lut = "off";
+defparam \fin_address|address[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[8]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N35
+dffeas \fin_address|address[8] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[8] .is_wysiwyg = "true";
+defparam \fin_address|address[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X2_Y0_N58
+cyclonev_io_ibuf \SW[9]~input (
+	.i(SW[9]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[9]~input_o ));
+// synopsys translate_off
+defparam \SW[9]~input .bus_hold = "false";
+defparam \SW[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N27
+cyclonev_lcell_comb \fin_address|Add0~37 (
+// Equation(s):
+// \fin_address|Add0~37_sumout  = SUM(( \fin_address|address [9] ) + ( \SW[9]~input_o  ) + ( \fin_address|Add0~34  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[9]~input_o ),
+	.datag(gnd),
+	.cin(\fin_address|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~37_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~37 .extended_lut = "off";
+defparam \fin_address|Add0~37 .lut_mask = 64'h0000FF0000000F0F;
+defparam \fin_address|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y3_N42
+cyclonev_lcell_comb \fin_address|address[9]~feeder (
+// Equation(s):
+// \fin_address|address[9]~feeder_combout  = ( \fin_address|Add0~37_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[9]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[9]~feeder .extended_lut = "off";
+defparam \fin_address|address[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[9]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y3_N44
+dffeas \fin_address|address[9] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[9] .is_wysiwyg = "true";
+defparam \fin_address|address[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: M10K_X58_Y2_N0
+cyclonev_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(vcc),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain(10'b0000000000),
+	.portaaddr({\fin_address|address [9],\fin_address|address [8],\fin_address|address [7],\fin_address|address [6],\fin_address|address [5],\fin_address|address [4],\fin_address|address [3],\fin_address|address [2],\fin_address|address [1],\fin_address|address [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(10'b0000000000),
+	.portbaddr(10'b0000000000),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
+	.portbdataout(),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom_data/rom_data.mif";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ALTSYNCRAM";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 1023;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 1024;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M20K";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init4 = "7F1F97D9F37C1ED7A9E678DE0775DA75DD4741CD729C7711C16F9BB6E1B46C5AE6ADA8695A267D9C665966498F63189619836017D5E9775D1715B96B5A1655895F57159559535414D52947511424FD3C4E5364CD304B52A4A1254891F4711A45D144450E4310941903404FE3ECF93D8F33C4EE3ACE9398E3384DE370D9358D4344CF330CA31CC5308C02F4BB2E4B62D0B12BCAD2A8A8298A32849F2749A260962509123C8D22C8921C85208801F87C1E8781D8741C8701B86C1A86819C6518C6117C5D1705A16056150531444F1384C1284911C46110421043F0F83C0EC390E0370D4340C8310C02E0B42C0AC290A0270982508C220842007C1E0741C06C1A06";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = "41805C160541404C13048110400F03C0E0340C0300B0280A024090200801C0601806014050100400C0300C020080200801004010040100000000000000000000000000000000000000010040100401008020080200C0300C0401005014060180601C08020090240A0280B0300C0340E03C0F040110481304C140541605C180641A06C1C0741E07C200842208C25098270A0290AC2C0B42E0C0310C8340D4370E0390EC3C0F83F104421104611C491284C1384F14453150561605A1705D17C6118C6519C681A86C1B8701C8741D8781E87C1F8802088521C8922C8D23C91250962609A2749F284A3298A82A8AD2BCB12D0B62E4BB2F4C0308C531CCA330CF344D";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = "4358D9370DE384E3398E93ACEE3C4F33D8F93ECFE40503419094310E4451445D1A4711F489254A12A4B5304CD364E53C4FD42511475294D54153559595715F589655A16B5B9715D1775E97D60183619896318F649966659C67DA2695A86ADAE6C5B46E1BB6F9C1711C7729CD741D475DDA775E078DE67A9ED7C1F37D9F97F20080E068260C83E12856198721F88A258A22B8BE328D6388EE3E9064491E4B93A519525796A5D9826399A699B6709CE769E67C9FE82A1688A2E8EA4694A5E9AA76A0A8EA6AA6ACABEB2AD6B8AEEBDB02C3B1AC9B32CFB4AD5B5EDAB76E0B8EE5BA2EBBBAF1BCEF6BE6FCBFB01C1306C270CC3B11C5316C671CC7B21C8F26CA72BC";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = "BB30CCF35CE33ACF73FD0B44D1B49D2F4ED4352D5757D675CD7B60D8B65D9F69DAF6EDC372DD376DE37ADF77FE0783E1787E278BE378FE4793E5797E639AE739EE83A2E8FA5E9FA9EAFACEBBB0EC7B3ED7B6EE3B9EEFBDEFBC0F07C3F13C6F1FC8F2BCBF37CEF3FD1F4BD3F53D6F5FD8F67DAF73DDF7BDFF83E1F8BE3F93E5F9BE7FA3E9FABEBFB3ECFB7EEFBFF0FC3F1FCBF3FCFF4FD7F5FDBF6FDFF7FE3F9FE7F9FEBFAFEFFBFF3FCFF3FDFF7FDFF7FEFFBFEFFBFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFBFEFFBFEFF7FDFF7FDFF3FCFF3FBFEFFAFEBF9FE7F9FE3F7FDFF6FDBF5FD7F4FCFF3FCBF1FC3F0FBFEEFB7ECFB3EBFABE9FA3E7F9B";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = "E5F93E3F8BE1F83DFF7BDDF73DAF67D8F5FD6F53D3F4BD1F3FCEF37CBF2BC8F1FC6F13C3F07C0EFBBDEEFB9EE3B6ED7B3EC7B0EBBACEAFA9E9FA5E8FA2E839EE739AE6397E5793E478FE378BE2787E1783E077FDF77ADE376DD372DC36EDAF69D9F65D8B60D7B5CD6757D5752D434ED2F49D1B44D0B3FCF73ACE335CCF30CBB2BCA726C8F21C7B1CC6716C5311C3B0CC2706C1301BFAFCBE6F6BCEF1BBAEBBA2E5B8EE0B76DAB5ED5B4ACFB32C9B1AC3B02BDAEEB8AD6B2ABEACAA6A6A8EA0A769AA5E94A468EA2E88A16829FE7C9E6769CE709B66999A639825D96A579525193A4B91E449063E8EE388D6328BE2B8A22588A1F872198561283E0C8260680E00";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N12
+cyclonev_lcell_comb \dac|shift_reg[11]~feeder (
+// Equation(s):
+// \dac|shift_reg[11]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [9] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [9]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[11]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[11]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[11]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[11]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N51
+cyclonev_lcell_comb \dac|shift_reg[10]~feeder (
+// Equation(s):
+// \dac|shift_reg[10]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [8] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[10]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[10]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[10]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[10]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N18
+cyclonev_lcell_comb \dac|shift_reg[9]~feeder (
+// Equation(s):
+// \dac|shift_reg[9]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [7] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[9]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[9]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[9]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N3
+cyclonev_lcell_comb \dac|shift_reg[8]~feeder (
+// Equation(s):
+// \dac|shift_reg[8]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [6] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[8]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[8]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[8]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N54
+cyclonev_lcell_comb \dac|shift_reg[7]~feeder (
+// Equation(s):
+// \dac|shift_reg[7]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [5] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [5]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[7]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[7]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N33
+cyclonev_lcell_comb \dac|shift_reg[6]~feeder (
+// Equation(s):
+// \dac|shift_reg[6]~feeder_combout  = \rom|altsyncram_component|auto_generated|q_a [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\rom|altsyncram_component|auto_generated|q_a [4]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[6]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[6]~feeder .lut_mask = 64'h00FF00FF00FF00FF;
+defparam \dac|shift_reg[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N42
+cyclonev_lcell_comb \dac|shift_reg[5]~feeder (
+// Equation(s):
+// \dac|shift_reg[5]~feeder_combout  = \rom|altsyncram_component|auto_generated|q_a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\rom|altsyncram_component|auto_generated|q_a [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[5]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[5]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[5]~feeder .lut_mask = 64'h00FF00FF00FF00FF;
+defparam \dac|shift_reg[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N45
+cyclonev_lcell_comb \dac|shift_reg[4]~feeder (
+// Equation(s):
+// \dac|shift_reg[4]~feeder_combout  = \rom|altsyncram_component|auto_generated|q_a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\rom|altsyncram_component|auto_generated|q_a [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[4]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[4]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[4]~feeder .lut_mask = 64'h00FF00FF00FF00FF;
+defparam \dac|shift_reg[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N6
+cyclonev_lcell_comb \dac|shift_reg[3]~feeder (
+// Equation(s):
+// \dac|shift_reg[3]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [1] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[3]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[3]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N45
+cyclonev_lcell_comb \dac|shift_reg~4 (
+// Equation(s):
+// \dac|shift_reg~4_combout  = ( \rom|altsyncram_component|auto_generated|q_a [0] & ( \dac|WideNor0~combout  & ( \dac|sr_state.WAIT_CSB_FALL~q  ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datad(gnd),
+	.datae(!\rom|altsyncram_component|auto_generated|q_a [0]),
+	.dataf(!\dac|WideNor0~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~4 .extended_lut = "off";
+defparam \dac|shift_reg~4 .lut_mask = 64'h0000000000000F0F;
+defparam \dac|shift_reg~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N47
+dffeas \dac|shift_reg[2] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[2] .is_wysiwyg = "true";
+defparam \dac|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N39
+cyclonev_lcell_comb \dac|always5~0 (
+// Equation(s):
+// \dac|always5~0_combout  = ( \dac|state [0] & ( \dac|sr_state.WAIT_CSB_FALL~q  & ( (((!\dac|state [4]) # (\dac|state [1])) # (\dac|state[3]~DUPLICATE_q )) # (\dac|state [2]) ) ) ) # ( !\dac|state [0] & ( \dac|sr_state.WAIT_CSB_FALL~q  & ( (((\dac|state 
+// [4]) # (\dac|state [1])) # (\dac|state[3]~DUPLICATE_q )) # (\dac|state [2]) ) ) ) # ( \dac|state [0] & ( !\dac|sr_state.WAIT_CSB_FALL~q  ) ) # ( !\dac|state [0] & ( !\dac|sr_state.WAIT_CSB_FALL~q  ) )
+
+	.dataa(!\dac|state [2]),
+	.datab(!\dac|state[3]~DUPLICATE_q ),
+	.datac(!\dac|state [1]),
+	.datad(!\dac|state [4]),
+	.datae(!\dac|state [0]),
+	.dataf(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|always5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|always5~0 .extended_lut = "off";
+defparam \dac|always5~0 .lut_mask = 64'hFFFFFFFF7FFFFF7F;
+defparam \dac|always5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N7
+dffeas \dac|shift_reg[3] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[3]~feeder_combout ),
+	.asdata(\dac|shift_reg [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[3] .is_wysiwyg = "true";
+defparam \dac|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N47
+dffeas \dac|shift_reg[4] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[4]~feeder_combout ),
+	.asdata(\dac|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[4] .is_wysiwyg = "true";
+defparam \dac|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N43
+dffeas \dac|shift_reg[5] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[5]~feeder_combout ),
+	.asdata(\dac|shift_reg [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[5] .is_wysiwyg = "true";
+defparam \dac|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N34
+dffeas \dac|shift_reg[6] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[6]~feeder_combout ),
+	.asdata(\dac|shift_reg [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[6] .is_wysiwyg = "true";
+defparam \dac|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N56
+dffeas \dac|shift_reg[7] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[7]~feeder_combout ),
+	.asdata(\dac|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[7] .is_wysiwyg = "true";
+defparam \dac|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N4
+dffeas \dac|shift_reg[8] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[8]~feeder_combout ),
+	.asdata(\dac|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[8] .is_wysiwyg = "true";
+defparam \dac|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N19
+dffeas \dac|shift_reg[9] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[9]~feeder_combout ),
+	.asdata(\dac|shift_reg [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[9] .is_wysiwyg = "true";
+defparam \dac|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N52
+dffeas \dac|shift_reg[10] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[10]~feeder_combout ),
+	.asdata(\dac|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[10] .is_wysiwyg = "true";
+defparam \dac|shift_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N13
+dffeas \dac|shift_reg[11] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[11]~feeder_combout ),
+	.asdata(\dac|shift_reg [10]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[11] .is_wysiwyg = "true";
+defparam \dac|shift_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N9
+cyclonev_lcell_comb \dac|shift_reg~3 (
+// Equation(s):
+// \dac|shift_reg~3_combout  = ( \dac|shift_reg [11] ) # ( !\dac|shift_reg [11] & ( (\dac|sr_state.WAIT_CSB_FALL~q  & \dac|WideNor0~combout ) ) )
+
+	.dataa(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\dac|WideNor0~combout ),
+	.datae(gnd),
+	.dataf(!\dac|shift_reg [11]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~3 .extended_lut = "off";
+defparam \dac|shift_reg~3 .lut_mask = 64'h00550055FFFFFFFF;
+defparam \dac|shift_reg~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N10
+dffeas \dac|shift_reg[12] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[12] .is_wysiwyg = "true";
+defparam \dac|shift_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N36
+cyclonev_lcell_comb \dac|shift_reg~2 (
+// Equation(s):
+// \dac|shift_reg~2_combout  = ( \dac|sr_state.WAIT_CSB_FALL~q  & ( \dac|WideNor0~combout  ) ) # ( !\dac|sr_state.WAIT_CSB_FALL~q  & ( \dac|WideNor0~combout  & ( \dac|shift_reg [12] ) ) ) # ( \dac|sr_state.WAIT_CSB_FALL~q  & ( !\dac|WideNor0~combout  & ( 
+// \dac|shift_reg [12] ) ) ) # ( !\dac|sr_state.WAIT_CSB_FALL~q  & ( !\dac|WideNor0~combout  & ( \dac|shift_reg [12] ) ) )
+
+	.dataa(gnd),
+	.datab(!\dac|shift_reg [12]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.dataf(!\dac|WideNor0~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~2 .extended_lut = "off";
+defparam \dac|shift_reg~2 .lut_mask = 64'h333333333333FFFF;
+defparam \dac|shift_reg~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N38
+dffeas \dac|shift_reg[13] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[13] .is_wysiwyg = "true";
+defparam \dac|shift_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N57
+cyclonev_lcell_comb \dac|shift_reg~1 (
+// Equation(s):
+// \dac|shift_reg~1_combout  = ( \dac|sr_state.WAIT_CSB_FALL~q  & ( \dac|WideNor0~combout  ) ) # ( !\dac|sr_state.WAIT_CSB_FALL~q  & ( \dac|WideNor0~combout  & ( \dac|shift_reg [13] ) ) ) # ( \dac|sr_state.WAIT_CSB_FALL~q  & ( !\dac|WideNor0~combout  & ( 
+// \dac|shift_reg [13] ) ) ) # ( !\dac|sr_state.WAIT_CSB_FALL~q  & ( !\dac|WideNor0~combout  & ( \dac|shift_reg [13] ) ) )
+
+	.dataa(gnd),
+	.datab(!\dac|shift_reg [13]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.dataf(!\dac|WideNor0~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~1 .extended_lut = "off";
+defparam \dac|shift_reg~1 .lut_mask = 64'h333333333333FFFF;
+defparam \dac|shift_reg~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N58
+dffeas \dac|shift_reg[14] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[14] .is_wysiwyg = "true";
+defparam \dac|shift_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N24
+cyclonev_lcell_comb \dac|shift_reg~0 (
+// Equation(s):
+// \dac|shift_reg~0_combout  = ( \dac|shift_reg [14] & ( \dac|WideNor0~combout  & ( !\dac|sr_state.WAIT_CSB_FALL~q  ) ) ) # ( \dac|shift_reg [14] & ( !\dac|WideNor0~combout  ) )
+
+	.dataa(gnd),
+	.datab(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\dac|shift_reg [14]),
+	.dataf(!\dac|WideNor0~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~0 .extended_lut = "off";
+defparam \dac|shift_reg~0 .lut_mask = 64'h0000FFFF0000CCCC;
+defparam \dac|shift_reg~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N25
+dffeas \dac|shift_reg[15] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[15] .is_wysiwyg = "true";
+defparam \dac|shift_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N0
+cyclonev_lcell_comb \dac|Equal2~0 (
+// Equation(s):
+// \dac|Equal2~0_combout  = ( \dac|state [0] & ( !\dac|state[3]~DUPLICATE_q  & ( (!\dac|state [1] & (!\dac|state [2] & \dac|state [4])) ) ) )
+
+	.dataa(gnd),
+	.datab(!\dac|state [1]),
+	.datac(!\dac|state [2]),
+	.datad(!\dac|state [4]),
+	.datae(!\dac|state [0]),
+	.dataf(!\dac|state[3]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Equal2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Equal2~0 .extended_lut = "off";
+defparam \dac|Equal2~0 .lut_mask = 64'h000000C000000000;
+defparam \dac|Equal2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N6
+cyclonev_lcell_comb \dac|dac_sck (
+// Equation(s):
+// \dac|dac_sck~combout  = ( \dac|state [0] & ( \dac|state [1] & ( \dac|clk_1MHz~q  ) ) ) # ( !\dac|state [0] & ( \dac|state [1] & ( \dac|clk_1MHz~q  ) ) ) # ( \dac|state [0] & ( !\dac|state [1] & ( ((!\dac|state[3]~DUPLICATE_q  & (!\dac|state [2] & 
+// \dac|state [4]))) # (\dac|clk_1MHz~q ) ) ) ) # ( !\dac|state [0] & ( !\dac|state [1] & ( ((!\dac|state[3]~DUPLICATE_q  & (!\dac|state [2] & !\dac|state [4]))) # (\dac|clk_1MHz~q ) ) ) )
+
+	.dataa(!\dac|state[3]~DUPLICATE_q ),
+	.datab(!\dac|clk_1MHz~q ),
+	.datac(!\dac|state [2]),
+	.datad(!\dac|state [4]),
+	.datae(!\dac|state [0]),
+	.dataf(!\dac|state [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|dac_sck~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|dac_sck .extended_lut = "off";
+defparam \dac|dac_sck .lut_mask = 64'hB33333B333333333;
+defparam \dac|dac_sck .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N30
+cyclonev_lcell_comb \p|count[0]~0 (
+// Equation(s):
+// \p|count[0]~0_combout  = !\p|count [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [0]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|count[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|count[0]~0 .extended_lut = "off";
+defparam \p|count[0]~0 .lut_mask = 64'hFF00FF00FF00FF00;
+defparam \p|count[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N31
+dffeas \p|count[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|count[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[0] .is_wysiwyg = "true";
+defparam \p|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N0
+cyclonev_lcell_comb \p|Add0~33 (
+// Equation(s):
+// \p|Add0~33_sumout  = SUM(( \p|count [1] ) + ( \p|count [0] ) + ( !VCC ))
+// \p|Add0~34  = CARRY(( \p|count [1] ) + ( \p|count [0] ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\p|count [0]),
+	.datad(!\p|count [1]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~33_sumout ),
+	.cout(\p|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~33 .extended_lut = "off";
+defparam \p|Add0~33 .lut_mask = 64'h0000F0F0000000FF;
+defparam \p|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N2
+dffeas \p|count[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[1] .is_wysiwyg = "true";
+defparam \p|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N3
+cyclonev_lcell_comb \p|Add0~29 (
+// Equation(s):
+// \p|Add0~29_sumout  = SUM(( \p|count [2] ) + ( GND ) + ( \p|Add0~34  ))
+// \p|Add0~30  = CARRY(( \p|count [2] ) + ( GND ) + ( \p|Add0~34  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~29_sumout ),
+	.cout(\p|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~29 .extended_lut = "off";
+defparam \p|Add0~29 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N5
+dffeas \p|count[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~29_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[2] .is_wysiwyg = "true";
+defparam \p|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N6
+cyclonev_lcell_comb \p|Add0~25 (
+// Equation(s):
+// \p|Add0~25_sumout  = SUM(( \p|count [3] ) + ( GND ) + ( \p|Add0~30  ))
+// \p|Add0~26  = CARRY(( \p|count [3] ) + ( GND ) + ( \p|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~25_sumout ),
+	.cout(\p|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~25 .extended_lut = "off";
+defparam \p|Add0~25 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N7
+dffeas \p|count[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[3] .is_wysiwyg = "true";
+defparam \p|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N9
+cyclonev_lcell_comb \p|Add0~21 (
+// Equation(s):
+// \p|Add0~21_sumout  = SUM(( \p|count [4] ) + ( GND ) + ( \p|Add0~26  ))
+// \p|Add0~22  = CARRY(( \p|count [4] ) + ( GND ) + ( \p|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [4]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~21_sumout ),
+	.cout(\p|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~21 .extended_lut = "off";
+defparam \p|Add0~21 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N11
+dffeas \p|count[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[4] .is_wysiwyg = "true";
+defparam \p|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N12
+cyclonev_lcell_comb \p|Add0~17 (
+// Equation(s):
+// \p|Add0~17_sumout  = SUM(( \p|count [5] ) + ( GND ) + ( \p|Add0~22  ))
+// \p|Add0~18  = CARRY(( \p|count [5] ) + ( GND ) + ( \p|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [5]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~17_sumout ),
+	.cout(\p|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~17 .extended_lut = "off";
+defparam \p|Add0~17 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N14
+dffeas \p|count[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[5] .is_wysiwyg = "true";
+defparam \p|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N15
+cyclonev_lcell_comb \p|Add0~13 (
+// Equation(s):
+// \p|Add0~13_sumout  = SUM(( \p|count [6] ) + ( GND ) + ( \p|Add0~18  ))
+// \p|Add0~14  = CARRY(( \p|count [6] ) + ( GND ) + ( \p|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [6]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~13_sumout ),
+	.cout(\p|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~13 .extended_lut = "off";
+defparam \p|Add0~13 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N17
+dffeas \p|count[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[6] .is_wysiwyg = "true";
+defparam \p|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N18
+cyclonev_lcell_comb \p|Add0~9 (
+// Equation(s):
+// \p|Add0~9_sumout  = SUM(( \p|count [7] ) + ( GND ) + ( \p|Add0~14  ))
+// \p|Add0~10  = CARRY(( \p|count [7] ) + ( GND ) + ( \p|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~9_sumout ),
+	.cout(\p|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~9 .extended_lut = "off";
+defparam \p|Add0~9 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N20
+dffeas \p|count[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[7] .is_wysiwyg = "true";
+defparam \p|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N21
+cyclonev_lcell_comb \p|Add0~5 (
+// Equation(s):
+// \p|Add0~5_sumout  = SUM(( \p|count [8] ) + ( GND ) + ( \p|Add0~10  ))
+// \p|Add0~6  = CARRY(( \p|count [8] ) + ( GND ) + ( \p|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [8]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~5_sumout ),
+	.cout(\p|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~5 .extended_lut = "off";
+defparam \p|Add0~5 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N22
+dffeas \p|count[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[8] .is_wysiwyg = "true";
+defparam \p|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N24
+cyclonev_lcell_comb \p|Add0~1 (
+// Equation(s):
+// \p|Add0~1_sumout  = SUM(( \p|count [9] ) + ( GND ) + ( \p|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [9]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~1 .extended_lut = "off";
+defparam \p|Add0~1 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N26
+dffeas \p|count[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~1_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[9] .is_wysiwyg = "true";
+defparam \p|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N16
+dffeas \p|d[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[9] .is_wysiwyg = "true";
+defparam \p|d[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N55
+dffeas \p|d[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[8] .is_wysiwyg = "true";
+defparam \p|d[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N40
+dffeas \p|d[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[7] .is_wysiwyg = "true";
+defparam \p|d[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N39
+cyclonev_lcell_comb \p|LessThan0~0 (
+// Equation(s):
+// \p|LessThan0~0_combout  = ( !\p|d [7] & ( \p|count [7] ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\p|d [7]),
+	.dataf(!\p|count [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~0 .extended_lut = "off";
+defparam \p|LessThan0~0 .lut_mask = 64'h00000000FFFF0000;
+defparam \p|LessThan0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N51
+cyclonev_lcell_comb \p|d[6]~feeder (
+// Equation(s):
+// \p|d[6]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [6] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|d[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|d[6]~feeder .extended_lut = "off";
+defparam \p|d[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \p|d[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N53
+dffeas \p|d[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|d[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[6] .is_wysiwyg = "true";
+defparam \p|d[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N44
+dffeas \p|d[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[3] .is_wysiwyg = "true";
+defparam \p|d[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N50
+dffeas \p|d[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[4] .is_wysiwyg = "true";
+defparam \p|d[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N41
+dffeas \p|d[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[2] .is_wysiwyg = "true";
+defparam \p|d[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N47
+dffeas \p|d[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[1] .is_wysiwyg = "true";
+defparam \p|d[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N52
+dffeas \p|d[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[0] .is_wysiwyg = "true";
+defparam \p|d[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N32
+dffeas \p|count[0]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|count[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count[0]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[0]~DUPLICATE .is_wysiwyg = "true";
+defparam \p|count[0]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N42
+cyclonev_lcell_comb \p|LessThan0~2 (
+// Equation(s):
+// \p|LessThan0~2_combout  = ( \p|d [0] & ( \p|count[0]~DUPLICATE_q  & ( (!\p|d [2] & (((\p|count [1] & !\p|d [1])) # (\p|count [2]))) # (\p|d [2] & (\p|count [1] & (\p|count [2] & !\p|d [1]))) ) ) ) # ( !\p|d [0] & ( \p|count[0]~DUPLICATE_q  & ( (!\p|d [2] 
+// & (((!\p|d [1]) # (\p|count [2])) # (\p|count [1]))) # (\p|d [2] & (\p|count [2] & ((!\p|d [1]) # (\p|count [1])))) ) ) ) # ( \p|d [0] & ( !\p|count[0]~DUPLICATE_q  & ( (!\p|d [2] & (((\p|count [1] & !\p|d [1])) # (\p|count [2]))) # (\p|d [2] & (\p|count 
+// [1] & (\p|count [2] & !\p|d [1]))) ) ) ) # ( !\p|d [0] & ( !\p|count[0]~DUPLICATE_q  & ( (!\p|d [2] & (((\p|count [1] & !\p|d [1])) # (\p|count [2]))) # (\p|d [2] & (\p|count [1] & (\p|count [2] & !\p|d [1]))) ) ) )
+
+	.dataa(!\p|count [1]),
+	.datab(!\p|d [2]),
+	.datac(!\p|count [2]),
+	.datad(!\p|d [1]),
+	.datae(!\p|d [0]),
+	.dataf(!\p|count[0]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~2 .extended_lut = "off";
+defparam \p|LessThan0~2 .lut_mask = 64'h4D0C4D0CCF4D4D0C;
+defparam \p|LessThan0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N48
+cyclonev_lcell_comb \p|LessThan0~3 (
+// Equation(s):
+// \p|LessThan0~3_combout  = ( \p|LessThan0~2_combout  & ( (!\p|count [4] & (!\p|d [4] & ((!\p|d [3]) # (\p|count [3])))) # (\p|count [4] & (((!\p|d [3]) # (!\p|d [4])) # (\p|count [3]))) ) ) # ( !\p|LessThan0~2_combout  & ( (!\p|count [4] & (\p|count [3] & 
+// (!\p|d [3] & !\p|d [4]))) # (\p|count [4] & ((!\p|d [4]) # ((\p|count [3] & !\p|d [3])))) ) )
+
+	.dataa(!\p|count [3]),
+	.datab(!\p|count [4]),
+	.datac(!\p|d [3]),
+	.datad(!\p|d [4]),
+	.datae(gnd),
+	.dataf(!\p|LessThan0~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~3 .extended_lut = "off";
+defparam \p|LessThan0~3 .lut_mask = 64'h73107310F731F731;
+defparam \p|LessThan0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N38
+dffeas \p|d[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[5] .is_wysiwyg = "true";
+defparam \p|d[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N33
+cyclonev_lcell_comb \p|LessThan0~1 (
+// Equation(s):
+// \p|LessThan0~1_combout  = ( \p|count [7] & ( !\p|d [7] ) ) # ( !\p|count [7] & ( \p|d [7] ) )
+
+	.dataa(!\p|d [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\p|count [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~1 .extended_lut = "off";
+defparam \p|LessThan0~1 .lut_mask = 64'h55555555AAAAAAAA;
+defparam \p|LessThan0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N36
+cyclonev_lcell_comb \p|LessThan0~4 (
+// Equation(s):
+// \p|LessThan0~4_combout  = ( \p|d [5] & ( !\p|LessThan0~1_combout  & ( (!\p|d [6] & (((\p|LessThan0~3_combout  & \p|count [5])) # (\p|count [6]))) # (\p|d [6] & (\p|count [6] & (\p|LessThan0~3_combout  & \p|count [5]))) ) ) ) # ( !\p|d [5] & ( 
+// !\p|LessThan0~1_combout  & ( (!\p|d [6] & (((\p|count [5]) # (\p|LessThan0~3_combout )) # (\p|count [6]))) # (\p|d [6] & (\p|count [6] & ((\p|count [5]) # (\p|LessThan0~3_combout )))) ) ) )
+
+	.dataa(!\p|d [6]),
+	.datab(!\p|count [6]),
+	.datac(!\p|LessThan0~3_combout ),
+	.datad(!\p|count [5]),
+	.datae(!\p|d [5]),
+	.dataf(!\p|LessThan0~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~4 .extended_lut = "off";
+defparam \p|LessThan0~4 .lut_mask = 64'h2BBB222B00000000;
+defparam \p|LessThan0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y2_N54
+cyclonev_lcell_comb \p|LessThan0~5 (
+// Equation(s):
+// \p|LessThan0~5_combout  = ( \p|LessThan0~4_combout  & ( \p|count [8] & ( (!\p|count [9] & \p|d [9]) ) ) ) # ( !\p|LessThan0~4_combout  & ( \p|count [8] & ( (!\p|count [9] & (((\p|d [8] & !\p|LessThan0~0_combout )) # (\p|d [9]))) # (\p|count [9] & (\p|d 
+// [9] & (\p|d [8] & !\p|LessThan0~0_combout ))) ) ) ) # ( \p|LessThan0~4_combout  & ( !\p|count [8] & ( (!\p|count [9] & ((\p|d [8]) # (\p|d [9]))) # (\p|count [9] & (\p|d [9] & \p|d [8])) ) ) ) # ( !\p|LessThan0~4_combout  & ( !\p|count [8] & ( (!\p|count 
+// [9] & (((!\p|LessThan0~0_combout ) # (\p|d [8])) # (\p|d [9]))) # (\p|count [9] & (\p|d [9] & ((!\p|LessThan0~0_combout ) # (\p|d [8])))) ) ) )
+
+	.dataa(!\p|count [9]),
+	.datab(!\p|d [9]),
+	.datac(!\p|d [8]),
+	.datad(!\p|LessThan0~0_combout ),
+	.datae(!\p|LessThan0~4_combout ),
+	.dataf(!\p|count [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~5 .extended_lut = "off";
+defparam \p|LessThan0~5 .lut_mask = 64'hBB2B2B2B2B222222;
+defparam \p|LessThan0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y2_N55
+dffeas \p|pwm_out (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|LessThan0~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|pwm_out~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|pwm_out .is_wysiwyg = "true";
+defparam \p|pwm_out .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N54
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[1][17]~5 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[1][17]~5_combout  = ( \SW[7]~input_o  & ( (\SW[5]~input_o  & \SW[6]~input_o ) ) )
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(gnd),
+	.datac(!\SW[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[1][17]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[1][17]~5 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[1][17]~5 .lut_mask = 64'h0000000005050505;
+defparam \mult|lpm_mult_component|mult_core|romout[1][17]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N57
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[0][17]~4 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[0][17]~4_combout  = ( \SW[3]~input_o  & ( \SW[1]~input_o  & ( \SW[2]~input_o  ) ) )
+
+	.dataa(!\SW[2]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SW[3]~input_o ),
+	.dataf(!\SW[1]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[0][17]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[0][17]~4 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[0][17]~4 .lut_mask = 64'h0000000000005555;
+defparam \mult|lpm_mult_component|mult_core|romout[0][17]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N12
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[0][16]~3 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[0][16]~3_combout  = ( \SW[3]~input_o  & ( \SW[1]~input_o  & ( !\SW[2]~input_o  ) ) ) # ( !\SW[3]~input_o  & ( \SW[1]~input_o  & ( (\SW[0]~input_o  & \SW[2]~input_o ) ) ) ) # ( \SW[3]~input_o  & ( !\SW[1]~input_o  
+// ) )
+
+	.dataa(gnd),
+	.datab(!\SW[0]~input_o ),
+	.datac(!\SW[2]~input_o ),
+	.datad(gnd),
+	.datae(!\SW[3]~input_o ),
+	.dataf(!\SW[1]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[0][16]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[0][16]~3 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[0][16]~3 .lut_mask = 64'h0000FFFF0303F0F0;
+defparam \mult|lpm_mult_component|mult_core|romout[0][16]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N6
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[0][15]~2 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[0][15]~2_combout  = ( \SW[3]~input_o  & ( \SW[1]~input_o  & ( !\SW[2]~input_o  ) ) ) # ( !\SW[3]~input_o  & ( \SW[1]~input_o  & ( (!\SW[0]~input_o  & \SW[2]~input_o ) ) ) ) # ( \SW[3]~input_o  & ( !\SW[1]~input_o  
+// & ( \SW[2]~input_o  ) ) ) # ( !\SW[3]~input_o  & ( !\SW[1]~input_o  & ( \SW[2]~input_o  ) ) )
+
+	.dataa(gnd),
+	.datab(!\SW[0]~input_o ),
+	.datac(!\SW[2]~input_o ),
+	.datad(gnd),
+	.datae(!\SW[3]~input_o ),
+	.dataf(!\SW[1]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[0][15]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[0][15]~2 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[0][15]~2 .lut_mask = 64'h0F0F0F0F0C0CF0F0;
+defparam \mult|lpm_mult_component|mult_core|romout[0][15]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N27
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[0][14]~1 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[0][14]~1_combout  = ( \SW[3]~input_o  & ( \SW[1]~input_o  & ( (\SW[2]~input_o  & \SW[0]~input_o ) ) ) ) # ( !\SW[3]~input_o  & ( \SW[1]~input_o  & ( (!\SW[2]~input_o ) # (!\SW[0]~input_o ) ) ) ) # ( \SW[3]~input_o 
+//  & ( !\SW[1]~input_o  & ( (\SW[0]~input_o ) # (\SW[2]~input_o ) ) ) ) # ( !\SW[3]~input_o  & ( !\SW[1]~input_o  & ( (\SW[2]~input_o  & \SW[0]~input_o ) ) ) )
+
+	.dataa(!\SW[2]~input_o ),
+	.datab(gnd),
+	.datac(!\SW[0]~input_o ),
+	.datad(gnd),
+	.datae(!\SW[3]~input_o ),
+	.dataf(!\SW[1]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[0][14]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[0][14]~1 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[0][14]~1 .lut_mask = 64'h05055F5FFAFA0505;
+defparam \mult|lpm_mult_component|mult_core|romout[0][14]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N57
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[1][9]~0 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[1][9]~0_combout  = ( \SW[4]~input_o  & ( !\SW[5]~input_o  ) ) # ( !\SW[4]~input_o  & ( \SW[5]~input_o  ) )
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[4]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[1][9]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[1][9]~0 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[1][9]~0 .lut_mask = 64'h55555555AAAAAAAA;
+defparam \mult|lpm_mult_component|mult_core|romout[1][9]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N0
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout  = CARRY(( GND ) + ( GND ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 .lut_mask = 64'h0000FFFF00000000;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N3
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout  = CARRY(( \SW[1]~input_o  ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout  ))
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 .lut_mask = 64'h0000FFFF00005555;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N6
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout  = CARRY(( \SW[2]~input_o  ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout  ))
+
+	.dataa(gnd),
+	.datab(!\SW[2]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 .lut_mask = 64'h0000FFFF00003333;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N9
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout  = CARRY(( \SW[3]~input_o  ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SW[3]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N12
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout  = CARRY(( \SW[0]~input_o  ) + ( \SW[4]~input_o  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout  ))
+
+	.dataa(gnd),
+	.datab(!\SW[0]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[4]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .lut_mask = 64'h0000FF0000003333;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N15
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout  = CARRY(( \SW[5]~input_o  ) + ( !\SW[0]~input_o  $ (!\SW[1]~input_o ) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout  ))
+
+	.dataa(gnd),
+	.datab(!\SW[0]~input_o ),
+	.datac(gnd),
+	.datad(!\SW[5]~input_o ),
+	.datae(gnd),
+	.dataf(!\SW[1]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 .lut_mask = 64'h0000CC33000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N18
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  = SUM(( \SW[6]~input_o  ) + ( !\SW[2]~input_o  $ (((!\SW[1]~input_o  & !\SW[0]~input_o ))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  = CARRY(( \SW[6]~input_o  ) + ( !\SW[2]~input_o  $ (((!\SW[1]~input_o  & !\SW[0]~input_o ))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout  ))
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(!\SW[2]~input_o ),
+	.datac(!\SW[0]~input_o ),
+	.datad(!\SW[6]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .lut_mask = 64'h00009393000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N21
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  = SUM(( !\SW[3]~input_o  $ ((((!\SW[1]~input_o  & !\SW[2]~input_o )) # (\SW[0]~input_o ))) ) + ( \SW[7]~input_o  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  = CARRY(( !\SW[3]~input_o  $ ((((!\SW[1]~input_o  & !\SW[2]~input_o )) # (\SW[0]~input_o ))) ) + ( \SW[7]~input_o  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  ))
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(!\SW[2]~input_o ),
+	.datac(!\SW[0]~input_o ),
+	.datad(!\SW[3]~input_o ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .lut_mask = 64'h0000FF000000708F;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N24
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  = SUM(( (!\SW[1]~input_o  & (((\SW[2]~input_o  & !\SW[0]~input_o )) # (\SW[3]~input_o ))) # (\SW[1]~input_o  & (((\SW[0]~input_o  & !\SW[3]~input_o )))) ) + ( \SW[4]~input_o 
+//  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  = CARRY(( (!\SW[1]~input_o  & (((\SW[2]~input_o  & !\SW[0]~input_o )) # (\SW[3]~input_o ))) # (\SW[1]~input_o  & (((\SW[0]~input_o  & !\SW[3]~input_o )))) ) + ( \SW[4]~input_o  ) + 
+// ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  ))
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(!\SW[2]~input_o ),
+	.datac(!\SW[0]~input_o ),
+	.datad(!\SW[3]~input_o ),
+	.datae(gnd),
+	.dataf(!\SW[4]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .lut_mask = 64'h0000FF00000025AA;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N27
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  = SUM(( (!\SW[1]~input_o  & ((!\SW[2]~input_o  & (!\SW[0]~input_o  $ (!\SW[3]~input_o ))) # (\SW[2]~input_o  & (\SW[0]~input_o  & \SW[3]~input_o )))) # (\SW[1]~input_o  & 
+// (!\SW[2]~input_o  $ ((!\SW[0]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|romout[1][9]~0_combout  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  = CARRY(( (!\SW[1]~input_o  & ((!\SW[2]~input_o  & (!\SW[0]~input_o  $ (!\SW[3]~input_o ))) # (\SW[2]~input_o  & (\SW[0]~input_o  & \SW[3]~input_o )))) # (\SW[1]~input_o  & 
+// (!\SW[2]~input_o  $ ((!\SW[0]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|romout[1][9]~0_combout  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  ))
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(!\SW[2]~input_o ),
+	.datac(!\SW[0]~input_o ),
+	.datad(!\SW[3]~input_o ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|romout[1][9]~0_combout ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .lut_mask = 64'h0000FF0000001C96;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N30
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  = SUM(( \mult|lpm_mult_component|mult_core|romout[0][14]~1_combout  ) + ( !\SW[6]~input_o  $ (((!\SW[5]~input_o  & !\SW[4]~input_o ))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  = CARRY(( \mult|lpm_mult_component|mult_core|romout[0][14]~1_combout  ) + ( !\SW[6]~input_o  $ (((!\SW[5]~input_o  & !\SW[4]~input_o ))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  ))
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(!\SW[4]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\mult|lpm_mult_component|mult_core|romout[0][14]~1_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .lut_mask = 64'h00008787000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N33
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  = SUM(( \mult|lpm_mult_component|mult_core|romout[0][15]~2_combout  ) + ( !\SW[7]~input_o  $ ((((!\SW[5]~input_o  & !\SW[6]~input_o )) # (\SW[4]~input_o ))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  = CARRY(( \mult|lpm_mult_component|mult_core|romout[0][15]~2_combout  ) + ( !\SW[7]~input_o  $ ((((!\SW[5]~input_o  & !\SW[6]~input_o )) # (\SW[4]~input_o ))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  ))
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(!\SW[4]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\mult|lpm_mult_component|mult_core|romout[0][15]~2_combout ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .lut_mask = 64'h0000B34C000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N36
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  = SUM(( \mult|lpm_mult_component|mult_core|romout[0][16]~3_combout  ) + ( (!\SW[5]~input_o  & (((!\SW[4]~input_o  & \SW[6]~input_o )) # (\SW[7]~input_o ))) # (\SW[5]~input_o 
+//  & (\SW[4]~input_o  & ((!\SW[7]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30  = CARRY(( \mult|lpm_mult_component|mult_core|romout[0][16]~3_combout  ) + ( (!\SW[5]~input_o  & (((!\SW[4]~input_o  & \SW[6]~input_o )) # (\SW[7]~input_o ))) # (\SW[5]~input_o  & 
+// (\SW[4]~input_o  & ((!\SW[7]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  ))
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(!\SW[4]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\mult|lpm_mult_component|mult_core|romout[0][16]~3_combout ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .lut_mask = 64'h0000E655000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N39
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  = SUM(( \mult|lpm_mult_component|mult_core|romout[0][17]~4_combout  ) + ( (!\SW[5]~input_o  & ((!\SW[4]~input_o  & (!\SW[6]~input_o  & \SW[7]~input_o )) # (\SW[4]~input_o  & 
+// (!\SW[6]~input_o  $ (\SW[7]~input_o ))))) # (\SW[5]~input_o  & (!\SW[4]~input_o  $ ((!\SW[6]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34  = CARRY(( \mult|lpm_mult_component|mult_core|romout[0][17]~4_combout  ) + ( (!\SW[5]~input_o  & ((!\SW[4]~input_o  & (!\SW[6]~input_o  & \SW[7]~input_o )) # (\SW[4]~input_o  & 
+// (!\SW[6]~input_o  $ (\SW[7]~input_o ))))) # (\SW[5]~input_o  & (!\SW[4]~input_o  $ ((!\SW[6]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30  ))
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(!\SW[4]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\mult|lpm_mult_component|mult_core|romout[0][17]~4_combout ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .lut_mask = 64'h0000CB69000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N42
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout  = SUM(( GND ) + ( (!\SW[5]~input_o  & ((!\SW[4]~input_o  & (\SW[6]~input_o  & \SW[7]~input_o )) # (\SW[4]~input_o  & ((\SW[7]~input_o ) # (\SW[6]~input_o ))))) # 
+// (\SW[5]~input_o  & (!\SW[7]~input_o  $ (((\SW[4]~input_o  & \SW[6]~input_o ))))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  = CARRY(( GND ) + ( (!\SW[5]~input_o  & ((!\SW[4]~input_o  & (\SW[6]~input_o  & \SW[7]~input_o )) # (\SW[4]~input_o  & ((\SW[7]~input_o ) # (\SW[6]~input_o ))))) # (\SW[5]~input_o  
+// & (!\SW[7]~input_o  $ (((\SW[4]~input_o  & \SW[6]~input_o ))))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34  ))
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(!\SW[4]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .lut_mask = 64'h0000A9D400000000;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N45
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout  = SUM(( GND ) + ( (!\SW[5]~input_o  & (((\SW[6]~input_o )))) # (\SW[5]~input_o  & ((!\SW[6]~input_o  & ((\SW[7]~input_o ))) # (\SW[6]~input_o  & (!\SW[4]~input_o  & 
+// !\SW[7]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42  = CARRY(( GND ) + ( (!\SW[5]~input_o  & (((\SW[6]~input_o )))) # (\SW[5]~input_o  & ((!\SW[6]~input_o  & ((\SW[7]~input_o ))) # (\SW[6]~input_o  & (!\SW[4]~input_o  & 
+// !\SW[7]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  ))
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(!\SW[4]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 .lut_mask = 64'h0000F1A500000000;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N48
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout  = SUM(( GND ) + ( (!\SW[6]~input_o  & (((\SW[7]~input_o )))) # (\SW[6]~input_o  & ((!\SW[5]~input_o  & ((\SW[7]~input_o ))) # (\SW[5]~input_o  & (\SW[4]~input_o  & 
+// !\SW[7]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46  = CARRY(( GND ) + ( (!\SW[6]~input_o  & (((\SW[7]~input_o )))) # (\SW[6]~input_o  & ((!\SW[5]~input_o  & ((\SW[7]~input_o ))) # (\SW[5]~input_o  & (\SW[4]~input_o  & 
+// !\SW[7]~input_o )))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42  ))
+
+	.dataa(!\SW[6]~input_o ),
+	.datab(!\SW[4]~input_o ),
+	.datac(!\SW[5]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 .lut_mask = 64'h0000FE0500000000;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y5_N51
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout  = SUM(( \mult|lpm_mult_component|mult_core|romout[1][17]~5_combout  ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|romout[1][17]~5_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 .lut_mask = 64'h0000FFFF000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N0
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  = SUM(( \SW[8]~input_o  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  ) + ( !VCC ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  = CARRY(( \SW[8]~input_o  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SW[8]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .lut_mask = 64'h0000FF0000000F0F;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N3
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  ) + ( \SW[9]~input_o  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  ) + ( \SW[9]~input_o  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  ))
+
+	.dataa(!\SW[9]~input_o ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .lut_mask = 64'h0000AAAA00000F0F;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N6
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  ))
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .lut_mask = 64'h0000FFFF00003333;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N9
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  ))
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .lut_mask = 64'h0000FFFF00005555;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N12
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  ))
+
+	.dataa(!\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .lut_mask = 64'h0000AAAA00000F0F;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N15
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  = SUM(( !\SW[8]~input_o  $ (!\SW[9]~input_o ) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  = CARRY(( !\SW[8]~input_o  $ (!\SW[9]~input_o ) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  ))
+
+	.dataa(!\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ),
+	.datad(!\SW[9]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .lut_mask = 64'h0000F0F0000055AA;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N18
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout  ) + ( (\SW[9]~input_o ) # (\SW[8]~input_o ) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout  ) + ( (\SW[9]~input_o ) # (\SW[8]~input_o ) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  ))
+
+	.dataa(!\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(!\SW[9]~input_o ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .lut_mask = 64'h0000A0A0000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N21
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  = SUM(( (!\SW[8]~input_o  & \SW[9]~input_o ) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  = CARRY(( (!\SW[8]~input_o  & \SW[9]~input_o ) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  ))
+
+	.dataa(!\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout ),
+	.datad(!\SW[9]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .lut_mask = 64'h0000F0F0000000AA;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N24
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  = SUM(( (\SW[8]~input_o  & \SW[9]~input_o ) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34  = CARRY(( (\SW[8]~input_o  & \SW[9]~input_o ) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  ))
+
+	.dataa(!\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\SW[9]~input_o ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .lut_mask = 64'h0000FF0000000055;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N27
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34  ))
+
+	.dataa(!\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .lut_mask = 64'h0000AAAA00000F0F;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N30
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  = SUM(( GND ) + ( \SW[9]~input_o  ) + ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42  = CARRY(( GND ) + ( \SW[9]~input_o  ) + ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SW[9]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 .lut_mask = 64'h0000F0F000000000;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N33
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  = SUM(( GND ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 .lut_mask = 64'h0000FFFF00000000;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N0
+cyclonev_lcell_comb \bcd|A2|WideOr3~0 (
+// Equation(s):
+// \bcd|A2|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  $ (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A2|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A2|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A2|WideOr3~0 .lut_mask = 64'h0F300F30C30CC30C;
+defparam \bcd|A2|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N42
+cyclonev_lcell_comb \bcd|A2|WideOr2~0 (
+// Equation(s):
+// \bcd|A2|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A2|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A2|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A2|WideOr2~0 .lut_mask = 64'h33033303C0CCC0CC;
+defparam \bcd|A2|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N45
+cyclonev_lcell_comb \bcd|A2|WideOr1~0 (
+// Equation(s):
+// \bcd|A2|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  $ (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ))) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A2|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A2|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A2|WideOr1~0 .lut_mask = 64'h0909090940404040;
+defparam \bcd|A2|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N21
+cyclonev_lcell_comb \bcd|A4|WideOr1~0 (
+// Equation(s):
+// \bcd|A4|WideOr1~0_combout  = (!\bcd|A2|WideOr2~0_combout  & (\bcd|A2|WideOr1~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ) # (\bcd|A2|WideOr3~0_combout )))) # (\bcd|A2|WideOr2~0_combout  & 
+// (!\bcd|A2|WideOr3~0_combout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout )))
+
+	.dataa(!\bcd|A2|WideOr3~0_combout ),
+	.datab(!\bcd|A2|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(!\bcd|A2|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A4|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A4|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A4|WideOr1~0 .lut_mask = 64'h206C206C206C206C;
+defparam \bcd|A4|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N15
+cyclonev_lcell_comb \bcd|A4|WideOr3~0 (
+// Equation(s):
+// \bcd|A4|WideOr3~0_combout  = ( \bcd|A2|WideOr2~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (!\bcd|A2|WideOr3~0_combout  $ (!\bcd|A2|WideOr1~0_combout ))) ) ) # ( 
+// !\bcd|A2|WideOr2~0_combout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  $ (!\bcd|A2|WideOr1~0_combout ) ) )
+
+	.dataa(!\bcd|A2|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(!\bcd|A2|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A2|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A4|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A4|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A4|WideOr3~0 .lut_mask = 64'h0FF00FF050A050A0;
+defparam \bcd|A4|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N18
+cyclonev_lcell_comb \bcd|A4|WideOr2~0 (
+// Equation(s):
+// \bcd|A4|WideOr2~0_combout  = (!\bcd|A2|WideOr3~0_combout  & (((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & \bcd|A2|WideOr1~0_combout )))) # (\bcd|A2|WideOr3~0_combout  & ((!\bcd|A2|WideOr2~0_combout  & 
+// ((!\bcd|A2|WideOr1~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ))) # (\bcd|A2|WideOr2~0_combout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\bcd|A2|WideOr1~0_combout ))))
+
+	.dataa(!\bcd|A2|WideOr3~0_combout ),
+	.datab(!\bcd|A2|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(!\bcd|A2|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A4|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A4|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A4|WideOr2~0 .lut_mask = 64'h45A445A445A445A4;
+defparam \bcd|A4|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N27
+cyclonev_lcell_comb \bcd|A6|WideOr3~0 (
+// Equation(s):
+// \bcd|A6|WideOr3~0_combout  = ( \bcd|A4|WideOr2~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & (!\bcd|A4|WideOr1~0_combout  $ (!\bcd|A4|WideOr3~0_combout ))) ) ) # ( 
+// !\bcd|A4|WideOr2~0_combout  & ( !\bcd|A4|WideOr1~0_combout  $ (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) ) )
+
+	.dataa(!\bcd|A4|WideOr1~0_combout ),
+	.datab(!\bcd|A4|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A4|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A6|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A6|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A6|WideOr3~0 .lut_mask = 64'h55AA55AA66006600;
+defparam \bcd|A6|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N6
+cyclonev_lcell_comb \bcd|A6|WideOr2~0 (
+// Equation(s):
+// \bcd|A6|WideOr2~0_combout  = ( \bcd|A4|WideOr2~0_combout  & ( (!\bcd|A4|WideOr3~0_combout  & (\bcd|A4|WideOr1~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout )) # (\bcd|A4|WideOr3~0_combout  & 
+// (!\bcd|A4|WideOr1~0_combout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout )) ) ) # ( !\bcd|A4|WideOr2~0_combout  & ( !\bcd|A4|WideOr3~0_combout  $ (((!\bcd|A4|WideOr1~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A4|WideOr3~0_combout ),
+	.datac(!\bcd|A4|WideOr1~0_combout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A4|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A6|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A6|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A6|WideOr2~0 .lut_mask = 64'h3C333C330C300C30;
+defparam \bcd|A6|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N9
+cyclonev_lcell_comb \bcd|A6|WideOr1~0 (
+// Equation(s):
+// \bcd|A6|WideOr1~0_combout  = ( \bcd|A4|WideOr2~0_combout  & ( (!\bcd|A4|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) ) ) # ( !\bcd|A4|WideOr2~0_combout  & ( (\bcd|A4|WideOr1~0_combout 
+//  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) # (\bcd|A4|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A4|WideOr1~0_combout ),
+	.datab(!\bcd|A4|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A4|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A6|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A6|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A6|WideOr1~0 .lut_mask = 64'h11551155CC00CC00;
+defparam \bcd|A6|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N30
+cyclonev_lcell_comb \bcd|A8|WideOr2~0 (
+// Equation(s):
+// \bcd|A8|WideOr2~0_combout  = ( \bcd|A6|WideOr1~0_combout  & ( (!\bcd|A6|WideOr3~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) # (\bcd|A6|WideOr3~0_combout  & (!\bcd|A6|WideOr2~0_combout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )) ) ) # ( !\bcd|A6|WideOr1~0_combout  & ( (\bcd|A6|WideOr3~0_combout  & ((!\bcd|A6|WideOr2~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) ) )
+
+	.dataa(!\bcd|A6|WideOr3~0_combout ),
+	.datab(!\bcd|A6|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A6|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A8|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A8|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A8|WideOr2~0 .lut_mask = 64'h45454545A4A4A4A4;
+defparam \bcd|A8|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N39
+cyclonev_lcell_comb \bcd|A8|WideOr3~0 (
+// Equation(s):
+// \bcd|A8|WideOr3~0_combout  = ( \bcd|A6|WideOr1~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ((!\bcd|A6|WideOr3~0_combout ) # (!\bcd|A6|WideOr2~0_combout ))) ) ) # ( 
+// !\bcd|A6|WideOr1~0_combout  & ( (!\bcd|A6|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) # (\bcd|A6|WideOr2~0_combout  & (\bcd|A6|WideOr3~0_combout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )) ) )
+
+	.dataa(!\bcd|A6|WideOr3~0_combout ),
+	.datab(!\bcd|A6|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A6|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A8|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A8|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A8|WideOr3~0 .lut_mask = 64'h11CC11CCEE00EE00;
+defparam \bcd|A8|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N33
+cyclonev_lcell_comb \bcd|A8|WideOr1~0 (
+// Equation(s):
+// \bcd|A8|WideOr1~0_combout  = ( \bcd|A6|WideOr1~0_combout  & ( !\bcd|A6|WideOr2~0_combout  $ (((!\bcd|A6|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) ) ) # ( 
+// !\bcd|A6|WideOr1~0_combout  & ( (!\bcd|A6|WideOr3~0_combout  & (\bcd|A6|WideOr2~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )) ) )
+
+	.dataa(!\bcd|A6|WideOr3~0_combout ),
+	.datab(!\bcd|A6|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A6|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A8|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A8|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A8|WideOr1~0 .lut_mask = 64'h2200220066CC66CC;
+defparam \bcd|A8|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N57
+cyclonev_lcell_comb \bcd|A11|WideOr1~0 (
+// Equation(s):
+// \bcd|A11|WideOr1~0_combout  = ( \bcd|A8|WideOr1~0_combout  & ( !\bcd|A8|WideOr2~0_combout  $ (((!\bcd|A8|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) ) ) # ( 
+// !\bcd|A8|WideOr1~0_combout  & ( (\bcd|A8|WideOr2~0_combout  & (!\bcd|A8|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) )
+
+	.dataa(!\bcd|A8|WideOr2~0_combout ),
+	.datab(!\bcd|A8|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A11|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A11|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A11|WideOr1~0 .lut_mask = 64'h4400440066AA66AA;
+defparam \bcd|A11|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N54
+cyclonev_lcell_comb \bcd|A11|WideOr2~0 (
+// Equation(s):
+// \bcd|A11|WideOr2~0_combout  = ( \bcd|A8|WideOr1~0_combout  & ( (!\bcd|A8|WideOr3~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) # (\bcd|A8|WideOr3~0_combout  & (!\bcd|A8|WideOr2~0_combout  
+// & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) ) # ( !\bcd|A8|WideOr1~0_combout  & ( (\bcd|A8|WideOr3~0_combout  & ((!\bcd|A8|WideOr2~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) ) )
+
+	.dataa(!\bcd|A8|WideOr2~0_combout ),
+	.datab(!\bcd|A8|WideOr3~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A11|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A11|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A11|WideOr2~0 .lut_mask = 64'h23232323C2C2C2C2;
+defparam \bcd|A11|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N51
+cyclonev_lcell_comb \bcd|A11|WideOr3~0 (
+// Equation(s):
+// \bcd|A11|WideOr3~0_combout  = ( \bcd|A8|WideOr1~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & ((!\bcd|A8|WideOr2~0_combout ) # (!\bcd|A8|WideOr3~0_combout ))) ) ) # ( 
+// !\bcd|A8|WideOr1~0_combout  & ( (!\bcd|A8|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) # (\bcd|A8|WideOr2~0_combout  & (\bcd|A8|WideOr3~0_combout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) )
+
+	.dataa(!\bcd|A8|WideOr2~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A8|WideOr3~0_combout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A11|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A11|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A11|WideOr3~0 .lut_mask = 64'h05AA05AAFA00FA00;
+defparam \bcd|A11|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N36
+cyclonev_lcell_comb \bcd|A14|WideOr3~0 (
+// Equation(s):
+// \bcd|A14|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( \bcd|A11|WideOr3~0_combout  & ( (!\bcd|A11|WideOr1~0_combout  & !\bcd|A11|WideOr2~0_combout ) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( \bcd|A11|WideOr3~0_combout  & ( !\bcd|A11|WideOr1~0_combout  $ (!\bcd|A11|WideOr2~0_combout ) ) ) ) # ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr3~0_combout  & ( (!\bcd|A11|WideOr1~0_combout  & !\bcd|A11|WideOr2~0_combout ) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr3~0_combout  & ( \bcd|A11|WideOr1~0_combout  ) ) )
+
+	.dataa(!\bcd|A11|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A11|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.dataf(!\bcd|A11|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A14|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A14|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A14|WideOr3~0 .lut_mask = 64'h5555A0A05A5AA0A0;
+defparam \bcd|A14|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N57
+cyclonev_lcell_comb \bcd|A14|WideOr2~0 (
+// Equation(s):
+// \bcd|A14|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( \bcd|A11|WideOr2~0_combout  & ( (!\bcd|A11|WideOr1~0_combout  & \bcd|A11|WideOr3~0_combout ) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( \bcd|A11|WideOr2~0_combout  & ( (\bcd|A11|WideOr1~0_combout  & !\bcd|A11|WideOr3~0_combout ) ) ) ) # ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr2~0_combout  & ( \bcd|A11|WideOr3~0_combout  ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr2~0_combout  & ( !\bcd|A11|WideOr1~0_combout  $ (!\bcd|A11|WideOr3~0_combout ) ) ) )
+
+	.dataa(!\bcd|A11|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A11|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.dataf(!\bcd|A11|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A14|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A14|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A14|WideOr2~0 .lut_mask = 64'h5A5A0F0F50500A0A;
+defparam \bcd|A14|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N24
+cyclonev_lcell_comb \bcd|A14|WideOr1~0 (
+// Equation(s):
+// \bcd|A14|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( \bcd|A11|WideOr3~0_combout  & ( (\bcd|A11|WideOr1~0_combout  & !\bcd|A11|WideOr2~0_combout ) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( \bcd|A11|WideOr3~0_combout  & ( (\bcd|A11|WideOr1~0_combout  & !\bcd|A11|WideOr2~0_combout ) ) ) ) # ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr3~0_combout  & ( (\bcd|A11|WideOr1~0_combout  & !\bcd|A11|WideOr2~0_combout ) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr3~0_combout  & ( \bcd|A11|WideOr2~0_combout  ) ) )
+
+	.dataa(!\bcd|A11|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A11|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.dataf(!\bcd|A11|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A14|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A14|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A14|WideOr1~0 .lut_mask = 64'h0F0F505050505050;
+defparam \bcd|A14|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N42
+cyclonev_lcell_comb \bcd|A17|WideOr2~0 (
+// Equation(s):
+// \bcd|A17|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & ( (\bcd|A14|WideOr3~0_combout  & ((!\bcd|A14|WideOr2~0_combout ) # (!\bcd|A14|WideOr1~0_combout ))) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & ( (!\bcd|A14|WideOr3~0_combout  & ((\bcd|A14|WideOr1~0_combout ))) # (\bcd|A14|WideOr3~0_combout  & (!\bcd|A14|WideOr2~0_combout  & !\bcd|A14|WideOr1~0_combout 
+// )) ) )
+
+	.dataa(!\bcd|A14|WideOr3~0_combout ),
+	.datab(!\bcd|A14|WideOr2~0_combout ),
+	.datac(!\bcd|A14|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A17|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A17|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A17|WideOr2~0 .lut_mask = 64'h4A4A4A4A54545454;
+defparam \bcd|A17|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N0
+cyclonev_lcell_comb \bcd|A17|WideOr3~0 (
+// Equation(s):
+// \bcd|A17|WideOr3~0_combout  = ( \bcd|A14|WideOr2~0_combout  & ( \bcd|A14|WideOr3~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & !\bcd|A14|WideOr1~0_combout ) ) ) ) # ( 
+// !\bcd|A14|WideOr2~0_combout  & ( \bcd|A14|WideOr3~0_combout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  $ (!\bcd|A14|WideOr1~0_combout ) ) ) ) # ( \bcd|A14|WideOr2~0_combout  & ( 
+// !\bcd|A14|WideOr3~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & \bcd|A14|WideOr1~0_combout ) ) ) ) # ( !\bcd|A14|WideOr2~0_combout  & ( !\bcd|A14|WideOr3~0_combout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  $ (!\bcd|A14|WideOr1~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datac(!\bcd|A14|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A14|WideOr2~0_combout ),
+	.dataf(!\bcd|A14|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A17|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A17|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A17|WideOr3~0 .lut_mask = 64'h3C3C0C0C3C3CC0C0;
+defparam \bcd|A17|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N45
+cyclonev_lcell_comb \bcd|A17|WideOr1~0 (
+// Equation(s):
+// \bcd|A17|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & ( (!\bcd|A14|WideOr2~0_combout  & \bcd|A14|WideOr1~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & ( (!\bcd|A14|WideOr3~0_combout  & (\bcd|A14|WideOr2~0_combout )) # (\bcd|A14|WideOr3~0_combout  & (!\bcd|A14|WideOr2~0_combout  & \bcd|A14|WideOr1~0_combout )) 
+// ) )
+
+	.dataa(!\bcd|A14|WideOr3~0_combout ),
+	.datab(!\bcd|A14|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A14|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A17|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A17|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A17|WideOr1~0 .lut_mask = 64'h2266226600CC00CC;
+defparam \bcd|A17|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N6
+cyclonev_lcell_comb \bcd|A21|WideOr1~0 (
+// Equation(s):
+// \bcd|A21|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & ( (!\bcd|A17|WideOr2~0_combout  & \bcd|A17|WideOr1~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & ( (!\bcd|A17|WideOr2~0_combout  & (\bcd|A17|WideOr3~0_combout  & \bcd|A17|WideOr1~0_combout )) # (\bcd|A17|WideOr2~0_combout  & (!\bcd|A17|WideOr3~0_combout )) 
+// ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A17|WideOr2~0_combout ),
+	.datac(!\bcd|A17|WideOr3~0_combout ),
+	.datad(!\bcd|A17|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A21|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A21|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A21|WideOr1~0 .lut_mask = 64'h303C303C00CC00CC;
+defparam \bcd|A21|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N24
+cyclonev_lcell_comb \bcd|A21|WideOr3~0 (
+// Equation(s):
+// \bcd|A21|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & ( (!\bcd|A17|WideOr2~0_combout  & !\bcd|A17|WideOr1~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & ( !\bcd|A17|WideOr1~0_combout  $ (((!\bcd|A17|WideOr3~0_combout ) # (!\bcd|A17|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A17|WideOr3~0_combout ),
+	.datab(!\bcd|A17|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A17|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A21|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A21|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A21|WideOr3~0 .lut_mask = 64'h11EE11EECC00CC00;
+defparam \bcd|A21|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N27
+cyclonev_lcell_comb \bcd|A21|WideOr2~0 (
+// Equation(s):
+// \bcd|A21|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & ( (\bcd|A17|WideOr3~0_combout  & ((!\bcd|A17|WideOr2~0_combout ) # (!\bcd|A17|WideOr1~0_combout ))) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & ( (!\bcd|A17|WideOr3~0_combout  & ((\bcd|A17|WideOr1~0_combout ))) # (\bcd|A17|WideOr3~0_combout  & (!\bcd|A17|WideOr2~0_combout  & !\bcd|A17|WideOr1~0_combout 
+// )) ) )
+
+	.dataa(!\bcd|A17|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A17|WideOr2~0_combout ),
+	.datad(!\bcd|A17|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A21|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A21|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A21|WideOr2~0 .lut_mask = 64'h50AA50AA55505550;
+defparam \bcd|A21|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N48
+cyclonev_lcell_comb \bcd|A25|WideOr1~0 (
+// Equation(s):
+// \bcd|A25|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( (\bcd|A21|WideOr1~0_combout  & !\bcd|A21|WideOr2~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( (!\bcd|A21|WideOr3~0_combout  & ((\bcd|A21|WideOr2~0_combout ))) # (\bcd|A21|WideOr3~0_combout  & (\bcd|A21|WideOr1~0_combout  & !\bcd|A21|WideOr2~0_combout 
+// )) ) )
+
+	.dataa(!\bcd|A21|WideOr1~0_combout ),
+	.datab(!\bcd|A21|WideOr3~0_combout ),
+	.datac(!\bcd|A21|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A25|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A25|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A25|WideOr1~0 .lut_mask = 64'h1C1C1C1C50505050;
+defparam \bcd|A25|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N6
+cyclonev_lcell_comb \bcd|A25|WideOr2~0 (
+// Equation(s):
+// \bcd|A25|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( (\bcd|A21|WideOr3~0_combout  & ((!\bcd|A21|WideOr1~0_combout ) # (!\bcd|A21|WideOr2~0_combout ))) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( (!\bcd|A21|WideOr1~0_combout  & (\bcd|A21|WideOr3~0_combout  & !\bcd|A21|WideOr2~0_combout )) # (\bcd|A21|WideOr1~0_combout  & (!\bcd|A21|WideOr3~0_combout 
+// )) ) )
+
+	.dataa(!\bcd|A21|WideOr1~0_combout ),
+	.datab(!\bcd|A21|WideOr3~0_combout ),
+	.datac(!\bcd|A21|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A25|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A25|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A25|WideOr2~0 .lut_mask = 64'h6464646432323232;
+defparam \bcd|A25|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N51
+cyclonev_lcell_comb \bcd|A25|WideOr3~0 (
+// Equation(s):
+// \bcd|A25|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( (!\bcd|A21|WideOr1~0_combout  & !\bcd|A21|WideOr2~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\bcd|A21|WideOr1~0_combout  $ (((!\bcd|A21|WideOr3~0_combout ) # (!\bcd|A21|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A21|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A21|WideOr3~0_combout ),
+	.datad(!\bcd|A21|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A25|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A25|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A25|WideOr3~0 .lut_mask = 64'h555A555AAA00AA00;
+defparam \bcd|A25|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N0
+cyclonev_lcell_comb \bcd|A29|WideOr3~0 (
+// Equation(s):
+// \bcd|A29|WideOr3~0_combout  = ( \bcd|A25|WideOr3~0_combout  & ( (!\bcd|A25|WideOr1~0_combout  & (!\bcd|A25|WideOr2~0_combout  $ (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ))) # (\bcd|A25|WideOr1~0_combout  & 
+// (!\bcd|A25|WideOr2~0_combout  & !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout )) ) ) # ( !\bcd|A25|WideOr3~0_combout  & ( (!\bcd|A25|WideOr1~0_combout  & (!\bcd|A25|WideOr2~0_combout  & 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout )) # (\bcd|A25|WideOr1~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ))) ) )
+
+	.dataa(!\bcd|A25|WideOr1~0_combout ),
+	.datab(!\bcd|A25|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A29|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A29|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A29|WideOr3~0 .lut_mask = 64'h5858585868686868;
+defparam \bcd|A29|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N3
+cyclonev_lcell_comb \bcd|A29|WideOr2~0 (
+// Equation(s):
+// \bcd|A29|WideOr2~0_combout  = ( \bcd|A25|WideOr3~0_combout  & ( (!\bcd|A25|WideOr1~0_combout  & ((!\bcd|A25|WideOr2~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ))) # (\bcd|A25|WideOr1~0_combout  & 
+// (!\bcd|A25|WideOr2~0_combout  & \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout )) ) ) # ( !\bcd|A25|WideOr3~0_combout  & ( (\bcd|A25|WideOr1~0_combout  & 
+// !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ) ) )
+
+	.dataa(!\bcd|A25|WideOr1~0_combout ),
+	.datab(!\bcd|A25|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A29|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A29|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A29|WideOr2~0 .lut_mask = 64'h505050508E8E8E8E;
+defparam \bcd|A29|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N54
+cyclonev_lcell_comb \bcd|A29|WideOr1~0 (
+// Equation(s):
+// \bcd|A29|WideOr1~0_combout  = ( \bcd|A25|WideOr3~0_combout  & ( (\bcd|A25|WideOr1~0_combout  & !\bcd|A25|WideOr2~0_combout ) ) ) # ( !\bcd|A25|WideOr3~0_combout  & ( (!\bcd|A25|WideOr2~0_combout  & (\bcd|A25|WideOr1~0_combout  & 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout )) # (\bcd|A25|WideOr2~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ))) ) )
+
+	.dataa(!\bcd|A25|WideOr1~0_combout ),
+	.datab(!\bcd|A25|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A29|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A29|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A29|WideOr1~0 .lut_mask = 64'h3434343444444444;
+defparam \bcd|A29|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N36
+cyclonev_lcell_comb \h0|WideOr6~0 (
+// Equation(s):
+// \h0|WideOr6~0_combout  = (!\bcd|A29|WideOr2~0_combout  & (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & (!\bcd|A29|WideOr3~0_combout  $ (\bcd|A29|WideOr1~0_combout )))) # (\bcd|A29|WideOr2~0_combout  & 
+// (!\bcd|A29|WideOr3~0_combout  & (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  $ (\bcd|A29|WideOr1~0_combout ))))
+
+	.dataa(!\bcd|A29|WideOr3~0_combout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datac(!\bcd|A29|WideOr2~0_combout ),
+	.datad(!\bcd|A29|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr6~0 .extended_lut = "off";
+defparam \h0|WideOr6~0 .lut_mask = 64'h2812281228122812;
+defparam \h0|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N39
+cyclonev_lcell_comb \h0|WideOr5~0 (
+// Equation(s):
+// \h0|WideOr5~0_combout  = ( \bcd|A29|WideOr2~0_combout  & ( (!\bcd|A29|WideOr3~0_combout  & (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  $ (!\bcd|A29|WideOr1~0_combout ))) # (\bcd|A29|WideOr3~0_combout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ) # (\bcd|A29|WideOr1~0_combout ))) ) ) # ( !\bcd|A29|WideOr2~0_combout  & ( (\bcd|A29|WideOr3~0_combout  & 
+// (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & \bcd|A29|WideOr1~0_combout )) ) )
+
+	.dataa(!\bcd|A29|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(!\bcd|A29|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr5~0 .extended_lut = "off";
+defparam \h0|WideOr5~0 .lut_mask = 64'h000500055AF55AF5;
+defparam \h0|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N42
+cyclonev_lcell_comb \h0|WideOr4~0 (
+// Equation(s):
+// \h0|WideOr4~0_combout  = (!\bcd|A29|WideOr2~0_combout  & (\bcd|A29|WideOr3~0_combout  & (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & !\bcd|A29|WideOr1~0_combout ))) # (\bcd|A29|WideOr2~0_combout  & 
+// (\bcd|A29|WideOr1~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ) # (\bcd|A29|WideOr3~0_combout ))))
+
+	.dataa(!\bcd|A29|WideOr3~0_combout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datac(!\bcd|A29|WideOr2~0_combout ),
+	.datad(!\bcd|A29|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr4~0 .extended_lut = "off";
+defparam \h0|WideOr4~0 .lut_mask = 64'h400D400D400D400D;
+defparam \h0|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N24
+cyclonev_lcell_comb \h0|WideOr3~0 (
+// Equation(s):
+// \h0|WideOr3~0_combout  = (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & ((!\bcd|A29|WideOr3~0_combout  & (\bcd|A29|WideOr2~0_combout  & !\bcd|A29|WideOr1~0_combout )) # (\bcd|A29|WideOr3~0_combout  & 
+// (!\bcd|A29|WideOr2~0_combout  & \bcd|A29|WideOr1~0_combout )))) # (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & (!\bcd|A29|WideOr3~0_combout  $ ((\bcd|A29|WideOr2~0_combout ))))
+
+	.dataa(!\bcd|A29|WideOr3~0_combout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datac(!\bcd|A29|WideOr2~0_combout ),
+	.datad(!\bcd|A29|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr3~0 .extended_lut = "off";
+defparam \h0|WideOr3~0 .lut_mask = 64'h2961296129612961;
+defparam \h0|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N45
+cyclonev_lcell_comb \h0|WideOr2~0 (
+// Equation(s):
+// \h0|WideOr2~0_combout  = ( \bcd|A29|WideOr2~0_combout  & ( (!\bcd|A29|WideOr1~0_combout  & ((!\bcd|A29|WideOr3~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) ) ) # ( !\bcd|A29|WideOr2~0_combout  & ( 
+// (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & ((!\bcd|A29|WideOr3~0_combout ) # (!\bcd|A29|WideOr1~0_combout ))) ) )
+
+	.dataa(!\bcd|A29|WideOr3~0_combout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datac(gnd),
+	.datad(!\bcd|A29|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr2~0 .extended_lut = "off";
+defparam \h0|WideOr2~0 .lut_mask = 64'h33223322BB00BB00;
+defparam \h0|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N30
+cyclonev_lcell_comb \h0|WideOr1~0 (
+// Equation(s):
+// \h0|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & ( !\bcd|A29|WideOr1~0_combout  $ (((!\bcd|A29|WideOr3~0_combout  & \bcd|A29|WideOr2~0_combout ))) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & ( (!\bcd|A29|WideOr1~0_combout  & (\bcd|A29|WideOr3~0_combout  & !\bcd|A29|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A29|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A29|WideOr3~0_combout ),
+	.datad(!\bcd|A29|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr1~0 .extended_lut = "off";
+defparam \h0|WideOr1~0 .lut_mask = 64'h0A000A00AA5AAA5A;
+defparam \h0|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N27
+cyclonev_lcell_comb \h0|WideOr0~0 (
+// Equation(s):
+// \h0|WideOr0~0_combout  = ( \bcd|A29|WideOr2~0_combout  & ( (!\bcd|A29|WideOr3~0_combout  & ((!\bcd|A29|WideOr1~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) # (\bcd|A29|WideOr3~0_combout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ) # (\bcd|A29|WideOr1~0_combout ))) ) ) # ( !\bcd|A29|WideOr2~0_combout  & ( (\bcd|A29|WideOr1~0_combout ) # (\bcd|A29|WideOr3~0_combout ) ) )
+
+	.dataa(!\bcd|A29|WideOr3~0_combout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datac(gnd),
+	.datad(!\bcd|A29|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr0~0 .extended_lut = "off";
+defparam \h0|WideOr0~0 .lut_mask = 64'h55FF55FFEE77EE77;
+defparam \h0|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N0
+cyclonev_lcell_comb \bcd|A7|WideOr2~0 (
+// Equation(s):
+// \bcd|A7|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  $ (((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) ) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))))) ) ) ) # ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )))) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )))) ) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A7|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A7|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A7|WideOr2~0 .lut_mask = 64'h118815887611EE11;
+defparam \bcd|A7|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N42
+cyclonev_lcell_comb \bcd|A7|WideOr3~0 (
+// Equation(s):
+// \bcd|A7|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout )))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )))) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) # ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )))) ) ) ) # ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  $ (((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )))) ) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  $ (((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))) ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A7|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A7|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A7|WideOr3~0 .lut_mask = 64'h46886289DC444666;
+defparam \bcd|A7|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N36
+cyclonev_lcell_comb \bcd|A8|WideOr0~0 (
+// Equation(s):
+// \bcd|A8|WideOr0~0_combout  = ( \bcd|A6|WideOr1~0_combout  & ( (!\bcd|A6|WideOr2~0_combout ) # ((!\bcd|A6|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )) ) ) # ( 
+// !\bcd|A6|WideOr1~0_combout  & ( (\bcd|A6|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ) # (\bcd|A6|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A6|WideOr3~0_combout ),
+	.datab(!\bcd|A6|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A6|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A8|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A8|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A8|WideOr0~0 .lut_mask = 64'h13131313ECECECEC;
+defparam \bcd|A8|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N30
+cyclonev_lcell_comb \bcd|A7|WideOr1~0 (
+// Equation(s):
+// \bcd|A7|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) ) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))) ) ) ) # ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  $ 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A7|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A7|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A7|WideOr1~0 .lut_mask = 64'h0066002201801100;
+defparam \bcd|A7|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N30
+cyclonev_lcell_comb \bcd|A10|WideOr1~0 (
+// Equation(s):
+// \bcd|A10|WideOr1~0_combout  = ( \bcd|A7|WideOr1~0_combout  & ( !\bcd|A7|WideOr2~0_combout  $ (((!\bcd|A7|WideOr3~0_combout  & !\bcd|A8|WideOr0~0_combout ))) ) ) # ( !\bcd|A7|WideOr1~0_combout  & ( (\bcd|A7|WideOr2~0_combout  & (!\bcd|A7|WideOr3~0_combout  
+// & !\bcd|A8|WideOr0~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A7|WideOr2~0_combout ),
+	.datac(!\bcd|A7|WideOr3~0_combout ),
+	.datad(!\bcd|A8|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A7|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A10|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A10|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A10|WideOr1~0 .lut_mask = 64'h300030003CCC3CCC;
+defparam \bcd|A10|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N48
+cyclonev_lcell_comb \bcd|A11|WideOr0~0 (
+// Equation(s):
+// \bcd|A11|WideOr0~0_combout  = ( \bcd|A8|WideOr1~0_combout  & ( (!\bcd|A8|WideOr2~0_combout ) # ((!\bcd|A8|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) ) # ( 
+// !\bcd|A8|WideOr1~0_combout  & ( (\bcd|A8|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ) # (\bcd|A8|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A8|WideOr2~0_combout ),
+	.datab(!\bcd|A8|WideOr3~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A11|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A11|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A11|WideOr0~0 .lut_mask = 64'h15151515EAEAEAEA;
+defparam \bcd|A11|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N51
+cyclonev_lcell_comb \bcd|A10|WideOr3~0 (
+// Equation(s):
+// \bcd|A10|WideOr3~0_combout  = ( \bcd|A7|WideOr3~0_combout  & ( (!\bcd|A7|WideOr1~0_combout  & (!\bcd|A7|WideOr2~0_combout  $ (!\bcd|A8|WideOr0~0_combout ))) # (\bcd|A7|WideOr1~0_combout  & (!\bcd|A7|WideOr2~0_combout  & !\bcd|A8|WideOr0~0_combout )) ) ) # 
+// ( !\bcd|A7|WideOr3~0_combout  & ( (!\bcd|A7|WideOr1~0_combout  & (!\bcd|A7|WideOr2~0_combout  & \bcd|A8|WideOr0~0_combout )) # (\bcd|A7|WideOr1~0_combout  & ((!\bcd|A8|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A7|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A7|WideOr2~0_combout ),
+	.datad(!\bcd|A8|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A7|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A10|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A10|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A10|WideOr3~0 .lut_mask = 64'h55A055A05AA05AA0;
+defparam \bcd|A10|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N39
+cyclonev_lcell_comb \bcd|A10|WideOr2~0 (
+// Equation(s):
+// \bcd|A10|WideOr2~0_combout  = ( \bcd|A8|WideOr0~0_combout  & ( (\bcd|A7|WideOr3~0_combout  & ((!\bcd|A7|WideOr1~0_combout ) # (!\bcd|A7|WideOr2~0_combout ))) ) ) # ( !\bcd|A8|WideOr0~0_combout  & ( (!\bcd|A7|WideOr1~0_combout  & (\bcd|A7|WideOr3~0_combout 
+//  & !\bcd|A7|WideOr2~0_combout )) # (\bcd|A7|WideOr1~0_combout  & (!\bcd|A7|WideOr3~0_combout )) ) )
+
+	.dataa(!\bcd|A7|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A7|WideOr3~0_combout ),
+	.datad(!\bcd|A7|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A10|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A10|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A10|WideOr2~0 .lut_mask = 64'h5A505A500F0A0F0A;
+defparam \bcd|A10|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N18
+cyclonev_lcell_comb \bcd|A13|WideOr3~0 (
+// Equation(s):
+// \bcd|A13|WideOr3~0_combout  = ( \bcd|A10|WideOr2~0_combout  & ( (!\bcd|A11|WideOr0~0_combout  & (!\bcd|A10|WideOr1~0_combout  $ (!\bcd|A10|WideOr3~0_combout ))) ) ) # ( !\bcd|A10|WideOr2~0_combout  & ( !\bcd|A10|WideOr1~0_combout  $ 
+// (!\bcd|A11|WideOr0~0_combout ) ) )
+
+	.dataa(!\bcd|A10|WideOr1~0_combout ),
+	.datab(!\bcd|A11|WideOr0~0_combout ),
+	.datac(!\bcd|A10|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A10|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A13|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A13|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A13|WideOr3~0 .lut_mask = 64'h6666666648484848;
+defparam \bcd|A13|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N36
+cyclonev_lcell_comb \bcd|A13|WideOr1~0 (
+// Equation(s):
+// \bcd|A13|WideOr1~0_combout  = ( \bcd|A10|WideOr1~0_combout  & ( !\bcd|A10|WideOr2~0_combout  $ (((!\bcd|A10|WideOr3~0_combout  & !\bcd|A11|WideOr0~0_combout ))) ) ) # ( !\bcd|A10|WideOr1~0_combout  & ( (\bcd|A10|WideOr2~0_combout  & 
+// (!\bcd|A10|WideOr3~0_combout  & !\bcd|A11|WideOr0~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A10|WideOr2~0_combout ),
+	.datac(!\bcd|A10|WideOr3~0_combout ),
+	.datad(!\bcd|A11|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A10|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A13|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A13|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A13|WideOr1~0 .lut_mask = 64'h300030003CCC3CCC;
+defparam \bcd|A13|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N21
+cyclonev_lcell_comb \bcd|A13|WideOr2~0 (
+// Equation(s):
+// \bcd|A13|WideOr2~0_combout  = ( \bcd|A10|WideOr2~0_combout  & ( (!\bcd|A10|WideOr1~0_combout  & (\bcd|A11|WideOr0~0_combout  & \bcd|A10|WideOr3~0_combout )) # (\bcd|A10|WideOr1~0_combout  & (!\bcd|A11|WideOr0~0_combout  & !\bcd|A10|WideOr3~0_combout )) ) 
+// ) # ( !\bcd|A10|WideOr2~0_combout  & ( !\bcd|A10|WideOr3~0_combout  $ (((!\bcd|A10|WideOr1~0_combout ) # (\bcd|A11|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A10|WideOr1~0_combout ),
+	.datab(!\bcd|A11|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A10|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A10|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A13|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A13|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A13|WideOr2~0 .lut_mask = 64'h44BB44BB44224422;
+defparam \bcd|A13|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N33
+cyclonev_lcell_comb \bcd|A14|WideOr0~0 (
+// Equation(s):
+// \bcd|A14|WideOr0~0_combout  = ( \bcd|A11|WideOr1~0_combout  & ( (!\bcd|A11|WideOr2~0_combout ) # ((!\bcd|A11|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout )) ) ) # ( 
+// !\bcd|A11|WideOr1~0_combout  & ( (\bcd|A11|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ) # (\bcd|A11|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A11|WideOr2~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A11|WideOr3~0_combout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A11|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A14|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A14|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A14|WideOr0~0 .lut_mask = 64'h05550555FAAAFAAA;
+defparam \bcd|A14|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N36
+cyclonev_lcell_comb \bcd|A16|WideOr3~0 (
+// Equation(s):
+// \bcd|A16|WideOr3~0_combout  = ( \bcd|A14|WideOr0~0_combout  & ( (!\bcd|A13|WideOr1~0_combout  & !\bcd|A13|WideOr2~0_combout ) ) ) # ( !\bcd|A14|WideOr0~0_combout  & ( !\bcd|A13|WideOr1~0_combout  $ (((!\bcd|A13|WideOr3~0_combout ) # 
+// (!\bcd|A13|WideOr2~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A13|WideOr3~0_combout ),
+	.datac(!\bcd|A13|WideOr1~0_combout ),
+	.datad(!\bcd|A13|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A14|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A16|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A16|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A16|WideOr3~0 .lut_mask = 64'h0F3C0F3CF000F000;
+defparam \bcd|A16|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N9
+cyclonev_lcell_comb \bcd|A16|WideOr1~0 (
+// Equation(s):
+// \bcd|A16|WideOr1~0_combout  = ( \bcd|A14|WideOr0~0_combout  & ( (\bcd|A13|WideOr1~0_combout  & !\bcd|A13|WideOr2~0_combout ) ) ) # ( !\bcd|A14|WideOr0~0_combout  & ( (!\bcd|A13|WideOr3~0_combout  & ((\bcd|A13|WideOr2~0_combout ))) # 
+// (\bcd|A13|WideOr3~0_combout  & (\bcd|A13|WideOr1~0_combout  & !\bcd|A13|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A13|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A13|WideOr3~0_combout ),
+	.datad(!\bcd|A13|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A14|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A16|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A16|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A16|WideOr1~0 .lut_mask = 64'h05F005F055005500;
+defparam \bcd|A16|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N39
+cyclonev_lcell_comb \bcd|A16|WideOr2~0 (
+// Equation(s):
+// \bcd|A16|WideOr2~0_combout  = ( \bcd|A13|WideOr1~0_combout  & ( (!\bcd|A14|WideOr0~0_combout  & (!\bcd|A13|WideOr3~0_combout )) # (\bcd|A14|WideOr0~0_combout  & (\bcd|A13|WideOr3~0_combout  & !\bcd|A13|WideOr2~0_combout )) ) ) # ( 
+// !\bcd|A13|WideOr1~0_combout  & ( (\bcd|A13|WideOr3~0_combout  & ((!\bcd|A13|WideOr2~0_combout ) # (\bcd|A14|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A14|WideOr0~0_combout ),
+	.datab(!\bcd|A13|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A13|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A13|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A16|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A16|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A16|WideOr2~0 .lut_mask = 64'h3311331199889988;
+defparam \bcd|A16|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N33
+cyclonev_lcell_comb \bcd|A17|WideOr0~0 (
+// Equation(s):
+// \bcd|A17|WideOr0~0_combout  = ( \bcd|A14|WideOr3~0_combout  & ( !\bcd|A14|WideOr2~0_combout  $ (!\bcd|A14|WideOr1~0_combout ) ) ) # ( !\bcd|A14|WideOr3~0_combout  & ( !\bcd|A14|WideOr1~0_combout  $ 
+// (((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ) # (!\bcd|A14|WideOr2~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datac(!\bcd|A14|WideOr2~0_combout ),
+	.datad(!\bcd|A14|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A14|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A17|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A17|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A17|WideOr0~0 .lut_mask = 64'h03FC03FC0FF00FF0;
+defparam \bcd|A17|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N21
+cyclonev_lcell_comb \bcd|A20|WideOr3~0 (
+// Equation(s):
+// \bcd|A20|WideOr3~0_combout  = ( \bcd|A17|WideOr0~0_combout  & ( (!\bcd|A16|WideOr1~0_combout  & !\bcd|A16|WideOr2~0_combout ) ) ) # ( !\bcd|A17|WideOr0~0_combout  & ( !\bcd|A16|WideOr1~0_combout  $ (((!\bcd|A16|WideOr3~0_combout ) # 
+// (!\bcd|A16|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A16|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A16|WideOr1~0_combout ),
+	.datad(!\bcd|A16|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A17|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A20|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A20|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A20|WideOr3~0 .lut_mask = 64'h0F5A0F5AF000F000;
+defparam \bcd|A20|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N18
+cyclonev_lcell_comb \bcd|A20|WideOr2~0 (
+// Equation(s):
+// \bcd|A20|WideOr2~0_combout  = ( \bcd|A17|WideOr0~0_combout  & ( (\bcd|A16|WideOr3~0_combout  & ((!\bcd|A16|WideOr1~0_combout ) # (!\bcd|A16|WideOr2~0_combout ))) ) ) # ( !\bcd|A17|WideOr0~0_combout  & ( (!\bcd|A16|WideOr3~0_combout  & 
+// (\bcd|A16|WideOr1~0_combout )) # (\bcd|A16|WideOr3~0_combout  & (!\bcd|A16|WideOr1~0_combout  & !\bcd|A16|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A16|WideOr3~0_combout ),
+	.datab(!\bcd|A16|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A16|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A17|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A20|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A20|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A20|WideOr2~0 .lut_mask = 64'h6622662255445544;
+defparam \bcd|A20|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N12
+cyclonev_lcell_comb \bcd|A20|WideOr1~0 (
+// Equation(s):
+// \bcd|A20|WideOr1~0_combout  = ( \bcd|A17|WideOr0~0_combout  & ( (\bcd|A16|WideOr1~0_combout  & !\bcd|A16|WideOr2~0_combout ) ) ) # ( !\bcd|A17|WideOr0~0_combout  & ( (!\bcd|A16|WideOr3~0_combout  & ((\bcd|A16|WideOr2~0_combout ))) # 
+// (\bcd|A16|WideOr3~0_combout  & (\bcd|A16|WideOr1~0_combout  & !\bcd|A16|WideOr2~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A16|WideOr1~0_combout ),
+	.datac(!\bcd|A16|WideOr3~0_combout ),
+	.datad(!\bcd|A16|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A17|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A20|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A20|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A20|WideOr1~0 .lut_mask = 64'h03F003F033003300;
+defparam \bcd|A20|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N51
+cyclonev_lcell_comb \bcd|A21|WideOr0~0 (
+// Equation(s):
+// \bcd|A21|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & ( !\bcd|A17|WideOr2~0_combout  $ (!\bcd|A17|WideOr1~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & ( !\bcd|A17|WideOr1~0_combout  $ (((!\bcd|A17|WideOr3~0_combout ) # (!\bcd|A17|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A17|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A17|WideOr2~0_combout ),
+	.datad(!\bcd|A17|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A21|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A21|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A21|WideOr0~0 .lut_mask = 64'h05FA05FA0FF00FF0;
+defparam \bcd|A21|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N15
+cyclonev_lcell_comb \bcd|A24|WideOr3~0 (
+// Equation(s):
+// \bcd|A24|WideOr3~0_combout  = ( \bcd|A21|WideOr0~0_combout  & ( (!\bcd|A20|WideOr2~0_combout  & !\bcd|A20|WideOr1~0_combout ) ) ) # ( !\bcd|A21|WideOr0~0_combout  & ( !\bcd|A20|WideOr1~0_combout  $ (((!\bcd|A20|WideOr3~0_combout ) # 
+// (!\bcd|A20|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A20|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A20|WideOr2~0_combout ),
+	.datad(!\bcd|A20|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A21|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A24|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A24|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A24|WideOr3~0 .lut_mask = 64'h05FA05FAF000F000;
+defparam \bcd|A24|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N9
+cyclonev_lcell_comb \bcd|A25|WideOr0~0 (
+// Equation(s):
+// \bcd|A25|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\bcd|A21|WideOr1~0_combout  $ (!\bcd|A21|WideOr2~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\bcd|A21|WideOr1~0_combout  $ (((!\bcd|A21|WideOr3~0_combout ) # (!\bcd|A21|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A21|WideOr1~0_combout ),
+	.datab(!\bcd|A21|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A21|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A25|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A25|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A25|WideOr0~0 .lut_mask = 64'h5566556655AA55AA;
+defparam \bcd|A25|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N57
+cyclonev_lcell_comb \bcd|A24|WideOr1~0 (
+// Equation(s):
+// \bcd|A24|WideOr1~0_combout  = ( \bcd|A21|WideOr0~0_combout  & ( (!\bcd|A20|WideOr2~0_combout  & \bcd|A20|WideOr1~0_combout ) ) ) # ( !\bcd|A21|WideOr0~0_combout  & ( (!\bcd|A20|WideOr3~0_combout  & (\bcd|A20|WideOr2~0_combout )) # 
+// (\bcd|A20|WideOr3~0_combout  & (!\bcd|A20|WideOr2~0_combout  & \bcd|A20|WideOr1~0_combout )) ) )
+
+	.dataa(!\bcd|A20|WideOr3~0_combout ),
+	.datab(!\bcd|A20|WideOr2~0_combout ),
+	.datac(!\bcd|A20|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A21|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A24|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A24|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A24|WideOr1~0 .lut_mask = 64'h262626260C0C0C0C;
+defparam \bcd|A24|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N54
+cyclonev_lcell_comb \bcd|A24|WideOr2~0 (
+// Equation(s):
+// \bcd|A24|WideOr2~0_combout  = ( \bcd|A20|WideOr1~0_combout  & ( (!\bcd|A20|WideOr3~0_combout  & ((!\bcd|A21|WideOr0~0_combout ))) # (\bcd|A20|WideOr3~0_combout  & (!\bcd|A20|WideOr2~0_combout  & \bcd|A21|WideOr0~0_combout )) ) ) # ( 
+// !\bcd|A20|WideOr1~0_combout  & ( (\bcd|A20|WideOr3~0_combout  & ((!\bcd|A20|WideOr2~0_combout ) # (\bcd|A21|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A20|WideOr3~0_combout ),
+	.datab(!\bcd|A20|WideOr2~0_combout ),
+	.datac(!\bcd|A21|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A24|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A24|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A24|WideOr2~0 .lut_mask = 64'h45454545A4A4A4A4;
+defparam \bcd|A24|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N21
+cyclonev_lcell_comb \bcd|A28|WideOr1~0 (
+// Equation(s):
+// \bcd|A28|WideOr1~0_combout  = ( \bcd|A24|WideOr2~0_combout  & ( (!\bcd|A24|WideOr3~0_combout  & !\bcd|A25|WideOr0~0_combout ) ) ) # ( !\bcd|A24|WideOr2~0_combout  & ( (\bcd|A24|WideOr1~0_combout  & ((\bcd|A25|WideOr0~0_combout ) # 
+// (\bcd|A24|WideOr3~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A24|WideOr3~0_combout ),
+	.datac(!\bcd|A25|WideOr0~0_combout ),
+	.datad(!\bcd|A24|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A28|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A28|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A28|WideOr1~0 .lut_mask = 64'h003F003FC0C0C0C0;
+defparam \bcd|A28|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N33
+cyclonev_lcell_comb \bcd|A28|WideOr3~0 (
+// Equation(s):
+// \bcd|A28|WideOr3~0_combout  = ( \bcd|A24|WideOr2~0_combout  & ( (!\bcd|A25|WideOr0~0_combout  & (!\bcd|A24|WideOr3~0_combout  $ (!\bcd|A24|WideOr1~0_combout ))) ) ) # ( !\bcd|A24|WideOr2~0_combout  & ( !\bcd|A25|WideOr0~0_combout  $ 
+// (!\bcd|A24|WideOr1~0_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A25|WideOr0~0_combout ),
+	.datac(!\bcd|A24|WideOr3~0_combout ),
+	.datad(!\bcd|A24|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A28|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A28|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A28|WideOr3~0 .lut_mask = 64'h33CC33CC0CC00CC0;
+defparam \bcd|A28|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N57
+cyclonev_lcell_comb \bcd|A29|WideOr0~0 (
+// Equation(s):
+// \bcd|A29|WideOr0~0_combout  = ( \bcd|A25|WideOr3~0_combout  & ( !\bcd|A25|WideOr1~0_combout  $ (!\bcd|A25|WideOr2~0_combout ) ) ) # ( !\bcd|A25|WideOr3~0_combout  & ( !\bcd|A25|WideOr1~0_combout  $ (((!\bcd|A25|WideOr2~0_combout ) # 
+// (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ))) ) )
+
+	.dataa(!\bcd|A25|WideOr1~0_combout ),
+	.datab(!\bcd|A25|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A29|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A29|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A29|WideOr0~0 .lut_mask = 64'h5656565666666666;
+defparam \bcd|A29|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N18
+cyclonev_lcell_comb \bcd|A28|WideOr2~0 (
+// Equation(s):
+// \bcd|A28|WideOr2~0_combout  = ( \bcd|A25|WideOr0~0_combout  & ( (\bcd|A24|WideOr3~0_combout  & ((!\bcd|A24|WideOr2~0_combout ) # (!\bcd|A24|WideOr1~0_combout ))) ) ) # ( !\bcd|A25|WideOr0~0_combout  & ( (!\bcd|A24|WideOr3~0_combout  & 
+// ((\bcd|A24|WideOr1~0_combout ))) # (\bcd|A24|WideOr3~0_combout  & (!\bcd|A24|WideOr2~0_combout  & !\bcd|A24|WideOr1~0_combout )) ) )
+
+	.dataa(!\bcd|A24|WideOr2~0_combout ),
+	.datab(!\bcd|A24|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A24|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A25|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A28|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A28|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A28|WideOr2~0 .lut_mask = 64'h22CC22CC33223322;
+defparam \bcd|A28|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N21
+cyclonev_lcell_comb \h1|WideOr6~0 (
+// Equation(s):
+// \h1|WideOr6~0_combout  = ( \bcd|A29|WideOr0~0_combout  & ( \bcd|A28|WideOr2~0_combout  & ( (!\bcd|A28|WideOr1~0_combout ) # (\bcd|A28|WideOr3~0_combout ) ) ) ) # ( !\bcd|A29|WideOr0~0_combout  & ( \bcd|A28|WideOr2~0_combout  & ( 
+// (\bcd|A28|WideOr3~0_combout ) # (\bcd|A28|WideOr1~0_combout ) ) ) ) # ( \bcd|A29|WideOr0~0_combout  & ( !\bcd|A28|WideOr2~0_combout  & ( !\bcd|A28|WideOr1~0_combout  $ (!\bcd|A28|WideOr3~0_combout ) ) ) ) # ( !\bcd|A29|WideOr0~0_combout  & ( 
+// !\bcd|A28|WideOr2~0_combout  ) )
+
+	.dataa(!\bcd|A28|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A28|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A29|WideOr0~0_combout ),
+	.dataf(!\bcd|A28|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr6~0 .extended_lut = "off";
+defparam \h1|WideOr6~0 .lut_mask = 64'hFFFF5A5A5F5FAFAF;
+defparam \h1|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N0
+cyclonev_lcell_comb \h1|WideOr5~0 (
+// Equation(s):
+// \h1|WideOr5~0_combout  = ( \bcd|A28|WideOr2~0_combout  & ( (!\bcd|A28|WideOr1~0_combout  & (!\bcd|A29|WideOr0~0_combout  $ (!\bcd|A28|WideOr3~0_combout ))) # (\bcd|A28|WideOr1~0_combout  & ((!\bcd|A29|WideOr0~0_combout ) # (\bcd|A28|WideOr3~0_combout ))) 
+// ) ) # ( !\bcd|A28|WideOr2~0_combout  & ( (\bcd|A28|WideOr1~0_combout  & (\bcd|A29|WideOr0~0_combout  & \bcd|A28|WideOr3~0_combout )) ) )
+
+	.dataa(!\bcd|A28|WideOr1~0_combout ),
+	.datab(!\bcd|A29|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A28|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr5~0 .extended_lut = "off";
+defparam \h1|WideOr5~0 .lut_mask = 64'h0011001166DD66DD;
+defparam \h1|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N9
+cyclonev_lcell_comb \h1|WideOr4~0 (
+// Equation(s):
+// \h1|WideOr4~0_combout  = ( \bcd|A29|WideOr0~0_combout  & ( \bcd|A28|WideOr2~0_combout  & ( (\bcd|A28|WideOr1~0_combout  & \bcd|A28|WideOr3~0_combout ) ) ) ) # ( !\bcd|A29|WideOr0~0_combout  & ( \bcd|A28|WideOr2~0_combout  & ( \bcd|A28|WideOr1~0_combout  ) 
+// ) ) # ( !\bcd|A29|WideOr0~0_combout  & ( !\bcd|A28|WideOr2~0_combout  & ( (!\bcd|A28|WideOr1~0_combout  & \bcd|A28|WideOr3~0_combout ) ) ) )
+
+	.dataa(!\bcd|A28|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A28|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A29|WideOr0~0_combout ),
+	.dataf(!\bcd|A28|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr4~0 .extended_lut = "off";
+defparam \h1|WideOr4~0 .lut_mask = 64'h0A0A000055550505;
+defparam \h1|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N15
+cyclonev_lcell_comb \h1|WideOr3~0 (
+// Equation(s):
+// \h1|WideOr3~0_combout  = ( \bcd|A29|WideOr0~0_combout  & ( \bcd|A28|WideOr2~0_combout  & ( !\bcd|A28|WideOr3~0_combout  ) ) ) # ( !\bcd|A29|WideOr0~0_combout  & ( \bcd|A28|WideOr2~0_combout  & ( (\bcd|A28|WideOr3~0_combout ) # (\bcd|A28|WideOr1~0_combout 
+// ) ) ) ) # ( \bcd|A29|WideOr0~0_combout  & ( !\bcd|A28|WideOr2~0_combout  & ( \bcd|A28|WideOr3~0_combout  ) ) ) # ( !\bcd|A29|WideOr0~0_combout  & ( !\bcd|A28|WideOr2~0_combout  & ( (!\bcd|A28|WideOr1~0_combout ) # (!\bcd|A28|WideOr3~0_combout ) ) ) )
+
+	.dataa(!\bcd|A28|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A28|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A29|WideOr0~0_combout ),
+	.dataf(!\bcd|A28|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr3~0 .extended_lut = "off";
+defparam \h1|WideOr3~0 .lut_mask = 64'hFAFA0F0F5F5FF0F0;
+defparam \h1|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N42
+cyclonev_lcell_comb \h1|WideOr2~0 (
+// Equation(s):
+// \h1|WideOr2~0_combout  = ( \bcd|A28|WideOr2~0_combout  & ( ((!\bcd|A29|WideOr0~0_combout  & \bcd|A28|WideOr3~0_combout )) # (\bcd|A28|WideOr1~0_combout ) ) ) # ( !\bcd|A28|WideOr2~0_combout  & ( (!\bcd|A29|WideOr0~0_combout ) # 
+// ((\bcd|A28|WideOr1~0_combout  & \bcd|A28|WideOr3~0_combout )) ) )
+
+	.dataa(!\bcd|A28|WideOr1~0_combout ),
+	.datab(!\bcd|A29|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A28|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr2~0 .extended_lut = "off";
+defparam \h1|WideOr2~0 .lut_mask = 64'hCCDDCCDD55DD55DD;
+defparam \h1|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N45
+cyclonev_lcell_comb \h1|WideOr1~0 (
+// Equation(s):
+// \h1|WideOr1~0_combout  = ( \bcd|A28|WideOr2~0_combout  & ( (!\bcd|A29|WideOr0~0_combout ) # (!\bcd|A28|WideOr1~0_combout  $ (\bcd|A28|WideOr3~0_combout )) ) ) # ( !\bcd|A28|WideOr2~0_combout  & ( ((!\bcd|A29|WideOr0~0_combout  & 
+// !\bcd|A28|WideOr3~0_combout )) # (\bcd|A28|WideOr1~0_combout ) ) )
+
+	.dataa(!\bcd|A28|WideOr1~0_combout ),
+	.datab(!\bcd|A29|WideOr0~0_combout ),
+	.datac(!\bcd|A28|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr1~0 .extended_lut = "off";
+defparam \h1|WideOr1~0 .lut_mask = 64'hD5D5D5D5EDEDEDED;
+defparam \h1|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N3
+cyclonev_lcell_comb \h1|WideOr0~0 (
+// Equation(s):
+// \h1|WideOr0~0_combout  = ( \bcd|A28|WideOr2~0_combout  & ( (!\bcd|A28|WideOr1~0_combout  & ((!\bcd|A29|WideOr0~0_combout ) # (!\bcd|A28|WideOr3~0_combout ))) # (\bcd|A28|WideOr1~0_combout  & ((\bcd|A28|WideOr3~0_combout ) # (\bcd|A29|WideOr0~0_combout ))) 
+// ) ) # ( !\bcd|A28|WideOr2~0_combout  & ( (\bcd|A28|WideOr3~0_combout ) # (\bcd|A28|WideOr1~0_combout ) ) )
+
+	.dataa(!\bcd|A28|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A29|WideOr0~0_combout ),
+	.datad(!\bcd|A28|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr0~0 .extended_lut = "off";
+defparam \h1|WideOr0~0 .lut_mask = 64'h55FF55FFAFF5AFF5;
+defparam \h1|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X65_Y9_N48
+cyclonev_lcell_comb \bcd|A1|WideOr0~0 (
+// Equation(s):
+// \bcd|A1|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datad(gnd),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A1|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A1|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A1|WideOr0~0 .lut_mask = 64'h03030F0F03030F0F;
+defparam \bcd|A1|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N3
+cyclonev_lcell_comb \bcd|A2|WideOr0~0 (
+// Equation(s):
+// \bcd|A2|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  $ 
+// (((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ))) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A2|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A2|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A2|WideOr0~0 .lut_mask = 64'h424242424B4B4B4B;
+defparam \bcd|A2|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N24
+cyclonev_lcell_comb \bcd|A6|WideOr0~0 (
+// Equation(s):
+// \bcd|A6|WideOr0~0_combout  = ( \bcd|A4|WideOr2~0_combout  & ( !\bcd|A4|WideOr1~0_combout  $ (((!\bcd|A4|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ))) ) ) # ( 
+// !\bcd|A4|WideOr2~0_combout  & ( \bcd|A4|WideOr1~0_combout  ) )
+
+	.dataa(!\bcd|A4|WideOr1~0_combout ),
+	.datab(!\bcd|A4|WideOr3~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A4|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A6|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A6|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A6|WideOr0~0 .lut_mask = 64'h555555556A6A6A6A;
+defparam \bcd|A6|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y9_N12
+cyclonev_lcell_comb \bcd|A4|WideOr0~0 (
+// Equation(s):
+// \bcd|A4|WideOr0~0_combout  = !\bcd|A2|WideOr1~0_combout  $ (((!\bcd|A2|WideOr2~0_combout ) # ((!\bcd|A2|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ))))
+
+	.dataa(!\bcd|A2|WideOr3~0_combout ),
+	.datab(!\bcd|A2|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(!\bcd|A2|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A4|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A4|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A4|WideOr0~0 .lut_mask = 64'h13EC13EC13EC13EC;
+defparam \bcd|A4|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N12
+cyclonev_lcell_comb \bcd|A15|WideOr2~0 (
+// Equation(s):
+// \bcd|A15|WideOr2~0_combout  = ( \bcd|A11|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A1|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout  & ((\bcd|A6|WideOr0~0_combout ) # (\bcd|A8|WideOr0~0_combout )))) # (\bcd|A1|WideOr0~0_combout  & 
+// (!\bcd|A2|WideOr0~0_combout  $ (((\bcd|A6|WideOr0~0_combout ))))) ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A1|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout  & ((\bcd|A6|WideOr0~0_combout ) # 
+// (\bcd|A8|WideOr0~0_combout )))) # (\bcd|A1|WideOr0~0_combout  & ((!\bcd|A2|WideOr0~0_combout  & ((!\bcd|A8|WideOr0~0_combout ) # (!\bcd|A6|WideOr0~0_combout ))) # (\bcd|A2|WideOr0~0_combout  & ((\bcd|A6|WideOr0~0_combout ))))) ) ) ) # ( 
+// \bcd|A11|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( (!\bcd|A1|WideOr0~0_combout  & (\bcd|A2|WideOr0~0_combout  & ((!\bcd|A6|WideOr0~0_combout )))) # (\bcd|A1|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout  & ((\bcd|A6|WideOr0~0_combout ) # 
+// (\bcd|A8|WideOr0~0_combout )))) ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( (!\bcd|A1|WideOr0~0_combout  & (\bcd|A2|WideOr0~0_combout  & !\bcd|A6|WideOr0~0_combout )) # (\bcd|A1|WideOr0~0_combout  & 
+// (!\bcd|A2|WideOr0~0_combout  & \bcd|A6|WideOr0~0_combout )) ) ) )
+
+	.dataa(!\bcd|A1|WideOr0~0_combout ),
+	.datab(!\bcd|A2|WideOr0~0_combout ),
+	.datac(!\bcd|A8|WideOr0~0_combout ),
+	.datad(!\bcd|A6|WideOr0~0_combout ),
+	.datae(!\bcd|A11|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A15|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A15|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A15|WideOr2~0 .lut_mask = 64'h224426444CD94C99;
+defparam \bcd|A15|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N30
+cyclonev_lcell_comb \bcd|A16|WideOr0~0 (
+// Equation(s):
+// \bcd|A16|WideOr0~0_combout  = ( \bcd|A13|WideOr3~0_combout  & ( !\bcd|A13|WideOr1~0_combout  $ (!\bcd|A13|WideOr2~0_combout ) ) ) # ( !\bcd|A13|WideOr3~0_combout  & ( !\bcd|A13|WideOr1~0_combout  $ (((!\bcd|A14|WideOr0~0_combout ) # 
+// (!\bcd|A13|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A14|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A13|WideOr1~0_combout ),
+	.datad(!\bcd|A13|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A13|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A16|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A16|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A16|WideOr0~0 .lut_mask = 64'h0F5A0F5A0FF00FF0;
+defparam \bcd|A16|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N42
+cyclonev_lcell_comb \bcd|A15|WideOr3~0 (
+// Equation(s):
+// \bcd|A15|WideOr3~0_combout  = ( \bcd|A11|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A1|WideOr0~0_combout  & ((!\bcd|A8|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout  & !\bcd|A6|WideOr0~0_combout )) # (\bcd|A8|WideOr0~0_combout  & 
+// ((\bcd|A6|WideOr0~0_combout ))))) # (\bcd|A1|WideOr0~0_combout  & (((!\bcd|A6|WideOr0~0_combout )))) ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A1|WideOr0~0_combout  & ((!\bcd|A2|WideOr0~0_combout  & 
+// (!\bcd|A8|WideOr0~0_combout  & !\bcd|A6|WideOr0~0_combout )) # (\bcd|A2|WideOr0~0_combout  & (\bcd|A8|WideOr0~0_combout  & \bcd|A6|WideOr0~0_combout )))) # (\bcd|A1|WideOr0~0_combout  & ((!\bcd|A6|WideOr0~0_combout ) # ((!\bcd|A2|WideOr0~0_combout  & 
+// !\bcd|A8|WideOr0~0_combout )))) ) ) ) # ( \bcd|A11|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( (!\bcd|A1|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout  $ (((!\bcd|A6|WideOr0~0_combout ))))) # (\bcd|A1|WideOr0~0_combout  & 
+// ((!\bcd|A2|WideOr0~0_combout  & (!\bcd|A8|WideOr0~0_combout  & !\bcd|A6|WideOr0~0_combout )) # (\bcd|A2|WideOr0~0_combout  & (\bcd|A8|WideOr0~0_combout  & \bcd|A6|WideOr0~0_combout )))) ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout 
+//  & ( (!\bcd|A6|WideOr0~0_combout  & (!\bcd|A1|WideOr0~0_combout  $ ((!\bcd|A2|WideOr0~0_combout )))) # (\bcd|A6|WideOr0~0_combout  & (!\bcd|A1|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout  & \bcd|A8|WideOr0~0_combout ))) ) ) )
+
+	.dataa(!\bcd|A1|WideOr0~0_combout ),
+	.datab(!\bcd|A2|WideOr0~0_combout ),
+	.datac(!\bcd|A8|WideOr0~0_combout ),
+	.datad(!\bcd|A6|WideOr0~0_combout ),
+	.datae(!\bcd|A11|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A15|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A15|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A15|WideOr3~0 .lut_mask = 64'h66086289D542D50A;
+defparam \bcd|A15|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N30
+cyclonev_lcell_comb \bcd|A15|WideOr1~0 (
+// Equation(s):
+// \bcd|A15|WideOr1~0_combout  = ( \bcd|A11|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (\bcd|A1|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout  & \bcd|A6|WideOr0~0_combout )) ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  
+// & ( (!\bcd|A1|WideOr0~0_combout  & (\bcd|A2|WideOr0~0_combout  & (!\bcd|A8|WideOr0~0_combout  & !\bcd|A6|WideOr0~0_combout ))) # (\bcd|A1|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout  & (\bcd|A8|WideOr0~0_combout  & \bcd|A6|WideOr0~0_combout ))) ) ) ) 
+// # ( \bcd|A11|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( (\bcd|A2|WideOr0~0_combout  & ((!\bcd|A1|WideOr0~0_combout  & ((\bcd|A6|WideOr0~0_combout ))) # (\bcd|A1|WideOr0~0_combout  & (!\bcd|A8|WideOr0~0_combout  & !\bcd|A6|WideOr0~0_combout 
+// )))) ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( (\bcd|A2|WideOr0~0_combout  & ((!\bcd|A1|WideOr0~0_combout  & ((\bcd|A6|WideOr0~0_combout ))) # (\bcd|A1|WideOr0~0_combout  & (!\bcd|A8|WideOr0~0_combout  & 
+// !\bcd|A6|WideOr0~0_combout )))) ) ) )
+
+	.dataa(!\bcd|A1|WideOr0~0_combout ),
+	.datab(!\bcd|A2|WideOr0~0_combout ),
+	.datac(!\bcd|A8|WideOr0~0_combout ),
+	.datad(!\bcd|A6|WideOr0~0_combout ),
+	.datae(!\bcd|A11|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A15|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A15|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A15|WideOr1~0 .lut_mask = 64'h1022102220040044;
+defparam \bcd|A15|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N24
+cyclonev_lcell_comb \bcd|A19|WideOr1~0 (
+// Equation(s):
+// \bcd|A19|WideOr1~0_combout  = ( \bcd|A15|WideOr1~0_combout  & ( !\bcd|A15|WideOr2~0_combout  $ (((!\bcd|A16|WideOr0~0_combout  & !\bcd|A15|WideOr3~0_combout ))) ) ) # ( !\bcd|A15|WideOr1~0_combout  & ( (\bcd|A15|WideOr2~0_combout  & 
+// (!\bcd|A16|WideOr0~0_combout  & !\bcd|A15|WideOr3~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A15|WideOr2~0_combout ),
+	.datac(!\bcd|A16|WideOr0~0_combout ),
+	.datad(!\bcd|A15|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A15|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A19|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A19|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A19|WideOr1~0 .lut_mask = 64'h300030003CCC3CCC;
+defparam \bcd|A19|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N54
+cyclonev_lcell_comb \bcd|A19|WideOr3~0 (
+// Equation(s):
+// \bcd|A19|WideOr3~0_combout  = ( \bcd|A15|WideOr2~0_combout  & ( (!\bcd|A16|WideOr0~0_combout  & (!\bcd|A15|WideOr1~0_combout  $ (!\bcd|A15|WideOr3~0_combout ))) ) ) # ( !\bcd|A15|WideOr2~0_combout  & ( !\bcd|A16|WideOr0~0_combout  $ 
+// (!\bcd|A15|WideOr1~0_combout ) ) )
+
+	.dataa(!\bcd|A16|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A15|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A15|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A19|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A19|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A19|WideOr3~0 .lut_mask = 64'h6666666622882288;
+defparam \bcd|A19|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N57
+cyclonev_lcell_comb \bcd|A19|WideOr2~0 (
+// Equation(s):
+// \bcd|A19|WideOr2~0_combout  = ( \bcd|A15|WideOr2~0_combout  & ( (!\bcd|A16|WideOr0~0_combout  & (\bcd|A15|WideOr1~0_combout  & !\bcd|A15|WideOr3~0_combout )) # (\bcd|A16|WideOr0~0_combout  & (!\bcd|A15|WideOr1~0_combout  & \bcd|A15|WideOr3~0_combout )) ) 
+// ) # ( !\bcd|A15|WideOr2~0_combout  & ( !\bcd|A15|WideOr3~0_combout  $ (((!\bcd|A15|WideOr1~0_combout ) # (\bcd|A16|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A16|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr1~0_combout ),
+	.datac(!\bcd|A15|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A15|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A19|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A19|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A19|WideOr2~0 .lut_mask = 64'h2D2D2D2D24242424;
+defparam \bcd|A19|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N15
+cyclonev_lcell_comb \bcd|A20|WideOr0~0 (
+// Equation(s):
+// \bcd|A20|WideOr0~0_combout  = ( \bcd|A17|WideOr0~0_combout  & ( !\bcd|A16|WideOr1~0_combout  $ (!\bcd|A16|WideOr2~0_combout ) ) ) # ( !\bcd|A17|WideOr0~0_combout  & ( !\bcd|A16|WideOr1~0_combout  $ (((!\bcd|A16|WideOr3~0_combout ) # 
+// (!\bcd|A16|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A16|WideOr3~0_combout ),
+	.datab(!\bcd|A16|WideOr1~0_combout ),
+	.datac(!\bcd|A16|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A17|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A20|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A20|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A20|WideOr0~0 .lut_mask = 64'h363636363C3C3C3C;
+defparam \bcd|A20|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N6
+cyclonev_lcell_comb \bcd|A23|WideOr2~0 (
+// Equation(s):
+// \bcd|A23|WideOr2~0_combout  = ( \bcd|A19|WideOr2~0_combout  & ( \bcd|A20|WideOr0~0_combout  & ( (!\bcd|A19|WideOr1~0_combout  & \bcd|A19|WideOr3~0_combout ) ) ) ) # ( !\bcd|A19|WideOr2~0_combout  & ( \bcd|A20|WideOr0~0_combout  & ( 
+// \bcd|A19|WideOr3~0_combout  ) ) ) # ( \bcd|A19|WideOr2~0_combout  & ( !\bcd|A20|WideOr0~0_combout  & ( (\bcd|A19|WideOr1~0_combout  & !\bcd|A19|WideOr3~0_combout ) ) ) ) # ( !\bcd|A19|WideOr2~0_combout  & ( !\bcd|A20|WideOr0~0_combout  & ( 
+// !\bcd|A19|WideOr1~0_combout  $ (!\bcd|A19|WideOr3~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A19|WideOr1~0_combout ),
+	.datac(!\bcd|A19|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A19|WideOr2~0_combout ),
+	.dataf(!\bcd|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A23|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A23|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A23|WideOr2~0 .lut_mask = 64'h3C3C30300F0F0C0C;
+defparam \bcd|A23|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N12
+cyclonev_lcell_comb \bcd|A23|WideOr3~0 (
+// Equation(s):
+// \bcd|A23|WideOr3~0_combout  = ( !\bcd|A19|WideOr2~0_combout  & ( \bcd|A20|WideOr0~0_combout  & ( !\bcd|A19|WideOr1~0_combout  ) ) ) # ( \bcd|A19|WideOr2~0_combout  & ( !\bcd|A20|WideOr0~0_combout  & ( !\bcd|A19|WideOr1~0_combout  $ 
+// (!\bcd|A19|WideOr3~0_combout ) ) ) ) # ( !\bcd|A19|WideOr2~0_combout  & ( !\bcd|A20|WideOr0~0_combout  & ( \bcd|A19|WideOr1~0_combout  ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A19|WideOr1~0_combout ),
+	.datac(!\bcd|A19|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A19|WideOr2~0_combout ),
+	.dataf(!\bcd|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A23|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A23|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A23|WideOr3~0 .lut_mask = 64'h33333C3CCCCC0000;
+defparam \bcd|A23|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y9_N48
+cyclonev_lcell_comb \bcd|A24|WideOr0~0 (
+// Equation(s):
+// \bcd|A24|WideOr0~0_combout  = ( \bcd|A20|WideOr1~0_combout  & ( (!\bcd|A20|WideOr2~0_combout ) # ((!\bcd|A21|WideOr0~0_combout  & !\bcd|A20|WideOr3~0_combout )) ) ) # ( !\bcd|A20|WideOr1~0_combout  & ( (\bcd|A20|WideOr2~0_combout  & 
+// ((\bcd|A20|WideOr3~0_combout ) # (\bcd|A21|WideOr0~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A20|WideOr2~0_combout ),
+	.datac(!\bcd|A21|WideOr0~0_combout ),
+	.datad(!\bcd|A20|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A24|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A24|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A24|WideOr0~0 .lut_mask = 64'h03330333FCCCFCCC;
+defparam \bcd|A24|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N51
+cyclonev_lcell_comb \bcd|A23|WideOr1~0 (
+// Equation(s):
+// \bcd|A23|WideOr1~0_combout  = ( !\bcd|A19|WideOr2~0_combout  & ( \bcd|A20|WideOr0~0_combout  & ( \bcd|A19|WideOr1~0_combout  ) ) ) # ( \bcd|A19|WideOr2~0_combout  & ( !\bcd|A20|WideOr0~0_combout  & ( !\bcd|A19|WideOr3~0_combout  ) ) ) # ( 
+// !\bcd|A19|WideOr2~0_combout  & ( !\bcd|A20|WideOr0~0_combout  & ( (\bcd|A19|WideOr3~0_combout  & \bcd|A19|WideOr1~0_combout ) ) ) )
+
+	.dataa(!\bcd|A19|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A19|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A19|WideOr2~0_combout ),
+	.dataf(!\bcd|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A23|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A23|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A23|WideOr1~0 .lut_mask = 64'h0505AAAA0F0F0000;
+defparam \bcd|A23|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N48
+cyclonev_lcell_comb \bcd|A27|WideOr1~0 (
+// Equation(s):
+// \bcd|A27|WideOr1~0_combout  = ( \bcd|A23|WideOr1~0_combout  & ( !\bcd|A23|WideOr2~0_combout  $ (((!\bcd|A23|WideOr3~0_combout  & !\bcd|A24|WideOr0~0_combout ))) ) ) # ( !\bcd|A23|WideOr1~0_combout  & ( (\bcd|A23|WideOr2~0_combout  & 
+// (!\bcd|A23|WideOr3~0_combout  & !\bcd|A24|WideOr0~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A23|WideOr2~0_combout ),
+	.datac(!\bcd|A23|WideOr3~0_combout ),
+	.datad(!\bcd|A24|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A23|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A27|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A27|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A27|WideOr1~0 .lut_mask = 64'h300030003CCC3CCC;
+defparam \bcd|A27|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y9_N12
+cyclonev_lcell_comb \bcd|A28|WideOr0~0 (
+// Equation(s):
+// \bcd|A28|WideOr0~0_combout  = ( \bcd|A24|WideOr3~0_combout  & ( !\bcd|A24|WideOr2~0_combout  $ (!\bcd|A24|WideOr1~0_combout ) ) ) # ( !\bcd|A24|WideOr3~0_combout  & ( !\bcd|A24|WideOr1~0_combout  $ (((!\bcd|A25|WideOr0~0_combout ) # 
+// (!\bcd|A24|WideOr2~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A25|WideOr0~0_combout ),
+	.datac(!\bcd|A24|WideOr2~0_combout ),
+	.datad(!\bcd|A24|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A28|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A28|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A28|WideOr0~0 .lut_mask = 64'h03FC03FC0FF00FF0;
+defparam \bcd|A28|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N57
+cyclonev_lcell_comb \bcd|A27|WideOr2~0 (
+// Equation(s):
+// \bcd|A27|WideOr2~0_combout  = ( \bcd|A23|WideOr1~0_combout  & ( (!\bcd|A23|WideOr3~0_combout  & ((!\bcd|A24|WideOr0~0_combout ))) # (\bcd|A23|WideOr3~0_combout  & (!\bcd|A23|WideOr2~0_combout  & \bcd|A24|WideOr0~0_combout )) ) ) # ( 
+// !\bcd|A23|WideOr1~0_combout  & ( (\bcd|A23|WideOr3~0_combout  & ((!\bcd|A23|WideOr2~0_combout ) # (\bcd|A24|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A23|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A23|WideOr2~0_combout ),
+	.datad(!\bcd|A24|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A23|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A27|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A27|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A27|WideOr2~0 .lut_mask = 64'h50555055AA50AA50;
+defparam \bcd|A27|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N24
+cyclonev_lcell_comb \bcd|A27|WideOr3~0 (
+// Equation(s):
+// \bcd|A27|WideOr3~0_combout  = ( \bcd|A23|WideOr1~0_combout  & ( (!\bcd|A24|WideOr0~0_combout  & ((!\bcd|A23|WideOr3~0_combout ) # (!\bcd|A23|WideOr2~0_combout ))) ) ) # ( !\bcd|A23|WideOr1~0_combout  & ( (!\bcd|A23|WideOr2~0_combout  & 
+// ((\bcd|A24|WideOr0~0_combout ))) # (\bcd|A23|WideOr2~0_combout  & (\bcd|A23|WideOr3~0_combout  & !\bcd|A24|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A23|WideOr3~0_combout ),
+	.datab(!\bcd|A23|WideOr2~0_combout ),
+	.datac(!\bcd|A24|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A23|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A27|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A27|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A27|WideOr3~0 .lut_mask = 64'h1C1C1C1CE0E0E0E0;
+defparam \bcd|A27|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N51
+cyclonev_lcell_comb \h2|WideOr6~0 (
+// Equation(s):
+// \h2|WideOr6~0_combout  = ( \bcd|A27|WideOr3~0_combout  & ( (!\bcd|A27|WideOr1~0_combout ) # ((!\bcd|A28|WideOr0~0_combout ) # (\bcd|A27|WideOr2~0_combout )) ) ) # ( !\bcd|A27|WideOr3~0_combout  & ( (!\bcd|A27|WideOr1~0_combout  & 
+// (!\bcd|A28|WideOr0~0_combout  $ (\bcd|A27|WideOr2~0_combout ))) # (\bcd|A27|WideOr1~0_combout  & ((!\bcd|A28|WideOr0~0_combout ) # (!\bcd|A27|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A27|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A28|WideOr0~0_combout ),
+	.datad(!\bcd|A27|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr6~0 .extended_lut = "off";
+defparam \h2|WideOr6~0 .lut_mask = 64'hF55AF55AFAFFFAFF;
+defparam \h2|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N30
+cyclonev_lcell_comb \h2|WideOr5~0 (
+// Equation(s):
+// \h2|WideOr5~0_combout  = ( \bcd|A28|WideOr0~0_combout  & ( (!\bcd|A27|WideOr3~0_combout  & (!\bcd|A27|WideOr1~0_combout  & \bcd|A27|WideOr2~0_combout )) # (\bcd|A27|WideOr3~0_combout  & (\bcd|A27|WideOr1~0_combout )) ) ) # ( !\bcd|A28|WideOr0~0_combout  & 
+// ( (\bcd|A27|WideOr2~0_combout  & ((\bcd|A27|WideOr1~0_combout ) # (\bcd|A27|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A27|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A27|WideOr1~0_combout ),
+	.datad(!\bcd|A27|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr5~0 .extended_lut = "off";
+defparam \h2|WideOr5~0 .lut_mask = 64'h005F005F05A505A5;
+defparam \h2|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N33
+cyclonev_lcell_comb \h2|WideOr4~0 (
+// Equation(s):
+// \h2|WideOr4~0_combout  = ( \bcd|A27|WideOr1~0_combout  & ( (\bcd|A27|WideOr2~0_combout  & ((!\bcd|A28|WideOr0~0_combout ) # (\bcd|A27|WideOr3~0_combout ))) ) ) # ( !\bcd|A27|WideOr1~0_combout  & ( (\bcd|A27|WideOr3~0_combout  & 
+// (!\bcd|A28|WideOr0~0_combout  & !\bcd|A27|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A27|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A27|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr4~0 .extended_lut = "off";
+defparam \h2|WideOr4~0 .lut_mask = 64'h4400440000DD00DD;
+defparam \h2|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N36
+cyclonev_lcell_comb \h2|WideOr3~0 (
+// Equation(s):
+// \h2|WideOr3~0_combout  = ( \bcd|A28|WideOr0~0_combout  & ( !\bcd|A27|WideOr3~0_combout  $ (!\bcd|A27|WideOr2~0_combout ) ) ) # ( !\bcd|A28|WideOr0~0_combout  & ( (!\bcd|A27|WideOr3~0_combout  & ((!\bcd|A27|WideOr2~0_combout ) # (\bcd|A27|WideOr1~0_combout 
+// ))) # (\bcd|A27|WideOr3~0_combout  & ((!\bcd|A27|WideOr1~0_combout ) # (\bcd|A27|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A27|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A27|WideOr1~0_combout ),
+	.datad(!\bcd|A27|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr3~0 .extended_lut = "off";
+defparam \h2|WideOr3~0 .lut_mask = 64'hFA5FFA5F55AA55AA;
+defparam \h2|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N39
+cyclonev_lcell_comb \h2|WideOr2~0 (
+// Equation(s):
+// \h2|WideOr2~0_combout  = ( \bcd|A27|WideOr1~0_combout  & ( ((!\bcd|A28|WideOr0~0_combout ) # (\bcd|A27|WideOr2~0_combout )) # (\bcd|A27|WideOr3~0_combout ) ) ) # ( !\bcd|A27|WideOr1~0_combout  & ( (!\bcd|A28|WideOr0~0_combout  & 
+// ((!\bcd|A27|WideOr2~0_combout ) # (\bcd|A27|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A27|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A27|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr2~0 .extended_lut = "off";
+defparam \h2|WideOr2~0 .lut_mask = 64'hCC44CC44DDFFDDFF;
+defparam \h2|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N42
+cyclonev_lcell_comb \h2|WideOr1~0 (
+// Equation(s):
+// \h2|WideOr1~0_combout  = ( \bcd|A28|WideOr0~0_combout  & ( !\bcd|A27|WideOr1~0_combout  $ (((!\bcd|A27|WideOr2~0_combout ) # (\bcd|A27|WideOr3~0_combout ))) ) ) # ( !\bcd|A28|WideOr0~0_combout  & ( (!\bcd|A27|WideOr3~0_combout ) # 
+// ((\bcd|A27|WideOr2~0_combout ) # (\bcd|A27|WideOr1~0_combout )) ) )
+
+	.dataa(!\bcd|A27|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A27|WideOr1~0_combout ),
+	.datad(!\bcd|A27|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr1~0 .extended_lut = "off";
+defparam \h2|WideOr1~0 .lut_mask = 64'hAFFFAFFF0FA50FA5;
+defparam \h2|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N45
+cyclonev_lcell_comb \h2|WideOr0~0 (
+// Equation(s):
+// \h2|WideOr0~0_combout  = ( \bcd|A27|WideOr1~0_combout  & ( ((!\bcd|A27|WideOr2~0_combout ) # (\bcd|A28|WideOr0~0_combout )) # (\bcd|A27|WideOr3~0_combout ) ) ) # ( !\bcd|A27|WideOr1~0_combout  & ( (!\bcd|A27|WideOr3~0_combout  & 
+// ((\bcd|A27|WideOr2~0_combout ))) # (\bcd|A27|WideOr3~0_combout  & ((!\bcd|A28|WideOr0~0_combout ) # (!\bcd|A27|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A27|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A27|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr0~0 .extended_lut = "off";
+defparam \h2|WideOr0~0 .lut_mask = 64'h55EE55EEFF77FF77;
+defparam \h2|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N12
+cyclonev_lcell_comb \bcd|A7|WideOr0~0 (
+// Equation(s):
+// \bcd|A7|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  $ (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & (((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )))) ) ) ) # ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) # 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ))) ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A7|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A7|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A7|WideOr0~0 .lut_mask = 64'h55445500552A55AA;
+defparam \bcd|A7|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y9_N24
+cyclonev_lcell_comb \bcd|A5|WideOr0~0 (
+// Equation(s):
+// \bcd|A5|WideOr0~0_combout  = ( \bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( \bcd|A1|WideOr0~0_combout  ) ) ) # ( !\bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( \bcd|A1|WideOr0~0_combout  ) ) ) # ( \bcd|A2|WideOr0~0_combout 
+//  & ( !\bcd|A4|WideOr0~0_combout  & ( \bcd|A1|WideOr0~0_combout  ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A1|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\bcd|A2|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A5|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A5|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A5|WideOr0~0 .lut_mask = 64'h0000333333333333;
+defparam \bcd|A5|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y9_N48
+cyclonev_lcell_comb \bcd|A10|WideOr0~0 (
+// Equation(s):
+// \bcd|A10|WideOr0~0_combout  = ( \bcd|A7|WideOr1~0_combout  & ( (!\bcd|A7|WideOr2~0_combout ) # ((!\bcd|A7|WideOr3~0_combout  & !\bcd|A8|WideOr0~0_combout )) ) ) # ( !\bcd|A7|WideOr1~0_combout  & ( (\bcd|A7|WideOr2~0_combout  & ((\bcd|A8|WideOr0~0_combout 
+// ) # (\bcd|A7|WideOr3~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A7|WideOr2~0_combout ),
+	.datac(!\bcd|A7|WideOr3~0_combout ),
+	.datad(!\bcd|A8|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A7|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A10|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A10|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A10|WideOr0~0 .lut_mask = 64'h03330333FCCCFCCC;
+defparam \bcd|A10|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N3
+cyclonev_lcell_comb \bcd|A12|WideOr0~0 (
+// Equation(s):
+// \bcd|A12|WideOr0~0_combout  = ( \bcd|A10|WideOr0~0_combout  & ( \bcd|A5|WideOr0~0_combout  ) ) # ( !\bcd|A10|WideOr0~0_combout  & ( (\bcd|A7|WideOr0~0_combout  & \bcd|A5|WideOr0~0_combout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\bcd|A7|WideOr0~0_combout ),
+	.datad(!\bcd|A5|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A10|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A12|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A12|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A12|WideOr0~0 .lut_mask = 64'h000F000F00FF00FF;
+defparam \bcd|A12|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N48
+cyclonev_lcell_comb \bcd|A15|WideOr0~0 (
+// Equation(s):
+// \bcd|A15|WideOr0~0_combout  = ( \bcd|A11|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( !\bcd|A1|WideOr0~0_combout  $ (!\bcd|A2|WideOr0~0_combout ) ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( 
+// (!\bcd|A1|WideOr0~0_combout  & (\bcd|A2|WideOr0~0_combout  & ((\bcd|A6|WideOr0~0_combout ) # (\bcd|A8|WideOr0~0_combout )))) # (\bcd|A1|WideOr0~0_combout  & (!\bcd|A2|WideOr0~0_combout )) ) ) ) # ( \bcd|A11|WideOr0~0_combout  & ( 
+// !\bcd|A4|WideOr0~0_combout  & ( (\bcd|A1|WideOr0~0_combout  & ((!\bcd|A2|WideOr0~0_combout ) # ((!\bcd|A8|WideOr0~0_combout  & !\bcd|A6|WideOr0~0_combout )))) ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( 
+// (\bcd|A1|WideOr0~0_combout  & ((!\bcd|A2|WideOr0~0_combout ) # ((!\bcd|A8|WideOr0~0_combout  & !\bcd|A6|WideOr0~0_combout )))) ) ) )
+
+	.dataa(!\bcd|A1|WideOr0~0_combout ),
+	.datab(!\bcd|A2|WideOr0~0_combout ),
+	.datac(!\bcd|A8|WideOr0~0_combout ),
+	.datad(!\bcd|A6|WideOr0~0_combout ),
+	.datae(!\bcd|A11|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A15|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A15|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A15|WideOr0~0 .lut_mask = 64'h5444544446666666;
+defparam \bcd|A15|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N6
+cyclonev_lcell_comb \bcd|A23|WideOr0~0 (
+// Equation(s):
+// \bcd|A23|WideOr0~0_combout  = ( \bcd|A20|WideOr0~0_combout  & ( !\bcd|A19|WideOr1~0_combout  $ (!\bcd|A19|WideOr2~0_combout ) ) ) # ( !\bcd|A20|WideOr0~0_combout  & ( !\bcd|A19|WideOr1~0_combout  $ (((!\bcd|A19|WideOr3~0_combout ) # 
+// (!\bcd|A19|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A19|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A19|WideOr1~0_combout ),
+	.datad(!\bcd|A19|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A23|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A23|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A23|WideOr0~0 .lut_mask = 64'h0F5A0F5A0FF00FF0;
+defparam \bcd|A23|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N9
+cyclonev_lcell_comb \bcd|A19|WideOr0~0 (
+// Equation(s):
+// \bcd|A19|WideOr0~0_combout  = ( \bcd|A15|WideOr3~0_combout  & ( !\bcd|A15|WideOr2~0_combout  $ (!\bcd|A15|WideOr1~0_combout ) ) ) # ( !\bcd|A15|WideOr3~0_combout  & ( !\bcd|A15|WideOr1~0_combout  $ (((!\bcd|A15|WideOr2~0_combout ) # 
+// (!\bcd|A16|WideOr0~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A15|WideOr2~0_combout ),
+	.datac(!\bcd|A15|WideOr1~0_combout ),
+	.datad(!\bcd|A16|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A15|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A19|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A19|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A19|WideOr0~0 .lut_mask = 64'h0F3C0F3C3C3C3C3C;
+defparam \bcd|A19|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N48
+cyclonev_lcell_comb \bcd|A26|Decoder0~2 (
+// Equation(s):
+// \bcd|A26|Decoder0~2_combout  = ( \bcd|A19|WideOr0~0_combout  & ( (!\bcd|A12|WideOr0~0_combout  & (!\bcd|A15|WideOr0~0_combout  & !\bcd|A23|WideOr0~0_combout )) ) ) # ( !\bcd|A19|WideOr0~0_combout  & ( (\bcd|A12|WideOr0~0_combout  & 
+// (\bcd|A15|WideOr0~0_combout  & !\bcd|A23|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A12|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr0~0_combout ),
+	.datac(!\bcd|A23|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~2 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~2 .lut_mask = 64'h1010101080808080;
+defparam \bcd|A26|Decoder0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N6
+cyclonev_lcell_comb \bcd|A26|Decoder0~0 (
+// Equation(s):
+// \bcd|A26|Decoder0~0_combout  = ( \bcd|A19|WideOr0~0_combout  & ( (!\bcd|A12|WideOr0~0_combout  & (!\bcd|A15|WideOr0~0_combout  & \bcd|A23|WideOr0~0_combout )) ) ) # ( !\bcd|A19|WideOr0~0_combout  & ( (\bcd|A12|WideOr0~0_combout  & 
+// (\bcd|A15|WideOr0~0_combout  & \bcd|A23|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A12|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr0~0_combout ),
+	.datac(!\bcd|A23|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~0 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~0 .lut_mask = 64'h0101010108080808;
+defparam \bcd|A26|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N54
+cyclonev_lcell_comb \bcd|A26|WideOr2 (
+// Equation(s):
+// \bcd|A26|WideOr2~combout  = ( \bcd|A12|WideOr0~0_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( (!\bcd|A26|Decoder0~2_combout  & (((\bcd|A19|WideOr0~0_combout ) # (\bcd|A23|WideOr0~0_combout )) # (\bcd|A15|WideOr0~0_combout ))) ) ) ) # ( 
+// !\bcd|A12|WideOr0~0_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( (!\bcd|A26|Decoder0~2_combout  & ((!\bcd|A15|WideOr0~0_combout ) # ((!\bcd|A23|WideOr0~0_combout ) # (!\bcd|A19|WideOr0~0_combout )))) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~2_combout ),
+	.datab(!\bcd|A15|WideOr0~0_combout ),
+	.datac(!\bcd|A23|WideOr0~0_combout ),
+	.datad(!\bcd|A19|WideOr0~0_combout ),
+	.datae(!\bcd|A12|WideOr0~0_combout ),
+	.dataf(!\bcd|A26|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|WideOr2~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|WideOr2 .extended_lut = "off";
+defparam \bcd|A26|WideOr2 .lut_mask = 64'hAAA82AAA00000000;
+defparam \bcd|A26|WideOr2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N15
+cyclonev_lcell_comb \bcd|A27|WideOr0~0 (
+// Equation(s):
+// \bcd|A27|WideOr0~0_combout  = ( \bcd|A23|WideOr1~0_combout  & ( (!\bcd|A23|WideOr2~0_combout ) # ((!\bcd|A23|WideOr3~0_combout  & !\bcd|A24|WideOr0~0_combout )) ) ) # ( !\bcd|A23|WideOr1~0_combout  & ( (\bcd|A23|WideOr2~0_combout  & 
+// ((\bcd|A24|WideOr0~0_combout ) # (\bcd|A23|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A23|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A23|WideOr2~0_combout ),
+	.datad(!\bcd|A24|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A23|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A27|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A27|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A27|WideOr0~0 .lut_mask = 64'h050F050FFAF0FAF0;
+defparam \bcd|A27|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N51
+cyclonev_lcell_comb \bcd|A26|Decoder0~3 (
+// Equation(s):
+// \bcd|A26|Decoder0~3_combout  = ( \bcd|A19|WideOr0~0_combout  & ( (\bcd|A12|WideOr0~0_combout  & (\bcd|A15|WideOr0~0_combout  & !\bcd|A23|WideOr0~0_combout )) ) ) # ( !\bcd|A19|WideOr0~0_combout  & ( (!\bcd|A12|WideOr0~0_combout  & 
+// (\bcd|A15|WideOr0~0_combout  & !\bcd|A23|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A12|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A23|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~3 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~3 .lut_mask = 64'h2200220011001100;
+defparam \bcd|A26|Decoder0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N0
+cyclonev_lcell_comb \bcd|A26|WideOr1 (
+// Equation(s):
+// \bcd|A26|WideOr1~combout  = ( !\bcd|A26|Decoder0~3_combout  & ( (!\bcd|A12|WideOr0~0_combout ) # (((!\bcd|A23|WideOr0~0_combout ) # (\bcd|A15|WideOr0~0_combout )) # (\bcd|A19|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A12|WideOr0~0_combout ),
+	.datab(!\bcd|A19|WideOr0~0_combout ),
+	.datac(!\bcd|A23|WideOr0~0_combout ),
+	.datad(!\bcd|A15|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A26|Decoder0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|WideOr1~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|WideOr1 .extended_lut = "off";
+defparam \bcd|A26|WideOr1 .lut_mask = 64'hFBFFFBFF00000000;
+defparam \bcd|A26|WideOr1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N39
+cyclonev_lcell_comb \bcd|A26|Decoder0~1 (
+// Equation(s):
+// \bcd|A26|Decoder0~1_combout  = ( \bcd|A19|WideOr0~0_combout  & ( (\bcd|A12|WideOr0~0_combout  & (!\bcd|A15|WideOr0~0_combout  & \bcd|A23|WideOr0~0_combout )) ) ) # ( !\bcd|A19|WideOr0~0_combout  & ( (!\bcd|A12|WideOr0~0_combout  & 
+// (!\bcd|A15|WideOr0~0_combout  & \bcd|A23|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A12|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A23|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~1 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~1 .lut_mask = 64'h0088008800440044;
+defparam \bcd|A26|Decoder0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N30
+cyclonev_lcell_comb \bcd|A26|WideOr3~0 (
+// Equation(s):
+// \bcd|A26|WideOr3~0_combout  = ( \bcd|A15|WideOr0~0_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( (!\bcd|A26|Decoder0~1_combout  & (((!\bcd|A19|WideOr0~0_combout ) # (\bcd|A23|WideOr0~0_combout )) # (\bcd|A12|WideOr0~0_combout ))) ) ) ) # ( 
+// !\bcd|A15|WideOr0~0_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( (!\bcd|A26|Decoder0~1_combout  & ((!\bcd|A12|WideOr0~0_combout ) # ((\bcd|A19|WideOr0~0_combout ) # (\bcd|A23|WideOr0~0_combout )))) ) ) )
+
+	.dataa(!\bcd|A12|WideOr0~0_combout ),
+	.datab(!\bcd|A26|Decoder0~1_combout ),
+	.datac(!\bcd|A23|WideOr0~0_combout ),
+	.datad(!\bcd|A19|WideOr0~0_combout ),
+	.datae(!\bcd|A15|WideOr0~0_combout ),
+	.dataf(!\bcd|A26|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A26|WideOr3~0 .lut_mask = 64'h8CCCCC4C00000000;
+defparam \bcd|A26|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N21
+cyclonev_lcell_comb \h3|WideOr6~0 (
+// Equation(s):
+// \h3|WideOr6~0_combout  = ( \bcd|A26|WideOr3~0_combout  & ( (!\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  $ (\bcd|A26|WideOr1~combout ))) # (\bcd|A26|WideOr2~combout  & ((!\bcd|A27|WideOr0~0_combout ) # (!\bcd|A26|WideOr1~combout ))) ) ) # ( 
+// !\bcd|A26|WideOr3~0_combout  & ( (!\bcd|A26|WideOr2~combout ) # ((!\bcd|A27|WideOr0~0_combout ) # (\bcd|A26|WideOr1~combout )) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr1~combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr6~0 .extended_lut = "off";
+defparam \h3|WideOr6~0 .lut_mask = 64'hEFEFEFEFD6D6D6D6;
+defparam \h3|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N0
+cyclonev_lcell_comb \h3|WideOr5~0 (
+// Equation(s):
+// \h3|WideOr5~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  $ (\bcd|A26|WideOr3~0_combout ))) ) ) # ( !\bcd|A26|WideOr1~combout  & ( (!\bcd|A27|WideOr0~0_combout  & (!\bcd|A26|WideOr2~combout )) # 
+// (\bcd|A27|WideOr0~0_combout  & ((!\bcd|A26|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr5~0 .extended_lut = "off";
+defparam \h3|WideOr5~0 .lut_mask = 64'hB8B8B8B882828282;
+defparam \h3|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N3
+cyclonev_lcell_comb \h3|WideOr4~0 (
+// Equation(s):
+// \h3|WideOr4~0_combout  = ( \bcd|A26|WideOr3~0_combout  & ( (!\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  & !\bcd|A26|WideOr1~combout )) ) ) # ( !\bcd|A26|WideOr3~0_combout  & ( (!\bcd|A26|WideOr2~combout  & ((!\bcd|A26|WideOr1~combout ))) # 
+// (\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  & \bcd|A26|WideOr1~combout )) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr1~combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr4~0 .extended_lut = "off";
+defparam \h3|WideOr4~0 .lut_mask = 64'hA4A4A4A480808080;
+defparam \h3|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N6
+cyclonev_lcell_comb \h3|WideOr3~0 (
+// Equation(s):
+// \h3|WideOr3~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  $ (\bcd|A26|WideOr3~0_combout ))) # (\bcd|A26|WideOr2~combout  & ((!\bcd|A27|WideOr0~0_combout ) # (!\bcd|A26|WideOr3~0_combout ))) ) ) # 
+// ( !\bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & ((!\bcd|A27|WideOr0~0_combout ) # (\bcd|A26|WideOr3~0_combout ))) # (\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  $ (!\bcd|A26|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr3~0 .extended_lut = "off";
+defparam \h3|WideOr3~0 .lut_mask = 64'h9E9E9E9ED6D6D6D6;
+defparam \h3|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N9
+cyclonev_lcell_comb \h3|WideOr2~0 (
+// Equation(s):
+// \h3|WideOr2~0_combout  = ( \bcd|A26|WideOr3~0_combout  & ( (!\bcd|A26|WideOr2~combout  & ((!\bcd|A26|WideOr1~combout ))) # (\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout )) ) ) # ( !\bcd|A26|WideOr3~0_combout  & ( (!\bcd|A27|WideOr0~0_combout ) 
+// # (!\bcd|A26|WideOr1~combout ) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr1~combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr2~0 .extended_lut = "off";
+defparam \h3|WideOr2~0 .lut_mask = 64'hFCFCFCFCE4E4E4E4;
+defparam \h3|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N12
+cyclonev_lcell_comb \h3|WideOr1~0 (
+// Equation(s):
+// \h3|WideOr1~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A27|WideOr0~0_combout  & ((!\bcd|A26|WideOr2~combout ) # (\bcd|A26|WideOr3~0_combout ))) # (\bcd|A27|WideOr0~0_combout  & (\bcd|A26|WideOr3~0_combout  & !\bcd|A26|WideOr2~combout )) ) ) # ( 
+// !\bcd|A26|WideOr1~combout  & ( (!\bcd|A27|WideOr0~0_combout ) # ((!\bcd|A26|WideOr3~0_combout ) # (\bcd|A26|WideOr2~combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr3~0_combout ),
+	.datad(!\bcd|A26|WideOr2~combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr1~0 .extended_lut = "off";
+defparam \h3|WideOr1~0 .lut_mask = 64'hFCFFFCFFCF0CCF0C;
+defparam \h3|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y11_N18
+cyclonev_lcell_comb \h3|WideOr0~0 (
+// Equation(s):
+// \h3|WideOr0~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & ((!\bcd|A27|WideOr0~0_combout ) # (\bcd|A26|WideOr3~0_combout ))) # (\bcd|A26|WideOr2~combout  & ((!\bcd|A26|WideOr3~0_combout ))) ) ) # ( !\bcd|A26|WideOr1~combout  & 
+// ( ((!\bcd|A26|WideOr3~0_combout ) # (\bcd|A27|WideOr0~0_combout )) # (\bcd|A26|WideOr2~combout ) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr0~0 .extended_lut = "off";
+defparam \h3|WideOr0~0 .lut_mask = 64'hF7F7F7F7DADADADA;
+defparam \h3|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N36
+cyclonev_lcell_comb \bcd|A26|Decoder0~4 (
+// Equation(s):
+// \bcd|A26|Decoder0~4_combout  = ( \bcd|A19|WideOr0~0_combout  & ( (\bcd|A12|WideOr0~0_combout  & (!\bcd|A15|WideOr0~0_combout  & !\bcd|A23|WideOr0~0_combout )) ) ) # ( !\bcd|A19|WideOr0~0_combout  & ( (!\bcd|A12|WideOr0~0_combout  & 
+// (!\bcd|A15|WideOr0~0_combout  & !\bcd|A23|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A12|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr0~0_combout ),
+	.datac(!\bcd|A23|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~4 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~4 .lut_mask = 64'h8080808040404040;
+defparam \bcd|A26|Decoder0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N9
+cyclonev_lcell_comb \bcd|A22|WideOr0~0 (
+// Equation(s):
+// \bcd|A22|WideOr0~0_combout  = ( \bcd|A19|WideOr0~0_combout  & ( !\bcd|A12|WideOr0~0_combout  ) ) # ( !\bcd|A19|WideOr0~0_combout  & ( (!\bcd|A12|WideOr0~0_combout ) # (!\bcd|A15|WideOr0~0_combout ) ) )
+
+	.dataa(!\bcd|A12|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A22|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A22|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A22|WideOr0~0 .lut_mask = 64'hEEEEEEEEAAAAAAAA;
+defparam \bcd|A22|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N24
+cyclonev_lcell_comb \h4|Decoder0~0 (
+// Equation(s):
+// \h4|Decoder0~0_combout  = ( !\bcd|A26|Decoder0~4_combout  & ( \bcd|A22|WideOr0~0_combout  & ( (!\bcd|A26|Decoder0~2_combout  & (!\bcd|A26|Decoder0~0_combout  & (!\bcd|A26|Decoder0~3_combout  & !\bcd|A26|Decoder0~1_combout ))) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~2_combout ),
+	.datab(!\bcd|A26|Decoder0~0_combout ),
+	.datac(!\bcd|A26|Decoder0~3_combout ),
+	.datad(!\bcd|A26|Decoder0~1_combout ),
+	.datae(!\bcd|A26|Decoder0~4_combout ),
+	.dataf(!\bcd|A22|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h4|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h4|Decoder0~0 .extended_lut = "off";
+defparam \h4|Decoder0~0 .lut_mask = 64'h0000000080000000;
+defparam \h4|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y9_N3
+cyclonev_lcell_comb \bcd|A13|WideOr0~0 (
+// Equation(s):
+// \bcd|A13|WideOr0~0_combout  = ( \bcd|A11|WideOr0~0_combout  & ( \bcd|A10|WideOr1~0_combout  & ( !\bcd|A10|WideOr2~0_combout  ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( \bcd|A10|WideOr1~0_combout  & ( (!\bcd|A10|WideOr3~0_combout ) # 
+// (!\bcd|A10|WideOr2~0_combout ) ) ) ) # ( \bcd|A11|WideOr0~0_combout  & ( !\bcd|A10|WideOr1~0_combout  & ( \bcd|A10|WideOr2~0_combout  ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( !\bcd|A10|WideOr1~0_combout  & ( (\bcd|A10|WideOr3~0_combout  & 
+// \bcd|A10|WideOr2~0_combout ) ) ) )
+
+	.dataa(!\bcd|A10|WideOr3~0_combout ),
+	.datab(!\bcd|A10|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\bcd|A11|WideOr0~0_combout ),
+	.dataf(!\bcd|A10|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A13|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A13|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A13|WideOr0~0 .lut_mask = 64'h11113333EEEECCCC;
+defparam \bcd|A13|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N18
+cyclonev_lcell_comb \h4|Decoder0~2 (
+// Equation(s):
+// \h4|Decoder0~2_combout  = ( \bcd|A5|WideOr0~0_combout  & ( \bcd|A10|WideOr0~0_combout  & ( \bcd|A7|WideOr0~0_combout  ) ) ) # ( \bcd|A5|WideOr0~0_combout  & ( !\bcd|A10|WideOr0~0_combout  & ( (\bcd|A7|WideOr0~0_combout  & ((\bcd|A16|WideOr0~0_combout ) # 
+// (\bcd|A13|WideOr0~0_combout ))) ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A13|WideOr0~0_combout ),
+	.datac(!\bcd|A16|WideOr0~0_combout ),
+	.datad(!\bcd|A7|WideOr0~0_combout ),
+	.datae(!\bcd|A5|WideOr0~0_combout ),
+	.dataf(!\bcd|A10|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h4|Decoder0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h4|Decoder0~2 .extended_lut = "off";
+defparam \h4|Decoder0~2 .lut_mask = 64'h0000003F000000FF;
+defparam \h4|Decoder0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N42
+cyclonev_lcell_comb \bcd|A26|WideOr0 (
+// Equation(s):
+// \bcd|A26|WideOr0~combout  = ( \bcd|A26|Decoder0~4_combout  & ( \bcd|A26|Decoder0~0_combout  ) ) # ( !\bcd|A26|Decoder0~4_combout  & ( \bcd|A26|Decoder0~0_combout  ) ) # ( \bcd|A26|Decoder0~4_combout  & ( !\bcd|A26|Decoder0~0_combout  ) ) # ( 
+// !\bcd|A26|Decoder0~4_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( ((\bcd|A26|Decoder0~3_combout ) # (\bcd|A26|Decoder0~1_combout )) # (\bcd|A26|Decoder0~2_combout ) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~2_combout ),
+	.datab(!\bcd|A26|Decoder0~1_combout ),
+	.datac(!\bcd|A26|Decoder0~3_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A26|Decoder0~4_combout ),
+	.dataf(!\bcd|A26|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|WideOr0~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|WideOr0 .extended_lut = "off";
+defparam \bcd|A26|WideOr0 .lut_mask = 64'h7F7FFFFFFFFFFFFF;
+defparam \bcd|A26|WideOr0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y11_N12
+cyclonev_lcell_comb \h4|Decoder0~1 (
+// Equation(s):
+// \h4|Decoder0~1_combout  = ( \bcd|A26|Decoder0~4_combout  & ( \bcd|A22|WideOr0~0_combout  ) ) # ( !\bcd|A26|Decoder0~4_combout  & ( \bcd|A22|WideOr0~0_combout  & ( (((\bcd|A26|Decoder0~1_combout ) # (\bcd|A26|Decoder0~3_combout )) # 
+// (\bcd|A26|Decoder0~0_combout )) # (\bcd|A26|Decoder0~2_combout ) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~2_combout ),
+	.datab(!\bcd|A26|Decoder0~0_combout ),
+	.datac(!\bcd|A26|Decoder0~3_combout ),
+	.datad(!\bcd|A26|Decoder0~1_combout ),
+	.datae(!\bcd|A26|Decoder0~4_combout ),
+	.dataf(!\bcd|A22|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h4|Decoder0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h4|Decoder0~1 .extended_lut = "off";
+defparam \h4|Decoder0~1 .lut_mask = 64'h000000007FFFFFFF;
+defparam \h4|Decoder0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X1_Y73_N0
+cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\~QUARTUS_CREATED_GND~I_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+endmodule
diff --git a/part_3/ex14/simulation/modelsim/ex10_modelsim.xrf b/part_3/ex14/simulation/modelsim/ex10_modelsim.xrf
new file mode 100755
index 0000000..491bf63
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/ex10_modelsim.xrf
@@ -0,0 +1,447 @@
+vendor_name = ModelSim
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/add3_ge5.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/hex_to_7seg.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.qip
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/tick_5000.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/spi2dac.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/pwm.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.qip
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/add_offset.v
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/stratix_ram_block.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_mux.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_decode.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/a_rdenreg.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altrom.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altram.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altdpram.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/altsyncram_6ng1.tdf
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/rom_data/rom_data.mif
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/multcore.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/bypassff.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altshift.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/csa_add.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/muleabz.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mul_lfrg.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mul_boothc.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult_y.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/dffpipe.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/addcore.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/look_add.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_d9h.tdf
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_89h.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altshift.tdf
+design_name = ex14
+instance = comp, \DAC_CS~output , DAC_CS~output, ex14, 1
+instance = comp, \DAC_SDI~output , DAC_SDI~output, ex14, 1
+instance = comp, \DAC_LD~output , DAC_LD~output, ex14, 1
+instance = comp, \DAC_SCK~output , DAC_SCK~output, ex14, 1
+instance = comp, \PWM_OUT~output , PWM_OUT~output, ex14, 1
+instance = comp, \HEX0[0]~output , HEX0[0]~output, ex14, 1
+instance = comp, \HEX0[1]~output , HEX0[1]~output, ex14, 1
+instance = comp, \HEX0[2]~output , HEX0[2]~output, ex14, 1
+instance = comp, \HEX0[3]~output , HEX0[3]~output, ex14, 1
+instance = comp, \HEX0[4]~output , HEX0[4]~output, ex14, 1
+instance = comp, \HEX0[5]~output , HEX0[5]~output, ex14, 1
+instance = comp, \HEX0[6]~output , HEX0[6]~output, ex14, 1
+instance = comp, \HEX1[0]~output , HEX1[0]~output, ex14, 1
+instance = comp, \HEX1[1]~output , HEX1[1]~output, ex14, 1
+instance = comp, \HEX1[2]~output , HEX1[2]~output, ex14, 1
+instance = comp, \HEX1[3]~output , HEX1[3]~output, ex14, 1
+instance = comp, \HEX1[4]~output , HEX1[4]~output, ex14, 1
+instance = comp, \HEX1[5]~output , HEX1[5]~output, ex14, 1
+instance = comp, \HEX1[6]~output , HEX1[6]~output, ex14, 1
+instance = comp, \HEX2[0]~output , HEX2[0]~output, ex14, 1
+instance = comp, \HEX2[1]~output , HEX2[1]~output, ex14, 1
+instance = comp, \HEX2[2]~output , HEX2[2]~output, ex14, 1
+instance = comp, \HEX2[3]~output , HEX2[3]~output, ex14, 1
+instance = comp, \HEX2[4]~output , HEX2[4]~output, ex14, 1
+instance = comp, \HEX2[5]~output , HEX2[5]~output, ex14, 1
+instance = comp, \HEX2[6]~output , HEX2[6]~output, ex14, 1
+instance = comp, \HEX3[0]~output , HEX3[0]~output, ex14, 1
+instance = comp, \HEX3[1]~output , HEX3[1]~output, ex14, 1
+instance = comp, \HEX3[2]~output , HEX3[2]~output, ex14, 1
+instance = comp, \HEX3[3]~output , HEX3[3]~output, ex14, 1
+instance = comp, \HEX3[4]~output , HEX3[4]~output, ex14, 1
+instance = comp, \HEX3[5]~output , HEX3[5]~output, ex14, 1
+instance = comp, \HEX3[6]~output , HEX3[6]~output, ex14, 1
+instance = comp, \HEX4[0]~output , HEX4[0]~output, ex14, 1
+instance = comp, \HEX4[1]~output , HEX4[1]~output, ex14, 1
+instance = comp, \HEX4[2]~output , HEX4[2]~output, ex14, 1
+instance = comp, \HEX4[3]~output , HEX4[3]~output, ex14, 1
+instance = comp, \HEX4[4]~output , HEX4[4]~output, ex14, 1
+instance = comp, \HEX4[5]~output , HEX4[5]~output, ex14, 1
+instance = comp, \HEX4[6]~output , HEX4[6]~output, ex14, 1
+instance = comp, \CLOCK_50~input , CLOCK_50~input, ex14, 1
+instance = comp, \CLOCK_50~inputCLKENA0 , CLOCK_50~inputCLKENA0, ex14, 1
+instance = comp, \dac|ctr[2] , dac|ctr[2], ex14, 1
+instance = comp, \dac|ctr~1 , dac|ctr~1, ex14, 1
+instance = comp, \dac|ctr[0] , dac|ctr[0], ex14, 1
+instance = comp, \dac|Add0~1 , dac|Add0~1, ex14, 1
+instance = comp, \dac|ctr[3] , dac|ctr[3], ex14, 1
+instance = comp, \dac|ctr[0]~DUPLICATE , dac|ctr[0]~DUPLICATE, ex14, 1
+instance = comp, \dac|Add0~0 , dac|Add0~0, ex14, 1
+instance = comp, \dac|ctr[4] , dac|ctr[4], ex14, 1
+instance = comp, \dac|ctr[3]~DUPLICATE , dac|ctr[3]~DUPLICATE, ex14, 1
+instance = comp, \dac|ctr~0 , dac|ctr~0, ex14, 1
+instance = comp, \dac|ctr[2]~DUPLICATE , dac|ctr[2]~DUPLICATE, ex14, 1
+instance = comp, \dac|ctr~2 , dac|ctr~2, ex14, 1
+instance = comp, \dac|ctr[1] , dac|ctr[1], ex14, 1
+instance = comp, \dac|clk_1MHz~0 , dac|clk_1MHz~0, ex14, 1
+instance = comp, \dac|clk_1MHz~feeder , dac|clk_1MHz~feeder, ex14, 1
+instance = comp, \dac|clk_1MHz , dac|clk_1MHz, ex14, 1
+instance = comp, \dac|state~0 , dac|state~0, ex14, 1
+instance = comp, \dac|state[4] , dac|state[4], ex14, 1
+instance = comp, \tick|count[15]~DUPLICATE , tick|count[15]~DUPLICATE, ex14, 1
+instance = comp, \tick|Add0~9 , tick|Add0~9, ex14, 1
+instance = comp, \tick|count[0]~1 , tick|count[0]~1, ex14, 1
+instance = comp, \tick|count[0] , tick|count[0], ex14, 1
+instance = comp, \tick|Add0~13 , tick|Add0~13, ex14, 1
+instance = comp, \tick|count[1]~2 , tick|count[1]~2, ex14, 1
+instance = comp, \tick|count[1] , tick|count[1], ex14, 1
+instance = comp, \tick|Add0~17 , tick|Add0~17, ex14, 1
+instance = comp, \tick|count[2]~3 , tick|count[2]~3, ex14, 1
+instance = comp, \tick|count[2] , tick|count[2], ex14, 1
+instance = comp, \tick|Add0~37 , tick|Add0~37, ex14, 1
+instance = comp, \tick|count[3] , tick|count[3], ex14, 1
+instance = comp, \tick|Add0~41 , tick|Add0~41, ex14, 1
+instance = comp, \tick|count[4] , tick|count[4], ex14, 1
+instance = comp, \tick|Add0~45 , tick|Add0~45, ex14, 1
+instance = comp, \tick|count[5]~feeder , tick|count[5]~feeder, ex14, 1
+instance = comp, \tick|count[5]~DUPLICATE , tick|count[5]~DUPLICATE, ex14, 1
+instance = comp, \tick|Add0~5 , tick|Add0~5, ex14, 1
+instance = comp, \tick|count[6] , tick|count[6], ex14, 1
+instance = comp, \tick|Add0~21 , tick|Add0~21, ex14, 1
+instance = comp, \tick|count[7]~4 , tick|count[7]~4, ex14, 1
+instance = comp, \tick|count[7]~DUPLICATE , tick|count[7]~DUPLICATE, ex14, 1
+instance = comp, \tick|Add0~25 , tick|Add0~25, ex14, 1
+instance = comp, \tick|count[8]~5 , tick|count[8]~5, ex14, 1
+instance = comp, \tick|count[8] , tick|count[8], ex14, 1
+instance = comp, \tick|Add0~1 , tick|Add0~1, ex14, 1
+instance = comp, \tick|count[9]~0 , tick|count[9]~0, ex14, 1
+instance = comp, \tick|count[9] , tick|count[9], ex14, 1
+instance = comp, \tick|Add0~49 , tick|Add0~49, ex14, 1
+instance = comp, \tick|count[10] , tick|count[10], ex14, 1
+instance = comp, \tick|Add0~53 , tick|Add0~53, ex14, 1
+instance = comp, \tick|count[11] , tick|count[11], ex14, 1
+instance = comp, \tick|Add0~29 , tick|Add0~29, ex14, 1
+instance = comp, \tick|count[12]~6 , tick|count[12]~6, ex14, 1
+instance = comp, \tick|count[12] , tick|count[12], ex14, 1
+instance = comp, \tick|Add0~57 , tick|Add0~57, ex14, 1
+instance = comp, \tick|count[13] , tick|count[13], ex14, 1
+instance = comp, \tick|Add0~61 , tick|Add0~61, ex14, 1
+instance = comp, \tick|count[14] , tick|count[14], ex14, 1
+instance = comp, \tick|Add0~33 , tick|Add0~33, ex14, 1
+instance = comp, \tick|count[15] , tick|count[15], ex14, 1
+instance = comp, \tick|count[5] , tick|count[5], ex14, 1
+instance = comp, \tick|Equal0~1 , tick|Equal0~1, ex14, 1
+instance = comp, \tick|count[7] , tick|count[7], ex14, 1
+instance = comp, \tick|Equal0~0 , tick|Equal0~0, ex14, 1
+instance = comp, \tick|Equal0~2 , tick|Equal0~2, ex14, 1
+instance = comp, \tick|Equal0~3 , tick|Equal0~3, ex14, 1
+instance = comp, \tick|CLK_OUT~feeder , tick|CLK_OUT~feeder, ex14, 1
+instance = comp, \tick|CLK_OUT , tick|CLK_OUT, ex14, 1
+instance = comp, \dac|sr_state.IDLE~0 , dac|sr_state.IDLE~0, ex14, 1
+instance = comp, \dac|sr_state.IDLE , dac|sr_state.IDLE, ex14, 1
+instance = comp, \dac|Selector2~0 , dac|Selector2~0, ex14, 1
+instance = comp, \dac|sr_state.WAIT_CSB_HIGH , dac|sr_state.WAIT_CSB_HIGH, ex14, 1
+instance = comp, \dac|sr_state.WAIT_CSB_FALL~0 , dac|sr_state.WAIT_CSB_FALL~0, ex14, 1
+instance = comp, \dac|sr_state.WAIT_CSB_FALL , dac|sr_state.WAIT_CSB_FALL, ex14, 1
+instance = comp, \dac|Selector3~0 , dac|Selector3~0, ex14, 1
+instance = comp, \dac|state[0] , dac|state[0], ex14, 1
+instance = comp, \dac|state~2 , dac|state~2, ex14, 1
+instance = comp, \dac|state[2] , dac|state[2], ex14, 1
+instance = comp, \dac|state[3] , dac|state[3], ex14, 1
+instance = comp, \dac|state~3 , dac|state~3, ex14, 1
+instance = comp, \dac|state[3]~DUPLICATE , dac|state[3]~DUPLICATE, ex14, 1
+instance = comp, \dac|state~1 , dac|state~1, ex14, 1
+instance = comp, \dac|state[1] , dac|state[1], ex14, 1
+instance = comp, \dac|WideNor0 , dac|WideNor0, ex14, 1
+instance = comp, \SW[0]~input , SW[0]~input, ex14, 1
+instance = comp, \fin_address|Add0~1 , fin_address|Add0~1, ex14, 1
+instance = comp, \fin_address|address[0] , fin_address|address[0], ex14, 1
+instance = comp, \SW[1]~input , SW[1]~input, ex14, 1
+instance = comp, \fin_address|Add0~5 , fin_address|Add0~5, ex14, 1
+instance = comp, \fin_address|address[1] , fin_address|address[1], ex14, 1
+instance = comp, \SW[2]~input , SW[2]~input, ex14, 1
+instance = comp, \fin_address|Add0~9 , fin_address|Add0~9, ex14, 1
+instance = comp, \fin_address|address[2]~feeder , fin_address|address[2]~feeder, ex14, 1
+instance = comp, \fin_address|address[2] , fin_address|address[2], ex14, 1
+instance = comp, \SW[3]~input , SW[3]~input, ex14, 1
+instance = comp, \fin_address|Add0~13 , fin_address|Add0~13, ex14, 1
+instance = comp, \fin_address|address[3]~feeder , fin_address|address[3]~feeder, ex14, 1
+instance = comp, \fin_address|address[3] , fin_address|address[3], ex14, 1
+instance = comp, \SW[4]~input , SW[4]~input, ex14, 1
+instance = comp, \fin_address|Add0~17 , fin_address|Add0~17, ex14, 1
+instance = comp, \fin_address|address[4]~feeder , fin_address|address[4]~feeder, ex14, 1
+instance = comp, \fin_address|address[4] , fin_address|address[4], ex14, 1
+instance = comp, \SW[5]~input , SW[5]~input, ex14, 1
+instance = comp, \fin_address|Add0~21 , fin_address|Add0~21, ex14, 1
+instance = comp, \fin_address|address[5]~feeder , fin_address|address[5]~feeder, ex14, 1
+instance = comp, \fin_address|address[5] , fin_address|address[5], ex14, 1
+instance = comp, \SW[6]~input , SW[6]~input, ex14, 1
+instance = comp, \fin_address|Add0~25 , fin_address|Add0~25, ex14, 1
+instance = comp, \fin_address|address[6]~feeder , fin_address|address[6]~feeder, ex14, 1
+instance = comp, \fin_address|address[6] , fin_address|address[6], ex14, 1
+instance = comp, \SW[7]~input , SW[7]~input, ex14, 1
+instance = comp, \fin_address|Add0~29 , fin_address|Add0~29, ex14, 1
+instance = comp, \fin_address|address[7]~feeder , fin_address|address[7]~feeder, ex14, 1
+instance = comp, \fin_address|address[7] , fin_address|address[7], ex14, 1
+instance = comp, \SW[8]~input , SW[8]~input, ex14, 1
+instance = comp, \fin_address|Add0~33 , fin_address|Add0~33, ex14, 1
+instance = comp, \fin_address|address[8]~feeder , fin_address|address[8]~feeder, ex14, 1
+instance = comp, \fin_address|address[8] , fin_address|address[8], ex14, 1
+instance = comp, \SW[9]~input , SW[9]~input, ex14, 1
+instance = comp, \fin_address|Add0~37 , fin_address|Add0~37, ex14, 1
+instance = comp, \fin_address|address[9]~feeder , fin_address|address[9]~feeder, ex14, 1
+instance = comp, \fin_address|address[9] , fin_address|address[9], ex14, 1
+instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, ex14, 1
+instance = comp, \dac|shift_reg[11]~feeder , dac|shift_reg[11]~feeder, ex14, 1
+instance = comp, \dac|shift_reg[10]~feeder , dac|shift_reg[10]~feeder, ex14, 1
+instance = comp, \dac|shift_reg[9]~feeder , dac|shift_reg[9]~feeder, ex14, 1
+instance = comp, \dac|shift_reg[8]~feeder , dac|shift_reg[8]~feeder, ex14, 1
+instance = comp, \dac|shift_reg[7]~feeder , dac|shift_reg[7]~feeder, ex14, 1
+instance = comp, \dac|shift_reg[6]~feeder , dac|shift_reg[6]~feeder, ex14, 1
+instance = comp, \dac|shift_reg[5]~feeder , dac|shift_reg[5]~feeder, ex14, 1
+instance = comp, \dac|shift_reg[4]~feeder , dac|shift_reg[4]~feeder, ex14, 1
+instance = comp, \dac|shift_reg[3]~feeder , dac|shift_reg[3]~feeder, ex14, 1
+instance = comp, \dac|shift_reg~4 , dac|shift_reg~4, ex14, 1
+instance = comp, \dac|shift_reg[2] , dac|shift_reg[2], ex14, 1
+instance = comp, \dac|always5~0 , dac|always5~0, ex14, 1
+instance = comp, \dac|shift_reg[3] , dac|shift_reg[3], ex14, 1
+instance = comp, \dac|shift_reg[4] , dac|shift_reg[4], ex14, 1
+instance = comp, \dac|shift_reg[5] , dac|shift_reg[5], ex14, 1
+instance = comp, \dac|shift_reg[6] , dac|shift_reg[6], ex14, 1
+instance = comp, \dac|shift_reg[7] , dac|shift_reg[7], ex14, 1
+instance = comp, \dac|shift_reg[8] , dac|shift_reg[8], ex14, 1
+instance = comp, \dac|shift_reg[9] , dac|shift_reg[9], ex14, 1
+instance = comp, \dac|shift_reg[10] , dac|shift_reg[10], ex14, 1
+instance = comp, \dac|shift_reg[11] , dac|shift_reg[11], ex14, 1
+instance = comp, \dac|shift_reg~3 , dac|shift_reg~3, ex14, 1
+instance = comp, \dac|shift_reg[12] , dac|shift_reg[12], ex14, 1
+instance = comp, \dac|shift_reg~2 , dac|shift_reg~2, ex14, 1
+instance = comp, \dac|shift_reg[13] , dac|shift_reg[13], ex14, 1
+instance = comp, \dac|shift_reg~1 , dac|shift_reg~1, ex14, 1
+instance = comp, \dac|shift_reg[14] , dac|shift_reg[14], ex14, 1
+instance = comp, \dac|shift_reg~0 , dac|shift_reg~0, ex14, 1
+instance = comp, \dac|shift_reg[15] , dac|shift_reg[15], ex14, 1
+instance = comp, \dac|Equal2~0 , dac|Equal2~0, ex14, 1
+instance = comp, \dac|dac_sck , dac|dac_sck, ex14, 1
+instance = comp, \p|count[0]~0 , p|count[0]~0, ex14, 1
+instance = comp, \p|count[0] , p|count[0], ex14, 1
+instance = comp, \p|Add0~33 , p|Add0~33, ex14, 1
+instance = comp, \p|count[1] , p|count[1], ex14, 1
+instance = comp, \p|Add0~29 , p|Add0~29, ex14, 1
+instance = comp, \p|count[2] , p|count[2], ex14, 1
+instance = comp, \p|Add0~25 , p|Add0~25, ex14, 1
+instance = comp, \p|count[3] , p|count[3], ex14, 1
+instance = comp, \p|Add0~21 , p|Add0~21, ex14, 1
+instance = comp, \p|count[4] , p|count[4], ex14, 1
+instance = comp, \p|Add0~17 , p|Add0~17, ex14, 1
+instance = comp, \p|count[5] , p|count[5], ex14, 1
+instance = comp, \p|Add0~13 , p|Add0~13, ex14, 1
+instance = comp, \p|count[6] , p|count[6], ex14, 1
+instance = comp, \p|Add0~9 , p|Add0~9, ex14, 1
+instance = comp, \p|count[7] , p|count[7], ex14, 1
+instance = comp, \p|Add0~5 , p|Add0~5, ex14, 1
+instance = comp, \p|count[8] , p|count[8], ex14, 1
+instance = comp, \p|Add0~1 , p|Add0~1, ex14, 1
+instance = comp, \p|count[9] , p|count[9], ex14, 1
+instance = comp, \p|d[9] , p|d[9], ex14, 1
+instance = comp, \p|d[8] , p|d[8], ex14, 1
+instance = comp, \p|d[7] , p|d[7], ex14, 1
+instance = comp, \p|LessThan0~0 , p|LessThan0~0, ex14, 1
+instance = comp, \p|d[6]~feeder , p|d[6]~feeder, ex14, 1
+instance = comp, \p|d[6] , p|d[6], ex14, 1
+instance = comp, \p|d[3] , p|d[3], ex14, 1
+instance = comp, \p|d[4] , p|d[4], ex14, 1
+instance = comp, \p|d[2] , p|d[2], ex14, 1
+instance = comp, \p|d[1] , p|d[1], ex14, 1
+instance = comp, \p|d[0] , p|d[0], ex14, 1
+instance = comp, \p|count[0]~DUPLICATE , p|count[0]~DUPLICATE, ex14, 1
+instance = comp, \p|LessThan0~2 , p|LessThan0~2, ex14, 1
+instance = comp, \p|LessThan0~3 , p|LessThan0~3, ex14, 1
+instance = comp, \p|d[5] , p|d[5], ex14, 1
+instance = comp, \p|LessThan0~1 , p|LessThan0~1, ex14, 1
+instance = comp, \p|LessThan0~4 , p|LessThan0~4, ex14, 1
+instance = comp, \p|LessThan0~5 , p|LessThan0~5, ex14, 1
+instance = comp, \p|pwm_out , p|pwm_out, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[1][17]~5 , mult|lpm_mult_component|mult_core|romout[1][17]~5, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][17]~4 , mult|lpm_mult_component|mult_core|romout[0][17]~4, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][16]~3 , mult|lpm_mult_component|mult_core|romout[0][16]~3, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][15]~2 , mult|lpm_mult_component|mult_core|romout[0][15]~2, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][14]~1 , mult|lpm_mult_component|mult_core|romout[0][14]~1, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[1][9]~0 , mult|lpm_mult_component|mult_core|romout[1][9]~0, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41, ex14, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45, ex14, 1
+instance = comp, \bcd|A2|WideOr3~0 , bcd|A2|WideOr3~0, ex14, 1
+instance = comp, \bcd|A2|WideOr2~0 , bcd|A2|WideOr2~0, ex14, 1
+instance = comp, \bcd|A2|WideOr1~0 , bcd|A2|WideOr1~0, ex14, 1
+instance = comp, \bcd|A4|WideOr1~0 , bcd|A4|WideOr1~0, ex14, 1
+instance = comp, \bcd|A4|WideOr3~0 , bcd|A4|WideOr3~0, ex14, 1
+instance = comp, \bcd|A4|WideOr2~0 , bcd|A4|WideOr2~0, ex14, 1
+instance = comp, \bcd|A6|WideOr3~0 , bcd|A6|WideOr3~0, ex14, 1
+instance = comp, \bcd|A6|WideOr2~0 , bcd|A6|WideOr2~0, ex14, 1
+instance = comp, \bcd|A6|WideOr1~0 , bcd|A6|WideOr1~0, ex14, 1
+instance = comp, \bcd|A8|WideOr2~0 , bcd|A8|WideOr2~0, ex14, 1
+instance = comp, \bcd|A8|WideOr3~0 , bcd|A8|WideOr3~0, ex14, 1
+instance = comp, \bcd|A8|WideOr1~0 , bcd|A8|WideOr1~0, ex14, 1
+instance = comp, \bcd|A11|WideOr1~0 , bcd|A11|WideOr1~0, ex14, 1
+instance = comp, \bcd|A11|WideOr2~0 , bcd|A11|WideOr2~0, ex14, 1
+instance = comp, \bcd|A11|WideOr3~0 , bcd|A11|WideOr3~0, ex14, 1
+instance = comp, \bcd|A14|WideOr3~0 , bcd|A14|WideOr3~0, ex14, 1
+instance = comp, \bcd|A14|WideOr2~0 , bcd|A14|WideOr2~0, ex14, 1
+instance = comp, \bcd|A14|WideOr1~0 , bcd|A14|WideOr1~0, ex14, 1
+instance = comp, \bcd|A17|WideOr2~0 , bcd|A17|WideOr2~0, ex14, 1
+instance = comp, \bcd|A17|WideOr3~0 , bcd|A17|WideOr3~0, ex14, 1
+instance = comp, \bcd|A17|WideOr1~0 , bcd|A17|WideOr1~0, ex14, 1
+instance = comp, \bcd|A21|WideOr1~0 , bcd|A21|WideOr1~0, ex14, 1
+instance = comp, \bcd|A21|WideOr3~0 , bcd|A21|WideOr3~0, ex14, 1
+instance = comp, \bcd|A21|WideOr2~0 , bcd|A21|WideOr2~0, ex14, 1
+instance = comp, \bcd|A25|WideOr1~0 , bcd|A25|WideOr1~0, ex14, 1
+instance = comp, \bcd|A25|WideOr2~0 , bcd|A25|WideOr2~0, ex14, 1
+instance = comp, \bcd|A25|WideOr3~0 , bcd|A25|WideOr3~0, ex14, 1
+instance = comp, \bcd|A29|WideOr3~0 , bcd|A29|WideOr3~0, ex14, 1
+instance = comp, \bcd|A29|WideOr2~0 , bcd|A29|WideOr2~0, ex14, 1
+instance = comp, \bcd|A29|WideOr1~0 , bcd|A29|WideOr1~0, ex14, 1
+instance = comp, \h0|WideOr6~0 , h0|WideOr6~0, ex14, 1
+instance = comp, \h0|WideOr5~0 , h0|WideOr5~0, ex14, 1
+instance = comp, \h0|WideOr4~0 , h0|WideOr4~0, ex14, 1
+instance = comp, \h0|WideOr3~0 , h0|WideOr3~0, ex14, 1
+instance = comp, \h0|WideOr2~0 , h0|WideOr2~0, ex14, 1
+instance = comp, \h0|WideOr1~0 , h0|WideOr1~0, ex14, 1
+instance = comp, \h0|WideOr0~0 , h0|WideOr0~0, ex14, 1
+instance = comp, \bcd|A7|WideOr2~0 , bcd|A7|WideOr2~0, ex14, 1
+instance = comp, \bcd|A7|WideOr3~0 , bcd|A7|WideOr3~0, ex14, 1
+instance = comp, \bcd|A8|WideOr0~0 , bcd|A8|WideOr0~0, ex14, 1
+instance = comp, \bcd|A7|WideOr1~0 , bcd|A7|WideOr1~0, ex14, 1
+instance = comp, \bcd|A10|WideOr1~0 , bcd|A10|WideOr1~0, ex14, 1
+instance = comp, \bcd|A11|WideOr0~0 , bcd|A11|WideOr0~0, ex14, 1
+instance = comp, \bcd|A10|WideOr3~0 , bcd|A10|WideOr3~0, ex14, 1
+instance = comp, \bcd|A10|WideOr2~0 , bcd|A10|WideOr2~0, ex14, 1
+instance = comp, \bcd|A13|WideOr3~0 , bcd|A13|WideOr3~0, ex14, 1
+instance = comp, \bcd|A13|WideOr1~0 , bcd|A13|WideOr1~0, ex14, 1
+instance = comp, \bcd|A13|WideOr2~0 , bcd|A13|WideOr2~0, ex14, 1
+instance = comp, \bcd|A14|WideOr0~0 , bcd|A14|WideOr0~0, ex14, 1
+instance = comp, \bcd|A16|WideOr3~0 , bcd|A16|WideOr3~0, ex14, 1
+instance = comp, \bcd|A16|WideOr1~0 , bcd|A16|WideOr1~0, ex14, 1
+instance = comp, \bcd|A16|WideOr2~0 , bcd|A16|WideOr2~0, ex14, 1
+instance = comp, \bcd|A17|WideOr0~0 , bcd|A17|WideOr0~0, ex14, 1
+instance = comp, \bcd|A20|WideOr3~0 , bcd|A20|WideOr3~0, ex14, 1
+instance = comp, \bcd|A20|WideOr2~0 , bcd|A20|WideOr2~0, ex14, 1
+instance = comp, \bcd|A20|WideOr1~0 , bcd|A20|WideOr1~0, ex14, 1
+instance = comp, \bcd|A21|WideOr0~0 , bcd|A21|WideOr0~0, ex14, 1
+instance = comp, \bcd|A24|WideOr3~0 , bcd|A24|WideOr3~0, ex14, 1
+instance = comp, \bcd|A25|WideOr0~0 , bcd|A25|WideOr0~0, ex14, 1
+instance = comp, \bcd|A24|WideOr1~0 , bcd|A24|WideOr1~0, ex14, 1
+instance = comp, \bcd|A24|WideOr2~0 , bcd|A24|WideOr2~0, ex14, 1
+instance = comp, \bcd|A28|WideOr1~0 , bcd|A28|WideOr1~0, ex14, 1
+instance = comp, \bcd|A28|WideOr3~0 , bcd|A28|WideOr3~0, ex14, 1
+instance = comp, \bcd|A29|WideOr0~0 , bcd|A29|WideOr0~0, ex14, 1
+instance = comp, \bcd|A28|WideOr2~0 , bcd|A28|WideOr2~0, ex14, 1
+instance = comp, \h1|WideOr6~0 , h1|WideOr6~0, ex14, 1
+instance = comp, \h1|WideOr5~0 , h1|WideOr5~0, ex14, 1
+instance = comp, \h1|WideOr4~0 , h1|WideOr4~0, ex14, 1
+instance = comp, \h1|WideOr3~0 , h1|WideOr3~0, ex14, 1
+instance = comp, \h1|WideOr2~0 , h1|WideOr2~0, ex14, 1
+instance = comp, \h1|WideOr1~0 , h1|WideOr1~0, ex14, 1
+instance = comp, \h1|WideOr0~0 , h1|WideOr0~0, ex14, 1
+instance = comp, \bcd|A1|WideOr0~0 , bcd|A1|WideOr0~0, ex14, 1
+instance = comp, \bcd|A2|WideOr0~0 , bcd|A2|WideOr0~0, ex14, 1
+instance = comp, \bcd|A6|WideOr0~0 , bcd|A6|WideOr0~0, ex14, 1
+instance = comp, \bcd|A4|WideOr0~0 , bcd|A4|WideOr0~0, ex14, 1
+instance = comp, \bcd|A15|WideOr2~0 , bcd|A15|WideOr2~0, ex14, 1
+instance = comp, \bcd|A16|WideOr0~0 , bcd|A16|WideOr0~0, ex14, 1
+instance = comp, \bcd|A15|WideOr3~0 , bcd|A15|WideOr3~0, ex14, 1
+instance = comp, \bcd|A15|WideOr1~0 , bcd|A15|WideOr1~0, ex14, 1
+instance = comp, \bcd|A19|WideOr1~0 , bcd|A19|WideOr1~0, ex14, 1
+instance = comp, \bcd|A19|WideOr3~0 , bcd|A19|WideOr3~0, ex14, 1
+instance = comp, \bcd|A19|WideOr2~0 , bcd|A19|WideOr2~0, ex14, 1
+instance = comp, \bcd|A20|WideOr0~0 , bcd|A20|WideOr0~0, ex14, 1
+instance = comp, \bcd|A23|WideOr2~0 , bcd|A23|WideOr2~0, ex14, 1
+instance = comp, \bcd|A23|WideOr3~0 , bcd|A23|WideOr3~0, ex14, 1
+instance = comp, \bcd|A24|WideOr0~0 , bcd|A24|WideOr0~0, ex14, 1
+instance = comp, \bcd|A23|WideOr1~0 , bcd|A23|WideOr1~0, ex14, 1
+instance = comp, \bcd|A27|WideOr1~0 , bcd|A27|WideOr1~0, ex14, 1
+instance = comp, \bcd|A28|WideOr0~0 , bcd|A28|WideOr0~0, ex14, 1
+instance = comp, \bcd|A27|WideOr2~0 , bcd|A27|WideOr2~0, ex14, 1
+instance = comp, \bcd|A27|WideOr3~0 , bcd|A27|WideOr3~0, ex14, 1
+instance = comp, \h2|WideOr6~0 , h2|WideOr6~0, ex14, 1
+instance = comp, \h2|WideOr5~0 , h2|WideOr5~0, ex14, 1
+instance = comp, \h2|WideOr4~0 , h2|WideOr4~0, ex14, 1
+instance = comp, \h2|WideOr3~0 , h2|WideOr3~0, ex14, 1
+instance = comp, \h2|WideOr2~0 , h2|WideOr2~0, ex14, 1
+instance = comp, \h2|WideOr1~0 , h2|WideOr1~0, ex14, 1
+instance = comp, \h2|WideOr0~0 , h2|WideOr0~0, ex14, 1
+instance = comp, \bcd|A7|WideOr0~0 , bcd|A7|WideOr0~0, ex14, 1
+instance = comp, \bcd|A5|WideOr0~0 , bcd|A5|WideOr0~0, ex14, 1
+instance = comp, \bcd|A10|WideOr0~0 , bcd|A10|WideOr0~0, ex14, 1
+instance = comp, \bcd|A12|WideOr0~0 , bcd|A12|WideOr0~0, ex14, 1
+instance = comp, \bcd|A15|WideOr0~0 , bcd|A15|WideOr0~0, ex14, 1
+instance = comp, \bcd|A23|WideOr0~0 , bcd|A23|WideOr0~0, ex14, 1
+instance = comp, \bcd|A19|WideOr0~0 , bcd|A19|WideOr0~0, ex14, 1
+instance = comp, \bcd|A26|Decoder0~2 , bcd|A26|Decoder0~2, ex14, 1
+instance = comp, \bcd|A26|Decoder0~0 , bcd|A26|Decoder0~0, ex14, 1
+instance = comp, \bcd|A26|WideOr2 , bcd|A26|WideOr2, ex14, 1
+instance = comp, \bcd|A27|WideOr0~0 , bcd|A27|WideOr0~0, ex14, 1
+instance = comp, \bcd|A26|Decoder0~3 , bcd|A26|Decoder0~3, ex14, 1
+instance = comp, \bcd|A26|WideOr1 , bcd|A26|WideOr1, ex14, 1
+instance = comp, \bcd|A26|Decoder0~1 , bcd|A26|Decoder0~1, ex14, 1
+instance = comp, \bcd|A26|WideOr3~0 , bcd|A26|WideOr3~0, ex14, 1
+instance = comp, \h3|WideOr6~0 , h3|WideOr6~0, ex14, 1
+instance = comp, \h3|WideOr5~0 , h3|WideOr5~0, ex14, 1
+instance = comp, \h3|WideOr4~0 , h3|WideOr4~0, ex14, 1
+instance = comp, \h3|WideOr3~0 , h3|WideOr3~0, ex14, 1
+instance = comp, \h3|WideOr2~0 , h3|WideOr2~0, ex14, 1
+instance = comp, \h3|WideOr1~0 , h3|WideOr1~0, ex14, 1
+instance = comp, \h3|WideOr0~0 , h3|WideOr0~0, ex14, 1
+instance = comp, \bcd|A26|Decoder0~4 , bcd|A26|Decoder0~4, ex14, 1
+instance = comp, \bcd|A22|WideOr0~0 , bcd|A22|WideOr0~0, ex14, 1
+instance = comp, \h4|Decoder0~0 , h4|Decoder0~0, ex14, 1
+instance = comp, \bcd|A13|WideOr0~0 , bcd|A13|WideOr0~0, ex14, 1
+instance = comp, \h4|Decoder0~2 , h4|Decoder0~2, ex14, 1
+instance = comp, \bcd|A26|WideOr0 , bcd|A26|WideOr0, ex14, 1
+instance = comp, \h4|Decoder0~1 , h4|Decoder0~1, ex14, 1
+instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, ex14, 1
diff --git a/part_3/ex14/simulation/modelsim/ex10_run_msim_rtl_verilog.do b/part_3/ex14/simulation/modelsim/ex10_run_msim_rtl_verilog.do
new file mode 100755
index 0000000..281cccf
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/ex10_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+
diff --git a/part_3/ex14/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak b/part_3/ex14/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak
new file mode 100755
index 0000000..281cccf
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+
diff --git a/part_3/ex14/simulation/modelsim/modelsim.ini b/part_3/ex14/simulation/modelsim/modelsim.ini
new file mode 100755
index 0000000..3912feb
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/modelsim.ini
@@ -0,0 +1,324 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+work = rtl_work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
diff --git a/part_3/ex14/simulation/modelsim/msim_transcript b/part_3/ex14/simulation/modelsim/msim_transcript
new file mode 100755
index 0000000..cb744ab
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/msim_transcript
@@ -0,0 +1,20 @@
+# Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl 
+# do ex10_run_msim_rtl_verilog.do 
+# if {[file exists rtl_work]} {
+# 	vdel -lib rtl_work -all
+# }
+# vlib rtl_work
+# vmap work rtl_work
+# Copying C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
+# Modifying modelsim.ini
+# ** Warning: Copied C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
+#          Updated modelsim.ini.
+# 
+# vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+# -- Compiling module spi2dac
+# 
+# Top level modules:
+# 	spi2dac
+# 
+# Load canceled
diff --git a/part_3/ex14/simulation/modelsim/rtl_work/_info b/part_3/ex14/simulation/modelsim/rtl_work/_info
new file mode 100755
index 0000000..499bdd4
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/rtl_work/_info
@@ -0,0 +1,25 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex14/simulation/modelsim/rtl_work/_vmake b/part_3/ex14/simulation/modelsim/rtl_work/_vmake
new file mode 100755
index 0000000..2f7e729
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/rtl_work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.dat b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.dat
new file mode 100755
index 0000000..a728b27
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.dat
diff --git a/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.dbs b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.dbs
new file mode 100755
index 0000000..740ad04
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.dbs
diff --git a/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
new file mode 100755
index 0000000..e874ed3
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -0,0 +1,30 @@
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+    generic(
+        BUF             : vl_logic := Hi1;
+        GA_N            : vl_logic := Hi1;
+        SHDN_N          : vl_logic := Hi1;
+        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        data_in         : in     vl_logic_vector(9 downto 0);
+        load            : in     vl_logic;
+        dac_sdi         : out    vl_logic;
+        dac_cs          : out    vl_logic;
+        dac_sck         : out    vl_logic;
+        dac_ld          : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BUF : constant is 1;
+    attribute mti_svvh_generic_type of GA_N : constant is 1;
+    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+    attribute mti_svvh_generic_type of TC : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
diff --git a/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/verilog.prw b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/verilog.prw
new file mode 100755
index 0000000..ca1d7f3
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/verilog.prw
diff --git a/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/verilog.psm b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/verilog.psm
new file mode 100755
index 0000000..97c417f
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/rtl_work/spi2dac/verilog.psm
diff --git a/part_3/ex14/simulation/modelsim/vsim.wlf b/part_3/ex14/simulation/modelsim/vsim.wlf
new file mode 100755
index 0000000..54e1dca
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/vsim.wlf
diff --git a/part_3/ex14/verilog_files/ROM.qip b/part_3/ex14/verilog_files/ROM.qip
new file mode 100755
index 0000000..dc92785
--- /dev/null
+++ b/part_3/ex14/verilog_files/ROM.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ROM_bb.v"]
diff --git a/part_3/ex14/verilog_files/ROM.v b/part_3/ex14/verilog_files/ROM.v
new file mode 100755
index 0000000..296e57c
--- /dev/null
+++ b/part_3/ex14/verilog_files/ROM.v
@@ -0,0 +1,160 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ROM.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ROM (
+	address,
+	clock,
+	q);
+
+	input	[9:0]  address;
+	input	  clock;
+	output	[9:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [9:0] sub_wire0;
+	wire [9:0] q = sub_wire0[9:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({10{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "./rom_data/rom_data.mif",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 1024,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 10,
+		altsyncram_component.width_a = 10,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./rom_data/rom_data.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+// Retrieval info: PRIVATE: WidthData NUMERIC "10"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./rom_data/rom_data.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q_a 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_3/ex14/verilog_files/add3_ge5.v b/part_3/ex14/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..65a561d
--- /dev/null
+++ b/part_3/ex14/verilog_files/add3_ge5.v
@@ -0,0 +1,25 @@
+module add3_ge5(w,a);
+	output [3:0] a;
+	input [3:0] w;
+	
+	reg [3:0] a;
+	
+	always @ (w)
+		case(w)
+			4'b0000: a <= 4'b0000;
+			4'b0001: a <= 4'b0001;
+			4'b0010: a <= 4'b0010;
+			4'b0011: a <= 4'b0011;
+			4'b0100: a <= 4'b0100;
+			4'b0101: a <= 4'b1000;
+			4'b0110: a <= 4'b1001;
+			4'b0111: a <= 4'b1010;
+			4'b1000: a <= 4'b1011;
+			4'b1001: a <= 4'b1100;
+			4'b1010: a <= 4'b1101;
+			4'b1011: a <= 4'b1110;
+			4'b1100: a <= 4'b1111;
+			
+			default: a <= 4'b0000;
+		endcase
+endmodule
diff --git a/part_3/ex14/verilog_files/bin2bcd_16.v b/part_3/ex14/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..fdfb655
--- /dev/null
+++ b/part_3/ex14/verilog_files/bin2bcd_16.v
@@ -0,0 +1,97 @@
+//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+//            .... it uses a shift-and-add3 algorithm
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     18 Sept 2016
+//------------------------------
+//   For more explanation of how this work, see 
+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+	input [15:0]	B;		// binary input number
+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD
+	
+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+	wire [3:0]	w26,w27,w28,w29;
+	wire [3:0]	a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+	wire [3:0]	a26,a27,a28,a29;
+
+	// Instantiate a tree of add3-if-greater than or equal to 5 cells
+	//  ... input is w_n, and output is a_n
+	add3_ge5 A1 (w1,a1);
+	add3_ge5 A2 (w2,a2);
+	add3_ge5 A3 (w3,a3);
+	add3_ge5 A4 (w4,a4);
+	add3_ge5 A5 (w5,a5);
+	add3_ge5 A6 (w6,a6);
+	add3_ge5 A7 (w7,a7);
+	add3_ge5 A8 (w8,a8);
+	add3_ge5 A9 (w9,a9);
+	add3_ge5 A10 (w10,a10);
+	add3_ge5 A11 (w11,a11);
+	add3_ge5 A12 (w12,a12);
+	add3_ge5 A13 (w13,a13);
+	add3_ge5 A14 (w14,a14);
+	add3_ge5 A15 (w15,a15);
+	add3_ge5 A16 (w16,a16);
+	add3_ge5 A17 (w17,a17);
+	add3_ge5 A18 (w18,a18);
+	add3_ge5 A19 (w19,a19);
+	add3_ge5 A20 (w20,a20);
+	add3_ge5 A21 (w21,a21);
+	add3_ge5 A22 (w22,a22);
+	add3_ge5 A23 (w23,a23);
+	add3_ge5 A24 (w24,a24);
+	add3_ge5 A25 (w25,a25);
+	add3_ge5 A26 (w26,a26);
+	add3_ge5 A27 (w27,a27);
+	add3_ge5 A28 (w28,a28);
+	add3_ge5 A29 (w29,a29);
+		
+	// wire the tree of add3 modules together
+	assign  w1 = {B[14:11]};		// wn is the input port to module An
+	assign  w2 = {a1[2:0], B[10]};
+	assign  w3 = {1'b0, B[15], a1[3], a2[3]};
+	assign  w4 = {a2[2:0], B[9]};
+	assign  w5 = {a3[2:0], a4[3]};
+	assign  w6 = {a4[2:0], B[8]};
+	assign  w7 = {a5[2:0], a6[3]};
+	assign  w8 = {a6[2:0], B[7]};
+	assign  w9 = {1'b0, a3[3], a5[3], a7[3]};
+	assign  w10 = {a7[2:0], a8[3]};
+	assign  w11 = {a8[2:0], B[6]};
+	assign  w12 = {a9[2:0], a10[3]};
+	assign  w13 = {a10[2:0], a11[3]};
+	assign  w14 = {a11[2:0], B[5]};
+	assign  w15 = {a12[2:0], a13[3]};
+	assign  w16 = {a13[2:0], a14[3]};
+	assign  w17 = {a14[2:0], B[4]};
+	assign  w18 = {1'b0, a9[3], a12[3], a15[3]};
+	assign  w19 = {a15[2:0], a16[3]};
+	assign  w20 = {a16[2:0], a17[3]};
+	assign  w21 = {a17[2:0], B[3]};
+	assign  w22 = {a18[2:0], a19[3]};
+	assign  w23 = {a19[2:0], a20[3]};
+	assign  w24 = {a20[2:0], a21[3]};
+	assign  w25 = {a21[2:0], B[2]};
+	assign  w26 = {a22[2:0], a23[3]};
+	assign  w27 = {a23[2:0], a24[3]};
+	assign  w28 = {a24[2:0], a25[3]};
+	assign  w29 = {a25[2:0], B[1]};
+	
+	// connect up to four BCD digit outputs	
+	assign BCD_0 = {a29[2:0],B[0]};
+	assign BCD_1 = {a28[2:0],a29[3]};
+	assign BCD_2 = {a27[2:0],a28[3]};
+	assign BCD_3 = {a26[2:0],a27[3]};
+	assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};	
+endmodule
+
+	
+	
+
diff --git a/part_2/ex9_final/verilog_files/hex_to_7seg.v b/part_3/ex14/verilog_files/hex_to_7seg.v
index 82aa9a5..82aa9a5 100755
--- a/part_2/ex9_final/verilog_files/hex_to_7seg.v
+++ b/part_3/ex14/verilog_files/hex_to_7seg.v
diff --git a/part_3/ex14/verilog_files/pwm.v b/part_3/ex14/verilog_files/pwm.v
new file mode 100755
index 0000000..6a6e10c
--- /dev/null
+++ b/part_3/ex14/verilog_files/pwm.v
@@ -0,0 +1,25 @@
+module pwm(clk, data_in, load, pwm_out);
+
+	input clk;
+	input [9:0] data_in;
+	input load;
+	output pwm_out;
+	
+	reg[9:0] d;
+	reg [9:0] count;
+	reg pwm_out;
+	
+	always @ (posedge clk)
+		if(load == 1'b1) d <= data_in;
+		
+	initial count = 10'b0;
+	
+	always @ (posedge clk) begin
+		count <= count + 1'b1;
+		if(count > d)
+			pwm_out <= 1'b0;
+		else
+			pwm_out <= 1'b1;
+		end
+		
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex14/verilog_files/spi2dac.v b/part_3/ex14/verilog_files/spi2dac.v
new file mode 100755
index 0000000..586a231
--- /dev/null
+++ b/part_3/ex14/verilog_files/spi2dac.v
@@ -0,0 +1,128 @@
+//------------------------------
+// Module name: spi2dac
+// Function: SPI interface for MPC4911 DAC
+// Creator:  Peter Cheung
+// Version:  2.0
+// Date:     8 Nov 2016
+//------------------------------
+
+module spi2dac (sysclk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld);
+
+	input	sysclk;			// 50MHz system clock of DE1
+	input	[9:0]	data_in;	// input data to DAC
+	input	load;				// Pulse to load data to dac
+	output dac_sdi;		// SPI serial data out
+	output dac_cs;			// chip select - low when sending data to dac
+	output dac_sck;		// SPI clock, 16 cycles at half sysclk freq
+	output dac_ld;
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire			sysclk, load;
+	wire [9:0]	data_in;
+	
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg			dac_cs, dac_ld;
+	wire			dac_sck, dac_sdi;
+	
+	parameter	BUF=1'b1;		// 0:no buffer, 1:Vref buffered
+	parameter	GA_N=1'b1;		// 0:gain = 2x, 1:gain = 1x
+	parameter	SHDN_N=1'b1;	// 0:power down, 1:dac active
+	
+	wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N};  // wire to VDD or GND
+	
+	// --- internal 1MHz symmetical clock generator -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	
+	parameter	TC = 5'd24;  // Terminal count - change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... Initialise when FPGA is configured
+	end
+		
+	always @ (posedge sysclk)    
+	  if (ctr==0) begin
+		  ctr <= TC;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+	// ---- end internal 1MHz symmetical clock generator ----------
+
+	// ---- FSM to detect rising edge of load and falling edge of dac_cs
+	// .... sr_state set on posedge of load
+	// .... sr_state reset when dac_cs goes high at the end of DAC output cycle
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			dac_start;		 // set if a DAC write is detected
+	
+	initial begin
+		sr_state = IDLE;
+		dac_start = 1'b0;	// set while sending data to DAC
+		end
+	
+	always @ (posedge sysclk)  // state transition
+		case (sr_state)
+			IDLE:	if (load==1'b1) sr_state <= WAIT_CSB_FALL;
+			WAIT_CSB_FALL: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+			WAIT_CSB_HIGH: if (dac_cs==1'b1) sr_state <= IDLE;
+			default: sr_state <= IDLE;
+		endcase
+	
+	always @ (*)
+		case (sr_state)
+			IDLE: dac_start = 1'b0;
+			WAIT_CSB_FALL: dac_start = 1'b1;
+			WAIT_CSB_HIGH: dac_start = 1'b0;
+			default: dac_start = 1'b0;
+		endcase
+		
+	//------- End circuit to detect start and end of conversion	state machine
+
+	//------- spi controller FSM
+	// .... with 17 states (idle, and S1-S16 
+	// .... for the 16 cycles each sending 1-bit to dac)
+	reg [4:0] 	state;
+	
+	initial	begin	
+		state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; 
+		end
+		
+	always @(posedge clk_1MHz)  // FSM state transition
+		case (state)
+			5'd0:	if (dac_start == 1'b1)    // waiting to start
+						state <= state + 1'b1; 
+					else 
+						state <= 5'b0; 
+			5'd17: 	state <= 5'd0;  // go back to idle state
+			default: state <= state + 1'b1;	// default go to next state
+		endcase
+	
+	always @ (*)	begin			// FSM output
+		dac_cs = 1'b0;  dac_ld = 1'b1;
+		case (state)
+			5'd0: 	dac_cs = 1'b1;
+			5'd17: 	begin dac_cs = 1'b1; dac_ld = 1'b0; end
+			default: begin dac_cs = 1'b0;	dac_ld = 1'b1;	end
+			endcase
+		end //always
+	// --------- END of spi controller FSM
+	
+	// shift register for output data
+	reg [15:0] shift_reg;
+	initial	begin	
+		shift_reg = 16'b0; 
+		end
+
+	always @(posedge clk_1MHz)
+		if((dac_start==1'b1)&&(dac_cs==1'b1))		// parallel load data to shift reg
+			shift_reg <= {cmd,data_in,2'b00};
+		else 													// .. else start shifting
+			shift_reg <= {shift_reg[14:0],1'b0};
+	
+	// Assign outputs to drive SPI interface to DAC
+			assign dac_sck = !clk_1MHz&!dac_cs;
+			assign dac_sdi = shift_reg[15];
+endmodule
+\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/tick_50000.v.bak b/part_3/ex14/verilog_files/tick_5000.v
index 45c4166..a048386 100755
--- a/part_2/ex9_final/verilog_files/tick_50000.v.bak
+++ b/part_3/ex14/verilog_files/tick_5000.v
@@ -1,4 +1,4 @@
-module tick_50000(CLOCK_IN, CLK_OUT);
+module tick_5000(CLOCK_IN, CLK_OUT);
 
 	parameter NBIT = 16;
 	
@@ -11,7 +11,7 @@ module tick_50000(CLOCK_IN, CLK_OUT);
 	
 	initial 
 		begin
-			count = 16'd24999;
+			count = 16'd4999;
 			CLK_OUT = 1'b0;
 		end
 	
@@ -19,12 +19,13 @@ module tick_50000(CLOCK_IN, CLK_OUT);
 		begin
 			if(count == 16'b0)
 				begin
-					CLK_OUT <= ~CLK_OUT;
-					count <= 16'd24999;
+					CLK_OUT <= 1'b1;
+					count <= 16'd4999;
 				end
 			else
 				begin
 					count <= count - 1'b1;
+					CLK_OUT <= 1'b0;
 				end
 		end
 
diff --git a/part_2/ex9_partially_working/verilog_files/tick_50000.v b/part_3/ex14/verilog_files/tick_5000.v.bak
index 7ccc81b..97fcf8b 100755
--- a/part_2/ex9_partially_working/verilog_files/tick_50000.v
+++ b/part_3/ex14/verilog_files/tick_5000.v.bak
@@ -11,7 +11,7 @@ module tick_50000(CLOCK_IN, CLK_OUT);
 	
 	initial 
 		begin
-			count = 16'd49999;
+			count = 16'd4999;
 			CLK_OUT = 1'b0;
 		end
 	
diff --git a/part_3/ex15/.qsys_edit/filters.xml b/part_3/ex15/.qsys_edit/filters.xml
new file mode 100755
index 0000000..2c6ab93
--- /dev/null
+++ b/part_3/ex15/.qsys_edit/filters.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="16.0" />
diff --git a/part_3/ex15/.qsys_edit/preferences.xml b/part_3/ex15/.qsys_edit/preferences.xml
new file mode 100755
index 0000000..c5b7680
--- /dev/null
+++ b/part_3/ex15/.qsys_edit/preferences.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+  <columns>
+   <connections preferredWidth="47" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1100" height="800" x="0" y="0" />
+</preferences>
diff --git a/part_3/ex15/add_offset.v b/part_3/ex15/add_offset.v
new file mode 100755
index 0000000..02882fb
--- /dev/null
+++ b/part_3/ex15/add_offset.v
@@ -0,0 +1,14 @@
+module add_offset(keys, tick, address);
+
+	input [9:0] keys;
+	input tick;
+	output [9:0] address;
+	
+	reg [9:0] address;
+	
+	initial address = 10'b0;
+
+	always @ (posedge tick)
+		address = keys + address;
+
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex15/add_offset.v.bak b/part_3/ex15/add_offset.v.bak
new file mode 100755
index 0000000..fb7bf2f
--- /dev/null
+++ b/part_3/ex15/add_offset.v.bak
@@ -0,0 +1,16 @@
+module add_offset(keys, tick, address);
+
+	input [9:0] key;
+	input tick;
+	output [9:0] address;
+	
+	reg [9:0] address;
+	
+	initial address = 10'b0;
+
+	always @ (posedge tick)
+		address = key + address;
+
+
+
+endmodule
+\ No newline at end of file
diff --git a/part_2/ex9_partially_working/c5_pin_model_dump.txt b/part_3/ex15/c5_pin_model_dump.txt
index a895a64..a895a64 100755
--- a/part_2/ex9_partially_working/c5_pin_model_dump.txt
+++ b/part_3/ex15/c5_pin_model_dump.txt
diff --git a/part_3/ex15/const_mult.qip b/part_3/ex15/const_mult.qip
new file mode 100755
index 0000000..c806a73
--- /dev/null
+++ b/part_3/ex15/const_mult.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
+set_global_assignment -name IP_TOOL_VERSION "16.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "const_mult.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "const_mult_bb.v"]
diff --git a/part_3/ex15/const_mult.v b/part_3/ex15/const_mult.v
new file mode 100755
index 0000000..e4b9ece
--- /dev/null
+++ b/part_3/ex15/const_mult.v
@@ -0,0 +1,109 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: const_mult.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Intel and sold by Intel or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module const_mult (
+	dataa,
+	result);
+
+	input	[9:0]  dataa;
+	output	[23:0]  result;
+
+	wire [13:0] sub_wire0 = 14'h2710;
+	wire [23:0] sub_wire1;
+	wire [23:0] result = sub_wire1[23:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (sub_wire0),
+				.result (sub_wire1),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sclr (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 10,
+		lpm_mult_component.lpm_widthb = 14,
+		lpm_mult_component.lpm_widthp = 24;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "10000"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "10"
+// Retrieval info: PRIVATE: WidthB NUMERIC "14"
+// Retrieval info: PRIVATE: WidthP NUMERIC "24"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "14"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "24"
+// Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
+// Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]"
+// Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
+// Retrieval info: CONNECT: @datab 0 0 14 0 10000 0 0 14 0
+// Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_3/ex15/const_mult_bb.v b/part_3/ex15/const_mult_bb.v
new file mode 100755
index 0000000..3cc17fb
--- /dev/null
+++ b/part_3/ex15/const_mult_bb.v
@@ -0,0 +1,82 @@
+// megafunction wizard: %LPM_MULT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: const_mult.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Intel and sold by Intel or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module const_mult (
+	dataa,
+	result);
+
+	input	[9:0]  dataa;
+	output	[23:0]  result;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "10000"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "10"
+// Retrieval info: PRIVATE: WidthB NUMERIC "14"
+// Retrieval info: PRIVATE: WidthP NUMERIC "24"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "14"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "24"
+// Retrieval info: USED_PORT: dataa 0 0 10 0 INPUT NODEFVAL "dataa[9..0]"
+// Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]"
+// Retrieval info: CONNECT: @dataa 0 0 10 0 dataa 0 0 10 0
+// Retrieval info: CONNECT: @datab 0 0 14 0 10000 0 0 14 0
+// Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL const_mult_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_3/ex15/db/.cmp.kpt b/part_3/ex15/db/.cmp.kpt
new file mode 100755
index 0000000..df5967a
--- /dev/null
+++ b/part_3/ex15/db/.cmp.kpt
diff --git a/part_3/ex15/db/add_sub_89h.tdf b/part_3/ex15/db/add_sub_89h.tdf
new file mode 100755
index 0000000..f2e4477
--- /dev/null
+++ b/part_3/ex15/db/add_sub_89h.tdf
@@ -0,0 +1,32 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=22 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+
+--synthesis_resources = lut 22 
+SUBDESIGN add_sub_89h
+( 
+	dataa[21..0]	:	input;
+	datab[21..0]	:	input;
+	result[21..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_3/ex15/db/add_sub_d9h.tdf b/part_3/ex15/db/add_sub_d9h.tdf
new file mode 100755
index 0000000..856ca69
--- /dev/null
+++ b/part_3/ex15/db/add_sub_d9h.tdf
@@ -0,0 +1,32 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=18 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+
+--synthesis_resources = lut 18 
+SUBDESIGN add_sub_d9h
+( 
+	dataa[17..0]	:	input;
+	datab[17..0]	:	input;
+	result[17..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_3/ex15/db/altsyncram_6ng1.tdf b/part_3/ex15/db/altsyncram_6ng1.tdf
new file mode 100755
index 0000000..e896d11
--- /dev/null
+++ b/part_3/ex15/db/altsyncram_6ng1.tdf
@@ -0,0 +1,264 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rom_data/rom_data.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=10 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 1 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_6ng1
+( 
+	address_a[9..0]	:	input;
+	clock0	:	input;
+	q_a[9..0]	:	output;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "none",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK0_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			INIT_FILE = "./rom_data/rom_data.mif",
+			INIT_FILE_LAYOUT = "port_a",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			OPERATION_MODE = "rom",
+			PORT_A_ADDRESS_CLEAR = "none",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_OUT_CLEAR = "none",
+			PORT_A_DATA_OUT_CLOCK = "clock0",
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 1023,
+			PORT_A_LOGICAL_RAM_DEPTH = 1024,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[9..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[9..0].clk0 = clock0;
+	ram_block1a[9..0].portaaddr[] = ( address_a_wire[9..0]);
+	ram_block1a[9..0].portare = B"1111111111";
+	address_a_wire[] = address_a[];
+	q_a[] = ( ram_block1a[9..0].portadataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_3/ex15/db/ex10.(0).cnf.cdb b/part_3/ex15/db/ex10.(0).cnf.cdb
new file mode 100755
index 0000000..8a5b3bc
--- /dev/null
+++ b/part_3/ex15/db/ex10.(0).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(0).cnf.hdb b/part_3/ex15/db/ex10.(0).cnf.hdb
new file mode 100755
index 0000000..f6c48a8
--- /dev/null
+++ b/part_3/ex15/db/ex10.(0).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(1).cnf.cdb b/part_3/ex15/db/ex10.(1).cnf.cdb
new file mode 100755
index 0000000..aa9f443
--- /dev/null
+++ b/part_3/ex15/db/ex10.(1).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(1).cnf.hdb b/part_3/ex15/db/ex10.(1).cnf.hdb
new file mode 100755
index 0000000..a44bc81
--- /dev/null
+++ b/part_3/ex15/db/ex10.(1).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(10).cnf.cdb b/part_3/ex15/db/ex10.(10).cnf.cdb
new file mode 100755
index 0000000..d5d59d0
--- /dev/null
+++ b/part_3/ex15/db/ex10.(10).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(10).cnf.hdb b/part_3/ex15/db/ex10.(10).cnf.hdb
new file mode 100755
index 0000000..ed39106
--- /dev/null
+++ b/part_3/ex15/db/ex10.(10).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(11).cnf.cdb b/part_3/ex15/db/ex10.(11).cnf.cdb
new file mode 100755
index 0000000..5f3d168
--- /dev/null
+++ b/part_3/ex15/db/ex10.(11).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(11).cnf.hdb b/part_3/ex15/db/ex10.(11).cnf.hdb
new file mode 100755
index 0000000..dc019e6
--- /dev/null
+++ b/part_3/ex15/db/ex10.(11).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(12).cnf.cdb b/part_3/ex15/db/ex10.(12).cnf.cdb
new file mode 100755
index 0000000..4f01395
--- /dev/null
+++ b/part_3/ex15/db/ex10.(12).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(12).cnf.hdb b/part_3/ex15/db/ex10.(12).cnf.hdb
new file mode 100755
index 0000000..b5373f0
--- /dev/null
+++ b/part_3/ex15/db/ex10.(12).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(13).cnf.cdb b/part_3/ex15/db/ex10.(13).cnf.cdb
new file mode 100755
index 0000000..9d4de53
--- /dev/null
+++ b/part_3/ex15/db/ex10.(13).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(13).cnf.hdb b/part_3/ex15/db/ex10.(13).cnf.hdb
new file mode 100755
index 0000000..143f7a7
--- /dev/null
+++ b/part_3/ex15/db/ex10.(13).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(14).cnf.cdb b/part_3/ex15/db/ex10.(14).cnf.cdb
new file mode 100755
index 0000000..2fe35f2
--- /dev/null
+++ b/part_3/ex15/db/ex10.(14).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(14).cnf.hdb b/part_3/ex15/db/ex10.(14).cnf.hdb
new file mode 100755
index 0000000..640c12b
--- /dev/null
+++ b/part_3/ex15/db/ex10.(14).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(15).cnf.cdb b/part_3/ex15/db/ex10.(15).cnf.cdb
new file mode 100755
index 0000000..558b88b
--- /dev/null
+++ b/part_3/ex15/db/ex10.(15).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(15).cnf.hdb b/part_3/ex15/db/ex10.(15).cnf.hdb
new file mode 100755
index 0000000..adc1d50
--- /dev/null
+++ b/part_3/ex15/db/ex10.(15).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(16).cnf.cdb b/part_3/ex15/db/ex10.(16).cnf.cdb
new file mode 100755
index 0000000..172b5a8
--- /dev/null
+++ b/part_3/ex15/db/ex10.(16).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(16).cnf.hdb b/part_3/ex15/db/ex10.(16).cnf.hdb
new file mode 100755
index 0000000..c423c6d
--- /dev/null
+++ b/part_3/ex15/db/ex10.(16).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(17).cnf.cdb b/part_3/ex15/db/ex10.(17).cnf.cdb
new file mode 100755
index 0000000..68ddee8
--- /dev/null
+++ b/part_3/ex15/db/ex10.(17).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(17).cnf.hdb b/part_3/ex15/db/ex10.(17).cnf.hdb
new file mode 100755
index 0000000..d5ba41f
--- /dev/null
+++ b/part_3/ex15/db/ex10.(17).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(18).cnf.cdb b/part_3/ex15/db/ex10.(18).cnf.cdb
new file mode 100755
index 0000000..a9837d9
--- /dev/null
+++ b/part_3/ex15/db/ex10.(18).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(18).cnf.hdb b/part_3/ex15/db/ex10.(18).cnf.hdb
new file mode 100755
index 0000000..9b20321
--- /dev/null
+++ b/part_3/ex15/db/ex10.(18).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(19).cnf.cdb b/part_3/ex15/db/ex10.(19).cnf.cdb
new file mode 100755
index 0000000..16466e4
--- /dev/null
+++ b/part_3/ex15/db/ex10.(19).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(19).cnf.hdb b/part_3/ex15/db/ex10.(19).cnf.hdb
new file mode 100755
index 0000000..a1b437a
--- /dev/null
+++ b/part_3/ex15/db/ex10.(19).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(2).cnf.cdb b/part_3/ex15/db/ex10.(2).cnf.cdb
new file mode 100755
index 0000000..f787cbe
--- /dev/null
+++ b/part_3/ex15/db/ex10.(2).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(2).cnf.hdb b/part_3/ex15/db/ex10.(2).cnf.hdb
new file mode 100755
index 0000000..6b08eb0
--- /dev/null
+++ b/part_3/ex15/db/ex10.(2).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(20).cnf.cdb b/part_3/ex15/db/ex10.(20).cnf.cdb
new file mode 100755
index 0000000..2f84115
--- /dev/null
+++ b/part_3/ex15/db/ex10.(20).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(20).cnf.hdb b/part_3/ex15/db/ex10.(20).cnf.hdb
new file mode 100755
index 0000000..0d58d20
--- /dev/null
+++ b/part_3/ex15/db/ex10.(20).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(21).cnf.cdb b/part_3/ex15/db/ex10.(21).cnf.cdb
new file mode 100755
index 0000000..921f0c8
--- /dev/null
+++ b/part_3/ex15/db/ex10.(21).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(21).cnf.hdb b/part_3/ex15/db/ex10.(21).cnf.hdb
new file mode 100755
index 0000000..b7c5052
--- /dev/null
+++ b/part_3/ex15/db/ex10.(21).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(3).cnf.cdb b/part_3/ex15/db/ex10.(3).cnf.cdb
new file mode 100755
index 0000000..e93f1ef
--- /dev/null
+++ b/part_3/ex15/db/ex10.(3).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(3).cnf.hdb b/part_3/ex15/db/ex10.(3).cnf.hdb
new file mode 100755
index 0000000..d0d6c76
--- /dev/null
+++ b/part_3/ex15/db/ex10.(3).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(4).cnf.cdb b/part_3/ex15/db/ex10.(4).cnf.cdb
new file mode 100755
index 0000000..662025b
--- /dev/null
+++ b/part_3/ex15/db/ex10.(4).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(4).cnf.hdb b/part_3/ex15/db/ex10.(4).cnf.hdb
new file mode 100755
index 0000000..3b5bf14
--- /dev/null
+++ b/part_3/ex15/db/ex10.(4).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(5).cnf.cdb b/part_3/ex15/db/ex10.(5).cnf.cdb
new file mode 100755
index 0000000..5f6c204
--- /dev/null
+++ b/part_3/ex15/db/ex10.(5).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(5).cnf.hdb b/part_3/ex15/db/ex10.(5).cnf.hdb
new file mode 100755
index 0000000..b1b34cc
--- /dev/null
+++ b/part_3/ex15/db/ex10.(5).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(6).cnf.cdb b/part_3/ex15/db/ex10.(6).cnf.cdb
new file mode 100755
index 0000000..2199dea
--- /dev/null
+++ b/part_3/ex15/db/ex10.(6).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(6).cnf.hdb b/part_3/ex15/db/ex10.(6).cnf.hdb
new file mode 100755
index 0000000..529bca3
--- /dev/null
+++ b/part_3/ex15/db/ex10.(6).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(7).cnf.cdb b/part_3/ex15/db/ex10.(7).cnf.cdb
new file mode 100755
index 0000000..4548752
--- /dev/null
+++ b/part_3/ex15/db/ex10.(7).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(7).cnf.hdb b/part_3/ex15/db/ex10.(7).cnf.hdb
new file mode 100755
index 0000000..98fe16b
--- /dev/null
+++ b/part_3/ex15/db/ex10.(7).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(8).cnf.cdb b/part_3/ex15/db/ex10.(8).cnf.cdb
new file mode 100755
index 0000000..9d625c8
--- /dev/null
+++ b/part_3/ex15/db/ex10.(8).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(8).cnf.hdb b/part_3/ex15/db/ex10.(8).cnf.hdb
new file mode 100755
index 0000000..d7a9493
--- /dev/null
+++ b/part_3/ex15/db/ex10.(8).cnf.hdb
diff --git a/part_3/ex15/db/ex10.(9).cnf.cdb b/part_3/ex15/db/ex10.(9).cnf.cdb
new file mode 100755
index 0000000..a62dc15
--- /dev/null
+++ b/part_3/ex15/db/ex10.(9).cnf.cdb
diff --git a/part_3/ex15/db/ex10.(9).cnf.hdb b/part_3/ex15/db/ex10.(9).cnf.hdb
new file mode 100755
index 0000000..35b77b5
--- /dev/null
+++ b/part_3/ex15/db/ex10.(9).cnf.hdb
diff --git a/part_3/ex15/db/ex10.asm.qmsg b/part_3/ex15/db/ex10.asm.qmsg
new file mode 100755
index 0000000..b1cf1d2
--- /dev/null
+++ b/part_3/ex15/db/ex10.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480703536180 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480703536183 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 18:32:15 2016 " "Processing started: Fri Dec 02 18:32:15 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480703536183 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480703536183 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480703536183 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480703537088 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480703541923 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "898 " "Peak virtual memory: 898 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480703545331 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 18:32:25 2016 " "Processing ended: Fri Dec 02 18:32:25 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480703545331 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480703545331 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480703545331 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480703545331 ""}
diff --git a/part_3/ex15/db/ex10.asm.rdb b/part_3/ex15/db/ex10.asm.rdb
new file mode 100755
index 0000000..01155c6
--- /dev/null
+++ b/part_3/ex15/db/ex10.asm.rdb
diff --git a/part_3/ex15/db/ex10.cmp.ammdb b/part_3/ex15/db/ex10.cmp.ammdb
new file mode 100755
index 0000000..bdced90
--- /dev/null
+++ b/part_3/ex15/db/ex10.cmp.ammdb
diff --git a/part_3/ex15/db/ex10.cmp.bpm b/part_3/ex15/db/ex10.cmp.bpm
new file mode 100755
index 0000000..8f2a080
--- /dev/null
+++ b/part_3/ex15/db/ex10.cmp.bpm
diff --git a/part_3/ex15/db/ex10.cmp.cdb b/part_3/ex15/db/ex10.cmp.cdb
new file mode 100755
index 0000000..98a8f53
--- /dev/null
+++ b/part_3/ex15/db/ex10.cmp.cdb
diff --git a/part_3/ex15/db/ex10.cmp.hdb b/part_3/ex15/db/ex10.cmp.hdb
new file mode 100755
index 0000000..096dd5a
--- /dev/null
+++ b/part_3/ex15/db/ex10.cmp.hdb
diff --git a/part_3/ex15/db/ex10.cmp.idb b/part_3/ex15/db/ex10.cmp.idb
new file mode 100755
index 0000000..acc2ef1
--- /dev/null
+++ b/part_3/ex15/db/ex10.cmp.idb
diff --git a/part_2/ex9_partially_working/db/ex9.cmp.logdb b/part_3/ex15/db/ex10.cmp.logdb
index b4567d7..81a7d98 100755
--- a/part_2/ex9_partially_working/db/ex9.cmp.logdb
+++ b/part_3/ex15/db/ex10.cmp.logdb
@@ -28,12 +28,18 @@ IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for
 IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
 IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
 IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
-IO_RULES_MATRIX,Total Pass,57;0;57;0;0;57;57;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Pass,45;0;45;0;0;45;45;0;45;45;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
 IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;57;0;57;57;0;0;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57,
+IO_RULES_MATRIX,Total Inapplicable,0;45;0;45;45;0;0;45;0;0;45;45;45;45;45;45;45;45;45;45;45;45;45;45;45;45;45;45,
 IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_LD,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PWM_OUT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
@@ -69,26 +75,8 @@ IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pa
 IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDO,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_SUMMARY,Total I/O Rules,28,
 IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
 IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
diff --git a/part_3/ex15/db/ex10.cmp.rdb b/part_3/ex15/db/ex10.cmp.rdb
new file mode 100755
index 0000000..414b8a6
--- /dev/null
+++ b/part_3/ex15/db/ex10.cmp.rdb
diff --git a/part_3/ex15/db/ex10.cmp_merge.kpt b/part_3/ex15/db/ex10.cmp_merge.kpt
new file mode 100755
index 0000000..f13b219
--- /dev/null
+++ b/part_3/ex15/db/ex10.cmp_merge.kpt
diff --git a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_3/ex15/db/ex10.cyclonev_io_sim_cache.ff_0c_fast.hsd
index da61997..da61997 100755
--- a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.ff_0c_fast.hsd
+++ b/part_3/ex15/db/ex10.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_3/ex15/db/ex10.cyclonev_io_sim_cache.ff_85c_fast.hsd
index 3a7a497..3a7a497 100755
--- a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.ff_85c_fast.hsd
+++ b/part_3/ex15/db/ex10.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_3/ex15/db/ex10.cyclonev_io_sim_cache.tt_0c_slow.hsd
index aa473fa..aa473fa 100755
--- a/part_2/ex9_partially_working/db/ex9.cyclonev_io_sim_cache.tt_0c_slow.hsd
+++ b/part_3/ex15/db/ex10.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_3/ex15/db/ex10.cyclonev_io_sim_cache.tt_85c_slow.hsd
index acc52a8..acc52a8 100755
--- a/part_2/ex9_final/db/ex9.cyclonev_io_sim_cache.tt_85c_slow.hsd
+++ b/part_3/ex15/db/ex10.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_2/ex9_partially_working/db/ex9.db_info b/part_3/ex15/db/ex10.db_info
index 70adca2..75e945b 100755
--- a/part_2/ex9_partially_working/db/ex9.db_info
+++ b/part_3/ex15/db/ex10.db_info
@@ -1,3 +1,3 @@
 Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 Version_Index = 402707200
-Creation_Time = Fri Nov 25 10:28:00 2016
+Creation_Time = Fri Dec 02 17:48:58 2016
diff --git a/part_3/ex15/db/ex10.eda.qmsg b/part_3/ex15/db/ex10.eda.qmsg
new file mode 100755
index 0000000..8f6e1b7
--- /dev/null
+++ b/part_3/ex15/db/ex10.eda.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480703559507 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480703559510 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 18:32:39 2016 " "Processing started: Fri Dec 02 18:32:39 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480703559510 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480703559510 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480703559510 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1480703560554 ""}
+{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1480703560593 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ex10.vo /Desktop/ex15/simulation/modelsim/ simulation " "Generated file ex10.vo in folder \"/Desktop/ex15/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1480703561032 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "816 " "Peak virtual memory: 816 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480703561193 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 18:32:41 2016 " "Processing ended: Fri Dec 02 18:32:41 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480703561193 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480703561193 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480703561193 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1480703561193 ""}
diff --git a/part_3/ex15/db/ex10.fit.qmsg b/part_3/ex15/db/ex10.fit.qmsg
new file mode 100755
index 0000000..aec2be7
--- /dev/null
+++ b/part_3/ex15/db/ex10.fit.qmsg
@@ -0,0 +1,46 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480703485218 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480703485220 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex10 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex10\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480703485517 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480703485577 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480703485577 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480703485995 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480703486249 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480703486267 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480703496223 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 59 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 59 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480703496316 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480703496316 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480703496317 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480703496321 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480703496322 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480703496323 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480703496325 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480703496326 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480703496326 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex10.sdc " "Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480703497301 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480703497302 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480703497306 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480703497307 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480703497307 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480703497326 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480703497326 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480703497326 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[4\] " "Node \"SW\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[5\] " "Node \"SW\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[6\] " "Node \"SW\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[7\] " "Node \"SW\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[8\] " "Node \"SW\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480703497369 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480703497369 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480703497385 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480703502317 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480703502571 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480703503259 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480703504016 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480703505079 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480703505083 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480703506588 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X67_Y0 X77_Y10 " "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10" {  } { { "loc" "" { Generic "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/" { { 1 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10"} { { 12 { 0 ""} 67 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480703511499 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480703511499 ""}
+{ "Info" "IVPR20K_VPR_STATUS_ROUTER_HOLD_BACKOFF_ENGAGED" "" "Design requires adding a large amount of routing delay for some signals to meet hold time requirements, and there is an excessive demand for the available routing resources. The Fitter is reducing the routing delays of some signals to help the routing algorithm converge, but doing so may cause hold time failures. For more information, refer to the \"Estimated Delay Added for Hold Timing\" section in the Fitter report." {  } {  } 0 188005 "Design requires adding a large amount of routing delay for some signals to meet hold time requirements, and there is an excessive demand for the available routing resources. The Fitter is reducing the routing delays of some signals to help the routing algorithm converge, but doing so may cause hold time failures. For more information, refer to the \"Estimated Delay Added for Hold Timing\" section in the Fitter report." 0 0 "Fitter" 0 -1 1480703517687 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480703522437 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480703522437 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:12 " "Fitter routing operations ending: elapsed time is 00:00:12" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480703522442 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480703524213 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480703524251 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480703524927 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480703524928 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480703525466 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480703528154 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480703528398 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Desktop/ex15/output_files/ex10.fit.smsg " "Generated suppressed messages file /Desktop/ex15/output_files/ex10.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480703528526 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 41 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2755 " "Peak virtual memory: 2755 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480703531139 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 18:32:11 2016 " "Processing ended: Fri Dec 02 18:32:11 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480703531139 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:47 " "Elapsed time: 00:00:47" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480703531139 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:11 " "Total CPU time (on all processors): 00:01:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480703531139 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480703531139 ""}
diff --git a/part_3/ex15/db/ex10.hier_info b/part_3/ex15/db/ex10.hier_info
new file mode 100755
index 0000000..08a8e80
--- /dev/null
+++ b/part_3/ex15/db/ex10.hier_info
@@ -0,0 +1,1978 @@
+|ex15
+CLOCK_50 => CLOCK_50.IN5
+DAC_CS <= spi2dac:dac.port4
+DAC_SDI <= spi2dac:dac.port3
+DAC_LD <= spi2dac:dac.port6
+DAC_SCK <= spi2dac:dac.port5
+ADC_SDI <= spi2adc:SPI_ADC.sdata_to_adc
+ADC_SCK <= spi2adc:SPI_ADC.adc_sck
+ADC_CS <= spi2adc:SPI_ADC.adc_cs
+ADC_SDO => ADC_SDO.IN1
+PWM_OUT <= pwm:p.port3
+HEX0[0] <= hex_to_7seg:h0.port0
+HEX0[1] <= hex_to_7seg:h0.port0
+HEX0[2] <= hex_to_7seg:h0.port0
+HEX0[3] <= hex_to_7seg:h0.port0
+HEX0[4] <= hex_to_7seg:h0.port0
+HEX0[5] <= hex_to_7seg:h0.port0
+HEX0[6] <= hex_to_7seg:h0.port0
+HEX1[0] <= hex_to_7seg:h1.port0
+HEX1[1] <= hex_to_7seg:h1.port0
+HEX1[2] <= hex_to_7seg:h1.port0
+HEX1[3] <= hex_to_7seg:h1.port0
+HEX1[4] <= hex_to_7seg:h1.port0
+HEX1[5] <= hex_to_7seg:h1.port0
+HEX1[6] <= hex_to_7seg:h1.port0
+HEX2[0] <= hex_to_7seg:h2.port0
+HEX2[1] <= hex_to_7seg:h2.port0
+HEX2[2] <= hex_to_7seg:h2.port0
+HEX2[3] <= hex_to_7seg:h2.port0
+HEX2[4] <= hex_to_7seg:h2.port0
+HEX2[5] <= hex_to_7seg:h2.port0
+HEX2[6] <= hex_to_7seg:h2.port0
+HEX3[0] <= hex_to_7seg:h3.port0
+HEX3[1] <= hex_to_7seg:h3.port0
+HEX3[2] <= hex_to_7seg:h3.port0
+HEX3[3] <= hex_to_7seg:h3.port0
+HEX3[4] <= hex_to_7seg:h3.port0
+HEX3[5] <= hex_to_7seg:h3.port0
+HEX3[6] <= hex_to_7seg:h3.port0
+HEX4[0] <= hex_to_7seg:h4.port0
+HEX4[1] <= hex_to_7seg:h4.port0
+HEX4[2] <= hex_to_7seg:h4.port0
+HEX4[3] <= hex_to_7seg:h4.port0
+HEX4[4] <= hex_to_7seg:h4.port0
+HEX4[5] <= hex_to_7seg:h4.port0
+HEX4[6] <= hex_to_7seg:h4.port0
+
+
+|ex15|tick_5000:tick
+CLOCK_IN => count[0].CLK
+CLOCK_IN => count[1].CLK
+CLOCK_IN => count[2].CLK
+CLOCK_IN => count[3].CLK
+CLOCK_IN => count[4].CLK
+CLOCK_IN => count[5].CLK
+CLOCK_IN => count[6].CLK
+CLOCK_IN => count[7].CLK
+CLOCK_IN => count[8].CLK
+CLOCK_IN => count[9].CLK
+CLOCK_IN => count[10].CLK
+CLOCK_IN => count[11].CLK
+CLOCK_IN => count[12].CLK
+CLOCK_IN => count[13].CLK
+CLOCK_IN => count[14].CLK
+CLOCK_IN => count[15].CLK
+CLOCK_IN => CLK_OUT~reg0.CLK
+CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|spi2adc:SPI_ADC
+sysclk => adc_start.CLK
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~1.DATAIN
+start => Selector1.IN1
+start => adc_start.OUTPUTSELECT
+start => Selector0.IN1
+channel => Selector6.IN6
+data_from_adc[0] <= data_from_adc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[1] <= data_from_adc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[2] <= data_from_adc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[3] <= data_from_adc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[4] <= data_from_adc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[5] <= data_from_adc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[6] <= data_from_adc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[7] <= data_from_adc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[8] <= data_from_adc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[9] <= data_from_adc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+sdata_to_adc <= adc_din.DB_MAX_OUTPUT_PORT_TYPE
+adc_cs <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+adc_sck <= adc_sck.DB_MAX_OUTPUT_PORT_TYPE
+sdata_from_adc => shift_reg[0].DATAIN
+
+
+|ex15|add_offset:fin_address
+keys[0] => Add0.IN10
+keys[1] => Add0.IN9
+keys[2] => Add0.IN8
+keys[3] => Add0.IN7
+keys[4] => Add0.IN6
+keys[5] => Add0.IN5
+keys[6] => Add0.IN4
+keys[7] => Add0.IN3
+keys[8] => Add0.IN2
+keys[9] => Add0.IN1
+tick => address[0]~reg0.CLK
+tick => address[1]~reg0.CLK
+tick => address[2]~reg0.CLK
+tick => address[3]~reg0.CLK
+tick => address[4]~reg0.CLK
+tick => address[5]~reg0.CLK
+tick => address[6]~reg0.CLK
+tick => address[7]~reg0.CLK
+tick => address[8]~reg0.CLK
+tick => address[9]~reg0.CLK
+address[0] <= address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[1] <= address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[2] <= address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[3] <= address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[4] <= address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[5] <= address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[6] <= address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[7] <= address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[8] <= address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+address[9] <= address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|ROM:rom
+address[0] => address[0].IN1
+address[1] => address[1].IN1
+address[2] => address[2].IN1
+address[3] => address[3].IN1
+address[4] => address[4].IN1
+address[5] => address[5].IN1
+address[6] => address[6].IN1
+address[7] => address[7].IN1
+address[8] => address[8].IN1
+address[9] => address[9].IN1
+clock => clock.IN1
+q[0] <= altsyncram:altsyncram_component.q_a
+q[1] <= altsyncram:altsyncram_component.q_a
+q[2] <= altsyncram:altsyncram_component.q_a
+q[3] <= altsyncram:altsyncram_component.q_a
+q[4] <= altsyncram:altsyncram_component.q_a
+q[5] <= altsyncram:altsyncram_component.q_a
+q[6] <= altsyncram:altsyncram_component.q_a
+q[7] <= altsyncram:altsyncram_component.q_a
+q[8] <= altsyncram:altsyncram_component.q_a
+q[9] <= altsyncram:altsyncram_component.q_a
+
+
+|ex15|ROM:rom|altsyncram:altsyncram_component
+wren_a => ~NO_FANOUT~
+rden_a => ~NO_FANOUT~
+wren_b => ~NO_FANOUT~
+rden_b => ~NO_FANOUT~
+data_a[0] => ~NO_FANOUT~
+data_a[1] => ~NO_FANOUT~
+data_a[2] => ~NO_FANOUT~
+data_a[3] => ~NO_FANOUT~
+data_a[4] => ~NO_FANOUT~
+data_a[5] => ~NO_FANOUT~
+data_a[6] => ~NO_FANOUT~
+data_a[7] => ~NO_FANOUT~
+data_a[8] => ~NO_FANOUT~
+data_a[9] => ~NO_FANOUT~
+data_b[0] => ~NO_FANOUT~
+address_a[0] => altsyncram_6ng1:auto_generated.address_a[0]
+address_a[1] => altsyncram_6ng1:auto_generated.address_a[1]
+address_a[2] => altsyncram_6ng1:auto_generated.address_a[2]
+address_a[3] => altsyncram_6ng1:auto_generated.address_a[3]
+address_a[4] => altsyncram_6ng1:auto_generated.address_a[4]
+address_a[5] => altsyncram_6ng1:auto_generated.address_a[5]
+address_a[6] => altsyncram_6ng1:auto_generated.address_a[6]
+address_a[7] => altsyncram_6ng1:auto_generated.address_a[7]
+address_a[8] => altsyncram_6ng1:auto_generated.address_a[8]
+address_a[9] => altsyncram_6ng1:auto_generated.address_a[9]
+address_b[0] => ~NO_FANOUT~
+addressstall_a => ~NO_FANOUT~
+addressstall_b => ~NO_FANOUT~
+clock0 => altsyncram_6ng1:auto_generated.clock0
+clock1 => ~NO_FANOUT~
+clocken0 => ~NO_FANOUT~
+clocken1 => ~NO_FANOUT~
+clocken2 => ~NO_FANOUT~
+clocken3 => ~NO_FANOUT~
+aclr0 => ~NO_FANOUT~
+aclr1 => ~NO_FANOUT~
+byteena_a[0] => ~NO_FANOUT~
+byteena_b[0] => ~NO_FANOUT~
+q_a[0] <= altsyncram_6ng1:auto_generated.q_a[0]
+q_a[1] <= altsyncram_6ng1:auto_generated.q_a[1]
+q_a[2] <= altsyncram_6ng1:auto_generated.q_a[2]
+q_a[3] <= altsyncram_6ng1:auto_generated.q_a[3]
+q_a[4] <= altsyncram_6ng1:auto_generated.q_a[4]
+q_a[5] <= altsyncram_6ng1:auto_generated.q_a[5]
+q_a[6] <= altsyncram_6ng1:auto_generated.q_a[6]
+q_a[7] <= altsyncram_6ng1:auto_generated.q_a[7]
+q_a[8] <= altsyncram_6ng1:auto_generated.q_a[8]
+q_a[9] <= altsyncram_6ng1:auto_generated.q_a[9]
+q_b[0] <= <GND>
+eccstatus[0] <= <GND>
+eccstatus[1] <= <GND>
+eccstatus[2] <= <GND>
+
+
+|ex15|ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated
+address_a[0] => ram_block1a0.PORTAADDR
+address_a[0] => ram_block1a1.PORTAADDR
+address_a[0] => ram_block1a2.PORTAADDR
+address_a[0] => ram_block1a3.PORTAADDR
+address_a[0] => ram_block1a4.PORTAADDR
+address_a[0] => ram_block1a5.PORTAADDR
+address_a[0] => ram_block1a6.PORTAADDR
+address_a[0] => ram_block1a7.PORTAADDR
+address_a[0] => ram_block1a8.PORTAADDR
+address_a[0] => ram_block1a9.PORTAADDR
+address_a[1] => ram_block1a0.PORTAADDR1
+address_a[1] => ram_block1a1.PORTAADDR1
+address_a[1] => ram_block1a2.PORTAADDR1
+address_a[1] => ram_block1a3.PORTAADDR1
+address_a[1] => ram_block1a4.PORTAADDR1
+address_a[1] => ram_block1a5.PORTAADDR1
+address_a[1] => ram_block1a6.PORTAADDR1
+address_a[1] => ram_block1a7.PORTAADDR1
+address_a[1] => ram_block1a8.PORTAADDR1
+address_a[1] => ram_block1a9.PORTAADDR1
+address_a[2] => ram_block1a0.PORTAADDR2
+address_a[2] => ram_block1a1.PORTAADDR2
+address_a[2] => ram_block1a2.PORTAADDR2
+address_a[2] => ram_block1a3.PORTAADDR2
+address_a[2] => ram_block1a4.PORTAADDR2
+address_a[2] => ram_block1a5.PORTAADDR2
+address_a[2] => ram_block1a6.PORTAADDR2
+address_a[2] => ram_block1a7.PORTAADDR2
+address_a[2] => ram_block1a8.PORTAADDR2
+address_a[2] => ram_block1a9.PORTAADDR2
+address_a[3] => ram_block1a0.PORTAADDR3
+address_a[3] => ram_block1a1.PORTAADDR3
+address_a[3] => ram_block1a2.PORTAADDR3
+address_a[3] => ram_block1a3.PORTAADDR3
+address_a[3] => ram_block1a4.PORTAADDR3
+address_a[3] => ram_block1a5.PORTAADDR3
+address_a[3] => ram_block1a6.PORTAADDR3
+address_a[3] => ram_block1a7.PORTAADDR3
+address_a[3] => ram_block1a8.PORTAADDR3
+address_a[3] => ram_block1a9.PORTAADDR3
+address_a[4] => ram_block1a0.PORTAADDR4
+address_a[4] => ram_block1a1.PORTAADDR4
+address_a[4] => ram_block1a2.PORTAADDR4
+address_a[4] => ram_block1a3.PORTAADDR4
+address_a[4] => ram_block1a4.PORTAADDR4
+address_a[4] => ram_block1a5.PORTAADDR4
+address_a[4] => ram_block1a6.PORTAADDR4
+address_a[4] => ram_block1a7.PORTAADDR4
+address_a[4] => ram_block1a8.PORTAADDR4
+address_a[4] => ram_block1a9.PORTAADDR4
+address_a[5] => ram_block1a0.PORTAADDR5
+address_a[5] => ram_block1a1.PORTAADDR5
+address_a[5] => ram_block1a2.PORTAADDR5
+address_a[5] => ram_block1a3.PORTAADDR5
+address_a[5] => ram_block1a4.PORTAADDR5
+address_a[5] => ram_block1a5.PORTAADDR5
+address_a[5] => ram_block1a6.PORTAADDR5
+address_a[5] => ram_block1a7.PORTAADDR5
+address_a[5] => ram_block1a8.PORTAADDR5
+address_a[5] => ram_block1a9.PORTAADDR5
+address_a[6] => ram_block1a0.PORTAADDR6
+address_a[6] => ram_block1a1.PORTAADDR6
+address_a[6] => ram_block1a2.PORTAADDR6
+address_a[6] => ram_block1a3.PORTAADDR6
+address_a[6] => ram_block1a4.PORTAADDR6
+address_a[6] => ram_block1a5.PORTAADDR6
+address_a[6] => ram_block1a6.PORTAADDR6
+address_a[6] => ram_block1a7.PORTAADDR6
+address_a[6] => ram_block1a8.PORTAADDR6
+address_a[6] => ram_block1a9.PORTAADDR6
+address_a[7] => ram_block1a0.PORTAADDR7
+address_a[7] => ram_block1a1.PORTAADDR7
+address_a[7] => ram_block1a2.PORTAADDR7
+address_a[7] => ram_block1a3.PORTAADDR7
+address_a[7] => ram_block1a4.PORTAADDR7
+address_a[7] => ram_block1a5.PORTAADDR7
+address_a[7] => ram_block1a6.PORTAADDR7
+address_a[7] => ram_block1a7.PORTAADDR7
+address_a[7] => ram_block1a8.PORTAADDR7
+address_a[7] => ram_block1a9.PORTAADDR7
+address_a[8] => ram_block1a0.PORTAADDR8
+address_a[8] => ram_block1a1.PORTAADDR8
+address_a[8] => ram_block1a2.PORTAADDR8
+address_a[8] => ram_block1a3.PORTAADDR8
+address_a[8] => ram_block1a4.PORTAADDR8
+address_a[8] => ram_block1a5.PORTAADDR8
+address_a[8] => ram_block1a6.PORTAADDR8
+address_a[8] => ram_block1a7.PORTAADDR8
+address_a[8] => ram_block1a8.PORTAADDR8
+address_a[8] => ram_block1a9.PORTAADDR8
+address_a[9] => ram_block1a0.PORTAADDR9
+address_a[9] => ram_block1a1.PORTAADDR9
+address_a[9] => ram_block1a2.PORTAADDR9
+address_a[9] => ram_block1a3.PORTAADDR9
+address_a[9] => ram_block1a4.PORTAADDR9
+address_a[9] => ram_block1a5.PORTAADDR9
+address_a[9] => ram_block1a6.PORTAADDR9
+address_a[9] => ram_block1a7.PORTAADDR9
+address_a[9] => ram_block1a8.PORTAADDR9
+address_a[9] => ram_block1a9.PORTAADDR9
+clock0 => ram_block1a0.CLK0
+clock0 => ram_block1a1.CLK0
+clock0 => ram_block1a2.CLK0
+clock0 => ram_block1a3.CLK0
+clock0 => ram_block1a4.CLK0
+clock0 => ram_block1a5.CLK0
+clock0 => ram_block1a6.CLK0
+clock0 => ram_block1a7.CLK0
+clock0 => ram_block1a8.CLK0
+clock0 => ram_block1a9.CLK0
+q_a[0] <= ram_block1a0.PORTADATAOUT
+q_a[1] <= ram_block1a1.PORTADATAOUT
+q_a[2] <= ram_block1a2.PORTADATAOUT
+q_a[3] <= ram_block1a3.PORTADATAOUT
+q_a[4] <= ram_block1a4.PORTADATAOUT
+q_a[5] <= ram_block1a5.PORTADATAOUT
+q_a[6] <= ram_block1a6.PORTADATAOUT
+q_a[7] <= ram_block1a7.PORTADATAOUT
+q_a[8] <= ram_block1a8.PORTADATAOUT
+q_a[9] <= ram_block1a9.PORTADATAOUT
+
+
+|ex15|spi2dac:dac
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~4.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => sr_state.OUTPUTSELECT
+load => sr_state.OUTPUTSELECT
+load => sr_state.OUTPUTSELECT
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= WideNor0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= Equal2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|pwm:p
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|const_mult:mult
+dataa[0] => dataa[0].IN1
+dataa[1] => dataa[1].IN1
+dataa[2] => dataa[2].IN1
+dataa[3] => dataa[3].IN1
+dataa[4] => dataa[4].IN1
+dataa[5] => dataa[5].IN1
+dataa[6] => dataa[6].IN1
+dataa[7] => dataa[7].IN1
+dataa[8] => dataa[8].IN1
+dataa[9] => dataa[9].IN1
+result[0] <= lpm_mult:lpm_mult_component.result
+result[1] <= lpm_mult:lpm_mult_component.result
+result[2] <= lpm_mult:lpm_mult_component.result
+result[3] <= lpm_mult:lpm_mult_component.result
+result[4] <= lpm_mult:lpm_mult_component.result
+result[5] <= lpm_mult:lpm_mult_component.result
+result[6] <= lpm_mult:lpm_mult_component.result
+result[7] <= lpm_mult:lpm_mult_component.result
+result[8] <= lpm_mult:lpm_mult_component.result
+result[9] <= lpm_mult:lpm_mult_component.result
+result[10] <= lpm_mult:lpm_mult_component.result
+result[11] <= lpm_mult:lpm_mult_component.result
+result[12] <= lpm_mult:lpm_mult_component.result
+result[13] <= lpm_mult:lpm_mult_component.result
+result[14] <= lpm_mult:lpm_mult_component.result
+result[15] <= lpm_mult:lpm_mult_component.result
+result[16] <= lpm_mult:lpm_mult_component.result
+result[17] <= lpm_mult:lpm_mult_component.result
+result[18] <= lpm_mult:lpm_mult_component.result
+result[19] <= lpm_mult:lpm_mult_component.result
+result[20] <= lpm_mult:lpm_mult_component.result
+result[21] <= lpm_mult:lpm_mult_component.result
+result[22] <= lpm_mult:lpm_mult_component.result
+result[23] <= lpm_mult:lpm_mult_component.result
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component
+dataa[0] => multcore:mult_core.dataa[0]
+dataa[1] => multcore:mult_core.dataa[1]
+dataa[2] => multcore:mult_core.dataa[2]
+dataa[3] => multcore:mult_core.dataa[3]
+dataa[4] => multcore:mult_core.dataa[4]
+dataa[5] => multcore:mult_core.dataa[5]
+dataa[6] => multcore:mult_core.dataa[6]
+dataa[7] => multcore:mult_core.dataa[7]
+dataa[8] => multcore:mult_core.dataa[8]
+dataa[9] => multcore:mult_core.dataa[9]
+datab[0] => multcore:mult_core.datab[0]
+datab[1] => multcore:mult_core.datab[1]
+datab[2] => multcore:mult_core.datab[2]
+datab[3] => multcore:mult_core.datab[3]
+datab[4] => multcore:mult_core.datab[4]
+datab[5] => multcore:mult_core.datab[5]
+datab[6] => multcore:mult_core.datab[6]
+datab[7] => multcore:mult_core.datab[7]
+datab[8] => multcore:mult_core.datab[8]
+datab[9] => multcore:mult_core.datab[9]
+datab[10] => multcore:mult_core.datab[10]
+datab[11] => multcore:mult_core.datab[11]
+datab[12] => multcore:mult_core.datab[12]
+datab[13] => multcore:mult_core.datab[13]
+sum[0] => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+sclr => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= altshift:external_latency_ffs.result[0]
+result[1] <= altshift:external_latency_ffs.result[1]
+result[2] <= altshift:external_latency_ffs.result[2]
+result[3] <= altshift:external_latency_ffs.result[3]
+result[4] <= altshift:external_latency_ffs.result[4]
+result[5] <= altshift:external_latency_ffs.result[5]
+result[6] <= altshift:external_latency_ffs.result[6]
+result[7] <= altshift:external_latency_ffs.result[7]
+result[8] <= altshift:external_latency_ffs.result[8]
+result[9] <= altshift:external_latency_ffs.result[9]
+result[10] <= altshift:external_latency_ffs.result[10]
+result[11] <= altshift:external_latency_ffs.result[11]
+result[12] <= altshift:external_latency_ffs.result[12]
+result[13] <= altshift:external_latency_ffs.result[13]
+result[14] <= altshift:external_latency_ffs.result[14]
+result[15] <= altshift:external_latency_ffs.result[15]
+result[16] <= altshift:external_latency_ffs.result[16]
+result[17] <= altshift:external_latency_ffs.result[17]
+result[18] <= altshift:external_latency_ffs.result[18]
+result[19] <= altshift:external_latency_ffs.result[19]
+result[20] <= altshift:external_latency_ffs.result[20]
+result[21] <= altshift:external_latency_ffs.result[21]
+result[22] <= altshift:external_latency_ffs.result[22]
+result[23] <= altshift:external_latency_ffs.result[23]
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[8] => _.IN0
+dataa[8] => _.IN3
+dataa[9] => ina_reg_clkd[1].IN0
+datab[0] => op_1.IN34
+datab[0] => op_2.IN35
+datab[0] => op_4.IN35
+datab[0] => op_5.IN35
+datab[0] => op_6.IN35
+datab[0] => op_7.IN35
+datab[0] => op_8.IN35
+datab[0] => op_9.IN35
+datab[0] => op_10.IN35
+datab[0] => op_11.IN35
+datab[0] => romout[0][0].IN1
+datab[0] => romout[1][0].IN1
+datab[0] => op_1.IN33
+datab[0] => op_3.IN33
+datab[0] => romout[0][1].IN1
+datab[0] => romout[1][1].IN1
+datab[0] => op_2.IN30
+datab[0] => op_3.IN30
+datab[0] => romout[0][2].IN1
+datab[0] => romout[1][2].IN1
+datab[0] => op_5.IN28
+datab[0] => romout[0][3].IN1
+datab[0] => romout[1][3].IN1
+datab[0] => romout[2][0].IN1
+datab[0] => romout[2][1].IN1
+datab[0] => romout[2][2].IN1
+datab[0] => romout[2][3].IN1
+datab[1] => op_1.IN32
+datab[1] => op_2.IN33
+datab[1] => op_4.IN33
+datab[1] => op_5.IN33
+datab[1] => op_6.IN33
+datab[1] => op_7.IN33
+datab[1] => op_8.IN33
+datab[1] => op_9.IN33
+datab[1] => op_10.IN33
+datab[1] => op_11.IN33
+datab[1] => romout[0][1].IN1
+datab[1] => romout[1][1].IN1
+datab[1] => op_1.IN31
+datab[1] => op_3.IN31
+datab[1] => romout[0][2].IN1
+datab[1] => romout[1][2].IN1
+datab[1] => op_2.IN28
+datab[1] => op_3.IN28
+datab[1] => romout[0][3].IN1
+datab[1] => romout[1][3].IN1
+datab[1] => op_5.IN26
+datab[1] => romout[0][4].IN1
+datab[1] => romout[1][4].IN1
+datab[1] => romout[2][1].IN1
+datab[1] => romout[2][2].IN1
+datab[1] => romout[2][3].IN1
+datab[1] => romout[2][4].IN1
+datab[2] => op_1.IN30
+datab[2] => op_2.IN31
+datab[2] => op_4.IN31
+datab[2] => op_5.IN31
+datab[2] => op_6.IN31
+datab[2] => op_7.IN31
+datab[2] => op_8.IN31
+datab[2] => op_9.IN31
+datab[2] => op_10.IN31
+datab[2] => op_11.IN31
+datab[2] => romout[0][2].IN1
+datab[2] => romout[1][2].IN1
+datab[2] => op_1.IN29
+datab[2] => op_3.IN29
+datab[2] => romout[0][3].IN1
+datab[2] => romout[1][3].IN1
+datab[2] => op_2.IN26
+datab[2] => op_3.IN26
+datab[2] => romout[0][4].IN1
+datab[2] => romout[1][4].IN1
+datab[2] => op_5.IN24
+datab[2] => romout[0][5].IN1
+datab[2] => romout[1][5].IN1
+datab[2] => romout[2][2].IN1
+datab[2] => romout[2][3].IN1
+datab[2] => romout[2][4].IN1
+datab[2] => romout[2][5].IN1
+datab[3] => op_1.IN28
+datab[3] => op_2.IN29
+datab[3] => op_4.IN29
+datab[3] => op_5.IN29
+datab[3] => op_6.IN29
+datab[3] => op_7.IN29
+datab[3] => op_8.IN29
+datab[3] => op_9.IN29
+datab[3] => op_10.IN29
+datab[3] => op_11.IN29
+datab[3] => romout[0][3].IN1
+datab[3] => romout[1][3].IN1
+datab[3] => op_1.IN27
+datab[3] => op_3.IN27
+datab[3] => romout[0][4].IN1
+datab[3] => romout[1][4].IN1
+datab[3] => op_2.IN24
+datab[3] => op_3.IN24
+datab[3] => romout[0][5].IN1
+datab[3] => romout[1][5].IN1
+datab[3] => op_5.IN22
+datab[3] => romout[0][6].IN1
+datab[3] => romout[1][6].IN1
+datab[3] => romout[2][3].IN1
+datab[3] => romout[2][4].IN1
+datab[3] => romout[2][5].IN1
+datab[3] => romout[2][6].IN1
+datab[4] => op_1.IN26
+datab[4] => op_2.IN27
+datab[4] => op_4.IN27
+datab[4] => op_5.IN27
+datab[4] => op_6.IN27
+datab[4] => op_7.IN27
+datab[4] => op_8.IN27
+datab[4] => op_9.IN27
+datab[4] => op_10.IN27
+datab[4] => op_11.IN27
+datab[4] => romout[0][4].IN1
+datab[4] => romout[1][4].IN1
+datab[4] => op_1.IN25
+datab[4] => op_3.IN25
+datab[4] => romout[0][5].IN1
+datab[4] => romout[1][5].IN1
+datab[4] => op_2.IN22
+datab[4] => op_3.IN22
+datab[4] => romout[0][6].IN1
+datab[4] => romout[1][6].IN1
+datab[4] => op_5.IN20
+datab[4] => romout[0][7].IN1
+datab[4] => romout[1][7].IN1
+datab[4] => romout[2][4].IN1
+datab[4] => romout[2][5].IN1
+datab[4] => romout[2][6].IN1
+datab[4] => romout[2][7].IN1
+datab[5] => op_1.IN24
+datab[5] => op_2.IN25
+datab[5] => op_4.IN25
+datab[5] => op_5.IN25
+datab[5] => op_6.IN25
+datab[5] => op_7.IN25
+datab[5] => op_8.IN25
+datab[5] => op_9.IN25
+datab[5] => op_10.IN25
+datab[5] => op_11.IN25
+datab[5] => romout[0][5].IN1
+datab[5] => romout[1][5].IN1
+datab[5] => op_1.IN23
+datab[5] => op_3.IN23
+datab[5] => romout[0][6].IN1
+datab[5] => romout[1][6].IN1
+datab[5] => op_2.IN20
+datab[5] => op_3.IN20
+datab[5] => romout[0][7].IN1
+datab[5] => romout[1][7].IN1
+datab[5] => op_5.IN18
+datab[5] => romout[0][8].IN1
+datab[5] => romout[1][8].IN1
+datab[5] => romout[2][5].IN1
+datab[5] => romout[2][6].IN1
+datab[5] => romout[2][7].IN1
+datab[5] => romout[2][8].IN1
+datab[6] => op_1.IN22
+datab[6] => op_2.IN23
+datab[6] => op_4.IN23
+datab[6] => op_5.IN23
+datab[6] => op_6.IN23
+datab[6] => op_7.IN23
+datab[6] => op_8.IN23
+datab[6] => op_9.IN23
+datab[6] => op_10.IN23
+datab[6] => op_11.IN23
+datab[6] => romout[0][6].IN1
+datab[6] => romout[1][6].IN1
+datab[6] => op_1.IN21
+datab[6] => op_3.IN21
+datab[6] => romout[0][7].IN1
+datab[6] => romout[1][7].IN1
+datab[6] => op_2.IN18
+datab[6] => op_3.IN18
+datab[6] => romout[0][8].IN1
+datab[6] => romout[1][8].IN1
+datab[6] => op_5.IN16
+datab[6] => romout[0][9].IN1
+datab[6] => romout[1][9].IN1
+datab[6] => romout[2][6].IN1
+datab[6] => romout[2][7].IN1
+datab[6] => romout[2][8].IN1
+datab[6] => romout[2][9].IN1
+datab[7] => op_1.IN20
+datab[7] => op_2.IN21
+datab[7] => op_4.IN21
+datab[7] => op_5.IN21
+datab[7] => op_6.IN21
+datab[7] => op_7.IN21
+datab[7] => op_8.IN21
+datab[7] => op_9.IN21
+datab[7] => op_10.IN21
+datab[7] => op_11.IN21
+datab[7] => romout[0][7].IN1
+datab[7] => romout[1][7].IN1
+datab[7] => op_1.IN19
+datab[7] => op_3.IN19
+datab[7] => romout[0][8].IN1
+datab[7] => romout[1][8].IN1
+datab[7] => op_2.IN16
+datab[7] => op_3.IN16
+datab[7] => romout[0][9].IN1
+datab[7] => romout[1][9].IN1
+datab[7] => op_5.IN14
+datab[7] => romout[0][10].IN1
+datab[7] => romout[1][10].IN1
+datab[7] => romout[2][7].IN1
+datab[7] => romout[2][8].IN1
+datab[7] => romout[2][9].IN1
+datab[7] => romout[2][10].IN1
+datab[8] => op_1.IN18
+datab[8] => op_2.IN19
+datab[8] => op_4.IN19
+datab[8] => op_5.IN19
+datab[8] => op_6.IN19
+datab[8] => op_7.IN19
+datab[8] => op_8.IN19
+datab[8] => op_9.IN19
+datab[8] => op_10.IN19
+datab[8] => op_11.IN19
+datab[8] => romout[0][8].IN1
+datab[8] => romout[1][8].IN1
+datab[8] => op_1.IN17
+datab[8] => op_3.IN17
+datab[8] => romout[0][9].IN1
+datab[8] => romout[1][9].IN1
+datab[8] => op_2.IN14
+datab[8] => op_3.IN14
+datab[8] => romout[0][10].IN1
+datab[8] => romout[1][10].IN1
+datab[8] => op_5.IN12
+datab[8] => romout[0][11].IN1
+datab[8] => romout[1][11].IN1
+datab[8] => romout[2][8].IN1
+datab[8] => romout[2][9].IN1
+datab[8] => romout[2][10].IN1
+datab[8] => romout[2][11].IN1
+datab[9] => op_1.IN16
+datab[9] => op_2.IN17
+datab[9] => op_4.IN17
+datab[9] => op_5.IN17
+datab[9] => op_6.IN17
+datab[9] => op_7.IN17
+datab[9] => op_8.IN17
+datab[9] => op_9.IN17
+datab[9] => op_10.IN17
+datab[9] => op_11.IN17
+datab[9] => romout[0][9].IN1
+datab[9] => romout[1][9].IN1
+datab[9] => op_1.IN15
+datab[9] => op_3.IN15
+datab[9] => romout[0][10].IN1
+datab[9] => romout[1][10].IN1
+datab[9] => op_2.IN12
+datab[9] => op_3.IN12
+datab[9] => romout[0][11].IN1
+datab[9] => romout[1][11].IN1
+datab[9] => op_5.IN10
+datab[9] => romout[0][12].IN1
+datab[9] => romout[1][12].IN1
+datab[9] => romout[2][9].IN1
+datab[9] => romout[2][10].IN1
+datab[9] => romout[2][11].IN1
+datab[9] => romout[2][12].IN1
+datab[10] => op_1.IN14
+datab[10] => op_2.IN15
+datab[10] => op_4.IN15
+datab[10] => op_5.IN15
+datab[10] => op_6.IN15
+datab[10] => op_7.IN15
+datab[10] => op_8.IN15
+datab[10] => op_9.IN15
+datab[10] => op_10.IN15
+datab[10] => op_11.IN15
+datab[10] => romout[0][10].IN1
+datab[10] => romout[1][10].IN1
+datab[10] => op_1.IN13
+datab[10] => op_3.IN13
+datab[10] => romout[0][11].IN1
+datab[10] => romout[1][11].IN1
+datab[10] => op_2.IN10
+datab[10] => op_3.IN10
+datab[10] => romout[0][12].IN1
+datab[10] => romout[1][12].IN1
+datab[10] => op_5.IN8
+datab[10] => romout[0][13].IN1
+datab[10] => romout[1][13].IN1
+datab[10] => romout[2][10].IN1
+datab[10] => romout[2][11].IN1
+datab[10] => romout[2][12].IN1
+datab[10] => romout[2][13].IN1
+datab[11] => op_1.IN12
+datab[11] => op_2.IN13
+datab[11] => op_4.IN13
+datab[11] => op_5.IN13
+datab[11] => op_6.IN13
+datab[11] => op_7.IN13
+datab[11] => op_8.IN13
+datab[11] => op_9.IN13
+datab[11] => op_10.IN13
+datab[11] => op_11.IN13
+datab[11] => romout[0][11].IN1
+datab[11] => romout[1][11].IN1
+datab[11] => op_1.IN11
+datab[11] => op_3.IN11
+datab[11] => romout[0][12].IN1
+datab[11] => romout[1][12].IN1
+datab[11] => op_2.IN8
+datab[11] => op_3.IN8
+datab[11] => romout[0][13].IN1
+datab[11] => romout[1][13].IN1
+datab[11] => op_5.IN6
+datab[11] => romout[0][14].IN1
+datab[11] => romout[1][14].IN1
+datab[11] => romout[2][11].IN1
+datab[11] => romout[2][12].IN1
+datab[11] => romout[2][13].IN1
+datab[11] => romout[2][14].IN1
+datab[12] => op_1.IN10
+datab[12] => op_2.IN11
+datab[12] => op_4.IN11
+datab[12] => op_5.IN11
+datab[12] => op_6.IN11
+datab[12] => op_7.IN11
+datab[12] => op_8.IN11
+datab[12] => op_9.IN11
+datab[12] => op_10.IN11
+datab[12] => op_11.IN11
+datab[12] => romout[0][12].IN1
+datab[12] => romout[1][12].IN1
+datab[12] => op_1.IN9
+datab[12] => op_3.IN9
+datab[12] => romout[0][13].IN1
+datab[12] => romout[1][13].IN1
+datab[12] => op_2.IN6
+datab[12] => op_3.IN6
+datab[12] => romout[0][14].IN1
+datab[12] => romout[1][14].IN1
+datab[12] => op_5.IN4
+datab[12] => romout[0][15].IN1
+datab[12] => romout[1][15].IN1
+datab[12] => romout[2][12].IN1
+datab[12] => romout[2][13].IN1
+datab[12] => romout[2][14].IN1
+datab[12] => romout[2][15].IN1
+datab[13] => op_1.IN8
+datab[13] => op_2.IN9
+datab[13] => op_4.IN9
+datab[13] => op_5.IN9
+datab[13] => op_6.IN9
+datab[13] => op_7.IN9
+datab[13] => op_8.IN9
+datab[13] => op_9.IN9
+datab[13] => op_10.IN9
+datab[13] => op_11.IN9
+datab[13] => romout[0][13].IN1
+datab[13] => romout[1][13].IN1
+datab[13] => op_1.IN7
+datab[13] => op_3.IN7
+datab[13] => romout[0][14].IN1
+datab[13] => romout[1][14].IN1
+datab[13] => op_2.IN4
+datab[13] => op_3.IN4
+datab[13] => romout[0][15].IN1
+datab[13] => romout[1][15].IN1
+datab[13] => op_5.IN2
+datab[13] => romout[0][16].IN1
+datab[13] => romout[1][16].IN1
+datab[13] => romout[2][13].IN1
+datab[13] => romout[2][14].IN1
+datab[13] => romout[2][15].IN1
+datab[13] => romout[2][16].IN1
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mpar_add:padder.result[0]
+result[1] <= mpar_add:padder.result[1]
+result[2] <= mpar_add:padder.result[2]
+result[3] <= mpar_add:padder.result[3]
+result[4] <= mpar_add:padder.result[4]
+result[5] <= mpar_add:padder.result[5]
+result[6] <= mpar_add:padder.result[6]
+result[7] <= mpar_add:padder.result[7]
+result[8] <= mpar_add:padder.result[8]
+result[9] <= mpar_add:padder.result[9]
+result[10] <= mpar_add:padder.result[10]
+result[11] <= mpar_add:padder.result[11]
+result[12] <= mpar_add:padder.result[12]
+result[13] <= mpar_add:padder.result[13]
+result[14] <= mpar_add:padder.result[14]
+result[15] <= mpar_add:padder.result[15]
+result[16] <= mpar_add:padder.result[16]
+result[17] <= mpar_add:padder.result[17]
+result[18] <= mpar_add:padder.result[18]
+result[19] <= mpar_add:padder.result[19]
+result[20] <= mpar_add:padder.result[20]
+result[21] <= mpar_add:padder.result[21]
+result[22] <= mpar_add:padder.result[22]
+result[23] <= mpar_add:padder.result[23]
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder
+data[0][0] => mpar_add:sub_par_add.data[0][0]
+data[0][1] => mpar_add:sub_par_add.data[0][1]
+data[0][2] => mpar_add:sub_par_add.data[0][2]
+data[0][3] => mpar_add:sub_par_add.data[0][3]
+data[0][4] => lpm_add_sub:adder[0].dataa[0]
+data[0][5] => lpm_add_sub:adder[0].dataa[1]
+data[0][6] => lpm_add_sub:adder[0].dataa[2]
+data[0][7] => lpm_add_sub:adder[0].dataa[3]
+data[0][8] => lpm_add_sub:adder[0].dataa[4]
+data[0][9] => lpm_add_sub:adder[0].dataa[5]
+data[0][10] => lpm_add_sub:adder[0].dataa[6]
+data[0][11] => lpm_add_sub:adder[0].dataa[7]
+data[0][12] => lpm_add_sub:adder[0].dataa[8]
+data[0][13] => lpm_add_sub:adder[0].dataa[9]
+data[0][14] => lpm_add_sub:adder[0].dataa[10]
+data[0][15] => lpm_add_sub:adder[0].dataa[11]
+data[0][16] => lpm_add_sub:adder[0].dataa[12]
+data[0][17] => lpm_add_sub:adder[0].dataa[13]
+data[1][0] => lpm_add_sub:adder[0].datab[0]
+data[1][1] => lpm_add_sub:adder[0].datab[1]
+data[1][2] => lpm_add_sub:adder[0].datab[2]
+data[1][3] => lpm_add_sub:adder[0].datab[3]
+data[1][4] => lpm_add_sub:adder[0].datab[4]
+data[1][5] => lpm_add_sub:adder[0].datab[5]
+data[1][6] => lpm_add_sub:adder[0].datab[6]
+data[1][7] => lpm_add_sub:adder[0].datab[7]
+data[1][8] => lpm_add_sub:adder[0].datab[8]
+data[1][9] => lpm_add_sub:adder[0].datab[9]
+data[1][10] => lpm_add_sub:adder[0].datab[10]
+data[1][11] => lpm_add_sub:adder[0].datab[11]
+data[1][12] => lpm_add_sub:adder[0].datab[12]
+data[1][13] => lpm_add_sub:adder[0].datab[13]
+data[1][14] => lpm_add_sub:adder[0].datab[14]
+data[1][15] => lpm_add_sub:adder[0].datab[15]
+data[1][16] => lpm_add_sub:adder[0].datab[16]
+data[1][17] => lpm_add_sub:adder[0].datab[17]
+data[2][0] => mpar_add:sub_par_add.data[1][0]
+data[2][1] => mpar_add:sub_par_add.data[1][1]
+data[2][2] => mpar_add:sub_par_add.data[1][2]
+data[2][3] => mpar_add:sub_par_add.data[1][3]
+data[2][4] => mpar_add:sub_par_add.data[1][4]
+data[2][5] => mpar_add:sub_par_add.data[1][5]
+data[2][6] => mpar_add:sub_par_add.data[1][6]
+data[2][7] => mpar_add:sub_par_add.data[1][7]
+data[2][8] => mpar_add:sub_par_add.data[1][8]
+data[2][9] => mpar_add:sub_par_add.data[1][9]
+data[2][10] => mpar_add:sub_par_add.data[1][10]
+data[2][11] => mpar_add:sub_par_add.data[1][11]
+data[2][12] => mpar_add:sub_par_add.data[1][12]
+data[2][13] => mpar_add:sub_par_add.data[1][13]
+data[2][14] => mpar_add:sub_par_add.data[1][14]
+data[2][15] => mpar_add:sub_par_add.data[1][15]
+data[2][16] => mpar_add:sub_par_add.data[1][16]
+data[2][17] => mpar_add:sub_par_add.data[1][17]
+cin => ~NO_FANOUT~
+clk => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mpar_add:sub_par_add.result[0]
+result[1] <= mpar_add:sub_par_add.result[1]
+result[2] <= mpar_add:sub_par_add.result[2]
+result[3] <= mpar_add:sub_par_add.result[3]
+result[4] <= mpar_add:sub_par_add.result[4]
+result[5] <= mpar_add:sub_par_add.result[5]
+result[6] <= mpar_add:sub_par_add.result[6]
+result[7] <= mpar_add:sub_par_add.result[7]
+result[8] <= mpar_add:sub_par_add.result[8]
+result[9] <= mpar_add:sub_par_add.result[9]
+result[10] <= mpar_add:sub_par_add.result[10]
+result[11] <= mpar_add:sub_par_add.result[11]
+result[12] <= mpar_add:sub_par_add.result[12]
+result[13] <= mpar_add:sub_par_add.result[13]
+result[14] <= mpar_add:sub_par_add.result[14]
+result[15] <= mpar_add:sub_par_add.result[15]
+result[16] <= mpar_add:sub_par_add.result[16]
+result[17] <= mpar_add:sub_par_add.result[17]
+result[18] <= mpar_add:sub_par_add.result[18]
+result[19] <= mpar_add:sub_par_add.result[19]
+result[20] <= mpar_add:sub_par_add.result[20]
+result[21] <= mpar_add:sub_par_add.result[21]
+result[22] <= mpar_add:sub_par_add.result[22]
+result[23] <= mpar_add:sub_par_add.result[23]
+result[24] <= mpar_add:sub_par_add.result[24]
+result[25] <= mpar_add:sub_par_add.result[25]
+result[26] <= mpar_add:sub_par_add.result[26]
+result[27] <= mpar_add:sub_par_add.result[27]
+result[28] <= mpar_add:sub_par_add.result[28]
+result[29] <= mpar_add:sub_par_add.result[29]
+clk_out <= <GND>
+aclr_out <= <GND>
+clken_out <= <GND>
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]
+dataa[0] => add_sub_d9h:auto_generated.dataa[0]
+dataa[1] => add_sub_d9h:auto_generated.dataa[1]
+dataa[2] => add_sub_d9h:auto_generated.dataa[2]
+dataa[3] => add_sub_d9h:auto_generated.dataa[3]
+dataa[4] => add_sub_d9h:auto_generated.dataa[4]
+dataa[5] => add_sub_d9h:auto_generated.dataa[5]
+dataa[6] => add_sub_d9h:auto_generated.dataa[6]
+dataa[7] => add_sub_d9h:auto_generated.dataa[7]
+dataa[8] => add_sub_d9h:auto_generated.dataa[8]
+dataa[9] => add_sub_d9h:auto_generated.dataa[9]
+dataa[10] => add_sub_d9h:auto_generated.dataa[10]
+dataa[11] => add_sub_d9h:auto_generated.dataa[11]
+dataa[12] => add_sub_d9h:auto_generated.dataa[12]
+dataa[13] => add_sub_d9h:auto_generated.dataa[13]
+dataa[14] => add_sub_d9h:auto_generated.dataa[14]
+dataa[15] => add_sub_d9h:auto_generated.dataa[15]
+dataa[16] => add_sub_d9h:auto_generated.dataa[16]
+dataa[17] => add_sub_d9h:auto_generated.dataa[17]
+datab[0] => add_sub_d9h:auto_generated.datab[0]
+datab[1] => add_sub_d9h:auto_generated.datab[1]
+datab[2] => add_sub_d9h:auto_generated.datab[2]
+datab[3] => add_sub_d9h:auto_generated.datab[3]
+datab[4] => add_sub_d9h:auto_generated.datab[4]
+datab[5] => add_sub_d9h:auto_generated.datab[5]
+datab[6] => add_sub_d9h:auto_generated.datab[6]
+datab[7] => add_sub_d9h:auto_generated.datab[7]
+datab[8] => add_sub_d9h:auto_generated.datab[8]
+datab[9] => add_sub_d9h:auto_generated.datab[9]
+datab[10] => add_sub_d9h:auto_generated.datab[10]
+datab[11] => add_sub_d9h:auto_generated.datab[11]
+datab[12] => add_sub_d9h:auto_generated.datab[12]
+datab[13] => add_sub_d9h:auto_generated.datab[13]
+datab[14] => add_sub_d9h:auto_generated.datab[14]
+datab[15] => add_sub_d9h:auto_generated.datab[15]
+datab[16] => add_sub_d9h:auto_generated.datab[16]
+datab[17] => add_sub_d9h:auto_generated.datab[17]
+cin => ~NO_FANOUT~
+add_sub => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= add_sub_d9h:auto_generated.result[0]
+result[1] <= add_sub_d9h:auto_generated.result[1]
+result[2] <= add_sub_d9h:auto_generated.result[2]
+result[3] <= add_sub_d9h:auto_generated.result[3]
+result[4] <= add_sub_d9h:auto_generated.result[4]
+result[5] <= add_sub_d9h:auto_generated.result[5]
+result[6] <= add_sub_d9h:auto_generated.result[6]
+result[7] <= add_sub_d9h:auto_generated.result[7]
+result[8] <= add_sub_d9h:auto_generated.result[8]
+result[9] <= add_sub_d9h:auto_generated.result[9]
+result[10] <= add_sub_d9h:auto_generated.result[10]
+result[11] <= add_sub_d9h:auto_generated.result[11]
+result[12] <= add_sub_d9h:auto_generated.result[12]
+result[13] <= add_sub_d9h:auto_generated.result[13]
+result[14] <= add_sub_d9h:auto_generated.result[14]
+result[15] <= add_sub_d9h:auto_generated.result[15]
+result[16] <= add_sub_d9h:auto_generated.result[16]
+result[17] <= add_sub_d9h:auto_generated.result[17]
+cout <= <GND>
+overflow <= <GND>
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated
+dataa[0] => op_1.IN34
+dataa[1] => op_1.IN32
+dataa[2] => op_1.IN30
+dataa[3] => op_1.IN28
+dataa[4] => op_1.IN26
+dataa[5] => op_1.IN24
+dataa[6] => op_1.IN22
+dataa[7] => op_1.IN20
+dataa[8] => op_1.IN18
+dataa[9] => op_1.IN16
+dataa[10] => op_1.IN14
+dataa[11] => op_1.IN12
+dataa[12] => op_1.IN10
+dataa[13] => op_1.IN8
+dataa[14] => op_1.IN6
+dataa[15] => op_1.IN4
+dataa[16] => op_1.IN2
+dataa[17] => op_1.IN0
+datab[0] => op_1.IN35
+datab[1] => op_1.IN33
+datab[2] => op_1.IN31
+datab[3] => op_1.IN29
+datab[4] => op_1.IN27
+datab[5] => op_1.IN25
+datab[6] => op_1.IN23
+datab[7] => op_1.IN21
+datab[8] => op_1.IN19
+datab[9] => op_1.IN17
+datab[10] => op_1.IN15
+datab[11] => op_1.IN13
+datab[12] => op_1.IN11
+datab[13] => op_1.IN9
+datab[14] => op_1.IN7
+datab[15] => op_1.IN5
+datab[16] => op_1.IN3
+datab[17] => op_1.IN1
+result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add
+data[0][0] => result[0].DATAIN
+data[0][1] => result[1].DATAIN
+data[0][2] => result[2].DATAIN
+data[0][3] => result[3].DATAIN
+data[0][4] => result[4].DATAIN
+data[0][5] => result[5].DATAIN
+data[0][6] => result[6].DATAIN
+data[0][7] => result[7].DATAIN
+data[0][8] => lpm_add_sub:adder[0].dataa[0]
+data[0][9] => lpm_add_sub:adder[0].dataa[1]
+data[0][10] => lpm_add_sub:adder[0].dataa[2]
+data[0][11] => lpm_add_sub:adder[0].dataa[3]
+data[0][12] => lpm_add_sub:adder[0].dataa[4]
+data[0][13] => lpm_add_sub:adder[0].dataa[5]
+data[0][14] => lpm_add_sub:adder[0].dataa[6]
+data[0][15] => lpm_add_sub:adder[0].dataa[7]
+data[0][16] => lpm_add_sub:adder[0].dataa[8]
+data[0][17] => lpm_add_sub:adder[0].dataa[9]
+data[0][18] => lpm_add_sub:adder[0].dataa[10]
+data[0][19] => lpm_add_sub:adder[0].dataa[11]
+data[0][20] => lpm_add_sub:adder[0].dataa[12]
+data[0][21] => lpm_add_sub:adder[0].dataa[13]
+data[1][0] => lpm_add_sub:adder[0].datab[0]
+data[1][1] => lpm_add_sub:adder[0].datab[1]
+data[1][2] => lpm_add_sub:adder[0].datab[2]
+data[1][3] => lpm_add_sub:adder[0].datab[3]
+data[1][4] => lpm_add_sub:adder[0].datab[4]
+data[1][5] => lpm_add_sub:adder[0].datab[5]
+data[1][6] => lpm_add_sub:adder[0].datab[6]
+data[1][7] => lpm_add_sub:adder[0].datab[7]
+data[1][8] => lpm_add_sub:adder[0].datab[8]
+data[1][9] => lpm_add_sub:adder[0].datab[9]
+data[1][10] => lpm_add_sub:adder[0].datab[10]
+data[1][11] => lpm_add_sub:adder[0].datab[11]
+data[1][12] => lpm_add_sub:adder[0].datab[12]
+data[1][13] => lpm_add_sub:adder[0].datab[13]
+data[1][14] => lpm_add_sub:adder[0].datab[14]
+data[1][15] => lpm_add_sub:adder[0].datab[15]
+data[1][16] => lpm_add_sub:adder[0].datab[16]
+data[1][17] => lpm_add_sub:adder[0].datab[17]
+data[1][18] => ~NO_FANOUT~
+data[1][19] => ~NO_FANOUT~
+data[1][20] => ~NO_FANOUT~
+data[1][21] => ~NO_FANOUT~
+cin => ~NO_FANOUT~
+clk => clk_out.IN0
+aclr => aclr_out.IN0
+clken => clken_out.IN0
+result[0] <= data[0][0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= data[0][1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= data[0][2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= data[0][3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= data[0][4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= data[0][5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= data[0][6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= data[0][7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= level_result_node[0][0].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= level_result_node[0][1].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= level_result_node[0][2].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= level_result_node[0][3].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= level_result_node[0][4].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= level_result_node[0][5].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= level_result_node[0][6].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= level_result_node[0][7].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= level_result_node[0][8].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= level_result_node[0][9].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= level_result_node[0][10].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= level_result_node[0][11].DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= level_result_node[0][12].DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= level_result_node[0][13].DB_MAX_OUTPUT_PORT_TYPE
+result[22] <= level_result_node[0][14].DB_MAX_OUTPUT_PORT_TYPE
+result[23] <= level_result_node[0][15].DB_MAX_OUTPUT_PORT_TYPE
+result[24] <= level_result_node[0][16].DB_MAX_OUTPUT_PORT_TYPE
+result[25] <= level_result_node[0][17].DB_MAX_OUTPUT_PORT_TYPE
+result[26] <= level_result_node[0][18].DB_MAX_OUTPUT_PORT_TYPE
+result[27] <= level_result_node[0][19].DB_MAX_OUTPUT_PORT_TYPE
+result[28] <= level_result_node[0][20].DB_MAX_OUTPUT_PORT_TYPE
+result[29] <= level_result_node[0][21].DB_MAX_OUTPUT_PORT_TYPE
+clk_out <= clk_out.DB_MAX_OUTPUT_PORT_TYPE
+aclr_out <= aclr_out.DB_MAX_OUTPUT_PORT_TYPE
+clken_out <= clken_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]
+dataa[0] => add_sub_89h:auto_generated.dataa[0]
+dataa[1] => add_sub_89h:auto_generated.dataa[1]
+dataa[2] => add_sub_89h:auto_generated.dataa[2]
+dataa[3] => add_sub_89h:auto_generated.dataa[3]
+dataa[4] => add_sub_89h:auto_generated.dataa[4]
+dataa[5] => add_sub_89h:auto_generated.dataa[5]
+dataa[6] => add_sub_89h:auto_generated.dataa[6]
+dataa[7] => add_sub_89h:auto_generated.dataa[7]
+dataa[8] => add_sub_89h:auto_generated.dataa[8]
+dataa[9] => add_sub_89h:auto_generated.dataa[9]
+dataa[10] => add_sub_89h:auto_generated.dataa[10]
+dataa[11] => add_sub_89h:auto_generated.dataa[11]
+dataa[12] => add_sub_89h:auto_generated.dataa[12]
+dataa[13] => add_sub_89h:auto_generated.dataa[13]
+dataa[14] => add_sub_89h:auto_generated.dataa[14]
+dataa[15] => add_sub_89h:auto_generated.dataa[15]
+dataa[16] => add_sub_89h:auto_generated.dataa[16]
+dataa[17] => add_sub_89h:auto_generated.dataa[17]
+dataa[18] => add_sub_89h:auto_generated.dataa[18]
+dataa[19] => add_sub_89h:auto_generated.dataa[19]
+dataa[20] => add_sub_89h:auto_generated.dataa[20]
+dataa[21] => add_sub_89h:auto_generated.dataa[21]
+datab[0] => add_sub_89h:auto_generated.datab[0]
+datab[1] => add_sub_89h:auto_generated.datab[1]
+datab[2] => add_sub_89h:auto_generated.datab[2]
+datab[3] => add_sub_89h:auto_generated.datab[3]
+datab[4] => add_sub_89h:auto_generated.datab[4]
+datab[5] => add_sub_89h:auto_generated.datab[5]
+datab[6] => add_sub_89h:auto_generated.datab[6]
+datab[7] => add_sub_89h:auto_generated.datab[7]
+datab[8] => add_sub_89h:auto_generated.datab[8]
+datab[9] => add_sub_89h:auto_generated.datab[9]
+datab[10] => add_sub_89h:auto_generated.datab[10]
+datab[11] => add_sub_89h:auto_generated.datab[11]
+datab[12] => add_sub_89h:auto_generated.datab[12]
+datab[13] => add_sub_89h:auto_generated.datab[13]
+datab[14] => add_sub_89h:auto_generated.datab[14]
+datab[15] => add_sub_89h:auto_generated.datab[15]
+datab[16] => add_sub_89h:auto_generated.datab[16]
+datab[17] => add_sub_89h:auto_generated.datab[17]
+datab[18] => add_sub_89h:auto_generated.datab[18]
+datab[19] => add_sub_89h:auto_generated.datab[19]
+datab[20] => add_sub_89h:auto_generated.datab[20]
+datab[21] => add_sub_89h:auto_generated.datab[21]
+cin => ~NO_FANOUT~
+add_sub => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= add_sub_89h:auto_generated.result[0]
+result[1] <= add_sub_89h:auto_generated.result[1]
+result[2] <= add_sub_89h:auto_generated.result[2]
+result[3] <= add_sub_89h:auto_generated.result[3]
+result[4] <= add_sub_89h:auto_generated.result[4]
+result[5] <= add_sub_89h:auto_generated.result[5]
+result[6] <= add_sub_89h:auto_generated.result[6]
+result[7] <= add_sub_89h:auto_generated.result[7]
+result[8] <= add_sub_89h:auto_generated.result[8]
+result[9] <= add_sub_89h:auto_generated.result[9]
+result[10] <= add_sub_89h:auto_generated.result[10]
+result[11] <= add_sub_89h:auto_generated.result[11]
+result[12] <= add_sub_89h:auto_generated.result[12]
+result[13] <= add_sub_89h:auto_generated.result[13]
+result[14] <= add_sub_89h:auto_generated.result[14]
+result[15] <= add_sub_89h:auto_generated.result[15]
+result[16] <= add_sub_89h:auto_generated.result[16]
+result[17] <= add_sub_89h:auto_generated.result[17]
+result[18] <= add_sub_89h:auto_generated.result[18]
+result[19] <= add_sub_89h:auto_generated.result[19]
+result[20] <= add_sub_89h:auto_generated.result[20]
+result[21] <= add_sub_89h:auto_generated.result[21]
+cout <= <GND>
+overflow <= <GND>
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated
+dataa[0] => op_1.IN42
+dataa[1] => op_1.IN40
+dataa[2] => op_1.IN38
+dataa[3] => op_1.IN36
+dataa[4] => op_1.IN34
+dataa[5] => op_1.IN32
+dataa[6] => op_1.IN30
+dataa[7] => op_1.IN28
+dataa[8] => op_1.IN26
+dataa[9] => op_1.IN24
+dataa[10] => op_1.IN22
+dataa[11] => op_1.IN20
+dataa[12] => op_1.IN18
+dataa[13] => op_1.IN16
+dataa[14] => op_1.IN14
+dataa[15] => op_1.IN12
+dataa[16] => op_1.IN10
+dataa[17] => op_1.IN8
+dataa[18] => op_1.IN6
+dataa[19] => op_1.IN4
+dataa[20] => op_1.IN2
+dataa[21] => op_1.IN0
+datab[0] => op_1.IN43
+datab[1] => op_1.IN41
+datab[2] => op_1.IN39
+datab[3] => op_1.IN37
+datab[4] => op_1.IN35
+datab[5] => op_1.IN33
+datab[6] => op_1.IN31
+datab[7] => op_1.IN29
+datab[8] => op_1.IN27
+datab[9] => op_1.IN25
+datab[10] => op_1.IN23
+datab[11] => op_1.IN21
+datab[12] => op_1.IN19
+datab[13] => op_1.IN17
+datab[14] => op_1.IN15
+datab[15] => op_1.IN13
+datab[16] => op_1.IN11
+datab[17] => op_1.IN9
+datab[18] => op_1.IN7
+datab[19] => op_1.IN5
+datab[20] => op_1.IN3
+datab[21] => op_1.IN1
+result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|const_mult:mult|lpm_mult:lpm_mult_component|altshift:external_latency_ffs
+data[0] => result[0].DATAIN
+data[1] => result[1].DATAIN
+data[2] => result[2].DATAIN
+data[3] => result[3].DATAIN
+data[4] => result[4].DATAIN
+data[5] => result[5].DATAIN
+data[6] => result[6].DATAIN
+data[7] => result[7].DATAIN
+data[8] => result[8].DATAIN
+data[9] => result[9].DATAIN
+data[10] => result[10].DATAIN
+data[11] => result[11].DATAIN
+data[12] => result[12].DATAIN
+data[13] => result[13].DATAIN
+data[14] => result[14].DATAIN
+data[15] => result[15].DATAIN
+data[16] => result[16].DATAIN
+data[17] => result[17].DATAIN
+data[18] => result[18].DATAIN
+data[19] => result[19].DATAIN
+data[20] => result[20].DATAIN
+data[21] => result[21].DATAIN
+data[22] => result[22].DATAIN
+data[23] => result[23].DATAIN
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= data[12].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= data[13].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= data[14].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= data[15].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= data[16].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= data[17].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= data[18].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= data[19].DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= data[20].DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= data[21].DB_MAX_OUTPUT_PORT_TYPE
+result[22] <= data[22].DB_MAX_OUTPUT_PORT_TYPE
+result[23] <= data[23].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd
+B[0] => BCD_0[0].DATAIN
+B[1] => w29[0].IN1
+B[2] => w25[0].IN1
+B[3] => w21[0].IN1
+B[4] => w17[0].IN1
+B[5] => w14[0].IN1
+B[6] => w11[0].IN1
+B[7] => w8[0].IN1
+B[8] => w6[0].IN1
+B[9] => w4[0].IN1
+B[10] => w2[0].IN1
+B[11] => w1[0].IN1
+B[12] => w1[1].IN1
+B[13] => w1[2].IN1
+B[14] => w1[3].IN1
+B[15] => w3[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A29.port1
+BCD_0[2] <= add3_ge5:A29.port1
+BCD_0[3] <= add3_ge5:A29.port1
+BCD_1[0] <= add3_ge5:A29.port1
+BCD_1[1] <= add3_ge5:A28.port1
+BCD_1[2] <= add3_ge5:A28.port1
+BCD_1[3] <= add3_ge5:A28.port1
+BCD_2[0] <= add3_ge5:A28.port1
+BCD_2[1] <= add3_ge5:A27.port1
+BCD_2[2] <= add3_ge5:A27.port1
+BCD_2[3] <= add3_ge5:A27.port1
+BCD_3[0] <= add3_ge5:A27.port1
+BCD_3[1] <= add3_ge5:A26.port1
+BCD_3[2] <= add3_ge5:A26.port1
+BCD_3[3] <= add3_ge5:A26.port1
+BCD_4[0] <= add3_ge5:A26.port1
+BCD_4[1] <= add3_ge5:A22.port1
+BCD_4[2] <= add3_ge5:A18.port1
+BCD_4[3] <= <GND>
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A1
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A2
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A3
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A4
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A5
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A6
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A7
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A8
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A9
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A10
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A11
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A12
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A13
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A14
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A15
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A16
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A17
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A18
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A19
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A20
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A21
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A22
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A23
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A24
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A25
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A26
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A27
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A28
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|bin2bcd_16:bcd|add3_ge5:A29
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex15|hex_to_7seg:h0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex15|hex_to_7seg:h1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex15|hex_to_7seg:h2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex15|hex_to_7seg:h3
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex15|hex_to_7seg:h4
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_3/ex15/db/ex10.hif b/part_3/ex15/db/ex10.hif
new file mode 100755
index 0000000..7755283
--- /dev/null
+++ b/part_3/ex15/db/ex10.hif
diff --git a/part_2/ex9_final/db/ex9.lpc.html b/part_3/ex15/db/ex10.lpc.html
index 795349d..d0570ee 100755
--- a/part_2/ex9_final/db/ex9.lpc.html
+++ b/part_3/ex15/db/ex10.lpc.html
@@ -16,15 +16,15 @@
 <TH>Output only Bidir</TH>
 </TR>
 <TR >
-<TD >SEG5</TD>
-<TD >4</TD>
+<TD >h4</TD>
 <TD >4</TD>
 <TD >0</TD>
-<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
 <TD >7</TD>
-<TD >4</TD>
-<TD >4</TD>
-<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -32,7 +32,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG4</TD>
+<TD >h3</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -48,7 +48,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG3</TD>
+<TD >h2</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -64,7 +64,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG2</TD>
+<TD >h1</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -80,7 +80,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG1</TD>
+<TD >h0</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -96,12 +96,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >SEG0</TD>
+<TD >bcd|A29</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >7</TD>
+<TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -112,7 +112,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A35</TD>
+<TD >bcd|A28</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -128,7 +128,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A34</TD>
+<TD >bcd|A27</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -144,7 +144,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A33</TD>
+<TD >bcd|A26</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -160,7 +160,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A32</TD>
+<TD >bcd|A25</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -176,15 +176,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A31</TD>
+<TD >bcd|A24</TD>
 <TD >4</TD>
-<TD >1</TD>
 <TD >0</TD>
-<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
 <TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -192,7 +192,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A30</TD>
+<TD >bcd|A23</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -208,7 +208,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A29</TD>
+<TD >bcd|A22</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -224,7 +224,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A28</TD>
+<TD >bcd|A21</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -240,7 +240,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A27</TD>
+<TD >bcd|A20</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -256,7 +256,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A26</TD>
+<TD >bcd|A19</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -272,15 +272,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A25</TD>
+<TD >bcd|A18</TD>
 <TD >4</TD>
+<TD >1</TD>
 <TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
 <TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -288,7 +288,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A24</TD>
+<TD >bcd|A17</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -304,7 +304,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A23</TD>
+<TD >bcd|A16</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -320,7 +320,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A22</TD>
+<TD >bcd|A15</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -336,7 +336,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A21</TD>
+<TD >bcd|A14</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -352,7 +352,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A20</TD>
+<TD >bcd|A13</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -368,15 +368,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A19</TD>
+<TD >bcd|A12</TD>
 <TD >4</TD>
-<TD >1</TD>
 <TD >0</TD>
-<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
 <TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -384,7 +384,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A18</TD>
+<TD >bcd|A11</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -400,7 +400,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A17</TD>
+<TD >bcd|A10</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -416,15 +416,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A16</TD>
+<TD >bcd|A9</TD>
 <TD >4</TD>
+<TD >1</TD>
 <TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
 <TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -432,7 +432,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A15</TD>
+<TD >bcd|A8</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -448,7 +448,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A14</TD>
+<TD >bcd|A7</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -464,7 +464,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A13</TD>
+<TD >bcd|A6</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -480,7 +480,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A12</TD>
+<TD >bcd|A5</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -496,7 +496,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A11</TD>
+<TD >bcd|A4</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -512,7 +512,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A10</TD>
+<TD >bcd|A3</TD>
 <TD >4</TD>
 <TD >1</TD>
 <TD >0</TD>
@@ -528,7 +528,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A9</TD>
+<TD >bcd|A2</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -544,7 +544,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A8</TD>
+<TD >bcd|A1</TD>
 <TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -560,15 +560,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A7</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >bcd</TD>
+<TD >16</TD>
+<TD >3</TD>
 <TD >0</TD>
+<TD >3</TD>
+<TD >20</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >3</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -576,12 +576,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A6</TD>
-<TD >4</TD>
+<TD >mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated</TD>
+<TD >44</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >4</TD>
+<TD >22</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -592,44 +592,28 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A5</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
+<TD >mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated</TD>
+<TD >36</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
+<TD >18</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A4</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A3</TD>
-<TD >4</TD>
+<TD >mult</TD>
+<TD >10</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >4</TD>
+<TD >24</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -640,31 +624,15 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD|A2</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >4</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
+<TD >p</TD>
+<TD >12</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
+<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
-</TR>
-<TR >
-<TD >BCD|A1</TD>
-<TD >4</TD>
-<TD >1</TD>
 <TD >0</TD>
-<TD >1</TD>
-<TD >4</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -672,12 +640,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >BCD</TD>
-<TD >16</TD>
+<TD >dac</TD>
+<TD >12</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >20</TD>
+<TD >4</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -688,12 +656,12 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >COUNT0</TD>
-<TD >3</TD>
+<TD >rom|altsyncram_component|auto_generated</TD>
+<TD >11</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >16</TD>
+<TD >10</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -704,47 +672,47 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >DEL0</TD>
-<TD >16</TD>
-<TD >7</TD>
+<TD >rom</TD>
+<TD >11</TD>
 <TD >0</TD>
-<TD >7</TD>
-<TD >1</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >7</TD>
 <TD >0</TD>
 <TD >0</TD>
+<TD >10</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-</TR>
-<TR >
-<TD >LFSR0</TD>
-<TD >2</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >7</TD>
 <TD >0</TD>
 <TD >0</TD>
+</TR>
+<TR >
+<TD >fin_address</TD>
+<TD >11</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
+<TD >10</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-</TR>
-<TR >
-<TD >FSM</TD>
-<TD >3</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
-<TD >12</TD>
 <TD >0</TD>
 <TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_ADC</TD>
+<TD >4</TD>
+<TD >1</TD>
 <TD >0</TD>
+<TD >1</TD>
+<TD >13</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
 <TD >0</TD>
@@ -752,7 +720,7 @@
 <TD >0</TD>
 </TR>
 <TR >
-<TD >TICK0</TD>
+<TD >tick</TD>
 <TD >1</TD>
 <TD >0</TD>
 <TD >0</TD>
diff --git a/part_3/ex15/db/ex10.lpc.rdb b/part_3/ex15/db/ex10.lpc.rdb
new file mode 100755
index 0000000..3a7e294
--- /dev/null
+++ b/part_3/ex15/db/ex10.lpc.rdb
diff --git a/part_3/ex15/db/ex10.lpc.txt b/part_3/ex15/db/ex10.lpc.txt
new file mode 100755
index 0000000..53735ff
--- /dev/null
+++ b/part_3/ex15/db/ex10.lpc.txt
@@ -0,0 +1,51 @@
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                                                        ;
++------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                                                    ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; h4                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h3                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h2                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h1                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; h0                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A29                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A28                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A27                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A26                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A25                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A24                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A23                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A22                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A21                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A20                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A19                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A18                                                                      ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A17                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A16                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A15                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A14                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A13                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A12                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A11                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A10                                                                      ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A9                                                                       ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A8                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A7                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A6                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A5                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A4                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A3                                                                       ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A2                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd|A1                                                                       ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; bcd                                                                          ; 16    ; 3              ; 0            ; 3              ; 20     ; 3               ; 3             ; 3               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated ; 44    ; 0              ; 0            ; 0              ; 22     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated             ; 36    ; 0              ; 0            ; 0              ; 18     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; mult                                                                         ; 10    ; 0              ; 0            ; 0              ; 24     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; p                                                                            ; 12    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; dac                                                                          ; 12    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; rom|altsyncram_component|auto_generated                                      ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; rom                                                                          ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; fin_address                                                                  ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_ADC                                                                      ; 4     ; 1              ; 0            ; 1              ; 13     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; tick                                                                         ; 1     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_2/ex9_partially_working/db/ex9.map.ammdb b/part_3/ex15/db/ex10.map.ammdb
index 174eb00..174eb00 100755
--- a/part_2/ex9_partially_working/db/ex9.map.ammdb
+++ b/part_3/ex15/db/ex10.map.ammdb
diff --git a/part_3/ex15/db/ex10.map.bpm b/part_3/ex15/db/ex10.map.bpm
new file mode 100755
index 0000000..a8ad7e0
--- /dev/null
+++ b/part_3/ex15/db/ex10.map.bpm
diff --git a/part_3/ex15/db/ex10.map.cdb b/part_3/ex15/db/ex10.map.cdb
new file mode 100755
index 0000000..8e64e18
--- /dev/null
+++ b/part_3/ex15/db/ex10.map.cdb
diff --git a/part_3/ex15/db/ex10.map.hdb b/part_3/ex15/db/ex10.map.hdb
new file mode 100755
index 0000000..88b8603
--- /dev/null
+++ b/part_3/ex15/db/ex10.map.hdb
diff --git a/part_3/ex15/db/ex10.map.kpt b/part_3/ex15/db/ex10.map.kpt
new file mode 100755
index 0000000..d95769d
--- /dev/null
+++ b/part_3/ex15/db/ex10.map.kpt
diff --git a/part_2/ex9_partially_working/db/ex9.map.logdb b/part_3/ex15/db/ex10.map.logdb
index d45424f..d45424f 100755
--- a/part_2/ex9_partially_working/db/ex9.map.logdb
+++ b/part_3/ex15/db/ex10.map.logdb
diff --git a/part_3/ex15/db/ex10.map.qmsg b/part_3/ex15/db/ex10.map.qmsg
new file mode 100755
index 0000000..ad27429
--- /dev/null
+++ b/part_3/ex15/db/ex10.map.qmsg
@@ -0,0 +1,89 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480703466390 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480703466393 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 18:31:06 2016 " "Processing started: Fri Dec 02 18:31:06 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480703466393 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703466393 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703466393 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703466707 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703466740 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480703467011 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480703467012 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "verilog_files/spi2adc.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475597 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475597 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex15.v 1 1 " "Found 1 design units, including 1 entities, in source file ex15.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex15 " "Found entity 1: ex15" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475607 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475607 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475613 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475613 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475621 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475621 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475626 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475626 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475627 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475627 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475627 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475627 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475628 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475628 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475628 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475628 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475628 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475629 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475629 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475629 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475630 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475630 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475630 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475631 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475631 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475631 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475631 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475631 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475632 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475632 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475632 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475632 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475632 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475632 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703475632 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475633 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475633 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/rom.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "verilog_files/ROM.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475638 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475638 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_5000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_5000 " "Found entity 1: tick_5000" {  } { { "verilog_files/tick_5000.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/tick_5000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475644 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475644 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475651 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475651 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475657 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475657 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "const_mult.v 1 1 " "Found 1 design units, including 1 entities, in source file const_mult.v" { { "Info" "ISGN_ENTITY_NAME" "1 const_mult " "Found entity 1: const_mult" {  } { { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475661 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475661 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_offset.v 1 1 " "Found 1 design units, including 1 entities, in source file add_offset.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_offset " "Found entity 1: add_offset" {  } { { "add_offset.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/add_offset.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703475669 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703475669 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex15 " "Elaborating entity \"ex15\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480703476355 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tick_5000 tick_5000:tick " "Elaborating entity \"tick_5000\" for hierarchy \"tick_5000:tick\"" {  } { { "ex15.v" "tick" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 17 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476435 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "ex15.v" "SPI_ADC" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 30 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476461 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_offset add_offset:fin_address " "Elaborating entity \"add_offset\" for hierarchy \"add_offset:fin_address\"" {  } { { "ex15.v" "fin_address" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 32 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476479 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:rom " "Elaborating entity \"ROM\" for hierarchy \"ROM:rom\"" {  } { { "ex15.v" "rom" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 34 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476494 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ROM:rom\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/ROM.v" "altsyncram_component" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v" 82 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476588 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "ROM:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ROM:rom\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/ROM.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v" 82 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476598 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"ROM:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom_data/rom_data.mif " "Parameter \"init_file\" = \"./rom_data/rom_data.mif\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 10 " "Parameter \"width_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476598 ""}  } { { "verilog_files/ROM.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v" 82 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480703476598 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6ng1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6ng1 " "Found entity 1: altsyncram_6ng1" {  } { { "db/altsyncram_6ng1.tdf" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/altsyncram_6ng1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703476650 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703476650 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_6ng1 ROM:rom\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated " "Elaborating entity \"altsyncram_6ng1\" for hierarchy \"ROM:rom\|altsyncram:altsyncram_component\|altsyncram_6ng1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476651 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:dac " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:dac\"" {  } { { "ex15.v" "dac" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 36 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476664 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:p " "Elaborating entity \"pwm\" for hierarchy \"pwm:p\"" {  } { { "ex15.v" "p" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 37 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476674 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "const_mult const_mult:mult " "Elaborating entity \"const_mult\" for hierarchy \"const_mult:mult\"" {  } { { "ex15.v" "mult" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 39 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476689 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "const_mult.v" "lpm_mult_component" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476742 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476749 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "const_mult:mult\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"const_mult:mult\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476751 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476751 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476751 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 10 " "Parameter \"lpm_widtha\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476751 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 14 " "Parameter \"lpm_widthb\" = \"14\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476751 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 24 " "Parameter \"lpm_widthp\" = \"24\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480703476751 ""}  } { { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480703476751 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multcore const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core " "Elaborating entity \"multcore\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\"" {  } { { "lpm_mult.tdf" "mult_core" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476786 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476800 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder " "Elaborating entity \"mpar_add\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\"" {  } { { "multcore.tdf" "padder" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476819 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "multcore.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476828 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476860 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476870 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_d9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_d9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_d9h " "Found entity 1: add_sub_d9h" {  } { { "db/add_sub_d9h.tdf" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/add_sub_d9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703476914 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703476914 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_d9h const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_d9h:auto_generated " "Elaborating entity \"add_sub_d9h\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_d9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476915 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add " "Elaborating entity \"mpar_add\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\"" {  } { { "mpar_add.tdf" "sub_par_add" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476927 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476935 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476939 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476949 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_89h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_89h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_89h " "Found entity 1: add_sub_89h" {  } { { "db/add_sub_89h.tdf" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/add_sub_89h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703476997 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703476997 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_89h const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_89h:auto_generated " "Elaborating entity \"add_sub_89h\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_89h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703476998 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift const_mult:mult\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs " "Elaborating entity \"altshift\" for hierarchy \"const_mult:mult\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\"" {  } { { "lpm_mult.tdf" "external_latency_ffs" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703477027 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "const_mult:mult\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs const_mult:mult\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"const_mult:mult\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } } { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703477034 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 bin2bcd_16:bcd " "Elaborating entity \"bin2bcd_16\" for hierarchy \"bin2bcd_16:bcd\"" {  } { { "ex15.v" "bcd" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 41 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703477036 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd_16:bcd\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd_16:bcd\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703477049 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:h0\"" {  } { { "ex15.v" "h0" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 43 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703477063 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1480703478392 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[1\] GND " "Pin \"HEX4\[1\]\" is stuck at GND" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 5 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480703478555 "|ex15|HEX4[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480703478555 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480703478637 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Desktop/ex15/output_files/ex10.map.smsg " "Generated suppressed messages file /Desktop/ex15/output_files/ex10.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703479383 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480703479899 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703479899 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "352 " "Implemented 352 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480703480787 ""} { "Info" "ICUT_CUT_TM_OPINS" "43 " "Implemented 43 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480703480787 ""} { "Info" "ICUT_CUT_TM_LCELLS" "297 " "Implemented 297 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480703480787 ""} { "Info" "ICUT_CUT_TM_RAMS" "10 " "Implemented 10 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1480703480787 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480703480787 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "918 " "Peak virtual memory: 918 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480703480984 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 18:31:20 2016 " "Processing ended: Fri Dec 02 18:31:20 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480703480984 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480703480984 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480703480984 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703480984 ""}
diff --git a/part_3/ex15/db/ex10.map.rdb b/part_3/ex15/db/ex10.map.rdb
new file mode 100755
index 0000000..12813dc
--- /dev/null
+++ b/part_3/ex15/db/ex10.map.rdb
diff --git a/part_3/ex15/db/ex10.map_bb.cdb b/part_3/ex15/db/ex10.map_bb.cdb
new file mode 100755
index 0000000..ca45276
--- /dev/null
+++ b/part_3/ex15/db/ex10.map_bb.cdb
diff --git a/part_3/ex15/db/ex10.map_bb.hdb b/part_3/ex15/db/ex10.map_bb.hdb
new file mode 100755
index 0000000..406ae7e
--- /dev/null
+++ b/part_3/ex15/db/ex10.map_bb.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.map_bb.logdb b/part_3/ex15/db/ex10.map_bb.logdb
index d45424f..d45424f 100755
--- a/part_2/ex9_partially_working/db/ex9.map_bb.logdb
+++ b/part_3/ex15/db/ex10.map_bb.logdb
diff --git a/part_3/ex15/db/ex10.pre_map.hdb b/part_3/ex15/db/ex10.pre_map.hdb
new file mode 100755
index 0000000..c12f5cf
--- /dev/null
+++ b/part_3/ex15/db/ex10.pre_map.hdb
diff --git a/part_3/ex15/db/ex10.root_partition.map.reg_db.cdb b/part_3/ex15/db/ex10.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..cd94dd7
--- /dev/null
+++ b/part_3/ex15/db/ex10.root_partition.map.reg_db.cdb
diff --git a/part_3/ex15/db/ex10.routing.rdb b/part_3/ex15/db/ex10.routing.rdb
new file mode 100755
index 0000000..a26b278
--- /dev/null
+++ b/part_3/ex15/db/ex10.routing.rdb
diff --git a/part_3/ex15/db/ex10.rtlv.hdb b/part_3/ex15/db/ex10.rtlv.hdb
new file mode 100755
index 0000000..ba66e87
--- /dev/null
+++ b/part_3/ex15/db/ex10.rtlv.hdb
diff --git a/part_3/ex15/db/ex10.rtlv_sg.cdb b/part_3/ex15/db/ex10.rtlv_sg.cdb
new file mode 100755
index 0000000..6f9a2b2
--- /dev/null
+++ b/part_3/ex15/db/ex10.rtlv_sg.cdb
diff --git a/part_3/ex15/db/ex10.rtlv_sg_swap.cdb b/part_3/ex15/db/ex10.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..f1f9bda
--- /dev/null
+++ b/part_3/ex15/db/ex10.rtlv_sg_swap.cdb
diff --git a/part_2/ex9_partially_working/db/ex9.sld_design_entry.sci b/part_3/ex15/db/ex10.sld_design_entry.sci
index 92c1102..92c1102 100755
--- a/part_2/ex9_partially_working/db/ex9.sld_design_entry.sci
+++ b/part_3/ex15/db/ex10.sld_design_entry.sci
diff --git a/part_2/ex9_partially_working/db/ex9.sld_design_entry_dsc.sci b/part_3/ex15/db/ex10.sld_design_entry_dsc.sci
index 92c1102..92c1102 100755
--- a/part_2/ex9_partially_working/db/ex9.sld_design_entry_dsc.sci
+++ b/part_3/ex15/db/ex10.sld_design_entry_dsc.sci
diff --git a/part_2/ex9_partially_working/db/ex9.smart_action.txt b/part_3/ex15/db/ex10.smart_action.txt
index 437a63e..437a63e 100755
--- a/part_2/ex9_partially_working/db/ex9.smart_action.txt
+++ b/part_3/ex15/db/ex10.smart_action.txt
diff --git a/part_3/ex15/db/ex10.smp_dump.txt b/part_3/ex15/db/ex10.smp_dump.txt
new file mode 100755
index 0000000..9417198
--- /dev/null
+++ b/part_3/ex15/db/ex10.smp_dump.txt
@@ -0,0 +1,12 @@
+
+State Machine - |ex15|spi2dac:dac|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
+
+State Machine - |ex15|spi2adc:SPI_ADC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
diff --git a/part_3/ex15/db/ex10.sta.qmsg b/part_3/ex15/db/ex10.sta.qmsg
new file mode 100755
index 0000000..ee1290f
--- /dev/null
+++ b/part_3/ex15/db/ex10.sta.qmsg
@@ -0,0 +1,53 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480703547238 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480703547241 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 18:32:26 2016 " "Processing started: Fri Dec 02 18:32:26 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480703547241 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703547241 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex10 -c ex10 " "Command: quartus_sta ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703547241 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480703547366 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703547798 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548151 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548151 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548198 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548198 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex10.sdc " "Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548867 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548869 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz " "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480703548873 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480703548873 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name tick_5000:tick\|CLK_OUT tick_5000:tick\|CLK_OUT " "create_clock -period 1.000 -name tick_5000:tick\|CLK_OUT tick_5000:tick\|CLK_OUT" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480703548873 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2dac:dac\|clk_1MHz spi2dac:dac\|clk_1MHz " "create_clock -period 1.000 -name spi2dac:dac\|clk_1MHz spi2dac:dac\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480703548873 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548873 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548881 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548892 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480703548894 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480703548948 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480703548986 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703548986 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.923 " "Worst-case setup slack is -3.923" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549007 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549007 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.923             -65.134 spi2dac:dac\|clk_1MHz  " "   -3.923             -65.134 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549007 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.552            -146.301 CLOCK_50  " "   -3.552            -146.301 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549007 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.471             -56.704 spi2adc:SPI_ADC\|clk_1MHz  " "   -3.471             -56.704 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549007 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.452             -23.249 tick_5000:tick\|CLK_OUT  " "   -2.452             -23.249 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549007 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703549007 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -3.138 " "Worst-case hold slack is -3.138" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.138             -49.029 CLOCK_50  " "   -3.138             -49.029 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.136               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.136               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.788               0.000 spi2dac:dac\|clk_1MHz  " "    0.788               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549028 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.040               0.000 tick_5000:tick\|CLK_OUT  " "    1.040               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549028 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703549028 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703549049 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703549074 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -111.881 CLOCK_50  " "   -2.174            -111.881 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -19.666 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.394             -19.666 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -11.148 spi2dac:dac\|clk_1MHz  " "   -0.394             -11.148 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549098 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.310 tick_5000:tick\|CLK_OUT  " "   -0.394              -5.310 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703549098 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703549098 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480703549136 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703549178 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703550428 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703550638 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480703550671 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703550671 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.070 " "Worst-case setup slack is -4.070" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.070             -66.448 spi2dac:dac\|clk_1MHz  " "   -4.070             -66.448 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.578             -55.099 spi2adc:SPI_ADC\|clk_1MHz  " "   -3.578             -55.099 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.387            -140.679 CLOCK_50  " "   -3.387            -140.679 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.474             -23.507 tick_5000:tick\|CLK_OUT  " "   -2.474             -23.507 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550693 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703550693 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -3.236 " "Worst-case hold slack is -3.236" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.236             -51.012 CLOCK_50  " "   -3.236             -51.012 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.165               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.165               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.746               0.000 spi2dac:dac\|clk_1MHz  " "    0.746               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550723 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.041               0.000 tick_5000:tick\|CLK_OUT  " "    1.041               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550723 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703550723 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703550748 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703550770 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550791 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550791 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -108.567 CLOCK_50  " "   -2.174            -108.567 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550791 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -18.781 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.394             -18.781 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550791 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -11.064 spi2dac:dac\|clk_1MHz  " "   -0.394             -11.064 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550791 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -5.180 tick_5000:tick\|CLK_OUT  " "   -0.394              -5.180 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703550791 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703550791 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480703550834 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703551175 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703552327 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703552485 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480703552487 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703552487 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.728 " "Worst-case setup slack is -2.728" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.728             -72.515 CLOCK_50  " "   -2.728             -72.515 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.849             -29.471 spi2dac:dac\|clk_1MHz  " "   -1.849             -29.471 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.613             -27.548 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.613             -27.548 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552512 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.235             -10.973 tick_5000:tick\|CLK_OUT  " "   -1.235             -10.973 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552512 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703552512 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.759 " "Worst-case hold slack is -1.759" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.759             -28.407 CLOCK_50  " "   -1.759             -28.407 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.139               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.139               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.252               0.000 tick_5000:tick\|CLK_OUT  " "    0.252               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.381               0.000 spi2dac:dac\|clk_1MHz  " "    0.381               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552534 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703552534 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703552554 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703552587 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552608 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552608 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -100.071 CLOCK_50  " "   -2.174            -100.071 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552608 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.056               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.056               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552608 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.094               0.000 spi2dac:dac\|clk_1MHz  " "    0.094               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552608 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.109               0.000 tick_5000:tick\|CLK_OUT  " "    0.109               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703552608 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703552608 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480703552651 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703553100 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480703553102 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703553102 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.252 " "Worst-case setup slack is -2.252" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553119 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553119 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.252             -58.896 CLOCK_50  " "   -2.252             -58.896 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553119 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.809             -28.153 spi2dac:dac\|clk_1MHz  " "   -1.809             -28.153 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553119 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.551             -24.730 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.551             -24.730 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553119 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.105              -9.791 tick_5000:tick\|CLK_OUT  " "   -1.105              -9.791 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553119 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703553119 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.741 " "Worst-case hold slack is -1.741" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553137 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553137 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.741             -28.450 CLOCK_50  " "   -1.741             -28.450 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553137 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.139               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.139               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553137 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.222               0.000 tick_5000:tick\|CLK_OUT  " "    0.222               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553137 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.353               0.000 spi2dac:dac\|clk_1MHz  " "    0.353               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553137 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703553137 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703553159 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703553178 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553211 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553211 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174            -106.958 CLOCK_50  " "   -2.174            -106.958 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553211 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.085               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.085               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553211 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.107               0.000 spi2dac:dac\|clk_1MHz  " "    0.107               0.000 spi2dac:dac\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553211 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.130               0.000 tick_5000:tick\|CLK_OUT  " "    0.130               0.000 tick_5000:tick\|CLK_OUT " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480703553211 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703553211 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703555795 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703555803 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 7 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1247 " "Peak virtual memory: 1247 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480703556309 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 18:32:36 2016 " "Processing ended: Fri Dec 02 18:32:36 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480703556309 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480703556309 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480703556309 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480703556309 ""}
diff --git a/part_3/ex15/db/ex10.sta.rdb b/part_3/ex15/db/ex10.sta.rdb
new file mode 100755
index 0000000..b5bc128
--- /dev/null
+++ b/part_3/ex15/db/ex10.sta.rdb
diff --git a/part_3/ex15/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb b/part_3/ex15/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..019416c
--- /dev/null
+++ b/part_3/ex15/db/ex10.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_2/ex9_partially_working/db/ex9.tis_db_list.ddb b/part_3/ex15/db/ex10.tis_db_list.ddb
index 88225e8..88225e8 100755
--- a/part_2/ex9_partially_working/db/ex9.tis_db_list.ddb
+++ b/part_3/ex15/db/ex10.tis_db_list.ddb
diff --git a/part_3/ex15/db/ex10.tiscmp.fast_1100mv_0c.ddb b/part_3/ex15/db/ex10.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..ececd95
--- /dev/null
+++ b/part_3/ex15/db/ex10.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_3/ex15/db/ex10.tiscmp.fast_1100mv_85c.ddb b/part_3/ex15/db/ex10.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..29a2cc9
--- /dev/null
+++ b/part_3/ex15/db/ex10.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_3/ex15/db/ex10.tiscmp.slow_1100mv_0c.ddb b/part_3/ex15/db/ex10.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..9a23bd0
--- /dev/null
+++ b/part_3/ex15/db/ex10.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_3/ex15/db/ex10.tiscmp.slow_1100mv_85c.ddb b/part_3/ex15/db/ex10.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..fc5b34a
--- /dev/null
+++ b/part_3/ex15/db/ex10.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_3/ex15/db/ex10.tmw_info b/part_3/ex15/db/ex10.tmw_info
new file mode 100755
index 0000000..012e3a6
--- /dev/null
+++ b/part_3/ex15/db/ex10.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:01:38
+start_analysis_synthesis:s:00:00:19-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:52-start_full_compilation
+start_assembler:s:00:00:11-start_full_compilation
+start_timing_analyzer:s:00:00:12-start_full_compilation
+start_eda_netlist_writer:s:00:00:04-start_full_compilation
diff --git a/part_3/ex15/db/ex10.vpr.ammdb b/part_3/ex15/db/ex10.vpr.ammdb
new file mode 100755
index 0000000..7737a33
--- /dev/null
+++ b/part_3/ex15/db/ex10.vpr.ammdb
diff --git a/part_3/ex15/db/ex10_1.cmp.bpm b/part_3/ex15/db/ex10_1.cmp.bpm
new file mode 100755
index 0000000..62b0cff
--- /dev/null
+++ b/part_3/ex15/db/ex10_1.cmp.bpm
diff --git a/part_2/ex9_partially_working/db/ex9_partition_pins.json b/part_3/ex15/db/ex10_partition_pins.json
index 701d3b6..cdb7c64 100755
--- a/part_2/ex9_partially_working/db/ex9_partition_pins.json
+++ b/part_3/ex15/db/ex10_partition_pins.json
@@ -4,6 +4,38 @@
 			"name" : "Top",
 			"pins" : [
 				{
+					"name" : "DAC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_LD",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "PWM_OUT",
+					"strict" : false
+				},
+				{
 					"name" : "HEX0[0]",
 					"strict" : false
 				},
@@ -120,10 +152,6 @@
 					"strict" : false
 				},
 				{
-					"name" : "HEX4[1]",
-					"strict" : false
-				},
-				{
 					"name" : "HEX4[2]",
 					"strict" : false
 				},
@@ -144,55 +172,11 @@
 					"strict" : false
 				},
 				{
-					"name" : "LEDR[0]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[1]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[2]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[3]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[4]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[5]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[6]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[7]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[8]",
-					"strict" : false
-				},
-				{
-					"name" : "LEDR[9]",
-					"strict" : false
-				},
-				{
-					"name" : "KEY[0]",
-					"strict" : false
-				},
-				{
 					"name" : "CLOCK_50",
 					"strict" : false
 				},
 				{
-					"name" : "KEY[3]",
+					"name" : "ADC_SDO",
 					"strict" : false
 				}
 			]
diff --git a/part_3/ex15/db/prev_cmp_ex10.qmsg b/part_3/ex15/db/prev_cmp_ex10.qmsg
new file mode 100755
index 0000000..27bf1c5
--- /dev/null
+++ b/part_3/ex15/db/prev_cmp_ex10.qmsg
@@ -0,0 +1,59 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480703378519 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480703378523 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 18:29:38 2016 " "Processing started: Fri Dec 02 18:29:38 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480703378523 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703378523 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703378523 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703378851 ""}
+{ "Critical Warning" "WHDB_IGNORED_ASGN_INVALID_NODE_NAME" "IO_STANDARD LEDR\[3\]#============================================================ " "Ignored assignment IO_STANDARD which contains an invalid node name \"LEDR\[3\]#============================================================\"" {  } {  } 1 136021 "Ignored assignment %1!s! which contains an invalid node name \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703378880 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480703379224 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480703379224 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "verilog_files/spi2adc.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387728 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387728 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex15.v 1 1 " "Found 1 design units, including 1 entities, in source file ex15.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex15 " "Found entity 1: ex15" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387738 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387738 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/add3_ge5.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387745 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387745 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/hex_to_7seg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387773 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387773 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387787 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387788 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387788 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387788 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387788 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387788 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387791 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387791 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387791 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387791 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387791 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387791 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387791 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387791 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387793 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387793 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387793 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387793 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387793 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387794 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387794 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387794 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387796 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480703387796 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387797 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387797 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/rom.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/rom.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Found entity 1: ROM" {  } { { "verilog_files/ROM.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387808 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387808 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/tick_5000.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v" { { "Info" "ISGN_ENTITY_NAME" "1 tick_5000 " "Found entity 1: tick_5000" {  } { { "verilog_files/tick_5000.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/tick_5000.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387819 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387819 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387828 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387828 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387835 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387835 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "const_mult.v 1 1 " "Found 1 design units, including 1 entities, in source file const_mult.v" { { "Info" "ISGN_ENTITY_NAME" "1 const_mult " "Found entity 1: const_mult" {  } { { "const_mult.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387842 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387842 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_offset.v 1 1 " "Found 1 design units, including 1 entities, in source file add_offset.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_offset " "Found entity 1: add_offset" {  } { { "add_offset.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/add_offset.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480703387848 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387848 ""}
+{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ADC_SDI ex15.v(22) " "Verilog HDL Implicit Net warning at ex15.v(22): created implicit net for \"ADC_SDI\"" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 22 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703387848 ""}
+{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ADC_CS ex15.v(23) " "Verilog HDL Implicit Net warning at ex15.v(23): created implicit net for \"ADC_CS\"" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 23 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703387850 ""}
+{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ADC_SCK ex15.v(24) " "Verilog HDL Implicit Net warning at ex15.v(24): created implicit net for \"ADC_SCK\"" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 24 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703387850 ""}
+{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ADC_SDO ex15.v(25) " "Verilog HDL Implicit Net warning at ex15.v(25): created implicit net for \"ADC_SDO\"" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 25 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703387850 ""}
+{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "offset ex15.v(27) " "Verilog HDL Implicit Net warning at ex15.v(27): created implicit net for \"offset\"" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 27 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480703387850 ""}
+{ "Error" "EVRFX_VERI_PORT_UNDECLARED" "ADC_SDI ex15.v(1) " "Verilog HDL Module Declaration error at ex15.v(1): port \"ADC_SDI\" is not declared as port" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 1 0 0 } }  } 0 10158 "Verilog HDL Module Declaration error at %2!s!: port \"%1!s!\" is not declared as port" 0 0 "Analysis & Synthesis" 0 -1 1480703387850 ""}
+{ "Error" "EVRFX_VERI_PORT_UNDECLARED" "ADC_SCK ex15.v(1) " "Verilog HDL Module Declaration error at ex15.v(1): port \"ADC_SCK\" is not declared as port" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 1 0 0 } }  } 0 10158 "Verilog HDL Module Declaration error at %2!s!: port \"%1!s!\" is not declared as port" 0 0 "Analysis & Synthesis" 0 -1 1480703387850 ""}
+{ "Error" "EVRFX_VERI_PORT_UNDECLARED" "ADC_CS ex15.v(1) " "Verilog HDL Module Declaration error at ex15.v(1): port \"ADC_CS\" is not declared as port" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 1 0 0 } }  } 0 10158 "Verilog HDL Module Declaration error at %2!s!: port \"%1!s!\" is not declared as port" 0 0 "Analysis & Synthesis" 0 -1 1480703387851 ""}
+{ "Error" "EVRFX_VERI_PORT_UNDECLARED" "ADC_SDO ex15.v(1) " "Verilog HDL Module Declaration error at ex15.v(1): port \"ADC_SDO\" is not declared as port" {  } { { "ex15.v" "" { Text "//icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v" 1 0 0 } }  } 0 10158 "Verilog HDL Module Declaration error at %2!s!: port \"%1!s!\" is not declared as port" 0 0 "Analysis & Synthesis" 0 -1 1480703387851 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Desktop/ex15/output_files/ex10.map.smsg " "Generated suppressed messages file /Desktop/ex15/output_files/ex10.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703387906 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 4 s 8 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 4 errors, 8 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "842 " "Peak virtual memory: 842 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480703388136 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Dec 02 18:29:48 2016 " "Processing ended: Fri Dec 02 18:29:48 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480703388136 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480703388136 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480703388136 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703388136 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 6 s 8 s " "Quartus Prime Full Compilation was unsuccessful. 6 errors, 8 warnings" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480703389248 ""}
diff --git a/part_2/ex9_final/ex9.qpf b/part_3/ex15/ex10.qpf
index 28b4ce8..e7dc424 100755
--- a/part_2/ex9_final/ex9.qpf
+++ b/part_3/ex15/ex10.qpf
@@ -19,13 +19,13 @@
 #
 # Quartus Prime
 # Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
+# Date created = 09:17:00  November 29, 2016
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "16.0"
-DATE = "10:28:00  November 25, 2016"
+DATE = "09:17:00  November 29, 2016"
 
 # Revisions
 
-PROJECT_REVISION = "ex9"
+PROJECT_REVISION = "ex10"
diff --git a/part_3/ex15/ex10.qsf b/part_3/ex15/ex10.qsf
new file mode 100755
index 0000000..3b80eb9
--- /dev/null
+++ b/part_3/ex15/ex10.qsf
@@ -0,0 +1,328 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition#============================================================
+# CLOCK
+#============================================================
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+
+
+
+#============================================================
+# HEX0
+#============================================================
+
+#============================================================
+# HEX1
+#============================================================
+
+#============================================================
+# HEX2
+#============================================================
+
+#============================================================
+# HEX3
+#============================================================
+
+#============================================================
+# HEX4
+#============================================================
+
+#============================================================
+# HEX5
+#============================================================
+
+#============================================================
+# KEY
+#============================================================
+
+#============================================================
+# LEDR
+#============================================================
+
+#============================================================
+# SW
+#============================================================
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
+# Date created = 09:17:00  November 29, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ex10_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex15
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:17:00  NOVEMBER 29, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to "LEDR[3]#============================================================"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_global_assignment -name VERILOG_FILE verilog_files/spi2adc.v
+set_global_assignment -name VERILOG_FILE ex15.v
+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
+set_global_assignment -name QIP_FILE verilog_files/ROM.qip
+set_global_assignment -name VERILOG_FILE verilog_files/ROM.v
+set_global_assignment -name VERILOG_FILE verilog_files/tick_5000.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2dac.v
+set_global_assignment -name VERILOG_FILE verilog_files/pwm.v
+set_global_assignment -name QIP_FILE const_mult.qip
+set_global_assignment -name VERILOG_FILE add_offset.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/part_3/ex15/ex10.qws b/part_3/ex15/ex10.qws
new file mode 100755
index 0000000..be35acb
--- /dev/null
+++ b/part_3/ex15/ex10.qws
diff --git a/part_3/ex15/ex10.v.bak b/part_3/ex15/ex10.v.bak
new file mode 100755
index 0000000..8b13789
--- /dev/null
+++ b/part_3/ex15/ex10.v.bak
@@ -0,0 +1 @@
+
diff --git a/part_2/ex8/ex8_assignment_defaults.qdf b/part_3/ex15/ex10_assignment_defaults.qdf
index 3dade63..7f6e4ac 100644..100755
--- a/part_2/ex8/ex8_assignment_defaults.qdf
+++ b/part_3/ex15/ex10_assignment_defaults.qdf
@@ -1,795 +1,799 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2016  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Intel and sold by Intel or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-# Date created = 20:04:49  December 11, 2016
-#
-# -------------------------------------------------------------------------- #
-#
-# Note:
-#
-# 1) Do not modify this file. This file was generated
-#    automatically by the Quartus Prime software and is used
-#    to preserve global assignments across Quartus Prime versions.
-#
-# -------------------------------------------------------------------------- #
-
-set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
-set_global_assignment -name IP_COMPONENT_INTERNAL Off
-set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
-set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
-set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
-set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
-set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
-set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
-set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
-set_global_assignment -name HC_OUTPUT_DIR hc_output
-set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
-set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
-set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
-set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
-set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
-set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
-set_global_assignment -name REVISION_TYPE Base -family "Arria V"
-set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
-set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
-set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
-set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
-set_global_assignment -name DO_COMBINED_ANALYSIS Off
-set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
-set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
-set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
-set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
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-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
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-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
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-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
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-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
-set_global_assignment -name OPTIMIZATION_MODE Balanced
-set_global_assignment -name ALLOW_REGISTER_MERGING On
-set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
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-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
-set_global_assignment -name MUX_RESTRUCTURE Auto
-set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
-set_global_assignment -name ENABLE_IP_DEBUG Off
-set_global_assignment -name SAVE_DISK_SPACE On
-set_global_assignment -name OCP_HW_EVAL -value OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE Any
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name TRUE_WYSIWYG_FLOW Off
-set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
-set_global_assignment -name STATE_MACHINE_PROCESSING Auto
-set_global_assignment -name SAFE_STATE_MACHINE Off
-set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
-set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
-set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
-set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
-set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
-set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
-set_global_assignment -name PARALLEL_SYNTHESIS On
-set_global_assignment -name DSP_BLOCK_BALANCING Auto
-set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
-set_global_assignment -name NOT_GATE_PUSH_BACK On
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
-set_global_assignment -name IGNORE_CARRY_BUFFERS Off
-set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
-set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_LCELL_BUFFERS Off
-set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
-set_global_assignment -name IGNORE_SOFT_BUFFERS On
-set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
-set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
-set_global_assignment -name AUTO_GLOBAL_OE_MAX On
-set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
-set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
-set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name ALLOW_XOR_GATE_USAGE On
-set_global_assignment -name AUTO_LCELL_INSERTION On
-set_global_assignment -name CARRY_CHAIN_LENGTH 48
-set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
-set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name CASCADE_CHAIN_LENGTH 2
-set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
-set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
-set_global_assignment -name AUTO_CARRY_CHAINS On
-set_global_assignment -name AUTO_CASCADE_CHAINS On
-set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
-set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
-set_global_assignment -name AUTO_ROM_RECOGNITION On
-set_global_assignment -name AUTO_RAM_RECOGNITION On
-set_global_assignment -name AUTO_DSP_RECOGNITION On
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
-set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
-set_global_assignment -name STRICT_RAM_RECOGNITION Off
-set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
-set_global_assignment -name FORCE_SYNCH_CLEAR Off
-set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
-set_global_assignment -name AUTO_RESOURCE_SHARING Off
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name MAX7000_FANIN_PER_CELL 100
-set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
-set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
-set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
-set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
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-set_global_assignment -name REPORT_PARAMETER_SETTINGS On
-set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
-set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
-set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
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-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
-set_global_assignment -name HDL_MESSAGE_LEVEL Level2
-set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
-set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
-set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
-set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
-set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
-set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
-set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
-set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
-set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
-set_global_assignment -name BLOCK_DESIGN_NAMING Auto
-set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
-set_global_assignment -name SYNTHESIS_EFFORT Auto
-set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
-set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
-set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
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-set_global_assignment -name MAX_LABS "-1 (Unlimited)"
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-set_global_assignment -name PRPOF_ID Off
-set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
-set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
-set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
-set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
-set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
-set_global_assignment -name AUTO_MERGE_PLLS On
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-set_global_assignment -name TXPMA_SLEW_RATE Low
-set_global_assignment -name ADCE_ENABLED Auto
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
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-set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
-set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
-set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
-set_global_assignment -name ENABLE_NCEO_OUTPUT Off
-set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
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-set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
-set_global_assignment -name STRATIX_UPDATE_MODE Standard
-set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
-set_global_assignment -name CVP_MODE Off
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
-set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
-set_global_assignment -name USE_CONF_DONE AUTO
-set_global_assignment -name USE_PWRMGT_SCL AUTO
-set_global_assignment -name USE_PWRMGT_SDA AUTO
-set_global_assignment -name USE_PWRMGT_ALERT AUTO
-set_global_assignment -name USE_INIT_DONE AUTO
-set_global_assignment -name USE_CVP_CONFDONE AUTO
-set_global_assignment -name USE_SEU_ERROR AUTO
-set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name USER_START_UP_CLOCK Off
-set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
-set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
-set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
-set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
-set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
-set_global_assignment -name ENABLE_VREFA_PIN Off
-set_global_assignment -name ENABLE_VREFB_PIN Off
-set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
-set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
-set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
-set_global_assignment -name INIT_DONE_OPEN_DRAIN On
-set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name ENABLE_CONFIGURATION_PINS On
-set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
-set_global_assignment -name ENABLE_NCE_PIN Off
-set_global_assignment -name ENABLE_BOOT_SEL_PIN On
-set_global_assignment -name CRC_ERROR_CHECKING Off
-set_global_assignment -name INTERNAL_SCRUBBING Off
-set_global_assignment -name PR_ERROR_OPEN_DRAIN On
-set_global_assignment -name PR_READY_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CVP_CONFDONE Off
-set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
-set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
-set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
-set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
-set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
-set_global_assignment -name OPTIMIZE_SSN Off
-set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
-set_global_assignment -name ECO_OPTIMIZE_TIMING Off
-set_global_assignment -name ECO_REGENERATE_REPORT Off
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
-set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
-set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
-set_global_assignment -name SEED 1
-set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
-set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
-set_global_assignment -name SLOW_SLEW_RATE Off
-set_global_assignment -name PCI_IO Off
-set_global_assignment -name TURBO_BIT On
-set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
-set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
-set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
-set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
-set_global_assignment -name NORMAL_LCELL_INSERT On
-set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
-set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
-set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
-set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
-set_global_assignment -name AUTO_TURBO_BIT ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
-set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
-set_global_assignment -name FITTER_EFFORT "Auto Fit"
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
-set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
-set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK On
-set_global_assignment -name AUTO_GLOBAL_OE On
-set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
-set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
-set_global_assignment -name ENABLE_HOLD_BACK_OFF On
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
-set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
-set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
-set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
-set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
-set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
-set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
-set_global_assignment -name PR_DONE_OPEN_DRAIN On
-set_global_assignment -name NCEO_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
-set_global_assignment -name ENABLE_PR_PINS Off
-set_global_assignment -name RESERVE_PR_PINS Off
-set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
-set_global_assignment -name PR_PINS_OPEN_DRAIN Off
-set_global_assignment -name CLAMPING_DIODE Off
-set_global_assignment -name TRI_STATE_SPI_PINS Off
-set_global_assignment -name UNUSED_TSD_PINS_GND Off
-set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
-set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
-set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
-set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
-set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
-set_global_assignment -name SEU_FIT_REPORT Off
-set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
-set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
-set_global_assignment -name COMPRESSION_MODE Off
-set_global_assignment -name CLOCK_SOURCE Internal
-set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
-set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
-set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
-set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
-set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
-set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
-set_global_assignment -name SECURITY_BIT Off
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
-set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
-set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
-set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
-set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
-set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
-set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
-set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
-set_global_assignment -name GENERATE_TTF_FILE Off
-set_global_assignment -name GENERATE_RBF_FILE Off
-set_global_assignment -name GENERATE_HEX_FILE Off
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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 10:58:36  November 29, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus Prime software and is used
+#    to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
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+set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY -value "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial x1" -family "Stratix 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS Off -family "Stratix 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name ENABLE_ED_CRC_CHECK On -family "Stratix 10"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ -family "Stratix 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off
+set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS OFF -family "Stratix 10"
+set_global_assignment -name HYPER_AWARE_OPTIMIZE_REGISTER_CHAINS ON -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000001
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000010
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000100
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0001000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0010000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/part_3/ex15/ex10_nativelink_simulation.rpt b/part_3/ex15/ex10_nativelink_simulation.rpt
new file mode 100755
index 0000000..91c988e
--- /dev/null
+++ b/part_3/ex15/ex10_nativelink_simulation.rpt
@@ -0,0 +1,22 @@
+Info: Start Nativelink Simulation process
+Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
+
+========= EDA Simulation Settings =====================
+
+Sim Mode              :  RTL
+Family                :  cyclonev
+Quartus root          :  c:/altera/16.0/quartus/bin64/
+Quartus sim root      :  c:/altera/16.0/quartus/eda/sim_lib
+Simulation Tool       :  modelsim-altera
+Simulation Language   :  verilog
+Simulation Mode       :  GUI
+Sim Output File       :  
+Sim SDF file          :  
+Sim dir               :  simulation\modelsim
+
+=======================================================
+
+Info: Starting NativeLink simulation with ModelSim-Altera software
+Sourced NativeLink script c:/altera/16.0/quartus/common/tcl/internal/nativelink/modelsim.tcl
+Warning: File ex10_run_msim_rtl_verilog.do already exists - backing up current file as ex10_run_msim_rtl_verilog.do.bak
+Info: Spawning ModelSim-Altera Simulation software 
diff --git a/part_3/ex15/ex14.v.bak b/part_3/ex15/ex14.v.bak
new file mode 100755
index 0000000..eaec90d
--- /dev/null
+++ b/part_3/ex15/ex14.v.bak
@@ -0,0 +1,18 @@
+module ex13(CLOCK_50, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT);
+
+	input CLOCK_50;
+	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT;
+	
+	wire load;
+	wire [9:0] data, count;
+	
+	tick_5000 t(CLOCK_50, load);
+	
+	counter_10 c(CLOCK_50, load, count);
+	
+	ROM r(count, CLOCK_50, data);
+	
+	spi2dac s(CLOCK_50, data, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
+	pwm p(CLOCK_50, data, load, PWM_OUT);
+	
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex15/ex15.v b/part_3/ex15/ex15.v
new file mode 100755
index 0000000..18ff51c
--- /dev/null
+++ b/part_3/ex15/ex15.v
@@ -0,0 +1,50 @@
+module ex15(CLOCK_50, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT, HEX0, HEX1, HEX2, HEX3, HEX4);
+
+	input CLOCK_50;
+	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT;
+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
+	
+	output 		ADC_SDI;			//Serial data out to SDI of the ADC
+	output 		ADC_SCK;		// ADC Clock signal
+	output		ADC_CS;			//Chip select to the ADC, low active
+	input 		ADC_SDO;			//Converted serial data from ADC	
+	
+	wire load;
+	wire [9:0] address, data;
+	wire [23:0] freq_tmp;
+	wire [19:0] freq_fin;
+	
+	tick_5000 tick(CLOCK_50, load);
+	
+	wire [9:0] 	data_in;	
+	
+	spi2adc SPI_ADC (										
+		.sysclk (CLOCK_50), 										
+		.channel (1'b0), 											
+		.start (load),
+		.data_from_adc (data_in),
+		.data_valid (),
+		.sdata_to_adc (ADC_SDI),
+		.adc_cs (ADC_CS),
+		.adc_sck (ADC_SCK),
+		.sdata_from_adc (ADC_SDO));	
+	
+	add_offset fin_address(data_in, load, address);
+	
+	ROM rom(address, CLOCK_50, data);
+	
+	spi2dac dac(CLOCK_50, data, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
+	pwm p(CLOCK_50, data, load, PWM_OUT);
+	
+	const_mult mult(data_in, freq_tmp);
+	
+	bin2bcd_16 bcd(freq_tmp[23:10], freq_fin[3:0], freq_fin[7:4], freq_fin[11:8], freq_fin[15:12], freq_fin[19:16]);
+	
+	hex_to_7seg h0(HEX0, freq_fin[3:0]);	
+	hex_to_7seg h1(HEX1, freq_fin[7:4]);
+	hex_to_7seg h2(HEX2, freq_fin[11:8]);
+	hex_to_7seg h3(HEX3, freq_fin[15:12]);
+	hex_to_7seg h4(HEX4, freq_fin[19:16]);
+	
+	
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex15/ex15.v.bak b/part_3/ex15/ex15.v.bak
new file mode 100755
index 0000000..1d6e721
--- /dev/null
+++ b/part_3/ex15/ex15.v.bak
@@ -0,0 +1,33 @@
+module ex14(CLOCK_50, KEY, DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT, HEX0, HEX1, HEX2, HEX3, HEX4);
+
+	input CLOCK_50;
+	input [9:0] KEY;
+	output DAC_CS, DAC_SDI, DAC_LD, DAC_SCK, PWM_OUT;
+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
+	
+	wire load;
+	wire [9:0] data;
+	wire [9:0] address;
+	wire [23:0] freq_tmp;
+	wire [19:0] freq_fin;
+	
+	tick_5000 tick(CLOCK_50, load);
+	
+	add_offset fin_address(KEY, load, address);
+	
+	ROM rom(address, CLOCK_50, data);
+	
+	spi2dac dac(CLOCK_50, data, load, DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
+	pwm p(CLOCK_50, data, load, PWM_OUT);
+	
+	const_mult mult(KEY, freq_tmp);
+	
+	bin2bcd_16 bcd(freq_tmp[23:10], freq_fin[19:16], freq_fin[15:12], freq_fin[11:8], freq_fin[7:4], freq_fin[3:0]);
+	
+	hex_to_7seg h0(HEX0, freq_fin[3:0]);	
+	hex_to_7seg h1(HEX1, freq_fin[7:4]);
+	hex_to_7seg h2(HEX2, freq_fin[11:8]);
+	hex_to_7seg h3(HEX3, freq_fin[15:12]);
+	hex_to_7seg h4(HEX4, freq_fin[19:16]);
+	
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex15/greybox_tmp/cbx_args.txt b/part_3/ex15/greybox_tmp/cbx_args.txt
new file mode 100755
index 0000000..0525819
--- /dev/null
+++ b/part_3/ex15/greybox_tmp/cbx_args.txt
@@ -0,0 +1,10 @@
+LPM_HINT=INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5
+LPM_REPRESENTATION=UNSIGNED
+LPM_TYPE=LPM_MULT
+LPM_WIDTHA=10
+LPM_WIDTHB=14
+LPM_WIDTHP=24
+DEVICE_FAMILY="Cyclone V"
+dataa
+datab
+result
diff --git a/part_3/ex15/greybox_tmp/greybox_tmp/mg1tj.v b/part_3/ex15/greybox_tmp/greybox_tmp/mg1tj.v
new file mode 100755
index 0000000..c7690aa
--- /dev/null
+++ b/part_3/ex15/greybox_tmp/greybox_tmp/mg1tj.v
@@ -0,0 +1,56 @@
+//lpm_mult CBX_SINGLE_OUTPUT_FILE="ON" LPM_HINT="INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5" LPM_REPRESENTATION="UNSIGNED" LPM_TYPE="LPM_MULT" LPM_WIDTHA=10 LPM_WIDTHB=14 LPM_WIDTHP=24 LPM_WIDTHS=1 dataa datab result
+//VERSION_BEGIN 16.1 cbx_mgl 2016:10:24:15:05:03:SJ cbx_stratixii 2016:10:24:15:04:16:SJ cbx_util_mgl 2016:10:24:15:04:16:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2016  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel MegaCore Function License Agreement, or other 
+//  applicable license agreement, including, without limitation, 
+//  that your use is for the sole purpose of programming logic 
+//  devices manufactured by Intel and sold by Intel or its 
+//  authorized distributors.  Please refer to the applicable 
+//  agreement for further details.
+
+
+
+//synthesis_resources = lpm_mult 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  mg1tj
+	( 
+	dataa,
+	datab,
+	result) /* synthesis synthesis_clearbox=1 */;
+	input   [9:0]  dataa;
+	input   [13:0]  datab;
+	output   [23:0]  result;
+
+	wire  [23:0]   wire_mgl_prim1_result;
+
+	lpm_mult   mgl_prim1
+	( 
+	.dataa(dataa),
+	.datab(datab),
+	.result(wire_mgl_prim1_result));
+	defparam
+		mgl_prim1.lpm_representation = "UNSIGNED",
+		mgl_prim1.lpm_type = "LPM_MULT",
+		mgl_prim1.lpm_widtha = 10,
+		mgl_prim1.lpm_widthb = 14,
+		mgl_prim1.lpm_widthp = 24,
+		mgl_prim1.lpm_widths = 1,
+		mgl_prim1.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
+	assign
+		result = wire_mgl_prim1_result;
+endmodule //mg1tj
+//VALID FILE
diff --git a/part_2/ex9_partially_working/incremental_db/README b/part_3/ex15/incremental_db/README
index 6191fbe..6191fbe 100755
--- a/part_2/ex9_partially_working/incremental_db/README
+++ b/part_3/ex15/incremental_db/README
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.db_info b/part_3/ex15/incremental_db/compiled_partitions/ex10.db_info
index f84b742..75e945b 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.db_info
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.db_info
@@ -1,3 +1,3 @@
 Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 Version_Index = 402707200
-Creation_Time = Fri Nov 25 10:41:49 2016
+Creation_Time = Fri Dec 02 17:48:58 2016
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.ammdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.ammdb
new file mode 100755
index 0000000..b97571f
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.ammdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.cdb
new file mode 100755
index 0000000..260530a
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.dfp
index b1c67d6..b1c67d6 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.dfp
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.dfp
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..9be2d85
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.hdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..a720980
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.sig
index af9b8e9..af9b8e9 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.hbdb.sig
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hbdb.sig
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hdb
new file mode 100755
index 0000000..40cddca
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.logdb
index d45424f..d45424f 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.cmp.logdb
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.logdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.rcfdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..bc1bd94
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.cmp.rcfdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.cdb
new file mode 100755
index 0000000..54b626c
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.dpi b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.dpi
new file mode 100755
index 0000000..e5644b2
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.dpi
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..69b09a0
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.cdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hb_info
index 8210c55..8210c55 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.hb_info
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hb_info
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..c87b267
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.hdb
diff --git a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.sig
index af9b8e9..af9b8e9 100755
--- a/part_2/ex9_partially_working/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.sig
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hbdb.sig
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hdb
new file mode 100755
index 0000000..0eb8f4f
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.hdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.kpt b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.kpt
new file mode 100755
index 0000000..c15d978
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.kpt
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.olf.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.olf.cdb
new file mode 100755
index 0000000..50af8b3
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.olf.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.olm.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.olm.cdb
new file mode 100755
index 0000000..cf375cc
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.olm.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.oln.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.oln.cdb
new file mode 100755
index 0000000..cc55b6f
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.oln.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.opi b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.opi
@@ -0,0 +1 @@
+1
+\ No newline at end of file
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orf.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orf.cdb
new file mode 100755
index 0000000..6673dce
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orf.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orm.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orm.cdb
new file mode 100755
index 0000000..0ed3ec5
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orm.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orn.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orn.cdb
new file mode 100755
index 0000000..729a8f6
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.map.orn.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.cdb
new file mode 100755
index 0000000..54b626c
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..69b09a0
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.cdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.hdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..c87b267
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hbdb.hdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hdb
new file mode 100755
index 0000000..0eb8f4f
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.hdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.kpt b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.kpt
new file mode 100755
index 0000000..c15d978
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.root_partition.rrp.kpt
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.rrp.hdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.rrp.hdb
new file mode 100755
index 0000000..a4f3bd1
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.rrp.hdb
diff --git a/part_3/ex15/incremental_db/compiled_partitions/ex10.rrs.cdb b/part_3/ex15/incremental_db/compiled_partitions/ex10.rrs.cdb
new file mode 100755
index 0000000..3699b3f
--- /dev/null
+++ b/part_3/ex15/incremental_db/compiled_partitions/ex10.rrs.cdb
diff --git a/part_3/ex15/output_files/ex10.asm.rpt b/part_3/ex15/output_files/ex10.asm.rpt
new file mode 100755
index 0000000..8033662
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex10
+Fri Dec 02 18:32:25 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: /Desktop/ex15/output_files/ex10.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Dec 02 18:32:25 2016 ;
+; Revision Name         ; ex10                                  ;
+; Top-level Entity Name ; ex15                                  ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++-------------------------------------+
+; Assembler Generated Files           ;
++-------------------------------------+
+; File Name                           ;
++-------------------------------------+
+; /Desktop/ex15/output_files/ex10.sof ;
++-------------------------------------+
+
+
++---------------------------------------------------------------+
+; Assembler Device Options: /Desktop/ex15/output_files/ex10.sof ;
++----------------+----------------------------------------------+
+; Option         ; Setting                                      ;
++----------------+----------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                 ;
+; JTAG usercode  ; 0x00B6F086                                   ;
+; Checksum       ; 0x00B6F086                                   ;
++----------------+----------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 18:32:15 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 898 megabytes
+    Info: Processing ended: Fri Dec 02 18:32:25 2016
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:07
+
+
diff --git a/part_3/ex15/output_files/ex10.done b/part_3/ex15/output_files/ex10.done
new file mode 100755
index 0000000..8409c75
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.done
@@ -0,0 +1 @@
+Fri Dec 02 18:32:42 2016
diff --git a/part_3/ex15/output_files/ex10.eda.rpt b/part_3/ex15/output_files/ex10.eda.rpt
new file mode 100755
index 0000000..551529f
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.eda.rpt
@@ -0,0 +1,96 @@
+EDA Netlist Writer report for ex10
+Fri Dec 02 18:32:41 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Dec 02 18:32:41 2016 ;
+; Revision Name             ; ex10                                  ;
+; Top-level Entity Name     ; ex15                                  ;
+; Family                    ; Cyclone V                             ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                           ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option                                                                                            ; Setting                   ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
+; Generate functional simulation netlist                                                            ; Off                       ;
+; Time scale                                                                                        ; 1 ps                      ;
+; Truncate long hierarchy paths                                                                     ; Off                       ;
+; Map illegal HDL characters                                                                        ; Off                       ;
+; Flatten buses into individual nodes                                                               ; Off                       ;
+; Maintain hierarchy                                                                                ; Off                       ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
+; Enable glitch filtering                                                                           ; Off                       ;
+; Do not write top level VHDL entity                                                                ; Off                       ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
+; Architecture name in VHDL output netlist                                                          ; structure                 ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++-------------------------------------------+
+; Simulation Generated Files                ;
++-------------------------------------------+
+; Generated Files                           ;
++-------------------------------------------+
+; /Desktop/ex15/simulation/modelsim/ex10.vo ;
++-------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 18:32:39 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
+Info (204019): Generated file ex10.vo in folder "/Desktop/ex15/simulation/modelsim/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
+    Info: Peak virtual memory: 816 megabytes
+    Info: Processing ended: Fri Dec 02 18:32:41 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/part_2/ex9_partially_working/output_files/ex9.fit.rpt b/part_3/ex15/output_files/ex10.fit.rpt
index d5b5f11..fe01100 100755
--- a/part_2/ex9_partially_working/output_files/ex9.fit.rpt
+++ b/part_3/ex15/output_files/ex10.fit.rpt
@@ -1,5 +1,5 @@
-Fitter report for ex9
-Fri Nov 25 11:27:54 2016
+Fitter report for ex10
+Fri Dec 02 18:32:08 2016
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 
 
@@ -28,16 +28,17 @@ Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
  20. Pad To Core Delay Chain Fanout
  21. Control Signals
  22. Global & Other Fast Signals
- 23. Routing Usage Summary
- 24. I/O Rules Summary
- 25. I/O Rules Details
- 26. I/O Rules Matrix
- 27. Fitter Device Options
- 28. Operating Settings and Conditions
- 29. Estimated Delay Added for Hold Timing Summary
- 30. Estimated Delay Added for Hold Timing Details
- 31. Fitter Messages
- 32. Fitter Suppressed Messages
+ 23. Fitter RAM Summary
+ 24. Routing Usage Summary
+ 25. I/O Rules Summary
+ 26. I/O Rules Details
+ 27. I/O Rules Matrix
+ 28. Fitter Device Options
+ 29. Operating Settings and Conditions
+ 30. Estimated Delay Added for Hold Timing Summary
+ 31. Estimated Delay Added for Hold Timing Details
+ 32. Fitter Messages
+ 33. Fitter Suppressed Messages
 
 
 
@@ -64,19 +65,19 @@ agreement for further details.
 +-----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                    ;
 +---------------------------------+-------------------------------------------------+
-; Fitter Status                   ; Successful - Fri Nov 25 11:27:54 2016           ;
+; Fitter Status                   ; Successful - Fri Dec 02 18:32:08 2016           ;
 ; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
+; Revision Name                   ; ex10                                            ;
+; Top-level Entity Name           ; ex15                                            ;
 ; Family                          ; Cyclone V                                       ;
 ; Device                          ; 5CSEMA5F31C6                                    ;
 ; Timing Models                   ; Final                                           ;
-; Logic utilization (in ALMs)     ; 154 / 32,070 ( < 1 % )                          ;
-; Total registers                 ; 95                                              ;
-; Total pins                      ; 57 / 457 ( 12 % )                               ;
+; Logic utilization (in ALMs)     ; 146 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 130                                             ;
+; Total pins                      ; 45 / 457 ( 10 % )                               ;
 ; Total virtual pins              ; 0                                               ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
-; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;
+; Total block memory bits         ; 10,240 / 4,065,280 ( < 1 % )                    ;
+; Total RAM Blocks                ; 1 / 397 ( < 1 % )                               ;
 ; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
 ; Total HSSI RX PCSs              ; 0                                               ;
 ; Total HSSI PMA RX Deserializers ; 0                                               ;
@@ -160,8 +161,8 @@ agreement for further details.
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
 ;     Processor 2            ;   0.7%      ;
-;     Processor 3            ;   0.7%      ;
-;     Processor 4            ;   0.7%      ;
+;     Processor 3            ;   0.6%      ;
+;     Processor 4            ;   0.6%      ;
 +----------------------------+-------------+
 
 
@@ -170,6 +171,14 @@ agreement for further details.
 +----------+--------------------------------------+
 ; Pin Name ; Reason                               ;
 +----------+--------------------------------------+
+; DAC_CS   ; Missing drive strength and slew rate ;
+; DAC_SDI  ; Missing drive strength and slew rate ;
+; DAC_LD   ; Missing drive strength and slew rate ;
+; DAC_SCK  ; Missing drive strength and slew rate ;
+; ADC_SDI  ; Missing drive strength and slew rate ;
+; ADC_SCK  ; Missing drive strength and slew rate ;
+; ADC_CS   ; Missing drive strength and slew rate ;
+; PWM_OUT  ; Missing drive strength and slew rate ;
 ; HEX0[0]  ; Missing drive strength and slew rate ;
 ; HEX0[1]  ; Missing drive strength and slew rate ;
 ; HEX0[2]  ; Missing drive strength and slew rate ;
@@ -205,43 +214,36 @@ agreement for further details.
 ; HEX4[4]  ; Missing drive strength and slew rate ;
 ; HEX4[5]  ; Missing drive strength and slew rate ;
 ; HEX4[6]  ; Missing drive strength and slew rate ;
-; HEX5[0]  ; Missing drive strength and slew rate ;
-; HEX5[1]  ; Missing drive strength and slew rate ;
-; HEX5[2]  ; Missing drive strength and slew rate ;
-; HEX5[3]  ; Missing drive strength and slew rate ;
-; HEX5[4]  ; Missing drive strength and slew rate ;
-; HEX5[5]  ; Missing drive strength and slew rate ;
-; HEX5[6]  ; Missing drive strength and slew rate ;
-; LEDR[0]  ; Missing drive strength and slew rate ;
-; LEDR[1]  ; Missing drive strength and slew rate ;
-; LEDR[2]  ; Missing drive strength and slew rate ;
-; LEDR[3]  ; Missing drive strength and slew rate ;
-; LEDR[4]  ; Missing drive strength and slew rate ;
-; LEDR[5]  ; Missing drive strength and slew rate ;
-; LEDR[6]  ; Missing drive strength and slew rate ;
-; LEDR[7]  ; Missing drive strength and slew rate ;
-; LEDR[8]  ; Missing drive strength and slew rate ;
-; LEDR[9]  ; Missing drive strength and slew rate ;
 +----------+--------------------------------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations                                                                                                                                                                                                            ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;
-; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[2]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[6]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[6]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[7]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[7]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[9]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[9]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[14]~DUPLICATE ;                  ;                       ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                                ;
++------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------+------------------+-----------------------+
+; Node                         ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                       ; Destination Port ; Destination Port Name ;
++------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0        ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                        ;                  ;                       ;
+; pwm:p|count[0]               ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; pwm:p|count[0]~DUPLICATE               ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[0]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[0]~DUPLICATE       ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[1]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[1]~DUPLICATE       ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[2]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[2]~DUPLICATE       ;                  ;                       ;
+; spi2adc:SPI_ADC|shift_reg[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|shift_reg[1]~DUPLICATE ;                  ;                       ;
+; spi2adc:SPI_ADC|shift_reg[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|shift_reg[8]~DUPLICATE ;                  ;                       ;
+; spi2adc:SPI_ADC|state[1]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[1]~DUPLICATE     ;                  ;                       ;
+; spi2adc:SPI_ADC|state[2]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[2]~DUPLICATE     ;                  ;                       ;
+; spi2adc:SPI_ADC|state[3]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[3]~DUPLICATE     ;                  ;                       ;
+; spi2dac:dac|state[2]         ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:dac|state[2]~DUPLICATE         ;                  ;                       ;
+; spi2dac:dac|state[4]         ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:dac|state[4]~DUPLICATE         ;                  ;                       ;
+; tick_5000:tick|count[1]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[1]~DUPLICATE      ;                  ;                       ;
+; tick_5000:tick|count[2]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[2]~DUPLICATE      ;                  ;                       ;
+; tick_5000:tick|count[3]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[3]~DUPLICATE      ;                  ;                       ;
+; tick_5000:tick|count[4]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[4]~DUPLICATE      ;                  ;                       ;
+; tick_5000:tick|count[6]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[6]~DUPLICATE      ;                  ;                       ;
+; tick_5000:tick|count[7]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[7]~DUPLICATE      ;                  ;                       ;
+; tick_5000:tick|count[9]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[9]~DUPLICATE      ;                  ;                       ;
+; tick_5000:tick|count[11]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[11]~DUPLICATE     ;                  ;                       ;
+; tick_5000:tick|count[13]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_5000:tick|count[13]~DUPLICATE     ;                  ;                       ;
++------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------+------------------+-----------------------+
 
 
 +--------------------------------------------------------------------------------------------+
@@ -249,20 +251,32 @@ agreement for further details.
 +--------------+----------------+--------------+------------+---------------+----------------+
 ; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
 +--------------+----------------+--------------+------------+---------------+----------------+
-; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[0]     ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]     ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
-; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
 ; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
 ; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
 ; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
@@ -273,30 +287,42 @@ agreement for further details.
 ; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
 ; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
 ; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; KEY[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; KEY[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex15           ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
 +--------------+----------------+--------------+------------+---------------+----------------+
 
 
@@ -306,8 +332,8 @@ agreement for further details.
 ; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
 +---------------------+--------------------+----------------------------+--------------------------+
 ; Placement (by node) ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 487 ) ; 0.00 % ( 0 / 487 )         ; 0.00 % ( 0 / 487 )       ;
-;     -- Achieved     ; 0.00 % ( 0 / 487 ) ; 0.00 % ( 0 / 487 )         ; 0.00 % ( 0 / 487 )       ;
+;     -- Requested    ; 0.00 % ( 0 / 469 ) ; 0.00 % ( 0 / 469 )         ; 0.00 % ( 0 / 469 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 469 ) ; 0.00 % ( 0 / 469 )         ; 0.00 % ( 0 / 469 )       ;
 ;                     ;                    ;                            ;                          ;
 ; Routing (by net)    ;                    ;                            ;                          ;
 ;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
@@ -330,7 +356,7 @@ agreement for further details.
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
 ; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 487 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; Top                            ; 0.00 % ( 0 / 469 )    ; N/A                     ; Source File       ; N/A                 ;       ;
 ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
 
@@ -338,7 +364,7 @@ agreement for further details.
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
+The pin-out file can be found in /Desktop/ex15/output_files/ex10.pin.
 
 
 +------------------------------------------------------------------------------------------+
@@ -346,14 +372,14 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 +-------------------------------------------------------------+--------------------+-------+
 ; Resource                                                    ; Usage              ; %     ;
 +-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 154 / 32,070       ; < 1 % ;
-; ALMs needed [=A-B+C]                                        ; 154                ;       ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 160 / 32,070       ; < 1 % ;
-;         [a] ALMs used for LUT logic and registers           ; 37                 ;       ;
-;         [b] ALMs used for LUT logic                         ; 117                ;       ;
-;         [c] ALMs used for registers                         ; 6                  ;       ;
+; Logic utilization (ALMs needed / total ALMs on device)      ; 146 / 32,070       ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 146                ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 161 / 32,070       ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 33                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 106                ;       ;
+;         [c] ALMs used for registers                         ; 22                 ;       ;
 ;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 6 / 32,070         ; < 1 % ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 15 / 32,070        ; < 1 % ;
 ;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
 ;         [a] Due to location constrained logic               ; 0                  ;       ;
 ;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
@@ -362,28 +388,28 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ;                                                             ;                    ;       ;
 ; Difficulty packing design                                   ; Low                ;       ;
 ;                                                             ;                    ;       ;
-; Total LABs:  partially or completely used                   ; 20 / 3,207         ; < 1 % ;
-;     -- Logic LABs                                           ; 20                 ;       ;
+; Total LABs:  partially or completely used                   ; 21 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 21                 ;       ;
 ;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
 ;                                                             ;                    ;       ;
-; Combinational ALUT usage for logic                          ; 287                ;       ;
+; Combinational ALUT usage for logic                          ; 258                ;       ;
 ;     -- 7 input functions                                    ; 0                  ;       ;
-;     -- 6 input functions                                    ; 23                 ;       ;
-;     -- 5 input functions                                    ; 14                 ;       ;
-;     -- 4 input functions                                    ; 150                ;       ;
-;     -- <=3 input functions                                  ; 100                ;       ;
-; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;
-; Dedicated logic registers                                   ; 95                 ;       ;
+;     -- 6 input functions                                    ; 22                 ;       ;
+;     -- 5 input functions                                    ; 25                 ;       ;
+;     -- 4 input functions                                    ; 124                ;       ;
+;     -- <=3 input functions                                  ; 87                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 28                 ;       ;
+; Dedicated logic registers                                   ; 130                ;       ;
 ;     -- By type:                                             ;                    ;       ;
-;         -- Primary logic registers                          ; 85 / 64,140        ; < 1 % ;
-;         -- Secondary logic registers                        ; 10 / 64,140        ; < 1 % ;
+;         -- Primary logic registers                          ; 109 / 64,140       ; < 1 % ;
+;         -- Secondary logic registers                        ; 21 / 64,140        ; < 1 % ;
 ;     -- By function:                                         ;                    ;       ;
-;         -- Design implementation registers                  ; 85                 ;       ;
-;         -- Routing optimization registers                   ; 10                 ;       ;
+;         -- Design implementation registers                  ; 110                ;       ;
+;         -- Routing optimization registers                   ; 20                 ;       ;
 ;                                                             ;                    ;       ;
 ; Virtual pins                                                ; 0                  ;       ;
-; I/O pins                                                    ; 57 / 457           ; 12 %  ;
-;     -- Clock pins                                           ; 4 / 8              ; 50 %  ;
+; I/O pins                                                    ; 45 / 457           ; 10 %  ;
+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;
 ;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
 ;                                                             ;                    ;       ;
 ; Hard processor system peripheral utilization                ;                    ;       ;
@@ -414,10 +440,10 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
 ;                                                             ;                    ;       ;
 ; Global signals                                              ; 1                  ;       ;
-; M10K blocks                                                 ; 0 / 397            ; 0 %   ;
+; M10K blocks                                                 ; 1 / 397            ; < 1 % ;
 ; Total MLAB memory bits                                      ; 0                  ;       ;
-; Total block memory bits                                     ; 0 / 4,065,280      ; 0 %   ;
-; Total block memory implementation bits                      ; 0 / 4,065,280      ; 0 %   ;
+; Total block memory bits                                     ; 10,240 / 4,065,280 ; < 1 % ;
+; Total block memory implementation bits                      ; 10,240 / 4,065,280 ; < 1 % ;
 ;                                                             ;                    ;       ;
 ; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
 ;                                                             ;                    ;       ;
@@ -434,12 +460,12 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
 ; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
 ; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
-; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
-; Peak interconnect usage (total/H/V)                         ; 3.6% / 3.8% / 3.1% ;       ;
-; Maximum fan-out                                             ; 58                 ;       ;
-; Highest non-global fan-out                                  ; 58                 ;       ;
-; Total fan-out                                               ; 1391               ;       ;
-; Average fan-out                                             ; 2.79               ;       ;
+; Average interconnect usage (total/H/V)                      ; 0.2% / 0.2% / 0.2% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 3.6% / 4.0% / 2.5% ;       ;
+; Maximum fan-out                                             ; 63                 ;       ;
+; Highest non-global fan-out                                  ; 36                 ;       ;
+; Total fan-out                                               ; 1412               ;       ;
+; Average fan-out                                             ; 2.78               ;       ;
 +-------------------------------------------------------------+--------------------+-------+
 
 
@@ -448,14 +474,14 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 +-------------------------------------------------------------+-----------------------+--------------------------------+
 ; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
 +-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 154 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-; ALMs needed [=A-B+C]                                        ; 154                   ; 0                              ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 160 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-;         [a] ALMs used for LUT logic and registers           ; 37                    ; 0                              ;
-;         [b] ALMs used for LUT logic                         ; 117                   ; 0                              ;
-;         [c] ALMs used for registers                         ; 6                     ; 0                              ;
+; Logic utilization (ALMs needed / total ALMs on device)      ; 146 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 146                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 161 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 33                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 106                   ; 0                              ;
+;         [c] ALMs used for registers                         ; 22                    ; 0                              ;
 ;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 6 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 15 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
 ;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
 ;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
 ;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
@@ -464,35 +490,36 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ;                                                             ;                       ;                                ;
 ; Difficulty packing design                                   ; Low                   ; Low                            ;
 ;                                                             ;                       ;                                ;
-; Total LABs:  partially or completely used                   ; 20 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
-;     -- Logic LABs                                           ; 20                    ; 0                              ;
+; Total LABs:  partially or completely used                   ; 21 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 21                    ; 0                              ;
 ;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
-; Combinational ALUT usage for logic                          ; 287                   ; 0                              ;
+; Combinational ALUT usage for logic                          ; 258                   ; 0                              ;
 ;     -- 7 input functions                                    ; 0                     ; 0                              ;
-;     -- 6 input functions                                    ; 23                    ; 0                              ;
-;     -- 5 input functions                                    ; 14                    ; 0                              ;
-;     -- 4 input functions                                    ; 150                   ; 0                              ;
-;     -- <=3 input functions                                  ; 100                   ; 0                              ;
-; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;
+;     -- 6 input functions                                    ; 22                    ; 0                              ;
+;     -- 5 input functions                                    ; 25                    ; 0                              ;
+;     -- 4 input functions                                    ; 124                   ; 0                              ;
+;     -- <=3 input functions                                  ; 87                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 28                    ; 0                              ;
 ; Memory ALUT usage                                           ; 0                     ; 0                              ;
 ;     -- 64-address deep                                      ; 0                     ; 0                              ;
 ;     -- 32-address deep                                      ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; Dedicated logic registers                                   ; 0                     ; 0                              ;
 ;     -- By type:                                             ;                       ;                                ;
-;         -- Primary logic registers                          ; 85 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
-;         -- Secondary logic registers                        ; 10 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;         -- Primary logic registers                          ; 109 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 21 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
 ;     -- By function:                                         ;                       ;                                ;
-;         -- Design implementation registers                  ; 85                    ; 0                              ;
-;         -- Routing optimization registers                   ; 10                    ; 0                              ;
+;         -- Design implementation registers                  ; 110                   ; 0                              ;
+;         -- Routing optimization registers                   ; 20                    ; 0                              ;
 ;                                                             ;                       ;                                ;
 ;                                                             ;                       ;                                ;
 ; Virtual pins                                                ; 0                     ; 0                              ;
-; I/O pins                                                    ; 57                    ; 0                              ;
+; I/O pins                                                    ; 45                    ; 0                              ;
 ; I/O registers                                               ; 0                     ; 0                              ;
-; Total block memory bits                                     ; 0                     ; 0                              ;
-; Total block memory implementation bits                      ; 0                     ; 0                              ;
+; Total block memory bits                                     ; 10240                 ; 0                              ;
+; Total block memory implementation bits                      ; 10240                 ; 0                              ;
+; M10K block                                                  ; 1 / 397 ( < 1 % )     ; 0 / 397 ( 0 % )                ;
 ; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
 ;                                                             ;                       ;                                ;
 ; Connections                                                 ;                       ;                                ;
@@ -502,16 +529,16 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ;     -- Registered Output Connections                        ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; Internal Connections                                        ;                       ;                                ;
-;     -- Total Connections                                    ; 1391                  ; 0                              ;
-;     -- Registered Connections                               ; 407                   ; 0                              ;
+;     -- Total Connections                                    ; 1412                  ; 0                              ;
+;     -- Registered Connections                               ; 470                   ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; External Connections                                        ;                       ;                                ;
 ;     -- Top                                                  ; 0                     ; 0                              ;
 ;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; Partition Interface                                         ;                       ;                                ;
-;     -- Input Ports                                          ; 5                     ; 0                              ;
-;     -- Output Ports                                         ; 52                    ; 0                              ;
+;     -- Input Ports                                          ; 2                     ; 0                              ;
+;     -- Output Ports                                         ; 43                    ; 0                              ;
 ;     -- Bidir Ports                                          ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; Registered Ports                                            ;                       ;                                ;
@@ -535,11 +562,8 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
 ; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
 +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 40                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; ADC_SDO  ; AJ21  ; 4A       ; 62           ; 0            ; 51           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 66                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
 +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
 
 
@@ -548,6 +572,13 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 +---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
 ; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
 +---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; ADC_CS  ; AG20  ; 4A       ; 62           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; ADC_SCK ; AF21  ; 4A       ; 70           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; ADC_SDI ; AG21  ; 4A       ; 54           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_CS  ; AD20  ; 4A       ; 82           ; 0            ; 40           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_LD  ; AK21  ; 4A       ; 68           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SCK ; AF20  ; 4A       ; 70           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SDI ; AG18  ; 4A       ; 58           ; 0            ; 74           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
@@ -583,46 +614,30 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[0] ; V25   ; 5B       ; 89           ; 20           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[1] ; AA28  ; 5B       ; 89           ; 21           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[2] ; Y27   ; 5B       ; 89           ; 25           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[3] ; AB27  ; 5B       ; 89           ; 23           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[4] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[5] ; AA26  ; 5B       ; 89           ; 23           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[6] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; PWM_OUT ; AJ20  ; 4A       ; 62           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 +---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
 
 
-+-----------------------------------------------------------------------------+
-; I/O Bank Usage                                                              ;
-+----------+-------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+-------------------+---------------+--------------+---------------+
-; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
-; B1L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
-; 3A       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 3B       ; 5 / 48 ( 10 % )   ; 3.3V          ; --           ; 3.3V          ;
-; 4A       ; 7 / 80 ( 9 % )    ; 3.3V          ; --           ; 3.3V          ;
-; 5A       ; 32 / 32 ( 100 % ) ; 3.3V          ; --           ; 3.3V          ;
-; 5B       ; 13 / 16 ( 81 % )  ; 3.3V          ; --           ; 3.3V          ;
-; 6B       ; 0 / 44 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 6A       ; 0 / 56 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7A       ; 0 / 19 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7B       ; 0 / 22 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7C       ; 0 / 12 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7D       ; 0 / 14 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 8A       ; 0 / 80 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-+----------+-------------------+---------------+--------------+---------------+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 0 / 32 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 1 / 48 ( 2 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 9 / 80 ( 11 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 27 / 32 ( 84 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 8 / 16 ( 50 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
 
 
 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -671,8 +686,8 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -682,10 +697,10 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
 ; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA25     ; 224        ; 5A             ; HEX5[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA26     ; 252        ; 5B             ; HEX5[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA28     ; 251        ; 5B             ; HEX5[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -713,8 +728,8 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB26     ; 226        ; 5A             ; HEX5[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB27     ; 254        ; 5B             ; HEX5[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -767,7 +782,7 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; DAC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -827,8 +842,8 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; DAC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF21     ; 173        ; 4A             ; ADC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -855,10 +870,10 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; DAC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG20     ; 157        ; 4A             ; ADC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG21     ; 143        ; 4A             ; ADC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -917,8 +932,8 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; PWM_OUT                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AJ21     ; 156        ; 4A             ; ADC_SDO                         ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -947,7 +962,7 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK21     ; 171        ; 4A             ; DAC_LD                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -1451,16 +1466,16 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
 ; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V25      ; 246        ; 5B             ; HEX5[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -1480,13 +1495,13 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
 ; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
@@ -1511,18 +1526,18 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
 ; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y27      ; 258        ; 5B             ; HEX5[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -1530,59 +1545,62 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 Note: Pin directions (input, output or bidir) are based on device operating in user mode.
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9                       ; 154.0 (0.5)          ; 159.0 (0.5)                      ; 5.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 287 (1)             ; 95 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
-;    |LFSR:LFSR0|            ; 2.5 (2.5)            ; 3.2 (3.2)                        ; 0.7 (0.7)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 67.7 (0.0)           ; 68.0 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 124 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A1|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A10|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A32|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
-;       |add3_ge5:A33|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 3.7 (3.7)            ; 4.0 (4.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:COUNT0|     ; 8.5 (8.5)            ; 9.0 (9.0)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
-;    |delay:DEL0|            ; 12.2 (12.2)          ; 13.2 (13.2)                      ; 0.9 (0.9)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 22 (22)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 8.9 (8.9)            ; 10.0 (10.0)                      ; 1.1 (1.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (16)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
-;    |tick_2500:TICK1|       ; 14.1 (14.1)          ; 14.7 (14.7)                      ; 0.6 (0.6)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 27 (27)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_2500:TICK1             ; tick_2500   ; work         ;
-;    |tick_50000:TICK0|      ; 18.1 (18.1)          ; 19.0 (19.0)                      ; 0.9 (0.9)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 27 (27)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++---------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                        ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                       ; Entity Name     ; Library Name ;
++---------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex15                                             ; 145.5 (0.5)          ; 160.0 (0.5)                      ; 14.5 (0.0)                                        ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 258 (1)             ; 130 (0)                   ; 0 (0)         ; 10240             ; 1     ; 0          ; 45   ; 0            ; |ex15                                                                                                                                                     ; ex15            ; work         ;
+;    |ROM:rom|                                      ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex15|ROM:rom                                                                                                                                             ; ROM             ; work         ;
+;       |altsyncram:altsyncram_component|           ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex15|ROM:rom|altsyncram:altsyncram_component                                                                                                             ; altsyncram      ; work         ;
+;          |altsyncram_6ng1:auto_generated|         ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 10240             ; 1     ; 0          ; 0    ; 0            ; |ex15|ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated                                                                              ; altsyncram_6ng1 ; work         ;
+;    |add_offset:fin_address|                       ; 2.5 (2.5)            ; 7.5 (7.5)                        ; 5.0 (5.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 10 (10)             ; 10 (10)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|add_offset:fin_address                                                                                                                              ; add_offset      ; work         ;
+;    |bin2bcd_16:bcd|                               ; 52.7 (0.0)           ; 54.0 (0.0)                       ; 1.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 97 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd                                                                                                                                      ; bin2bcd_16      ; work         ;
+;       |add3_ge5:A1|                               ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A1                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A10|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A10                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A11|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A11                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A12|                              ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A12                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A13|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A13                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A14|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A14                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A15|                              ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A15                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A16|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A16                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A17|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A17                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A19|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A19                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A2|                               ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A2                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A20|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A20                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A21|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A21                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A22|                              ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A22                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A23|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A23                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A24|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A24                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A25|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A25                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A26|                              ; 6.0 (6.0)            ; 6.0 (6.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 9 (9)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A26                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A27|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A27                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A28|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A28                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A29|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A29                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A4|                               ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A4                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A5|                               ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A5                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A6|                               ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A6                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A7|                               ; 2.7 (2.7)            ; 4.0 (4.0)                        ; 1.3 (1.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A7                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A8|                               ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A8                                                                                                                          ; add3_ge5        ; work         ;
+;    |const_mult:mult|                              ; 18.0 (0.0)           ; 18.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult                                                                                                                                     ; const_mult      ; work         ;
+;       |lpm_mult:lpm_mult_component|               ; 18.0 (0.0)           ; 18.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component                                                                                                         ; lpm_mult        ; work         ;
+;          |multcore:mult_core|                     ; 18.0 (3.0)           ; 18.0 (3.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (6)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core                                                                                      ; multcore        ; work         ;
+;             |mpar_add:padder|                     ; 15.0 (0.0)           ; 15.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 30 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder                                                                      ; mpar_add        ; work         ;
+;                |lpm_add_sub:adder[0]|             ; 9.0 (0.0)            ; 9.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; lpm_add_sub     ; work         ;
+;                   |add_sub_d9h:auto_generated|    ; 9.0 (9.0)            ; 9.0 (9.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (18)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated                      ; add_sub_d9h     ; work         ;
+;                |mpar_add:sub_par_add|             ; 6.0 (0.0)            ; 6.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 12 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; mpar_add        ; work         ;
+;                   |lpm_add_sub:adder[0]|          ; 6.0 (0.0)            ; 6.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 12 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; lpm_add_sub     ; work         ;
+;                      |add_sub_89h:auto_generated| ; 6.0 (6.0)            ; 6.0 (6.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 12 (12)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated ; add_sub_89h     ; work         ;
+;    |hex_to_7seg:h0|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h0                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h1|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h1                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h2|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h2                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h3|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h3                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h4|                               ; 2.5 (2.5)            ; 2.5 (2.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h4                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |pwm:p|                                        ; 9.3 (9.3)            ; 11.5 (11.5)                      ; 2.2 (2.2)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (16)             ; 22 (22)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|pwm:p                                                                                                                                               ; pwm             ; work         ;
+;    |spi2adc:SPI_ADC|                              ; 15.2 (15.2)          ; 20.2 (20.2)                      ; 5.1 (5.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 21 (21)             ; 47 (47)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|spi2adc:SPI_ADC                                                                                                                                     ; spi2adc         ; work         ;
+;    |spi2dac:dac|                                  ; 16.5 (16.5)          ; 17.2 (17.2)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 19 (19)             ; 25 (25)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|spi2dac:dac                                                                                                                                         ; spi2dac         ; work         ;
+;    |tick_5000:tick|                               ; 14.3 (14.3)          ; 14.5 (14.5)                      ; 0.2 (0.2)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 27 (27)             ; 26 (26)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex15|tick_5000:tick                                                                                                                                      ; tick_5000       ; work         ;
++---------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
@@ -1591,8 +1609,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
 ; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
 +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; DAC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_LD   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; PWM_OUT  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
@@ -1628,63 +1652,41 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; KEY[0]   ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
 ; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[3]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; ADC_SDO  ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
 +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
 
 
-+-------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                                                ;
-+-------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;
-+-------------------------------------------------+-------------------+---------+
-; KEY[1]                                          ;                   ;         ;
-; KEY[2]                                          ;                   ;         ;
-; KEY[0]                                          ;                   ;         ;
-;      - counter_16:COUNT0|count~0                ; 0                 ; 0       ;
-; CLOCK_50                                        ;                   ;         ;
-;      - tick_50000:TICK0|CLK_OUT                 ; 0                 ; 0       ;
-;      - tick_2500:TICK1|CLK_OUT                  ; 0                 ; 0       ;
-; KEY[3]                                          ;                   ;         ;
-;      - formula_fsm:FSM|Selector2~0              ; 1                 ; 0       ;
-;      - formula_fsm:FSM|Selector3~0              ; 1                 ; 0       ;
-;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 1                 ; 0       ;
-+-------------------------------------------------+-------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                                                                                 ;
-+-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; Name                                ; Location            ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50                            ; PIN_AF14            ; 3       ; Clock                      ; no     ; --                   ; --               ; --                        ;
-; CLOCK_50                            ; PIN_AF14            ; 38      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
-; counter_16:COUNT0|count~0           ; MLABCELL_X84_Y4_N48 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; counter_16:COUNT0|state             ; FF_X84_Y4_N53       ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|count[1]~0               ; MLABCELL_X84_Y1_N48 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|state.COUNTING           ; FF_X83_Y1_N17       ; 18      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X85_Y1_N59       ; 19      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;
-; tick_2500:TICK1|CLK_OUT             ; FF_X81_Y1_N13       ; 10      ; Clock                      ; no     ; --                   ; --               ; --                        ;
-; tick_50000:TICK0|CLK_OUT            ; FF_X83_Y2_N20       ; 58      ; Clock, Clock enable        ; no     ; --                   ; --               ; --                        ;
-+-------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
++-------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                    ;
++-------------------------------------+-------------------+---------+
+; Source Pin / Fanout                 ; Pad To Core Index ; Setting ;
++-------------------------------------+-------------------+---------+
+; CLOCK_50                            ;                   ;         ;
+;      - spi2adc:SPI_ADC|clk_1MHz     ; 0                 ; 0       ;
+;      - spi2dac:dac|clk_1MHz         ; 0                 ; 0       ;
+;      - tick_5000:tick|CLK_OUT       ; 0                 ; 0       ;
+; ADC_SDO                             ;                   ;         ;
+;      - spi2adc:SPI_ADC|shift_reg[0] ; 0                 ; 0       ;
++-------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                ;
++---------------------------+---------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
+; Name                      ; Location            ; Fan-Out ; Usage               ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------+---------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                  ; PIN_AF14            ; 4       ; Clock               ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                  ; PIN_AF14            ; 63      ; Clock               ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; spi2adc:SPI_ADC|adc_done  ; FF_X75_Y6_N34       ; 10      ; Clock enable        ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|always3~0 ; LABCELL_X75_Y6_N42  ; 12      ; Clock enable        ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|clk_1MHz  ; FF_X74_Y6_N59       ; 36      ; Clock               ; no     ; --                   ; --               ; --                        ;
+; spi2dac:dac|Equal0~0      ; LABCELL_X74_Y6_N27  ; 5       ; Clock enable        ; no     ; --                   ; --               ; --                        ;
+; spi2dac:dac|always5~0     ; MLABCELL_X72_Y6_N45 ; 9       ; Sync. load          ; no     ; --                   ; --               ; --                        ;
+; spi2dac:dac|clk_1MHz      ; FF_X74_Y6_N32       ; 23      ; Clock               ; no     ; --                   ; --               ; --                        ;
+; tick_5000:tick|CLK_OUT    ; FF_X81_Y6_N14       ; 25      ; Clock, Clock enable ; no     ; --                   ; --               ; --                        ;
+; tick_5000:tick|Equal0~3   ; MLABCELL_X82_Y6_N57 ; 15      ; Sync. clear         ; no     ; --                   ; --               ; --                        ;
++---------------------------+---------------------+---------+---------------------+--------+----------------------+------------------+---------------------------+
 
 
 +-----------------------------------------------------------------------------------------------------+
@@ -1692,23 +1694,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------+----------+---------+----------------------+------------------+---------------------------+
 ; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
 +----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 38      ; Global Clock         ; GCLK6            ; --                        ;
+; CLOCK_50 ; PIN_AF14 ; 63      ; Global Clock         ; GCLK6            ; --                        ;
 +----------+----------+---------+----------------------+------------------+---------------------------+
 
 
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; Name                                                                              ; Type ; Mode ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF                     ; Location       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs         ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; Single Clock ; 1024         ; 10           ; --           ; --           ; yes                    ; yes                     ; --                     ; --                      ; 10240 ; 1024                        ; 10                          ; --                          ; --                          ; 10240               ; 1           ; 0          ; ./rom_data/rom_data.mif ; M10K_X76_Y6_N0 ; Don't care           ; New data        ; New data        ; Off      ; No                     ; No - Address Too Wide ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+-------------------------+----------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
 +-----------------------------------------------------------------------+
 ; Routing Usage Summary                                                 ;
 +---------------------------------------------+-------------------------+
 ; Routing Resource Type                       ; Usage                   ;
 +---------------------------------------------+-------------------------+
-; Block interconnects                         ; 349 / 289,320 ( < 1 % ) ;
-; C12 interconnects                           ; 7 / 13,420 ( < 1 % )    ;
-; C2 interconnects                            ; 126 / 119,108 ( < 1 % ) ;
-; C4 interconnects                            ; 95 / 56,300 ( < 1 % )   ;
+; Block interconnects                         ; 365 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 16 / 13,420 ( < 1 % )   ;
+; C2 interconnects                            ; 157 / 119,108 ( < 1 % ) ;
+; C4 interconnects                            ; 141 / 56,300 ( < 1 % )  ;
 ; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
 ; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
 ; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
-; Direct links                                ; 63 / 289,320 ( < 1 % )  ;
+; Direct links                                ; 49 / 289,320 ( < 1 % )  ;
 ; Global clocks                               ; 1 / 16 ( 6 % )          ;
 ; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
 ; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
@@ -1764,12 +1776,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
 ; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
 ; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
-; Local interconnects                         ; 127 / 84,580 ( < 1 % )  ;
+; Local interconnects                         ; 107 / 84,580 ( < 1 % )  ;
 ; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
-; R14 interconnects                           ; 56 / 12,676 ( < 1 % )   ;
-; R14/C12 interconnect drivers                ; 59 / 20,720 ( < 1 % )   ;
-; R3 interconnects                            ; 175 / 130,992 ( < 1 % ) ;
-; R6 interconnects                            ; 166 / 266,960 ( < 1 % ) ;
+; R14 interconnects                           ; 76 / 12,676 ( < 1 % )   ;
+; R14/C12 interconnect drivers                ; 89 / 20,720 ( < 1 % )   ;
+; R3 interconnects                            ; 210 / 130,992 ( < 1 % ) ;
+; R6 interconnects                            ; 322 / 266,960 ( < 1 % ) ;
 ; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
 ; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
 +---------------------------------------------+-------------------------+
@@ -1829,12 +1841,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
 ; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
 +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Total Pass         ; 57        ; 0            ; 57        ; 0            ; 0            ; 57        ; 57        ; 0            ; 57        ; 57        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Pass         ; 45        ; 0            ; 45        ; 0            ; 0            ; 45        ; 45        ; 0            ; 45        ; 45        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
 ; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
-; Total Inapplicable ; 0         ; 57           ; 0         ; 57           ; 57           ; 0         ; 0         ; 57           ; 0         ; 0         ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ;
+; Total Inapplicable ; 0         ; 45           ; 0         ; 45           ; 45           ; 0         ; 0         ; 45           ; 0         ; 0         ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ; 45           ;
 ; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
-; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_LD             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; PWM_OUT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
@@ -1870,26 +1888,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDO            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
 
 
@@ -1936,115 +1936,131 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +---------------------------+--------+
 
 
-+-------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary                                                               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; CLOCK_50                                                     ; CLOCK_50                 ; 48.8              ;
-; tick_50000:TICK0|CLK_OUT                                     ; tick_2500:TICK1|CLK_OUT  ; 26.5              ;
-; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 22.9              ;
-; tick_2500:TICK1|CLK_OUT                                      ; tick_2500:TICK1|CLK_OUT  ; 8.3               ;
-; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 2.7               ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 2.6               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
++---------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                           ;
++-------------------------------------------------+-----------------------------------+-------------------+
+; Source Clock(s)                                 ; Destination Clock(s)              ; Delay Added in ns ;
++-------------------------------------------------+-----------------------------------+-------------------+
+; CLOCK_50                                        ; CLOCK_50                          ; 71.5              ;
+; tick_5000:tick|CLK_OUT                          ; CLOCK_50                          ; 38.7              ;
+; spi2adc:SPI_ADC|clk_1MHz                        ; spi2adc:SPI_ADC|clk_1MHz          ; 34.2              ;
+; spi2dac:dac|clk_1MHz                            ; CLOCK_50                          ; 25.8              ;
+; spi2adc:SPI_ADC|clk_1MHz                        ; CLOCK_50                          ; 16.5              ;
+; spi2dac:dac|clk_1MHz                            ; spi2dac:dac|clk_1MHz              ; 13.8              ;
+; spi2dac:dac|clk_1MHz                            ; CLOCK_50,spi2dac:dac|clk_1MHz,I/O ; 9.0               ;
+; spi2adc:SPI_ADC|clk_1MHz,tick_5000:tick|CLK_OUT ; tick_5000:tick|CLK_OUT            ; 8.2               ;
++-------------------------------------------------+-----------------------------------+-------------------+
 Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
 This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
 
 
-+--------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details                                                    ;
-+----------------------------------------+-------------------------------------+-------------------+
-; Source Register                        ; Destination Register                ; Delay Added in ns ;
-+----------------------------------------+-------------------------------------+-------------------+
-; tick_50000:TICK0|CLK_OUT               ; tick_2500:TICK1|CLK_OUT             ; 5.988             ;
-; tick_2500:TICK1|count[11]              ; tick_2500:TICK1|CLK_OUT             ; 2.378             ;
-; tick_2500:TICK1|count[5]               ; tick_2500:TICK1|CLK_OUT             ; 2.208             ;
-; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT            ; 2.161             ;
-; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT            ; 2.135             ;
-; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT            ; 2.084             ;
-; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT            ; 2.083             ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[2]             ; 2.077             ;
-; tick_2500:TICK1|count[9]               ; tick_2500:TICK1|CLK_OUT             ; 2.065             ;
-; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT            ; 2.053             ;
-; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT            ; 2.050             ;
-; tick_2500:TICK1|count[10]              ; tick_2500:TICK1|CLK_OUT             ; 2.046             ;
-; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT            ; 2.043             ;
-; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT            ; 2.013             ;
-; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT            ; 2.011             ;
-; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT            ; 1.990             ;
-; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT            ; 1.975             ;
-; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT            ; 1.972             ;
-; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT            ; 1.972             ;
-; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT            ; 1.966             ;
-; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT            ; 1.950             ;
-; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT            ; 1.928             ;
-; tick_2500:TICK1|count[4]               ; tick_2500:TICK1|CLK_OUT             ; 1.919             ;
-; tick_2500:TICK1|count[2]               ; tick_2500:TICK1|CLK_OUT             ; 1.652             ;
-; tick_2500:TICK1|count[3]               ; tick_2500:TICK1|CLK_OUT             ; 1.628             ;
-; tick_2500:TICK1|count[0]               ; tick_2500:TICK1|CLK_OUT             ; 1.615             ;
-; tick_2500:TICK1|count[6]               ; tick_2500:TICK1|CLK_OUT             ; 1.606             ;
-; tick_2500:TICK1|count[7]               ; tick_2500:TICK1|CLK_OUT             ; 1.603             ;
-; tick_2500:TICK1|count[1]               ; tick_2500:TICK1|CLK_OUT             ; 1.602             ;
-; tick_2500:TICK1|count[8]               ; tick_2500:TICK1|CLK_OUT             ; 1.569             ;
-; formula_fsm:FSM|start_delay            ; delay:DEL0|count[11]                ; 1.448             ;
-; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|ledr[4]             ; 0.962             ;
-; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|ledr[9]             ; 0.956             ;
-; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|ledr[6]             ; 0.941             ;
-; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|ledr[8]             ; 0.941             ;
-; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|ledr[7]             ; 0.921             ;
-; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|ledr[2]             ; 0.916             ;
-; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|ledr[5]             ; 0.910             ;
-; delay:DEL0|count[6]                    ; delay:DEL0|count[11]                ; 0.901             ;
-; delay:DEL0|count[8]                    ; delay:DEL0|count[11]                ; 0.899             ;
-; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|ledr[1]             ; 0.895             ;
-; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|ledr[3]             ; 0.890             ;
-; delay:DEL0|count[2]                    ; delay:DEL0|count[11]                ; 0.859             ;
-; delay:DEL0|count[3]                    ; delay:DEL0|count[11]                ; 0.855             ;
-; delay:DEL0|count[13]                   ; delay:DEL0|count[11]                ; 0.854             ;
-; delay:DEL0|count[10]                   ; delay:DEL0|count[11]                ; 0.837             ;
-; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[2]             ; 0.821             ;
-; delay:DEL0|count[4]                    ; delay:DEL0|count[11]                ; 0.792             ;
-; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.791             ;
-; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.791             ;
-; delay:DEL0|count[12]                   ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|count[9]                    ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|count[7]                    ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|count[1]                    ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|count[0]                    ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|count[5]                    ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|count[11]                   ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|state.IDLE                  ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|state.COUNTING              ; delay:DEL0|count[11]                ; 0.747             ;
-; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE               ; 0.679             ;
-; delay:DEL0|state.TIME_OUT              ; delay:DEL0|state.IDLE               ; 0.679             ;
-; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.644             ;
-; KEY[3]                                 ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.644             ;
-; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.644             ;
-; LFSR:LFSR0|COUNT[5]                    ; delay:DEL0|count[11]                ; 0.632             ;
-; LFSR:LFSR0|COUNT[4]                    ; delay:DEL0|count[10]                ; 0.628             ;
-; LFSR:LFSR0|COUNT[6]                    ; delay:DEL0|count[12]                ; 0.628             ;
-; LFSR:LFSR0|COUNT[2]                    ; delay:DEL0|count[8]                 ; 0.622             ;
-; counter_16:COUNT0|state                ; counter_16:COUNT0|count[0]          ; 0.525             ;
-; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                 ; 0.429             ;
-; counter_16:COUNT0|count[9]             ; counter_16:COUNT0|count[15]         ; 0.267             ;
-; counter_16:COUNT0|count[7]             ; counter_16:COUNT0|count[15]         ; 0.253             ;
-; counter_16:COUNT0|count[1]             ; counter_16:COUNT0|count[15]         ; 0.247             ;
-; counter_16:COUNT0|count[12]            ; counter_16:COUNT0|count[15]         ; 0.246             ;
-; counter_16:COUNT0|count[0]             ; counter_16:COUNT0|count[15]         ; 0.246             ;
-; counter_16:COUNT0|count[8]             ; counter_16:COUNT0|count[15]         ; 0.244             ;
-; counter_16:COUNT0|count[5]             ; counter_16:COUNT0|count[15]         ; 0.239             ;
-; counter_16:COUNT0|count[13]            ; counter_16:COUNT0|count[15]         ; 0.236             ;
-; counter_16:COUNT0|count[3]             ; counter_16:COUNT0|count[15]         ; 0.234             ;
-; counter_16:COUNT0|count[6]             ; counter_16:COUNT0|count[15]         ; 0.233             ;
-; KEY[0]                                 ; counter_16:COUNT0|count[0]          ; 0.121             ;
-; counter_16:COUNT0|count[11]            ; counter_16:COUNT0|count[15]         ; 0.059             ;
-; counter_16:COUNT0|count[14]            ; counter_16:COUNT0|count[15]         ; 0.054             ;
-; counter_16:COUNT0|count[2]             ; counter_16:COUNT0|count[15]         ; 0.053             ;
-; counter_16:COUNT0|count[10]            ; counter_16:COUNT0|count[15]         ; 0.048             ;
-; counter_16:COUNT0|count[4]             ; counter_16:COUNT0|count[15]         ; 0.048             ;
-+----------------------------------------+-------------------------------------+-------------------+
-Note: This table only shows the top 86 path(s) that have the largest delay added for hold.
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                       ;
++----------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                        ; Destination Register                                                                                   ; Delay Added in ns ;
++----------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------+
+; spi2dac:dac|clk_1MHz                   ; spi2dac:dac|clk_1MHz                                                                                   ; 6.034             ;
+; spi2adc:SPI_ADC|clk_1MHz               ; spi2adc:SPI_ADC|clk_1MHz                                                                               ; 5.876             ;
+; tick_5000:tick|CLK_OUT                 ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL                                                                 ; 4.515             ;
+; spi2dac:dac|state[2]                   ; spi2dac:dac|sr_state.WAIT_CSB_HIGH                                                                     ; 4.302             ;
+; spi2dac:dac|state[1]                   ; spi2dac:dac|sr_state.WAIT_CSB_HIGH                                                                     ; 4.300             ;
+; spi2dac:dac|state[0]                   ; spi2dac:dac|sr_state.WAIT_CSB_HIGH                                                                     ; 4.263             ;
+; spi2dac:dac|state[4]                   ; spi2dac:dac|sr_state.WAIT_CSB_HIGH                                                                     ; 4.235             ;
+; spi2dac:dac|state[3]                   ; spi2dac:dac|sr_state.WAIT_CSB_HIGH                                                                     ; 4.235             ;
+; spi2adc:SPI_ADC|adc_cs                 ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL                                                                 ; 4.147             ;
+; add_offset:fin_address|address[7]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.884             ;
+; add_offset:fin_address|address[6]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.884             ;
+; add_offset:fin_address|address[4]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.884             ;
+; add_offset:fin_address|address[2]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.884             ;
+; add_offset:fin_address|address[1]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.884             ;
+; add_offset:fin_address|address[8]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.866             ;
+; add_offset:fin_address|address[5]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.866             ;
+; add_offset:fin_address|address[3]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.866             ;
+; add_offset:fin_address|address[0]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.866             ;
+; add_offset:fin_address|address[9]      ; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ram_block1a9~porta_address_reg0 ; 3.866             ;
+; tick_5000:tick|count[10]               ; tick_5000:tick|CLK_OUT                                                                                 ; 2.101             ;
+; tick_5000:tick|count[12]               ; tick_5000:tick|CLK_OUT                                                                                 ; 2.042             ;
+; tick_5000:tick|count[4]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.993             ;
+; tick_5000:tick|count[7]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.990             ;
+; tick_5000:tick|count[2]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.990             ;
+; tick_5000:tick|count[3]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.987             ;
+; tick_5000:tick|count[5]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.975             ;
+; tick_5000:tick|count[6]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.952             ;
+; tick_5000:tick|count[1]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.941             ;
+; tick_5000:tick|count[8]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.877             ;
+; tick_5000:tick|count[9]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.872             ;
+; tick_5000:tick|count[0]                ; tick_5000:tick|CLK_OUT                                                                                 ; 1.825             ;
+; tick_5000:tick|count[15]               ; tick_5000:tick|CLK_OUT                                                                                 ; 1.804             ;
+; tick_5000:tick|count[11]               ; tick_5000:tick|CLK_OUT                                                                                 ; 1.803             ;
+; tick_5000:tick|count[13]               ; tick_5000:tick|CLK_OUT                                                                                 ; 1.771             ;
+; tick_5000:tick|count[14]               ; tick_5000:tick|CLK_OUT                                                                                 ; 1.640             ;
+; spi2adc:SPI_ADC|ctr[2]                 ; spi2adc:SPI_ADC|clk_1MHz                                                                               ; 1.624             ;
+; spi2adc:SPI_ADC|ctr[4]                 ; spi2adc:SPI_ADC|clk_1MHz                                                                               ; 1.622             ;
+; spi2adc:SPI_ADC|ctr[3]                 ; spi2adc:SPI_ADC|clk_1MHz                                                                               ; 1.611             ;
+; spi2adc:SPI_ADC|ctr[0]                 ; spi2adc:SPI_ADC|clk_1MHz                                                                               ; 1.574             ;
+; spi2adc:SPI_ADC|ctr[1]                 ; spi2adc:SPI_ADC|clk_1MHz                                                                               ; 1.553             ;
+; spi2adc:SPI_ADC|state[1]               ; spi2adc:SPI_ADC|adc_cs                                                                                 ; 1.004             ;
+; spi2adc:SPI_ADC|state[4]               ; spi2adc:SPI_ADC|adc_din                                                                                ; 0.987             ;
+; spi2adc:SPI_ADC|shift_reg[7]           ; spi2adc:SPI_ADC|shift_reg[8]                                                                           ; 0.955             ;
+; spi2adc:SPI_ADC|shift_reg[5]           ; spi2adc:SPI_ADC|shift_reg[6]                                                                           ; 0.955             ;
+; spi2adc:SPI_ADC|shift_reg[3]           ; spi2adc:SPI_ADC|shift_reg[4]                                                                           ; 0.955             ;
+; spi2adc:SPI_ADC|shift_reg[1]           ; spi2adc:SPI_ADC|shift_reg[2]                                                                           ; 0.955             ;
+; spi2adc:SPI_ADC|state[0]               ; spi2adc:SPI_ADC|shift_ena                                                                              ; 0.948             ;
+; spi2adc:SPI_ADC|shift_reg[8]           ; spi2adc:SPI_ADC|shift_reg[9]                                                                           ; 0.942             ;
+; spi2adc:SPI_ADC|shift_reg[6]           ; spi2adc:SPI_ADC|shift_reg[7]                                                                           ; 0.942             ;
+; spi2adc:SPI_ADC|shift_reg[4]           ; spi2adc:SPI_ADC|shift_reg[5]                                                                           ; 0.942             ;
+; spi2adc:SPI_ADC|shift_reg[2]           ; spi2adc:SPI_ADC|shift_reg[3]                                                                           ; 0.942             ;
+; spi2adc:SPI_ADC|shift_reg[0]           ; spi2adc:SPI_ADC|shift_reg[1]                                                                           ; 0.942             ;
+; spi2adc:SPI_ADC|state[2]               ; spi2adc:SPI_ADC|shift_ena                                                                              ; 0.936             ;
+; spi2dac:dac|shift_reg[12]              ; spi2dac:dac|shift_reg[13]                                                                              ; 0.924             ;
+; spi2dac:dac|shift_reg[14]              ; spi2dac:dac|shift_reg[15]                                                                              ; 0.924             ;
+; spi2adc:SPI_ADC|state[3]               ; spi2adc:SPI_ADC|shift_ena                                                                              ; 0.915             ;
+; spi2dac:dac|shift_reg[13]              ; spi2dac:dac|shift_reg[14]                                                                              ; 0.909             ;
+; spi2adc:SPI_ADC|data_from_adc[0]       ; add_offset:fin_address|address[3]                                                                      ; 0.883             ;
+; spi2adc:SPI_ADC|data_from_adc[3]       ; add_offset:fin_address|address[3]                                                                      ; 0.883             ;
+; spi2adc:SPI_ADC|data_from_adc[2]       ; add_offset:fin_address|address[3]                                                                      ; 0.883             ;
+; spi2adc:SPI_ADC|data_from_adc[1]       ; add_offset:fin_address|address[3]                                                                      ; 0.883             ;
+; spi2adc:SPI_ADC|data_from_adc[7]       ; add_offset:fin_address|address[7]                                                                      ; 0.875             ;
+; spi2adc:SPI_ADC|data_from_adc[6]       ; add_offset:fin_address|address[7]                                                                      ; 0.875             ;
+; spi2adc:SPI_ADC|data_from_adc[5]       ; add_offset:fin_address|address[7]                                                                      ; 0.875             ;
+; spi2adc:SPI_ADC|data_from_adc[4]       ; add_offset:fin_address|address[7]                                                                      ; 0.875             ;
+; spi2dac:dac|shift_reg[11]              ; spi2dac:dac|shift_reg[12]                                                                              ; 0.830             ;
+; spi2adc:SPI_ADC|data_from_adc[9]       ; add_offset:fin_address|address[9]                                                                      ; 0.763             ;
+; spi2adc:SPI_ADC|data_from_adc[8]       ; add_offset:fin_address|address[9]                                                                      ; 0.763             ;
+; pwm:p|count[0]                         ; pwm:p|count[9]                                                                                         ; 0.580             ;
+; spi2dac:dac|shift_reg[3]               ; spi2dac:dac|shift_reg[4]                                                                               ; 0.565             ;
+; spi2dac:dac|shift_reg[7]               ; spi2dac:dac|shift_reg[8]                                                                               ; 0.565             ;
+; spi2dac:dac|shift_reg[8]               ; spi2dac:dac|shift_reg[9]                                                                               ; 0.565             ;
+; spi2dac:dac|shift_reg[5]               ; spi2dac:dac|shift_reg[6]                                                                               ; 0.563             ;
+; spi2dac:dac|shift_reg[9]               ; spi2dac:dac|shift_reg[10]                                                                              ; 0.540             ;
+; spi2dac:dac|shift_reg[4]               ; spi2dac:dac|shift_reg[5]                                                                               ; 0.530             ;
+; spi2dac:dac|shift_reg[2]               ; spi2dac:dac|shift_reg[3]                                                                               ; 0.514             ;
+; spi2dac:dac|shift_reg[6]               ; spi2dac:dac|shift_reg[7]                                                                               ; 0.514             ;
+; spi2dac:dac|shift_reg[10]              ; spi2dac:dac|shift_reg[11]                                                                              ; 0.507             ;
+; pwm:p|count[9]                         ; pwm:p|pwm_out                                                                                          ; 0.490             ;
+; spi2adc:SPI_ADC|sr_state.IDLE          ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL                                                                 ; 0.456             ;
+; spi2dac:dac|sr_state.WAIT_CSB_FALL     ; spi2dac:dac|sr_state.IDLE                                                                              ; 0.428             ;
+; spi2adc:SPI_ADC|sr_state.WAIT_CSB_HIGH ; spi2adc:SPI_ADC|sr_state.IDLE                                                                          ; 0.423             ;
+; spi2dac:dac|sr_state.IDLE              ; spi2dac:dac|sr_state.WAIT_CSB_FALL                                                                     ; 0.419             ;
+; spi2dac:dac|sr_state.WAIT_CSB_HIGH     ; spi2dac:dac|sr_state.IDLE                                                                              ; 0.415             ;
+; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; spi2adc:SPI_ADC|adc_start                                                                              ; 0.383             ;
+; pwm:p|count[7]                         ; pwm:p|pwm_out                                                                                          ; 0.322             ;
+; pwm:p|count[8]                         ; pwm:p|pwm_out                                                                                          ; 0.294             ;
+; pwm:p|d[8]                             ; pwm:p|pwm_out                                                                                          ; 0.281             ;
+; pwm:p|count[5]                         ; pwm:p|pwm_out                                                                                          ; 0.272             ;
+; spi2adc:SPI_ADC|adc_done               ; spi2adc:SPI_ADC|data_from_adc[1]                                                                       ; 0.268             ;
+; spi2adc:SPI_ADC|shift_reg[9]           ; spi2adc:SPI_ADC|data_from_adc[9]                                                                       ; 0.226             ;
+; pwm:p|d[9]                             ; pwm:p|pwm_out                                                                                          ; 0.219             ;
+; pwm:p|d[6]                             ; pwm:p|pwm_out                                                                                          ; 0.211             ;
+; pwm:p|count[6]                         ; pwm:p|pwm_out                                                                                          ; 0.208             ;
+; pwm:p|d[7]                             ; pwm:p|pwm_out                                                                                          ; 0.151             ;
+; pwm:p|d[5]                             ; pwm:p|pwm_out                                                                                          ; 0.138             ;
+; pwm:p|d[4]                             ; pwm:p|pwm_out                                                                                          ; 0.138             ;
+; pwm:p|d[3]                             ; pwm:p|pwm_out                                                                                          ; 0.138             ;
+; pwm:p|d[2]                             ; pwm:p|pwm_out                                                                                          ; 0.138             ;
+; pwm:p|d[1]                             ; pwm:p|pwm_out                                                                                          ; 0.138             ;
++----------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
 
 
 +-----------------+
@@ -2052,18 +2068,18 @@ Note: This table only shows the top 86 path(s) that have the largest delay added
 +-----------------+
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex10"
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
 Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
 Info (184020): Starting Fitter periphery placement operations
 Info (11191): Automatically promoted 1 clock (1 global)
-    Info (11162): CLOCK_50~inputCLKENA0 with 28 fanout uses global clock CLKCTRL_G6
+    Info (11162): CLOCK_50~inputCLKENA0 with 59 fanout uses global clock CLKCTRL_G6
 Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
 Info (176233): Starting register packing
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
 Info (332144): No user constrained base clocks found in the design
 Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
@@ -2071,20 +2087,32 @@ Info (332130): Timing requirements not specified -- quality metrics such as perf
 Info (176235): Finished register packing
     Extra Info (176219): No registers were packed into other blocks
 Warning (15705): Ignored locations or region assignments to the following nodes
-    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
     Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
     Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
     Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
@@ -2104,10 +2132,11 @@ Info (170137): Fitter placement was successful
 Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
 Info (170193): Fitter routing operations beginning
 Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
+    Info (170196): Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10
+Info (188005): Design requires adding a large amount of routing delay for some signals to meet hold time requirements, and there is an excessive demand for the available routing resources. The Fitter is reducing the routing delays of some signals to help the routing algorithm converge, but doing so may cause hold time failures. For more information, refer to the "Estimated Delay Added for Hold Timing" section in the Fitter report.
 Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
     Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:12
 Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
@@ -2115,17 +2144,17 @@ Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 30 warnings
-    Info: Peak virtual memory: 2617 megabytes
-    Info: Processing ended: Fri Nov 25 11:27:54 2016
-    Info: Elapsed time: 00:00:35
-    Info: Total CPU time (on all processors): 00:01:03
+Info (144001): Generated suppressed messages file /Desktop/ex15/output_files/ex10.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 41 warnings
+    Info: Peak virtual memory: 2755 megabytes
+    Info: Processing ended: Fri Dec 02 18:32:11 2016
+    Info: Elapsed time: 00:00:47
+    Info: Total CPU time (on all processors): 00:01:11
 
 
 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in C:/New folder/ex9/output_files/ex9.fit.smsg.
+The suppressed messages can be found in /Desktop/ex15/output_files/ex10.fit.smsg.
 
 
diff --git a/part_2/ex9_partially_working/output_files/ex9.fit.smsg b/part_3/ex15/output_files/ex10.fit.smsg
index 43eead5..43eead5 100755
--- a/part_2/ex9_partially_working/output_files/ex9.fit.smsg
+++ b/part_3/ex15/output_files/ex10.fit.smsg
diff --git a/part_3/ex15/output_files/ex10.fit.summary b/part_3/ex15/output_files/ex10.fit.summary
new file mode 100755
index 0000000..549091c
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Fri Dec 02 18:32:08 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex10
+Top-level Entity Name : ex15
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 146 / 32,070 ( < 1 % )
+Total registers : 130
+Total pins : 45 / 457 ( 10 % )
+Total virtual pins : 0
+Total block memory bits : 10,240 / 4,065,280 ( < 1 % )
+Total RAM Blocks : 1 / 397 ( < 1 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_3/ex15/output_files/ex10.flow.rpt b/part_3/ex15/output_files/ex10.flow.rpt
new file mode 100755
index 0000000..8017c2e
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.flow.rpt
@@ -0,0 +1,136 @@
+Flow report for ex10
+Fri Dec 02 18:32:41 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Fri Dec 02 18:32:41 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex10                                            ;
+; Top-level Entity Name           ; ex15                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 146 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 130                                             ;
+; Total pins                      ; 45 / 457 ( 10 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 10,240 / 4,065,280 ( < 1 % )                    ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 12/02/2016 18:31:06 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex10                ;
++-------------------+---------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                           ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id     ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID               ; 260248564477497.148070346608980       ; --            ; --          ; --             ;
+; EDA_OUTPUT_DATA_FORMAT              ; Verilog Hdl                           ; --            ; --          ; eda_simulation ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)             ; <None>        ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --             ;
+; MISC_FILE                           ; verilog_files/ROM_bb.v                ; --            ; --          ; --             ;
+; MISC_FILE                           ; const_mult_bb.v                       ; --            ; --          ; --             ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; ex15        ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; ex15        ; Top            ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; ex15        ; Top            ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --             ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --             ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --             ;
+; TOP_LEVEL_ENTITY                    ; ex15                                  ; ex10          ; --          ; --             ;
++-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:13     ; 1.0                     ; 918 MB              ; 00:00:22                           ;
+; Fitter                    ; 00:00:44     ; 1.0                     ; 2755 MB             ; 00:01:10                           ;
+; Assembler                 ; 00:00:10     ; 1.0                     ; 897 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:09     ; 1.1                     ; 1247 MB             ; 00:00:07                           ;
+; EDA Netlist Writer        ; 00:00:02     ; 1.0                     ; 816 MB              ; 00:00:01                           ;
+; Total                     ; 00:01:18     ; --                      ; --                  ; 00:01:46                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
+; EDA Netlist Writer        ; eews104a-002     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10
+quartus_fit --read_settings_files=off --write_settings_files=off ex10 -c ex10
+quartus_asm --read_settings_files=off --write_settings_files=off ex10 -c ex10
+quartus_sta ex10 -c ex10
+quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10
+
+
+
diff --git a/part_3/ex15/output_files/ex10.jdi b/part_3/ex15/output_files/ex10.jdi
new file mode 100755
index 0000000..703b411
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="c4bdb5eeac19da9532da"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex10.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_3/ex15/output_files/ex10.map.rpt b/part_3/ex15/output_files/ex10.map.rpt
new file mode 100755
index 0000000..9522b12
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.map.rpt
@@ -0,0 +1,842 @@
+Analysis & Synthesis report for ex10
+Fri Dec 02 18:31:20 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |ex15|spi2dac:dac|sr_state
+ 11. State Machine - |ex15|spi2adc:SPI_ADC|sr_state
+ 12. Registers Removed During Synthesis
+ 13. Removed Registers Triggering Further Register Optimizations
+ 14. General Register Statistics
+ 15. Inverted Register Statistics
+ 16. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 17. Source assignments for ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated
+ 18. Parameter Settings for User Entity Instance: tick_5000:tick
+ 19. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC
+ 20. Parameter Settings for User Entity Instance: ROM:rom|altsyncram:altsyncram_component
+ 21. Parameter Settings for User Entity Instance: spi2dac:dac
+ 22. Parameter Settings for User Entity Instance: const_mult:mult|lpm_mult:lpm_mult_component
+ 23. altsyncram Parameter Settings by Entity Instance
+ 24. lpm_mult Parameter Settings by Entity Instance
+ 25. Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A18"
+ 26. Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A9"
+ 27. Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A3"
+ 28. Port Connectivity Checks: "bin2bcd_16:bcd"
+ 29. Port Connectivity Checks: "const_mult:mult"
+ 30. Port Connectivity Checks: "spi2adc:SPI_ADC"
+ 31. Post-Synthesis Netlist Statistics for Top Partition
+ 32. Elapsed Time Per Partition
+ 33. Analysis & Synthesis Messages
+ 34. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Fri Dec 02 18:31:20 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex10                                            ;
+; Top-level Entity Name           ; ex15                                            ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 110                                             ;
+; Total pins                      ; 45                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 10,240                                          ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex15               ; ex10               ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                         ;
++----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                              ; File Name with Absolute Path                                           ; Library ;
++----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+
+; verilog_files/spi2adc.v          ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2adc.v       ;         ;
+; ex15.v                           ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v                        ;         ;
+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/add3_ge5.v      ;         ;
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/hex_to_7seg.v   ;         ;
+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v    ;         ;
+; verilog_files/ROM.v              ; yes             ; User Wizard-Generated File             ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v           ;         ;
+; verilog_files/tick_5000.v        ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/tick_5000.v     ;         ;
+; verilog_files/spi2dac.v          ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2dac.v       ;         ;
+; verilog_files/pwm.v              ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/pwm.v           ;         ;
+; const_mult.v                     ; yes             ; User Wizard-Generated File             ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v                  ;         ;
+; add_offset.v                     ; yes             ; User Verilog HDL File                  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/add_offset.v                  ;         ;
+; altsyncram.tdf                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf          ;         ;
+; stratix_ram_block.inc            ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/stratix_ram_block.inc   ;         ;
+; lpm_mux.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_mux.inc             ;         ;
+; lpm_decode.inc                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_decode.inc          ;         ;
+; aglobal160.inc                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc          ;         ;
+; a_rdenreg.inc                    ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/a_rdenreg.inc           ;         ;
+; altrom.inc                       ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altrom.inc              ;         ;
+; altram.inc                       ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altram.inc              ;         ;
+; altdpram.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altdpram.inc            ;         ;
+; db/altsyncram_6ng1.tdf           ; yes             ; Auto-Generated Megafunction            ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/altsyncram_6ng1.tdf        ;         ;
+; rom_data/rom_data.mif            ; yes             ; Auto-Found Memory Initialization File  ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/rom_data/rom_data.mif         ;         ;
+; lpm_mult.tdf                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf            ;         ;
+; lpm_add_sub.inc                  ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.inc         ;         ;
+; multcore.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/multcore.inc            ;         ;
+; bypassff.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/bypassff.inc            ;         ;
+; altshift.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altshift.inc            ;         ;
+; multcore.tdf                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf            ;         ;
+; csa_add.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/csa_add.inc             ;         ;
+; mpar_add.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.inc            ;         ;
+; muleabz.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/muleabz.inc             ;         ;
+; mul_lfrg.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/mul_lfrg.inc            ;         ;
+; mul_boothc.inc                   ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/mul_boothc.inc          ;         ;
+; alt_ded_mult.inc                 ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult.inc        ;         ;
+; alt_ded_mult_y.inc               ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult_y.inc      ;         ;
+; dffpipe.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/dffpipe.inc             ;         ;
+; mpar_add.tdf                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf            ;         ;
+; lpm_add_sub.tdf                  ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;         ;
+; addcore.inc                      ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/addcore.inc             ;         ;
+; look_add.inc                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/look_add.inc            ;         ;
+; alt_stratix_add_sub.inc          ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;         ;
+; db/add_sub_d9h.tdf               ; yes             ; Auto-Generated Megafunction            ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/add_sub_d9h.tdf            ;         ;
+; db/add_sub_89h.tdf               ; yes             ; Auto-Generated Megafunction            ; //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/add_sub_89h.tdf            ;         ;
+; altshift.tdf                     ; yes             ; Megafunction                           ; c:/altera/16.0/quartus/libraries/megafunctions/altshift.tdf            ;         ;
++----------------------------------+-----------------+----------------------------------------+------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimate of Logic utilization (ALMs needed) ; 146            ;
+;                                             ;                ;
+; Combinational ALUT usage for logic          ; 257            ;
+;     -- 7 input functions                    ; 0              ;
+;     -- 6 input functions                    ; 22             ;
+;     -- 5 input functions                    ; 25             ;
+;     -- 4 input functions                    ; 124            ;
+;     -- <=3 input functions                  ; 86             ;
+;                                             ;                ;
+; Dedicated logic registers                   ; 110            ;
+;                                             ;                ;
+; I/O pins                                    ; 45             ;
+; Total MLAB memory bits                      ; 0              ;
+; Total block memory bits                     ; 10240          ;
+;                                             ;                ;
+; Total DSP Blocks                            ; 0              ;
+;                                             ;                ;
+; Maximum fan-out node                        ; CLOCK_50~input ;
+; Maximum fan-out                             ; 62             ;
+; Total fan-out                               ; 1435           ;
+; Average fan-out                             ; 3.07           ;
++---------------------------------------------+----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                      ;
++---------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                        ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                       ; Entity Name     ; Library Name ;
++---------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex15                                             ; 257 (0)           ; 110 (0)      ; 10240             ; 0          ; 45   ; 0            ; |ex15                                                                                                                                                     ; ex15            ; work         ;
+;    |ROM:rom|                                      ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex15|ROM:rom                                                                                                                                             ; ROM             ; work         ;
+;       |altsyncram:altsyncram_component|           ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex15|ROM:rom|altsyncram:altsyncram_component                                                                                                             ; altsyncram      ; work         ;
+;          |altsyncram_6ng1:auto_generated|         ; 0 (0)             ; 0 (0)        ; 10240             ; 0          ; 0    ; 0            ; |ex15|ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated                                                                              ; altsyncram_6ng1 ; work         ;
+;    |add_offset:fin_address|                       ; 10 (10)           ; 10 (10)      ; 0                 ; 0          ; 0    ; 0            ; |ex15|add_offset:fin_address                                                                                                                              ; add_offset      ; work         ;
+;    |bin2bcd_16:bcd|                               ; 97 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd                                                                                                                                      ; bin2bcd_16      ; work         ;
+;       |add3_ge5:A10|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A10                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A11|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A11                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A12|                              ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A12                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A13|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A13                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A14|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A14                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A15|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A15                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A16|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A16                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A17|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A17                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A19|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A19                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A1|                               ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A1                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A20|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A20                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A21|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A21                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A22|                              ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A22                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A23|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A23                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A24|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A24                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A25|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A25                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A26|                              ; 9 (9)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A26                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A27|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A27                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A28|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A28                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A29|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A29                                                                                                                         ; add3_ge5        ; work         ;
+;       |add3_ge5:A2|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A2                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A4|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A4                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A5|                               ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A5                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A6|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A6                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A7|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A7                                                                                                                          ; add3_ge5        ; work         ;
+;       |add3_ge5:A8|                               ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|bin2bcd_16:bcd|add3_ge5:A8                                                                                                                          ; add3_ge5        ; work         ;
+;    |const_mult:mult|                              ; 36 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult                                                                                                                                     ; const_mult      ; work         ;
+;       |lpm_mult:lpm_mult_component|               ; 36 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component                                                                                                         ; lpm_mult        ; work         ;
+;          |multcore:mult_core|                     ; 36 (6)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core                                                                                      ; multcore        ; work         ;
+;             |mpar_add:padder|                     ; 30 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder                                                                      ; mpar_add        ; work         ;
+;                |lpm_add_sub:adder[0]|             ; 18 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; lpm_add_sub     ; work         ;
+;                   |add_sub_d9h:auto_generated|    ; 18 (18)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated                      ; add_sub_d9h     ; work         ;
+;                |mpar_add:sub_par_add|             ; 12 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; mpar_add        ; work         ;
+;                   |lpm_add_sub:adder[0]|          ; 12 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; lpm_add_sub     ; work         ;
+;                      |add_sub_89h:auto_generated| ; 12 (12)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated ; add_sub_89h     ; work         ;
+;    |hex_to_7seg:h0|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h0                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h1|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h1                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h2|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h2                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h3|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h3                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:h4|                               ; 3 (3)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex15|hex_to_7seg:h4                                                                                                                                      ; hex_to_7seg     ; work         ;
+;    |pwm:p|                                        ; 16 (16)           ; 21 (21)      ; 0                 ; 0          ; 0    ; 0            ; |ex15|pwm:p                                                                                                                                               ; pwm             ; work         ;
+;    |spi2adc:SPI_ADC|                              ; 21 (21)           ; 39 (39)      ; 0                 ; 0          ; 0    ; 0            ; |ex15|spi2adc:SPI_ADC                                                                                                                                     ; spi2adc         ; work         ;
+;    |spi2dac:dac|                                  ; 19 (19)           ; 23 (23)      ; 0                 ; 0          ; 0    ; 0            ; |ex15|spi2dac:dac                                                                                                                                         ; spi2dac         ; work         ;
+;    |tick_5000:tick|                               ; 27 (27)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex15|tick_5000:tick                                                                                                                                      ; tick_5000       ; work         ;
++---------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                              ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+; Name                                                                              ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                     ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+; ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 1024         ; 10           ; --           ; --           ; 10240 ; ./rom_data/rom_data.mif ;
++-----------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                   ;
++--------+--------------+---------+--------------+--------------+-----------------------+-----------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance       ; IP Include File ;
++--------+--------------+---------+--------------+--------------+-----------------------+-----------------+
+; Altera ; LPM_MULT     ; 16.1    ; N/A          ; N/A          ; |ex15|const_mult:mult ; const_mult.v    ;
++--------+--------------+---------+--------------+--------------+-----------------------+-----------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex15|spi2dac:dac|sr_state                                               ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex15|spi2adc:SPI_ADC|sr_state                                           ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                             ;
++---------------------------------------+----------------------------------------+
+; Register name                         ; Reason for Removal                     ;
++---------------------------------------+----------------------------------------+
+; spi2dac:dac|shift_reg[0,1]            ; Stuck at GND due to stuck port data_in ;
+; spi2dac:dac|ctr[4]                    ; Merged with spi2adc:SPI_ADC|ctr[4]     ;
+; spi2dac:dac|ctr[3]                    ; Merged with spi2adc:SPI_ADC|ctr[3]     ;
+; spi2dac:dac|ctr[2]                    ; Merged with spi2adc:SPI_ADC|ctr[2]     ;
+; spi2dac:dac|ctr[1]                    ; Merged with spi2adc:SPI_ADC|ctr[1]     ;
+; spi2dac:dac|ctr[0]                    ; Merged with spi2adc:SPI_ADC|ctr[0]     ;
+; Total Number of Removed Registers = 7 ;                                        ;
++---------------------------------------+----------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                   ;
++--------------------------+---------------------------+----------------------------------------+
+; Register name            ; Reason for Removal        ; Registers Removed due to This Register ;
++--------------------------+---------------------------+----------------------------------------+
+; spi2dac:dac|shift_reg[0] ; Stuck at GND              ; spi2dac:dac|shift_reg[1]               ;
+;                          ; due to stuck port data_in ;                                        ;
++--------------------------+---------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 110   ;
+; Number of registers using Synchronous Clear  ; 9     ;
+; Number of registers using Synchronous Load   ; 9     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 32    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; spi2adc:SPI_ADC|adc_cs                 ; 7       ;
+; tick_5000:tick|count[9]                ; 2       ;
+; tick_5000:tick|count[0]                ; 2       ;
+; tick_5000:tick|count[1]                ; 2       ;
+; tick_5000:tick|count[2]                ; 2       ;
+; tick_5000:tick|count[7]                ; 2       ;
+; tick_5000:tick|count[8]                ; 2       ;
+; tick_5000:tick|count[12]               ; 2       ;
+; Total number of inverted registers = 8 ;         ;
++----------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |ex15|spi2dac:dac|Selector1 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; Source assignments for ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated ;
++---------------------------------+--------------------+------+---------------------------------+
+; Assignment                      ; Value              ; From ; To                              ;
++---------------------------------+--------------------+------+---------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                               ;
++---------------------------------+--------------------+------+---------------------------------+
+
+
++-------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: tick_5000:tick ;
++----------------+-------+------------------------------------+
+; Parameter Name ; Value ; Type                               ;
++----------------+-------+------------------------------------+
+; NBIT           ; 16    ; Signed Integer                     ;
++----------------+-------+------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; SGL            ; 1     ; Unsigned Binary                     ;
+; MSBF           ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: ROM:rom|altsyncram:altsyncram_component ;
++------------------------------------+-------------------------+-----------------------+
+; Parameter Name                     ; Value                   ; Type                  ;
++------------------------------------+-------------------------+-----------------------+
+; BYTE_SIZE_BLOCK                    ; 8                       ; Untyped               ;
+; AUTO_CARRY_CHAINS                  ; ON                      ; AUTO_CARRY            ;
+; IGNORE_CARRY_BUFFERS               ; OFF                     ; IGNORE_CARRY          ;
+; AUTO_CASCADE_CHAINS                ; ON                      ; AUTO_CASCADE          ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                     ; IGNORE_CASCADE        ;
+; WIDTH_BYTEENA                      ; 1                       ; Untyped               ;
+; OPERATION_MODE                     ; ROM                     ; Untyped               ;
+; WIDTH_A                            ; 10                      ; Signed Integer        ;
+; WIDTHAD_A                          ; 10                      ; Signed Integer        ;
+; NUMWORDS_A                         ; 1024                    ; Signed Integer        ;
+; OUTDATA_REG_A                      ; CLOCK0                  ; Untyped               ;
+; ADDRESS_ACLR_A                     ; NONE                    ; Untyped               ;
+; OUTDATA_ACLR_A                     ; NONE                    ; Untyped               ;
+; WRCONTROL_ACLR_A                   ; NONE                    ; Untyped               ;
+; INDATA_ACLR_A                      ; NONE                    ; Untyped               ;
+; BYTEENA_ACLR_A                     ; NONE                    ; Untyped               ;
+; WIDTH_B                            ; 1                       ; Untyped               ;
+; WIDTHAD_B                          ; 1                       ; Untyped               ;
+; NUMWORDS_B                         ; 1                       ; Untyped               ;
+; INDATA_REG_B                       ; CLOCK1                  ; Untyped               ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                  ; Untyped               ;
+; RDCONTROL_REG_B                    ; CLOCK1                  ; Untyped               ;
+; ADDRESS_REG_B                      ; CLOCK1                  ; Untyped               ;
+; OUTDATA_REG_B                      ; UNREGISTERED            ; Untyped               ;
+; BYTEENA_REG_B                      ; CLOCK1                  ; Untyped               ;
+; INDATA_ACLR_B                      ; NONE                    ; Untyped               ;
+; WRCONTROL_ACLR_B                   ; NONE                    ; Untyped               ;
+; ADDRESS_ACLR_B                     ; NONE                    ; Untyped               ;
+; OUTDATA_ACLR_B                     ; NONE                    ; Untyped               ;
+; RDCONTROL_ACLR_B                   ; NONE                    ; Untyped               ;
+; BYTEENA_ACLR_B                     ; NONE                    ; Untyped               ;
+; WIDTH_BYTEENA_A                    ; 1                       ; Signed Integer        ;
+; WIDTH_BYTEENA_B                    ; 1                       ; Untyped               ;
+; RAM_BLOCK_TYPE                     ; AUTO                    ; Untyped               ;
+; BYTE_SIZE                          ; 8                       ; Untyped               ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE               ; Untyped               ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ    ; Untyped               ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ    ; Untyped               ;
+; INIT_FILE                          ; ./rom_data/rom_data.mif ; Untyped               ;
+; INIT_FILE_LAYOUT                   ; PORT_A                  ; Untyped               ;
+; MAXIMUM_DEPTH                      ; 0                       ; Untyped               ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS                  ; Untyped               ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL                  ; Untyped               ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS                  ; Untyped               ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                  ; Untyped               ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN         ; Untyped               ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN         ; Untyped               ;
+; ENABLE_ECC                         ; FALSE                   ; Untyped               ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                   ; Untyped               ;
+; WIDTH_ECCSTATUS                    ; 3                       ; Untyped               ;
+; DEVICE_FAMILY                      ; Cyclone V               ; Untyped               ;
+; CBXI_PARAMETER                     ; altsyncram_6ng1         ; Untyped               ;
++------------------------------------+-------------------------+-----------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2dac:dac ;
++----------------+-------+---------------------------------+
+; Parameter Name ; Value ; Type                            ;
++----------------+-------+---------------------------------+
+; BUF            ; 1     ; Unsigned Binary                 ;
+; GA_N           ; 1     ; Unsigned Binary                 ;
+; SHDN_N         ; 1     ; Unsigned Binary                 ;
+; TC             ; 11000 ; Unsigned Binary                 ;
+; IDLE           ; 00    ; Unsigned Binary                 ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                 ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                 ;
++----------------+-------+---------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: const_mult:mult|lpm_mult:lpm_mult_component ;
++------------------------------------------------+-----------+-----------------------------+
+; Parameter Name                                 ; Value     ; Type                        ;
++------------------------------------------------+-----------+-----------------------------+
+; AUTO_CARRY_CHAINS                              ; ON        ; AUTO_CARRY                  ;
+; IGNORE_CARRY_BUFFERS                           ; OFF       ; IGNORE_CARRY                ;
+; AUTO_CASCADE_CHAINS                            ; ON        ; AUTO_CASCADE                ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF       ; IGNORE_CASCADE              ;
+; LPM_WIDTHA                                     ; 10        ; Signed Integer              ;
+; LPM_WIDTHB                                     ; 14        ; Signed Integer              ;
+; LPM_WIDTHP                                     ; 24        ; Signed Integer              ;
+; LPM_WIDTHR                                     ; 0         ; Untyped                     ;
+; LPM_WIDTHS                                     ; 1         ; Untyped                     ;
+; LPM_REPRESENTATION                             ; UNSIGNED  ; Untyped                     ;
+; LPM_PIPELINE                                   ; 0         ; Untyped                     ;
+; LATENCY                                        ; 0         ; Untyped                     ;
+; INPUT_A_IS_CONSTANT                            ; NO        ; Untyped                     ;
+; INPUT_B_IS_CONSTANT                            ; YES       ; Untyped                     ;
+; USE_EAB                                        ; OFF       ; Untyped                     ;
+; MAXIMIZE_SPEED                                 ; 5         ; Untyped                     ;
+; DEVICE_FAMILY                                  ; Cyclone V ; Untyped                     ;
+; CARRY_CHAIN                                    ; MANUAL    ; Untyped                     ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT       ; TECH_MAPPER_APEX20K         ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO      ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0         ; Untyped                     ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0         ; Untyped                     ;
+; CBXI_PARAMETER                                 ; NOTHING   ; Untyped                     ;
+; INPUT_A_FIXED_VALUE                            ; Bx        ; Untyped                     ;
+; INPUT_B_FIXED_VALUE                            ; Bx        ; Untyped                     ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF       ; Untyped                     ;
++------------------------------------------------+-----------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance                                    ;
++-------------------------------------------+-----------------------------------------+
+; Name                                      ; Value                                   ;
++-------------------------------------------+-----------------------------------------+
+; Number of entity instances                ; 1                                       ;
+; Entity Instance                           ; ROM:rom|altsyncram:altsyncram_component ;
+;     -- OPERATION_MODE                     ; ROM                                     ;
+;     -- WIDTH_A                            ; 10                                      ;
+;     -- NUMWORDS_A                         ; 1024                                    ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                  ;
+;     -- WIDTH_B                            ; 1                                       ;
+;     -- NUMWORDS_B                         ; 1                                       ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                  ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                    ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                               ;
++-------------------------------------------+-----------------------------------------+
+
+
++-------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                      ;
++---------------------------------------+---------------------------------------------+
+; Name                                  ; Value                                       ;
++---------------------------------------+---------------------------------------------+
+; Number of entity instances            ; 1                                           ;
+; Entity Instance                       ; const_mult:mult|lpm_mult:lpm_mult_component ;
+;     -- LPM_WIDTHA                     ; 10                                          ;
+;     -- LPM_WIDTHB                     ; 14                                          ;
+;     -- LPM_WIDTHP                     ; 24                                          ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                    ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                          ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                         ;
+;     -- USE_EAB                        ; OFF                                         ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                        ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                          ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                          ;
++---------------------------------------+---------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A18" ;
++------+-------+----------+-------------------------------+
+; Port ; Type  ; Severity ; Details                       ;
++------+-------+----------+-------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                  ;
++------+-------+----------+-------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A9" ;
++------+-------+----------+------------------------------+
+; Port ; Type  ; Severity ; Details                      ;
++------+-------+----------+------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                 ;
++------+-------+----------+------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:bcd|add3_ge5:A3" ;
++------+-------+----------+------------------------------+
+; Port ; Type  ; Severity ; Details                      ;
++------+-------+----------+------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                 ;
++------+-------+----------+------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "bin2bcd_16:bcd"                                                                                                                              ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                                                                                                       ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; B    ; Input ; Warning  ; Input port expression (14 bits) is smaller than the input port (16 bits) it drives.  Extra input bit(s) "B[15..14]" will be connected to GND. ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "const_mult:mult"                                                                            ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                             ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+; result[9..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++--------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------+
+; Port Connectivity Checks: "spi2adc:SPI_ADC"             ;
++------------+--------+----------+------------------------+
+; Port       ; Type   ; Severity ; Details                ;
++------------+--------+----------+------------------------+
+; channel    ; Input  ; Info     ; Stuck at GND           ;
+; data_valid ; Output ; Info     ; Explicitly unconnected ;
++------------+--------+----------+------------------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 110                         ;
+;     ENA               ; 32                          ;
+;     SCLR              ; 9                           ;
+;     SLD               ; 9                           ;
+;     plain             ; 60                          ;
+; arriav_lcell_comb     ; 280                         ;
+;     arith             ; 65                          ;
+;         0 data inputs ; 2                           ;
+;         1 data inputs ; 31                          ;
+;         2 data inputs ; 16                          ;
+;         3 data inputs ; 5                           ;
+;         4 data inputs ; 5                           ;
+;         5 data inputs ; 6                           ;
+;     normal            ; 215                         ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 32                          ;
+;         2 data inputs ; 8                           ;
+;         3 data inputs ; 14                          ;
+;         4 data inputs ; 119                         ;
+;         5 data inputs ; 19                          ;
+;         6 data inputs ; 22                          ;
+; boundary_port         ; 45                          ;
+; stratixv_ram_block    ; 10                          ;
+;                       ;                             ;
+; Max LUT depth         ; 17.00                       ;
+; Average LUT depth     ; 8.36                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:01     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 18:31:06 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex10 -c ex10
+Critical Warning (136021): Ignored assignment IO_STANDARD which contains an invalid node name "LEDR[3]#============================================================"
+Critical Warning (136021): Ignored assignment IO_STANDARD which contains an invalid node name "LEDR[3]#============================================================"
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v
+    Info (12023): Found entity 1: spi2adc File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2adc.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file ex15.v
+    Info (12023): Found entity 1: ex15 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/add3_ge5.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/hex_to_7seg.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/rom.v
+    Info (12023): Found entity 1: ROM File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/tick_5000.v
+    Info (12023): Found entity 1: tick_5000 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/tick_5000.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v
+    Info (12023): Found entity 1: spi2dac File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2dac.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/pwm.v
+    Info (12023): Found entity 1: pwm File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/pwm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file const_mult.v
+    Info (12023): Found entity 1: const_mult File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file add_offset.v
+    Info (12023): Found entity 1: add_offset File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/add_offset.v Line: 1
+Info (12127): Elaborating entity "ex15" for the top level hierarchy
+Info (12128): Elaborating entity "tick_5000" for hierarchy "tick_5000:tick" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 17
+Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 30
+Info (12128): Elaborating entity "add_offset" for hierarchy "add_offset:fin_address" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 32
+Info (12128): Elaborating entity "ROM" for hierarchy "ROM:rom" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 34
+Info (12128): Elaborating entity "altsyncram" for hierarchy "ROM:rom|altsyncram:altsyncram_component" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v Line: 82
+Info (12130): Elaborated megafunction instantiation "ROM:rom|altsyncram:altsyncram_component" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v Line: 82
+Info (12133): Instantiated megafunction "ROM:rom|altsyncram:altsyncram_component" with the following parameter: File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v Line: 82
+    Info (12134): Parameter "address_aclr_a" = "NONE"
+    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
+    Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
+    Info (12134): Parameter "init_file" = "./rom_data/rom_data.mif"
+    Info (12134): Parameter "intended_device_family" = "Cyclone V"
+    Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
+    Info (12134): Parameter "lpm_type" = "altsyncram"
+    Info (12134): Parameter "numwords_a" = "1024"
+    Info (12134): Parameter "operation_mode" = "ROM"
+    Info (12134): Parameter "outdata_aclr_a" = "NONE"
+    Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
+    Info (12134): Parameter "widthad_a" = "10"
+    Info (12134): Parameter "width_a" = "10"
+    Info (12134): Parameter "width_byteena_a" = "1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_6ng1.tdf
+    Info (12023): Found entity 1: altsyncram_6ng1 File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/altsyncram_6ng1.tdf Line: 28
+Info (12128): Elaborating entity "altsyncram_6ng1" for hierarchy "ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 792
+Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:dac" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 36
+Info (12128): Elaborating entity "pwm" for hierarchy "pwm:p" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 37
+Info (12128): Elaborating entity "const_mult" for hierarchy "const_mult:mult" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 39
+Info (12128): Elaborating entity "lpm_mult" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v Line: 59
+Info (12130): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v Line: 59
+Info (12133): Instantiated megafunction "const_mult:mult|lpm_mult:lpm_mult_component" with the following parameter: File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v Line: 59
+    Info (12134): Parameter "lpm_hint" = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+    Info (12134): Parameter "lpm_representation" = "UNSIGNED"
+    Info (12134): Parameter "lpm_type" = "LPM_MULT"
+    Info (12134): Parameter "lpm_widtha" = "10"
+    Info (12134): Parameter "lpm_widthb" = "14"
+    Info (12134): Parameter "lpm_widthp" = "24"
+Info (12128): Elaborating entity "multcore" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309
+Info (12128): Elaborating entity "mpar_add" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder" File: c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf Line: 229
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf Line: 229
+Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_d9h.tdf
+    Info (12023): Found entity 1: add_sub_d9h File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/add_sub_d9h.tdf Line: 23
+Info (12128): Elaborating entity "add_sub_d9h" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119
+Info (12128): Elaborating entity "mpar_add" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
+Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_89h.tdf
+    Info (12023): Found entity 1: add_sub_89h File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/add_sub_89h.tdf Line: 23
+Info (12128): Elaborating entity "add_sub_89h" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119
+Info (12128): Elaborating entity "altshift" for hierarchy "const_mult:mult|lpm_mult:lpm_mult_component|altshift:external_latency_ffs" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352
+Info (12131): Elaborated megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component|altshift:external_latency_ffs", which is child of megafunction instantiation "const_mult:mult|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "bin2bcd_16:bcd" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 41
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "bin2bcd_16:bcd|add3_ge5:A1" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:h0" File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 43
+Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX4[1]" is stuck at GND File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v Line: 5
+Info (286030): Timing-Driven Synthesis is running
+Info (144001): Generated suppressed messages file /Desktop/ex15/output_files/ex10.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 352 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 2 input pins
+    Info (21059): Implemented 43 output pins
+    Info (21061): Implemented 297 logic cells
+    Info (21064): Implemented 10 RAM segments
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 918 megabytes
+    Info: Processing ended: Fri Dec 02 18:31:20 2016
+    Info: Elapsed time: 00:00:14
+    Info: Total CPU time (on all processors): 00:00:23
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in /Desktop/ex15/output_files/ex10.map.smsg.
+
+
diff --git a/part_3/ex15/output_files/ex10.map.smsg b/part_3/ex15/output_files/ex10.map.smsg
new file mode 100755
index 0000000..0d3862e
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.map.smsg
@@ -0,0 +1,29 @@
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_3/ex15/output_files/ex10.map.summary b/part_3/ex15/output_files/ex10.map.summary
new file mode 100755
index 0000000..e8914b6
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Fri Dec 02 18:31:20 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex10
+Top-level Entity Name : ex15
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 110
+Total pins : 45
+Total virtual pins : 0
+Total block memory bits : 10,240
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_2/ex9_final/output_files/ex9.pin b/part_3/ex15/output_files/ex10.pin
index 6b2c6db..5ba008b 100755
--- a/part_2/ex9_final/output_files/ex9.pin
+++ b/part_3/ex15/output_files/ex10.pin
@@ -74,7 +74,7 @@
  ---------------------------------------------------------------------------------
 
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-CHIP  "ex9"  ASSIGNED TO AN: 5CSEMA5F31C6
+CHIP  "ex10"  ASSIGNED TO AN: 5CSEMA5F31C6
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
 -------------------------------------------------------------------------------------------------------------
@@ -119,8 +119,8 @@ VCCPD3A                      : AA10      : power  :                   : 2.5V
 GND                          : AA11      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
-KEY[0]                       : AA14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
-KEY[1]                       : AA15      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
 VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
@@ -130,10 +130,10 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :
 GND                          : AA22      : gnd    :                   :         :           :                
 VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
 HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[6]                      : AA25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[5]                      : AA26      : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
 VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
-HEX5[1]                      : AA28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
 VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
 GND                          : AB1       : gnd    :                   :         :           :                
@@ -161,8 +161,8 @@ HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :
 HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
 VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
 HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[4]                      : AB26      : output : 3.3-V LVTTL       :         : 5A        : Y              
-HEX5[3]                      : AB27      : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
 HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
 GND                          : AB29      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
@@ -215,7 +215,7 @@ VCCPD3B4A                    : AD16      : power  :                   : 3.3V
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
 VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD20      :        :                   :         : 4A        :                
+DAC_CS                       : AD20      : output : 3.3-V LVTTL       :         : 4A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
 VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
 GND                          : AD23      : gnd    :                   :         :           :                
@@ -275,8 +275,8 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :
 GND                          : AF17      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21      :        :                   :         : 4A        :                
+DAC_SCK                      : AF20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SCK                      : AF21      : output : 3.3-V LVTTL       :         : 4A        : Y              
 VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
@@ -303,10 +303,10 @@ GND                          : AG14      : gnd    :                   :
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18      :        :                   :         : 4A        :                
+DAC_SDI                      : AG18      : output : 3.3-V LVTTL       :         : 4A        : Y              
 VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21      :        :                   :         : 4A        :                
+ADC_CS                       : AG20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SDI                      : AG21      : output : 3.3-V LVTTL       :         : 4A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
 GND                          : AG24      : gnd    :                   :         :           :                
@@ -365,8 +365,8 @@ RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :
 RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
 GND                          : AJ18      : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20      :        :                   :         : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21      :        :                   :         : 4A        :                
+PWM_OUT                      : AJ20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SDO                      : AJ21      : input  : 3.3-V LVTTL       :         : 4A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
 VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
@@ -395,7 +395,7 @@ VREFB4AN0                    : AK17      : power  :                   :
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
 VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK21      :        :                   :         : 4A        :                
+DAC_LD                       : AK21      : output : 3.3-V LVTTL       :         : 4A        : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
@@ -899,16 +899,16 @@ GND                          : V12       : gnd    :                   :
 VCC                          : V13       : power  :                   : 1.1V    :           :                
 GND                          : V14       : gnd    :                   :         :           :                
 VCC                          : V15       : power  :                   : 1.1V    :           :                
-LEDR[0]                      : V16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[2]                      : V17       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[3]                      : V18       : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
 GND                          : V19       : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
 GND                          : V21       : gnd    :                   :         :           :                
 VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
 HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
 VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
-HEX5[0]                      : V25       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
 VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
@@ -928,13 +928,13 @@ GND                          : W11       : gnd    :                   :
 VCC                          : W12       : power  :                   : 1.1V    :           :                
 GND                          : W13       : gnd    :                   :         :           :                
 VCC                          : W14       : power  :                   : 1.1V    :           :                
-KEY[2]                       : W15       : input  : 3.3-V LVTTL       :         : 3B        : Y              
-LEDR[1]                      : W16       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[4]                      : W17       : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
 GND                          : W18       : gnd    :                   :         :           :                
-LEDR[5]                      : W19       : output : 3.3-V LVTTL       :         : 4A        : Y              
-LEDR[7]                      : W20       : output : 3.3-V LVTTL       :         : 5A        : Y              
-LEDR[8]                      : W21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                
 HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
 VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
 HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
@@ -959,18 +959,18 @@ GND                          : Y12       : gnd    :                   :
 VCC                          : Y13       : power  :                   : 1.1V    :           :                
 GND                          : Y14       : gnd    :                   :         :           :                
 GND                          : Y15       : gnd    :                   :         :           :                
-KEY[3]                       : Y16       : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
-LEDR[6]                      : Y19       : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
 GND                          : Y20       : gnd    :                   :         :           :                
-LEDR[9]                      : Y21       : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
 VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
 HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
 HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
 GND                          : Y25       : gnd    :                   :         :           :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
-HEX5[2]                      : Y27       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
 RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
 GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_2/ex9_partially_working/output_files/ex9.sld b/part_3/ex15/output_files/ex10.sld
index 41a6030..41a6030 100755
--- a/part_2/ex9_partially_working/output_files/ex9.sld
+++ b/part_3/ex15/output_files/ex10.sld
diff --git a/part_3/ex15/output_files/ex10.sof b/part_3/ex15/output_files/ex10.sof
new file mode 100755
index 0000000..aa055f7
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.sof
diff --git a/part_2/ex9_final/output_files/ex9.sta.rpt b/part_3/ex15/output_files/ex10.sta.rpt
index 49ef994..f90cbcd 100755
--- a/part_2/ex9_final/output_files/ex9.sta.rpt
+++ b/part_3/ex15/output_files/ex10.sta.rpt
@@ -1,5 +1,5 @@
-TimeQuest Timing Analyzer report for ex9
-Fri Nov 25 12:11:15 2016
+TimeQuest Timing Analyzer report for ex10
+Fri Dec 02 18:32:36 2016
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 
 
@@ -83,7 +83,7 @@ agreement for further details.
 +-----------------------+---------------------------------------------------------+
 ; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
 ; Timing Analyzer       ; TimeQuest                                               ;
-; Revision Name         ; ex9                                                     ;
+; Revision Name         ; ex10                                                    ;
 ; Device Family         ; Cyclone V                                               ;
 ; Device Name           ; 5CSEMA5F31C6                                            ;
 ; Timing Models         ; Final                                                   ;
@@ -100,26 +100,27 @@ agreement for further details.
 ; Number detected on machine ; 8           ;
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
-; Average used               ; 1.14        ;
+; Average used               ; 1.09        ;
 ; Maximum used               ; 4           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   4.8%      ;
-;     Processor 3            ;   4.8%      ;
-;     Processor 4            ;   4.7%      ;
+;     Processor 2            ;   3.0%      ;
+;     Processor 3            ;   3.0%      ;
+;     Processor 4            ;   2.9%      ;
 +----------------------------+-------------+
 
 
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                                                                                   ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
-; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                             ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+; Clock Name               ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                      ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+; CLOCK_50                 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                 ;
+; spi2adc:SPI_ADC|clk_1MHz ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2adc:SPI_ADC|clk_1MHz } ;
+; spi2dac:dac|clk_1MHz     ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2dac:dac|clk_1MHz }     ;
+; tick_5000:tick|CLK_OUT   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_5000:tick|CLK_OUT }   ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
 
 
 +----------------------------------------------------------------+
@@ -127,8 +128,10 @@ agreement for further details.
 +------------+-----------------+--------------------------+------+
 ; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
 +------------+-----------------+--------------------------+------+
-; 224.11 MHz ; 224.11 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 328.19 MHz ; 328.19 MHz      ; CLOCK_50                 ;      ;
+; 205.76 MHz ; 205.76 MHz      ; spi2adc:SPI_ADC|clk_1MHz ;      ;
+; 257.0 MHz  ; 257.0 MHz       ; spi2dac:dac|clk_1MHz     ;      ;
+; 277.7 MHz  ; 277.7 MHz       ; CLOCK_50                 ;      ;
+; 289.69 MHz ; 289.69 MHz      ; tick_5000:tick|CLK_OUT   ;      ;
 +------------+-----------------+--------------------------+------+
 This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
 
@@ -139,26 +142,28 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 HTML report is unavailable in plain text report export.
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -3.462 ; -161.413      ;
-; CLOCK_50                            ; -2.047 ; -40.775       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675 ; -1.675        ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary               ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; spi2dac:dac|clk_1MHz     ; -3.923 ; -65.134       ;
+; CLOCK_50                 ; -3.552 ; -146.301      ;
+; spi2adc:SPI_ADC|clk_1MHz ; -3.471 ; -56.704       ;
+; tick_5000:tick|CLK_OUT   ; -2.452 ; -23.249       ;
++--------------------------+--------+---------------+
 
 
-+-------------------------------------------------------------+
-; Slow 1100mV 85C Model Hold Summary                          ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.179 ; 0.000         ;
-; CLOCK_50                            ; 0.385 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.629 ; 0.000         ;
-+-------------------------------------+-------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -3.138 ; -49.029       ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.136  ; 0.000         ;
+; spi2dac:dac|clk_1MHz     ; 0.788  ; 0.000         ;
+; tick_5000:tick|CLK_OUT   ; 1.040  ; 0.000         ;
++--------------------------+--------+---------------+
 
 
 ------------------------------------------
@@ -173,15 +178,16 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.637 ; -18.132       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.762       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.459  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -111.881      ;
+; spi2adc:SPI_ADC|clk_1MHz ; -0.394 ; -19.666       ;
+; spi2dac:dac|clk_1MHz     ; -0.394 ; -11.148       ;
+; tick_5000:tick|CLK_OUT   ; -0.394 ; -5.310        ;
++--------------------------+--------+---------------+
 
 
 -----------------------------------------------
@@ -195,32 +201,36 @@ No synchronizer chains to report.
 +------------+-----------------+--------------------------+------+
 ; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
 +------------+-----------------+--------------------------+------+
-; 226.45 MHz ; 226.45 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 300.93 MHz ; 300.93 MHz      ; CLOCK_50                 ;      ;
+; 219.59 MHz ; 219.59 MHz      ; spi2adc:SPI_ADC|clk_1MHz ;      ;
+; 259.13 MHz ; 259.13 MHz      ; spi2dac:dac|clk_1MHz     ;      ;
+; 260.21 MHz ; 260.21 MHz      ; CLOCK_50                 ;      ;
+; 287.85 MHz ; 287.85 MHz      ; tick_5000:tick|CLK_OUT   ;      ;
 +------------+-----------------+--------------------------+------+
 This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -3.416 ; -157.230      ;
-; CLOCK_50                            ; -2.323 ; -41.799       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.568 ; -1.568        ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; spi2dac:dac|clk_1MHz     ; -4.070 ; -66.448       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -3.578 ; -55.099       ;
+; CLOCK_50                 ; -3.387 ; -140.679      ;
+; tick_5000:tick|CLK_OUT   ; -2.474 ; -23.507       ;
++--------------------------+--------+---------------+
 
 
-+-------------------------------------------------------------+
-; Slow 1100mV 0C Model Hold Summary                           ;
-+-------------------------------------+-------+---------------+
-; Clock                               ; Slack ; End Point TNS ;
-+-------------------------------------+-------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; 0.193 ; 0.000         ;
-; CLOCK_50                            ; 0.405 ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.501 ; 0.000         ;
-+-------------------------------------+-------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary                 ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -3.236 ; -51.012       ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.165  ; 0.000         ;
+; spi2dac:dac|clk_1MHz     ; 0.746  ; 0.000         ;
+; tick_5000:tick|CLK_OUT   ; 1.041  ; 0.000         ;
++--------------------------+--------+---------------+
 
 
 -----------------------------------------
@@ -235,15 +245,16 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.689 ; -16.816       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -38.286       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.412  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary  ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -108.567      ;
+; spi2adc:SPI_ADC|clk_1MHz ; -0.394 ; -18.781       ;
+; spi2dac:dac|clk_1MHz     ; -0.394 ; -11.064       ;
+; tick_5000:tick|CLK_OUT   ; -0.394 ; -5.180        ;
++--------------------------+--------+---------------+
 
 
 ----------------------------------------------
@@ -252,26 +263,28 @@ No paths to report.
 No synchronizer chains to report.
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -1.794 ; -79.872       ;
-; CLOCK_50                            ; -0.918 ; -13.912       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.572 ; -0.572        ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary               ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.728 ; -72.515       ;
+; spi2dac:dac|clk_1MHz     ; -1.849 ; -29.471       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -1.613 ; -27.548       ;
+; tick_5000:tick|CLK_OUT   ; -1.235 ; -10.973       ;
++--------------------------+--------+---------------+
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Hold Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -0.020 ; -0.037        ;
-; CLOCK_50                            ; 0.185  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.202  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -1.759 ; -28.407       ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.139  ; 0.000         ;
+; tick_5000:tick|CLK_OUT   ; 0.252  ; 0.000         ;
+; spi2dac:dac|clk_1MHz     ; 0.381  ; 0.000         ;
++--------------------------+--------+---------------+
 
 
 ------------------------------------------
@@ -286,15 +299,16 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.740 ; -12.957       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.012 ; -0.190        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.478  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -100.071      ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.056  ; 0.000         ;
+; spi2dac:dac|clk_1MHz     ; 0.094  ; 0.000         ;
+; tick_5000:tick|CLK_OUT   ; 0.109  ; 0.000         ;
++--------------------------+--------+---------------+
 
 
 -----------------------------------------------
@@ -303,26 +317,28 @@ No paths to report.
 No synchronizer chains to report.
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -1.581 ; -69.264       ;
-; CLOCK_50                            ; -0.868 ; -11.639       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.462 ; -0.462        ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.252 ; -58.896       ;
+; spi2dac:dac|clk_1MHz     ; -1.809 ; -28.153       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -1.551 ; -24.730       ;
+; tick_5000:tick|CLK_OUT   ; -1.105 ; -9.791        ;
++--------------------------+--------+---------------+
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Hold Summary                            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; tick_50000:TICK0|CLK_OUT            ; -0.021 ; -0.052        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.122  ; 0.000         ;
-; CLOCK_50                            ; 0.177  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary                 ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -1.741 ; -28.450       ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.139  ; 0.000         ;
+; tick_5000:tick|CLK_OUT   ; 0.222  ; 0.000         ;
+; spi2dac:dac|clk_1MHz     ; 0.353  ; 0.000         ;
++--------------------------+--------+---------------+
 
 
 -----------------------------------------
@@ -337,15 +353,16 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.789 ; -15.486       ;
-; tick_50000:TICK0|CLK_OUT            ; 0.024  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.468  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary  ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -106.958      ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.085  ; 0.000         ;
+; spi2dac:dac|clk_1MHz     ; 0.107  ; 0.000         ;
+; tick_5000:tick|CLK_OUT   ; 0.130  ; 0.000         ;
++--------------------------+--------+---------------+
 
 
 ----------------------------------------------
@@ -354,20 +371,22 @@ No paths to report.
 No synchronizer chains to report.
 
 
-+-----------------------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                                                 ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Clock                                ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Worst-case Slack                     ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.789              ;
-;  CLOCK_50                            ; -2.323   ; 0.177  ; N/A      ; N/A     ; -0.789              ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.122  ; N/A      ; N/A     ; 0.412               ;
-;  tick_50000:TICK0|CLK_OUT            ; -3.462   ; -0.021 ; N/A      ; N/A     ; -0.394              ;
-; Design-wide TNS                      ; -203.863 ; -0.052 ; 0.0      ; 0.0     ; -56.894             ;
-;  CLOCK_50                            ; -41.799  ; 0.000  ; N/A      ; N/A     ; -18.132             ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.675   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
-;  tick_50000:TICK0|CLK_OUT            ; -161.413 ; -0.052 ; N/A      ; N/A     ; -38.762             ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
++-------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                       ;
++---------------------------+----------+---------+----------+---------+---------------------+
+; Clock                     ; Setup    ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
++---------------------------+----------+---------+----------+---------+---------------------+
+; Worst-case Slack          ; -4.070   ; -3.236  ; N/A      ; N/A     ; -2.174              ;
+;  CLOCK_50                 ; -3.552   ; -3.236  ; N/A      ; N/A     ; -2.174              ;
+;  spi2adc:SPI_ADC|clk_1MHz ; -3.578   ; 0.136   ; N/A      ; N/A     ; -0.394              ;
+;  spi2dac:dac|clk_1MHz     ; -4.070   ; 0.353   ; N/A      ; N/A     ; -0.394              ;
+;  tick_5000:tick|CLK_OUT   ; -2.474   ; 0.222   ; N/A      ; N/A     ; -0.394              ;
+; Design-wide TNS           ; -291.388 ; -51.012 ; 0.0      ; 0.0     ; -148.005            ;
+;  CLOCK_50                 ; -146.301 ; -51.012 ; N/A      ; N/A     ; -111.881            ;
+;  spi2adc:SPI_ADC|clk_1MHz ; -56.704  ; 0.000   ; N/A      ; N/A     ; -19.666             ;
+;  spi2dac:dac|clk_1MHz     ; -66.448  ; 0.000   ; N/A      ; N/A     ; -11.148             ;
+;  tick_5000:tick|CLK_OUT   ; -23.507  ; 0.000   ; N/A      ; N/A     ; -5.310              ;
++---------------------------+----------+---------+----------+---------+---------------------+
 
 
 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -375,6 +394,14 @@ No synchronizer chains to report.
 +---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
 ; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
 +---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 ; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 ; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 ; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
@@ -410,23 +437,6 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 +---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
 
 
@@ -435,11 +445,8 @@ No synchronizer chains to report.
 +----------+--------------+-----------------+-----------------+
 ; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
 +----------+--------------+-----------------+-----------------+
-; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
 ; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ADC_SDO  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
 +----------+--------------+-----------------+-----------------+
 
 
@@ -448,6 +455,14 @@ No synchronizer chains to report.
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 ; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
 ; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
 ; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
 ; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
@@ -483,23 +498,6 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 
 
@@ -508,6 +506,14 @@ No synchronizer chains to report.
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 ; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
@@ -543,23 +549,6 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 
 
@@ -568,6 +557,14 @@ No synchronizer chains to report.
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 ; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
@@ -603,23 +600,6 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 
 
@@ -628,6 +608,14 @@ No synchronizer chains to report.
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 ; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
 ; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
@@ -663,49 +651,44 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------+
-; Setup Transfers                                                                                                       ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
++-------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                 ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; From Clock               ; To Clock                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; CLOCK_50                 ; CLOCK_50                 ; 615      ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 5        ; 1        ; 0        ; 0        ;
+; spi2dac:dac|clk_1MHz     ; CLOCK_50                 ; 16       ; 1        ; 0        ; 0        ;
+; tick_5000:tick|CLK_OUT   ; CLOCK_50                 ; 25       ; 15       ; 0        ; 0        ;
+; CLOCK_50                 ; spi2adc:SPI_ADC|clk_1MHz ; 3        ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; 58       ; 10       ; 24       ; 11       ;
+; CLOCK_50                 ; spi2dac:dac|clk_1MHz     ; 25       ; 0        ; 0        ; 0        ;
+; spi2dac:dac|clk_1MHz     ; spi2dac:dac|clk_1MHz     ; 113      ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; tick_5000:tick|CLK_OUT   ; 55       ; 0        ; 0        ; 0        ;
+; tick_5000:tick|CLK_OUT   ; tick_5000:tick|CLK_OUT   ; 55       ; 0        ; 0        ; 0        ;
++--------------------------+--------------------------+----------+----------+----------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
 
 
-+-----------------------------------------------------------------------------------------------------------------------+
-; Hold Transfers                                                                                                        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 416      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 43       ; 25       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 1042     ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
++-------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                  ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; From Clock               ; To Clock                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; CLOCK_50                 ; CLOCK_50                 ; 615      ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 5        ; 1        ; 0        ; 0        ;
+; spi2dac:dac|clk_1MHz     ; CLOCK_50                 ; 16       ; 1        ; 0        ; 0        ;
+; tick_5000:tick|CLK_OUT   ; CLOCK_50                 ; 25       ; 15       ; 0        ; 0        ;
+; CLOCK_50                 ; spi2adc:SPI_ADC|clk_1MHz ; 3        ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; 58       ; 10       ; 24       ; 11       ;
+; CLOCK_50                 ; spi2dac:dac|clk_1MHz     ; 25       ; 0        ; 0        ; 0        ;
+; spi2dac:dac|clk_1MHz     ; spi2dac:dac|clk_1MHz     ; 113      ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; tick_5000:tick|CLK_OUT   ; 55       ; 0        ; 0        ; 0        ;
+; tick_5000:tick|CLK_OUT   ; tick_5000:tick|CLK_OUT   ; 55       ; 0        ; 0        ; 0        ;
++--------------------------+--------------------------+----------+----------+----------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
 
 
@@ -728,22 +711,23 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +---------------------------------+-------+------+
 ; Illegal Clocks                  ; 0     ; 0    ;
 ; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 2     ; 2    ;
-; Unconstrained Input Port Paths  ; 20    ; 20   ;
-; Unconstrained Output Ports      ; 45    ; 45   ;
-; Unconstrained Output Port Paths ; 500   ; 500  ;
+; Unconstrained Input Ports       ; 1     ; 1    ;
+; Unconstrained Input Port Paths  ; 1     ; 1    ;
+; Unconstrained Output Ports      ; 42    ; 42   ;
+; Unconstrained Output Port Paths ; 362   ; 362  ;
 +---------------------------------+-------+------+
 
 
-+------------------------------------------------------------------------------------------------+
-; Clock Status Summary                                                                           ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; Target                              ; Clock                               ; Type ; Status      ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;
-+-------------------------------------+-------------------------------------+------+-------------+
++--------------------------------------------------------------------------+
+; Clock Status Summary                                                     ;
++--------------------------+--------------------------+------+-------------+
+; Target                   ; Clock                    ; Type ; Status      ;
++--------------------------+--------------------------+------+-------------+
+; CLOCK_50                 ; CLOCK_50                 ; Base ; Constrained ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; Base ; Constrained ;
+; spi2dac:dac|clk_1MHz     ; spi2dac:dac|clk_1MHz     ; Base ; Constrained ;
+; tick_5000:tick|CLK_OUT   ; tick_5000:tick|CLK_OUT   ; Base ; Constrained ;
++--------------------------+--------------------------+------+-------------+
 
 
 +---------------------------------------------------------------------------------------------------+
@@ -751,8 +735,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +------------+--------------------------------------------------------------------------------------+
 ; Input Port ; Comment                                                                              ;
 +------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +------------+--------------------------------------------------------------------------------------+
 
 
@@ -761,6 +744,13 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +-------------+---------------------------------------------------------------------------------------+
 ; Output Port ; Comment                                                                               ;
 +-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -790,22 +780,12 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +-------------+---------------------------------------------------------------------------------------+
 
 
@@ -814,8 +794,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +------------+--------------------------------------------------------------------------------------+
 ; Input Port ; Comment                                                                              ;
 +------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +------------+--------------------------------------------------------------------------------------+
 
 
@@ -824,6 +803,13 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +-------------+---------------------------------------------------------------------------------------+
 ; Output Port ; Comment                                                                               ;
 +-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -853,22 +839,12 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +-------------+---------------------------------------------------------------------------------------+
 
 
@@ -878,128 +854,141 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime TimeQuest Timing Analyzer
     Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Fri Nov 25 12:11:09 2016
-Info: Command: quartus_sta ex9 -c ex9
+    Info: Processing started: Fri Dec 02 18:32:26 2016
+Info: Command: quartus_sta ex10 -c ex10
 Info: qsta_default_script.tcl version: #1
+Critical Warning (136021): Ignored assignment IO_STANDARD which contains an invalid node name "LEDR[3]#============================================================"
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
 Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
 Info (332105): Deriving Clocks
-    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
+    Info (332105): create_clock -period 1.000 -name spi2adc:SPI_ADC|clk_1MHz spi2adc:SPI_ADC|clk_1MHz
     Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
-    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
+    Info (332105): create_clock -period 1.000 -name tick_5000:tick|CLK_OUT tick_5000:tick|CLK_OUT
+    Info (332105): create_clock -period 1.000 -name spi2dac:dac|clk_1MHz spi2dac:dac|clk_1MHz
 Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
 Info: Analyzing Slow 1100mV 85C Model
 Critical Warning (332148): Timing requirements not met
     Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.462
+Info (332146): Worst-case setup slack is -3.923
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -3.462            -161.413 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -2.047             -40.775 CLOCK_50 
-    Info (332119):    -1.675              -1.675 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is 0.179
+    Info (332119):    -3.923             -65.134 spi2dac:dac|clk_1MHz 
+    Info (332119):    -3.552            -146.301 CLOCK_50 
+    Info (332119):    -3.471             -56.704 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -2.452             -23.249 tick_5000:tick|CLK_OUT 
+Info (332146): Worst-case hold slack is -3.138
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):     0.179               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.385               0.000 CLOCK_50 
-    Info (332119):     0.629               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -3.138             -49.029 CLOCK_50 
+    Info (332119):     0.136               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.788               0.000 spi2dac:dac|clk_1MHz 
+    Info (332119):     1.040               0.000 tick_5000:tick|CLK_OUT 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.637
+Info (332146): Worst-case minimum pulse width slack is -2.174
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.637             -18.132 CLOCK_50 
-    Info (332119):    -0.394             -38.762 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.459               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -2.174            -111.881 CLOCK_50 
+    Info (332119):    -0.394             -19.666 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.394             -11.148 spi2dac:dac|clk_1MHz 
+    Info (332119):    -0.394              -5.310 tick_5000:tick|CLK_OUT 
 Info: Analyzing Slow 1100mV 0C Model
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
 Critical Warning (332148): Timing requirements not met
     Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.416
+Info (332146): Worst-case setup slack is -4.070
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -3.416            -157.230 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -2.323             -41.799 CLOCK_50 
-    Info (332119):    -1.568              -1.568 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is 0.193
+    Info (332119):    -4.070             -66.448 spi2dac:dac|clk_1MHz 
+    Info (332119):    -3.578             -55.099 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -3.387            -140.679 CLOCK_50 
+    Info (332119):    -2.474             -23.507 tick_5000:tick|CLK_OUT 
+Info (332146): Worst-case hold slack is -3.236
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):     0.193               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.405               0.000 CLOCK_50 
-    Info (332119):     0.501               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -3.236             -51.012 CLOCK_50 
+    Info (332119):     0.165               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.746               0.000 spi2dac:dac|clk_1MHz 
+    Info (332119):     1.041               0.000 tick_5000:tick|CLK_OUT 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.689
+Info (332146): Worst-case minimum pulse width slack is -2.174
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.689             -16.816 CLOCK_50 
-    Info (332119):    -0.394             -38.286 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.412               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -2.174            -108.567 CLOCK_50 
+    Info (332119):    -0.394             -18.781 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.394             -11.064 spi2dac:dac|clk_1MHz 
+    Info (332119):    -0.394              -5.180 tick_5000:tick|CLK_OUT 
 Info: Analyzing Fast 1100mV 85C Model
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
 Critical Warning (332148): Timing requirements not met
     Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.794
+Info (332146): Worst-case setup slack is -2.728
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -1.794             -79.872 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.918             -13.912 CLOCK_50 
-    Info (332119):    -0.572              -0.572 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -0.020
+    Info (332119):    -2.728             -72.515 CLOCK_50 
+    Info (332119):    -1.849             -29.471 spi2dac:dac|clk_1MHz 
+    Info (332119):    -1.613             -27.548 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -1.235             -10.973 tick_5000:tick|CLK_OUT 
+Info (332146): Worst-case hold slack is -1.759
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.020              -0.037 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.185               0.000 CLOCK_50 
-    Info (332119):     0.202               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -1.759             -28.407 CLOCK_50 
+    Info (332119):     0.139               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.252               0.000 tick_5000:tick|CLK_OUT 
+    Info (332119):     0.381               0.000 spi2dac:dac|clk_1MHz 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.740
+Info (332146): Worst-case minimum pulse width slack is -2.174
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.740             -12.957 CLOCK_50 
-    Info (332119):    -0.012              -0.190 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.478               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -2.174            -100.071 CLOCK_50 
+    Info (332119):     0.056               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.094               0.000 spi2dac:dac|clk_1MHz 
+    Info (332119):     0.109               0.000 tick_5000:tick|CLK_OUT 
 Info: Analyzing Fast 1100mV 0C Model
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
 Critical Warning (332148): Timing requirements not met
     Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.581
+Info (332146): Worst-case setup slack is -2.252
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -1.581             -69.264 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.868             -11.639 CLOCK_50 
-    Info (332119):    -0.462              -0.462 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -0.021
+    Info (332119):    -2.252             -58.896 CLOCK_50 
+    Info (332119):    -1.809             -28.153 spi2dac:dac|clk_1MHz 
+    Info (332119):    -1.551             -24.730 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -1.105              -9.791 tick_5000:tick|CLK_OUT 
+Info (332146): Worst-case hold slack is -1.741
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.021              -0.052 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.122               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-    Info (332119):     0.177               0.000 CLOCK_50 
+    Info (332119):    -1.741             -28.450 CLOCK_50 
+    Info (332119):     0.139               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.222               0.000 tick_5000:tick|CLK_OUT 
+    Info (332119):     0.353               0.000 spi2dac:dac|clk_1MHz 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.789
+Info (332146): Worst-case minimum pulse width slack is -2.174
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.789             -15.486 CLOCK_50 
-    Info (332119):     0.024               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.468               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -2.174            -106.958 CLOCK_50 
+    Info (332119):     0.085               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.107               0.000 spi2dac:dac|clk_1MHz 
+    Info (332119):     0.130               0.000 tick_5000:tick|CLK_OUT 
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
-    Info: Peak virtual memory: 1213 megabytes
-    Info: Processing ended: Fri Nov 25 12:11:15 2016
-    Info: Elapsed time: 00:00:06
-    Info: Total CPU time (on all processors): 00:00:06
+    Info: Peak virtual memory: 1247 megabytes
+    Info: Processing ended: Fri Dec 02 18:32:36 2016
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:07
 
 
diff --git a/part_3/ex15/output_files/ex10.sta.summary b/part_3/ex15/output_files/ex10.sta.summary
new file mode 100755
index 0000000..350a683
--- /dev/null
+++ b/part_3/ex15/output_files/ex10.sta.summary
@@ -0,0 +1,197 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'spi2dac:dac|clk_1MHz'
+Slack : -3.923
+TNS   : -65.134
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -3.552
+TNS   : -146.301
+
+Type  : Slow 1100mV 85C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -3.471
+TNS   : -56.704
+
+Type  : Slow 1100mV 85C Model Setup 'tick_5000:tick|CLK_OUT'
+Slack : -2.452
+TNS   : -23.249
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : -3.138
+TNS   : -49.029
+
+Type  : Slow 1100mV 85C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.136
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'spi2dac:dac|clk_1MHz'
+Slack : 0.788
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'tick_5000:tick|CLK_OUT'
+Slack : 1.040
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -111.881
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -0.394
+TNS   : -19.666
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2dac:dac|clk_1MHz'
+Slack : -0.394
+TNS   : -11.148
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'tick_5000:tick|CLK_OUT'
+Slack : -0.394
+TNS   : -5.310
+
+Type  : Slow 1100mV 0C Model Setup 'spi2dac:dac|clk_1MHz'
+Slack : -4.070
+TNS   : -66.448
+
+Type  : Slow 1100mV 0C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -3.578
+TNS   : -55.099
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -3.387
+TNS   : -140.679
+
+Type  : Slow 1100mV 0C Model Setup 'tick_5000:tick|CLK_OUT'
+Slack : -2.474
+TNS   : -23.507
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : -3.236
+TNS   : -51.012
+
+Type  : Slow 1100mV 0C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.165
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'spi2dac:dac|clk_1MHz'
+Slack : 0.746
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'tick_5000:tick|CLK_OUT'
+Slack : 1.041
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -108.567
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -0.394
+TNS   : -18.781
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2dac:dac|clk_1MHz'
+Slack : -0.394
+TNS   : -11.064
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'tick_5000:tick|CLK_OUT'
+Slack : -0.394
+TNS   : -5.180
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -2.728
+TNS   : -72.515
+
+Type  : Fast 1100mV 85C Model Setup 'spi2dac:dac|clk_1MHz'
+Slack : -1.849
+TNS   : -29.471
+
+Type  : Fast 1100mV 85C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -1.613
+TNS   : -27.548
+
+Type  : Fast 1100mV 85C Model Setup 'tick_5000:tick|CLK_OUT'
+Slack : -1.235
+TNS   : -10.973
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : -1.759
+TNS   : -28.407
+
+Type  : Fast 1100mV 85C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.139
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'tick_5000:tick|CLK_OUT'
+Slack : 0.252
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'spi2dac:dac|clk_1MHz'
+Slack : 0.381
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -100.071
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.056
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2dac:dac|clk_1MHz'
+Slack : 0.094
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'tick_5000:tick|CLK_OUT'
+Slack : 0.109
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.252
+TNS   : -58.896
+
+Type  : Fast 1100mV 0C Model Setup 'spi2dac:dac|clk_1MHz'
+Slack : -1.809
+TNS   : -28.153
+
+Type  : Fast 1100mV 0C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -1.551
+TNS   : -24.730
+
+Type  : Fast 1100mV 0C Model Setup 'tick_5000:tick|CLK_OUT'
+Slack : -1.105
+TNS   : -9.791
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : -1.741
+TNS   : -28.450
+
+Type  : Fast 1100mV 0C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.139
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'tick_5000:tick|CLK_OUT'
+Slack : 0.222
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'spi2dac:dac|clk_1MHz'
+Slack : 0.353
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -106.958
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.085
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2dac:dac|clk_1MHz'
+Slack : 0.107
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'tick_5000:tick|CLK_OUT'
+Slack : 0.130
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_3/ex15/rom_data/rom_data.mif b/part_3/ex15/rom_data/rom_data.mif
new file mode 100755
index 0000000..a688b6f
--- /dev/null
+++ b/part_3/ex15/rom_data/rom_data.mif
@@ -0,0 +1,1032 @@
+-- ROM Initialization file
+WIDTH = 10;
+DEPTH = 1024;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT
+BEGIN
+   0 :  200;
+   1 :  203;
+   2 :  206;
+   3 :  209;
+   4 :  20C;
+   5 :  20F;
+   6 :  212;
+   7 :  215;
+   8 :  219;
+   9 :  21C;
+   A :  21F;
+   B :  222;
+   C :  225;
+   D :  228;
+   E :  22B;
+   F :  22F;
+  10 :  232;
+  11 :  235;
+  12 :  238;
+  13 :  23B;
+  14 :  23E;
+  15 :  241;
+  16 :  244;
+  17 :  247;
+  18 :  24B;
+  19 :  24E;
+  1A :  251;
+  1B :  254;
+  1C :  257;
+  1D :  25A;
+  1E :  25D;
+  1F :  260;
+  20 :  263;
+  21 :  266;
+  22 :  269;
+  23 :  26D;
+  24 :  270;
+  25 :  273;
+  26 :  276;
+  27 :  279;
+  28 :  27C;
+  29 :  27F;
+  2A :  282;
+  2B :  285;
+  2C :  288;
+  2D :  28B;
+  2E :  28E;
+  2F :  291;
+  30 :  294;
+  31 :  297;
+  32 :  29A;
+  33 :  29D;
+  34 :  2A0;
+  35 :  2A3;
+  36 :  2A6;
+  37 :  2A9;
+  38 :  2AC;
+  39 :  2AF;
+  3A :  2B2;
+  3B :  2B5;
+  3C :  2B8;
+  3D :  2BB;
+  3E :  2BD;
+  3F :  2C0;
+  40 :  2C3;
+  41 :  2C6;
+  42 :  2C9;
+  43 :  2CC;
+  44 :  2CF;
+  45 :  2D2;
+  46 :  2D5;
+  47 :  2D7;
+  48 :  2DA;
+  49 :  2DD;
+  4A :  2E0;
+  4B :  2E3;
+  4C :  2E5;
+  4D :  2E8;
+  4E :  2EB;
+  4F :  2EE;
+  50 :  2F1;
+  51 :  2F3;
+  52 :  2F6;
+  53 :  2F9;
+  54 :  2FC;
+  55 :  2FE;
+  56 :  301;
+  57 :  304;
+  58 :  306;
+  59 :  309;
+  5A :  30C;
+  5B :  30E;
+  5C :  311;
+  5D :  314;
+  5E :  316;
+  5F :  319;
+  60 :  31C;
+  61 :  31E;
+  62 :  321;
+  63 :  323;
+  64 :  326;
+  65 :  329;
+  66 :  32B;
+  67 :  32E;
+  68 :  330;
+  69 :  333;
+  6A :  335;
+  6B :  338;
+  6C :  33A;
+  6D :  33D;
+  6E :  33F;
+  6F :  342;
+  70 :  344;
+  71 :  346;
+  72 :  349;
+  73 :  34B;
+  74 :  34E;
+  75 :  350;
+  76 :  352;
+  77 :  355;
+  78 :  357;
+  79 :  359;
+  7A :  35C;
+  7B :  35E;
+  7C :  360;
+  7D :  362;
+  7E :  365;
+  7F :  367;
+  80 :  369;
+  81 :  36B;
+  82 :  36E;
+  83 :  370;
+  84 :  372;
+  85 :  374;
+  86 :  376;
+  87 :  378;
+  88 :  37A;
+  89 :  37D;
+  8A :  37F;
+  8B :  381;
+  8C :  383;
+  8D :  385;
+  8E :  387;
+  8F :  389;
+  90 :  38B;
+  91 :  38D;
+  92 :  38F;
+  93 :  391;
+  94 :  393;
+  95 :  395;
+  96 :  397;
+  97 :  398;
+  98 :  39A;
+  99 :  39C;
+  9A :  39E;
+  9B :  3A0;
+  9C :  3A2;
+  9D :  3A3;
+  9E :  3A5;
+  9F :  3A7;
+  A0 :  3A9;
+  A1 :  3AB;
+  A2 :  3AC;
+  A3 :  3AE;
+  A4 :  3B0;
+  A5 :  3B1;
+  A6 :  3B3;
+  A7 :  3B5;
+  A8 :  3B6;
+  A9 :  3B8;
+  AA :  3B9;
+  AB :  3BB;
+  AC :  3BD;
+  AD :  3BE;
+  AE :  3C0;
+  AF :  3C1;
+  B0 :  3C3;
+  B1 :  3C4;
+  B2 :  3C6;
+  B3 :  3C7;
+  B4 :  3C8;
+  B5 :  3CA;
+  B6 :  3CB;
+  B7 :  3CD;
+  B8 :  3CE;
+  B9 :  3CF;
+  BA :  3D1;
+  BB :  3D2;
+  BC :  3D3;
+  BD :  3D4;
+  BE :  3D6;
+  BF :  3D7;
+  C0 :  3D8;
+  C1 :  3D9;
+  C2 :  3DA;
+  C3 :  3DC;
+  C4 :  3DD;
+  C5 :  3DE;
+  C6 :  3DF;
+  C7 :  3E0;
+  C8 :  3E1;
+  C9 :  3E2;
+  CA :  3E3;
+  CB :  3E4;
+  CC :  3E5;
+  CD :  3E6;
+  CE :  3E7;
+  CF :  3E8;
+  D0 :  3E9;
+  D1 :  3EA;
+  D2 :  3EB;
+  D3 :  3EC;
+  D4 :  3EC;
+  D5 :  3ED;
+  D6 :  3EE;
+  D7 :  3EF;
+  D8 :  3F0;
+  D9 :  3F0;
+  DA :  3F1;
+  DB :  3F2;
+  DC :  3F3;
+  DD :  3F3;
+  DE :  3F4;
+  DF :  3F5;
+  E0 :  3F5;
+  E1 :  3F6;
+  E2 :  3F6;
+  E3 :  3F7;
+  E4 :  3F7;
+  E5 :  3F8;
+  E6 :  3F9;
+  E7 :  3F9;
+  E8 :  3F9;
+  E9 :  3FA;
+  EA :  3FA;
+  EB :  3FB;
+  EC :  3FB;
+  ED :  3FC;
+  EE :  3FC;
+  EF :  3FC;
+  F0 :  3FD;
+  F1 :  3FD;
+  F2 :  3FD;
+  F3 :  3FD;
+  F4 :  3FE;
+  F5 :  3FE;
+  F6 :  3FE;
+  F7 :  3FE;
+  F8 :  3FE;
+  F9 :  3FF;
+  FA :  3FF;
+  FB :  3FF;
+  FC :  3FF;
+  FD :  3FF;
+  FE :  3FF;
+  FF :  3FF;
+ 100 :  3FF;
+ 101 :  3FF;
+ 102 :  3FF;
+ 103 :  3FF;
+ 104 :  3FF;
+ 105 :  3FF;
+ 106 :  3FF;
+ 107 :  3FF;
+ 108 :  3FE;
+ 109 :  3FE;
+ 10A :  3FE;
+ 10B :  3FE;
+ 10C :  3FE;
+ 10D :  3FD;
+ 10E :  3FD;
+ 10F :  3FD;
+ 110 :  3FD;
+ 111 :  3FC;
+ 112 :  3FC;
+ 113 :  3FC;
+ 114 :  3FB;
+ 115 :  3FB;
+ 116 :  3FA;
+ 117 :  3FA;
+ 118 :  3F9;
+ 119 :  3F9;
+ 11A :  3F9;
+ 11B :  3F8;
+ 11C :  3F7;
+ 11D :  3F7;
+ 11E :  3F6;
+ 11F :  3F6;
+ 120 :  3F5;
+ 121 :  3F5;
+ 122 :  3F4;
+ 123 :  3F3;
+ 124 :  3F3;
+ 125 :  3F2;
+ 126 :  3F1;
+ 127 :  3F0;
+ 128 :  3F0;
+ 129 :  3EF;
+ 12A :  3EE;
+ 12B :  3ED;
+ 12C :  3EC;
+ 12D :  3EC;
+ 12E :  3EB;
+ 12F :  3EA;
+ 130 :  3E9;
+ 131 :  3E8;
+ 132 :  3E7;
+ 133 :  3E6;
+ 134 :  3E5;
+ 135 :  3E4;
+ 136 :  3E3;
+ 137 :  3E2;
+ 138 :  3E1;
+ 139 :  3E0;
+ 13A :  3DF;
+ 13B :  3DE;
+ 13C :  3DD;
+ 13D :  3DC;
+ 13E :  3DA;
+ 13F :  3D9;
+ 140 :  3D8;
+ 141 :  3D7;
+ 142 :  3D6;
+ 143 :  3D4;
+ 144 :  3D3;
+ 145 :  3D2;
+ 146 :  3D1;
+ 147 :  3CF;
+ 148 :  3CE;
+ 149 :  3CD;
+ 14A :  3CB;
+ 14B :  3CA;
+ 14C :  3C8;
+ 14D :  3C7;
+ 14E :  3C6;
+ 14F :  3C4;
+ 150 :  3C3;
+ 151 :  3C1;
+ 152 :  3C0;
+ 153 :  3BE;
+ 154 :  3BD;
+ 155 :  3BB;
+ 156 :  3B9;
+ 157 :  3B8;
+ 158 :  3B6;
+ 159 :  3B5;
+ 15A :  3B3;
+ 15B :  3B1;
+ 15C :  3B0;
+ 15D :  3AE;
+ 15E :  3AC;
+ 15F :  3AB;
+ 160 :  3A9;
+ 161 :  3A7;
+ 162 :  3A5;
+ 163 :  3A3;
+ 164 :  3A2;
+ 165 :  3A0;
+ 166 :  39E;
+ 167 :  39C;
+ 168 :  39A;
+ 169 :  398;
+ 16A :  397;
+ 16B :  395;
+ 16C :  393;
+ 16D :  391;
+ 16E :  38F;
+ 16F :  38D;
+ 170 :  38B;
+ 171 :  389;
+ 172 :  387;
+ 173 :  385;
+ 174 :  383;
+ 175 :  381;
+ 176 :  37F;
+ 177 :  37D;
+ 178 :  37A;
+ 179 :  378;
+ 17A :  376;
+ 17B :  374;
+ 17C :  372;
+ 17D :  370;
+ 17E :  36E;
+ 17F :  36B;
+ 180 :  369;
+ 181 :  367;
+ 182 :  365;
+ 183 :  362;
+ 184 :  360;
+ 185 :  35E;
+ 186 :  35C;
+ 187 :  359;
+ 188 :  357;
+ 189 :  355;
+ 18A :  352;
+ 18B :  350;
+ 18C :  34E;
+ 18D :  34B;
+ 18E :  349;
+ 18F :  346;
+ 190 :  344;
+ 191 :  342;
+ 192 :  33F;
+ 193 :  33D;
+ 194 :  33A;
+ 195 :  338;
+ 196 :  335;
+ 197 :  333;
+ 198 :  330;
+ 199 :  32E;
+ 19A :  32B;
+ 19B :  329;
+ 19C :  326;
+ 19D :  323;
+ 19E :  321;
+ 19F :  31E;
+ 1A0 :  31C;
+ 1A1 :  319;
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+ 1AD :  2F9;
+ 1AE :  2F6;
+ 1AF :  2F3;
+ 1B0 :  2F1;
+ 1B1 :  2EE;
+ 1B2 :  2EB;
+ 1B3 :  2E8;
+ 1B4 :  2E5;
+ 1B5 :  2E3;
+ 1B6 :  2E0;
+ 1B7 :  2DD;
+ 1B8 :  2DA;
+ 1B9 :  2D7;
+ 1BA :  2D5;
+ 1BB :  2D2;
+ 1BC :  2CF;
+ 1BD :  2CC;
+ 1BE :  2C9;
+ 1BF :  2C6;
+ 1C0 :  2C3;
+ 1C1 :  2C0;
+ 1C2 :  2BD;
+ 1C3 :  2BB;
+ 1C4 :  2B8;
+ 1C5 :  2B5;
+ 1C6 :  2B2;
+ 1C7 :  2AF;
+ 1C8 :  2AC;
+ 1C9 :  2A9;
+ 1CA :  2A6;
+ 1CB :  2A3;
+ 1CC :  2A0;
+ 1CD :  29D;
+ 1CE :  29A;
+ 1CF :  297;
+ 1D0 :  294;
+ 1D1 :  291;
+ 1D2 :  28E;
+ 1D3 :  28B;
+ 1D4 :  288;
+ 1D5 :  285;
+ 1D6 :  282;
+ 1D7 :  27F;
+ 1D8 :  27C;
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+ 1DC :  270;
+ 1DD :  26D;
+ 1DE :  269;
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+ 1FA :  212;
+ 1FB :  20F;
+ 1FC :  20C;
+ 1FD :  209;
+ 1FE :  206;
+ 1FF :  203;
+ 200 :  200;
+ 201 :  1FC;
+ 202 :  1F9;
+ 203 :  1F6;
+ 204 :  1F3;
+ 205 :  1F0;
+ 206 :  1ED;
+ 207 :  1EA;
+ 208 :  1E6;
+ 209 :  1E3;
+ 20A :  1E0;
+ 20B :  1DD;
+ 20C :  1DA;
+ 20D :  1D7;
+ 20E :  1D4;
+ 20F :  1D0;
+ 210 :  1CD;
+ 211 :  1CA;
+ 212 :  1C7;
+ 213 :  1C4;
+ 214 :  1C1;
+ 215 :  1BE;
+ 216 :  1BB;
+ 217 :  1B8;
+ 218 :  1B4;
+ 219 :  1B1;
+ 21A :  1AE;
+ 21B :  1AB;
+ 21C :  1A8;
+ 21D :  1A5;
+ 21E :  1A2;
+ 21F :  19F;
+ 220 :  19C;
+ 221 :  199;
+ 222 :  196;
+ 223 :  192;
+ 224 :  18F;
+ 225 :  18C;
+ 226 :  189;
+ 227 :  186;
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+ 22A :  17D;
+ 22B :  17A;
+ 22C :  177;
+ 22D :  174;
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+ 231 :  168;
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+ 234 :  15F;
+ 235 :  15C;
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+ 237 :  156;
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+ 239 :  150;
+ 23A :  14D;
+ 23B :  14A;
+ 23C :  147;
+ 23D :  144;
+ 23E :  142;
+ 23F :  13F;
+ 240 :  13C;
+ 241 :  139;
+ 242 :  136;
+ 243 :  133;
+ 244 :  130;
+ 245 :  12D;
+ 246 :  12A;
+ 247 :  128;
+ 248 :  125;
+ 249 :  122;
+ 24A :  11F;
+ 24B :  11C;
+ 24C :  11A;
+ 24D :  117;
+ 24E :  114;
+ 24F :  111;
+ 250 :  10E;
+ 251 :  10C;
+ 252 :  109;
+ 253 :  106;
+ 254 :  103;
+ 255 :  101;
+ 256 :   FE;
+ 257 :   FB;
+ 258 :   F9;
+ 259 :   F6;
+ 25A :   F3;
+ 25B :   F1;
+ 25C :   EE;
+ 25D :   EB;
+ 25E :   E9;
+ 25F :   E6;
+ 260 :   E3;
+ 261 :   E1;
+ 262 :   DE;
+ 263 :   DC;
+ 264 :   D9;
+ 265 :   D6;
+ 266 :   D4;
+ 267 :   D1;
+ 268 :   CF;
+ 269 :   CC;
+ 26A :   CA;
+ 26B :   C7;
+ 26C :   C5;
+ 26D :   C2;
+ 26E :   C0;
+ 26F :   BD;
+ 270 :   BB;
+ 271 :   B9;
+ 272 :   B6;
+ 273 :   B4;
+ 274 :   B1;
+ 275 :   AF;
+ 276 :   AD;
+ 277 :   AA;
+ 278 :   A8;
+ 279 :   A6;
+ 27A :   A3;
+ 27B :   A1;
+ 27C :   9F;
+ 27D :   9D;
+ 27E :   9A;
+ 27F :   98;
+ 280 :   96;
+ 281 :   94;
+ 282 :   91;
+ 283 :   8F;
+ 284 :   8D;
+ 285 :   8B;
+ 286 :   89;
+ 287 :   87;
+ 288 :   85;
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+ 28A :   80;
+ 28B :   7E;
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+ 2AA :   46;
+ 2AB :   44;
+ 2AC :   42;
+ 2AD :   41;
+ 2AE :   3F;
+ 2AF :   3E;
+ 2B0 :   3C;
+ 2B1 :   3B;
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+ 2B3 :   38;
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+ 2B5 :   35;
+ 2B6 :   34;
+ 2B7 :   32;
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+ 2BB :   2D;
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+ 2BF :   28;
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+ 2C1 :   26;
+ 2C2 :   25;
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+ 2C7 :   1F;
+ 2C8 :   1E;
+ 2C9 :   1D;
+ 2CA :   1C;
+ 2CB :   1B;
+ 2CC :   1A;
+ 2CD :   19;
+ 2CE :   18;
+ 2CF :   17;
+ 2D0 :   16;
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+ 2D2 :   14;
+ 2D3 :   13;
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+ 2D8 :    F;
+ 2D9 :    F;
+ 2DA :    E;
+ 2DB :    D;
+ 2DC :    C;
+ 2DD :    C;
+ 2DE :    B;
+ 2DF :    A;
+ 2E0 :    A;
+ 2E1 :    9;
+ 2E2 :    9;
+ 2E3 :    8;
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+ 2F6 :    1;
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+ 2F8 :    1;
+ 2F9 :    0;
+ 2FA :    0;
+ 2FB :    0;
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+ 2FD :    0;
+ 2FE :    0;
+ 2FF :    0;
+ 300 :    0;
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+ 38B :   AF;
+ 38C :   B1;
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+ 399 :   D1;
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+ 39F :   E1;
+ 3A0 :   E3;
+ 3A1 :   E6;
+ 3A2 :   E9;
+ 3A3 :   EB;
+ 3A4 :   EE;
+ 3A5 :   F1;
+ 3A6 :   F3;
+ 3A7 :   F6;
+ 3A8 :   F9;
+ 3A9 :   FB;
+ 3AA :   FE;
+ 3AB :  101;
+ 3AC :  103;
+ 3AD :  106;
+ 3AE :  109;
+ 3AF :  10C;
+ 3B0 :  10E;
+ 3B1 :  111;
+ 3B2 :  114;
+ 3B3 :  117;
+ 3B4 :  11A;
+ 3B5 :  11C;
+ 3B6 :  11F;
+ 3B7 :  122;
+ 3B8 :  125;
+ 3B9 :  128;
+ 3BA :  12A;
+ 3BB :  12D;
+ 3BC :  130;
+ 3BD :  133;
+ 3BE :  136;
+ 3BF :  139;
+ 3C0 :  13C;
+ 3C1 :  13F;
+ 3C2 :  142;
+ 3C3 :  144;
+ 3C4 :  147;
+ 3C5 :  14A;
+ 3C6 :  14D;
+ 3C7 :  150;
+ 3C8 :  153;
+ 3C9 :  156;
+ 3CA :  159;
+ 3CB :  15C;
+ 3CC :  15F;
+ 3CD :  162;
+ 3CE :  165;
+ 3CF :  168;
+ 3D0 :  16B;
+ 3D1 :  16E;
+ 3D2 :  171;
+ 3D3 :  174;
+ 3D4 :  177;
+ 3D5 :  17A;
+ 3D6 :  17D;
+ 3D7 :  180;
+ 3D8 :  183;
+ 3D9 :  186;
+ 3DA :  189;
+ 3DB :  18C;
+ 3DC :  18F;
+ 3DD :  192;
+ 3DE :  196;
+ 3DF :  199;
+ 3E0 :  19C;
+ 3E1 :  19F;
+ 3E2 :  1A2;
+ 3E3 :  1A5;
+ 3E4 :  1A8;
+ 3E5 :  1AB;
+ 3E6 :  1AE;
+ 3E7 :  1B1;
+ 3E8 :  1B4;
+ 3E9 :  1B8;
+ 3EA :  1BB;
+ 3EB :  1BE;
+ 3EC :  1C1;
+ 3ED :  1C4;
+ 3EE :  1C7;
+ 3EF :  1CA;
+ 3F0 :  1CD;
+ 3F1 :  1D0;
+ 3F2 :  1D4;
+ 3F3 :  1D7;
+ 3F4 :  1DA;
+ 3F5 :  1DD;
+ 3F6 :  1E0;
+ 3F7 :  1E3;
+ 3F8 :  1E6;
+ 3F9 :  1EA;
+ 3FA :  1ED;
+ 3FB :  1F0;
+ 3FC :  1F3;
+ 3FD :  1F6;
+ 3FE :  1F9;
+ 3FF :  1FC;
+END
diff --git a/part_3/ex15/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex15/simulation/modelsim/do_files/tb_spi2dac.do
new file mode 100755
index 0000000..b12a7d7
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/do_files/tb_spi2dac.do
@@ -0,0 +1,17 @@
+add wave -position end  sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end  dac_sdi
+add wave -position end  dac_cs
+add wave -position end  dac_sck
+add wave -position end  dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex15/simulation/modelsim/ex10.sft b/part_3/ex15/simulation/modelsim/ex10.sft
new file mode 100755
index 0000000..f324fea
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/ex10.sft
@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (Verilog)"
diff --git a/part_3/ex15/simulation/modelsim/ex10.vo b/part_3/ex15/simulation/modelsim/ex10.vo
new file mode 100755
index 0000000..b032524
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/ex10.vo
@@ -0,0 +1,10972 @@
+// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, the Altera Quartus Prime License Agreement,
+// the Altera MegaCore Function License Agreement, or other 
+// applicable license agreement, including, without limitation, 
+// that your use is for the sole purpose of programming logic 
+// devices manufactured by Altera and sold by Altera or its 
+// authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition"
+
+// DATE "12/02/2016 18:32:40"
+
+// 
+// Device: Altera 5CSEMA5F31C6 Package FBGA896
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module ex15 (
+	CLOCK_50,
+	DAC_CS,
+	DAC_SDI,
+	DAC_LD,
+	DAC_SCK,
+	ADC_SDI,
+	ADC_SCK,
+	ADC_CS,
+	ADC_SDO,
+	PWM_OUT,
+	HEX0,
+	HEX1,
+	HEX2,
+	HEX3,
+	HEX4);
+input 	CLOCK_50;
+output 	DAC_CS;
+output 	DAC_SDI;
+output 	DAC_LD;
+output 	DAC_SCK;
+output 	ADC_SDI;
+output 	ADC_SCK;
+output 	ADC_CS;
+input 	ADC_SDO;
+output 	PWM_OUT;
+output 	[6:0] HEX0;
+output 	[6:0] HEX1;
+output 	[6:0] HEX2;
+output 	[6:0] HEX3;
+output 	[6:0] HEX4;
+
+// Design Ports Information
+// DAC_CS	=>  Location: PIN_AD20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_SDI	=>  Location: PIN_AG18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_LD	=>  Location: PIN_AK21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_SCK	=>  Location: PIN_AF20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_SDI	=>  Location: PIN_AG21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_SCK	=>  Location: PIN_AF21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_CS	=>  Location: PIN_AG20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// PWM_OUT	=>  Location: PIN_AJ20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[0]	=>  Location: PIN_AE26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[1]	=>  Location: PIN_AE27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[2]	=>  Location: PIN_AE28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[3]	=>  Location: PIN_AG27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[4]	=>  Location: PIN_AF28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[5]	=>  Location: PIN_AG28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[6]	=>  Location: PIN_AH28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[0]	=>  Location: PIN_AJ29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[1]	=>  Location: PIN_AH29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[2]	=>  Location: PIN_AH30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[3]	=>  Location: PIN_AG30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[4]	=>  Location: PIN_AF29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[5]	=>  Location: PIN_AF30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[6]	=>  Location: PIN_AD27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[0]	=>  Location: PIN_AB23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[1]	=>  Location: PIN_AE29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[2]	=>  Location: PIN_AD29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[3]	=>  Location: PIN_AC28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[4]	=>  Location: PIN_AD30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[5]	=>  Location: PIN_AC29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[6]	=>  Location: PIN_AC30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[0]	=>  Location: PIN_AD26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[1]	=>  Location: PIN_AC27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[2]	=>  Location: PIN_AD25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[3]	=>  Location: PIN_AC25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[4]	=>  Location: PIN_AB28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[5]	=>  Location: PIN_AB25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[6]	=>  Location: PIN_AB22,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[0]	=>  Location: PIN_AA24,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[1]	=>  Location: PIN_Y23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[2]	=>  Location: PIN_Y24,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[3]	=>  Location: PIN_W22,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[4]	=>  Location: PIN_W24,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[5]	=>  Location: PIN_V23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX4[6]	=>  Location: PIN_W25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// CLOCK_50	=>  Location: PIN_AF14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ADC_SDO	=>  Location: PIN_AJ21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \CLOCK_50~input_o ;
+wire \dac|clk_1MHz~0_combout ;
+wire \CLOCK_50~inputCLKENA0_outclk ;
+wire \SPI_ADC|ctr~1_combout ;
+wire \SPI_ADC|ctr[0]~DUPLICATE_q ;
+wire \SPI_ADC|ctr~2_combout ;
+wire \SPI_ADC|ctr[1]~DUPLICATE_q ;
+wire \SPI_ADC|ctr~0_combout ;
+wire \SPI_ADC|ctr[2]~DUPLICATE_q ;
+wire \SPI_ADC|Add0~1_combout ;
+wire \SPI_ADC|Add0~0_combout ;
+wire \dac|Equal0~0_combout ;
+wire \dac|clk_1MHz~q ;
+wire \dac|state~2_combout ;
+wire \dac|state~3_combout ;
+wire \dac|state~0_combout ;
+wire \dac|state[4]~feeder_combout ;
+wire \dac|state[4]~DUPLICATE_q ;
+wire \dac|state~1_combout ;
+wire \tick|Add0~9_sumout ;
+wire \tick|count[0]~1_combout ;
+wire \tick|Add0~10 ;
+wire \tick|Add0~13_sumout ;
+wire \tick|count[1]~2_combout ;
+wire \tick|count[1]~DUPLICATE_q ;
+wire \tick|Add0~14 ;
+wire \tick|Add0~17_sumout ;
+wire \tick|count[2]~3_combout ;
+wire \tick|count[2]~DUPLICATE_q ;
+wire \tick|Add0~18 ;
+wire \tick|Add0~33_sumout ;
+wire \tick|Add0~34 ;
+wire \tick|Add0~37_sumout ;
+wire \tick|Add0~38 ;
+wire \tick|Add0~41_sumout ;
+wire \tick|Add0~42 ;
+wire \tick|Add0~45_sumout ;
+wire \tick|Add0~46 ;
+wire \tick|Add0~21_sumout ;
+wire \tick|count[7]~4_combout ;
+wire \tick|count[7]~DUPLICATE_q ;
+wire \tick|Add0~22 ;
+wire \tick|Add0~25_sumout ;
+wire \tick|count[8]~5_combout ;
+wire \tick|Add0~26 ;
+wire \tick|Add0~1_sumout ;
+wire \tick|count[9]~0_combout ;
+wire \tick|count[9]~DUPLICATE_q ;
+wire \tick|Add0~2 ;
+wire \tick|Add0~5_sumout ;
+wire \tick|Add0~6 ;
+wire \tick|Add0~49_sumout ;
+wire \tick|count[11]~DUPLICATE_q ;
+wire \tick|Add0~50 ;
+wire \tick|Add0~29_sumout ;
+wire \tick|count[12]~6_combout ;
+wire \tick|count[4]~DUPLICATE_q ;
+wire \tick|count[3]~DUPLICATE_q ;
+wire \tick|count[6]~DUPLICATE_q ;
+wire \tick|Equal0~1_combout ;
+wire \tick|Equal0~0_combout ;
+wire \tick|count[13]~DUPLICATE_q ;
+wire \tick|Add0~30 ;
+wire \tick|Add0~53_sumout ;
+wire \tick|Add0~54 ;
+wire \tick|Add0~57_sumout ;
+wire \tick|Add0~58 ;
+wire \tick|Add0~61_sumout ;
+wire \tick|Equal0~2_combout ;
+wire \tick|Equal0~3_combout ;
+wire \tick|CLK_OUT~feeder_combout ;
+wire \tick|CLK_OUT~q ;
+wire \dac|sr_state.IDLE~0_combout ;
+wire \dac|sr_state.IDLE~q ;
+wire \dac|Selector2~0_combout ;
+wire \dac|sr_state.WAIT_CSB_HIGH~q ;
+wire \dac|sr_state.WAIT_CSB_FALL~0_combout ;
+wire \dac|sr_state.WAIT_CSB_FALL~q ;
+wire \dac|Selector3~0_combout ;
+wire \dac|state[2]~DUPLICATE_q ;
+wire \dac|WideNor0~combout ;
+wire \SPI_ADC|clk_1MHz~0_combout ;
+wire \SPI_ADC|clk_1MHz~q ;
+wire \ADC_SDO~input_o ;
+wire \SPI_ADC|state[1]~DUPLICATE_q ;
+wire \SPI_ADC|state[1]~1_combout ;
+wire \SPI_ADC|state[3]~DUPLICATE_q ;
+wire \SPI_ADC|state[3]~3_combout ;
+wire \SPI_ADC|state~0_combout ;
+wire \SPI_ADC|Selector4~0_combout ;
+wire \SPI_ADC|adc_cs~q ;
+wire \SPI_ADC|Selector2~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_ADC|Selector0~0_combout ;
+wire \SPI_ADC|sr_state.IDLE~q ;
+wire \SPI_ADC|Selector1~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_ADC|adc_start~0_combout ;
+wire \SPI_ADC|adc_start~q ;
+wire \SPI_ADC|Selector5~0_combout ;
+wire \SPI_ADC|state[2]~2_combout ;
+wire \SPI_ADC|WideOr0~0_combout ;
+wire \SPI_ADC|shift_ena~q ;
+wire \SPI_ADC|always3~0_combout ;
+wire \SPI_ADC|Decoder0~0_combout ;
+wire \SPI_ADC|adc_done~q ;
+wire \fin_address|Add0~1_sumout ;
+wire \fin_address|address[0]~feeder_combout ;
+wire \SPI_ADC|shift_reg[1]~feeder_combout ;
+wire \fin_address|Add0~2 ;
+wire \fin_address|Add0~5_sumout ;
+wire \fin_address|address[1]~feeder_combout ;
+wire \SPI_ADC|shift_reg[1]~DUPLICATE_q ;
+wire \fin_address|Add0~6 ;
+wire \fin_address|Add0~9_sumout ;
+wire \fin_address|address[2]~feeder_combout ;
+wire \SPI_ADC|shift_reg[3]~feeder_combout ;
+wire \fin_address|Add0~10 ;
+wire \fin_address|Add0~13_sumout ;
+wire \fin_address|address[3]~feeder_combout ;
+wire \fin_address|Add0~14 ;
+wire \fin_address|Add0~17_sumout ;
+wire \fin_address|address[4]~feeder_combout ;
+wire \SPI_ADC|shift_reg[5]~feeder_combout ;
+wire \fin_address|Add0~18 ;
+wire \fin_address|Add0~21_sumout ;
+wire \fin_address|address[5]~feeder_combout ;
+wire \SPI_ADC|shift_reg[6]~feeder_combout ;
+wire \fin_address|Add0~22 ;
+wire \fin_address|Add0~25_sumout ;
+wire \fin_address|address[6]~feeder_combout ;
+wire \SPI_ADC|shift_reg[7]~feeder_combout ;
+wire \fin_address|Add0~26 ;
+wire \fin_address|Add0~29_sumout ;
+wire \fin_address|address[7]~feeder_combout ;
+wire \fin_address|Add0~30 ;
+wire \fin_address|Add0~33_sumout ;
+wire \fin_address|address[8]~feeder_combout ;
+wire \SPI_ADC|shift_reg[8]~DUPLICATE_q ;
+wire \fin_address|Add0~34 ;
+wire \fin_address|Add0~37_sumout ;
+wire \fin_address|address[9]~feeder_combout ;
+wire \dac|shift_reg[11]~feeder_combout ;
+wire \dac|shift_reg[10]~feeder_combout ;
+wire \dac|shift_reg[9]~feeder_combout ;
+wire \dac|shift_reg[8]~feeder_combout ;
+wire \dac|shift_reg[7]~feeder_combout ;
+wire \dac|shift_reg[6]~feeder_combout ;
+wire \dac|shift_reg[5]~feeder_combout ;
+wire \dac|shift_reg[4]~feeder_combout ;
+wire \dac|shift_reg[3]~feeder_combout ;
+wire \dac|shift_reg~4_combout ;
+wire \dac|always5~0_combout ;
+wire \dac|shift_reg~3_combout ;
+wire \dac|shift_reg~2_combout ;
+wire \dac|shift_reg~1_combout ;
+wire \dac|shift_reg~0_combout ;
+wire \dac|Equal2~0_combout ;
+wire \dac|dac_sck~combout ;
+wire \SPI_ADC|state[2]~DUPLICATE_q ;
+wire \SPI_ADC|Selector6~0_combout ;
+wire \SPI_ADC|adc_din~q ;
+wire \SPI_ADC|adc_sck~combout ;
+wire \p|count[0]~0_combout ;
+wire \p|count[0]~DUPLICATE_q ;
+wire \p|Add0~33_sumout ;
+wire \p|Add0~34 ;
+wire \p|Add0~29_sumout ;
+wire \p|Add0~30 ;
+wire \p|Add0~25_sumout ;
+wire \p|Add0~26 ;
+wire \p|Add0~21_sumout ;
+wire \p|Add0~22 ;
+wire \p|Add0~17_sumout ;
+wire \p|Add0~18 ;
+wire \p|Add0~13_sumout ;
+wire \p|Add0~14 ;
+wire \p|Add0~9_sumout ;
+wire \p|Add0~10 ;
+wire \p|Add0~5_sumout ;
+wire \p|d[7]~feeder_combout ;
+wire \p|LessThan0~1_combout ;
+wire \p|d[0]~feeder_combout ;
+wire \p|LessThan0~2_combout ;
+wire \p|LessThan0~3_combout ;
+wire \p|LessThan0~4_combout ;
+wire \p|Add0~6 ;
+wire \p|Add0~1_sumout ;
+wire \p|LessThan0~0_combout ;
+wire \p|LessThan0~5_combout ;
+wire \p|pwm_out~q ;
+wire \mult|lpm_mult_component|mult_core|romout[1][17]~5_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[0][17]~4_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[0][16]~3_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[0][15]~2_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[0][14]~1_combout ;
+wire \mult|lpm_mult_component|mult_core|romout[1][9]~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ;
+wire \bcd|A2|WideOr1~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ;
+wire \bcd|A2|WideOr3~0_combout ;
+wire \bcd|A2|WideOr2~0_combout ;
+wire \bcd|A4|WideOr2~0_combout ;
+wire \bcd|A4|WideOr1~0_combout ;
+wire \bcd|A4|WideOr3~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ;
+wire \bcd|A6|WideOr1~0_combout ;
+wire \bcd|A6|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ;
+wire \bcd|A6|WideOr3~0_combout ;
+wire \bcd|A8|WideOr3~0_combout ;
+wire \bcd|A8|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ;
+wire \bcd|A8|WideOr1~0_combout ;
+wire \bcd|A11|WideOr3~0_combout ;
+wire \bcd|A11|WideOr1~0_combout ;
+wire \bcd|A11|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ;
+wire \bcd|A14|WideOr1~0_combout ;
+wire \bcd|A14|WideOr3~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ;
+wire \bcd|A14|WideOr2~0_combout ;
+wire \bcd|A17|WideOr1~0_combout ;
+wire \bcd|A17|WideOr3~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ;
+wire \bcd|A17|WideOr2~0_combout ;
+wire \bcd|A21|WideOr3~0_combout ;
+wire \bcd|A21|WideOr1~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ;
+wire \bcd|A21|WideOr2~0_combout ;
+wire \bcd|A25|WideOr3~0_combout ;
+wire \bcd|A25|WideOr1~0_combout ;
+wire \bcd|A25|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ;
+wire \bcd|A29|WideOr1~0_combout ;
+wire \bcd|A29|WideOr2~0_combout ;
+wire \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ;
+wire \bcd|A29|WideOr3~0_combout ;
+wire \h0|WideOr6~0_combout ;
+wire \h0|WideOr5~0_combout ;
+wire \h0|WideOr4~0_combout ;
+wire \h0|WideOr3~0_combout ;
+wire \h0|WideOr2~0_combout ;
+wire \h0|WideOr1~0_combout ;
+wire \h0|WideOr0~0_combout ;
+wire \bcd|A25|WideOr0~0_combout ;
+wire \bcd|A17|WideOr0~0_combout ;
+wire \bcd|A14|WideOr0~0_combout ;
+wire \bcd|A7|WideOr2~0_combout ;
+wire \bcd|A7|WideOr3~0_combout ;
+wire \bcd|A8|WideOr0~0_combout ;
+wire \bcd|A7|WideOr1~0_combout ;
+wire \bcd|A10|WideOr2~0_combout ;
+wire \bcd|A11|WideOr0~0_combout ;
+wire \bcd|A10|WideOr1~0_combout ;
+wire \bcd|A10|WideOr3~0_combout ;
+wire \bcd|A13|WideOr1~0_combout ;
+wire \bcd|A13|WideOr2~0_combout ;
+wire \bcd|A13|WideOr3~0_combout ;
+wire \bcd|A16|WideOr1~0_combout ;
+wire \bcd|A16|WideOr3~0_combout ;
+wire \bcd|A16|WideOr2~0_combout ;
+wire \bcd|A20|WideOr3~0_combout ;
+wire \bcd|A20|WideOr2~0_combout ;
+wire \bcd|A21|WideOr0~0_combout ;
+wire \bcd|A20|WideOr1~0_combout ;
+wire \bcd|A24|WideOr1~0_combout ;
+wire \bcd|A24|WideOr2~0_combout ;
+wire \bcd|A24|WideOr3~0_combout ;
+wire \bcd|A28|WideOr3~0_combout ;
+wire \bcd|A28|WideOr2~0_combout ;
+wire \bcd|A29|WideOr0~0_combout ;
+wire \bcd|A28|WideOr1~0_combout ;
+wire \h1|WideOr6~0_combout ;
+wire \h1|WideOr5~0_combout ;
+wire \h1|WideOr4~0_combout ;
+wire \h1|WideOr3~0_combout ;
+wire \h1|WideOr2~0_combout ;
+wire \h1|WideOr1~0_combout ;
+wire \h1|WideOr0~0_combout ;
+wire \bcd|A6|WideOr0~0_combout ;
+wire \bcd|A1|WideOr0~0_combout ;
+wire \bcd|A2|WideOr0~0_combout ;
+wire \bcd|A4|WideOr0~0_combout ;
+wire \bcd|A15|WideOr1~0_combout ;
+wire \bcd|A16|WideOr0~0_combout ;
+wire \bcd|A15|WideOr3~0_combout ;
+wire \bcd|A15|WideOr2~0_combout ;
+wire \bcd|A19|WideOr1~0_combout ;
+wire \bcd|A20|WideOr0~0_combout ;
+wire \bcd|A19|WideOr2~0_combout ;
+wire \bcd|A19|WideOr3~0_combout ;
+wire \bcd|A23|WideOr2~0_combout ;
+wire \bcd|A23|WideOr3~0_combout ;
+wire \bcd|A23|WideOr1~0_combout ;
+wire \bcd|A24|WideOr0~0_combout ;
+wire \bcd|A27|WideOr3~0_combout ;
+wire \bcd|A28|WideOr0~0_combout ;
+wire \bcd|A27|WideOr2~0_combout ;
+wire \bcd|A27|WideOr1~0_combout ;
+wire \h2|WideOr6~0_combout ;
+wire \h2|WideOr5~0_combout ;
+wire \h2|WideOr4~0_combout ;
+wire \h2|WideOr3~0_combout ;
+wire \h2|WideOr2~0_combout ;
+wire \h2|WideOr1~0_combout ;
+wire \h2|WideOr0~0_combout ;
+wire \bcd|A27|WideOr0~0_combout ;
+wire \bcd|A23|WideOr0~0_combout ;
+wire \bcd|A19|WideOr0~0_combout ;
+wire \bcd|A15|WideOr0~0_combout ;
+wire \bcd|A10|WideOr0~0_combout ;
+wire \bcd|A7|WideOr0~0_combout ;
+wire \bcd|A5|WideOr0~0_combout ;
+wire \bcd|A12|WideOr0~0_combout ;
+wire \bcd|A26|Decoder0~0_combout ;
+wire \bcd|A26|Decoder0~2_combout ;
+wire \bcd|A26|WideOr2~combout ;
+wire \bcd|A26|Decoder0~1_combout ;
+wire \bcd|A26|WideOr3~0_combout ;
+wire \bcd|A26|Decoder0~3_combout ;
+wire \bcd|A26|WideOr1~combout ;
+wire \h3|WideOr6~0_combout ;
+wire \h3|WideOr5~0_combout ;
+wire \h3|WideOr4~0_combout ;
+wire \h3|WideOr3~0_combout ;
+wire \h3|WideOr2~0_combout ;
+wire \h3|WideOr1~0_combout ;
+wire \h3|WideOr0~0_combout ;
+wire \bcd|A26|Decoder0~4_combout ;
+wire \bcd|A22|WideOr0~0_combout ;
+wire \h4|Decoder0~0_combout ;
+wire \bcd|A13|WideOr0~0_combout ;
+wire \h4|Decoder0~2_combout ;
+wire \bcd|A26|WideOr0~combout ;
+wire \h4|Decoder0~1_combout ;
+wire [4:0] \dac|state ;
+wire [9:0] \rom|altsyncram_component|auto_generated|q_a ;
+wire [15:0] \tick|count ;
+wire [9:0] \p|d ;
+wire [15:0] \dac|shift_reg ;
+wire [4:0] \SPI_ADC|ctr ;
+wire [4:0] \SPI_ADC|state ;
+wire [9:0] \p|count ;
+wire [9:0] \SPI_ADC|data_from_adc ;
+wire [9:0] \SPI_ADC|shift_reg ;
+wire [9:0] \fin_address|address ;
+
+wire [9:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
+
+assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
+assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
+assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
+assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
+assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
+assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
+assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
+assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];
+assign \rom|altsyncram_component|auto_generated|q_a [8] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8];
+assign \rom|altsyncram_component|auto_generated|q_a [9] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [9];
+
+// Location: IOOBUF_X82_Y0_N42
+cyclonev_io_obuf \DAC_CS~output (
+	.i(\dac|WideNor0~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_CS),
+	.obar());
+// synopsys translate_off
+defparam \DAC_CS~output .bus_hold = "false";
+defparam \DAC_CS~output .open_drain_output = "false";
+defparam \DAC_CS~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X58_Y0_N76
+cyclonev_io_obuf \DAC_SDI~output (
+	.i(\dac|shift_reg [15]),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_SDI),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SDI~output .bus_hold = "false";
+defparam \DAC_SDI~output .open_drain_output = "false";
+defparam \DAC_SDI~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X68_Y0_N36
+cyclonev_io_obuf \DAC_LD~output (
+	.i(!\dac|Equal2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_LD),
+	.obar());
+// synopsys translate_off
+defparam \DAC_LD~output .bus_hold = "false";
+defparam \DAC_LD~output .open_drain_output = "false";
+defparam \DAC_LD~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N2
+cyclonev_io_obuf \DAC_SCK~output (
+	.i(!\dac|dac_sck~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_SCK),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SCK~output .bus_hold = "false";
+defparam \DAC_SCK~output .open_drain_output = "false";
+defparam \DAC_SCK~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X54_Y0_N2
+cyclonev_io_obuf \ADC_SDI~output (
+	.i(\SPI_ADC|adc_din~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_SDI),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SDI~output .bus_hold = "false";
+defparam \ADC_SDI~output .open_drain_output = "false";
+defparam \ADC_SDI~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N19
+cyclonev_io_obuf \ADC_SCK~output (
+	.i(!\SPI_ADC|adc_sck~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_SCK),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SCK~output .bus_hold = "false";
+defparam \ADC_SCK~output .open_drain_output = "false";
+defparam \ADC_SCK~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N19
+cyclonev_io_obuf \ADC_CS~output (
+	.i(!\SPI_ADC|adc_cs~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_CS),
+	.obar());
+// synopsys translate_off
+defparam \ADC_CS~output .bus_hold = "false";
+defparam \ADC_CS~output .open_drain_output = "false";
+defparam \ADC_CS~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N36
+cyclonev_io_obuf \PWM_OUT~output (
+	.i(\p|pwm_out~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(PWM_OUT),
+	.obar());
+// synopsys translate_off
+defparam \PWM_OUT~output .bus_hold = "false";
+defparam \PWM_OUT~output .open_drain_output = "false";
+defparam \PWM_OUT~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N39
+cyclonev_io_obuf \HEX0[0]~output (
+	.i(\h0|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[0]~output .bus_hold = "false";
+defparam \HEX0[0]~output .open_drain_output = "false";
+defparam \HEX0[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N79
+cyclonev_io_obuf \HEX0[1]~output (
+	.i(\h0|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[1]~output .bus_hold = "false";
+defparam \HEX0[1]~output .open_drain_output = "false";
+defparam \HEX0[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N96
+cyclonev_io_obuf \HEX0[2]~output (
+	.i(\h0|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[2]~output .bus_hold = "false";
+defparam \HEX0[2]~output .open_drain_output = "false";
+defparam \HEX0[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N79
+cyclonev_io_obuf \HEX0[3]~output (
+	.i(\h0|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[3]~output .bus_hold = "false";
+defparam \HEX0[3]~output .open_drain_output = "false";
+defparam \HEX0[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N56
+cyclonev_io_obuf \HEX0[4]~output (
+	.i(\h0|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[4]~output .bus_hold = "false";
+defparam \HEX0[4]~output .open_drain_output = "false";
+defparam \HEX0[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N39
+cyclonev_io_obuf \HEX0[5]~output (
+	.i(\h0|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[5]~output .bus_hold = "false";
+defparam \HEX0[5]~output .open_drain_output = "false";
+defparam \HEX0[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N96
+cyclonev_io_obuf \HEX0[6]~output (
+	.i(!\h0|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[6]~output .bus_hold = "false";
+defparam \HEX0[6]~output .open_drain_output = "false";
+defparam \HEX0[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y6_N39
+cyclonev_io_obuf \HEX1[0]~output (
+	.i(!\h1|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[0]~output .bus_hold = "false";
+defparam \HEX1[0]~output .open_drain_output = "false";
+defparam \HEX1[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y6_N56
+cyclonev_io_obuf \HEX1[1]~output (
+	.i(\h1|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[1]~output .bus_hold = "false";
+defparam \HEX1[1]~output .open_drain_output = "false";
+defparam \HEX1[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N39
+cyclonev_io_obuf \HEX1[2]~output (
+	.i(\h1|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[2]~output .bus_hold = "false";
+defparam \HEX1[2]~output .open_drain_output = "false";
+defparam \HEX1[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N56
+cyclonev_io_obuf \HEX1[3]~output (
+	.i(!\h1|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[3]~output .bus_hold = "false";
+defparam \HEX1[3]~output .open_drain_output = "false";
+defparam \HEX1[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N39
+cyclonev_io_obuf \HEX1[4]~output (
+	.i(!\h1|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[4]~output .bus_hold = "false";
+defparam \HEX1[4]~output .open_drain_output = "false";
+defparam \HEX1[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N56
+cyclonev_io_obuf \HEX1[5]~output (
+	.i(!\h1|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[5]~output .bus_hold = "false";
+defparam \HEX1[5]~output .open_drain_output = "false";
+defparam \HEX1[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N56
+cyclonev_io_obuf \HEX1[6]~output (
+	.i(!\h1|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[6]~output .bus_hold = "false";
+defparam \HEX1[6]~output .open_drain_output = "false";
+defparam \HEX1[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N22
+cyclonev_io_obuf \HEX2[0]~output (
+	.i(!\h2|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[0]~output .bus_hold = "false";
+defparam \HEX2[0]~output .open_drain_output = "false";
+defparam \HEX2[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y23_N39
+cyclonev_io_obuf \HEX2[1]~output (
+	.i(\h2|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[1]~output .bus_hold = "false";
+defparam \HEX2[1]~output .open_drain_output = "false";
+defparam \HEX2[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y23_N56
+cyclonev_io_obuf \HEX2[2]~output (
+	.i(\h2|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[2]~output .bus_hold = "false";
+defparam \HEX2[2]~output .open_drain_output = "false";
+defparam \HEX2[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N79
+cyclonev_io_obuf \HEX2[3]~output (
+	.i(!\h2|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[3]~output .bus_hold = "false";
+defparam \HEX2[3]~output .open_drain_output = "false";
+defparam \HEX2[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y25_N39
+cyclonev_io_obuf \HEX2[4]~output (
+	.i(!\h2|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[4]~output .bus_hold = "false";
+defparam \HEX2[4]~output .open_drain_output = "false";
+defparam \HEX2[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N96
+cyclonev_io_obuf \HEX2[5]~output (
+	.i(!\h2|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[5]~output .bus_hold = "false";
+defparam \HEX2[5]~output .open_drain_output = "false";
+defparam \HEX2[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y25_N56
+cyclonev_io_obuf \HEX2[6]~output (
+	.i(!\h2|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[6]~output .bus_hold = "false";
+defparam \HEX2[6]~output .open_drain_output = "false";
+defparam \HEX2[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N5
+cyclonev_io_obuf \HEX3[0]~output (
+	.i(!\h3|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[0]~output .bus_hold = "false";
+defparam \HEX3[0]~output .open_drain_output = "false";
+defparam \HEX3[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N22
+cyclonev_io_obuf \HEX3[1]~output (
+	.i(\h3|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[1]~output .bus_hold = "false";
+defparam \HEX3[1]~output .open_drain_output = "false";
+defparam \HEX3[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N45
+cyclonev_io_obuf \HEX3[2]~output (
+	.i(\h3|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[2]~output .bus_hold = "false";
+defparam \HEX3[2]~output .open_drain_output = "false";
+defparam \HEX3[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N62
+cyclonev_io_obuf \HEX3[3]~output (
+	.i(!\h3|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[3]~output .bus_hold = "false";
+defparam \HEX3[3]~output .open_drain_output = "false";
+defparam \HEX3[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y21_N39
+cyclonev_io_obuf \HEX3[4]~output (
+	.i(!\h3|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[4]~output .bus_hold = "false";
+defparam \HEX3[4]~output .open_drain_output = "false";
+defparam \HEX3[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N62
+cyclonev_io_obuf \HEX3[5]~output (
+	.i(!\h3|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[5]~output .bus_hold = "false";
+defparam \HEX3[5]~output .open_drain_output = "false";
+defparam \HEX3[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N5
+cyclonev_io_obuf \HEX3[6]~output (
+	.i(!\h3|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[6]~output .bus_hold = "false";
+defparam \HEX3[6]~output .open_drain_output = "false";
+defparam \HEX3[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N45
+cyclonev_io_obuf \HEX4[0]~output (
+	.i(\h4|Decoder0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[0]~output .bus_hold = "false";
+defparam \HEX4[0]~output .open_drain_output = "false";
+defparam \HEX4[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N5
+cyclonev_io_obuf \HEX4[1]~output (
+	.i(gnd),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[1]~output .bus_hold = "false";
+defparam \HEX4[1]~output .open_drain_output = "false";
+defparam \HEX4[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N22
+cyclonev_io_obuf \HEX4[2]~output (
+	.i(\h4|Decoder0~2_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[2]~output .bus_hold = "false";
+defparam \HEX4[2]~output .open_drain_output = "false";
+defparam \HEX4[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N22
+cyclonev_io_obuf \HEX4[3]~output (
+	.i(\h4|Decoder0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[3]~output .bus_hold = "false";
+defparam \HEX4[3]~output .open_drain_output = "false";
+defparam \HEX4[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N22
+cyclonev_io_obuf \HEX4[4]~output (
+	.i(!\bcd|A26|WideOr0~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[4]~output .bus_hold = "false";
+defparam \HEX4[4]~output .open_drain_output = "false";
+defparam \HEX4[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N5
+cyclonev_io_obuf \HEX4[5]~output (
+	.i(!\h4|Decoder0~1_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[5]~output .bus_hold = "false";
+defparam \HEX4[5]~output .open_drain_output = "false";
+defparam \HEX4[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N45
+cyclonev_io_obuf \HEX4[6]~output (
+	.i(\bcd|A22|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX4[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX4[6]~output .bus_hold = "false";
+defparam \HEX4[6]~output .open_drain_output = "false";
+defparam \HEX4[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X32_Y0_N1
+cyclonev_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N57
+cyclonev_lcell_comb \dac|clk_1MHz~0 (
+// Equation(s):
+// \dac|clk_1MHz~0_combout  = !\dac|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(!\dac|clk_1MHz~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|clk_1MHz~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|clk_1MHz~0 .extended_lut = "off";
+defparam \dac|clk_1MHz~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;
+defparam \dac|clk_1MHz~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: CLKCTRL_G6
+cyclonev_clkena \CLOCK_50~inputCLKENA0 (
+	.inclk(\CLOCK_50~input_o ),
+	.ena(vcc),
+	.outclk(\CLOCK_50~inputCLKENA0_outclk ),
+	.enaout());
+// synopsys translate_off
+defparam \CLOCK_50~inputCLKENA0 .clock_type = "global clock";
+defparam \CLOCK_50~inputCLKENA0 .disable_mode = "low";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_mode = "always enabled";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_power_up = "high";
+defparam \CLOCK_50~inputCLKENA0 .test_syn = "high";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N44
+dffeas \SPI_ADC|ctr[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N42
+cyclonev_lcell_comb \SPI_ADC|ctr~1 (
+// Equation(s):
+// \SPI_ADC|ctr~1_combout  = ( !\SPI_ADC|ctr [0] & ( !\dac|Equal0~0_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SPI_ADC|ctr [0]),
+	.dataf(!\dac|Equal0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~1 .extended_lut = "off";
+defparam \SPI_ADC|ctr~1 .lut_mask = 64'hFFFF000000000000;
+defparam \SPI_ADC|ctr~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N43
+dffeas \SPI_ADC|ctr[0]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[0]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[0]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[0]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N57
+cyclonev_lcell_comb \SPI_ADC|ctr~2 (
+// Equation(s):
+// \SPI_ADC|ctr~2_combout  = ( \SPI_ADC|ctr [1] & ( \SPI_ADC|ctr[0]~DUPLICATE_q  & ( !\dac|Equal0~0_combout  ) ) ) # ( !\SPI_ADC|ctr [1] & ( !\SPI_ADC|ctr[0]~DUPLICATE_q  & ( !\dac|Equal0~0_combout  ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\dac|Equal0~0_combout ),
+	.datae(!\SPI_ADC|ctr [1]),
+	.dataf(!\SPI_ADC|ctr[0]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~2 .extended_lut = "off";
+defparam \SPI_ADC|ctr~2 .lut_mask = 64'hFF0000000000FF00;
+defparam \SPI_ADC|ctr~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N58
+dffeas \SPI_ADC|ctr[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N59
+dffeas \SPI_ADC|ctr[1]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[1]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[1]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N31
+dffeas \SPI_ADC|ctr[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N30
+cyclonev_lcell_comb \SPI_ADC|ctr~0 (
+// Equation(s):
+// \SPI_ADC|ctr~0_combout  = ( \SPI_ADC|ctr [2] & ( \SPI_ADC|ctr[0]~DUPLICATE_q  & ( !\dac|Equal0~0_combout  ) ) ) # ( \SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr[0]~DUPLICATE_q  & ( (\SPI_ADC|ctr[1]~DUPLICATE_q  & !\dac|Equal0~0_combout ) ) ) ) # ( !\SPI_ADC|ctr [2] 
+// & ( !\SPI_ADC|ctr[0]~DUPLICATE_q  & ( (!\SPI_ADC|ctr[1]~DUPLICATE_q  & !\dac|Equal0~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.datac(!\dac|Equal0~0_combout ),
+	.datad(gnd),
+	.datae(!\SPI_ADC|ctr [2]),
+	.dataf(!\SPI_ADC|ctr[0]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~0 .extended_lut = "off";
+defparam \SPI_ADC|ctr~0 .lut_mask = 64'hC0C030300000F0F0;
+defparam \SPI_ADC|ctr~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N32
+dffeas \SPI_ADC|ctr[2]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N27
+cyclonev_lcell_comb \SPI_ADC|Add0~1 (
+// Equation(s):
+// \SPI_ADC|Add0~1_combout  = ( \SPI_ADC|ctr [2] & ( \SPI_ADC|ctr [3] ) ) # ( !\SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr [3] $ (((\SPI_ADC|ctr[1]~DUPLICATE_q ) # (\SPI_ADC|ctr [0]))) ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|ctr [0]),
+	.datac(!\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.datad(!\SPI_ADC|ctr [3]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|ctr [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Add0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~1 .extended_lut = "off";
+defparam \SPI_ADC|Add0~1 .lut_mask = 64'hC03FC03F00FF00FF;
+defparam \SPI_ADC|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N29
+dffeas \SPI_ADC|ctr[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N24
+cyclonev_lcell_comb \SPI_ADC|Add0~0 (
+// Equation(s):
+// \SPI_ADC|Add0~0_combout  = ( \SPI_ADC|ctr [2] & ( \SPI_ADC|ctr [4] ) ) # ( !\SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr [4] $ ((((\SPI_ADC|ctr[1]~DUPLICATE_q ) # (\SPI_ADC|ctr [0])) # (\SPI_ADC|ctr [3]))) ) )
+
+	.dataa(!\SPI_ADC|ctr [3]),
+	.datab(!\SPI_ADC|ctr [0]),
+	.datac(!\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.datad(!\SPI_ADC|ctr [4]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|ctr [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Add0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~0 .extended_lut = "off";
+defparam \SPI_ADC|Add0~0 .lut_mask = 64'h807F807F00FF00FF;
+defparam \SPI_ADC|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N25
+dffeas \SPI_ADC|ctr[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N27
+cyclonev_lcell_comb \dac|Equal0~0 (
+// Equation(s):
+// \dac|Equal0~0_combout  = ( !\SPI_ADC|ctr [3] & ( (!\SPI_ADC|ctr [1] & (!\SPI_ADC|ctr[2]~DUPLICATE_q  & (!\SPI_ADC|ctr [0] & !\SPI_ADC|ctr [4]))) ) )
+
+	.dataa(!\SPI_ADC|ctr [1]),
+	.datab(!\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.datac(!\SPI_ADC|ctr [0]),
+	.datad(!\SPI_ADC|ctr [4]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|ctr [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Equal0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Equal0~0 .extended_lut = "off";
+defparam \dac|Equal0~0 .lut_mask = 64'h8000800000000000;
+defparam \dac|Equal0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N32
+dffeas \dac|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(gnd),
+	.asdata(\dac|clk_1MHz~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\dac|Equal0~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|clk_1MHz .is_wysiwyg = "true";
+defparam \dac|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N3
+cyclonev_lcell_comb \dac|state~2 (
+// Equation(s):
+// \dac|state~2_combout  = ( \dac|state [2] & ( (!\dac|state [0]) # (!\dac|state [1]) ) ) # ( !\dac|state [2] & ( (\dac|state [0] & \dac|state [1]) ) )
+
+	.dataa(!\dac|state [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\dac|state [1]),
+	.datae(gnd),
+	.dataf(!\dac|state [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state~2 .extended_lut = "off";
+defparam \dac|state~2 .lut_mask = 64'h00550055FFAAFFAA;
+defparam \dac|state~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N8
+dffeas \dac|state[2] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~2_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[2] .is_wysiwyg = "true";
+defparam \dac|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N21
+cyclonev_lcell_comb \dac|state~3 (
+// Equation(s):
+// \dac|state~3_combout  = ( \dac|state [1] & ( !\dac|state [3] $ (((!\dac|state [2]) # (!\dac|state [0]))) ) ) # ( !\dac|state [1] & ( \dac|state [3] ) )
+
+	.dataa(!\dac|state [3]),
+	.datab(gnd),
+	.datac(!\dac|state [2]),
+	.datad(!\dac|state [0]),
+	.datae(gnd),
+	.dataf(!\dac|state [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state~3 .extended_lut = "off";
+defparam \dac|state~3 .lut_mask = 64'h55555555555A555A;
+defparam \dac|state~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N29
+dffeas \dac|state[3] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~3_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[3] .is_wysiwyg = "true";
+defparam \dac|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N12
+cyclonev_lcell_comb \dac|state~0 (
+// Equation(s):
+// \dac|state~0_combout  = ( \dac|state [1] & ( !\dac|state[4]~DUPLICATE_q  $ (((!\dac|state [2]) # ((!\dac|state [0]) # (!\dac|state [3])))) ) ) # ( !\dac|state [1] & ( (\dac|state[4]~DUPLICATE_q  & (((!\dac|state [0]) # (\dac|state [3])) # (\dac|state 
+// [2]))) ) )
+
+	.dataa(!\dac|state[4]~DUPLICATE_q ),
+	.datab(!\dac|state [2]),
+	.datac(!\dac|state [0]),
+	.datad(!\dac|state [3]),
+	.datae(gnd),
+	.dataf(!\dac|state [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state~0 .extended_lut = "off";
+defparam \dac|state~0 .lut_mask = 64'h5155515555565556;
+defparam \dac|state~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N36
+cyclonev_lcell_comb \dac|state[4]~feeder (
+// Equation(s):
+// \dac|state[4]~feeder_combout  = \dac|state~0_combout 
+
+	.dataa(gnd),
+	.datab(!\dac|state~0_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state[4]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state[4]~feeder .extended_lut = "off";
+defparam \dac|state[4]~feeder .lut_mask = 64'h3333333333333333;
+defparam \dac|state[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N37
+dffeas \dac|state[4]~DUPLICATE (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|state[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state[4]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[4]~DUPLICATE .is_wysiwyg = "true";
+defparam \dac|state[4]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N27
+cyclonev_lcell_comb \dac|state~1 (
+// Equation(s):
+// \dac|state~1_combout  = ( \dac|state[4]~DUPLICATE_q  & ( (!\dac|state [0] & (\dac|state [1])) # (\dac|state [0] & (!\dac|state [1] & ((\dac|state [3]) # (\dac|state [2])))) ) ) # ( !\dac|state[4]~DUPLICATE_q  & ( !\dac|state [0] $ (!\dac|state [1]) ) )
+
+	.dataa(!\dac|state [0]),
+	.datab(!\dac|state [1]),
+	.datac(!\dac|state [2]),
+	.datad(!\dac|state [3]),
+	.datae(gnd),
+	.dataf(!\dac|state[4]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|state~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|state~1 .extended_lut = "off";
+defparam \dac|state~1 .lut_mask = 64'h6666666626662666;
+defparam \dac|state~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N5
+dffeas \dac|state[1] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~1_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[1] .is_wysiwyg = "true";
+defparam \dac|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N49
+dffeas \tick|count[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[9]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[9] .is_wysiwyg = "true";
+defparam \tick|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N0
+cyclonev_lcell_comb \tick|Add0~9 (
+// Equation(s):
+// \tick|Add0~9_sumout  = SUM(( !\tick|count [0] ) + ( VCC ) + ( !VCC ))
+// \tick|Add0~10  = CARRY(( !\tick|count [0] ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [0]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~9_sumout ),
+	.cout(\tick|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~9 .extended_lut = "off";
+defparam \tick|Add0~9 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N54
+cyclonev_lcell_comb \tick|count[0]~1 (
+// Equation(s):
+// \tick|count[0]~1_combout  = !\tick|Add0~9_sumout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|Add0~9_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[0]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[0]~1 .extended_lut = "off";
+defparam \tick|count[0]~1 .lut_mask = 64'hFF00FF00FF00FF00;
+defparam \tick|count[0]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N56
+dffeas \tick|count[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[0]~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[0] .is_wysiwyg = "true";
+defparam \tick|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N3
+cyclonev_lcell_comb \tick|Add0~13 (
+// Equation(s):
+// \tick|Add0~13_sumout  = SUM(( !\tick|count[1]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~10  ))
+// \tick|Add0~14  = CARRY(( !\tick|count[1]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count[1]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~13_sumout ),
+	.cout(\tick|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~13 .extended_lut = "off";
+defparam \tick|Add0~13 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y6_N57
+cyclonev_lcell_comb \tick|count[1]~2 (
+// Equation(s):
+// \tick|count[1]~2_combout  = ( !\tick|Add0~13_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\tick|Add0~13_sumout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[1]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[1]~2 .extended_lut = "off";
+defparam \tick|count[1]~2 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \tick|count[1]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N58
+dffeas \tick|count[1]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[1]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[1]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[1]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[1]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N6
+cyclonev_lcell_comb \tick|Add0~17 (
+// Equation(s):
+// \tick|Add0~17_sumout  = SUM(( !\tick|count[2]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~14  ))
+// \tick|Add0~18  = CARRY(( !\tick|count[2]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count[2]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~17_sumout ),
+	.cout(\tick|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~17 .extended_lut = "off";
+defparam \tick|Add0~17 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y6_N21
+cyclonev_lcell_comb \tick|count[2]~3 (
+// Equation(s):
+// \tick|count[2]~3_combout  = ( !\tick|Add0~17_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~17_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[2]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[2]~3 .extended_lut = "off";
+defparam \tick|count[2]~3 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[2]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N22
+dffeas \tick|count[2]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[2]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N9
+cyclonev_lcell_comb \tick|Add0~33 (
+// Equation(s):
+// \tick|Add0~33_sumout  = SUM(( \tick|count [3] ) + ( VCC ) + ( \tick|Add0~18  ))
+// \tick|Add0~34  = CARRY(( \tick|count [3] ) + ( VCC ) + ( \tick|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~33_sumout ),
+	.cout(\tick|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~33 .extended_lut = "off";
+defparam \tick|Add0~33 .lut_mask = 64'h00000000000000FF;
+defparam \tick|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N10
+dffeas \tick|count[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[3] .is_wysiwyg = "true";
+defparam \tick|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N12
+cyclonev_lcell_comb \tick|Add0~37 (
+// Equation(s):
+// \tick|Add0~37_sumout  = SUM(( \tick|count [4] ) + ( VCC ) + ( \tick|Add0~34  ))
+// \tick|Add0~38  = CARRY(( \tick|count [4] ) + ( VCC ) + ( \tick|Add0~34  ))
+
+	.dataa(gnd),
+	.datab(!\tick|count [4]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~37_sumout ),
+	.cout(\tick|Add0~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~37 .extended_lut = "off";
+defparam \tick|Add0~37 .lut_mask = 64'h0000000000003333;
+defparam \tick|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N14
+dffeas \tick|count[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~37_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[4] .is_wysiwyg = "true";
+defparam \tick|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N15
+cyclonev_lcell_comb \tick|Add0~41 (
+// Equation(s):
+// \tick|Add0~41_sumout  = SUM(( \tick|count [5] ) + ( VCC ) + ( \tick|Add0~38  ))
+// \tick|Add0~42  = CARRY(( \tick|count [5] ) + ( VCC ) + ( \tick|Add0~38  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\tick|count [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~41_sumout ),
+	.cout(\tick|Add0~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~41 .extended_lut = "off";
+defparam \tick|Add0~41 .lut_mask = 64'h0000000000000F0F;
+defparam \tick|Add0~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N17
+dffeas \tick|count[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~41_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[5] .is_wysiwyg = "true";
+defparam \tick|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N18
+cyclonev_lcell_comb \tick|Add0~45 (
+// Equation(s):
+// \tick|Add0~45_sumout  = SUM(( \tick|count [6] ) + ( VCC ) + ( \tick|Add0~42  ))
+// \tick|Add0~46  = CARRY(( \tick|count [6] ) + ( VCC ) + ( \tick|Add0~42  ))
+
+	.dataa(!\tick|count [6]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~45_sumout ),
+	.cout(\tick|Add0~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~45 .extended_lut = "off";
+defparam \tick|Add0~45 .lut_mask = 64'h0000000000005555;
+defparam \tick|Add0~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N20
+dffeas \tick|count[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~45_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[6] .is_wysiwyg = "true";
+defparam \tick|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N21
+cyclonev_lcell_comb \tick|Add0~21 (
+// Equation(s):
+// \tick|Add0~21_sumout  = SUM(( !\tick|count[7]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~46  ))
+// \tick|Add0~22  = CARRY(( !\tick|count[7]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~46  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count[7]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~21_sumout ),
+	.cout(\tick|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~21 .extended_lut = "off";
+defparam \tick|Add0~21 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y6_N33
+cyclonev_lcell_comb \tick|count[7]~4 (
+// Equation(s):
+// \tick|count[7]~4_combout  = ( !\tick|Add0~21_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\tick|Add0~21_sumout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[7]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[7]~4 .extended_lut = "off";
+defparam \tick|count[7]~4 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \tick|count[7]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N34
+dffeas \tick|count[7]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[7]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[7]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[7]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[7]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N24
+cyclonev_lcell_comb \tick|Add0~25 (
+// Equation(s):
+// \tick|Add0~25_sumout  = SUM(( !\tick|count [8] ) + ( VCC ) + ( \tick|Add0~22  ))
+// \tick|Add0~26  = CARRY(( !\tick|count [8] ) + ( VCC ) + ( \tick|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [8]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~25_sumout ),
+	.cout(\tick|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~25 .extended_lut = "off";
+defparam \tick|Add0~25 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y6_N42
+cyclonev_lcell_comb \tick|count[8]~5 (
+// Equation(s):
+// \tick|count[8]~5_combout  = ( !\tick|Add0~25_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[8]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[8]~5 .extended_lut = "off";
+defparam \tick|count[8]~5 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[8]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N43
+dffeas \tick|count[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[8]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[8] .is_wysiwyg = "true";
+defparam \tick|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N27
+cyclonev_lcell_comb \tick|Add0~1 (
+// Equation(s):
+// \tick|Add0~1_sumout  = SUM(( !\tick|count [9] ) + ( VCC ) + ( \tick|Add0~26  ))
+// \tick|Add0~2  = CARRY(( !\tick|count [9] ) + ( VCC ) + ( \tick|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\tick|count [9]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~1_sumout ),
+	.cout(\tick|Add0~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~1 .extended_lut = "off";
+defparam \tick|Add0~1 .lut_mask = 64'h000000000000FF00;
+defparam \tick|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y6_N48
+cyclonev_lcell_comb \tick|count[9]~0 (
+// Equation(s):
+// \tick|count[9]~0_combout  = ( !\tick|Add0~1_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[9]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[9]~0 .extended_lut = "off";
+defparam \tick|count[9]~0 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[9]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N50
+dffeas \tick|count[9]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[9]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[9]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[9]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[9]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N30
+cyclonev_lcell_comb \tick|Add0~5 (
+// Equation(s):
+// \tick|Add0~5_sumout  = SUM(( \tick|count [10] ) + ( VCC ) + ( \tick|Add0~2  ))
+// \tick|Add0~6  = CARRY(( \tick|count [10] ) + ( VCC ) + ( \tick|Add0~2  ))
+
+	.dataa(gnd),
+	.datab(!\tick|count [10]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~5_sumout ),
+	.cout(\tick|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~5 .extended_lut = "off";
+defparam \tick|Add0~5 .lut_mask = 64'h0000000000003333;
+defparam \tick|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N32
+dffeas \tick|count[10] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[10] .is_wysiwyg = "true";
+defparam \tick|count[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N33
+cyclonev_lcell_comb \tick|Add0~49 (
+// Equation(s):
+// \tick|Add0~49_sumout  = SUM(( \tick|count[11]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~6  ))
+// \tick|Add0~50  = CARRY(( \tick|count[11]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~6  ))
+
+	.dataa(!\tick|count[11]~DUPLICATE_q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~49_sumout ),
+	.cout(\tick|Add0~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~49 .extended_lut = "off";
+defparam \tick|Add0~49 .lut_mask = 64'h0000000000005555;
+defparam \tick|Add0~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N35
+dffeas \tick|count[11]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~49_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[11]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[11]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[11]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N36
+cyclonev_lcell_comb \tick|Add0~29 (
+// Equation(s):
+// \tick|Add0~29_sumout  = SUM(( !\tick|count [12] ) + ( VCC ) + ( \tick|Add0~50  ))
+// \tick|Add0~30  = CARRY(( !\tick|count [12] ) + ( VCC ) + ( \tick|Add0~50  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\tick|count [12]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~29_sumout ),
+	.cout(\tick|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~29 .extended_lut = "off";
+defparam \tick|Add0~29 .lut_mask = 64'h000000000000F0F0;
+defparam \tick|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N51
+cyclonev_lcell_comb \tick|count[12]~6 (
+// Equation(s):
+// \tick|count[12]~6_combout  = ( !\tick|Add0~29_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|count[12]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|count[12]~6 .extended_lut = "off";
+defparam \tick|count[12]~6 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \tick|count[12]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N53
+dffeas \tick|count[12] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[12]~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[12] .is_wysiwyg = "true";
+defparam \tick|count[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N13
+dffeas \tick|count[4]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~37_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[4]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[4]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[4]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N11
+dffeas \tick|count[3]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[3]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[3]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[3]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N19
+dffeas \tick|count[6]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~45_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[6]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[6]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[6]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N48
+cyclonev_lcell_comb \tick|Equal0~1 (
+// Equation(s):
+// \tick|Equal0~1_combout  = ( !\tick|count[6]~DUPLICATE_q  & ( (\tick|count [12] & (!\tick|count[4]~DUPLICATE_q  & (!\tick|count[3]~DUPLICATE_q  & !\tick|count [5]))) ) )
+
+	.dataa(!\tick|count [12]),
+	.datab(!\tick|count[4]~DUPLICATE_q ),
+	.datac(!\tick|count[3]~DUPLICATE_q ),
+	.datad(!\tick|count [5]),
+	.datae(gnd),
+	.dataf(!\tick|count[6]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|Equal0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Equal0~1 .extended_lut = "off";
+defparam \tick|Equal0~1 .lut_mask = 64'h4000400000000000;
+defparam \tick|Equal0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N59
+dffeas \tick|count[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[1]~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[1] .is_wysiwyg = "true";
+defparam \tick|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N23
+dffeas \tick|count[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[2]~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[2] .is_wysiwyg = "true";
+defparam \tick|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N35
+dffeas \tick|count[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|count[7]~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[7] .is_wysiwyg = "true";
+defparam \tick|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y6_N27
+cyclonev_lcell_comb \tick|Equal0~0 (
+// Equation(s):
+// \tick|Equal0~0_combout  = ( \tick|count [0] & ( \tick|count [7] & ( (\tick|count [1] & (\tick|count [2] & \tick|count [8])) ) ) )
+
+	.dataa(gnd),
+	.datab(!\tick|count [1]),
+	.datac(!\tick|count [2]),
+	.datad(!\tick|count [8]),
+	.datae(!\tick|count [0]),
+	.dataf(!\tick|count [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|Equal0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Equal0~0 .extended_lut = "off";
+defparam \tick|Equal0~0 .lut_mask = 64'h0000000000000003;
+defparam \tick|Equal0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N40
+dffeas \tick|count[13]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~53_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count[13]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[13]~DUPLICATE .is_wysiwyg = "true";
+defparam \tick|count[13]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N39
+cyclonev_lcell_comb \tick|Add0~53 (
+// Equation(s):
+// \tick|Add0~53_sumout  = SUM(( \tick|count[13]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~30  ))
+// \tick|Add0~54  = CARRY(( \tick|count[13]~DUPLICATE_q  ) + ( VCC ) + ( \tick|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\tick|count[13]~DUPLICATE_q ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~53_sumout ),
+	.cout(\tick|Add0~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~53 .extended_lut = "off";
+defparam \tick|Add0~53 .lut_mask = 64'h0000000000000F0F;
+defparam \tick|Add0~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N41
+dffeas \tick|count[13] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~53_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[13] .is_wysiwyg = "true";
+defparam \tick|count[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N34
+dffeas \tick|count[11] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~49_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[11] .is_wysiwyg = "true";
+defparam \tick|count[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N42
+cyclonev_lcell_comb \tick|Add0~57 (
+// Equation(s):
+// \tick|Add0~57_sumout  = SUM(( \tick|count [14] ) + ( VCC ) + ( \tick|Add0~54  ))
+// \tick|Add0~58  = CARRY(( \tick|count [14] ) + ( VCC ) + ( \tick|Add0~54  ))
+
+	.dataa(gnd),
+	.datab(!\tick|count [14]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~57_sumout ),
+	.cout(\tick|Add0~58 ),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~57 .extended_lut = "off";
+defparam \tick|Add0~57 .lut_mask = 64'h0000000000003333;
+defparam \tick|Add0~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N44
+dffeas \tick|count[14] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~57_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[14] .is_wysiwyg = "true";
+defparam \tick|count[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N45
+cyclonev_lcell_comb \tick|Add0~61 (
+// Equation(s):
+// \tick|Add0~61_sumout  = SUM(( \tick|count [15] ) + ( VCC ) + ( \tick|Add0~58  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\tick|count [15]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\tick|Add0~58 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\tick|Add0~61_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Add0~61 .extended_lut = "off";
+defparam \tick|Add0~61 .lut_mask = 64'h0000000000000F0F;
+defparam \tick|Add0~61 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X82_Y6_N46
+dffeas \tick|count[15] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\tick|Add0~61_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\tick|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|count [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|count[15] .is_wysiwyg = "true";
+defparam \tick|count[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y6_N36
+cyclonev_lcell_comb \tick|Equal0~2 (
+// Equation(s):
+// \tick|Equal0~2_combout  = ( !\tick|count [15] & ( (!\tick|count [13] & (!\tick|count [11] & !\tick|count [14])) ) )
+
+	.dataa(!\tick|count [13]),
+	.datab(!\tick|count [11]),
+	.datac(!\tick|count [14]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\tick|count [15]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|Equal0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Equal0~2 .extended_lut = "off";
+defparam \tick|Equal0~2 .lut_mask = 64'h8080808000000000;
+defparam \tick|Equal0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X82_Y6_N57
+cyclonev_lcell_comb \tick|Equal0~3 (
+// Equation(s):
+// \tick|Equal0~3_combout  = ( !\tick|count [10] & ( (\tick|count[9]~DUPLICATE_q  & (\tick|Equal0~1_combout  & (\tick|Equal0~0_combout  & \tick|Equal0~2_combout ))) ) )
+
+	.dataa(!\tick|count[9]~DUPLICATE_q ),
+	.datab(!\tick|Equal0~1_combout ),
+	.datac(!\tick|Equal0~0_combout ),
+	.datad(!\tick|Equal0~2_combout ),
+	.datae(gnd),
+	.dataf(!\tick|count [10]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|Equal0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|Equal0~3 .extended_lut = "off";
+defparam \tick|Equal0~3 .lut_mask = 64'h0001000100000000;
+defparam \tick|Equal0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y6_N12
+cyclonev_lcell_comb \tick|CLK_OUT~feeder (
+// Equation(s):
+// \tick|CLK_OUT~feeder_combout  = \tick|Equal0~3_combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\tick|Equal0~3_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\tick|CLK_OUT~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \tick|CLK_OUT~feeder .extended_lut = "off";
+defparam \tick|CLK_OUT~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \tick|CLK_OUT~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X81_Y6_N14
+dffeas \tick|CLK_OUT (
+	.clk(\CLOCK_50~input_o ),
+	.d(\tick|CLK_OUT~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\tick|CLK_OUT~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \tick|CLK_OUT .is_wysiwyg = "true";
+defparam \tick|CLK_OUT .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N30
+cyclonev_lcell_comb \dac|sr_state.IDLE~0 (
+// Equation(s):
+// \dac|sr_state.IDLE~0_combout  = ( \dac|sr_state.WAIT_CSB_FALL~q  & ( (!\dac|WideNor0~combout ) # ((!\dac|sr_state.WAIT_CSB_HIGH~q  & ((\dac|sr_state.IDLE~q ) # (\tick|CLK_OUT~q )))) ) ) # ( !\dac|sr_state.WAIT_CSB_FALL~q  & ( 
+// (!\dac|sr_state.WAIT_CSB_HIGH~q  & (((\dac|sr_state.IDLE~q ) # (\tick|CLK_OUT~q )))) # (\dac|sr_state.WAIT_CSB_HIGH~q  & (!\dac|WideNor0~combout  & ((\dac|sr_state.IDLE~q ) # (\tick|CLK_OUT~q )))) ) )
+
+	.dataa(!\dac|sr_state.WAIT_CSB_HIGH~q ),
+	.datab(!\dac|WideNor0~combout ),
+	.datac(!\tick|CLK_OUT~q ),
+	.datad(!\dac|sr_state.IDLE~q ),
+	.datae(gnd),
+	.dataf(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|sr_state.IDLE~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|sr_state.IDLE~0 .extended_lut = "off";
+defparam \dac|sr_state.IDLE~0 .lut_mask = 64'h0EEE0EEECEEECEEE;
+defparam \dac|sr_state.IDLE~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N32
+dffeas \dac|sr_state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|sr_state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|sr_state.IDLE .is_wysiwyg = "true";
+defparam \dac|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N48
+cyclonev_lcell_comb \dac|Selector2~0 (
+// Equation(s):
+// \dac|Selector2~0_combout  = ( \dac|state [0] & ( \dac|state[4]~DUPLICATE_q  & ( (\dac|sr_state.IDLE~q  & (((\dac|state [2]) # (\dac|state [3])) # (\dac|state [1]))) ) ) ) # ( !\dac|state [0] & ( \dac|state[4]~DUPLICATE_q  & ( \dac|sr_state.IDLE~q  ) ) ) # 
+// ( \dac|state [0] & ( !\dac|state[4]~DUPLICATE_q  & ( \dac|sr_state.IDLE~q  ) ) ) # ( !\dac|state [0] & ( !\dac|state[4]~DUPLICATE_q  & ( (\dac|sr_state.IDLE~q  & (((\dac|state [2]) # (\dac|state [3])) # (\dac|state [1]))) ) ) )
+
+	.dataa(!\dac|state [1]),
+	.datab(!\dac|sr_state.IDLE~q ),
+	.datac(!\dac|state [3]),
+	.datad(!\dac|state [2]),
+	.datae(!\dac|state [0]),
+	.dataf(!\dac|state[4]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Selector2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Selector2~0 .extended_lut = "off";
+defparam \dac|Selector2~0 .lut_mask = 64'h1333333333331333;
+defparam \dac|Selector2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N50
+dffeas \dac|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \dac|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N33
+cyclonev_lcell_comb \dac|sr_state.WAIT_CSB_FALL~0 (
+// Equation(s):
+// \dac|sr_state.WAIT_CSB_FALL~0_combout  = ( \tick|CLK_OUT~q  & ( (!\dac|WideNor0~combout  & (((!\dac|sr_state.IDLE~q  & !\dac|sr_state.WAIT_CSB_FALL~q )))) # (\dac|WideNor0~combout  & (!\dac|sr_state.WAIT_CSB_HIGH~q  & ((!\dac|sr_state.IDLE~q ) # 
+// (\dac|sr_state.WAIT_CSB_FALL~q )))) ) ) # ( !\tick|CLK_OUT~q  & ( (!\dac|sr_state.WAIT_CSB_HIGH~q  & (\dac|WideNor0~combout  & \dac|sr_state.WAIT_CSB_FALL~q )) ) )
+
+	.dataa(!\dac|sr_state.WAIT_CSB_HIGH~q ),
+	.datab(!\dac|WideNor0~combout ),
+	.datac(!\dac|sr_state.IDLE~q ),
+	.datad(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datae(gnd),
+	.dataf(!\tick|CLK_OUT~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|sr_state.WAIT_CSB_FALL~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|sr_state.WAIT_CSB_FALL~0 .extended_lut = "off";
+defparam \dac|sr_state.WAIT_CSB_FALL~0 .lut_mask = 64'h00220022E022E022;
+defparam \dac|sr_state.WAIT_CSB_FALL~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N35
+dffeas \dac|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\dac|sr_state.WAIT_CSB_FALL~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \dac|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N9
+cyclonev_lcell_comb \dac|Selector3~0 (
+// Equation(s):
+// \dac|Selector3~0_combout  = ( \dac|state [1] & ( \dac|state[4]~DUPLICATE_q  & ( !\dac|state [0] ) ) ) # ( !\dac|state [1] & ( \dac|state[4]~DUPLICATE_q  & ( !\dac|state [0] ) ) ) # ( \dac|state [1] & ( !\dac|state[4]~DUPLICATE_q  & ( !\dac|state [0] ) ) ) 
+// # ( !\dac|state [1] & ( !\dac|state[4]~DUPLICATE_q  & ( (!\dac|state [0] & (((\dac|state [3]) # (\dac|state [2])) # (\dac|sr_state.WAIT_CSB_FALL~q ))) ) ) )
+
+	.dataa(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datab(!\dac|state [0]),
+	.datac(!\dac|state [2]),
+	.datad(!\dac|state [3]),
+	.datae(!\dac|state [1]),
+	.dataf(!\dac|state[4]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Selector3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Selector3~0 .extended_lut = "off";
+defparam \dac|Selector3~0 .lut_mask = 64'h4CCCCCCCCCCCCCCC;
+defparam \dac|Selector3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N23
+dffeas \dac|state[0] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|Selector3~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[0] .is_wysiwyg = "true";
+defparam \dac|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N7
+dffeas \dac|state[2]~DUPLICATE (
+	.clk(\dac|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\dac|state~2_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \dac|state[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N57
+cyclonev_lcell_comb \dac|WideNor0 (
+// Equation(s):
+// \dac|WideNor0~combout  = ( \dac|state[4]~DUPLICATE_q  & ( (\dac|state [0] & (!\dac|state[2]~DUPLICATE_q  & (!\dac|state [3] & !\dac|state [1]))) ) ) # ( !\dac|state[4]~DUPLICATE_q  & ( (!\dac|state [0] & (!\dac|state[2]~DUPLICATE_q  & (!\dac|state [3] & 
+// !\dac|state [1]))) ) )
+
+	.dataa(!\dac|state [0]),
+	.datab(!\dac|state[2]~DUPLICATE_q ),
+	.datac(!\dac|state [3]),
+	.datad(!\dac|state [1]),
+	.datae(gnd),
+	.dataf(!\dac|state[4]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|WideNor0~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|WideNor0 .extended_lut = "off";
+defparam \dac|WideNor0 .lut_mask = 64'h8000800040004000;
+defparam \dac|WideNor0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N24
+cyclonev_lcell_comb \SPI_ADC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_ADC|clk_1MHz~0_combout  = ( !\SPI_ADC|clk_1MHz~q  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|clk_1MHz~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|clk_1MHz~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~0 .extended_lut = "off";
+defparam \SPI_ADC|clk_1MHz~0 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \SPI_ADC|clk_1MHz~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N59
+dffeas \SPI_ADC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(gnd),
+	.asdata(\SPI_ADC|clk_1MHz~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\dac|Equal0~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_ADC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y0_N52
+cyclonev_io_ibuf \ADC_SDO~input (
+	.i(ADC_SDO),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\ADC_SDO~input_o ));
+// synopsys translate_off
+defparam \ADC_SDO~input .bus_hold = "false";
+defparam \ADC_SDO~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N37
+dffeas \SPI_ADC|state[1]~DUPLICATE (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[1]~1_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state[1]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[1]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|state[1]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N48
+cyclonev_lcell_comb \SPI_ADC|state[1]~1 (
+// Equation(s):
+// \SPI_ADC|state[1]~1_combout  = ( \SPI_ADC|state[1]~DUPLICATE_q  & ( !\SPI_ADC|state [0] ) ) # ( !\SPI_ADC|state[1]~DUPLICATE_q  & ( \SPI_ADC|state [0] ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state[1]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[1]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[1]~1 .extended_lut = "off";
+defparam \SPI_ADC|state[1]~1 .lut_mask = 64'h33333333CCCCCCCC;
+defparam \SPI_ADC|state[1]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N38
+dffeas \SPI_ADC|state[1] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[1]~1_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N4
+dffeas \SPI_ADC|state[3]~DUPLICATE (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[3]~3_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state[3]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[3]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|state[3]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N27
+cyclonev_lcell_comb \SPI_ADC|state[3]~3 (
+// Equation(s):
+// \SPI_ADC|state[3]~3_combout  = ( \SPI_ADC|state [2] & ( !\SPI_ADC|state[3]~DUPLICATE_q  $ (((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [1]))) ) ) # ( !\SPI_ADC|state [2] & ( \SPI_ADC|state[3]~DUPLICATE_q  ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|state[3]~DUPLICATE_q ),
+	.datac(!\SPI_ADC|state [0]),
+	.datad(!\SPI_ADC|state [1]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[3]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[3]~3 .extended_lut = "off";
+defparam \SPI_ADC|state[3]~3 .lut_mask = 64'h33333333333C333C;
+defparam \SPI_ADC|state[3]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N5
+dffeas \SPI_ADC|state[3] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[3]~3_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N30
+cyclonev_lcell_comb \SPI_ADC|state~0 (
+// Equation(s):
+// \SPI_ADC|state~0_combout  = ( \SPI_ADC|state [0] & ( !\SPI_ADC|state [4] $ (((!\SPI_ADC|state [1]) # ((!\SPI_ADC|state [2]) # (!\SPI_ADC|state [3])))) ) ) # ( !\SPI_ADC|state [0] & ( (\SPI_ADC|state [4] & (((\SPI_ADC|state [3]) # (\SPI_ADC|state [2])) # 
+// (\SPI_ADC|state [1]))) ) )
+
+	.dataa(!\SPI_ADC|state [1]),
+	.datab(!\SPI_ADC|state [2]),
+	.datac(!\SPI_ADC|state [3]),
+	.datad(!\SPI_ADC|state [4]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state~0 .extended_lut = "off";
+defparam \SPI_ADC|state~0 .lut_mask = 64'h007F007F01FE01FE;
+defparam \SPI_ADC|state~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N47
+dffeas \SPI_ADC|state[4] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N18
+cyclonev_lcell_comb \SPI_ADC|Selector4~0 (
+// Equation(s):
+// \SPI_ADC|Selector4~0_combout  = ( \SPI_ADC|state[1]~DUPLICATE_q  & ( \SPI_ADC|state [0] ) ) # ( !\SPI_ADC|state[1]~DUPLICATE_q  & ( \SPI_ADC|state [0] ) ) # ( \SPI_ADC|state[1]~DUPLICATE_q  & ( !\SPI_ADC|state [0] ) ) # ( !\SPI_ADC|state[1]~DUPLICATE_q  & 
+// ( !\SPI_ADC|state [0] & ( (((!\SPI_ADC|state [4] & \SPI_ADC|adc_start~q )) # (\SPI_ADC|state[3]~DUPLICATE_q )) # (\SPI_ADC|state [2]) ) ) )
+
+	.dataa(!\SPI_ADC|state [2]),
+	.datab(!\SPI_ADC|state [4]),
+	.datac(!\SPI_ADC|state[3]~DUPLICATE_q ),
+	.datad(!\SPI_ADC|adc_start~q ),
+	.datae(!\SPI_ADC|state[1]~DUPLICATE_q ),
+	.dataf(!\SPI_ADC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector4~0 .lut_mask = 64'h5FDFFFFFFFFFFFFF;
+defparam \SPI_ADC|Selector4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N20
+dffeas \SPI_ADC|adc_cs (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N6
+cyclonev_lcell_comb \SPI_ADC|Selector2~0 (
+// Equation(s):
+// \SPI_ADC|Selector2~0_combout  = ( \SPI_ADC|adc_cs~q  & ( \SPI_ADC|sr_state.IDLE~q  ) )
+
+	.dataa(!\SPI_ADC|sr_state.IDLE~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector2~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector2~0 .lut_mask = 64'h0000000055555555;
+defparam \SPI_ADC|Selector2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N8
+dffeas \SPI_ADC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N51
+cyclonev_lcell_comb \SPI_ADC|Selector0~0 (
+// Equation(s):
+// \SPI_ADC|Selector0~0_combout  = ( \SPI_ADC|adc_cs~q  & ( (\SPI_ADC|sr_state.IDLE~q ) # (\tick|CLK_OUT~q ) ) ) # ( !\SPI_ADC|adc_cs~q  & ( (!\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & ((\SPI_ADC|sr_state.IDLE~q ) # (\tick|CLK_OUT~q ))) ) )
+
+	.dataa(!\tick|CLK_OUT~q ),
+	.datab(gnd),
+	.datac(!\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.datad(!\SPI_ADC|sr_state.IDLE~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector0~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector0~0 .lut_mask = 64'h50F050F055FF55FF;
+defparam \SPI_ADC|Selector0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N53
+dffeas \SPI_ADC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N24
+cyclonev_lcell_comb \SPI_ADC|Selector1~0 (
+// Equation(s):
+// \SPI_ADC|Selector1~0_combout  = ( \SPI_ADC|adc_cs~q  & ( (!\SPI_ADC|sr_state.IDLE~q  & \tick|CLK_OUT~q ) ) ) # ( !\SPI_ADC|adc_cs~q  & ( ((!\SPI_ADC|sr_state.IDLE~q  & \tick|CLK_OUT~q )) # (\SPI_ADC|sr_state.WAIT_CSB_FALL~q ) ) )
+
+	.dataa(!\SPI_ADC|sr_state.IDLE~q ),
+	.datab(gnd),
+	.datac(!\tick|CLK_OUT~q ),
+	.datad(!\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector1~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector1~0 .lut_mask = 64'h0AFF0AFF0A0A0A0A;
+defparam \SPI_ADC|Selector1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N25
+dffeas \SPI_ADC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N9
+cyclonev_lcell_comb \SPI_ADC|adc_start~0 (
+// Equation(s):
+// \SPI_ADC|adc_start~0_combout  = ( \SPI_ADC|adc_cs~q  & ( ((!\SPI_ADC|sr_state.IDLE~q  & \tick|CLK_OUT~q )) # (\SPI_ADC|adc_start~q ) ) ) # ( !\SPI_ADC|adc_cs~q  & ( (!\SPI_ADC|sr_state.IDLE~q  & (((\SPI_ADC|adc_start~q )) # (\tick|CLK_OUT~q ))) # 
+// (\SPI_ADC|sr_state.IDLE~q  & (((\SPI_ADC|sr_state.WAIT_CSB_FALL~q  & \SPI_ADC|adc_start~q )))) ) )
+
+	.dataa(!\SPI_ADC|sr_state.IDLE~q ),
+	.datab(!\tick|CLK_OUT~q ),
+	.datac(!\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(!\SPI_ADC|adc_start~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|adc_start~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~0 .extended_lut = "off";
+defparam \SPI_ADC|adc_start~0 .lut_mask = 64'h22AF22AF22FF22FF;
+defparam \SPI_ADC|adc_start~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N11
+dffeas \SPI_ADC|adc_start (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|adc_start~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_start .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N15
+cyclonev_lcell_comb \SPI_ADC|Selector5~0 (
+// Equation(s):
+// \SPI_ADC|Selector5~0_combout  = ( \SPI_ADC|state[1]~DUPLICATE_q  & ( \SPI_ADC|adc_start~q  & ( !\SPI_ADC|state [0] ) ) ) # ( !\SPI_ADC|state[1]~DUPLICATE_q  & ( \SPI_ADC|adc_start~q  & ( (!\SPI_ADC|state [0] & ((!\SPI_ADC|state [4]) # ((\SPI_ADC|state 
+// [3]) # (\SPI_ADC|state [2])))) ) ) ) # ( \SPI_ADC|state[1]~DUPLICATE_q  & ( !\SPI_ADC|adc_start~q  & ( !\SPI_ADC|state [0] ) ) ) # ( !\SPI_ADC|state[1]~DUPLICATE_q  & ( !\SPI_ADC|adc_start~q  & ( (!\SPI_ADC|state [0] & ((\SPI_ADC|state [3]) # 
+// (\SPI_ADC|state [2]))) ) ) )
+
+	.dataa(!\SPI_ADC|state [0]),
+	.datab(!\SPI_ADC|state [4]),
+	.datac(!\SPI_ADC|state [2]),
+	.datad(!\SPI_ADC|state [3]),
+	.datae(!\SPI_ADC|state[1]~DUPLICATE_q ),
+	.dataf(!\SPI_ADC|adc_start~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector5~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector5~0 .lut_mask = 64'h0AAAAAAA8AAAAAAA;
+defparam \SPI_ADC|Selector5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N14
+dffeas \SPI_ADC|state[0] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|Selector5~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N39
+cyclonev_lcell_comb \SPI_ADC|state[2]~2 (
+// Equation(s):
+// \SPI_ADC|state[2]~2_combout  = ( \SPI_ADC|state[1]~DUPLICATE_q  & ( !\SPI_ADC|state [2] $ (!\SPI_ADC|state [0]) ) ) # ( !\SPI_ADC|state[1]~DUPLICATE_q  & ( \SPI_ADC|state [2] ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|state [2]),
+	.datac(!\SPI_ADC|state [0]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state[1]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[2]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[2]~2 .extended_lut = "off";
+defparam \SPI_ADC|state[2]~2 .lut_mask = 64'h333333333C3C3C3C;
+defparam \SPI_ADC|state[2]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N22
+dffeas \SPI_ADC|state[2] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[2]~2_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N54
+cyclonev_lcell_comb \SPI_ADC|WideOr0~0 (
+// Equation(s):
+// \SPI_ADC|WideOr0~0_combout  = ( \SPI_ADC|state [4] & ( (((\SPI_ADC|state[3]~DUPLICATE_q ) # (\SPI_ADC|state [0])) # (\SPI_ADC|state[1]~DUPLICATE_q )) # (\SPI_ADC|state [2]) ) ) # ( !\SPI_ADC|state [4] & ( (!\SPI_ADC|state [2] & 
+// (((\SPI_ADC|state[3]~DUPLICATE_q )))) # (\SPI_ADC|state [2] & ((!\SPI_ADC|state[1]~DUPLICATE_q ) # ((!\SPI_ADC|state [0]) # (!\SPI_ADC|state[3]~DUPLICATE_q )))) ) )
+
+	.dataa(!\SPI_ADC|state [2]),
+	.datab(!\SPI_ADC|state[1]~DUPLICATE_q ),
+	.datac(!\SPI_ADC|state [0]),
+	.datad(!\SPI_ADC|state[3]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~0 .extended_lut = "off";
+defparam \SPI_ADC|WideOr0~0 .lut_mask = 64'h55FE55FE7FFF7FFF;
+defparam \SPI_ADC|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N56
+dffeas \SPI_ADC|shift_ena (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|WideOr0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_ena~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_ena .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_ena .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N42
+cyclonev_lcell_comb \SPI_ADC|always3~0 (
+// Equation(s):
+// \SPI_ADC|always3~0_combout  = ( \SPI_ADC|shift_ena~q  & ( \SPI_ADC|adc_cs~q  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SPI_ADC|shift_ena~q ),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|always3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|always3~0 .extended_lut = "off";
+defparam \SPI_ADC|always3~0 .lut_mask = 64'h000000000000FFFF;
+defparam \SPI_ADC|always3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N44
+dffeas \SPI_ADC|shift_reg[0] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\ADC_SDO~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N33
+cyclonev_lcell_comb \SPI_ADC|Decoder0~0 (
+// Equation(s):
+// \SPI_ADC|Decoder0~0_combout  = ( \SPI_ADC|state [0] & ( (\SPI_ADC|state [1] & (\SPI_ADC|state [2] & (!\SPI_ADC|state [4] & \SPI_ADC|state[3]~DUPLICATE_q ))) ) )
+
+	.dataa(!\SPI_ADC|state [1]),
+	.datab(!\SPI_ADC|state [2]),
+	.datac(!\SPI_ADC|state [4]),
+	.datad(!\SPI_ADC|state[3]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~0 .extended_lut = "off";
+defparam \SPI_ADC|Decoder0~0 .lut_mask = 64'h0000000000100010;
+defparam \SPI_ADC|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N34
+dffeas \SPI_ADC|adc_done (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Decoder0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_done~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_done .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_done .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N32
+dffeas \SPI_ADC|data_from_adc[0] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N30
+cyclonev_lcell_comb \fin_address|Add0~1 (
+// Equation(s):
+// \fin_address|Add0~1_sumout  = SUM(( \SPI_ADC|data_from_adc [0] ) + ( \fin_address|address [0] ) + ( !VCC ))
+// \fin_address|Add0~2  = CARRY(( \SPI_ADC|data_from_adc [0] ) + ( \fin_address|address [0] ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [0]),
+	.datad(!\SPI_ADC|data_from_adc [0]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~1_sumout ),
+	.cout(\fin_address|Add0~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~1 .extended_lut = "off";
+defparam \fin_address|Add0~1 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N24
+cyclonev_lcell_comb \fin_address|address[0]~feeder (
+// Equation(s):
+// \fin_address|address[0]~feeder_combout  = ( \fin_address|Add0~1_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[0]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[0]~feeder .extended_lut = "off";
+defparam \fin_address|address[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[0]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N26
+dffeas \fin_address|address[0] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[0] .is_wysiwyg = "true";
+defparam \fin_address|address[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N45
+cyclonev_lcell_comb \SPI_ADC|shift_reg[1]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[1]~feeder_combout  = \SPI_ADC|shift_reg [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|shift_reg [0]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[1]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \SPI_ADC|shift_reg[1]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N46
+dffeas \SPI_ADC|shift_reg[1] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N35
+dffeas \SPI_ADC|data_from_adc[1] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N33
+cyclonev_lcell_comb \fin_address|Add0~5 (
+// Equation(s):
+// \fin_address|Add0~5_sumout  = SUM(( \SPI_ADC|data_from_adc [1] ) + ( \fin_address|address [1] ) + ( \fin_address|Add0~2  ))
+// \fin_address|Add0~6  = CARRY(( \SPI_ADC|data_from_adc [1] ) + ( \fin_address|address [1] ) + ( \fin_address|Add0~2  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [1]),
+	.datad(!\SPI_ADC|data_from_adc [1]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~5_sumout ),
+	.cout(\fin_address|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~5 .extended_lut = "off";
+defparam \fin_address|Add0~5 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N9
+cyclonev_lcell_comb \fin_address|address[1]~feeder (
+// Equation(s):
+// \fin_address|address[1]~feeder_combout  = \fin_address|Add0~5_sumout 
+
+	.dataa(gnd),
+	.datab(!\fin_address|Add0~5_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[1]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[1]~feeder .extended_lut = "off";
+defparam \fin_address|address[1]~feeder .lut_mask = 64'h3333333333333333;
+defparam \fin_address|address[1]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N11
+dffeas \fin_address|address[1] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[1] .is_wysiwyg = "true";
+defparam \fin_address|address[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N47
+dffeas \SPI_ADC|shift_reg[1]~DUPLICATE (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg[1]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[1]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N8
+dffeas \SPI_ADC|shift_reg[2] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg[1]~DUPLICATE_q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N38
+dffeas \SPI_ADC|data_from_adc[2] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N36
+cyclonev_lcell_comb \fin_address|Add0~9 (
+// Equation(s):
+// \fin_address|Add0~9_sumout  = SUM(( \SPI_ADC|data_from_adc [2] ) + ( \fin_address|address [2] ) + ( \fin_address|Add0~6  ))
+// \fin_address|Add0~10  = CARRY(( \SPI_ADC|data_from_adc [2] ) + ( \fin_address|address [2] ) + ( \fin_address|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [2]),
+	.datad(!\SPI_ADC|data_from_adc [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~9_sumout ),
+	.cout(\fin_address|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~9 .extended_lut = "off";
+defparam \fin_address|Add0~9 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N21
+cyclonev_lcell_comb \fin_address|address[2]~feeder (
+// Equation(s):
+// \fin_address|address[2]~feeder_combout  = \fin_address|Add0~9_sumout 
+
+	.dataa(gnd),
+	.datab(!\fin_address|Add0~9_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[2]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[2]~feeder .extended_lut = "off";
+defparam \fin_address|address[2]~feeder .lut_mask = 64'h3333333333333333;
+defparam \fin_address|address[2]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N23
+dffeas \fin_address|address[2] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[2] .is_wysiwyg = "true";
+defparam \fin_address|address[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N9
+cyclonev_lcell_comb \SPI_ADC|shift_reg[3]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[3]~feeder_combout  = \SPI_ADC|shift_reg [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|shift_reg [2]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[3]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \SPI_ADC|shift_reg[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N10
+dffeas \SPI_ADC|shift_reg[3] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N41
+dffeas \SPI_ADC|data_from_adc[3] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N39
+cyclonev_lcell_comb \fin_address|Add0~13 (
+// Equation(s):
+// \fin_address|Add0~13_sumout  = SUM(( \SPI_ADC|data_from_adc [3] ) + ( \fin_address|address [3] ) + ( \fin_address|Add0~10  ))
+// \fin_address|Add0~14  = CARRY(( \SPI_ADC|data_from_adc [3] ) + ( \fin_address|address [3] ) + ( \fin_address|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [3]),
+	.datad(!\SPI_ADC|data_from_adc [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~13_sumout ),
+	.cout(\fin_address|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~13 .extended_lut = "off";
+defparam \fin_address|Add0~13 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N12
+cyclonev_lcell_comb \fin_address|address[3]~feeder (
+// Equation(s):
+// \fin_address|address[3]~feeder_combout  = ( \fin_address|Add0~13_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[3]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[3]~feeder .extended_lut = "off";
+defparam \fin_address|address[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N14
+dffeas \fin_address|address[3] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[3] .is_wysiwyg = "true";
+defparam \fin_address|address[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N14
+dffeas \SPI_ADC|shift_reg[4] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N44
+dffeas \SPI_ADC|data_from_adc[4] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N42
+cyclonev_lcell_comb \fin_address|Add0~17 (
+// Equation(s):
+// \fin_address|Add0~17_sumout  = SUM(( \SPI_ADC|data_from_adc [4] ) + ( \fin_address|address [4] ) + ( \fin_address|Add0~14  ))
+// \fin_address|Add0~18  = CARRY(( \SPI_ADC|data_from_adc [4] ) + ( \fin_address|address [4] ) + ( \fin_address|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [4]),
+	.datad(!\SPI_ADC|data_from_adc [4]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~17_sumout ),
+	.cout(\fin_address|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~17 .extended_lut = "off";
+defparam \fin_address|Add0~17 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N3
+cyclonev_lcell_comb \fin_address|address[4]~feeder (
+// Equation(s):
+// \fin_address|address[4]~feeder_combout  = \fin_address|Add0~17_sumout 
+
+	.dataa(gnd),
+	.datab(!\fin_address|Add0~17_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[4]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[4]~feeder .extended_lut = "off";
+defparam \fin_address|address[4]~feeder .lut_mask = 64'h3333333333333333;
+defparam \fin_address|address[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N5
+dffeas \fin_address|address[4] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[4] .is_wysiwyg = "true";
+defparam \fin_address|address[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N15
+cyclonev_lcell_comb \SPI_ADC|shift_reg[5]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[5]~feeder_combout  = \SPI_ADC|shift_reg [4]
+
+	.dataa(!\SPI_ADC|shift_reg [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[5]~feeder .lut_mask = 64'h5555555555555555;
+defparam \SPI_ADC|shift_reg[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N16
+dffeas \SPI_ADC|shift_reg[5] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N47
+dffeas \SPI_ADC|data_from_adc[5] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N45
+cyclonev_lcell_comb \fin_address|Add0~21 (
+// Equation(s):
+// \fin_address|Add0~21_sumout  = SUM(( \SPI_ADC|data_from_adc [5] ) + ( \fin_address|address [5] ) + ( \fin_address|Add0~18  ))
+// \fin_address|Add0~22  = CARRY(( \SPI_ADC|data_from_adc [5] ) + ( \fin_address|address [5] ) + ( \fin_address|Add0~18  ))
+
+	.dataa(!\fin_address|address [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [5]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~21_sumout ),
+	.cout(\fin_address|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~21 .extended_lut = "off";
+defparam \fin_address|Add0~21 .lut_mask = 64'h0000AAAA000000FF;
+defparam \fin_address|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N18
+cyclonev_lcell_comb \fin_address|address[5]~feeder (
+// Equation(s):
+// \fin_address|address[5]~feeder_combout  = ( \fin_address|Add0~21_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~21_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[5]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[5]~feeder .extended_lut = "off";
+defparam \fin_address|address[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N20
+dffeas \fin_address|address[5] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[5] .is_wysiwyg = "true";
+defparam \fin_address|address[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N0
+cyclonev_lcell_comb \SPI_ADC|shift_reg[6]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[6]~feeder_combout  = \SPI_ADC|shift_reg [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|shift_reg [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[6]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \SPI_ADC|shift_reg[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N2
+dffeas \SPI_ADC|shift_reg[6] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N50
+dffeas \SPI_ADC|data_from_adc[6] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N48
+cyclonev_lcell_comb \fin_address|Add0~25 (
+// Equation(s):
+// \fin_address|Add0~25_sumout  = SUM(( \SPI_ADC|data_from_adc [6] ) + ( \fin_address|address [6] ) + ( \fin_address|Add0~22  ))
+// \fin_address|Add0~26  = CARRY(( \SPI_ADC|data_from_adc [6] ) + ( \fin_address|address [6] ) + ( \fin_address|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [6]),
+	.datad(!\SPI_ADC|data_from_adc [6]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~25_sumout ),
+	.cout(\fin_address|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~25 .extended_lut = "off";
+defparam \fin_address|Add0~25 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N27
+cyclonev_lcell_comb \fin_address|address[6]~feeder (
+// Equation(s):
+// \fin_address|address[6]~feeder_combout  = ( \fin_address|Add0~25_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[6]~feeder .extended_lut = "off";
+defparam \fin_address|address[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N29
+dffeas \fin_address|address[6] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[6] .is_wysiwyg = "true";
+defparam \fin_address|address[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N3
+cyclonev_lcell_comb \SPI_ADC|shift_reg[7]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[7]~feeder_combout  = ( \SPI_ADC|shift_reg [6] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[7]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[7]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N4
+dffeas \SPI_ADC|shift_reg[7] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N53
+dffeas \SPI_ADC|data_from_adc[7] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N51
+cyclonev_lcell_comb \fin_address|Add0~29 (
+// Equation(s):
+// \fin_address|Add0~29_sumout  = SUM(( \SPI_ADC|data_from_adc [7] ) + ( \fin_address|address [7] ) + ( \fin_address|Add0~26  ))
+// \fin_address|Add0~30  = CARRY(( \SPI_ADC|data_from_adc [7] ) + ( \fin_address|address [7] ) + ( \fin_address|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\fin_address|address [7]),
+	.datad(!\SPI_ADC|data_from_adc [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~29_sumout ),
+	.cout(\fin_address|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~29 .extended_lut = "off";
+defparam \fin_address|Add0~29 .lut_mask = 64'h0000F0F0000000FF;
+defparam \fin_address|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N15
+cyclonev_lcell_comb \fin_address|address[7]~feeder (
+// Equation(s):
+// \fin_address|address[7]~feeder_combout  = ( \fin_address|Add0~29_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~29_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[7]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[7]~feeder .extended_lut = "off";
+defparam \fin_address|address[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N17
+dffeas \fin_address|address[7] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[7] .is_wysiwyg = "true";
+defparam \fin_address|address[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N50
+dffeas \SPI_ADC|shift_reg[8] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N56
+dffeas \SPI_ADC|data_from_adc[8] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N54
+cyclonev_lcell_comb \fin_address|Add0~33 (
+// Equation(s):
+// \fin_address|Add0~33_sumout  = SUM(( \SPI_ADC|data_from_adc [8] ) + ( \fin_address|address [8] ) + ( \fin_address|Add0~30  ))
+// \fin_address|Add0~34  = CARRY(( \SPI_ADC|data_from_adc [8] ) + ( \fin_address|address [8] ) + ( \fin_address|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(!\fin_address|address [8]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [8]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~33_sumout ),
+	.cout(\fin_address|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~33 .extended_lut = "off";
+defparam \fin_address|Add0~33 .lut_mask = 64'h0000CCCC000000FF;
+defparam \fin_address|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N6
+cyclonev_lcell_comb \fin_address|address[8]~feeder (
+// Equation(s):
+// \fin_address|address[8]~feeder_combout  = ( \fin_address|Add0~33_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[8]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[8]~feeder .extended_lut = "off";
+defparam \fin_address|address[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[8]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N8
+dffeas \fin_address|address[8] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[8] .is_wysiwyg = "true";
+defparam \fin_address|address[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N49
+dffeas \SPI_ADC|shift_reg[8]~DUPLICATE (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg[8]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[8]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[8]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X74_Y6_N53
+dffeas \SPI_ADC|shift_reg[9] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg[8]~DUPLICATE_q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N59
+dffeas \SPI_ADC|data_from_adc[9] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N57
+cyclonev_lcell_comb \fin_address|Add0~37 (
+// Equation(s):
+// \fin_address|Add0~37_sumout  = SUM(( \SPI_ADC|data_from_adc [9] ) + ( \fin_address|address [9] ) + ( \fin_address|Add0~34  ))
+
+	.dataa(!\fin_address|address [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [9]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\fin_address|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\fin_address|Add0~37_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|Add0~37 .extended_lut = "off";
+defparam \fin_address|Add0~37 .lut_mask = 64'h0000AAAA000000FF;
+defparam \fin_address|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y6_N0
+cyclonev_lcell_comb \fin_address|address[9]~feeder (
+// Equation(s):
+// \fin_address|address[9]~feeder_combout  = ( \fin_address|Add0~37_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\fin_address|Add0~37_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\fin_address|address[9]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \fin_address|address[9]~feeder .extended_lut = "off";
+defparam \fin_address|address[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \fin_address|address[9]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y6_N2
+dffeas \fin_address|address[9] (
+	.clk(\tick|CLK_OUT~q ),
+	.d(\fin_address|address[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\fin_address|address [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \fin_address|address[9] .is_wysiwyg = "true";
+defparam \fin_address|address[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: M10K_X76_Y6_N0
+cyclonev_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 (
+	.portawe(vcc),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(vcc),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain(10'b0000000000),
+	.portaaddr({\fin_address|address [9],\fin_address|address [8],\fin_address|address [7],\fin_address|address [6],\fin_address|address [5],\fin_address|address [4],\fin_address|address [3],\fin_address|address [2],\fin_address|address [1],\fin_address|address [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(10'b0000000000),
+	.portbaddr(10'b0000000000),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
+	.portbdataout(),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom_data/rom_data.mif";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated|ALTSYNCRAM";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 1023;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 1024;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 10;
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M20K";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init4 = "7F1F97D9F37C1ED7A9E678DE0775DA75DD4741CD729C7711C16F9BB6E1B46C5AE6ADA8695A267D9C665966498F63189619836017D5E9775D1715B96B5A1655895F57159559535414D52947511424FD3C4E5364CD304B52A4A1254891F4711A45D144450E4310941903404FE3ECF93D8F33C4EE3ACE9398E3384DE370D9358D4344CF330CA31CC5308C02F4BB2E4B62D0B12BCAD2A8A8298A32849F2749A260962509123C8D22C8921C85208801F87C1E8781D8741C8701B86C1A86819C6518C6117C5D1705A16056150531444F1384C1284911C46110421043F0F83C0EC390E0370D4340C8310C02E0B42C0AC290A0270982508C220842007C1E0741C06C1A06";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = "41805C160541404C13048110400F03C0E0340C0300B0280A024090200801C0601806014050100400C0300C020080200801004010040100000000000000000000000000000000000000010040100401008020080200C0300C0401005014060180601C08020090240A0280B0300C0340E03C0F040110481304C140541605C180641A06C1C0741E07C200842208C25098270A0290AC2C0B42E0C0310C8340D4370E0390EC3C0F83F104421104611C491284C1384F14453150561605A1705D17C6118C6519C681A86C1B8701C8741D8781E87C1F8802088521C8922C8D23C91250962609A2749F284A3298A82A8AD2BCB12D0B62E4BB2F4C0308C531CCA330CF344D";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = "4358D9370DE384E3398E93ACEE3C4F33D8F93ECFE40503419094310E4451445D1A4711F489254A12A4B5304CD364E53C4FD42511475294D54153559595715F589655A16B5B9715D1775E97D60183619896318F649966659C67DA2695A86ADAE6C5B46E1BB6F9C1711C7729CD741D475DDA775E078DE67A9ED7C1F37D9F97F20080E068260C83E12856198721F88A258A22B8BE328D6388EE3E9064491E4B93A519525796A5D9826399A699B6709CE769E67C9FE82A1688A2E8EA4694A5E9AA76A0A8EA6AA6ACABEB2AD6B8AEEBDB02C3B1AC9B32CFB4AD5B5EDAB76E0B8EE5BA2EBBBAF1BCEF6BE6FCBFB01C1306C270CC3B11C5316C671CC7B21C8F26CA72BC";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = "BB30CCF35CE33ACF73FD0B44D1B49D2F4ED4352D5757D675CD7B60D8B65D9F69DAF6EDC372DD376DE37ADF77FE0783E1787E278BE378FE4793E5797E639AE739EE83A2E8FA5E9FA9EAFACEBBB0EC7B3ED7B6EE3B9EEFBDEFBC0F07C3F13C6F1FC8F2BCBF37CEF3FD1F4BD3F53D6F5FD8F67DAF73DDF7BDFF83E1F8BE3F93E5F9BE7FA3E9FABEBFB3ECFB7EEFBFF0FC3F1FCBF3FCFF4FD7F5FDBF6FDFF7FE3F9FE7F9FEBFAFEFFBFF3FCFF3FDFF7FDFF7FEFFBFEFFBFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFBFEFFBFEFF7FDFF7FDFF3FCFF3FBFEFFAFEBF9FE7F9FE3F7FDFF6FDBF5FD7F4FCFF3FCBF1FC3F0FBFEEFB7ECFB3EBFABE9FA3E7F9B";
+defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = "E5F93E3F8BE1F83DFF7BDDF73DAF67D8F5FD6F53D3F4BD1F3FCEF37CBF2BC8F1FC6F13C3F07C0EFBBDEEFB9EE3B6ED7B3EC7B0EBBACEAFA9E9FA5E8FA2E839EE739AE6397E5793E478FE378BE2787E1783E077FDF77ADE376DD372DC36EDAF69D9F65D8B60D7B5CD6757D5752D434ED2F49D1B44D0B3FCF73ACE335CCF30CBB2BCA726C8F21C7B1CC6716C5311C3B0CC2706C1301BFAFCBE6F6BCEF1BBAEBBA2E5B8EE0B76DAB5ED5B4ACFB32C9B1AC3B02BDAEEB8AD6B2ABEACAA6A6A8EA0A769AA5E94A468EA2E88A16829FE7C9E6769CE709B66999A639825D96A579525193A4B91E449063E8EE388D6328BE2B8A22588A1F872198561283E0C8260680E00";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N54
+cyclonev_lcell_comb \dac|shift_reg[11]~feeder (
+// Equation(s):
+// \dac|shift_reg[11]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [9] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [9]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[11]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[11]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[11]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[11]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N15
+cyclonev_lcell_comb \dac|shift_reg[10]~feeder (
+// Equation(s):
+// \dac|shift_reg[10]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [8] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[10]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[10]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[10]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[10]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N24
+cyclonev_lcell_comb \dac|shift_reg[9]~feeder (
+// Equation(s):
+// \dac|shift_reg[9]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [7] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[9]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[9]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[9]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N0
+cyclonev_lcell_comb \dac|shift_reg[8]~feeder (
+// Equation(s):
+// \dac|shift_reg[8]~feeder_combout  = \rom|altsyncram_component|auto_generated|q_a [6]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\rom|altsyncram_component|auto_generated|q_a [6]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[8]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[8]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[8]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \dac|shift_reg[8]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N15
+cyclonev_lcell_comb \dac|shift_reg[7]~feeder (
+// Equation(s):
+// \dac|shift_reg[7]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [5] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [5]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[7]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[7]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N12
+cyclonev_lcell_comb \dac|shift_reg[6]~feeder (
+// Equation(s):
+// \dac|shift_reg[6]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [4] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[6]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \dac|shift_reg[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N18
+cyclonev_lcell_comb \dac|shift_reg[5]~feeder (
+// Equation(s):
+// \dac|shift_reg[5]~feeder_combout  = \rom|altsyncram_component|auto_generated|q_a [3]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\rom|altsyncram_component|auto_generated|q_a [3]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[5]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[5]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[5]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \dac|shift_reg[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N18
+cyclonev_lcell_comb \dac|shift_reg[4]~feeder (
+// Equation(s):
+// \dac|shift_reg[4]~feeder_combout  = \rom|altsyncram_component|auto_generated|q_a [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\rom|altsyncram_component|auto_generated|q_a [2]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[4]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[4]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[4]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \dac|shift_reg[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N39
+cyclonev_lcell_comb \dac|shift_reg[3]~feeder (
+// Equation(s):
+// \dac|shift_reg[3]~feeder_combout  = \rom|altsyncram_component|auto_generated|q_a [1]
+
+	.dataa(!\rom|altsyncram_component|auto_generated|q_a [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg[3]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg[3]~feeder .extended_lut = "off";
+defparam \dac|shift_reg[3]~feeder .lut_mask = 64'h5555555555555555;
+defparam \dac|shift_reg[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N48
+cyclonev_lcell_comb \dac|shift_reg~4 (
+// Equation(s):
+// \dac|shift_reg~4_combout  = ( \dac|WideNor0~combout  & ( (\rom|altsyncram_component|auto_generated|q_a [0] & \dac|sr_state.WAIT_CSB_FALL~q ) ) )
+
+	.dataa(gnd),
+	.datab(!\rom|altsyncram_component|auto_generated|q_a [0]),
+	.datac(gnd),
+	.datad(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datae(!\dac|WideNor0~combout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~4 .extended_lut = "off";
+defparam \dac|shift_reg~4 .lut_mask = 64'h0000003300000033;
+defparam \dac|shift_reg~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N49
+dffeas \dac|shift_reg[2] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[2] .is_wysiwyg = "true";
+defparam \dac|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N38
+dffeas \dac|state[4] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|state[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|state[4] .is_wysiwyg = "true";
+defparam \dac|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X72_Y6_N45
+cyclonev_lcell_comb \dac|always5~0 (
+// Equation(s):
+// \dac|always5~0_combout  = ( \dac|state [0] & ( \dac|sr_state.WAIT_CSB_FALL~q  & ( (((!\dac|state [4]) # (\dac|state [2])) # (\dac|state [3])) # (\dac|state [1]) ) ) ) # ( !\dac|state [0] & ( \dac|sr_state.WAIT_CSB_FALL~q  & ( (((\dac|state [4]) # 
+// (\dac|state [2])) # (\dac|state [3])) # (\dac|state [1]) ) ) ) # ( \dac|state [0] & ( !\dac|sr_state.WAIT_CSB_FALL~q  ) ) # ( !\dac|state [0] & ( !\dac|sr_state.WAIT_CSB_FALL~q  ) )
+
+	.dataa(!\dac|state [1]),
+	.datab(!\dac|state [3]),
+	.datac(!\dac|state [2]),
+	.datad(!\dac|state [4]),
+	.datae(!\dac|state [0]),
+	.dataf(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|always5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|always5~0 .extended_lut = "off";
+defparam \dac|always5~0 .lut_mask = 64'hFFFFFFFF7FFFFF7F;
+defparam \dac|always5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N40
+dffeas \dac|shift_reg[3] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[3]~feeder_combout ),
+	.asdata(\dac|shift_reg [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[3] .is_wysiwyg = "true";
+defparam \dac|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N19
+dffeas \dac|shift_reg[4] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[4]~feeder_combout ),
+	.asdata(\dac|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[4] .is_wysiwyg = "true";
+defparam \dac|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N19
+dffeas \dac|shift_reg[5] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[5]~feeder_combout ),
+	.asdata(\dac|shift_reg [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[5] .is_wysiwyg = "true";
+defparam \dac|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N13
+dffeas \dac|shift_reg[6] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[6]~feeder_combout ),
+	.asdata(\dac|shift_reg [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[6] .is_wysiwyg = "true";
+defparam \dac|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N17
+dffeas \dac|shift_reg[7] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[7]~feeder_combout ),
+	.asdata(\dac|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[7] .is_wysiwyg = "true";
+defparam \dac|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N1
+dffeas \dac|shift_reg[8] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[8]~feeder_combout ),
+	.asdata(\dac|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[8] .is_wysiwyg = "true";
+defparam \dac|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N25
+dffeas \dac|shift_reg[9] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[9]~feeder_combout ),
+	.asdata(\dac|shift_reg [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[9] .is_wysiwyg = "true";
+defparam \dac|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N16
+dffeas \dac|shift_reg[10] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[10]~feeder_combout ),
+	.asdata(\dac|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[10] .is_wysiwyg = "true";
+defparam \dac|shift_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X72_Y6_N56
+dffeas \dac|shift_reg[11] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg[11]~feeder_combout ),
+	.asdata(\dac|shift_reg [10]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\dac|always5~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[11] .is_wysiwyg = "true";
+defparam \dac|shift_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N3
+cyclonev_lcell_comb \dac|shift_reg~3 (
+// Equation(s):
+// \dac|shift_reg~3_combout  = ( \dac|shift_reg [11] ) # ( !\dac|shift_reg [11] & ( (\dac|sr_state.WAIT_CSB_FALL~q  & \dac|WideNor0~combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datac(gnd),
+	.datad(!\dac|WideNor0~combout ),
+	.datae(gnd),
+	.dataf(!\dac|shift_reg [11]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~3 .extended_lut = "off";
+defparam \dac|shift_reg~3 .lut_mask = 64'h00330033FFFFFFFF;
+defparam \dac|shift_reg~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N4
+dffeas \dac|shift_reg[12] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[12] .is_wysiwyg = "true";
+defparam \dac|shift_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N36
+cyclonev_lcell_comb \dac|shift_reg~2 (
+// Equation(s):
+// \dac|shift_reg~2_combout  = ( \dac|shift_reg [12] ) # ( !\dac|shift_reg [12] & ( (\dac|sr_state.WAIT_CSB_FALL~q  & \dac|WideNor0~combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datac(gnd),
+	.datad(!\dac|WideNor0~combout ),
+	.datae(gnd),
+	.dataf(!\dac|shift_reg [12]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~2 .extended_lut = "off";
+defparam \dac|shift_reg~2 .lut_mask = 64'h00330033FFFFFFFF;
+defparam \dac|shift_reg~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N37
+dffeas \dac|shift_reg[13] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[13] .is_wysiwyg = "true";
+defparam \dac|shift_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N39
+cyclonev_lcell_comb \dac|shift_reg~1 (
+// Equation(s):
+// \dac|shift_reg~1_combout  = ( \dac|shift_reg [13] ) # ( !\dac|shift_reg [13] & ( (\dac|sr_state.WAIT_CSB_FALL~q  & \dac|WideNor0~combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datac(gnd),
+	.datad(!\dac|WideNor0~combout ),
+	.datae(gnd),
+	.dataf(!\dac|shift_reg [13]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~1 .extended_lut = "off";
+defparam \dac|shift_reg~1 .lut_mask = 64'h00330033FFFFFFFF;
+defparam \dac|shift_reg~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N40
+dffeas \dac|shift_reg[14] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[14] .is_wysiwyg = "true";
+defparam \dac|shift_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N0
+cyclonev_lcell_comb \dac|shift_reg~0 (
+// Equation(s):
+// \dac|shift_reg~0_combout  = ( \dac|shift_reg [14] & ( (!\dac|sr_state.WAIT_CSB_FALL~q ) # (!\dac|WideNor0~combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\dac|sr_state.WAIT_CSB_FALL~q ),
+	.datac(gnd),
+	.datad(!\dac|WideNor0~combout ),
+	.datae(gnd),
+	.dataf(!\dac|shift_reg [14]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|shift_reg~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|shift_reg~0 .extended_lut = "off";
+defparam \dac|shift_reg~0 .lut_mask = 64'h00000000FFCCFFCC;
+defparam \dac|shift_reg~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X73_Y6_N1
+dffeas \dac|shift_reg[15] (
+	.clk(\dac|clk_1MHz~q ),
+	.d(\dac|shift_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\dac|shift_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \dac|shift_reg[15] .is_wysiwyg = "true";
+defparam \dac|shift_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N21
+cyclonev_lcell_comb \dac|Equal2~0 (
+// Equation(s):
+// \dac|Equal2~0_combout  = ( \dac|state[4]~DUPLICATE_q  & ( (\dac|state [0] & (!\dac|state [3] & (!\dac|state [1] & !\dac|state[2]~DUPLICATE_q ))) ) )
+
+	.dataa(!\dac|state [0]),
+	.datab(!\dac|state [3]),
+	.datac(!\dac|state [1]),
+	.datad(!\dac|state[2]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(!\dac|state[4]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|Equal2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|Equal2~0 .extended_lut = "off";
+defparam \dac|Equal2~0 .lut_mask = 64'h0000000040004000;
+defparam \dac|Equal2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X73_Y6_N6
+cyclonev_lcell_comb \dac|dac_sck (
+// Equation(s):
+// \dac|dac_sck~combout  = ( \dac|state [3] & ( \dac|clk_1MHz~q  ) ) # ( !\dac|state [3] & ( \dac|clk_1MHz~q  ) ) # ( !\dac|state [3] & ( !\dac|clk_1MHz~q  & ( (!\dac|state[2]~DUPLICATE_q  & (!\dac|state [1] & (!\dac|state [0] $ (\dac|state[4]~DUPLICATE_q 
+// )))) ) ) )
+
+	.dataa(!\dac|state [0]),
+	.datab(!\dac|state[4]~DUPLICATE_q ),
+	.datac(!\dac|state[2]~DUPLICATE_q ),
+	.datad(!\dac|state [1]),
+	.datae(!\dac|state [3]),
+	.dataf(!\dac|clk_1MHz~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\dac|dac_sck~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \dac|dac_sck .extended_lut = "off";
+defparam \dac|dac_sck .lut_mask = 64'h90000000FFFFFFFF;
+defparam \dac|dac_sck .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N23
+dffeas \SPI_ADC|state[2]~DUPLICATE (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[2]~2_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|state[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N0
+cyclonev_lcell_comb \SPI_ADC|Selector6~0 (
+// Equation(s):
+// \SPI_ADC|Selector6~0_combout  = ( !\SPI_ADC|state [4] & ( \SPI_ADC|state [0] & ( (!\SPI_ADC|state[2]~DUPLICATE_q  & !\SPI_ADC|state[3]~DUPLICATE_q ) ) ) ) # ( !\SPI_ADC|state [4] & ( !\SPI_ADC|state [0] & ( (!\SPI_ADC|state[2]~DUPLICATE_q  & 
+// (!\SPI_ADC|state[1]~DUPLICATE_q  & (!\SPI_ADC|state[3]~DUPLICATE_q  & \SPI_ADC|adc_start~q ))) ) ) )
+
+	.dataa(!\SPI_ADC|state[2]~DUPLICATE_q ),
+	.datab(!\SPI_ADC|state[1]~DUPLICATE_q ),
+	.datac(!\SPI_ADC|state[3]~DUPLICATE_q ),
+	.datad(!\SPI_ADC|adc_start~q ),
+	.datae(!\SPI_ADC|state [4]),
+	.dataf(!\SPI_ADC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector6~0 .lut_mask = 64'h00800000A0A00000;
+defparam \SPI_ADC|Selector6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y6_N1
+dffeas \SPI_ADC|adc_din (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Selector6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_din~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_din .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_din .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y6_N57
+cyclonev_lcell_comb \SPI_ADC|adc_sck (
+// Equation(s):
+// \SPI_ADC|adc_sck~combout  = ( \SPI_ADC|adc_cs~q  & ( \SPI_ADC|clk_1MHz~q  ) ) # ( !\SPI_ADC|adc_cs~q  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|clk_1MHz~q ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|adc_sck~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_sck .extended_lut = "off";
+defparam \SPI_ADC|adc_sck .lut_mask = 64'hFFFFFFFF0F0F0F0F;
+defparam \SPI_ADC|adc_sck .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N32
+dffeas \p|count[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|count[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[0] .is_wysiwyg = "true";
+defparam \p|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N30
+cyclonev_lcell_comb \p|count[0]~0 (
+// Equation(s):
+// \p|count[0]~0_combout  = !\p|count [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [0]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|count[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|count[0]~0 .extended_lut = "off";
+defparam \p|count[0]~0 .lut_mask = 64'hFF00FF00FF00FF00;
+defparam \p|count[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N31
+dffeas \p|count[0]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|count[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count[0]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[0]~DUPLICATE .is_wysiwyg = "true";
+defparam \p|count[0]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N0
+cyclonev_lcell_comb \p|Add0~33 (
+// Equation(s):
+// \p|Add0~33_sumout  = SUM(( \p|count [1] ) + ( \p|count[0]~DUPLICATE_q  ) + ( !VCC ))
+// \p|Add0~34  = CARRY(( \p|count [1] ) + ( \p|count[0]~DUPLICATE_q  ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\p|count[0]~DUPLICATE_q ),
+	.datad(!\p|count [1]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~33_sumout ),
+	.cout(\p|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~33 .extended_lut = "off";
+defparam \p|Add0~33 .lut_mask = 64'h0000F0F0000000FF;
+defparam \p|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N2
+dffeas \p|count[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[1] .is_wysiwyg = "true";
+defparam \p|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N3
+cyclonev_lcell_comb \p|Add0~29 (
+// Equation(s):
+// \p|Add0~29_sumout  = SUM(( \p|count [2] ) + ( GND ) + ( \p|Add0~34  ))
+// \p|Add0~30  = CARRY(( \p|count [2] ) + ( GND ) + ( \p|Add0~34  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~29_sumout ),
+	.cout(\p|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~29 .extended_lut = "off";
+defparam \p|Add0~29 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N5
+dffeas \p|count[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~29_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[2] .is_wysiwyg = "true";
+defparam \p|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N6
+cyclonev_lcell_comb \p|Add0~25 (
+// Equation(s):
+// \p|Add0~25_sumout  = SUM(( \p|count [3] ) + ( GND ) + ( \p|Add0~30  ))
+// \p|Add0~26  = CARRY(( \p|count [3] ) + ( GND ) + ( \p|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~25_sumout ),
+	.cout(\p|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~25 .extended_lut = "off";
+defparam \p|Add0~25 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N7
+dffeas \p|count[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[3] .is_wysiwyg = "true";
+defparam \p|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N9
+cyclonev_lcell_comb \p|Add0~21 (
+// Equation(s):
+// \p|Add0~21_sumout  = SUM(( \p|count [4] ) + ( GND ) + ( \p|Add0~26  ))
+// \p|Add0~22  = CARRY(( \p|count [4] ) + ( GND ) + ( \p|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [4]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~21_sumout ),
+	.cout(\p|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~21 .extended_lut = "off";
+defparam \p|Add0~21 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N11
+dffeas \p|count[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[4] .is_wysiwyg = "true";
+defparam \p|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N12
+cyclonev_lcell_comb \p|Add0~17 (
+// Equation(s):
+// \p|Add0~17_sumout  = SUM(( \p|count [5] ) + ( GND ) + ( \p|Add0~22  ))
+// \p|Add0~18  = CARRY(( \p|count [5] ) + ( GND ) + ( \p|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [5]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~17_sumout ),
+	.cout(\p|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~17 .extended_lut = "off";
+defparam \p|Add0~17 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N14
+dffeas \p|count[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[5] .is_wysiwyg = "true";
+defparam \p|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N15
+cyclonev_lcell_comb \p|Add0~13 (
+// Equation(s):
+// \p|Add0~13_sumout  = SUM(( \p|count [6] ) + ( GND ) + ( \p|Add0~18  ))
+// \p|Add0~14  = CARRY(( \p|count [6] ) + ( GND ) + ( \p|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [6]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~13_sumout ),
+	.cout(\p|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~13 .extended_lut = "off";
+defparam \p|Add0~13 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N17
+dffeas \p|count[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[6] .is_wysiwyg = "true";
+defparam \p|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N18
+cyclonev_lcell_comb \p|Add0~9 (
+// Equation(s):
+// \p|Add0~9_sumout  = SUM(( \p|count [7] ) + ( GND ) + ( \p|Add0~14  ))
+// \p|Add0~10  = CARRY(( \p|count [7] ) + ( GND ) + ( \p|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~9_sumout ),
+	.cout(\p|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~9 .extended_lut = "off";
+defparam \p|Add0~9 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N19
+dffeas \p|count[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[7] .is_wysiwyg = "true";
+defparam \p|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N21
+cyclonev_lcell_comb \p|Add0~5 (
+// Equation(s):
+// \p|Add0~5_sumout  = SUM(( \p|count [8] ) + ( GND ) + ( \p|Add0~10  ))
+// \p|Add0~6  = CARRY(( \p|count [8] ) + ( GND ) + ( \p|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [8]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~5_sumout ),
+	.cout(\p|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~5 .extended_lut = "off";
+defparam \p|Add0~5 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N23
+dffeas \p|count[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[8] .is_wysiwyg = "true";
+defparam \p|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X78_Y7_N58
+dffeas \p|d[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[8] .is_wysiwyg = "true";
+defparam \p|d[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N40
+dffeas \p|d[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[6] .is_wysiwyg = "true";
+defparam \p|d[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y7_N51
+cyclonev_lcell_comb \p|d[7]~feeder (
+// Equation(s):
+// \p|d[7]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [7] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|d[7]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|d[7]~feeder .extended_lut = "off";
+defparam \p|d[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \p|d[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y7_N53
+dffeas \p|d[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|d[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[7] .is_wysiwyg = "true";
+defparam \p|d[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y7_N54
+cyclonev_lcell_comb \p|LessThan0~1 (
+// Equation(s):
+// \p|LessThan0~1_combout  = ( \p|count [7] & ( !\p|d [7] ) ) # ( !\p|count [7] & ( \p|d [7] ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\p|d [7]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\p|count [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~1 .extended_lut = "off";
+defparam \p|LessThan0~1 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \p|LessThan0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N43
+dffeas \p|d[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[3] .is_wysiwyg = "true";
+defparam \p|d[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N38
+dffeas \p|d[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[4] .is_wysiwyg = "true";
+defparam \p|d[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N58
+dffeas \p|d[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[2] .is_wysiwyg = "true";
+defparam \p|d[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N39
+cyclonev_lcell_comb \p|d[0]~feeder (
+// Equation(s):
+// \p|d[0]~feeder_combout  = ( \rom|altsyncram_component|auto_generated|q_a [0] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\rom|altsyncram_component|auto_generated|q_a [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|d[0]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|d[0]~feeder .extended_lut = "off";
+defparam \p|d[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \p|d[0]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N41
+dffeas \p|d[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|d[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[0] .is_wysiwyg = "true";
+defparam \p|d[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N47
+dffeas \p|d[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[1] .is_wysiwyg = "true";
+defparam \p|d[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N42
+cyclonev_lcell_comb \p|LessThan0~2 (
+// Equation(s):
+// \p|LessThan0~2_combout  = ( \p|count [2] & ( \p|count [0] & ( (!\p|d [2]) # ((!\p|d [0] & ((!\p|d [1]) # (\p|count [1]))) # (\p|d [0] & (\p|count [1] & !\p|d [1]))) ) ) ) # ( !\p|count [2] & ( \p|count [0] & ( (!\p|d [2] & ((!\p|d [0] & ((!\p|d [1]) # 
+// (\p|count [1]))) # (\p|d [0] & (\p|count [1] & !\p|d [1])))) ) ) ) # ( \p|count [2] & ( !\p|count [0] & ( (!\p|d [2]) # ((\p|count [1] & !\p|d [1])) ) ) ) # ( !\p|count [2] & ( !\p|count [0] & ( (!\p|d [2] & (\p|count [1] & !\p|d [1])) ) ) )
+
+	.dataa(!\p|d [2]),
+	.datab(!\p|d [0]),
+	.datac(!\p|count [1]),
+	.datad(!\p|d [1]),
+	.datae(!\p|count [2]),
+	.dataf(!\p|count [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~2 .extended_lut = "off";
+defparam \p|LessThan0~2 .lut_mask = 64'h0A00AFAA8A08EFAE;
+defparam \p|LessThan0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N36
+cyclonev_lcell_comb \p|LessThan0~3 (
+// Equation(s):
+// \p|LessThan0~3_combout  = ( \p|LessThan0~2_combout  & ( (!\p|count [4] & (!\p|d [4] & ((!\p|d [3]) # (\p|count [3])))) # (\p|count [4] & ((!\p|d [3]) # ((!\p|d [4]) # (\p|count [3])))) ) ) # ( !\p|LessThan0~2_combout  & ( (!\p|count [4] & (!\p|d [3] & 
+// (\p|count [3] & !\p|d [4]))) # (\p|count [4] & ((!\p|d [4]) # ((!\p|d [3] & \p|count [3])))) ) )
+
+	.dataa(!\p|d [3]),
+	.datab(!\p|count [4]),
+	.datac(!\p|count [3]),
+	.datad(!\p|d [4]),
+	.datae(gnd),
+	.dataf(!\p|LessThan0~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~3 .extended_lut = "off";
+defparam \p|LessThan0~3 .lut_mask = 64'h3B023B02BF23BF23;
+defparam \p|LessThan0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N56
+dffeas \p|d[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[5] .is_wysiwyg = "true";
+defparam \p|d[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N54
+cyclonev_lcell_comb \p|LessThan0~4 (
+// Equation(s):
+// \p|LessThan0~4_combout  = ( \p|d [5] & ( \p|count [5] & ( (!\p|LessThan0~1_combout  & ((!\p|d [6] & ((\p|count [6]) # (\p|LessThan0~3_combout ))) # (\p|d [6] & (\p|LessThan0~3_combout  & \p|count [6])))) ) ) ) # ( !\p|d [5] & ( \p|count [5] & ( 
+// (!\p|LessThan0~1_combout  & ((!\p|d [6]) # (\p|count [6]))) ) ) ) # ( \p|d [5] & ( !\p|count [5] & ( (!\p|d [6] & (!\p|LessThan0~1_combout  & \p|count [6])) ) ) ) # ( !\p|d [5] & ( !\p|count [5] & ( (!\p|LessThan0~1_combout  & ((!\p|d [6] & ((\p|count 
+// [6]) # (\p|LessThan0~3_combout ))) # (\p|d [6] & (\p|LessThan0~3_combout  & \p|count [6])))) ) ) )
+
+	.dataa(!\p|d [6]),
+	.datab(!\p|LessThan0~1_combout ),
+	.datac(!\p|LessThan0~3_combout ),
+	.datad(!\p|count [6]),
+	.datae(!\p|d [5]),
+	.dataf(!\p|count [5]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~4 .extended_lut = "off";
+defparam \p|LessThan0~4 .lut_mask = 64'h088C008888CC088C;
+defparam \p|LessThan0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y7_N4
+dffeas \p|d[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\rom|altsyncram_component|auto_generated|q_a [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\tick|CLK_OUT~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|d [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|d[9] .is_wysiwyg = "true";
+defparam \p|d[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N24
+cyclonev_lcell_comb \p|Add0~1 (
+// Equation(s):
+// \p|Add0~1_sumout  = SUM(( \p|count [9] ) + ( GND ) + ( \p|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\p|count [9]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\p|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\p|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|Add0~1 .extended_lut = "off";
+defparam \p|Add0~1 .lut_mask = 64'h0000FFFF000000FF;
+defparam \p|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N25
+dffeas \p|count[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|Add0~1_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|count[9] .is_wysiwyg = "true";
+defparam \p|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N33
+cyclonev_lcell_comb \p|LessThan0~0 (
+// Equation(s):
+// \p|LessThan0~0_combout  = ( \p|count [7] & ( !\p|d [7] ) )
+
+	.dataa(!\p|d [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\p|count [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~0 .extended_lut = "off";
+defparam \p|LessThan0~0 .lut_mask = 64'h00000000AAAAAAAA;
+defparam \p|LessThan0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y7_N48
+cyclonev_lcell_comb \p|LessThan0~5 (
+// Equation(s):
+// \p|LessThan0~5_combout  = ( \p|count [9] & ( \p|LessThan0~0_combout  & ( (!\p|count [8] & (\p|d [8] & \p|d [9])) ) ) ) # ( !\p|count [9] & ( \p|LessThan0~0_combout  & ( ((!\p|count [8] & \p|d [8])) # (\p|d [9]) ) ) ) # ( \p|count [9] & ( 
+// !\p|LessThan0~0_combout  & ( (\p|d [9] & ((!\p|count [8] & ((!\p|LessThan0~4_combout ) # (\p|d [8]))) # (\p|count [8] & (\p|d [8] & !\p|LessThan0~4_combout )))) ) ) ) # ( !\p|count [9] & ( !\p|LessThan0~0_combout  & ( ((!\p|count [8] & 
+// ((!\p|LessThan0~4_combout ) # (\p|d [8]))) # (\p|count [8] & (\p|d [8] & !\p|LessThan0~4_combout ))) # (\p|d [9]) ) ) )
+
+	.dataa(!\p|count [8]),
+	.datab(!\p|d [8]),
+	.datac(!\p|LessThan0~4_combout ),
+	.datad(!\p|d [9]),
+	.datae(!\p|count [9]),
+	.dataf(!\p|LessThan0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\p|LessThan0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \p|LessThan0~5 .extended_lut = "off";
+defparam \p|LessThan0~5 .lut_mask = 64'hB2FF00B222FF0022;
+defparam \p|LessThan0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y7_N49
+dffeas \p|pwm_out (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\p|LessThan0~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\p|pwm_out~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \p|pwm_out .is_wysiwyg = "true";
+defparam \p|pwm_out .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N57
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[1][17]~5 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[1][17]~5_combout  = ( \SPI_ADC|data_from_adc [7] & ( (\SPI_ADC|data_from_adc [6] & \SPI_ADC|data_from_adc [5]) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[1][17]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[1][17]~5 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[1][17]~5 .lut_mask = 64'h0000000011111111;
+defparam \mult|lpm_mult_component|mult_core|romout[1][17]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N39
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[0][17]~4 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[0][17]~4_combout  = ( \SPI_ADC|data_from_adc [3] & ( (\SPI_ADC|data_from_adc [1] & \SPI_ADC|data_from_adc [2]) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(!\SPI_ADC|data_from_adc [2]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[0][17]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[0][17]~4 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[0][17]~4 .lut_mask = 64'h0000000011111111;
+defparam \mult|lpm_mult_component|mult_core|romout[0][17]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N18
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[0][16]~3 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[0][16]~3_combout  = ( \SPI_ADC|data_from_adc [1] & ( (!\SPI_ADC|data_from_adc [2] & (\SPI_ADC|data_from_adc [3])) # (\SPI_ADC|data_from_adc [2] & (!\SPI_ADC|data_from_adc [3] & \SPI_ADC|data_from_adc [0])) ) ) # ( 
+// !\SPI_ADC|data_from_adc [1] & ( \SPI_ADC|data_from_adc [3] ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [2]),
+	.datac(!\SPI_ADC|data_from_adc [3]),
+	.datad(!\SPI_ADC|data_from_adc [0]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[0][16]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[0][16]~3 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[0][16]~3 .lut_mask = 64'h0F0F0F0F0C3C0C3C;
+defparam \mult|lpm_mult_component|mult_core|romout[0][16]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N21
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[0][15]~2 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[0][15]~2_combout  = ( \SPI_ADC|data_from_adc [1] & ( (!\SPI_ADC|data_from_adc [3] & (\SPI_ADC|data_from_adc [2] & !\SPI_ADC|data_from_adc [0])) # (\SPI_ADC|data_from_adc [3] & (!\SPI_ADC|data_from_adc [2])) ) ) # 
+// ( !\SPI_ADC|data_from_adc [1] & ( \SPI_ADC|data_from_adc [2] ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [3]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [2]),
+	.datad(!\SPI_ADC|data_from_adc [0]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[0][15]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[0][15]~2 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[0][15]~2 .lut_mask = 64'h0F0F0F0F5A505A50;
+defparam \mult|lpm_mult_component|mult_core|romout[0][15]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y6_N36
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[0][14]~1 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[0][14]~1_combout  = ( \SPI_ADC|data_from_adc [3] & ( (!\SPI_ADC|data_from_adc [1] & ((\SPI_ADC|data_from_adc [0]) # (\SPI_ADC|data_from_adc [2]))) # (\SPI_ADC|data_from_adc [1] & (\SPI_ADC|data_from_adc [2] & 
+// \SPI_ADC|data_from_adc [0])) ) ) # ( !\SPI_ADC|data_from_adc [3] & ( !\SPI_ADC|data_from_adc [1] $ (((!\SPI_ADC|data_from_adc [2]) # (!\SPI_ADC|data_from_adc [0]))) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(!\SPI_ADC|data_from_adc [2]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [0]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[0][14]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[0][14]~1 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[0][14]~1 .lut_mask = 64'h5566556622BB22BB;
+defparam \mult|lpm_mult_component|mult_core|romout[0][14]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N54
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|romout[1][9]~0 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|romout[1][9]~0_combout  = ( \SPI_ADC|data_from_adc [4] & ( !\SPI_ADC|data_from_adc [5] ) ) # ( !\SPI_ADC|data_from_adc [4] & ( \SPI_ADC|data_from_adc [5] ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\mult|lpm_mult_component|mult_core|romout[1][9]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|romout[1][9]~0 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|romout[1][9]~0 .lut_mask = 64'h33333333CCCCCCCC;
+defparam \mult|lpm_mult_component|mult_core|romout[1][9]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N0
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout  = CARRY(( GND ) + ( GND ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 .lut_mask = 64'h0000FFFF00000000;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N3
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout  = CARRY(( \SPI_ADC|data_from_adc [1] ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 .lut_mask = 64'h0000FFFF00005555;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N6
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout  = CARRY(( \SPI_ADC|data_from_adc [2] ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout  ))
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [2]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 .lut_mask = 64'h0000FFFF00003333;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N9
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout  = CARRY(( \SPI_ADC|data_from_adc [3] ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .lut_mask = 64'h0000FFFF00005555;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N12
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout  = CARRY(( \SPI_ADC|data_from_adc [0] ) + ( \SPI_ADC|data_from_adc [4] ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout  ))
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .lut_mask = 64'h0000F0F000003333;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N15
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout  = CARRY(( \SPI_ADC|data_from_adc [5] ) + ( !\SPI_ADC|data_from_adc [0] $ (!\SPI_ADC|data_from_adc [1]) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout  ))
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [1]),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 .lut_mask = 64'h0000CC3300000F0F;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N18
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  = SUM(( !\SPI_ADC|data_from_adc [2] $ (((!\SPI_ADC|data_from_adc [1] & !\SPI_ADC|data_from_adc [0]))) ) + ( \SPI_ADC|data_from_adc [6] ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  = CARRY(( !\SPI_ADC|data_from_adc [2] $ (((!\SPI_ADC|data_from_adc [1] & !\SPI_ADC|data_from_adc [0]))) ) + ( \SPI_ADC|data_from_adc [6] ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [6]),
+	.datad(!\SPI_ADC|data_from_adc [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .lut_mask = 64'h0000F0F000007788;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N21
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  = SUM(( \SPI_ADC|data_from_adc [7] ) + ( !\SPI_ADC|data_from_adc [3] $ ((((!\SPI_ADC|data_from_adc [1] & !\SPI_ADC|data_from_adc [2])) # (\SPI_ADC|data_from_adc [0]))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  = CARRY(( \SPI_ADC|data_from_adc [7] ) + ( !\SPI_ADC|data_from_adc [3] $ ((((!\SPI_ADC|data_from_adc [1] & !\SPI_ADC|data_from_adc [2])) # (\SPI_ADC|data_from_adc [0]))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [2]),
+	.datad(!\SPI_ADC|data_from_adc [7]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .lut_mask = 64'h0000B34C000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N24
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  = SUM(( \SPI_ADC|data_from_adc [4] ) + ( (!\SPI_ADC|data_from_adc [1] & (((!\SPI_ADC|data_from_adc [0] & \SPI_ADC|data_from_adc [2])) # (\SPI_ADC|data_from_adc [3]))) # 
+// (\SPI_ADC|data_from_adc [1] & (\SPI_ADC|data_from_adc [0] & ((!\SPI_ADC|data_from_adc [3])))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  = CARRY(( \SPI_ADC|data_from_adc [4] ) + ( (!\SPI_ADC|data_from_adc [1] & (((!\SPI_ADC|data_from_adc [0] & \SPI_ADC|data_from_adc [2])) # (\SPI_ADC|data_from_adc [3]))) # 
+// (\SPI_ADC|data_from_adc [1] & (\SPI_ADC|data_from_adc [0] & ((!\SPI_ADC|data_from_adc [3])))) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [2]),
+	.datad(!\SPI_ADC|data_from_adc [4]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .lut_mask = 64'h0000E655000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N27
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  = SUM(( \mult|lpm_mult_component|mult_core|romout[1][9]~0_combout  ) + ( (!\SPI_ADC|data_from_adc [1] & ((!\SPI_ADC|data_from_adc [0] & (!\SPI_ADC|data_from_adc [2] & 
+// \SPI_ADC|data_from_adc [3])) # (\SPI_ADC|data_from_adc [0] & (!\SPI_ADC|data_from_adc [2] $ (\SPI_ADC|data_from_adc [3]))))) # (\SPI_ADC|data_from_adc [1] & (!\SPI_ADC|data_from_adc [0] $ ((!\SPI_ADC|data_from_adc [2])))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  = CARRY(( \mult|lpm_mult_component|mult_core|romout[1][9]~0_combout  ) + ( (!\SPI_ADC|data_from_adc [1] & ((!\SPI_ADC|data_from_adc [0] & (!\SPI_ADC|data_from_adc [2] & 
+// \SPI_ADC|data_from_adc [3])) # (\SPI_ADC|data_from_adc [0] & (!\SPI_ADC|data_from_adc [2] $ (\SPI_ADC|data_from_adc [3]))))) # (\SPI_ADC|data_from_adc [1] & (!\SPI_ADC|data_from_adc [0] $ ((!\SPI_ADC|data_from_adc [2])))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [2]),
+	.datad(!\mult|lpm_mult_component|mult_core|romout[1][9]~0_combout ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .lut_mask = 64'h0000CB69000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N30
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  = SUM(( !\SPI_ADC|data_from_adc [6] $ (((!\SPI_ADC|data_from_adc [5] & !\SPI_ADC|data_from_adc [4]))) ) + ( \mult|lpm_mult_component|mult_core|romout[0][14]~1_combout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  = CARRY(( !\SPI_ADC|data_from_adc [6] $ (((!\SPI_ADC|data_from_adc [5] & !\SPI_ADC|data_from_adc [4]))) ) + ( \mult|lpm_mult_component|mult_core|romout[0][14]~1_combout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|romout[0][14]~1_combout ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .lut_mask = 64'h0000FF0000006A6A;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N33
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  = SUM(( !\SPI_ADC|data_from_adc [7] $ ((((!\SPI_ADC|data_from_adc [6] & !\SPI_ADC|data_from_adc [5])) # (\SPI_ADC|data_from_adc [4]))) ) + ( 
+// \mult|lpm_mult_component|mult_core|romout[0][15]~2_combout  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  = CARRY(( !\SPI_ADC|data_from_adc [7] $ ((((!\SPI_ADC|data_from_adc [6] & !\SPI_ADC|data_from_adc [5])) # (\SPI_ADC|data_from_adc [4]))) ) + ( 
+// \mult|lpm_mult_component|mult_core|romout[0][15]~2_combout  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(!\SPI_ADC|data_from_adc [7]),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|romout[0][15]~2_combout ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .lut_mask = 64'h0000FF000000708F;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N36
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  = SUM(( (!\SPI_ADC|data_from_adc [5] & (((\SPI_ADC|data_from_adc [6] & !\SPI_ADC|data_from_adc [4])) # (\SPI_ADC|data_from_adc [7]))) # (\SPI_ADC|data_from_adc [5] & 
+// (((\SPI_ADC|data_from_adc [4] & !\SPI_ADC|data_from_adc [7])))) ) + ( \mult|lpm_mult_component|mult_core|romout[0][16]~3_combout  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30  = CARRY(( (!\SPI_ADC|data_from_adc [5] & (((\SPI_ADC|data_from_adc [6] & !\SPI_ADC|data_from_adc [4])) # (\SPI_ADC|data_from_adc [7]))) # (\SPI_ADC|data_from_adc [5] & 
+// (((\SPI_ADC|data_from_adc [4] & !\SPI_ADC|data_from_adc [7])))) ) + ( \mult|lpm_mult_component|mult_core|romout[0][16]~3_combout  ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(!\SPI_ADC|data_from_adc [7]),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|romout[0][16]~3_combout ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .lut_mask = 64'h0000FF00000043CC;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N39
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  = SUM(( \mult|lpm_mult_component|mult_core|romout[0][17]~4_combout  ) + ( (!\SPI_ADC|data_from_adc [6] & (!\SPI_ADC|data_from_adc [4] $ (((!\SPI_ADC|data_from_adc [7]) # 
+// (\SPI_ADC|data_from_adc [5]))))) # (\SPI_ADC|data_from_adc [6] & ((!\SPI_ADC|data_from_adc [5] & (\SPI_ADC|data_from_adc [4] & \SPI_ADC|data_from_adc [7])) # (\SPI_ADC|data_from_adc [5] & (!\SPI_ADC|data_from_adc [4])))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34  = CARRY(( \mult|lpm_mult_component|mult_core|romout[0][17]~4_combout  ) + ( (!\SPI_ADC|data_from_adc [6] & (!\SPI_ADC|data_from_adc [4] $ (((!\SPI_ADC|data_from_adc [7]) # 
+// (\SPI_ADC|data_from_adc [5]))))) # (\SPI_ADC|data_from_adc [6] & ((!\SPI_ADC|data_from_adc [5] & (\SPI_ADC|data_from_adc [4] & \SPI_ADC|data_from_adc [7])) # (\SPI_ADC|data_from_adc [5] & (!\SPI_ADC|data_from_adc [4])))) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(!\mult|lpm_mult_component|mult_core|romout[0][17]~4_combout ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [7]),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .lut_mask = 64'h0000E569000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N42
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout  = SUM(( (!\SPI_ADC|data_from_adc [5] & ((!\SPI_ADC|data_from_adc [6] & (\SPI_ADC|data_from_adc [4] & \SPI_ADC|data_from_adc [7])) # (\SPI_ADC|data_from_adc [6] & 
+// ((\SPI_ADC|data_from_adc [7]) # (\SPI_ADC|data_from_adc [4]))))) # (\SPI_ADC|data_from_adc [5] & (!\SPI_ADC|data_from_adc [7] $ (((\SPI_ADC|data_from_adc [6] & \SPI_ADC|data_from_adc [4]))))) ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  = CARRY(( (!\SPI_ADC|data_from_adc [5] & ((!\SPI_ADC|data_from_adc [6] & (\SPI_ADC|data_from_adc [4] & \SPI_ADC|data_from_adc [7])) # (\SPI_ADC|data_from_adc [6] & 
+// ((\SPI_ADC|data_from_adc [7]) # (\SPI_ADC|data_from_adc [4]))))) # (\SPI_ADC|data_from_adc [5] & (!\SPI_ADC|data_from_adc [7] $ (((\SPI_ADC|data_from_adc [6] & \SPI_ADC|data_from_adc [4]))))) ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(!\SPI_ADC|data_from_adc [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .lut_mask = 64'h0000FFFF0000364D;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N45
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout  = SUM(( (!\SPI_ADC|data_from_adc [6] & (\SPI_ADC|data_from_adc [5] & ((\SPI_ADC|data_from_adc [7])))) # (\SPI_ADC|data_from_adc [6] & ((!\SPI_ADC|data_from_adc [5]) # 
+// ((!\SPI_ADC|data_from_adc [4] & !\SPI_ADC|data_from_adc [7])))) ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42  = CARRY(( (!\SPI_ADC|data_from_adc [6] & (\SPI_ADC|data_from_adc [5] & ((\SPI_ADC|data_from_adc [7])))) # (\SPI_ADC|data_from_adc [6] & ((!\SPI_ADC|data_from_adc [5]) # 
+// ((!\SPI_ADC|data_from_adc [4] & !\SPI_ADC|data_from_adc [7])))) ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(!\SPI_ADC|data_from_adc [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 .lut_mask = 64'h0000FFFF00005466;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N48
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout  = SUM(( (!\SPI_ADC|data_from_adc [6] & (((\SPI_ADC|data_from_adc [7])))) # (\SPI_ADC|data_from_adc [6] & ((!\SPI_ADC|data_from_adc [5] & ((\SPI_ADC|data_from_adc [7]))) # 
+// (\SPI_ADC|data_from_adc [5] & (\SPI_ADC|data_from_adc [4] & !\SPI_ADC|data_from_adc [7])))) ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42  ))
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46  = CARRY(( (!\SPI_ADC|data_from_adc [6] & (((\SPI_ADC|data_from_adc [7])))) # (\SPI_ADC|data_from_adc [6] & ((!\SPI_ADC|data_from_adc [5] & ((\SPI_ADC|data_from_adc [7]))) # 
+// (\SPI_ADC|data_from_adc [5] & (\SPI_ADC|data_from_adc [4] & !\SPI_ADC|data_from_adc [7])))) ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(!\SPI_ADC|data_from_adc [5]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(!\SPI_ADC|data_from_adc [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 .lut_mask = 64'h0000FFFF000001EE;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y6_N51
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout  = SUM(( \mult|lpm_mult_component|mult_core|romout[1][17]~5_combout  ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|romout[1][17]~5_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N0
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  ) + ( \SPI_ADC|data_from_adc [8] ) + ( !VCC ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  ) + ( \SPI_ADC|data_from_adc [8] ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ),
+	.datac(!\SPI_ADC|data_from_adc [8]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .lut_mask = 64'h0000F0F000003333;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N3
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  ) + ( \SPI_ADC|data_from_adc [9] ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  ) + ( \SPI_ADC|data_from_adc [9] ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [9]),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .lut_mask = 64'h0000F0F0000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N6
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N9
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  ) + ( GND ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  ))
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .lut_mask = 64'h0000FFFF00005555;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N12
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  ) + ( \SPI_ADC|data_from_adc [8] ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  ) + ( \SPI_ADC|data_from_adc [8] ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .lut_mask = 64'h0000AAAA000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N15
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  = SUM(( !\SPI_ADC|data_from_adc [8] $ (!\SPI_ADC|data_from_adc [9]) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  = CARRY(( !\SPI_ADC|data_from_adc [8] $ (!\SPI_ADC|data_from_adc [9]) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [8]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .lut_mask = 64'h0000FF0000005A5A;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N18
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout  ) + ( (\SPI_ADC|data_from_adc [9]) # (\SPI_ADC|data_from_adc [8]) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout  ) + ( (\SPI_ADC|data_from_adc [9]) # (\SPI_ADC|data_from_adc [8]) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [9]),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .lut_mask = 64'h0000AA00000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N21
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  = SUM(( (!\SPI_ADC|data_from_adc [8] & \SPI_ADC|data_from_adc [9]) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  = CARRY(( (!\SPI_ADC|data_from_adc [8] & \SPI_ADC|data_from_adc [9]) ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [8]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41_sumout ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .lut_mask = 64'h0000FF0000000A0A;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N24
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  = SUM(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout  ) + ( (\SPI_ADC|data_from_adc [8] & \SPI_ADC|data_from_adc [9]) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34  = CARRY(( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout  ) + ( (\SPI_ADC|data_from_adc [8] & \SPI_ADC|data_from_adc [9]) ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45_sumout ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [9]),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .lut_mask = 64'h0000FFAA000000FF;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N27
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  = SUM(( \SPI_ADC|data_from_adc [8] ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38  = CARRY(( \SPI_ADC|data_from_adc [8] ) + ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout  ) + ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49_sumout ),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .lut_mask = 64'h0000FF0000005555;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N30
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  = SUM(( GND ) + ( \SPI_ADC|data_from_adc [9] ) + ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38  ))
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42  = CARRY(( GND ) + ( \SPI_ADC|data_from_adc [9] ) + ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38  ))
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [9]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.cout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 .lut_mask = 64'h0000CCCC00000000;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N33
+cyclonev_lcell_comb \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 (
+// Equation(s):
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  = SUM(( GND ) + ( GND ) + ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 .extended_lut = "off";
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 .lut_mask = 64'h0000FFFF00000000;
+defparam \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N51
+cyclonev_lcell_comb \bcd|A2|WideOr1~0 (
+// Equation(s):
+// \bcd|A2|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A2|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A2|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A2|WideOr1~0 .lut_mask = 64'h5000500005A005A0;
+defparam \bcd|A2|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N21
+cyclonev_lcell_comb \bcd|A2|WideOr3~0 (
+// Equation(s):
+// \bcd|A2|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  $ (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A2|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A2|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A2|WideOr3~0 .lut_mask = 64'h11AA11AA88668866;
+defparam \bcd|A2|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N18
+cyclonev_lcell_comb \bcd|A2|WideOr2~0 (
+// Equation(s):
+// \bcd|A2|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout )) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout )) ) )
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A2|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A2|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A2|WideOr2~0 .lut_mask = 64'h3C303C300C3C0C3C;
+defparam \bcd|A2|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N54
+cyclonev_lcell_comb \bcd|A4|WideOr2~0 (
+// Equation(s):
+// \bcd|A4|WideOr2~0_combout  = ( \bcd|A2|WideOr2~0_combout  & ( (!\bcd|A2|WideOr1~0_combout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & \bcd|A2|WideOr3~0_combout )) # (\bcd|A2|WideOr1~0_combout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\bcd|A2|WideOr3~0_combout )) ) ) # ( !\bcd|A2|WideOr2~0_combout  & ( !\bcd|A2|WideOr3~0_combout  $ (((!\bcd|A2|WideOr1~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ))) ) )
+
+	.dataa(!\bcd|A2|WideOr1~0_combout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datac(!\bcd|A2|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A2|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A4|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A4|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A4|WideOr2~0 .lut_mask = 64'h4B4B4B4B42424242;
+defparam \bcd|A4|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N57
+cyclonev_lcell_comb \bcd|A4|WideOr1~0 (
+// Equation(s):
+// \bcd|A4|WideOr1~0_combout  = ( \bcd|A2|WideOr2~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\bcd|A2|WideOr3~0_combout ) ) ) # ( !\bcd|A2|WideOr2~0_combout  & ( (\bcd|A2|WideOr1~0_combout 
+//  & ((\bcd|A2|WideOr3~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ))) ) )
+
+	.dataa(!\bcd|A2|WideOr1~0_combout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datac(gnd),
+	.datad(!\bcd|A2|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A2|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A4|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A4|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A4|WideOr1~0 .lut_mask = 64'h11551155CC00CC00;
+defparam \bcd|A4|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N3
+cyclonev_lcell_comb \bcd|A4|WideOr3~0 (
+// Equation(s):
+// \bcd|A4|WideOr3~0_combout  = ( \bcd|A2|WideOr2~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (!\bcd|A2|WideOr1~0_combout  $ (!\bcd|A2|WideOr3~0_combout ))) ) ) # ( 
+// !\bcd|A2|WideOr2~0_combout  & ( !\bcd|A2|WideOr1~0_combout  $ (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ) ) )
+
+	.dataa(!\bcd|A2|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(!\bcd|A2|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A2|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A4|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A4|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A4|WideOr3~0 .lut_mask = 64'h5A5A5A5A50A050A0;
+defparam \bcd|A4|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N33
+cyclonev_lcell_comb \bcd|A6|WideOr1~0 (
+// Equation(s):
+// \bcd|A6|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (!\bcd|A4|WideOr2~0_combout  & \bcd|A4|WideOr1~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (!\bcd|A4|WideOr2~0_combout  & (\bcd|A4|WideOr1~0_combout  & \bcd|A4|WideOr3~0_combout )) # (\bcd|A4|WideOr2~0_combout  & ((!\bcd|A4|WideOr3~0_combout ))) ) 
+// )
+
+	.dataa(!\bcd|A4|WideOr2~0_combout ),
+	.datab(!\bcd|A4|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A4|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A6|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A6|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A6|WideOr1~0 .lut_mask = 64'h5522552222222222;
+defparam \bcd|A6|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N30
+cyclonev_lcell_comb \bcd|A6|WideOr2~0 (
+// Equation(s):
+// \bcd|A6|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (\bcd|A4|WideOr3~0_combout  & ((!\bcd|A4|WideOr1~0_combout ) # (!\bcd|A4|WideOr2~0_combout ))) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (!\bcd|A4|WideOr1~0_combout  & (!\bcd|A4|WideOr2~0_combout  & \bcd|A4|WideOr3~0_combout )) # (\bcd|A4|WideOr1~0_combout  & ((!\bcd|A4|WideOr3~0_combout ))) 
+// ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A4|WideOr1~0_combout ),
+	.datac(!\bcd|A4|WideOr2~0_combout ),
+	.datad(!\bcd|A4|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A6|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A6|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A6|WideOr2~0 .lut_mask = 64'h33C033C000FC00FC;
+defparam \bcd|A6|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N15
+cyclonev_lcell_comb \bcd|A6|WideOr3~0 (
+// Equation(s):
+// \bcd|A6|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (!\bcd|A4|WideOr2~0_combout  & !\bcd|A4|WideOr1~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( !\bcd|A4|WideOr1~0_combout  $ (((!\bcd|A4|WideOr2~0_combout ) # (!\bcd|A4|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A4|WideOr2~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A4|WideOr1~0_combout ),
+	.datad(!\bcd|A4|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A6|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A6|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A6|WideOr3~0 .lut_mask = 64'h0F5A0F5AA0A0A0A0;
+defparam \bcd|A6|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N27
+cyclonev_lcell_comb \bcd|A8|WideOr3~0 (
+// Equation(s):
+// \bcd|A8|WideOr3~0_combout  = ( \bcd|A6|WideOr3~0_combout  & ( (!\bcd|A6|WideOr1~0_combout  & (!\bcd|A6|WideOr2~0_combout  $ (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) # (\bcd|A6|WideOr1~0_combout  & 
+// (!\bcd|A6|WideOr2~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )) ) ) # ( !\bcd|A6|WideOr3~0_combout  & ( (!\bcd|A6|WideOr1~0_combout  & (!\bcd|A6|WideOr2~0_combout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )) # (\bcd|A6|WideOr1~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) ) )
+
+	.dataa(!\bcd|A6|WideOr1~0_combout ),
+	.datab(!\bcd|A6|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A6|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A8|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A8|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A8|WideOr3~0 .lut_mask = 64'h5858585868686868;
+defparam \bcd|A8|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N6
+cyclonev_lcell_comb \bcd|A8|WideOr2~0 (
+// Equation(s):
+// \bcd|A8|WideOr2~0_combout  = ( \bcd|A6|WideOr3~0_combout  & ( (!\bcd|A6|WideOr2~0_combout  & ((!\bcd|A6|WideOr1~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) # (\bcd|A6|WideOr2~0_combout  & 
+// (!\bcd|A6|WideOr1~0_combout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )) ) ) # ( !\bcd|A6|WideOr3~0_combout  & ( (\bcd|A6|WideOr1~0_combout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A6|WideOr2~0_combout ),
+	.datac(!\bcd|A6|WideOr1~0_combout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A6|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A8|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A8|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A8|WideOr2~0 .lut_mask = 64'h0F000F00C0FCC0FC;
+defparam \bcd|A8|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N9
+cyclonev_lcell_comb \bcd|A8|WideOr1~0 (
+// Equation(s):
+// \bcd|A8|WideOr1~0_combout  = ( \bcd|A6|WideOr3~0_combout  & ( (\bcd|A6|WideOr1~0_combout  & !\bcd|A6|WideOr2~0_combout ) ) ) # ( !\bcd|A6|WideOr3~0_combout  & ( (!\bcd|A6|WideOr2~0_combout  & (\bcd|A6|WideOr1~0_combout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )) # (\bcd|A6|WideOr2~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) ) )
+
+	.dataa(!\bcd|A6|WideOr1~0_combout ),
+	.datab(!\bcd|A6|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A6|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A8|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A8|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A8|WideOr1~0 .lut_mask = 64'h3434343444444444;
+defparam \bcd|A8|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N39
+cyclonev_lcell_comb \bcd|A11|WideOr3~0 (
+// Equation(s):
+// \bcd|A11|WideOr3~0_combout  = ( \bcd|A8|WideOr1~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & ((!\bcd|A8|WideOr3~0_combout ) # (!\bcd|A8|WideOr2~0_combout ))) ) ) # ( 
+// !\bcd|A8|WideOr1~0_combout  & ( (!\bcd|A8|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) # (\bcd|A8|WideOr2~0_combout  & (\bcd|A8|WideOr3~0_combout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) )
+
+	.dataa(!\bcd|A8|WideOr3~0_combout ),
+	.datab(!\bcd|A8|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A11|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A11|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A11|WideOr3~0 .lut_mask = 64'h11CC11CCEE00EE00;
+defparam \bcd|A11|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N45
+cyclonev_lcell_comb \bcd|A11|WideOr1~0 (
+// Equation(s):
+// \bcd|A11|WideOr1~0_combout  = ( \bcd|A8|WideOr1~0_combout  & ( !\bcd|A8|WideOr2~0_combout  $ (((!\bcd|A8|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) ) ) # ( 
+// !\bcd|A8|WideOr1~0_combout  & ( (!\bcd|A8|WideOr3~0_combout  & (\bcd|A8|WideOr2~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) )
+
+	.dataa(!\bcd|A8|WideOr3~0_combout ),
+	.datab(!\bcd|A8|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A11|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A11|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A11|WideOr1~0 .lut_mask = 64'h2200220066CC66CC;
+defparam \bcd|A11|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N42
+cyclonev_lcell_comb \bcd|A11|WideOr2~0 (
+// Equation(s):
+// \bcd|A11|WideOr2~0_combout  = ( \bcd|A8|WideOr1~0_combout  & ( (!\bcd|A8|WideOr3~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) # (\bcd|A8|WideOr3~0_combout  & (!\bcd|A8|WideOr2~0_combout  
+// & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) ) # ( !\bcd|A8|WideOr1~0_combout  & ( (\bcd|A8|WideOr3~0_combout  & ((!\bcd|A8|WideOr2~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) ) )
+
+	.dataa(!\bcd|A8|WideOr3~0_combout ),
+	.datab(!\bcd|A8|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A11|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A11|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A11|WideOr2~0 .lut_mask = 64'h45454545A4A4A4A4;
+defparam \bcd|A11|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N30
+cyclonev_lcell_comb \bcd|A14|WideOr1~0 (
+// Equation(s):
+// \bcd|A14|WideOr1~0_combout  = ( !\bcd|A11|WideOr2~0_combout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( \bcd|A11|WideOr1~0_combout  ) ) ) # ( \bcd|A11|WideOr2~0_combout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr3~0_combout  ) ) ) # ( !\bcd|A11|WideOr2~0_combout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( (\bcd|A11|WideOr3~0_combout  & \bcd|A11|WideOr1~0_combout ) ) ) )
+
+	.dataa(!\bcd|A11|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A11|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A11|WideOr2~0_combout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A14|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A14|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A14|WideOr1~0 .lut_mask = 64'h0505AAAA0F0F0000;
+defparam \bcd|A14|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N27
+cyclonev_lcell_comb \bcd|A14|WideOr3~0 (
+// Equation(s):
+// \bcd|A14|WideOr3~0_combout  = ( \bcd|A11|WideOr1~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ((!\bcd|A11|WideOr3~0_combout ) # (!\bcd|A11|WideOr2~0_combout ))) ) ) # ( 
+// !\bcd|A11|WideOr1~0_combout  & ( (!\bcd|A11|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ))) # (\bcd|A11|WideOr2~0_combout  & (\bcd|A11|WideOr3~0_combout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout )) ) )
+
+	.dataa(!\bcd|A11|WideOr3~0_combout ),
+	.datab(!\bcd|A11|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A11|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A14|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A14|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A14|WideOr3~0 .lut_mask = 64'h1C1C1C1CE0E0E0E0;
+defparam \bcd|A14|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N51
+cyclonev_lcell_comb \bcd|A14|WideOr2~0 (
+// Equation(s):
+// \bcd|A14|WideOr2~0_combout  = ( \bcd|A11|WideOr2~0_combout  & ( \bcd|A11|WideOr3~0_combout  & ( (!\bcd|A11|WideOr1~0_combout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ) ) ) ) # ( 
+// !\bcd|A11|WideOr2~0_combout  & ( \bcd|A11|WideOr3~0_combout  & ( (!\bcd|A11|WideOr1~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ) ) ) ) # ( \bcd|A11|WideOr2~0_combout  & ( 
+// !\bcd|A11|WideOr3~0_combout  & ( (\bcd|A11|WideOr1~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ) ) ) ) # ( !\bcd|A11|WideOr2~0_combout  & ( !\bcd|A11|WideOr3~0_combout  & ( 
+// (\bcd|A11|WideOr1~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ) ) ) )
+
+	.dataa(!\bcd|A11|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datad(gnd),
+	.datae(!\bcd|A11|WideOr2~0_combout ),
+	.dataf(!\bcd|A11|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A14|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A14|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A14|WideOr2~0 .lut_mask = 64'h50505050AFAF0A0A;
+defparam \bcd|A14|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N36
+cyclonev_lcell_comb \bcd|A17|WideOr1~0 (
+// Equation(s):
+// \bcd|A17|WideOr1~0_combout  = ( \bcd|A14|WideOr2~0_combout  & ( (!\bcd|A14|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ) ) ) # ( !\bcd|A14|WideOr2~0_combout  & ( 
+// (\bcd|A14|WideOr1~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ) # (\bcd|A14|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A14|WideOr1~0_combout ),
+	.datab(!\bcd|A14|WideOr3~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A14|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A17|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A17|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A17|WideOr1~0 .lut_mask = 64'h15151515C0C0C0C0;
+defparam \bcd|A17|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N39
+cyclonev_lcell_comb \bcd|A17|WideOr3~0 (
+// Equation(s):
+// \bcd|A17|WideOr3~0_combout  = ( \bcd|A14|WideOr2~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & (!\bcd|A14|WideOr1~0_combout  $ (!\bcd|A14|WideOr3~0_combout ))) ) ) # ( 
+// !\bcd|A14|WideOr2~0_combout  & ( !\bcd|A14|WideOr1~0_combout  $ (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ) ) )
+
+	.dataa(!\bcd|A14|WideOr1~0_combout ),
+	.datab(!\bcd|A14|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A14|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A17|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A17|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A17|WideOr3~0 .lut_mask = 64'h55AA55AA66006600;
+defparam \bcd|A17|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N6
+cyclonev_lcell_comb \bcd|A17|WideOr2~0 (
+// Equation(s):
+// \bcd|A17|WideOr2~0_combout  = ( \bcd|A14|WideOr2~0_combout  & ( (!\bcd|A14|WideOr1~0_combout  & (\bcd|A14|WideOr3~0_combout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout )) # (\bcd|A14|WideOr1~0_combout  & 
+// (!\bcd|A14|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout )) ) ) # ( !\bcd|A14|WideOr2~0_combout  & ( !\bcd|A14|WideOr3~0_combout  $ (((!\bcd|A14|WideOr1~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ))) ) )
+
+	.dataa(!\bcd|A14|WideOr1~0_combout ),
+	.datab(!\bcd|A14|WideOr3~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A14|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A17|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A17|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A17|WideOr2~0 .lut_mask = 64'h6363636342424242;
+defparam \bcd|A17|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N27
+cyclonev_lcell_comb \bcd|A21|WideOr3~0 (
+// Equation(s):
+// \bcd|A21|WideOr3~0_combout  = ( \bcd|A17|WideOr2~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & (!\bcd|A17|WideOr1~0_combout  $ (!\bcd|A17|WideOr3~0_combout ))) ) ) # ( 
+// !\bcd|A17|WideOr2~0_combout  & ( !\bcd|A17|WideOr1~0_combout  $ (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ) ) )
+
+	.dataa(!\bcd|A17|WideOr1~0_combout ),
+	.datab(!\bcd|A17|WideOr3~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A17|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A21|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A21|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A21|WideOr3~0 .lut_mask = 64'h5A5A5A5A60606060;
+defparam \bcd|A21|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N18
+cyclonev_lcell_comb \bcd|A21|WideOr1~0 (
+// Equation(s):
+// \bcd|A21|WideOr1~0_combout  = ( \bcd|A17|WideOr3~0_combout  & ( (!\bcd|A17|WideOr2~0_combout  & \bcd|A17|WideOr1~0_combout ) ) ) # ( !\bcd|A17|WideOr3~0_combout  & ( (!\bcd|A17|WideOr2~0_combout  & (\bcd|A17|WideOr1~0_combout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout )) # (\bcd|A17|WideOr2~0_combout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A17|WideOr2~0_combout ),
+	.datac(!\bcd|A17|WideOr1~0_combout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A17|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A21|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A21|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A21|WideOr1~0 .lut_mask = 64'h330C330C0C0C0C0C;
+defparam \bcd|A21|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N24
+cyclonev_lcell_comb \bcd|A21|WideOr2~0 (
+// Equation(s):
+// \bcd|A21|WideOr2~0_combout  = ( \bcd|A17|WideOr2~0_combout  & ( (!\bcd|A17|WideOr1~0_combout  & (\bcd|A17|WideOr3~0_combout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout )) # (\bcd|A17|WideOr1~0_combout  & 
+// (!\bcd|A17|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout )) ) ) # ( !\bcd|A17|WideOr2~0_combout  & ( !\bcd|A17|WideOr3~0_combout  $ (((!\bcd|A17|WideOr1~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ))) ) )
+
+	.dataa(!\bcd|A17|WideOr1~0_combout ),
+	.datab(!\bcd|A17|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A17|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A21|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A21|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A21|WideOr2~0 .lut_mask = 64'h6633663344224422;
+defparam \bcd|A21|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N48
+cyclonev_lcell_comb \bcd|A25|WideOr3~0 (
+// Equation(s):
+// \bcd|A25|WideOr3~0_combout  = ( \bcd|A21|WideOr2~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & (!\bcd|A21|WideOr3~0_combout  $ (!\bcd|A21|WideOr1~0_combout ))) ) ) # ( 
+// !\bcd|A21|WideOr2~0_combout  & ( !\bcd|A21|WideOr1~0_combout  $ (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ) ) )
+
+	.dataa(!\bcd|A21|WideOr3~0_combout ),
+	.datab(!\bcd|A21|WideOr1~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A21|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A25|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A25|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A25|WideOr3~0 .lut_mask = 64'h3C3C3C3C60606060;
+defparam \bcd|A25|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N30
+cyclonev_lcell_comb \bcd|A25|WideOr1~0 (
+// Equation(s):
+// \bcd|A25|WideOr1~0_combout  = ( \bcd|A21|WideOr2~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & !\bcd|A21|WideOr3~0_combout ) ) ) # ( !\bcd|A21|WideOr2~0_combout  & ( 
+// (\bcd|A21|WideOr1~0_combout  & ((\bcd|A21|WideOr3~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A21|WideOr1~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(!\bcd|A21|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A21|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A25|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A25|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A25|WideOr1~0 .lut_mask = 64'h03330333F000F000;
+defparam \bcd|A25|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N51
+cyclonev_lcell_comb \bcd|A25|WideOr2~0 (
+// Equation(s):
+// \bcd|A25|WideOr2~0_combout  = ( \bcd|A21|WideOr2~0_combout  & ( (!\bcd|A21|WideOr3~0_combout  & (\bcd|A21|WideOr1~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout )) # (\bcd|A21|WideOr3~0_combout  & 
+// (!\bcd|A21|WideOr1~0_combout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout )) ) ) # ( !\bcd|A21|WideOr2~0_combout  & ( !\bcd|A21|WideOr3~0_combout  $ (((!\bcd|A21|WideOr1~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ))) ) )
+
+	.dataa(!\bcd|A21|WideOr3~0_combout ),
+	.datab(!\bcd|A21|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A21|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A25|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A25|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A25|WideOr2~0 .lut_mask = 64'h6655665522442244;
+defparam \bcd|A25|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N54
+cyclonev_lcell_comb \bcd|A29|WideOr1~0 (
+// Equation(s):
+// \bcd|A29|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  & ( (\bcd|A25|WideOr1~0_combout  & !\bcd|A25|WideOr2~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  & ( (!\bcd|A25|WideOr3~0_combout  & ((\bcd|A25|WideOr2~0_combout ))) # (\bcd|A25|WideOr3~0_combout  & (\bcd|A25|WideOr1~0_combout  & !\bcd|A25|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A25|WideOr3~0_combout ),
+	.datab(!\bcd|A25|WideOr1~0_combout ),
+	.datac(!\bcd|A25|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A29|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A29|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A29|WideOr1~0 .lut_mask = 64'h1A1A1A1A30303030;
+defparam \bcd|A29|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N3
+cyclonev_lcell_comb \bcd|A29|WideOr2~0 (
+// Equation(s):
+// \bcd|A29|WideOr2~0_combout  = ( \bcd|A25|WideOr2~0_combout  & ( (!\bcd|A25|WideOr3~0_combout  & (\bcd|A25|WideOr1~0_combout  & !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout )) # (\bcd|A25|WideOr3~0_combout  & 
+// (!\bcd|A25|WideOr1~0_combout  & \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout )) ) ) # ( !\bcd|A25|WideOr2~0_combout  & ( !\bcd|A25|WideOr3~0_combout  $ (((!\bcd|A25|WideOr1~0_combout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ))) ) )
+
+	.dataa(!\bcd|A25|WideOr3~0_combout ),
+	.datab(!\bcd|A25|WideOr1~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A25|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A29|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A29|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A29|WideOr2~0 .lut_mask = 64'h6565656524242424;
+defparam \bcd|A29|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N0
+cyclonev_lcell_comb \bcd|A29|WideOr3~0 (
+// Equation(s):
+// \bcd|A29|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  & ( (!\bcd|A25|WideOr1~0_combout  & !\bcd|A25|WideOr2~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  & ( !\bcd|A25|WideOr1~0_combout  $ (((!\bcd|A25|WideOr3~0_combout ) # (!\bcd|A25|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A25|WideOr3~0_combout ),
+	.datab(!\bcd|A25|WideOr1~0_combout ),
+	.datac(!\bcd|A25|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A29|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A29|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A29|WideOr3~0 .lut_mask = 64'h36363636C0C0C0C0;
+defparam \bcd|A29|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N15
+cyclonev_lcell_comb \h0|WideOr6~0 (
+// Equation(s):
+// \h0|WideOr6~0_combout  = ( \bcd|A29|WideOr3~0_combout  & ( (\bcd|A29|WideOr1~0_combout  & (!\bcd|A29|WideOr2~0_combout  & \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout )) ) ) # ( !\bcd|A29|WideOr3~0_combout  & ( 
+// (!\bcd|A29|WideOr1~0_combout  & (!\bcd|A29|WideOr2~0_combout  $ (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) # (\bcd|A29|WideOr1~0_combout  & (\bcd|A29|WideOr2~0_combout  & 
+// \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout )) ) )
+
+	.dataa(!\bcd|A29|WideOr1~0_combout ),
+	.datab(!\bcd|A29|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr6~0 .extended_lut = "off";
+defparam \h0|WideOr6~0 .lut_mask = 64'h2929292904040404;
+defparam \h0|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N42
+cyclonev_lcell_comb \h0|WideOr5~0 (
+// Equation(s):
+// \h0|WideOr5~0_combout  = ( \bcd|A29|WideOr3~0_combout  & ( (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & (\bcd|A29|WideOr2~0_combout )) # 
+// (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & ((\bcd|A29|WideOr1~0_combout ))) ) ) # ( !\bcd|A29|WideOr3~0_combout  & ( (\bcd|A29|WideOr2~0_combout  & (!\bcd|A29|WideOr1~0_combout  $ 
+// (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A29|WideOr2~0_combout ),
+	.datac(!\bcd|A29|WideOr1~0_combout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr5~0 .extended_lut = "off";
+defparam \h0|WideOr5~0 .lut_mask = 64'h03300330330F330F;
+defparam \h0|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N39
+cyclonev_lcell_comb \h0|WideOr4~0 (
+// Equation(s):
+// \h0|WideOr4~0_combout  = ( \bcd|A29|WideOr3~0_combout  & ( (!\bcd|A29|WideOr1~0_combout  & (!\bcd|A29|WideOr2~0_combout  & !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout )) # (\bcd|A29|WideOr1~0_combout  & 
+// (\bcd|A29|WideOr2~0_combout )) ) ) # ( !\bcd|A29|WideOr3~0_combout  & ( (\bcd|A29|WideOr1~0_combout  & (\bcd|A29|WideOr2~0_combout  & !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout )) ) )
+
+	.dataa(!\bcd|A29|WideOr1~0_combout ),
+	.datab(!\bcd|A29|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr4~0 .extended_lut = "off";
+defparam \h0|WideOr4~0 .lut_mask = 64'h1010101091919191;
+defparam \h0|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N6
+cyclonev_lcell_comb \h0|WideOr3~0 (
+// Equation(s):
+// \h0|WideOr3~0_combout  = ( \bcd|A29|WideOr3~0_combout  & ( (!\bcd|A29|WideOr2~0_combout  & (\bcd|A29|WideOr1~0_combout  & !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout )) # (\bcd|A29|WideOr2~0_combout  & 
+// ((\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) ) ) # ( !\bcd|A29|WideOr3~0_combout  & ( (!\bcd|A29|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) # 
+// (\bcd|A29|WideOr2~0_combout  & (!\bcd|A29|WideOr1~0_combout  & !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout )) ) )
+
+	.dataa(!\bcd|A29|WideOr1~0_combout ),
+	.datab(!\bcd|A29|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr3~0 .extended_lut = "off";
+defparam \h0|WideOr3~0 .lut_mask = 64'h2C2C2C2C43434343;
+defparam \h0|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N9
+cyclonev_lcell_comb \h0|WideOr2~0 (
+// Equation(s):
+// \h0|WideOr2~0_combout  = ( \bcd|A29|WideOr3~0_combout  & ( (!\bcd|A29|WideOr1~0_combout  & \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ) ) ) # ( !\bcd|A29|WideOr3~0_combout  & ( (!\bcd|A29|WideOr2~0_combout  & 
+// ((\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) # (\bcd|A29|WideOr2~0_combout  & (!\bcd|A29|WideOr1~0_combout )) ) )
+
+	.dataa(!\bcd|A29|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A29|WideOr2~0_combout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr2~0 .extended_lut = "off";
+defparam \h0|WideOr2~0 .lut_mask = 64'h0AFA0AFA00AA00AA;
+defparam \h0|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N24
+cyclonev_lcell_comb \h0|WideOr1~0 (
+// Equation(s):
+// \h0|WideOr1~0_combout  = ( \bcd|A29|WideOr3~0_combout  & ( (!\bcd|A29|WideOr1~0_combout  & ((!\bcd|A29|WideOr2~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) ) ) # ( !\bcd|A29|WideOr3~0_combout  & ( 
+// (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  & (!\bcd|A29|WideOr1~0_combout  $ (\bcd|A29|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A29|WideOr1~0_combout ),
+	.datab(!\bcd|A29|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr1~0 .extended_lut = "off";
+defparam \h0|WideOr1~0 .lut_mask = 64'h090909098A8A8A8A;
+defparam \h0|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N27
+cyclonev_lcell_comb \h0|WideOr0~0 (
+// Equation(s):
+// \h0|WideOr0~0_combout  = ( \bcd|A29|WideOr3~0_combout  & ( ((!\bcd|A29|WideOr2~0_combout ) # (!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout )) # (\bcd|A29|WideOr1~0_combout ) ) ) # ( !\bcd|A29|WideOr3~0_combout  & ( 
+// (!\bcd|A29|WideOr1~0_combout  & (\bcd|A29|WideOr2~0_combout )) # (\bcd|A29|WideOr1~0_combout  & ((!\bcd|A29|WideOr2~0_combout ) # (\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ))) ) )
+
+	.dataa(!\bcd|A29|WideOr1~0_combout ),
+	.datab(!\bcd|A29|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A29|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h0|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h0|WideOr0~0 .extended_lut = "off";
+defparam \h0|WideOr0~0 .lut_mask = 64'h67676767FDFDFDFD;
+defparam \h0|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N33
+cyclonev_lcell_comb \bcd|A25|WideOr0~0 (
+// Equation(s):
+// \bcd|A25|WideOr0~0_combout  = ( \bcd|A21|WideOr2~0_combout  & ( !\bcd|A21|WideOr1~0_combout  $ (((!\bcd|A21|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ))) ) ) # ( 
+// !\bcd|A21|WideOr2~0_combout  & ( \bcd|A21|WideOr1~0_combout  ) )
+
+	.dataa(!\bcd|A21|WideOr3~0_combout ),
+	.datab(!\bcd|A21|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A21|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A25|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A25|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A25|WideOr0~0 .lut_mask = 64'h3333333366CC66CC;
+defparam \bcd|A25|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N9
+cyclonev_lcell_comb \bcd|A17|WideOr0~0 (
+// Equation(s):
+// \bcd|A17|WideOr0~0_combout  = ( \bcd|A14|WideOr2~0_combout  & ( !\bcd|A14|WideOr1~0_combout  $ (((!\bcd|A14|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ))) ) ) # ( 
+// !\bcd|A14|WideOr2~0_combout  & ( \bcd|A14|WideOr1~0_combout  ) )
+
+	.dataa(!\bcd|A14|WideOr1~0_combout ),
+	.datab(!\bcd|A14|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A14|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A17|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A17|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A17|WideOr0~0 .lut_mask = 64'h5555555566AA66AA;
+defparam \bcd|A17|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N24
+cyclonev_lcell_comb \bcd|A14|WideOr0~0 (
+// Equation(s):
+// \bcd|A14|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr2~0_combout  $ (!\bcd|A11|WideOr1~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\bcd|A11|WideOr1~0_combout  $ (((!\bcd|A11|WideOr3~0_combout ) # (!\bcd|A11|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A11|WideOr3~0_combout ),
+	.datab(!\bcd|A11|WideOr2~0_combout ),
+	.datac(!\bcd|A11|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A14|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A14|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A14|WideOr0~0 .lut_mask = 64'h1E1E1E1E3C3C3C3C;
+defparam \bcd|A14|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N48
+cyclonev_lcell_comb \bcd|A7|WideOr2~0 (
+// Equation(s):
+// \bcd|A7|WideOr2~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) # 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout )))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )))) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout )) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) ) ) ) # ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ))) ) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A7|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A7|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A7|WideOr2~0 .lut_mask = 64'h330044CC04CCCCB3;
+defparam \bcd|A7|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N42
+cyclonev_lcell_comb \bcd|A7|WideOr3~0 (
+// Equation(s):
+// \bcd|A7|WideOr3~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) # ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ))) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ) # (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout )))) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) ) ) ) # ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )))) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout )))) ) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout )))) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// (((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )))) ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A7|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A7|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A7|WideOr3~0 .lut_mask = 64'h334C8815C801FF80;
+defparam \bcd|A7|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N24
+cyclonev_lcell_comb \bcd|A8|WideOr0~0 (
+// Equation(s):
+// \bcd|A8|WideOr0~0_combout  = ( \bcd|A6|WideOr3~0_combout  & ( !\bcd|A6|WideOr1~0_combout  $ (!\bcd|A6|WideOr2~0_combout ) ) ) # ( !\bcd|A6|WideOr3~0_combout  & ( !\bcd|A6|WideOr1~0_combout  $ (((!\bcd|A6|WideOr2~0_combout ) # 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) ) )
+
+	.dataa(!\bcd|A6|WideOr1~0_combout ),
+	.datab(!\bcd|A6|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A6|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A8|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A8|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A8|WideOr0~0 .lut_mask = 64'h5566556666666666;
+defparam \bcd|A8|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N54
+cyclonev_lcell_comb \bcd|A7|WideOr1~0 (
+// Equation(s):
+// \bcd|A7|WideOr1~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout )))) ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) ) ) ) # ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) ) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A7|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A7|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A7|WideOr1~0 .lut_mask = 64'h003320002200004C;
+defparam \bcd|A7|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N0
+cyclonev_lcell_comb \bcd|A10|WideOr2~0 (
+// Equation(s):
+// \bcd|A10|WideOr2~0_combout  = ( \bcd|A8|WideOr0~0_combout  & ( \bcd|A7|WideOr1~0_combout  & ( (!\bcd|A7|WideOr2~0_combout  & \bcd|A7|WideOr3~0_combout ) ) ) ) # ( !\bcd|A8|WideOr0~0_combout  & ( \bcd|A7|WideOr1~0_combout  & ( !\bcd|A7|WideOr3~0_combout  ) 
+// ) ) # ( \bcd|A8|WideOr0~0_combout  & ( !\bcd|A7|WideOr1~0_combout  & ( \bcd|A7|WideOr3~0_combout  ) ) ) # ( !\bcd|A8|WideOr0~0_combout  & ( !\bcd|A7|WideOr1~0_combout  & ( (!\bcd|A7|WideOr2~0_combout  & \bcd|A7|WideOr3~0_combout ) ) ) )
+
+	.dataa(!\bcd|A7|WideOr2~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A7|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A8|WideOr0~0_combout ),
+	.dataf(!\bcd|A7|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A10|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A10|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A10|WideOr2~0 .lut_mask = 64'h0A0A0F0FF0F00A0A;
+defparam \bcd|A10|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N36
+cyclonev_lcell_comb \bcd|A11|WideOr0~0 (
+// Equation(s):
+// \bcd|A11|WideOr0~0_combout  = ( \bcd|A8|WideOr1~0_combout  & ( (!\bcd|A8|WideOr2~0_combout ) # ((!\bcd|A8|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) ) # ( 
+// !\bcd|A8|WideOr1~0_combout  & ( (\bcd|A8|WideOr2~0_combout  & ((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ) # (\bcd|A8|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A8|WideOr3~0_combout ),
+	.datab(!\bcd|A8|WideOr2~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A8|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A11|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A11|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A11|WideOr0~0 .lut_mask = 64'h13131313ECECECEC;
+defparam \bcd|A11|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N18
+cyclonev_lcell_comb \bcd|A10|WideOr1~0 (
+// Equation(s):
+// \bcd|A10|WideOr1~0_combout  = ( \bcd|A7|WideOr2~0_combout  & ( (!\bcd|A8|WideOr0~0_combout  & !\bcd|A7|WideOr3~0_combout ) ) ) # ( !\bcd|A7|WideOr2~0_combout  & ( (\bcd|A7|WideOr1~0_combout  & ((\bcd|A7|WideOr3~0_combout ) # (\bcd|A8|WideOr0~0_combout ))) 
+// ) )
+
+	.dataa(!\bcd|A7|WideOr1~0_combout ),
+	.datab(!\bcd|A8|WideOr0~0_combout ),
+	.datac(!\bcd|A7|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A7|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A10|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A10|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A10|WideOr1~0 .lut_mask = 64'h15151515C0C0C0C0;
+defparam \bcd|A10|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N21
+cyclonev_lcell_comb \bcd|A10|WideOr3~0 (
+// Equation(s):
+// \bcd|A10|WideOr3~0_combout  = ( \bcd|A7|WideOr2~0_combout  & ( (!\bcd|A8|WideOr0~0_combout  & (!\bcd|A7|WideOr1~0_combout  $ (!\bcd|A7|WideOr3~0_combout ))) ) ) # ( !\bcd|A7|WideOr2~0_combout  & ( !\bcd|A7|WideOr1~0_combout  $ (!\bcd|A8|WideOr0~0_combout 
+// ) ) )
+
+	.dataa(!\bcd|A7|WideOr1~0_combout ),
+	.datab(!\bcd|A8|WideOr0~0_combout ),
+	.datac(!\bcd|A7|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A7|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A10|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A10|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A10|WideOr3~0 .lut_mask = 64'h6666666648484848;
+defparam \bcd|A10|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N21
+cyclonev_lcell_comb \bcd|A13|WideOr1~0 (
+// Equation(s):
+// \bcd|A13|WideOr1~0_combout  = ( \bcd|A10|WideOr1~0_combout  & ( \bcd|A10|WideOr3~0_combout  & ( !\bcd|A10|WideOr2~0_combout  ) ) ) # ( \bcd|A10|WideOr1~0_combout  & ( !\bcd|A10|WideOr3~0_combout  & ( !\bcd|A10|WideOr2~0_combout  $ 
+// (!\bcd|A11|WideOr0~0_combout ) ) ) ) # ( !\bcd|A10|WideOr1~0_combout  & ( !\bcd|A10|WideOr3~0_combout  & ( (\bcd|A10|WideOr2~0_combout  & !\bcd|A11|WideOr0~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A10|WideOr2~0_combout ),
+	.datac(!\bcd|A11|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A10|WideOr1~0_combout ),
+	.dataf(!\bcd|A10|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A13|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A13|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A13|WideOr1~0 .lut_mask = 64'h30303C3C0000CCCC;
+defparam \bcd|A13|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N51
+cyclonev_lcell_comb \bcd|A13|WideOr2~0 (
+// Equation(s):
+// \bcd|A13|WideOr2~0_combout  = ( \bcd|A11|WideOr0~0_combout  & ( (\bcd|A10|WideOr3~0_combout  & ((!\bcd|A10|WideOr2~0_combout ) # (!\bcd|A10|WideOr1~0_combout ))) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( (!\bcd|A10|WideOr3~0_combout  & 
+// ((\bcd|A10|WideOr1~0_combout ))) # (\bcd|A10|WideOr3~0_combout  & (!\bcd|A10|WideOr2~0_combout  & !\bcd|A10|WideOr1~0_combout )) ) )
+
+	.dataa(!\bcd|A10|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A10|WideOr2~0_combout ),
+	.datad(!\bcd|A10|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A11|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A13|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A13|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A13|WideOr2~0 .lut_mask = 64'h50AA50AA55505550;
+defparam \bcd|A13|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y10_N24
+cyclonev_lcell_comb \bcd|A13|WideOr3~0 (
+// Equation(s):
+// \bcd|A13|WideOr3~0_combout  = ( !\bcd|A10|WideOr1~0_combout  & ( \bcd|A11|WideOr0~0_combout  & ( !\bcd|A10|WideOr2~0_combout  ) ) ) # ( \bcd|A10|WideOr1~0_combout  & ( !\bcd|A11|WideOr0~0_combout  & ( (!\bcd|A10|WideOr2~0_combout ) # 
+// (!\bcd|A10|WideOr3~0_combout ) ) ) ) # ( !\bcd|A10|WideOr1~0_combout  & ( !\bcd|A11|WideOr0~0_combout  & ( (\bcd|A10|WideOr2~0_combout  & \bcd|A10|WideOr3~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A10|WideOr2~0_combout ),
+	.datac(!\bcd|A10|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A10|WideOr1~0_combout ),
+	.dataf(!\bcd|A11|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A13|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A13|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A13|WideOr3~0 .lut_mask = 64'h0303FCFCCCCC0000;
+defparam \bcd|A13|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N15
+cyclonev_lcell_comb \bcd|A16|WideOr1~0 (
+// Equation(s):
+// \bcd|A16|WideOr1~0_combout  = ( \bcd|A13|WideOr3~0_combout  & ( (\bcd|A13|WideOr1~0_combout  & !\bcd|A13|WideOr2~0_combout ) ) ) # ( !\bcd|A13|WideOr3~0_combout  & ( (!\bcd|A14|WideOr0~0_combout  & ((\bcd|A13|WideOr2~0_combout ))) # 
+// (\bcd|A14|WideOr0~0_combout  & (\bcd|A13|WideOr1~0_combout  & !\bcd|A13|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A14|WideOr0~0_combout ),
+	.datab(!\bcd|A13|WideOr1~0_combout ),
+	.datac(!\bcd|A13|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A13|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A16|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A16|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A16|WideOr1~0 .lut_mask = 64'h1A1A1A1A30303030;
+defparam \bcd|A16|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N9
+cyclonev_lcell_comb \bcd|A16|WideOr3~0 (
+// Equation(s):
+// \bcd|A16|WideOr3~0_combout  = ( \bcd|A13|WideOr3~0_combout  & ( (!\bcd|A14|WideOr0~0_combout  & (!\bcd|A13|WideOr1~0_combout  $ (!\bcd|A13|WideOr2~0_combout ))) # (\bcd|A14|WideOr0~0_combout  & (!\bcd|A13|WideOr1~0_combout  & !\bcd|A13|WideOr2~0_combout 
+// )) ) ) # ( !\bcd|A13|WideOr3~0_combout  & ( (!\bcd|A14|WideOr0~0_combout  & (\bcd|A13|WideOr1~0_combout )) # (\bcd|A14|WideOr0~0_combout  & (!\bcd|A13|WideOr1~0_combout  & !\bcd|A13|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A14|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A13|WideOr1~0_combout ),
+	.datad(!\bcd|A13|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A13|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A16|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A16|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A16|WideOr3~0 .lut_mask = 64'h5A0A5A0A5AA05AA0;
+defparam \bcd|A16|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N12
+cyclonev_lcell_comb \bcd|A16|WideOr2~0 (
+// Equation(s):
+// \bcd|A16|WideOr2~0_combout  = ( \bcd|A13|WideOr3~0_combout  & ( (!\bcd|A14|WideOr0~0_combout  & (!\bcd|A13|WideOr1~0_combout  & !\bcd|A13|WideOr2~0_combout )) # (\bcd|A14|WideOr0~0_combout  & ((!\bcd|A13|WideOr1~0_combout ) # (!\bcd|A13|WideOr2~0_combout 
+// ))) ) ) # ( !\bcd|A13|WideOr3~0_combout  & ( (!\bcd|A14|WideOr0~0_combout  & \bcd|A13|WideOr1~0_combout ) ) )
+
+	.dataa(!\bcd|A14|WideOr0~0_combout ),
+	.datab(!\bcd|A13|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A13|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A13|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A16|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A16|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A16|WideOr2~0 .lut_mask = 64'h22222222DD44DD44;
+defparam \bcd|A16|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N54
+cyclonev_lcell_comb \bcd|A20|WideOr3~0 (
+// Equation(s):
+// \bcd|A20|WideOr3~0_combout  = ( \bcd|A16|WideOr2~0_combout  & ( (!\bcd|A17|WideOr0~0_combout  & (!\bcd|A16|WideOr1~0_combout  $ (!\bcd|A16|WideOr3~0_combout ))) ) ) # ( !\bcd|A16|WideOr2~0_combout  & ( !\bcd|A17|WideOr0~0_combout  $ 
+// (!\bcd|A16|WideOr1~0_combout ) ) )
+
+	.dataa(!\bcd|A17|WideOr0~0_combout ),
+	.datab(!\bcd|A16|WideOr1~0_combout ),
+	.datac(!\bcd|A16|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A16|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A20|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A20|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A20|WideOr3~0 .lut_mask = 64'h6666666628282828;
+defparam \bcd|A20|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N57
+cyclonev_lcell_comb \bcd|A20|WideOr2~0 (
+// Equation(s):
+// \bcd|A20|WideOr2~0_combout  = ( \bcd|A16|WideOr2~0_combout  & ( (!\bcd|A17|WideOr0~0_combout  & (\bcd|A16|WideOr1~0_combout  & !\bcd|A16|WideOr3~0_combout )) # (\bcd|A17|WideOr0~0_combout  & (!\bcd|A16|WideOr1~0_combout  & \bcd|A16|WideOr3~0_combout )) ) 
+// ) # ( !\bcd|A16|WideOr2~0_combout  & ( !\bcd|A16|WideOr3~0_combout  $ (((!\bcd|A16|WideOr1~0_combout ) # (\bcd|A17|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A17|WideOr0~0_combout ),
+	.datab(!\bcd|A16|WideOr1~0_combout ),
+	.datac(!\bcd|A16|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A16|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A20|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A20|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A20|WideOr2~0 .lut_mask = 64'h2D2D2D2D24242424;
+defparam \bcd|A20|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N21
+cyclonev_lcell_comb \bcd|A21|WideOr0~0 (
+// Equation(s):
+// \bcd|A21|WideOr0~0_combout  = ( \bcd|A17|WideOr2~0_combout  & ( !\bcd|A17|WideOr1~0_combout  $ (((!\bcd|A17|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ))) ) ) # ( 
+// !\bcd|A17|WideOr2~0_combout  & ( \bcd|A17|WideOr1~0_combout  ) )
+
+	.dataa(!\bcd|A17|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A17|WideOr3~0_combout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datae(gnd),
+	.dataf(!\bcd|A17|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A21|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A21|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A21|WideOr0~0 .lut_mask = 64'h555555555AAA5AAA;
+defparam \bcd|A21|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N6
+cyclonev_lcell_comb \bcd|A20|WideOr1~0 (
+// Equation(s):
+// \bcd|A20|WideOr1~0_combout  = ( \bcd|A16|WideOr1~0_combout  & ( !\bcd|A16|WideOr2~0_combout  $ (((!\bcd|A17|WideOr0~0_combout  & !\bcd|A16|WideOr3~0_combout ))) ) ) # ( !\bcd|A16|WideOr1~0_combout  & ( (\bcd|A16|WideOr2~0_combout  & 
+// (!\bcd|A17|WideOr0~0_combout  & !\bcd|A16|WideOr3~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A16|WideOr2~0_combout ),
+	.datac(!\bcd|A17|WideOr0~0_combout ),
+	.datad(!\bcd|A16|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A16|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A20|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A20|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A20|WideOr1~0 .lut_mask = 64'h300030003CCC3CCC;
+defparam \bcd|A20|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N42
+cyclonev_lcell_comb \bcd|A24|WideOr1~0 (
+// Equation(s):
+// \bcd|A24|WideOr1~0_combout  = ( \bcd|A20|WideOr1~0_combout  & ( !\bcd|A20|WideOr2~0_combout  $ (((!\bcd|A20|WideOr3~0_combout  & !\bcd|A21|WideOr0~0_combout ))) ) ) # ( !\bcd|A20|WideOr1~0_combout  & ( (!\bcd|A20|WideOr3~0_combout  & 
+// (\bcd|A20|WideOr2~0_combout  & !\bcd|A21|WideOr0~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A20|WideOr3~0_combout ),
+	.datac(!\bcd|A20|WideOr2~0_combout ),
+	.datad(!\bcd|A21|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A24|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A24|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A24|WideOr1~0 .lut_mask = 64'h0C000C003CF03CF0;
+defparam \bcd|A24|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N15
+cyclonev_lcell_comb \bcd|A24|WideOr2~0 (
+// Equation(s):
+// \bcd|A24|WideOr2~0_combout  = ( \bcd|A20|WideOr1~0_combout  & ( (!\bcd|A20|WideOr3~0_combout  & ((!\bcd|A21|WideOr0~0_combout ))) # (\bcd|A20|WideOr3~0_combout  & (!\bcd|A20|WideOr2~0_combout  & \bcd|A21|WideOr0~0_combout )) ) ) # ( 
+// !\bcd|A20|WideOr1~0_combout  & ( (\bcd|A20|WideOr3~0_combout  & ((!\bcd|A20|WideOr2~0_combout ) # (\bcd|A21|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A20|WideOr2~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A20|WideOr3~0_combout ),
+	.datad(!\bcd|A21|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A24|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A24|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A24|WideOr2~0 .lut_mask = 64'h0A0F0A0FF00AF00A;
+defparam \bcd|A24|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N12
+cyclonev_lcell_comb \bcd|A24|WideOr3~0 (
+// Equation(s):
+// \bcd|A24|WideOr3~0_combout  = ( \bcd|A20|WideOr1~0_combout  & ( (!\bcd|A21|WideOr0~0_combout  & ((!\bcd|A20|WideOr2~0_combout ) # (!\bcd|A20|WideOr3~0_combout ))) ) ) # ( !\bcd|A20|WideOr1~0_combout  & ( (!\bcd|A20|WideOr2~0_combout  & 
+// ((\bcd|A21|WideOr0~0_combout ))) # (\bcd|A20|WideOr2~0_combout  & (\bcd|A20|WideOr3~0_combout  & !\bcd|A21|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A20|WideOr2~0_combout ),
+	.datab(!\bcd|A20|WideOr3~0_combout ),
+	.datac(!\bcd|A21|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A24|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A24|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A24|WideOr3~0 .lut_mask = 64'h1A1A1A1AE0E0E0E0;
+defparam \bcd|A24|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N51
+cyclonev_lcell_comb \bcd|A28|WideOr3~0 (
+// Equation(s):
+// \bcd|A28|WideOr3~0_combout  = ( \bcd|A24|WideOr3~0_combout  & ( (!\bcd|A25|WideOr0~0_combout  & (!\bcd|A24|WideOr1~0_combout  $ (!\bcd|A24|WideOr2~0_combout ))) # (\bcd|A25|WideOr0~0_combout  & (!\bcd|A24|WideOr1~0_combout  & !\bcd|A24|WideOr2~0_combout 
+// )) ) ) # ( !\bcd|A24|WideOr3~0_combout  & ( (!\bcd|A25|WideOr0~0_combout  & (\bcd|A24|WideOr1~0_combout )) # (\bcd|A25|WideOr0~0_combout  & (!\bcd|A24|WideOr1~0_combout  & !\bcd|A24|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A25|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A24|WideOr1~0_combout ),
+	.datad(!\bcd|A24|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A28|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A28|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A28|WideOr3~0 .lut_mask = 64'h5A0A5A0A5AA05AA0;
+defparam \bcd|A28|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N18
+cyclonev_lcell_comb \bcd|A28|WideOr2~0 (
+// Equation(s):
+// \bcd|A28|WideOr2~0_combout  = ( \bcd|A24|WideOr3~0_combout  & ( (!\bcd|A25|WideOr0~0_combout  & (!\bcd|A24|WideOr1~0_combout  & !\bcd|A24|WideOr2~0_combout )) # (\bcd|A25|WideOr0~0_combout  & ((!\bcd|A24|WideOr1~0_combout ) # (!\bcd|A24|WideOr2~0_combout 
+// ))) ) ) # ( !\bcd|A24|WideOr3~0_combout  & ( (!\bcd|A25|WideOr0~0_combout  & \bcd|A24|WideOr1~0_combout ) ) )
+
+	.dataa(!\bcd|A25|WideOr0~0_combout ),
+	.datab(!\bcd|A24|WideOr1~0_combout ),
+	.datac(!\bcd|A24|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A28|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A28|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A28|WideOr2~0 .lut_mask = 64'h22222222D4D4D4D4;
+defparam \bcd|A28|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N57
+cyclonev_lcell_comb \bcd|A29|WideOr0~0 (
+// Equation(s):
+// \bcd|A29|WideOr0~0_combout  = ( \bcd|A25|WideOr2~0_combout  & ( !\bcd|A25|WideOr1~0_combout  $ (((!\bcd|A25|WideOr3~0_combout  & !\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ))) ) ) # ( !\bcd|A25|WideOr2~0_combout  & ( 
+// \bcd|A25|WideOr1~0_combout  ) )
+
+	.dataa(!\bcd|A25|WideOr3~0_combout ),
+	.datab(!\bcd|A25|WideOr1~0_combout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A25|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A29|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A29|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A29|WideOr0~0 .lut_mask = 64'h333333336C6C6C6C;
+defparam \bcd|A29|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N21
+cyclonev_lcell_comb \bcd|A28|WideOr1~0 (
+// Equation(s):
+// \bcd|A28|WideOr1~0_combout  = ( \bcd|A24|WideOr3~0_combout  & ( (\bcd|A24|WideOr1~0_combout  & !\bcd|A24|WideOr2~0_combout ) ) ) # ( !\bcd|A24|WideOr3~0_combout  & ( (!\bcd|A25|WideOr0~0_combout  & ((\bcd|A24|WideOr2~0_combout ))) # 
+// (\bcd|A25|WideOr0~0_combout  & (\bcd|A24|WideOr1~0_combout  & !\bcd|A24|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A25|WideOr0~0_combout ),
+	.datab(!\bcd|A24|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A24|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A28|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A28|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A28|WideOr1~0 .lut_mask = 64'h11AA11AA33003300;
+defparam \bcd|A28|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N48
+cyclonev_lcell_comb \h1|WideOr6~0 (
+// Equation(s):
+// \h1|WideOr6~0_combout  = ( \bcd|A28|WideOr1~0_combout  & ( (!\bcd|A29|WideOr0~0_combout ) # (!\bcd|A28|WideOr3~0_combout  $ (\bcd|A28|WideOr2~0_combout )) ) ) # ( !\bcd|A28|WideOr1~0_combout  & ( (!\bcd|A28|WideOr2~0_combout  $ (\bcd|A29|WideOr0~0_combout 
+// )) # (\bcd|A28|WideOr3~0_combout ) ) )
+
+	.dataa(!\bcd|A28|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr2~0_combout ),
+	.datac(!\bcd|A29|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr6~0 .extended_lut = "off";
+defparam \h1|WideOr6~0 .lut_mask = 64'hD7D7D7D7F9F9F9F9;
+defparam \h1|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N51
+cyclonev_lcell_comb \h1|WideOr5~0 (
+// Equation(s):
+// \h1|WideOr5~0_combout  = (!\bcd|A28|WideOr3~0_combout  & (\bcd|A28|WideOr2~0_combout  & (!\bcd|A28|WideOr1~0_combout  $ (!\bcd|A29|WideOr0~0_combout )))) # (\bcd|A28|WideOr3~0_combout  & ((!\bcd|A29|WideOr0~0_combout  & (\bcd|A28|WideOr2~0_combout )) # 
+// (\bcd|A29|WideOr0~0_combout  & ((\bcd|A28|WideOr1~0_combout )))))
+
+	.dataa(!\bcd|A28|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr2~0_combout ),
+	.datac(!\bcd|A28|WideOr1~0_combout ),
+	.datad(!\bcd|A29|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr5~0 .extended_lut = "off";
+defparam \h1|WideOr5~0 .lut_mask = 64'h1325132513251325;
+defparam \h1|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N42
+cyclonev_lcell_comb \h1|WideOr4~0 (
+// Equation(s):
+// \h1|WideOr4~0_combout  = ( \bcd|A28|WideOr1~0_combout  & ( (\bcd|A28|WideOr2~0_combout  & ((!\bcd|A29|WideOr0~0_combout ) # (\bcd|A28|WideOr3~0_combout ))) ) ) # ( !\bcd|A28|WideOr1~0_combout  & ( (\bcd|A28|WideOr3~0_combout  & 
+// (!\bcd|A28|WideOr2~0_combout  & !\bcd|A29|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A28|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr2~0_combout ),
+	.datac(!\bcd|A29|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr4~0 .extended_lut = "off";
+defparam \h1|WideOr4~0 .lut_mask = 64'h4040404031313131;
+defparam \h1|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N45
+cyclonev_lcell_comb \h1|WideOr3~0 (
+// Equation(s):
+// \h1|WideOr3~0_combout  = (!\bcd|A29|WideOr0~0_combout  & ((!\bcd|A28|WideOr3~0_combout  & ((!\bcd|A28|WideOr2~0_combout ) # (\bcd|A28|WideOr1~0_combout ))) # (\bcd|A28|WideOr3~0_combout  & ((!\bcd|A28|WideOr1~0_combout ) # (\bcd|A28|WideOr2~0_combout 
+// ))))) # (\bcd|A29|WideOr0~0_combout  & (!\bcd|A28|WideOr3~0_combout  $ ((!\bcd|A28|WideOr2~0_combout ))))
+
+	.dataa(!\bcd|A28|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr2~0_combout ),
+	.datac(!\bcd|A28|WideOr1~0_combout ),
+	.datad(!\bcd|A29|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr3~0 .extended_lut = "off";
+defparam \h1|WideOr3~0 .lut_mask = 64'hDB66DB66DB66DB66;
+defparam \h1|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N36
+cyclonev_lcell_comb \h1|WideOr2~0 (
+// Equation(s):
+// \h1|WideOr2~0_combout  = ( \bcd|A28|WideOr1~0_combout  & ( ((!\bcd|A29|WideOr0~0_combout ) # (\bcd|A28|WideOr2~0_combout )) # (\bcd|A28|WideOr3~0_combout ) ) ) # ( !\bcd|A28|WideOr1~0_combout  & ( (!\bcd|A29|WideOr0~0_combout  & 
+// ((!\bcd|A28|WideOr2~0_combout ) # (\bcd|A28|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A28|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr2~0_combout ),
+	.datac(!\bcd|A29|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr2~0 .extended_lut = "off";
+defparam \h1|WideOr2~0 .lut_mask = 64'hD0D0D0D0F7F7F7F7;
+defparam \h1|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N39
+cyclonev_lcell_comb \h1|WideOr1~0 (
+// Equation(s):
+// \h1|WideOr1~0_combout  = (!\bcd|A28|WideOr3~0_combout  & ((!\bcd|A29|WideOr0~0_combout ) # (!\bcd|A28|WideOr2~0_combout  $ (!\bcd|A28|WideOr1~0_combout )))) # (\bcd|A28|WideOr3~0_combout  & (((\bcd|A28|WideOr2~0_combout  & !\bcd|A29|WideOr0~0_combout )) # 
+// (\bcd|A28|WideOr1~0_combout )))
+
+	.dataa(!\bcd|A28|WideOr3~0_combout ),
+	.datab(!\bcd|A28|WideOr2~0_combout ),
+	.datac(!\bcd|A28|WideOr1~0_combout ),
+	.datad(!\bcd|A29|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr1~0 .extended_lut = "off";
+defparam \h1|WideOr1~0 .lut_mask = 64'hBF2DBF2DBF2DBF2D;
+defparam \h1|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N18
+cyclonev_lcell_comb \h1|WideOr0~0 (
+// Equation(s):
+// \h1|WideOr0~0_combout  = ( \bcd|A28|WideOr1~0_combout  & ( ((!\bcd|A28|WideOr2~0_combout ) # (\bcd|A28|WideOr3~0_combout )) # (\bcd|A29|WideOr0~0_combout ) ) ) # ( !\bcd|A28|WideOr1~0_combout  & ( (!\bcd|A28|WideOr3~0_combout  & 
+// ((\bcd|A28|WideOr2~0_combout ))) # (\bcd|A28|WideOr3~0_combout  & ((!\bcd|A29|WideOr0~0_combout ) # (!\bcd|A28|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A29|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A28|WideOr3~0_combout ),
+	.datad(!\bcd|A28|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A28|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h1|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h1|WideOr0~0 .extended_lut = "off";
+defparam \h1|WideOr0~0 .lut_mask = 64'h0FFA0FFAFF5FFF5F;
+defparam \h1|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N12
+cyclonev_lcell_comb \bcd|A6|WideOr0~0 (
+// Equation(s):
+// \bcd|A6|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( !\bcd|A4|WideOr2~0_combout  $ (!\bcd|A4|WideOr1~0_combout ) ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( !\bcd|A4|WideOr1~0_combout  $ (((!\bcd|A4|WideOr2~0_combout ) # (!\bcd|A4|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A4|WideOr2~0_combout ),
+	.datab(!\bcd|A4|WideOr1~0_combout ),
+	.datac(!\bcd|A4|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A6|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A6|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A6|WideOr0~0 .lut_mask = 64'h3636363666666666;
+defparam \bcd|A6|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y8_N3
+cyclonev_lcell_comb \bcd|A1|WideOr0~0 (
+// Equation(s):
+// \bcd|A1|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  ) ) # ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A1|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A1|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A1|WideOr0~0 .lut_mask = 64'h000000005555FFFF;
+defparam \bcd|A1|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N48
+cyclonev_lcell_comb \bcd|A2|WideOr0~0 (
+// Equation(s):
+// \bcd|A2|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ))) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & ( 
+// (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(gnd),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A2|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A2|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A2|WideOr0~0 .lut_mask = 64'h0C0C0C0C30F330F3;
+defparam \bcd|A2|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y8_N0
+cyclonev_lcell_comb \bcd|A4|WideOr0~0 (
+// Equation(s):
+// \bcd|A4|WideOr0~0_combout  = ( \bcd|A2|WideOr2~0_combout  & ( !\bcd|A2|WideOr1~0_combout  $ (((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\bcd|A2|WideOr3~0_combout ))) ) ) # ( 
+// !\bcd|A2|WideOr2~0_combout  & ( \bcd|A2|WideOr1~0_combout  ) )
+
+	.dataa(!\bcd|A2|WideOr1~0_combout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datac(!\bcd|A2|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A2|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A4|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A4|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A4|WideOr0~0 .lut_mask = 64'h555555556A6A6A6A;
+defparam \bcd|A4|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N6
+cyclonev_lcell_comb \bcd|A15|WideOr1~0 (
+// Equation(s):
+// \bcd|A15|WideOr1~0_combout  = ( \bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A6|WideOr0~0_combout  & (!\bcd|A11|WideOr0~0_combout  & (!\bcd|A8|WideOr0~0_combout  & !\bcd|A1|WideOr0~0_combout ))) ) ) ) # ( !\bcd|A2|WideOr0~0_combout 
+//  & ( \bcd|A4|WideOr0~0_combout  & ( (\bcd|A6|WideOr0~0_combout  & (\bcd|A1|WideOr0~0_combout  & ((\bcd|A8|WideOr0~0_combout ) # (\bcd|A11|WideOr0~0_combout )))) ) ) ) # ( \bcd|A2|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( 
+// (!\bcd|A6|WideOr0~0_combout  & (!\bcd|A8|WideOr0~0_combout  & \bcd|A1|WideOr0~0_combout )) # (\bcd|A6|WideOr0~0_combout  & ((!\bcd|A1|WideOr0~0_combout ))) ) ) )
+
+	.dataa(!\bcd|A6|WideOr0~0_combout ),
+	.datab(!\bcd|A11|WideOr0~0_combout ),
+	.datac(!\bcd|A8|WideOr0~0_combout ),
+	.datad(!\bcd|A1|WideOr0~0_combout ),
+	.datae(!\bcd|A2|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A15|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A15|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A15|WideOr1~0 .lut_mask = 64'h000055A000158000;
+defparam \bcd|A15|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N3
+cyclonev_lcell_comb \bcd|A16|WideOr0~0 (
+// Equation(s):
+// \bcd|A16|WideOr0~0_combout  = ( \bcd|A13|WideOr1~0_combout  & ( (!\bcd|A13|WideOr2~0_combout ) # ((!\bcd|A14|WideOr0~0_combout  & !\bcd|A13|WideOr3~0_combout )) ) ) # ( !\bcd|A13|WideOr1~0_combout  & ( (\bcd|A13|WideOr2~0_combout  & 
+// ((\bcd|A13|WideOr3~0_combout ) # (\bcd|A14|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A14|WideOr0~0_combout ),
+	.datab(!\bcd|A13|WideOr3~0_combout ),
+	.datac(!\bcd|A13|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A13|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A16|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A16|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A16|WideOr0~0 .lut_mask = 64'h07070707F8F8F8F8;
+defparam \bcd|A16|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N54
+cyclonev_lcell_comb \bcd|A15|WideOr3~0 (
+// Equation(s):
+// \bcd|A15|WideOr3~0_combout  = ( \bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A6|WideOr0~0_combout  & ((\bcd|A1|WideOr0~0_combout ))) # (\bcd|A6|WideOr0~0_combout  & (\bcd|A8|WideOr0~0_combout  & !\bcd|A1|WideOr0~0_combout )) ) ) ) 
+// # ( !\bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A6|WideOr0~0_combout  & (((!\bcd|A8|WideOr0~0_combout ) # (\bcd|A1|WideOr0~0_combout )))) # (\bcd|A6|WideOr0~0_combout  & ((!\bcd|A11|WideOr0~0_combout  & 
+// (!\bcd|A8|WideOr0~0_combout  & \bcd|A1|WideOr0~0_combout )) # (\bcd|A11|WideOr0~0_combout  & (\bcd|A8|WideOr0~0_combout  & !\bcd|A1|WideOr0~0_combout )))) ) ) ) # ( \bcd|A2|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( (!\bcd|A6|WideOr0~0_combout 
+//  & (((!\bcd|A1|WideOr0~0_combout )))) # (\bcd|A6|WideOr0~0_combout  & (\bcd|A11|WideOr0~0_combout  & (\bcd|A8|WideOr0~0_combout  & \bcd|A1|WideOr0~0_combout ))) ) ) ) # ( !\bcd|A2|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( 
+// (!\bcd|A6|WideOr0~0_combout  & (\bcd|A1|WideOr0~0_combout  & ((!\bcd|A11|WideOr0~0_combout ) # (!\bcd|A8|WideOr0~0_combout )))) # (\bcd|A6|WideOr0~0_combout  & (!\bcd|A1|WideOr0~0_combout  & ((\bcd|A8|WideOr0~0_combout ) # (\bcd|A11|WideOr0~0_combout )))) 
+// ) ) )
+
+	.dataa(!\bcd|A6|WideOr0~0_combout ),
+	.datab(!\bcd|A11|WideOr0~0_combout ),
+	.datac(!\bcd|A8|WideOr0~0_combout ),
+	.datad(!\bcd|A1|WideOr0~0_combout ),
+	.datae(!\bcd|A2|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A15|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A15|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A15|WideOr3~0 .lut_mask = 64'h15A8AA01A1EA05AA;
+defparam \bcd|A15|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N24
+cyclonev_lcell_comb \bcd|A15|WideOr2~0 (
+// Equation(s):
+// \bcd|A15|WideOr2~0_combout  = ( \bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (\bcd|A6|WideOr0~0_combout  & \bcd|A1|WideOr0~0_combout ) ) ) ) # ( !\bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A6|WideOr0~0_combout  & 
+// (((\bcd|A1|WideOr0~0_combout ) # (\bcd|A8|WideOr0~0_combout )))) # (\bcd|A6|WideOr0~0_combout  & ((!\bcd|A1|WideOr0~0_combout ) # ((!\bcd|A11|WideOr0~0_combout  & !\bcd|A8|WideOr0~0_combout )))) ) ) ) # ( \bcd|A2|WideOr0~0_combout  & ( 
+// !\bcd|A4|WideOr0~0_combout  & ( (!\bcd|A6|WideOr0~0_combout  & !\bcd|A1|WideOr0~0_combout ) ) ) ) # ( !\bcd|A2|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( (\bcd|A1|WideOr0~0_combout  & (((\bcd|A11|WideOr0~0_combout  & \bcd|A8|WideOr0~0_combout 
+// )) # (\bcd|A6|WideOr0~0_combout ))) ) ) )
+
+	.dataa(!\bcd|A6|WideOr0~0_combout ),
+	.datab(!\bcd|A11|WideOr0~0_combout ),
+	.datac(!\bcd|A8|WideOr0~0_combout ),
+	.datad(!\bcd|A1|WideOr0~0_combout ),
+	.datae(!\bcd|A2|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A15|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A15|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A15|WideOr2~0 .lut_mask = 64'h0057AA005FEA0055;
+defparam \bcd|A15|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N48
+cyclonev_lcell_comb \bcd|A19|WideOr1~0 (
+// Equation(s):
+// \bcd|A19|WideOr1~0_combout  = ( \bcd|A15|WideOr2~0_combout  & ( (!\bcd|A16|WideOr0~0_combout  & !\bcd|A15|WideOr3~0_combout ) ) ) # ( !\bcd|A15|WideOr2~0_combout  & ( (\bcd|A15|WideOr1~0_combout  & ((\bcd|A15|WideOr3~0_combout ) # 
+// (\bcd|A16|WideOr0~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A15|WideOr1~0_combout ),
+	.datac(!\bcd|A16|WideOr0~0_combout ),
+	.datad(!\bcd|A15|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A15|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A19|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A19|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A19|WideOr1~0 .lut_mask = 64'h03330333F000F000;
+defparam \bcd|A19|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N21
+cyclonev_lcell_comb \bcd|A20|WideOr0~0 (
+// Equation(s):
+// \bcd|A20|WideOr0~0_combout  = ( \bcd|A16|WideOr3~0_combout  & ( !\bcd|A16|WideOr1~0_combout  $ (!\bcd|A16|WideOr2~0_combout ) ) ) # ( !\bcd|A16|WideOr3~0_combout  & ( !\bcd|A16|WideOr1~0_combout  $ (((!\bcd|A16|WideOr2~0_combout ) # 
+// (!\bcd|A17|WideOr0~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A16|WideOr1~0_combout ),
+	.datac(!\bcd|A16|WideOr2~0_combout ),
+	.datad(!\bcd|A17|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A16|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A20|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A20|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A20|WideOr0~0 .lut_mask = 64'h333C333C3C3C3C3C;
+defparam \bcd|A20|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N15
+cyclonev_lcell_comb \bcd|A19|WideOr2~0 (
+// Equation(s):
+// \bcd|A19|WideOr2~0_combout  = ( \bcd|A15|WideOr2~0_combout  & ( (!\bcd|A16|WideOr0~0_combout  & (\bcd|A15|WideOr1~0_combout  & !\bcd|A15|WideOr3~0_combout )) # (\bcd|A16|WideOr0~0_combout  & (!\bcd|A15|WideOr1~0_combout  & \bcd|A15|WideOr3~0_combout )) ) 
+// ) # ( !\bcd|A15|WideOr2~0_combout  & ( !\bcd|A15|WideOr3~0_combout  $ (((!\bcd|A15|WideOr1~0_combout ) # (\bcd|A16|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A16|WideOr0~0_combout ),
+	.datab(!\bcd|A15|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A15|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A15|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A19|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A19|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A19|WideOr2~0 .lut_mask = 64'h22DD22DD22442244;
+defparam \bcd|A19|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N12
+cyclonev_lcell_comb \bcd|A19|WideOr3~0 (
+// Equation(s):
+// \bcd|A19|WideOr3~0_combout  = ( \bcd|A15|WideOr2~0_combout  & ( (!\bcd|A16|WideOr0~0_combout  & (!\bcd|A15|WideOr1~0_combout  $ (!\bcd|A15|WideOr3~0_combout ))) ) ) # ( !\bcd|A15|WideOr2~0_combout  & ( !\bcd|A15|WideOr1~0_combout  $ 
+// (!\bcd|A16|WideOr0~0_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A15|WideOr1~0_combout ),
+	.datac(!\bcd|A16|WideOr0~0_combout ),
+	.datad(!\bcd|A15|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A15|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A19|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A19|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A19|WideOr3~0 .lut_mask = 64'h3C3C3C3C30C030C0;
+defparam \bcd|A19|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N30
+cyclonev_lcell_comb \bcd|A23|WideOr2~0 (
+// Equation(s):
+// \bcd|A23|WideOr2~0_combout  = ( \bcd|A19|WideOr3~0_combout  & ( (!\bcd|A19|WideOr1~0_combout  & ((!\bcd|A19|WideOr2~0_combout ) # (\bcd|A20|WideOr0~0_combout ))) # (\bcd|A19|WideOr1~0_combout  & (\bcd|A20|WideOr0~0_combout  & !\bcd|A19|WideOr2~0_combout 
+// )) ) ) # ( !\bcd|A19|WideOr3~0_combout  & ( (\bcd|A19|WideOr1~0_combout  & !\bcd|A20|WideOr0~0_combout ) ) )
+
+	.dataa(!\bcd|A19|WideOr1~0_combout ),
+	.datab(!\bcd|A20|WideOr0~0_combout ),
+	.datac(!\bcd|A19|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A23|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A23|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A23|WideOr2~0 .lut_mask = 64'h44444444B2B2B2B2;
+defparam \bcd|A23|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N3
+cyclonev_lcell_comb \bcd|A23|WideOr3~0 (
+// Equation(s):
+// \bcd|A23|WideOr3~0_combout  = ( \bcd|A19|WideOr3~0_combout  & ( (!\bcd|A19|WideOr1~0_combout  & (!\bcd|A20|WideOr0~0_combout  $ (!\bcd|A19|WideOr2~0_combout ))) # (\bcd|A19|WideOr1~0_combout  & (!\bcd|A20|WideOr0~0_combout  & !\bcd|A19|WideOr2~0_combout 
+// )) ) ) # ( !\bcd|A19|WideOr3~0_combout  & ( (!\bcd|A19|WideOr1~0_combout  & (\bcd|A20|WideOr0~0_combout  & !\bcd|A19|WideOr2~0_combout )) # (\bcd|A19|WideOr1~0_combout  & (!\bcd|A20|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A19|WideOr1~0_combout ),
+	.datab(!\bcd|A20|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A19|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A23|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A23|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A23|WideOr3~0 .lut_mask = 64'h6644664466886688;
+defparam \bcd|A23|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N33
+cyclonev_lcell_comb \bcd|A23|WideOr1~0 (
+// Equation(s):
+// \bcd|A23|WideOr1~0_combout  = ( \bcd|A19|WideOr3~0_combout  & ( (\bcd|A19|WideOr1~0_combout  & !\bcd|A19|WideOr2~0_combout ) ) ) # ( !\bcd|A19|WideOr3~0_combout  & ( (!\bcd|A20|WideOr0~0_combout  & ((\bcd|A19|WideOr2~0_combout ))) # 
+// (\bcd|A20|WideOr0~0_combout  & (\bcd|A19|WideOr1~0_combout  & !\bcd|A19|WideOr2~0_combout )) ) )
+
+	.dataa(!\bcd|A19|WideOr1~0_combout ),
+	.datab(!\bcd|A20|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A19|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A23|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A23|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A23|WideOr1~0 .lut_mask = 64'h11CC11CC55005500;
+defparam \bcd|A23|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y8_N45
+cyclonev_lcell_comb \bcd|A24|WideOr0~0 (
+// Equation(s):
+// \bcd|A24|WideOr0~0_combout  = ( \bcd|A20|WideOr1~0_combout  & ( (!\bcd|A20|WideOr2~0_combout ) # ((!\bcd|A20|WideOr3~0_combout  & !\bcd|A21|WideOr0~0_combout )) ) ) # ( !\bcd|A20|WideOr1~0_combout  & ( (\bcd|A20|WideOr2~0_combout  & 
+// ((\bcd|A21|WideOr0~0_combout ) # (\bcd|A20|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A20|WideOr2~0_combout ),
+	.datab(!\bcd|A20|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A21|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A24|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A24|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A24|WideOr0~0 .lut_mask = 64'h11551155EEAAEEAA;
+defparam \bcd|A24|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N0
+cyclonev_lcell_comb \bcd|A27|WideOr3~0 (
+// Equation(s):
+// \bcd|A27|WideOr3~0_combout  = ( \bcd|A24|WideOr0~0_combout  & ( (!\bcd|A23|WideOr2~0_combout  & !\bcd|A23|WideOr1~0_combout ) ) ) # ( !\bcd|A24|WideOr0~0_combout  & ( !\bcd|A23|WideOr1~0_combout  $ (((!\bcd|A23|WideOr2~0_combout ) # 
+// (!\bcd|A23|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A23|WideOr2~0_combout ),
+	.datab(!\bcd|A23|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A23|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A27|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A27|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A27|WideOr3~0 .lut_mask = 64'h11EE11EEAA00AA00;
+defparam \bcd|A27|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N48
+cyclonev_lcell_comb \bcd|A28|WideOr0~0 (
+// Equation(s):
+// \bcd|A28|WideOr0~0_combout  = ( \bcd|A24|WideOr3~0_combout  & ( !\bcd|A24|WideOr1~0_combout  $ (!\bcd|A24|WideOr2~0_combout ) ) ) # ( !\bcd|A24|WideOr3~0_combout  & ( !\bcd|A24|WideOr1~0_combout  $ (((!\bcd|A25|WideOr0~0_combout ) # 
+// (!\bcd|A24|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A25|WideOr0~0_combout ),
+	.datab(!\bcd|A24|WideOr1~0_combout ),
+	.datac(!\bcd|A24|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A28|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A28|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A28|WideOr0~0 .lut_mask = 64'h363636363C3C3C3C;
+defparam \bcd|A28|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N3
+cyclonev_lcell_comb \bcd|A27|WideOr2~0 (
+// Equation(s):
+// \bcd|A27|WideOr2~0_combout  = ( \bcd|A24|WideOr0~0_combout  & ( (\bcd|A23|WideOr3~0_combout  & ((!\bcd|A23|WideOr2~0_combout ) # (!\bcd|A23|WideOr1~0_combout ))) ) ) # ( !\bcd|A24|WideOr0~0_combout  & ( (!\bcd|A23|WideOr3~0_combout  & 
+// ((\bcd|A23|WideOr1~0_combout ))) # (\bcd|A23|WideOr3~0_combout  & (!\bcd|A23|WideOr2~0_combout  & !\bcd|A23|WideOr1~0_combout )) ) )
+
+	.dataa(!\bcd|A23|WideOr2~0_combout ),
+	.datab(!\bcd|A23|WideOr3~0_combout ),
+	.datac(!\bcd|A23|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A27|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A27|WideOr2~0 .extended_lut = "off";
+defparam \bcd|A27|WideOr2~0 .lut_mask = 64'h2C2C2C2C32323232;
+defparam \bcd|A27|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N30
+cyclonev_lcell_comb \bcd|A27|WideOr1~0 (
+// Equation(s):
+// \bcd|A27|WideOr1~0_combout  = ( \bcd|A24|WideOr0~0_combout  & ( (!\bcd|A23|WideOr2~0_combout  & \bcd|A23|WideOr1~0_combout ) ) ) # ( !\bcd|A24|WideOr0~0_combout  & ( (!\bcd|A23|WideOr3~0_combout  & (\bcd|A23|WideOr2~0_combout )) # 
+// (\bcd|A23|WideOr3~0_combout  & (!\bcd|A23|WideOr2~0_combout  & \bcd|A23|WideOr1~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A23|WideOr3~0_combout ),
+	.datac(!\bcd|A23|WideOr2~0_combout ),
+	.datad(!\bcd|A23|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A27|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A27|WideOr1~0 .extended_lut = "off";
+defparam \bcd|A27|WideOr1~0 .lut_mask = 64'h0C3C0C3C00F000F0;
+defparam \bcd|A27|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N33
+cyclonev_lcell_comb \h2|WideOr6~0 (
+// Equation(s):
+// \h2|WideOr6~0_combout  = ( \bcd|A27|WideOr1~0_combout  & ( (!\bcd|A28|WideOr0~0_combout ) # (!\bcd|A27|WideOr3~0_combout  $ (\bcd|A27|WideOr2~0_combout )) ) ) # ( !\bcd|A27|WideOr1~0_combout  & ( (!\bcd|A28|WideOr0~0_combout  $ (\bcd|A27|WideOr2~0_combout 
+// )) # (\bcd|A27|WideOr3~0_combout ) ) )
+
+	.dataa(!\bcd|A27|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A28|WideOr0~0_combout ),
+	.datad(!\bcd|A27|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr6~0 .extended_lut = "off";
+defparam \h2|WideOr6~0 .lut_mask = 64'hF55FF55FFAF5FAF5;
+defparam \h2|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N12
+cyclonev_lcell_comb \h2|WideOr5~0 (
+// Equation(s):
+// \h2|WideOr5~0_combout  = ( \bcd|A27|WideOr1~0_combout  & ( (!\bcd|A28|WideOr0~0_combout  & (\bcd|A27|WideOr2~0_combout )) # (\bcd|A28|WideOr0~0_combout  & ((\bcd|A27|WideOr3~0_combout ))) ) ) # ( !\bcd|A27|WideOr1~0_combout  & ( 
+// (\bcd|A27|WideOr2~0_combout  & (!\bcd|A28|WideOr0~0_combout  $ (!\bcd|A27|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A27|WideOr2~0_combout ),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(!\bcd|A27|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr5~0 .extended_lut = "off";
+defparam \h2|WideOr5~0 .lut_mask = 64'h1414141447474747;
+defparam \h2|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N15
+cyclonev_lcell_comb \h2|WideOr4~0 (
+// Equation(s):
+// \h2|WideOr4~0_combout  = ( \bcd|A27|WideOr1~0_combout  & ( (\bcd|A27|WideOr2~0_combout  & ((!\bcd|A28|WideOr0~0_combout ) # (\bcd|A27|WideOr3~0_combout ))) ) ) # ( !\bcd|A27|WideOr1~0_combout  & ( (!\bcd|A27|WideOr2~0_combout  & 
+// (!\bcd|A28|WideOr0~0_combout  & \bcd|A27|WideOr3~0_combout )) ) )
+
+	.dataa(!\bcd|A27|WideOr2~0_combout ),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A27|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr4~0 .extended_lut = "off";
+defparam \h2|WideOr4~0 .lut_mask = 64'h0088008844554455;
+defparam \h2|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N42
+cyclonev_lcell_comb \h2|WideOr3~0 (
+// Equation(s):
+// \h2|WideOr3~0_combout  = ( \bcd|A27|WideOr1~0_combout  & ( (!\bcd|A28|WideOr0~0_combout  & ((!\bcd|A27|WideOr3~0_combout ) # (\bcd|A27|WideOr2~0_combout ))) # (\bcd|A28|WideOr0~0_combout  & (!\bcd|A27|WideOr2~0_combout  $ (!\bcd|A27|WideOr3~0_combout ))) 
+// ) ) # ( !\bcd|A27|WideOr1~0_combout  & ( (!\bcd|A28|WideOr0~0_combout  & ((!\bcd|A27|WideOr2~0_combout ) # (\bcd|A27|WideOr3~0_combout ))) # (\bcd|A28|WideOr0~0_combout  & (!\bcd|A27|WideOr2~0_combout  $ (!\bcd|A27|WideOr3~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(!\bcd|A27|WideOr2~0_combout ),
+	.datad(!\bcd|A27|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr3~0 .extended_lut = "off";
+defparam \h2|WideOr3~0 .lut_mask = 64'hC3FCC3FCCF3CCF3C;
+defparam \h2|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N45
+cyclonev_lcell_comb \h2|WideOr2~0 (
+// Equation(s):
+// \h2|WideOr2~0_combout  = ( \bcd|A27|WideOr1~0_combout  & ( ((!\bcd|A28|WideOr0~0_combout ) # (\bcd|A27|WideOr3~0_combout )) # (\bcd|A27|WideOr2~0_combout ) ) ) # ( !\bcd|A27|WideOr1~0_combout  & ( (!\bcd|A28|WideOr0~0_combout  & 
+// ((!\bcd|A27|WideOr2~0_combout ) # (\bcd|A27|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A27|WideOr2~0_combout ),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A27|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr2~0 .extended_lut = "off";
+defparam \h2|WideOr2~0 .lut_mask = 64'h88CC88CCDDFFDDFF;
+defparam \h2|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N30
+cyclonev_lcell_comb \h2|WideOr1~0 (
+// Equation(s):
+// \h2|WideOr1~0_combout  = ( \bcd|A27|WideOr3~0_combout  & ( ((!\bcd|A28|WideOr0~0_combout  & \bcd|A27|WideOr2~0_combout )) # (\bcd|A27|WideOr1~0_combout ) ) ) # ( !\bcd|A27|WideOr3~0_combout  & ( (!\bcd|A28|WideOr0~0_combout ) # 
+// (!\bcd|A27|WideOr2~0_combout  $ (!\bcd|A27|WideOr1~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(!\bcd|A27|WideOr2~0_combout ),
+	.datad(!\bcd|A27|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr1~0 .extended_lut = "off";
+defparam \h2|WideOr1~0 .lut_mask = 64'hCFFCCFFC0CFF0CFF;
+defparam \h2|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y12_N33
+cyclonev_lcell_comb \h2|WideOr0~0 (
+// Equation(s):
+// \h2|WideOr0~0_combout  = ( \bcd|A27|WideOr3~0_combout  & ( (!\bcd|A27|WideOr2~0_combout ) # ((!\bcd|A28|WideOr0~0_combout ) # (\bcd|A27|WideOr1~0_combout )) ) ) # ( !\bcd|A27|WideOr3~0_combout  & ( (!\bcd|A27|WideOr2~0_combout  & 
+// ((\bcd|A27|WideOr1~0_combout ))) # (\bcd|A27|WideOr2~0_combout  & ((!\bcd|A27|WideOr1~0_combout ) # (\bcd|A28|WideOr0~0_combout ))) ) )
+
+	.dataa(!\bcd|A27|WideOr2~0_combout ),
+	.datab(!\bcd|A28|WideOr0~0_combout ),
+	.datac(!\bcd|A27|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h2|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h2|WideOr0~0 .extended_lut = "off";
+defparam \h2|WideOr0~0 .lut_mask = 64'h5B5B5B5BEFEFEFEF;
+defparam \h2|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N39
+cyclonev_lcell_comb \bcd|A27|WideOr0~0 (
+// Equation(s):
+// \bcd|A27|WideOr0~0_combout  = ( \bcd|A24|WideOr0~0_combout  & ( !\bcd|A23|WideOr2~0_combout  $ (!\bcd|A23|WideOr1~0_combout ) ) ) # ( !\bcd|A24|WideOr0~0_combout  & ( !\bcd|A23|WideOr1~0_combout  $ (((!\bcd|A23|WideOr2~0_combout ) # 
+// (!\bcd|A23|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A23|WideOr2~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A23|WideOr3~0_combout ),
+	.datad(!\bcd|A23|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A24|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A27|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A27|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A27|WideOr0~0 .lut_mask = 64'h05FA05FA55AA55AA;
+defparam \bcd|A27|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N0
+cyclonev_lcell_comb \bcd|A23|WideOr0~0 (
+// Equation(s):
+// \bcd|A23|WideOr0~0_combout  = ( \bcd|A19|WideOr3~0_combout  & ( !\bcd|A19|WideOr1~0_combout  $ (!\bcd|A19|WideOr2~0_combout ) ) ) # ( !\bcd|A19|WideOr3~0_combout  & ( !\bcd|A19|WideOr1~0_combout  $ (((!\bcd|A20|WideOr0~0_combout ) # 
+// (!\bcd|A19|WideOr2~0_combout ))) ) )
+
+	.dataa(!\bcd|A19|WideOr1~0_combout ),
+	.datab(!\bcd|A20|WideOr0~0_combout ),
+	.datac(!\bcd|A19|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A19|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A23|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A23|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A23|WideOr0~0 .lut_mask = 64'h565656565A5A5A5A;
+defparam \bcd|A23|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N45
+cyclonev_lcell_comb \bcd|A19|WideOr0~0 (
+// Equation(s):
+// \bcd|A19|WideOr0~0_combout  = ( \bcd|A15|WideOr2~0_combout  & ( !\bcd|A15|WideOr1~0_combout  $ (((!\bcd|A16|WideOr0~0_combout  & !\bcd|A15|WideOr3~0_combout ))) ) ) # ( !\bcd|A15|WideOr2~0_combout  & ( \bcd|A15|WideOr1~0_combout  ) )
+
+	.dataa(!\bcd|A16|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A15|WideOr1~0_combout ),
+	.datad(!\bcd|A15|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A15|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A19|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A19|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A19|WideOr0~0 .lut_mask = 64'h0F0F0F0F5AF05AF0;
+defparam \bcd|A19|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N0
+cyclonev_lcell_comb \bcd|A15|WideOr0~0 (
+// Equation(s):
+// \bcd|A15|WideOr0~0_combout  = ( \bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( (!\bcd|A1|WideOr0~0_combout  & (((\bcd|A8|WideOr0~0_combout ) # (\bcd|A11|WideOr0~0_combout )) # (\bcd|A6|WideOr0~0_combout ))) ) ) ) # ( 
+// !\bcd|A2|WideOr0~0_combout  & ( \bcd|A4|WideOr0~0_combout  & ( \bcd|A1|WideOr0~0_combout  ) ) ) # ( \bcd|A2|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( (!\bcd|A6|WideOr0~0_combout  & (!\bcd|A8|WideOr0~0_combout  & \bcd|A1|WideOr0~0_combout )) ) 
+// ) ) # ( !\bcd|A2|WideOr0~0_combout  & ( !\bcd|A4|WideOr0~0_combout  & ( \bcd|A1|WideOr0~0_combout  ) ) )
+
+	.dataa(!\bcd|A6|WideOr0~0_combout ),
+	.datab(!\bcd|A11|WideOr0~0_combout ),
+	.datac(!\bcd|A8|WideOr0~0_combout ),
+	.datad(!\bcd|A1|WideOr0~0_combout ),
+	.datae(!\bcd|A2|WideOr0~0_combout ),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A15|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A15|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A15|WideOr0~0 .lut_mask = 64'h00FF00A000FF7F00;
+defparam \bcd|A15|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X84_Y8_N54
+cyclonev_lcell_comb \bcd|A10|WideOr0~0 (
+// Equation(s):
+// \bcd|A10|WideOr0~0_combout  = ( \bcd|A8|WideOr0~0_combout  & ( \bcd|A7|WideOr1~0_combout  & ( !\bcd|A7|WideOr2~0_combout  ) ) ) # ( !\bcd|A8|WideOr0~0_combout  & ( \bcd|A7|WideOr1~0_combout  & ( (!\bcd|A7|WideOr2~0_combout ) # (!\bcd|A7|WideOr3~0_combout 
+// ) ) ) ) # ( \bcd|A8|WideOr0~0_combout  & ( !\bcd|A7|WideOr1~0_combout  & ( \bcd|A7|WideOr2~0_combout  ) ) ) # ( !\bcd|A8|WideOr0~0_combout  & ( !\bcd|A7|WideOr1~0_combout  & ( (\bcd|A7|WideOr2~0_combout  & \bcd|A7|WideOr3~0_combout ) ) ) )
+
+	.dataa(!\bcd|A7|WideOr2~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A7|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A8|WideOr0~0_combout ),
+	.dataf(!\bcd|A7|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A10|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A10|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A10|WideOr0~0 .lut_mask = 64'h05055555FAFAAAAA;
+defparam \bcd|A10|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y6_N36
+cyclonev_lcell_comb \bcd|A7|WideOr0~0 (
+// Equation(s):
+// \bcd|A7|WideOr0~0_combout  = ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  ) ) ) # ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( (!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ) # 
+// ((!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout )) ) ) ) # ( 
+// \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( !\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout  & ( 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout  & (((\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) # 
+// (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout )) # (\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ))) ) ) )
+
+	.dataa(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41_sumout ),
+	.datac(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.dataf(!\mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A7|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A7|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A7|WideOr0~0 .lut_mask = 64'h00001333EECCCCCC;
+defparam \bcd|A7|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N42
+cyclonev_lcell_comb \bcd|A5|WideOr0~0 (
+// Equation(s):
+// \bcd|A5|WideOr0~0_combout  = ( \bcd|A4|WideOr0~0_combout  & ( \bcd|A1|WideOr0~0_combout  ) ) # ( !\bcd|A4|WideOr0~0_combout  & ( (\bcd|A1|WideOr0~0_combout  & \bcd|A2|WideOr0~0_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A1|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\bcd|A2|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A4|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A5|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A5|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A5|WideOr0~0 .lut_mask = 64'h0033003333333333;
+defparam \bcd|A5|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N39
+cyclonev_lcell_comb \bcd|A12|WideOr0~0 (
+// Equation(s):
+// \bcd|A12|WideOr0~0_combout  = ( \bcd|A5|WideOr0~0_combout  & ( (\bcd|A7|WideOr0~0_combout ) # (\bcd|A10|WideOr0~0_combout ) ) )
+
+	.dataa(!\bcd|A10|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\bcd|A7|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A5|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A12|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A12|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A12|WideOr0~0 .lut_mask = 64'h000000005F5F5F5F;
+defparam \bcd|A12|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N51
+cyclonev_lcell_comb \bcd|A26|Decoder0~0 (
+// Equation(s):
+// \bcd|A26|Decoder0~0_combout  = ( \bcd|A12|WideOr0~0_combout  & ( (\bcd|A23|WideOr0~0_combout  & (!\bcd|A19|WideOr0~0_combout  & \bcd|A15|WideOr0~0_combout )) ) ) # ( !\bcd|A12|WideOr0~0_combout  & ( (\bcd|A23|WideOr0~0_combout  & 
+// (\bcd|A19|WideOr0~0_combout  & !\bcd|A15|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A23|WideOr0~0_combout ),
+	.datab(!\bcd|A19|WideOr0~0_combout ),
+	.datac(!\bcd|A15|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A12|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~0 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~0 .lut_mask = 64'h1010101004040404;
+defparam \bcd|A26|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N15
+cyclonev_lcell_comb \bcd|A26|Decoder0~2 (
+// Equation(s):
+// \bcd|A26|Decoder0~2_combout  = ( \bcd|A12|WideOr0~0_combout  & ( (!\bcd|A23|WideOr0~0_combout  & (!\bcd|A19|WideOr0~0_combout  & \bcd|A15|WideOr0~0_combout )) ) ) # ( !\bcd|A12|WideOr0~0_combout  & ( (!\bcd|A23|WideOr0~0_combout  & 
+// (\bcd|A19|WideOr0~0_combout  & !\bcd|A15|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A23|WideOr0~0_combout ),
+	.datab(!\bcd|A19|WideOr0~0_combout ),
+	.datac(!\bcd|A15|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A12|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~2 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~2 .lut_mask = 64'h2020202008080808;
+defparam \bcd|A26|Decoder0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N18
+cyclonev_lcell_comb \bcd|A26|WideOr2 (
+// Equation(s):
+// \bcd|A26|WideOr2~combout  = ( \bcd|A19|WideOr0~0_combout  & ( \bcd|A12|WideOr0~0_combout  & ( (!\bcd|A26|Decoder0~0_combout  & !\bcd|A26|Decoder0~2_combout ) ) ) ) # ( !\bcd|A19|WideOr0~0_combout  & ( \bcd|A12|WideOr0~0_combout  & ( 
+// (!\bcd|A26|Decoder0~0_combout  & (!\bcd|A26|Decoder0~2_combout  & ((\bcd|A23|WideOr0~0_combout ) # (\bcd|A15|WideOr0~0_combout )))) ) ) ) # ( \bcd|A19|WideOr0~0_combout  & ( !\bcd|A12|WideOr0~0_combout  & ( (!\bcd|A26|Decoder0~0_combout  & 
+// (!\bcd|A26|Decoder0~2_combout  & ((!\bcd|A15|WideOr0~0_combout ) # (!\bcd|A23|WideOr0~0_combout )))) ) ) ) # ( !\bcd|A19|WideOr0~0_combout  & ( !\bcd|A12|WideOr0~0_combout  & ( (!\bcd|A26|Decoder0~0_combout  & !\bcd|A26|Decoder0~2_combout ) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~0_combout ),
+	.datab(!\bcd|A15|WideOr0~0_combout ),
+	.datac(!\bcd|A23|WideOr0~0_combout ),
+	.datad(!\bcd|A26|Decoder0~2_combout ),
+	.datae(!\bcd|A19|WideOr0~0_combout ),
+	.dataf(!\bcd|A12|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|WideOr2~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|WideOr2 .extended_lut = "off";
+defparam \bcd|A26|WideOr2 .lut_mask = 64'hAA00A8002A00AA00;
+defparam \bcd|A26|WideOr2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N48
+cyclonev_lcell_comb \bcd|A26|Decoder0~1 (
+// Equation(s):
+// \bcd|A26|Decoder0~1_combout  = (\bcd|A23|WideOr0~0_combout  & (!\bcd|A15|WideOr0~0_combout  & (!\bcd|A19|WideOr0~0_combout  $ (\bcd|A12|WideOr0~0_combout ))))
+
+	.dataa(!\bcd|A23|WideOr0~0_combout ),
+	.datab(!\bcd|A19|WideOr0~0_combout ),
+	.datac(!\bcd|A12|WideOr0~0_combout ),
+	.datad(!\bcd|A15|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~1 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~1 .lut_mask = 64'h4100410041004100;
+defparam \bcd|A26|Decoder0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N6
+cyclonev_lcell_comb \bcd|A26|WideOr3~0 (
+// Equation(s):
+// \bcd|A26|WideOr3~0_combout  = ( \bcd|A23|WideOr0~0_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( !\bcd|A26|Decoder0~1_combout  ) ) ) # ( !\bcd|A23|WideOr0~0_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( (!\bcd|A26|Decoder0~1_combout  & 
+// ((!\bcd|A19|WideOr0~0_combout  & ((!\bcd|A12|WideOr0~0_combout ) # (\bcd|A15|WideOr0~0_combout ))) # (\bcd|A19|WideOr0~0_combout  & ((!\bcd|A15|WideOr0~0_combout ) # (\bcd|A12|WideOr0~0_combout ))))) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~1_combout ),
+	.datab(!\bcd|A19|WideOr0~0_combout ),
+	.datac(!\bcd|A12|WideOr0~0_combout ),
+	.datad(!\bcd|A15|WideOr0~0_combout ),
+	.datae(!\bcd|A23|WideOr0~0_combout ),
+	.dataf(!\bcd|A26|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|WideOr3~0 .extended_lut = "off";
+defparam \bcd|A26|WideOr3~0 .lut_mask = 64'hA28AAAAA00000000;
+defparam \bcd|A26|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N27
+cyclonev_lcell_comb \bcd|A26|Decoder0~3 (
+// Equation(s):
+// \bcd|A26|Decoder0~3_combout  = ( \bcd|A12|WideOr0~0_combout  & ( (!\bcd|A23|WideOr0~0_combout  & (\bcd|A19|WideOr0~0_combout  & \bcd|A15|WideOr0~0_combout )) ) ) # ( !\bcd|A12|WideOr0~0_combout  & ( (!\bcd|A23|WideOr0~0_combout  & 
+// (!\bcd|A19|WideOr0~0_combout  & \bcd|A15|WideOr0~0_combout )) ) )
+
+	.dataa(!\bcd|A23|WideOr0~0_combout ),
+	.datab(!\bcd|A19|WideOr0~0_combout ),
+	.datac(!\bcd|A15|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A12|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~3 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~3 .lut_mask = 64'h0808080802020202;
+defparam \bcd|A26|Decoder0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N24
+cyclonev_lcell_comb \bcd|A26|WideOr1 (
+// Equation(s):
+// \bcd|A26|WideOr1~combout  = ( \bcd|A12|WideOr0~0_combout  & ( (!\bcd|A26|Decoder0~3_combout  & ((!\bcd|A23|WideOr0~0_combout ) # ((\bcd|A15|WideOr0~0_combout ) # (\bcd|A19|WideOr0~0_combout )))) ) ) # ( !\bcd|A12|WideOr0~0_combout  & ( 
+// !\bcd|A26|Decoder0~3_combout  ) )
+
+	.dataa(!\bcd|A23|WideOr0~0_combout ),
+	.datab(!\bcd|A19|WideOr0~0_combout ),
+	.datac(!\bcd|A26|Decoder0~3_combout ),
+	.datad(!\bcd|A15|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A12|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|WideOr1~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|WideOr1 .extended_lut = "off";
+defparam \bcd|A26|WideOr1 .lut_mask = 64'hF0F0F0F0B0F0B0F0;
+defparam \bcd|A26|WideOr1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N9
+cyclonev_lcell_comb \h3|WideOr6~0 (
+// Equation(s):
+// \h3|WideOr6~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr3~0_combout ) # (!\bcd|A27|WideOr0~0_combout  $ (!\bcd|A26|WideOr2~combout )) ) ) # ( !\bcd|A26|WideOr1~combout  & ( (!\bcd|A27|WideOr0~0_combout ) # (!\bcd|A26|WideOr2~combout  $ 
+// (\bcd|A26|WideOr3~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr2~combout ),
+	.datad(!\bcd|A26|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr6~0 .extended_lut = "off";
+defparam \h3|WideOr6~0 .lut_mask = 64'hFCCFFCCFFF3CFF3C;
+defparam \h3|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N24
+cyclonev_lcell_comb \h3|WideOr5~0 (
+// Equation(s):
+// \h3|WideOr5~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  $ (\bcd|A26|WideOr3~0_combout ))) ) ) # ( !\bcd|A26|WideOr1~combout  & ( (!\bcd|A27|WideOr0~0_combout  & (!\bcd|A26|WideOr2~combout )) # 
+// (\bcd|A27|WideOr0~0_combout  & ((!\bcd|A26|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr5~0 .extended_lut = "off";
+defparam \h3|WideOr5~0 .lut_mask = 64'hB8B8B8B882828282;
+defparam \h3|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N27
+cyclonev_lcell_comb \h3|WideOr4~0 (
+// Equation(s):
+// \h3|WideOr4~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A27|WideOr0~0_combout  & (\bcd|A26|WideOr2~combout  & !\bcd|A26|WideOr3~0_combout )) ) ) # ( !\bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & ((!\bcd|A27|WideOr0~0_combout ) # 
+// (!\bcd|A26|WideOr3~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr2~combout ),
+	.datad(!\bcd|A26|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr4~0 .extended_lut = "off";
+defparam \h3|WideOr4~0 .lut_mask = 64'hF0C0F0C00C000C00;
+defparam \h3|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N54
+cyclonev_lcell_comb \h3|WideOr3~0 (
+// Equation(s):
+// \h3|WideOr3~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  $ (\bcd|A26|WideOr3~0_combout ))) # (\bcd|A26|WideOr2~combout  & ((!\bcd|A27|WideOr0~0_combout ) # (!\bcd|A26|WideOr3~0_combout ))) ) ) # 
+// ( !\bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & ((!\bcd|A27|WideOr0~0_combout ) # (\bcd|A26|WideOr3~0_combout ))) # (\bcd|A26|WideOr2~combout  & (!\bcd|A27|WideOr0~0_combout  $ (!\bcd|A26|WideOr3~0_combout ))) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr3~0 .extended_lut = "off";
+defparam \h3|WideOr3~0 .lut_mask = 64'h9E9E9E9ED6D6D6D6;
+defparam \h3|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N57
+cyclonev_lcell_comb \h3|WideOr2~0 (
+// Equation(s):
+// \h3|WideOr2~0_combout  = ( \bcd|A26|WideOr2~combout  & ( (!\bcd|A27|WideOr0~0_combout ) # ((!\bcd|A26|WideOr1~combout  & !\bcd|A26|WideOr3~0_combout )) ) ) # ( !\bcd|A26|WideOr2~combout  & ( (!\bcd|A26|WideOr1~combout ) # ((!\bcd|A27|WideOr0~0_combout  & 
+// !\bcd|A26|WideOr3~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr1~combout ),
+	.datad(!\bcd|A26|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr2~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr2~0 .extended_lut = "off";
+defparam \h3|WideOr2~0 .lut_mask = 64'hFCF0FCF0FCCCFCCC;
+defparam \h3|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N36
+cyclonev_lcell_comb \h3|WideOr1~0 (
+// Equation(s):
+// \h3|WideOr1~0_combout  = ( \bcd|A27|WideOr0~0_combout  & ( !\bcd|A26|WideOr1~combout  $ (((!\bcd|A26|WideOr2~combout  & \bcd|A26|WideOr3~0_combout ))) ) ) # ( !\bcd|A27|WideOr0~0_combout  & ( (!\bcd|A26|WideOr1~combout ) # ((!\bcd|A26|WideOr2~combout ) # 
+// (\bcd|A26|WideOr3~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A26|WideOr1~combout ),
+	.datac(!\bcd|A26|WideOr2~combout ),
+	.datad(!\bcd|A26|WideOr3~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A27|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr1~0 .extended_lut = "off";
+defparam \h3|WideOr1~0 .lut_mask = 64'hFCFFFCFFCC3CCC3C;
+defparam \h3|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y12_N6
+cyclonev_lcell_comb \h3|WideOr0~0 (
+// Equation(s):
+// \h3|WideOr0~0_combout  = ( \bcd|A26|WideOr1~combout  & ( (!\bcd|A26|WideOr2~combout  & ((!\bcd|A27|WideOr0~0_combout ) # (\bcd|A26|WideOr3~0_combout ))) # (\bcd|A26|WideOr2~combout  & ((!\bcd|A26|WideOr3~0_combout ))) ) ) # ( !\bcd|A26|WideOr1~combout  & 
+// ( ((!\bcd|A26|WideOr3~0_combout ) # (\bcd|A27|WideOr0~0_combout )) # (\bcd|A26|WideOr2~combout ) ) )
+
+	.dataa(!\bcd|A26|WideOr2~combout ),
+	.datab(!\bcd|A27|WideOr0~0_combout ),
+	.datac(!\bcd|A26|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\bcd|A26|WideOr1~combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h3|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h3|WideOr0~0 .extended_lut = "off";
+defparam \h3|WideOr0~0 .lut_mask = 64'hF7F7F7F7DADADADA;
+defparam \h3|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N12
+cyclonev_lcell_comb \bcd|A26|Decoder0~4 (
+// Equation(s):
+// \bcd|A26|Decoder0~4_combout  = (!\bcd|A23|WideOr0~0_combout  & (!\bcd|A15|WideOr0~0_combout  & (!\bcd|A19|WideOr0~0_combout  $ (\bcd|A12|WideOr0~0_combout ))))
+
+	.dataa(!\bcd|A23|WideOr0~0_combout ),
+	.datab(!\bcd|A19|WideOr0~0_combout ),
+	.datac(!\bcd|A12|WideOr0~0_combout ),
+	.datad(!\bcd|A15|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|Decoder0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|Decoder0~4 .extended_lut = "off";
+defparam \bcd|A26|Decoder0~4 .lut_mask = 64'h8200820082008200;
+defparam \bcd|A26|Decoder0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N33
+cyclonev_lcell_comb \bcd|A22|WideOr0~0 (
+// Equation(s):
+// \bcd|A22|WideOr0~0_combout  = ( \bcd|A12|WideOr0~0_combout  & ( (!\bcd|A19|WideOr0~0_combout  & !\bcd|A15|WideOr0~0_combout ) ) ) # ( !\bcd|A12|WideOr0~0_combout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\bcd|A19|WideOr0~0_combout ),
+	.datad(!\bcd|A15|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A12|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A22|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A22|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A22|WideOr0~0 .lut_mask = 64'hFFFFFFFFF000F000;
+defparam \bcd|A22|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N54
+cyclonev_lcell_comb \h4|Decoder0~0 (
+// Equation(s):
+// \h4|Decoder0~0_combout  = ( \bcd|A22|WideOr0~0_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( (!\bcd|A26|Decoder0~1_combout  & (!\bcd|A26|Decoder0~2_combout  & (!\bcd|A26|Decoder0~3_combout  & !\bcd|A26|Decoder0~4_combout ))) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~1_combout ),
+	.datab(!\bcd|A26|Decoder0~2_combout ),
+	.datac(!\bcd|A26|Decoder0~3_combout ),
+	.datad(!\bcd|A26|Decoder0~4_combout ),
+	.datae(!\bcd|A22|WideOr0~0_combout ),
+	.dataf(!\bcd|A26|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h4|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h4|Decoder0~0 .extended_lut = "off";
+defparam \h4|Decoder0~0 .lut_mask = 64'h0000800000000000;
+defparam \h4|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N36
+cyclonev_lcell_comb \bcd|A13|WideOr0~0 (
+// Equation(s):
+// \bcd|A13|WideOr0~0_combout  = ( \bcd|A11|WideOr0~0_combout  & ( !\bcd|A10|WideOr2~0_combout  $ (!\bcd|A10|WideOr1~0_combout ) ) ) # ( !\bcd|A11|WideOr0~0_combout  & ( !\bcd|A10|WideOr1~0_combout  $ (((!\bcd|A10|WideOr2~0_combout ) # 
+// (!\bcd|A10|WideOr3~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\bcd|A10|WideOr2~0_combout ),
+	.datac(!\bcd|A10|WideOr3~0_combout ),
+	.datad(!\bcd|A10|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A11|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A13|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A13|WideOr0~0 .extended_lut = "off";
+defparam \bcd|A13|WideOr0~0 .lut_mask = 64'h03FC03FC33CC33CC;
+defparam \bcd|A13|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N30
+cyclonev_lcell_comb \h4|Decoder0~2 (
+// Equation(s):
+// \h4|Decoder0~2_combout  = ( \bcd|A10|WideOr0~0_combout  & ( (\bcd|A5|WideOr0~0_combout  & \bcd|A7|WideOr0~0_combout ) ) ) # ( !\bcd|A10|WideOr0~0_combout  & ( (\bcd|A5|WideOr0~0_combout  & (\bcd|A7|WideOr0~0_combout  & ((\bcd|A13|WideOr0~0_combout ) # 
+// (\bcd|A16|WideOr0~0_combout )))) ) )
+
+	.dataa(!\bcd|A16|WideOr0~0_combout ),
+	.datab(!\bcd|A5|WideOr0~0_combout ),
+	.datac(!\bcd|A13|WideOr0~0_combout ),
+	.datad(!\bcd|A7|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\bcd|A10|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h4|Decoder0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h4|Decoder0~2 .extended_lut = "off";
+defparam \h4|Decoder0~2 .lut_mask = 64'h0013001300330033;
+defparam \h4|Decoder0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N36
+cyclonev_lcell_comb \bcd|A26|WideOr0 (
+// Equation(s):
+// \bcd|A26|WideOr0~combout  = ( \bcd|A26|Decoder0~3_combout  & ( \bcd|A26|Decoder0~2_combout  ) ) # ( !\bcd|A26|Decoder0~3_combout  & ( \bcd|A26|Decoder0~2_combout  ) ) # ( \bcd|A26|Decoder0~3_combout  & ( !\bcd|A26|Decoder0~2_combout  ) ) # ( 
+// !\bcd|A26|Decoder0~3_combout  & ( !\bcd|A26|Decoder0~2_combout  & ( ((\bcd|A26|Decoder0~0_combout ) # (\bcd|A26|Decoder0~4_combout )) # (\bcd|A26|Decoder0~1_combout ) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~1_combout ),
+	.datab(!\bcd|A26|Decoder0~4_combout ),
+	.datac(!\bcd|A26|Decoder0~0_combout ),
+	.datad(gnd),
+	.datae(!\bcd|A26|Decoder0~3_combout ),
+	.dataf(!\bcd|A26|Decoder0~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\bcd|A26|WideOr0~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \bcd|A26|WideOr0 .extended_lut = "off";
+defparam \bcd|A26|WideOr0 .lut_mask = 64'h7F7FFFFFFFFFFFFF;
+defparam \bcd|A26|WideOr0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X87_Y12_N42
+cyclonev_lcell_comb \h4|Decoder0~1 (
+// Equation(s):
+// \h4|Decoder0~1_combout  = ( \bcd|A22|WideOr0~0_combout  & ( \bcd|A26|Decoder0~0_combout  ) ) # ( \bcd|A22|WideOr0~0_combout  & ( !\bcd|A26|Decoder0~0_combout  & ( (((\bcd|A26|Decoder0~4_combout ) # (\bcd|A26|Decoder0~3_combout )) # 
+// (\bcd|A26|Decoder0~2_combout )) # (\bcd|A26|Decoder0~1_combout ) ) ) )
+
+	.dataa(!\bcd|A26|Decoder0~1_combout ),
+	.datab(!\bcd|A26|Decoder0~2_combout ),
+	.datac(!\bcd|A26|Decoder0~3_combout ),
+	.datad(!\bcd|A26|Decoder0~4_combout ),
+	.datae(!\bcd|A22|WideOr0~0_combout ),
+	.dataf(!\bcd|A26|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\h4|Decoder0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \h4|Decoder0~1 .extended_lut = "off";
+defparam \h4|Decoder0~1 .lut_mask = 64'h00007FFF0000FFFF;
+defparam \h4|Decoder0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X29_Y33_N3
+cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\~QUARTUS_CREATED_GND~I_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+endmodule
diff --git a/part_3/ex15/simulation/modelsim/ex10_modelsim.xrf b/part_3/ex15/simulation/modelsim/ex10_modelsim.xrf
new file mode 100755
index 0000000..e49c737
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/ex10_modelsim.xrf
@@ -0,0 +1,512 @@
+vendor_name = ModelSim
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2adc.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/ex15.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/add3_ge5.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/hex_to_7seg.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/bin2bcd_16.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.qip
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/ROM.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/tick_5000.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/spi2dac.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/verilog_files/pwm.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.qip
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/const_mult.v
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/add_offset.v
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/stratix_ram_block.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_mux.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_decode.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/a_rdenreg.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altrom.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altram.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altdpram.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/altsyncram_6ng1.tdf
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/rom_data/rom_data.mif
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/multcore.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/bypassff.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altshift.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/csa_add.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/muleabz.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mul_lfrg.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mul_boothc.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult_y.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/dffpipe.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/addcore.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/look_add.inc
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/add_sub_d9h.tdf
+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex15/db/add_sub_89h.tdf
+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altshift.tdf
+design_name = ex15
+instance = comp, \DAC_CS~output , DAC_CS~output, ex15, 1
+instance = comp, \DAC_SDI~output , DAC_SDI~output, ex15, 1
+instance = comp, \DAC_LD~output , DAC_LD~output, ex15, 1
+instance = comp, \DAC_SCK~output , DAC_SCK~output, ex15, 1
+instance = comp, \ADC_SDI~output , ADC_SDI~output, ex15, 1
+instance = comp, \ADC_SCK~output , ADC_SCK~output, ex15, 1
+instance = comp, \ADC_CS~output , ADC_CS~output, ex15, 1
+instance = comp, \PWM_OUT~output , PWM_OUT~output, ex15, 1
+instance = comp, \HEX0[0]~output , HEX0[0]~output, ex15, 1
+instance = comp, \HEX0[1]~output , HEX0[1]~output, ex15, 1
+instance = comp, \HEX0[2]~output , HEX0[2]~output, ex15, 1
+instance = comp, \HEX0[3]~output , HEX0[3]~output, ex15, 1
+instance = comp, \HEX0[4]~output , HEX0[4]~output, ex15, 1
+instance = comp, \HEX0[5]~output , HEX0[5]~output, ex15, 1
+instance = comp, \HEX0[6]~output , HEX0[6]~output, ex15, 1
+instance = comp, \HEX1[0]~output , HEX1[0]~output, ex15, 1
+instance = comp, \HEX1[1]~output , HEX1[1]~output, ex15, 1
+instance = comp, \HEX1[2]~output , HEX1[2]~output, ex15, 1
+instance = comp, \HEX1[3]~output , HEX1[3]~output, ex15, 1
+instance = comp, \HEX1[4]~output , HEX1[4]~output, ex15, 1
+instance = comp, \HEX1[5]~output , HEX1[5]~output, ex15, 1
+instance = comp, \HEX1[6]~output , HEX1[6]~output, ex15, 1
+instance = comp, \HEX2[0]~output , HEX2[0]~output, ex15, 1
+instance = comp, \HEX2[1]~output , HEX2[1]~output, ex15, 1
+instance = comp, \HEX2[2]~output , HEX2[2]~output, ex15, 1
+instance = comp, \HEX2[3]~output , HEX2[3]~output, ex15, 1
+instance = comp, \HEX2[4]~output , HEX2[4]~output, ex15, 1
+instance = comp, \HEX2[5]~output , HEX2[5]~output, ex15, 1
+instance = comp, \HEX2[6]~output , HEX2[6]~output, ex15, 1
+instance = comp, \HEX3[0]~output , HEX3[0]~output, ex15, 1
+instance = comp, \HEX3[1]~output , HEX3[1]~output, ex15, 1
+instance = comp, \HEX3[2]~output , HEX3[2]~output, ex15, 1
+instance = comp, \HEX3[3]~output , HEX3[3]~output, ex15, 1
+instance = comp, \HEX3[4]~output , HEX3[4]~output, ex15, 1
+instance = comp, \HEX3[5]~output , HEX3[5]~output, ex15, 1
+instance = comp, \HEX3[6]~output , HEX3[6]~output, ex15, 1
+instance = comp, \HEX4[0]~output , HEX4[0]~output, ex15, 1
+instance = comp, \HEX4[1]~output , HEX4[1]~output, ex15, 1
+instance = comp, \HEX4[2]~output , HEX4[2]~output, ex15, 1
+instance = comp, \HEX4[3]~output , HEX4[3]~output, ex15, 1
+instance = comp, \HEX4[4]~output , HEX4[4]~output, ex15, 1
+instance = comp, \HEX4[5]~output , HEX4[5]~output, ex15, 1
+instance = comp, \HEX4[6]~output , HEX4[6]~output, ex15, 1
+instance = comp, \CLOCK_50~input , CLOCK_50~input, ex15, 1
+instance = comp, \dac|clk_1MHz~0 , dac|clk_1MHz~0, ex15, 1
+instance = comp, \CLOCK_50~inputCLKENA0 , CLOCK_50~inputCLKENA0, ex15, 1
+instance = comp, \SPI_ADC|ctr[0] , SPI_ADC|ctr[0], ex15, 1
+instance = comp, \SPI_ADC|ctr~1 , SPI_ADC|ctr~1, ex15, 1
+instance = comp, \SPI_ADC|ctr[0]~DUPLICATE , SPI_ADC|ctr[0]~DUPLICATE, ex15, 1
+instance = comp, \SPI_ADC|ctr~2 , SPI_ADC|ctr~2, ex15, 1
+instance = comp, \SPI_ADC|ctr[1] , SPI_ADC|ctr[1], ex15, 1
+instance = comp, \SPI_ADC|ctr[1]~DUPLICATE , SPI_ADC|ctr[1]~DUPLICATE, ex15, 1
+instance = comp, \SPI_ADC|ctr[2] , SPI_ADC|ctr[2], ex15, 1
+instance = comp, \SPI_ADC|ctr~0 , SPI_ADC|ctr~0, ex15, 1
+instance = comp, \SPI_ADC|ctr[2]~DUPLICATE , SPI_ADC|ctr[2]~DUPLICATE, ex15, 1
+instance = comp, \SPI_ADC|Add0~1 , SPI_ADC|Add0~1, ex15, 1
+instance = comp, \SPI_ADC|ctr[3] , SPI_ADC|ctr[3], ex15, 1
+instance = comp, \SPI_ADC|Add0~0 , SPI_ADC|Add0~0, ex15, 1
+instance = comp, \SPI_ADC|ctr[4] , SPI_ADC|ctr[4], ex15, 1
+instance = comp, \dac|Equal0~0 , dac|Equal0~0, ex15, 1
+instance = comp, \dac|clk_1MHz , dac|clk_1MHz, ex15, 1
+instance = comp, \dac|state~2 , dac|state~2, ex15, 1
+instance = comp, \dac|state[2] , dac|state[2], ex15, 1
+instance = comp, \dac|state~3 , dac|state~3, ex15, 1
+instance = comp, \dac|state[3] , dac|state[3], ex15, 1
+instance = comp, \dac|state~0 , dac|state~0, ex15, 1
+instance = comp, \dac|state[4]~feeder , dac|state[4]~feeder, ex15, 1
+instance = comp, \dac|state[4]~DUPLICATE , dac|state[4]~DUPLICATE, ex15, 1
+instance = comp, \dac|state~1 , dac|state~1, ex15, 1
+instance = comp, \dac|state[1] , dac|state[1], ex15, 1
+instance = comp, \tick|count[9] , tick|count[9], ex15, 1
+instance = comp, \tick|Add0~9 , tick|Add0~9, ex15, 1
+instance = comp, \tick|count[0]~1 , tick|count[0]~1, ex15, 1
+instance = comp, \tick|count[0] , tick|count[0], ex15, 1
+instance = comp, \tick|Add0~13 , tick|Add0~13, ex15, 1
+instance = comp, \tick|count[1]~2 , tick|count[1]~2, ex15, 1
+instance = comp, \tick|count[1]~DUPLICATE , tick|count[1]~DUPLICATE, ex15, 1
+instance = comp, \tick|Add0~17 , tick|Add0~17, ex15, 1
+instance = comp, \tick|count[2]~3 , tick|count[2]~3, ex15, 1
+instance = comp, \tick|count[2]~DUPLICATE , tick|count[2]~DUPLICATE, ex15, 1
+instance = comp, \tick|Add0~33 , tick|Add0~33, ex15, 1
+instance = comp, \tick|count[3] , tick|count[3], ex15, 1
+instance = comp, \tick|Add0~37 , tick|Add0~37, ex15, 1
+instance = comp, \tick|count[4] , tick|count[4], ex15, 1
+instance = comp, \tick|Add0~41 , tick|Add0~41, ex15, 1
+instance = comp, \tick|count[5] , tick|count[5], ex15, 1
+instance = comp, \tick|Add0~45 , tick|Add0~45, ex15, 1
+instance = comp, \tick|count[6] , tick|count[6], ex15, 1
+instance = comp, \tick|Add0~21 , tick|Add0~21, ex15, 1
+instance = comp, \tick|count[7]~4 , tick|count[7]~4, ex15, 1
+instance = comp, \tick|count[7]~DUPLICATE , tick|count[7]~DUPLICATE, ex15, 1
+instance = comp, \tick|Add0~25 , tick|Add0~25, ex15, 1
+instance = comp, \tick|count[8]~5 , tick|count[8]~5, ex15, 1
+instance = comp, \tick|count[8] , tick|count[8], ex15, 1
+instance = comp, \tick|Add0~1 , tick|Add0~1, ex15, 1
+instance = comp, \tick|count[9]~0 , tick|count[9]~0, ex15, 1
+instance = comp, \tick|count[9]~DUPLICATE , tick|count[9]~DUPLICATE, ex15, 1
+instance = comp, \tick|Add0~5 , tick|Add0~5, ex15, 1
+instance = comp, \tick|count[10] , tick|count[10], ex15, 1
+instance = comp, \tick|Add0~49 , tick|Add0~49, ex15, 1
+instance = comp, \tick|count[11]~DUPLICATE , tick|count[11]~DUPLICATE, ex15, 1
+instance = comp, \tick|Add0~29 , tick|Add0~29, ex15, 1
+instance = comp, \tick|count[12]~6 , tick|count[12]~6, ex15, 1
+instance = comp, \tick|count[12] , tick|count[12], ex15, 1
+instance = comp, \tick|count[4]~DUPLICATE , tick|count[4]~DUPLICATE, ex15, 1
+instance = comp, \tick|count[3]~DUPLICATE , tick|count[3]~DUPLICATE, ex15, 1
+instance = comp, \tick|count[6]~DUPLICATE , tick|count[6]~DUPLICATE, ex15, 1
+instance = comp, \tick|Equal0~1 , tick|Equal0~1, ex15, 1
+instance = comp, \tick|count[1] , tick|count[1], ex15, 1
+instance = comp, \tick|count[2] , tick|count[2], ex15, 1
+instance = comp, \tick|count[7] , tick|count[7], ex15, 1
+instance = comp, \tick|Equal0~0 , tick|Equal0~0, ex15, 1
+instance = comp, \tick|count[13]~DUPLICATE , tick|count[13]~DUPLICATE, ex15, 1
+instance = comp, \tick|Add0~53 , tick|Add0~53, ex15, 1
+instance = comp, \tick|count[13] , tick|count[13], ex15, 1
+instance = comp, \tick|count[11] , tick|count[11], ex15, 1
+instance = comp, \tick|Add0~57 , tick|Add0~57, ex15, 1
+instance = comp, \tick|count[14] , tick|count[14], ex15, 1
+instance = comp, \tick|Add0~61 , tick|Add0~61, ex15, 1
+instance = comp, \tick|count[15] , tick|count[15], ex15, 1
+instance = comp, \tick|Equal0~2 , tick|Equal0~2, ex15, 1
+instance = comp, \tick|Equal0~3 , tick|Equal0~3, ex15, 1
+instance = comp, \tick|CLK_OUT~feeder , tick|CLK_OUT~feeder, ex15, 1
+instance = comp, \tick|CLK_OUT , tick|CLK_OUT, ex15, 1
+instance = comp, \dac|sr_state.IDLE~0 , dac|sr_state.IDLE~0, ex15, 1
+instance = comp, \dac|sr_state.IDLE , dac|sr_state.IDLE, ex15, 1
+instance = comp, \dac|Selector2~0 , dac|Selector2~0, ex15, 1
+instance = comp, \dac|sr_state.WAIT_CSB_HIGH , dac|sr_state.WAIT_CSB_HIGH, ex15, 1
+instance = comp, \dac|sr_state.WAIT_CSB_FALL~0 , dac|sr_state.WAIT_CSB_FALL~0, ex15, 1
+instance = comp, \dac|sr_state.WAIT_CSB_FALL , dac|sr_state.WAIT_CSB_FALL, ex15, 1
+instance = comp, \dac|Selector3~0 , dac|Selector3~0, ex15, 1
+instance = comp, \dac|state[0] , dac|state[0], ex15, 1
+instance = comp, \dac|state[2]~DUPLICATE , dac|state[2]~DUPLICATE, ex15, 1
+instance = comp, \dac|WideNor0 , dac|WideNor0, ex15, 1
+instance = comp, \SPI_ADC|clk_1MHz~0 , SPI_ADC|clk_1MHz~0, ex15, 1
+instance = comp, \SPI_ADC|clk_1MHz , SPI_ADC|clk_1MHz, ex15, 1
+instance = comp, \ADC_SDO~input , ADC_SDO~input, ex15, 1
+instance = comp, \SPI_ADC|state[1]~DUPLICATE , SPI_ADC|state[1]~DUPLICATE, ex15, 1
+instance = comp, \SPI_ADC|state[1]~1 , SPI_ADC|state[1]~1, ex15, 1
+instance = comp, \SPI_ADC|state[1] , SPI_ADC|state[1], ex15, 1
+instance = comp, \SPI_ADC|state[3]~DUPLICATE , SPI_ADC|state[3]~DUPLICATE, ex15, 1
+instance = comp, \SPI_ADC|state[3]~3 , SPI_ADC|state[3]~3, ex15, 1
+instance = comp, \SPI_ADC|state[3] , SPI_ADC|state[3], ex15, 1
+instance = comp, \SPI_ADC|state~0 , SPI_ADC|state~0, ex15, 1
+instance = comp, \SPI_ADC|state[4] , SPI_ADC|state[4], ex15, 1
+instance = comp, \SPI_ADC|Selector4~0 , SPI_ADC|Selector4~0, ex15, 1
+instance = comp, \SPI_ADC|adc_cs , SPI_ADC|adc_cs, ex15, 1
+instance = comp, \SPI_ADC|Selector2~0 , SPI_ADC|Selector2~0, ex15, 1
+instance = comp, \SPI_ADC|sr_state.WAIT_CSB_HIGH , SPI_ADC|sr_state.WAIT_CSB_HIGH, ex15, 1
+instance = comp, \SPI_ADC|Selector0~0 , SPI_ADC|Selector0~0, ex15, 1
+instance = comp, \SPI_ADC|sr_state.IDLE , SPI_ADC|sr_state.IDLE, ex15, 1
+instance = comp, \SPI_ADC|Selector1~0 , SPI_ADC|Selector1~0, ex15, 1
+instance = comp, \SPI_ADC|sr_state.WAIT_CSB_FALL , SPI_ADC|sr_state.WAIT_CSB_FALL, ex15, 1
+instance = comp, \SPI_ADC|adc_start~0 , SPI_ADC|adc_start~0, ex15, 1
+instance = comp, \SPI_ADC|adc_start , SPI_ADC|adc_start, ex15, 1
+instance = comp, \SPI_ADC|Selector5~0 , SPI_ADC|Selector5~0, ex15, 1
+instance = comp, \SPI_ADC|state[0] , SPI_ADC|state[0], ex15, 1
+instance = comp, \SPI_ADC|state[2]~2 , SPI_ADC|state[2]~2, ex15, 1
+instance = comp, \SPI_ADC|state[2] , SPI_ADC|state[2], ex15, 1
+instance = comp, \SPI_ADC|WideOr0~0 , SPI_ADC|WideOr0~0, ex15, 1
+instance = comp, \SPI_ADC|shift_ena , SPI_ADC|shift_ena, ex15, 1
+instance = comp, \SPI_ADC|always3~0 , SPI_ADC|always3~0, ex15, 1
+instance = comp, \SPI_ADC|shift_reg[0] , SPI_ADC|shift_reg[0], ex15, 1
+instance = comp, \SPI_ADC|Decoder0~0 , SPI_ADC|Decoder0~0, ex15, 1
+instance = comp, \SPI_ADC|adc_done , SPI_ADC|adc_done, ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[0] , SPI_ADC|data_from_adc[0], ex15, 1
+instance = comp, \fin_address|Add0~1 , fin_address|Add0~1, ex15, 1
+instance = comp, \fin_address|address[0]~feeder , fin_address|address[0]~feeder, ex15, 1
+instance = comp, \fin_address|address[0] , fin_address|address[0], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[1]~feeder , SPI_ADC|shift_reg[1]~feeder, ex15, 1
+instance = comp, \SPI_ADC|shift_reg[1] , SPI_ADC|shift_reg[1], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[1] , SPI_ADC|data_from_adc[1], ex15, 1
+instance = comp, \fin_address|Add0~5 , fin_address|Add0~5, ex15, 1
+instance = comp, \fin_address|address[1]~feeder , fin_address|address[1]~feeder, ex15, 1
+instance = comp, \fin_address|address[1] , fin_address|address[1], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[1]~DUPLICATE , SPI_ADC|shift_reg[1]~DUPLICATE, ex15, 1
+instance = comp, \SPI_ADC|shift_reg[2] , SPI_ADC|shift_reg[2], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[2] , SPI_ADC|data_from_adc[2], ex15, 1
+instance = comp, \fin_address|Add0~9 , fin_address|Add0~9, ex15, 1
+instance = comp, \fin_address|address[2]~feeder , fin_address|address[2]~feeder, ex15, 1
+instance = comp, \fin_address|address[2] , fin_address|address[2], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[3]~feeder , SPI_ADC|shift_reg[3]~feeder, ex15, 1
+instance = comp, \SPI_ADC|shift_reg[3] , SPI_ADC|shift_reg[3], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[3] , SPI_ADC|data_from_adc[3], ex15, 1
+instance = comp, \fin_address|Add0~13 , fin_address|Add0~13, ex15, 1
+instance = comp, \fin_address|address[3]~feeder , fin_address|address[3]~feeder, ex15, 1
+instance = comp, \fin_address|address[3] , fin_address|address[3], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[4] , SPI_ADC|shift_reg[4], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[4] , SPI_ADC|data_from_adc[4], ex15, 1
+instance = comp, \fin_address|Add0~17 , fin_address|Add0~17, ex15, 1
+instance = comp, \fin_address|address[4]~feeder , fin_address|address[4]~feeder, ex15, 1
+instance = comp, \fin_address|address[4] , fin_address|address[4], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[5]~feeder , SPI_ADC|shift_reg[5]~feeder, ex15, 1
+instance = comp, \SPI_ADC|shift_reg[5] , SPI_ADC|shift_reg[5], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[5] , SPI_ADC|data_from_adc[5], ex15, 1
+instance = comp, \fin_address|Add0~21 , fin_address|Add0~21, ex15, 1
+instance = comp, \fin_address|address[5]~feeder , fin_address|address[5]~feeder, ex15, 1
+instance = comp, \fin_address|address[5] , fin_address|address[5], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[6]~feeder , SPI_ADC|shift_reg[6]~feeder, ex15, 1
+instance = comp, \SPI_ADC|shift_reg[6] , SPI_ADC|shift_reg[6], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[6] , SPI_ADC|data_from_adc[6], ex15, 1
+instance = comp, \fin_address|Add0~25 , fin_address|Add0~25, ex15, 1
+instance = comp, \fin_address|address[6]~feeder , fin_address|address[6]~feeder, ex15, 1
+instance = comp, \fin_address|address[6] , fin_address|address[6], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[7]~feeder , SPI_ADC|shift_reg[7]~feeder, ex15, 1
+instance = comp, \SPI_ADC|shift_reg[7] , SPI_ADC|shift_reg[7], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[7] , SPI_ADC|data_from_adc[7], ex15, 1
+instance = comp, \fin_address|Add0~29 , fin_address|Add0~29, ex15, 1
+instance = comp, \fin_address|address[7]~feeder , fin_address|address[7]~feeder, ex15, 1
+instance = comp, \fin_address|address[7] , fin_address|address[7], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[8] , SPI_ADC|shift_reg[8], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[8] , SPI_ADC|data_from_adc[8], ex15, 1
+instance = comp, \fin_address|Add0~33 , fin_address|Add0~33, ex15, 1
+instance = comp, \fin_address|address[8]~feeder , fin_address|address[8]~feeder, ex15, 1
+instance = comp, \fin_address|address[8] , fin_address|address[8], ex15, 1
+instance = comp, \SPI_ADC|shift_reg[8]~DUPLICATE , SPI_ADC|shift_reg[8]~DUPLICATE, ex15, 1
+instance = comp, \SPI_ADC|shift_reg[9] , SPI_ADC|shift_reg[9], ex15, 1
+instance = comp, \SPI_ADC|data_from_adc[9] , SPI_ADC|data_from_adc[9], ex15, 1
+instance = comp, \fin_address|Add0~37 , fin_address|Add0~37, ex15, 1
+instance = comp, \fin_address|address[9]~feeder , fin_address|address[9]~feeder, ex15, 1
+instance = comp, \fin_address|address[9] , fin_address|address[9], ex15, 1
+instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, ex15, 1
+instance = comp, \dac|shift_reg[11]~feeder , dac|shift_reg[11]~feeder, ex15, 1
+instance = comp, \dac|shift_reg[10]~feeder , dac|shift_reg[10]~feeder, ex15, 1
+instance = comp, \dac|shift_reg[9]~feeder , dac|shift_reg[9]~feeder, ex15, 1
+instance = comp, \dac|shift_reg[8]~feeder , dac|shift_reg[8]~feeder, ex15, 1
+instance = comp, \dac|shift_reg[7]~feeder , dac|shift_reg[7]~feeder, ex15, 1
+instance = comp, \dac|shift_reg[6]~feeder , dac|shift_reg[6]~feeder, ex15, 1
+instance = comp, \dac|shift_reg[5]~feeder , dac|shift_reg[5]~feeder, ex15, 1
+instance = comp, \dac|shift_reg[4]~feeder , dac|shift_reg[4]~feeder, ex15, 1
+instance = comp, \dac|shift_reg[3]~feeder , dac|shift_reg[3]~feeder, ex15, 1
+instance = comp, \dac|shift_reg~4 , dac|shift_reg~4, ex15, 1
+instance = comp, \dac|shift_reg[2] , dac|shift_reg[2], ex15, 1
+instance = comp, \dac|state[4] , dac|state[4], ex15, 1
+instance = comp, \dac|always5~0 , dac|always5~0, ex15, 1
+instance = comp, \dac|shift_reg[3] , dac|shift_reg[3], ex15, 1
+instance = comp, \dac|shift_reg[4] , dac|shift_reg[4], ex15, 1
+instance = comp, \dac|shift_reg[5] , dac|shift_reg[5], ex15, 1
+instance = comp, \dac|shift_reg[6] , dac|shift_reg[6], ex15, 1
+instance = comp, \dac|shift_reg[7] , dac|shift_reg[7], ex15, 1
+instance = comp, \dac|shift_reg[8] , dac|shift_reg[8], ex15, 1
+instance = comp, \dac|shift_reg[9] , dac|shift_reg[9], ex15, 1
+instance = comp, \dac|shift_reg[10] , dac|shift_reg[10], ex15, 1
+instance = comp, \dac|shift_reg[11] , dac|shift_reg[11], ex15, 1
+instance = comp, \dac|shift_reg~3 , dac|shift_reg~3, ex15, 1
+instance = comp, \dac|shift_reg[12] , dac|shift_reg[12], ex15, 1
+instance = comp, \dac|shift_reg~2 , dac|shift_reg~2, ex15, 1
+instance = comp, \dac|shift_reg[13] , dac|shift_reg[13], ex15, 1
+instance = comp, \dac|shift_reg~1 , dac|shift_reg~1, ex15, 1
+instance = comp, \dac|shift_reg[14] , dac|shift_reg[14], ex15, 1
+instance = comp, \dac|shift_reg~0 , dac|shift_reg~0, ex15, 1
+instance = comp, \dac|shift_reg[15] , dac|shift_reg[15], ex15, 1
+instance = comp, \dac|Equal2~0 , dac|Equal2~0, ex15, 1
+instance = comp, \dac|dac_sck , dac|dac_sck, ex15, 1
+instance = comp, \SPI_ADC|state[2]~DUPLICATE , SPI_ADC|state[2]~DUPLICATE, ex15, 1
+instance = comp, \SPI_ADC|Selector6~0 , SPI_ADC|Selector6~0, ex15, 1
+instance = comp, \SPI_ADC|adc_din , SPI_ADC|adc_din, ex15, 1
+instance = comp, \SPI_ADC|adc_sck , SPI_ADC|adc_sck, ex15, 1
+instance = comp, \p|count[0] , p|count[0], ex15, 1
+instance = comp, \p|count[0]~0 , p|count[0]~0, ex15, 1
+instance = comp, \p|count[0]~DUPLICATE , p|count[0]~DUPLICATE, ex15, 1
+instance = comp, \p|Add0~33 , p|Add0~33, ex15, 1
+instance = comp, \p|count[1] , p|count[1], ex15, 1
+instance = comp, \p|Add0~29 , p|Add0~29, ex15, 1
+instance = comp, \p|count[2] , p|count[2], ex15, 1
+instance = comp, \p|Add0~25 , p|Add0~25, ex15, 1
+instance = comp, \p|count[3] , p|count[3], ex15, 1
+instance = comp, \p|Add0~21 , p|Add0~21, ex15, 1
+instance = comp, \p|count[4] , p|count[4], ex15, 1
+instance = comp, \p|Add0~17 , p|Add0~17, ex15, 1
+instance = comp, \p|count[5] , p|count[5], ex15, 1
+instance = comp, \p|Add0~13 , p|Add0~13, ex15, 1
+instance = comp, \p|count[6] , p|count[6], ex15, 1
+instance = comp, \p|Add0~9 , p|Add0~9, ex15, 1
+instance = comp, \p|count[7] , p|count[7], ex15, 1
+instance = comp, \p|Add0~5 , p|Add0~5, ex15, 1
+instance = comp, \p|count[8] , p|count[8], ex15, 1
+instance = comp, \p|d[8] , p|d[8], ex15, 1
+instance = comp, \p|d[6] , p|d[6], ex15, 1
+instance = comp, \p|d[7]~feeder , p|d[7]~feeder, ex15, 1
+instance = comp, \p|d[7] , p|d[7], ex15, 1
+instance = comp, \p|LessThan0~1 , p|LessThan0~1, ex15, 1
+instance = comp, \p|d[3] , p|d[3], ex15, 1
+instance = comp, \p|d[4] , p|d[4], ex15, 1
+instance = comp, \p|d[2] , p|d[2], ex15, 1
+instance = comp, \p|d[0]~feeder , p|d[0]~feeder, ex15, 1
+instance = comp, \p|d[0] , p|d[0], ex15, 1
+instance = comp, \p|d[1] , p|d[1], ex15, 1
+instance = comp, \p|LessThan0~2 , p|LessThan0~2, ex15, 1
+instance = comp, \p|LessThan0~3 , p|LessThan0~3, ex15, 1
+instance = comp, \p|d[5] , p|d[5], ex15, 1
+instance = comp, \p|LessThan0~4 , p|LessThan0~4, ex15, 1
+instance = comp, \p|d[9] , p|d[9], ex15, 1
+instance = comp, \p|Add0~1 , p|Add0~1, ex15, 1
+instance = comp, \p|count[9] , p|count[9], ex15, 1
+instance = comp, \p|LessThan0~0 , p|LessThan0~0, ex15, 1
+instance = comp, \p|LessThan0~5 , p|LessThan0~5, ex15, 1
+instance = comp, \p|pwm_out , p|pwm_out, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[1][17]~5 , mult|lpm_mult_component|mult_core|romout[1][17]~5, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][17]~4 , mult|lpm_mult_component|mult_core|romout[0][17]~4, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][16]~3 , mult|lpm_mult_component|mult_core|romout[0][16]~3, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][15]~2 , mult|lpm_mult_component|mult_core|romout[0][15]~2, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][14]~1 , mult|lpm_mult_component|mult_core|romout[0][14]~1, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|romout[1][9]~0 , mult|lpm_mult_component|mult_core|romout[1][9]~0, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41, ex15, 1
+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45, ex15, 1
+instance = comp, \bcd|A2|WideOr1~0 , bcd|A2|WideOr1~0, ex15, 1
+instance = comp, \bcd|A2|WideOr3~0 , bcd|A2|WideOr3~0, ex15, 1
+instance = comp, \bcd|A2|WideOr2~0 , bcd|A2|WideOr2~0, ex15, 1
+instance = comp, \bcd|A4|WideOr2~0 , bcd|A4|WideOr2~0, ex15, 1
+instance = comp, \bcd|A4|WideOr1~0 , bcd|A4|WideOr1~0, ex15, 1
+instance = comp, \bcd|A4|WideOr3~0 , bcd|A4|WideOr3~0, ex15, 1
+instance = comp, \bcd|A6|WideOr1~0 , bcd|A6|WideOr1~0, ex15, 1
+instance = comp, \bcd|A6|WideOr2~0 , bcd|A6|WideOr2~0, ex15, 1
+instance = comp, \bcd|A6|WideOr3~0 , bcd|A6|WideOr3~0, ex15, 1
+instance = comp, \bcd|A8|WideOr3~0 , bcd|A8|WideOr3~0, ex15, 1
+instance = comp, \bcd|A8|WideOr2~0 , bcd|A8|WideOr2~0, ex15, 1
+instance = comp, \bcd|A8|WideOr1~0 , bcd|A8|WideOr1~0, ex15, 1
+instance = comp, \bcd|A11|WideOr3~0 , bcd|A11|WideOr3~0, ex15, 1
+instance = comp, \bcd|A11|WideOr1~0 , bcd|A11|WideOr1~0, ex15, 1
+instance = comp, \bcd|A11|WideOr2~0 , bcd|A11|WideOr2~0, ex15, 1
+instance = comp, \bcd|A14|WideOr1~0 , bcd|A14|WideOr1~0, ex15, 1
+instance = comp, \bcd|A14|WideOr3~0 , bcd|A14|WideOr3~0, ex15, 1
+instance = comp, \bcd|A14|WideOr2~0 , bcd|A14|WideOr2~0, ex15, 1
+instance = comp, \bcd|A17|WideOr1~0 , bcd|A17|WideOr1~0, ex15, 1
+instance = comp, \bcd|A17|WideOr3~0 , bcd|A17|WideOr3~0, ex15, 1
+instance = comp, \bcd|A17|WideOr2~0 , bcd|A17|WideOr2~0, ex15, 1
+instance = comp, \bcd|A21|WideOr3~0 , bcd|A21|WideOr3~0, ex15, 1
+instance = comp, \bcd|A21|WideOr1~0 , bcd|A21|WideOr1~0, ex15, 1
+instance = comp, \bcd|A21|WideOr2~0 , bcd|A21|WideOr2~0, ex15, 1
+instance = comp, \bcd|A25|WideOr3~0 , bcd|A25|WideOr3~0, ex15, 1
+instance = comp, \bcd|A25|WideOr1~0 , bcd|A25|WideOr1~0, ex15, 1
+instance = comp, \bcd|A25|WideOr2~0 , bcd|A25|WideOr2~0, ex15, 1
+instance = comp, \bcd|A29|WideOr1~0 , bcd|A29|WideOr1~0, ex15, 1
+instance = comp, \bcd|A29|WideOr2~0 , bcd|A29|WideOr2~0, ex15, 1
+instance = comp, \bcd|A29|WideOr3~0 , bcd|A29|WideOr3~0, ex15, 1
+instance = comp, \h0|WideOr6~0 , h0|WideOr6~0, ex15, 1
+instance = comp, \h0|WideOr5~0 , h0|WideOr5~0, ex15, 1
+instance = comp, \h0|WideOr4~0 , h0|WideOr4~0, ex15, 1
+instance = comp, \h0|WideOr3~0 , h0|WideOr3~0, ex15, 1
+instance = comp, \h0|WideOr2~0 , h0|WideOr2~0, ex15, 1
+instance = comp, \h0|WideOr1~0 , h0|WideOr1~0, ex15, 1
+instance = comp, \h0|WideOr0~0 , h0|WideOr0~0, ex15, 1
+instance = comp, \bcd|A25|WideOr0~0 , bcd|A25|WideOr0~0, ex15, 1
+instance = comp, \bcd|A17|WideOr0~0 , bcd|A17|WideOr0~0, ex15, 1
+instance = comp, \bcd|A14|WideOr0~0 , bcd|A14|WideOr0~0, ex15, 1
+instance = comp, \bcd|A7|WideOr2~0 , bcd|A7|WideOr2~0, ex15, 1
+instance = comp, \bcd|A7|WideOr3~0 , bcd|A7|WideOr3~0, ex15, 1
+instance = comp, \bcd|A8|WideOr0~0 , bcd|A8|WideOr0~0, ex15, 1
+instance = comp, \bcd|A7|WideOr1~0 , bcd|A7|WideOr1~0, ex15, 1
+instance = comp, \bcd|A10|WideOr2~0 , bcd|A10|WideOr2~0, ex15, 1
+instance = comp, \bcd|A11|WideOr0~0 , bcd|A11|WideOr0~0, ex15, 1
+instance = comp, \bcd|A10|WideOr1~0 , bcd|A10|WideOr1~0, ex15, 1
+instance = comp, \bcd|A10|WideOr3~0 , bcd|A10|WideOr3~0, ex15, 1
+instance = comp, \bcd|A13|WideOr1~0 , bcd|A13|WideOr1~0, ex15, 1
+instance = comp, \bcd|A13|WideOr2~0 , bcd|A13|WideOr2~0, ex15, 1
+instance = comp, \bcd|A13|WideOr3~0 , bcd|A13|WideOr3~0, ex15, 1
+instance = comp, \bcd|A16|WideOr1~0 , bcd|A16|WideOr1~0, ex15, 1
+instance = comp, \bcd|A16|WideOr3~0 , bcd|A16|WideOr3~0, ex15, 1
+instance = comp, \bcd|A16|WideOr2~0 , bcd|A16|WideOr2~0, ex15, 1
+instance = comp, \bcd|A20|WideOr3~0 , bcd|A20|WideOr3~0, ex15, 1
+instance = comp, \bcd|A20|WideOr2~0 , bcd|A20|WideOr2~0, ex15, 1
+instance = comp, \bcd|A21|WideOr0~0 , bcd|A21|WideOr0~0, ex15, 1
+instance = comp, \bcd|A20|WideOr1~0 , bcd|A20|WideOr1~0, ex15, 1
+instance = comp, \bcd|A24|WideOr1~0 , bcd|A24|WideOr1~0, ex15, 1
+instance = comp, \bcd|A24|WideOr2~0 , bcd|A24|WideOr2~0, ex15, 1
+instance = comp, \bcd|A24|WideOr3~0 , bcd|A24|WideOr3~0, ex15, 1
+instance = comp, \bcd|A28|WideOr3~0 , bcd|A28|WideOr3~0, ex15, 1
+instance = comp, \bcd|A28|WideOr2~0 , bcd|A28|WideOr2~0, ex15, 1
+instance = comp, \bcd|A29|WideOr0~0 , bcd|A29|WideOr0~0, ex15, 1
+instance = comp, \bcd|A28|WideOr1~0 , bcd|A28|WideOr1~0, ex15, 1
+instance = comp, \h1|WideOr6~0 , h1|WideOr6~0, ex15, 1
+instance = comp, \h1|WideOr5~0 , h1|WideOr5~0, ex15, 1
+instance = comp, \h1|WideOr4~0 , h1|WideOr4~0, ex15, 1
+instance = comp, \h1|WideOr3~0 , h1|WideOr3~0, ex15, 1
+instance = comp, \h1|WideOr2~0 , h1|WideOr2~0, ex15, 1
+instance = comp, \h1|WideOr1~0 , h1|WideOr1~0, ex15, 1
+instance = comp, \h1|WideOr0~0 , h1|WideOr0~0, ex15, 1
+instance = comp, \bcd|A6|WideOr0~0 , bcd|A6|WideOr0~0, ex15, 1
+instance = comp, \bcd|A1|WideOr0~0 , bcd|A1|WideOr0~0, ex15, 1
+instance = comp, \bcd|A2|WideOr0~0 , bcd|A2|WideOr0~0, ex15, 1
+instance = comp, \bcd|A4|WideOr0~0 , bcd|A4|WideOr0~0, ex15, 1
+instance = comp, \bcd|A15|WideOr1~0 , bcd|A15|WideOr1~0, ex15, 1
+instance = comp, \bcd|A16|WideOr0~0 , bcd|A16|WideOr0~0, ex15, 1
+instance = comp, \bcd|A15|WideOr3~0 , bcd|A15|WideOr3~0, ex15, 1
+instance = comp, \bcd|A15|WideOr2~0 , bcd|A15|WideOr2~0, ex15, 1
+instance = comp, \bcd|A19|WideOr1~0 , bcd|A19|WideOr1~0, ex15, 1
+instance = comp, \bcd|A20|WideOr0~0 , bcd|A20|WideOr0~0, ex15, 1
+instance = comp, \bcd|A19|WideOr2~0 , bcd|A19|WideOr2~0, ex15, 1
+instance = comp, \bcd|A19|WideOr3~0 , bcd|A19|WideOr3~0, ex15, 1
+instance = comp, \bcd|A23|WideOr2~0 , bcd|A23|WideOr2~0, ex15, 1
+instance = comp, \bcd|A23|WideOr3~0 , bcd|A23|WideOr3~0, ex15, 1
+instance = comp, \bcd|A23|WideOr1~0 , bcd|A23|WideOr1~0, ex15, 1
+instance = comp, \bcd|A24|WideOr0~0 , bcd|A24|WideOr0~0, ex15, 1
+instance = comp, \bcd|A27|WideOr3~0 , bcd|A27|WideOr3~0, ex15, 1
+instance = comp, \bcd|A28|WideOr0~0 , bcd|A28|WideOr0~0, ex15, 1
+instance = comp, \bcd|A27|WideOr2~0 , bcd|A27|WideOr2~0, ex15, 1
+instance = comp, \bcd|A27|WideOr1~0 , bcd|A27|WideOr1~0, ex15, 1
+instance = comp, \h2|WideOr6~0 , h2|WideOr6~0, ex15, 1
+instance = comp, \h2|WideOr5~0 , h2|WideOr5~0, ex15, 1
+instance = comp, \h2|WideOr4~0 , h2|WideOr4~0, ex15, 1
+instance = comp, \h2|WideOr3~0 , h2|WideOr3~0, ex15, 1
+instance = comp, \h2|WideOr2~0 , h2|WideOr2~0, ex15, 1
+instance = comp, \h2|WideOr1~0 , h2|WideOr1~0, ex15, 1
+instance = comp, \h2|WideOr0~0 , h2|WideOr0~0, ex15, 1
+instance = comp, \bcd|A27|WideOr0~0 , bcd|A27|WideOr0~0, ex15, 1
+instance = comp, \bcd|A23|WideOr0~0 , bcd|A23|WideOr0~0, ex15, 1
+instance = comp, \bcd|A19|WideOr0~0 , bcd|A19|WideOr0~0, ex15, 1
+instance = comp, \bcd|A15|WideOr0~0 , bcd|A15|WideOr0~0, ex15, 1
+instance = comp, \bcd|A10|WideOr0~0 , bcd|A10|WideOr0~0, ex15, 1
+instance = comp, \bcd|A7|WideOr0~0 , bcd|A7|WideOr0~0, ex15, 1
+instance = comp, \bcd|A5|WideOr0~0 , bcd|A5|WideOr0~0, ex15, 1
+instance = comp, \bcd|A12|WideOr0~0 , bcd|A12|WideOr0~0, ex15, 1
+instance = comp, \bcd|A26|Decoder0~0 , bcd|A26|Decoder0~0, ex15, 1
+instance = comp, \bcd|A26|Decoder0~2 , bcd|A26|Decoder0~2, ex15, 1
+instance = comp, \bcd|A26|WideOr2 , bcd|A26|WideOr2, ex15, 1
+instance = comp, \bcd|A26|Decoder0~1 , bcd|A26|Decoder0~1, ex15, 1
+instance = comp, \bcd|A26|WideOr3~0 , bcd|A26|WideOr3~0, ex15, 1
+instance = comp, \bcd|A26|Decoder0~3 , bcd|A26|Decoder0~3, ex15, 1
+instance = comp, \bcd|A26|WideOr1 , bcd|A26|WideOr1, ex15, 1
+instance = comp, \h3|WideOr6~0 , h3|WideOr6~0, ex15, 1
+instance = comp, \h3|WideOr5~0 , h3|WideOr5~0, ex15, 1
+instance = comp, \h3|WideOr4~0 , h3|WideOr4~0, ex15, 1
+instance = comp, \h3|WideOr3~0 , h3|WideOr3~0, ex15, 1
+instance = comp, \h3|WideOr2~0 , h3|WideOr2~0, ex15, 1
+instance = comp, \h3|WideOr1~0 , h3|WideOr1~0, ex15, 1
+instance = comp, \h3|WideOr0~0 , h3|WideOr0~0, ex15, 1
+instance = comp, \bcd|A26|Decoder0~4 , bcd|A26|Decoder0~4, ex15, 1
+instance = comp, \bcd|A22|WideOr0~0 , bcd|A22|WideOr0~0, ex15, 1
+instance = comp, \h4|Decoder0~0 , h4|Decoder0~0, ex15, 1
+instance = comp, \bcd|A13|WideOr0~0 , bcd|A13|WideOr0~0, ex15, 1
+instance = comp, \h4|Decoder0~2 , h4|Decoder0~2, ex15, 1
+instance = comp, \bcd|A26|WideOr0 , bcd|A26|WideOr0, ex15, 1
+instance = comp, \h4|Decoder0~1 , h4|Decoder0~1, ex15, 1
+instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, ex15, 1
diff --git a/part_3/ex15/simulation/modelsim/ex10_run_msim_rtl_verilog.do b/part_3/ex15/simulation/modelsim/ex10_run_msim_rtl_verilog.do
new file mode 100755
index 0000000..281cccf
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/ex10_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+
diff --git a/part_3/ex15/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak b/part_3/ex15/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak
new file mode 100755
index 0000000..281cccf
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+
diff --git a/part_3/ex15/simulation/modelsim/modelsim.ini b/part_3/ex15/simulation/modelsim/modelsim.ini
new file mode 100755
index 0000000..3912feb
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/modelsim.ini
@@ -0,0 +1,324 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+work = rtl_work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
diff --git a/part_3/ex15/simulation/modelsim/msim_transcript b/part_3/ex15/simulation/modelsim/msim_transcript
new file mode 100755
index 0000000..cb744ab
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/msim_transcript
@@ -0,0 +1,20 @@
+# Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl 
+# do ex10_run_msim_rtl_verilog.do 
+# if {[file exists rtl_work]} {
+# 	vdel -lib rtl_work -all
+# }
+# vlib rtl_work
+# vmap work rtl_work
+# Copying C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
+# Modifying modelsim.ini
+# ** Warning: Copied C:\altera\13.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
+#          Updated modelsim.ini.
+# 
+# vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+# -- Compiling module spi2dac
+# 
+# Top level modules:
+# 	spi2dac
+# 
+# Load canceled
diff --git a/part_3/ex15/simulation/modelsim/rtl_work/_info b/part_3/ex15/simulation/modelsim/rtl_work/_info
new file mode 100755
index 0000000..499bdd4
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/rtl_work/_info
@@ -0,0 +1,25 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex15/simulation/modelsim/rtl_work/_vmake b/part_3/ex15/simulation/modelsim/rtl_work/_vmake
new file mode 100755
index 0000000..2f7e729
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/rtl_work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.dat b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.dat
new file mode 100755
index 0000000..a728b27
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.dat
diff --git a/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.dbs b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.dbs
new file mode 100755
index 0000000..740ad04
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.dbs
diff --git a/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
new file mode 100755
index 0000000..e874ed3
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -0,0 +1,30 @@
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+    generic(
+        BUF             : vl_logic := Hi1;
+        GA_N            : vl_logic := Hi1;
+        SHDN_N          : vl_logic := Hi1;
+        TC              : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        data_in         : in     vl_logic_vector(9 downto 0);
+        load            : in     vl_logic;
+        dac_sdi         : out    vl_logic;
+        dac_cs          : out    vl_logic;
+        dac_sck         : out    vl_logic;
+        dac_ld          : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of BUF : constant is 1;
+    attribute mti_svvh_generic_type of GA_N : constant is 1;
+    attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+    attribute mti_svvh_generic_type of TC : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
diff --git a/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/verilog.prw b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/verilog.prw
new file mode 100755
index 0000000..ca1d7f3
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/verilog.prw
diff --git a/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/verilog.psm b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/verilog.psm
new file mode 100755
index 0000000..97c417f
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/rtl_work/spi2dac/verilog.psm
diff --git a/part_3/ex15/simulation/modelsim/vsim.wlf b/part_3/ex15/simulation/modelsim/vsim.wlf
new file mode 100755
index 0000000..54e1dca
--- /dev/null
+++ b/part_3/ex15/simulation/modelsim/vsim.wlf
diff --git a/part_3/ex15/verilog_files/ROM.qip b/part_3/ex15/verilog_files/ROM.qip
new file mode 100755
index 0000000..dc92785
--- /dev/null
+++ b/part_3/ex15/verilog_files/ROM.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ROM_bb.v"]
diff --git a/part_3/ex15/verilog_files/ROM.v b/part_3/ex15/verilog_files/ROM.v
new file mode 100755
index 0000000..296e57c
--- /dev/null
+++ b/part_3/ex15/verilog_files/ROM.v
@@ -0,0 +1,160 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: ROM.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ROM (
+	address,
+	clock,
+	q);
+
+	input	[9:0]  address;
+	input	  clock;
+	output	[9:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [9:0] sub_wire0;
+	wire [9:0] q = sub_wire0[9:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({10{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "./rom_data/rom_data.mif",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 1024,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 10,
+		altsyncram_component.width_a = 10,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./rom_data/rom_data.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+// Retrieval info: PRIVATE: WidthData NUMERIC "10"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./rom_data/rom_data.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q_a 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ROM_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_3/ex15/verilog_files/add3_ge5.v b/part_3/ex15/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..65a561d
--- /dev/null
+++ b/part_3/ex15/verilog_files/add3_ge5.v
@@ -0,0 +1,25 @@
+module add3_ge5(w,a);
+	output [3:0] a;
+	input [3:0] w;
+	
+	reg [3:0] a;
+	
+	always @ (w)
+		case(w)
+			4'b0000: a <= 4'b0000;
+			4'b0001: a <= 4'b0001;
+			4'b0010: a <= 4'b0010;
+			4'b0011: a <= 4'b0011;
+			4'b0100: a <= 4'b0100;
+			4'b0101: a <= 4'b1000;
+			4'b0110: a <= 4'b1001;
+			4'b0111: a <= 4'b1010;
+			4'b1000: a <= 4'b1011;
+			4'b1001: a <= 4'b1100;
+			4'b1010: a <= 4'b1101;
+			4'b1011: a <= 4'b1110;
+			4'b1100: a <= 4'b1111;
+			
+			default: a <= 4'b0000;
+		endcase
+endmodule
diff --git a/part_3/ex15/verilog_files/bin2bcd_16.v b/part_3/ex15/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..fdfb655
--- /dev/null
+++ b/part_3/ex15/verilog_files/bin2bcd_16.v
@@ -0,0 +1,97 @@
+//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+//            .... it uses a shift-and-add3 algorithm
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     18 Sept 2016
+//------------------------------
+//   For more explanation of how this work, see 
+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+	input [15:0]	B;		// binary input number
+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD
+	
+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+	wire [3:0]	w26,w27,w28,w29;
+	wire [3:0]	a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+	wire [3:0]	a26,a27,a28,a29;
+
+	// Instantiate a tree of add3-if-greater than or equal to 5 cells
+	//  ... input is w_n, and output is a_n
+	add3_ge5 A1 (w1,a1);
+	add3_ge5 A2 (w2,a2);
+	add3_ge5 A3 (w3,a3);
+	add3_ge5 A4 (w4,a4);
+	add3_ge5 A5 (w5,a5);
+	add3_ge5 A6 (w6,a6);
+	add3_ge5 A7 (w7,a7);
+	add3_ge5 A8 (w8,a8);
+	add3_ge5 A9 (w9,a9);
+	add3_ge5 A10 (w10,a10);
+	add3_ge5 A11 (w11,a11);
+	add3_ge5 A12 (w12,a12);
+	add3_ge5 A13 (w13,a13);
+	add3_ge5 A14 (w14,a14);
+	add3_ge5 A15 (w15,a15);
+	add3_ge5 A16 (w16,a16);
+	add3_ge5 A17 (w17,a17);
+	add3_ge5 A18 (w18,a18);
+	add3_ge5 A19 (w19,a19);
+	add3_ge5 A20 (w20,a20);
+	add3_ge5 A21 (w21,a21);
+	add3_ge5 A22 (w22,a22);
+	add3_ge5 A23 (w23,a23);
+	add3_ge5 A24 (w24,a24);
+	add3_ge5 A25 (w25,a25);
+	add3_ge5 A26 (w26,a26);
+	add3_ge5 A27 (w27,a27);
+	add3_ge5 A28 (w28,a28);
+	add3_ge5 A29 (w29,a29);
+		
+	// wire the tree of add3 modules together
+	assign  w1 = {B[14:11]};		// wn is the input port to module An
+	assign  w2 = {a1[2:0], B[10]};
+	assign  w3 = {1'b0, B[15], a1[3], a2[3]};
+	assign  w4 = {a2[2:0], B[9]};
+	assign  w5 = {a3[2:0], a4[3]};
+	assign  w6 = {a4[2:0], B[8]};
+	assign  w7 = {a5[2:0], a6[3]};
+	assign  w8 = {a6[2:0], B[7]};
+	assign  w9 = {1'b0, a3[3], a5[3], a7[3]};
+	assign  w10 = {a7[2:0], a8[3]};
+	assign  w11 = {a8[2:0], B[6]};
+	assign  w12 = {a9[2:0], a10[3]};
+	assign  w13 = {a10[2:0], a11[3]};
+	assign  w14 = {a11[2:0], B[5]};
+	assign  w15 = {a12[2:0], a13[3]};
+	assign  w16 = {a13[2:0], a14[3]};
+	assign  w17 = {a14[2:0], B[4]};
+	assign  w18 = {1'b0, a9[3], a12[3], a15[3]};
+	assign  w19 = {a15[2:0], a16[3]};
+	assign  w20 = {a16[2:0], a17[3]};
+	assign  w21 = {a17[2:0], B[3]};
+	assign  w22 = {a18[2:0], a19[3]};
+	assign  w23 = {a19[2:0], a20[3]};
+	assign  w24 = {a20[2:0], a21[3]};
+	assign  w25 = {a21[2:0], B[2]};
+	assign  w26 = {a22[2:0], a23[3]};
+	assign  w27 = {a23[2:0], a24[3]};
+	assign  w28 = {a24[2:0], a25[3]};
+	assign  w29 = {a25[2:0], B[1]};
+	
+	// connect up to four BCD digit outputs	
+	assign BCD_0 = {a29[2:0],B[0]};
+	assign BCD_1 = {a28[2:0],a29[3]};
+	assign BCD_2 = {a27[2:0],a28[3]};
+	assign BCD_3 = {a26[2:0],a27[3]};
+	assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};	
+endmodule
+
+	
+	
+
diff --git a/part_2/ex9_partially_working/verilog_files/hex_to_7seg.v b/part_3/ex15/verilog_files/hex_to_7seg.v
index 82aa9a5..82aa9a5 100755
--- a/part_2/ex9_partially_working/verilog_files/hex_to_7seg.v
+++ b/part_3/ex15/verilog_files/hex_to_7seg.v
diff --git a/part_3/ex15/verilog_files/pwm.v b/part_3/ex15/verilog_files/pwm.v
new file mode 100755
index 0000000..6a6e10c
--- /dev/null
+++ b/part_3/ex15/verilog_files/pwm.v
@@ -0,0 +1,25 @@
+module pwm(clk, data_in, load, pwm_out);
+
+	input clk;
+	input [9:0] data_in;
+	input load;
+	output pwm_out;
+	
+	reg[9:0] d;
+	reg [9:0] count;
+	reg pwm_out;
+	
+	always @ (posedge clk)
+		if(load == 1'b1) d <= data_in;
+		
+	initial count = 10'b0;
+	
+	always @ (posedge clk) begin
+		count <= count + 1'b1;
+		if(count > d)
+			pwm_out <= 1'b0;
+		else
+			pwm_out <= 1'b1;
+		end
+		
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex15/verilog_files/spi2adc.v b/part_3/ex15/verilog_files/spi2adc.v
new file mode 100755
index 0000000..3878f71
--- /dev/null
+++ b/part_3/ex15/verilog_files/spi2adc.v
@@ -0,0 +1,150 @@
+//------------------------------
+// Module name: spi2adc
+// Function: SPI interface for MCP3002 ADC
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     24 Jan 2014
+//------------------------------
+
+module spi2adc (sysclk, start, channel, data_from_adc, data_valid, 
+						sdata_to_adc, adc_cs, adc_sck, sdata_from_adc);
+
+	input	sysclk;			// 50MHz system clock of DE0
+	input	start;			// Pulse to start ADC, minimum wide = clock period
+	input	channel;			// channel 0 or 1 to be converted
+	output [9:0] data_from_adc;	// 10-bit ADC result
+	output data_valid;	// High indicates that converted data valid
+	output sdata_to_adc;	// Serial commands send to adc chip
+	output adc_cs;			// chip select - low when converting
+	output adc_sck;		// SPI clock - active during conversion
+	input sdata_from_adc;	// Converted serial data from ADC, MSB first
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire	sysclk, start, sdata_from_adc;
+
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg [9:0]	data_from_adc;
+	reg			adc_cs;
+	wire			sdata_to_adc, adc_sck, data_valid;
+	
+//-------------Configuration parameters for ADC --------
+	parameter	SGL=1'b1;	// 0:diff i/p, 1:single-ended
+	parameter	MSBF=1'b1;	// 0:LSB first, 1:MSB first
+			
+// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... to start.  Initialise to make simulation easier
+	end
+		
+	always @ (posedge sysclk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+// ---- end internal clock generator ----------
+
+// ---- Detect start is asserted with a small state machine
+	// .... FF set on positive edge of start
+	// .... reset when adc_cs goes high again
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			adc_start;
+	
+	initial begin
+		sr_state = IDLE;
+		adc_start = 1'b0;	// set while sending data to ADC
+		end
+	
+	always @ (posedge sysclk)
+		case (sr_state)
+			IDLE:	if (start==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						adc_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (adc_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (adc_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						adc_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+//------- End circuit to detect start and end of conversion	
+
+	
+// spi controller designed as a state machine
+// .... with 16 states (idle, and S1-S15 indicated by state value
+
+	reg [4:0] 	state;
+	reg  	adc_done, adc_din, shift_ena;
+	
+	initial	begin	
+		state = 5'b0; adc_cs = 1'b1; adc_done = 1'b0; 
+		adc_din = 1'b0; shift_ena <= 1'b0;
+		end
+		
+	always @(posedge clk_1MHz)  begin
+	
+	// default outputs and state transition
+		adc_cs <= 1'b0;  adc_done <= 1'b0;  adc_din <= 1'b0; shift_ena <= 1'b0;
+		state <= state + 1'b1;
+		case (state)
+			5'd0:	begin
+						if (adc_start==1'b0) begin
+							state <= 5'd0;			// still idle
+							adc_cs <= 1'b1;		// chip select not active
+							end
+						else begin
+							state <= 5'd1;			// start converting
+							adc_din <= 1'b1;		// start bit is 1
+							end
+					end
+			5'd1:	adc_din <= SGL;				// SGL bit
+			5'd2:	adc_din <= channel;			// CH bit
+			5'd3:	adc_din <= MSBF;				// MSB first bit
+			5'd4: shift_ena <= 1'b1;  			// start shifting data from adc
+			5'd15: begin
+						shift_ena <= 1'b0;
+						adc_done <= 1'b1;
+					 end
+			5'd16: begin  
+						adc_cs <= 1'b1;		// last state - disable chip select
+						state <= 5'd0;  		// go back to idle state
+					 end
+			default: 				
+						shift_ena <= 1'b1;	// unspecified states are covered by default above
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [9:0] shift_reg;
+	initial	begin
+			shift_reg = 10'b0;
+			data_from_adc = 10'b0;
+			end
+	
+	always @(negedge clk_1MHz)
+		if((adc_cs==1'b0)&&(shift_ena==1'b1))		// start shifting data_in
+				shift_reg <= {shift_reg[8:0],sdata_from_adc};
+	
+	// Latch converted output data
+	always @(posedge clk_1MHz)
+		if(adc_done) 					
+				data_from_adc = shift_reg;
+
+	// Assign outputs to drive SPI interface to DAC
+		assign adc_sck = !clk_1MHz & !adc_cs;
+		assign sdata_to_adc = adc_din;
+		assign data_valid = adc_cs;
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex15/verilog_files/spi2dac.v b/part_3/ex15/verilog_files/spi2dac.v
new file mode 100755
index 0000000..586a231
--- /dev/null
+++ b/part_3/ex15/verilog_files/spi2dac.v
@@ -0,0 +1,128 @@
+//------------------------------
+// Module name: spi2dac
+// Function: SPI interface for MPC4911 DAC
+// Creator:  Peter Cheung
+// Version:  2.0
+// Date:     8 Nov 2016
+//------------------------------
+
+module spi2dac (sysclk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld);
+
+	input	sysclk;			// 50MHz system clock of DE1
+	input	[9:0]	data_in;	// input data to DAC
+	input	load;				// Pulse to load data to dac
+	output dac_sdi;		// SPI serial data out
+	output dac_cs;			// chip select - low when sending data to dac
+	output dac_sck;		// SPI clock, 16 cycles at half sysclk freq
+	output dac_ld;
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire			sysclk, load;
+	wire [9:0]	data_in;
+	
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg			dac_cs, dac_ld;
+	wire			dac_sck, dac_sdi;
+	
+	parameter	BUF=1'b1;		// 0:no buffer, 1:Vref buffered
+	parameter	GA_N=1'b1;		// 0:gain = 2x, 1:gain = 1x
+	parameter	SHDN_N=1'b1;	// 0:power down, 1:dac active
+	
+	wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N};  // wire to VDD or GND
+	
+	// --- internal 1MHz symmetical clock generator -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	
+	parameter	TC = 5'd24;  // Terminal count - change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... Initialise when FPGA is configured
+	end
+		
+	always @ (posedge sysclk)    
+	  if (ctr==0) begin
+		  ctr <= TC;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+	// ---- end internal 1MHz symmetical clock generator ----------
+
+	// ---- FSM to detect rising edge of load and falling edge of dac_cs
+	// .... sr_state set on posedge of load
+	// .... sr_state reset when dac_cs goes high at the end of DAC output cycle
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			dac_start;		 // set if a DAC write is detected
+	
+	initial begin
+		sr_state = IDLE;
+		dac_start = 1'b0;	// set while sending data to DAC
+		end
+	
+	always @ (posedge sysclk)  // state transition
+		case (sr_state)
+			IDLE:	if (load==1'b1) sr_state <= WAIT_CSB_FALL;
+			WAIT_CSB_FALL: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+			WAIT_CSB_HIGH: if (dac_cs==1'b1) sr_state <= IDLE;
+			default: sr_state <= IDLE;
+		endcase
+	
+	always @ (*)
+		case (sr_state)
+			IDLE: dac_start = 1'b0;
+			WAIT_CSB_FALL: dac_start = 1'b1;
+			WAIT_CSB_HIGH: dac_start = 1'b0;
+			default: dac_start = 1'b0;
+		endcase
+		
+	//------- End circuit to detect start and end of conversion	state machine
+
+	//------- spi controller FSM
+	// .... with 17 states (idle, and S1-S16 
+	// .... for the 16 cycles each sending 1-bit to dac)
+	reg [4:0] 	state;
+	
+	initial	begin	
+		state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; 
+		end
+		
+	always @(posedge clk_1MHz)  // FSM state transition
+		case (state)
+			5'd0:	if (dac_start == 1'b1)    // waiting to start
+						state <= state + 1'b1; 
+					else 
+						state <= 5'b0; 
+			5'd17: 	state <= 5'd0;  // go back to idle state
+			default: state <= state + 1'b1;	// default go to next state
+		endcase
+	
+	always @ (*)	begin			// FSM output
+		dac_cs = 1'b0;  dac_ld = 1'b1;
+		case (state)
+			5'd0: 	dac_cs = 1'b1;
+			5'd17: 	begin dac_cs = 1'b1; dac_ld = 1'b0; end
+			default: begin dac_cs = 1'b0;	dac_ld = 1'b1;	end
+			endcase
+		end //always
+	// --------- END of spi controller FSM
+	
+	// shift register for output data
+	reg [15:0] shift_reg;
+	initial	begin	
+		shift_reg = 16'b0; 
+		end
+
+	always @(posedge clk_1MHz)
+		if((dac_start==1'b1)&&(dac_cs==1'b1))		// parallel load data to shift reg
+			shift_reg <= {cmd,data_in,2'b00};
+		else 													// .. else start shifting
+			shift_reg <= {shift_reg[14:0],1'b0};
+	
+	// Assign outputs to drive SPI interface to DAC
+			assign dac_sck = !clk_1MHz&!dac_cs;
+			assign dac_sdi = shift_reg[15];
+endmodule
+\ No newline at end of file
diff --git a/part_3/ex15/verilog_files/tick_5000.v b/part_3/ex15/verilog_files/tick_5000.v
new file mode 100755
index 0000000..a048386
--- /dev/null
+++ b/part_3/ex15/verilog_files/tick_5000.v
@@ -0,0 +1,32 @@
+module tick_5000(CLOCK_IN, CLK_OUT);
+
+	parameter NBIT = 16;
+	
+	input CLOCK_IN;
+	output CLK_OUT;
+	
+	reg [NBIT-1:0] count;
+	
+	reg CLK_OUT;
+	
+	initial 
+		begin
+			count = 16'd4999;
+			CLK_OUT = 1'b0;
+		end
+	
+	always @ (posedge CLOCK_IN)
+		begin
+			if(count == 16'b0)
+				begin
+					CLK_OUT <= 1'b1;
+					count <= 16'd4999;
+				end
+			else
+				begin
+					count <= count - 1'b1;
+					CLK_OUT <= 1'b0;
+				end
+		end
+
+endmodule
+\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/tick_50000.v b/part_3/ex15/verilog_files/tick_5000.v.bak
index 7ccc81b..97fcf8b 100755
--- a/part_2/ex9_final/verilog_files/tick_50000.v
+++ b/part_3/ex15/verilog_files/tick_5000.v.bak
@@ -11,7 +11,7 @@ module tick_50000(CLOCK_IN, CLK_OUT);
 	
 	initial 
 		begin
-			count = 16'd49999;
+			count = 16'd4999;
 			CLK_OUT = 1'b0;
 		end
 	
diff --git a/part_3/mylib/ROM.qip b/part_3/mylib/ROM.qip
new file mode 100755
index 0000000..dc92785
--- /dev/null
+++ b/part_3/mylib/ROM.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ROM.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ROM_bb.v"]
diff --git a/part_3/mylib/add3_ge5.v b/part_3/mylib/add3_ge5.v
new file mode 100755
index 0000000..65a561d
--- /dev/null
+++ b/part_3/mylib/add3_ge5.v
@@ -0,0 +1,25 @@
+module add3_ge5(w,a);
+	output [3:0] a;
+	input [3:0] w;
+	
+	reg [3:0] a;
+	
+	always @ (w)
+		case(w)
+			4'b0000: a <= 4'b0000;
+			4'b0001: a <= 4'b0001;
+			4'b0010: a <= 4'b0010;
+			4'b0011: a <= 4'b0011;
+			4'b0100: a <= 4'b0100;
+			4'b0101: a <= 4'b1000;
+			4'b0110: a <= 4'b1001;
+			4'b0111: a <= 4'b1010;
+			4'b1000: a <= 4'b1011;
+			4'b1001: a <= 4'b1100;
+			4'b1010: a <= 4'b1101;
+			4'b1011: a <= 4'b1110;
+			4'b1100: a <= 4'b1111;
+			
+			default: a <= 4'b0000;
+		endcase
+endmodule
diff --git a/part_3/mylib/bin2bcd_16.v b/part_3/mylib/bin2bcd_16.v
new file mode 100755
index 0000000..fdfb655
--- /dev/null
+++ b/part_3/mylib/bin2bcd_16.v
@@ -0,0 +1,97 @@
+//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+//            .... it uses a shift-and-add3 algorithm
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     18 Sept 2016
+//------------------------------
+//   For more explanation of how this work, see 
+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+	input [15:0]	B;		// binary input number
+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD
+	
+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+	wire [3:0]	w26,w27,w28,w29;
+	wire [3:0]	a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+	wire [3:0]	a26,a27,a28,a29;
+
+	// Instantiate a tree of add3-if-greater than or equal to 5 cells
+	//  ... input is w_n, and output is a_n
+	add3_ge5 A1 (w1,a1);
+	add3_ge5 A2 (w2,a2);
+	add3_ge5 A3 (w3,a3);
+	add3_ge5 A4 (w4,a4);
+	add3_ge5 A5 (w5,a5);
+	add3_ge5 A6 (w6,a6);
+	add3_ge5 A7 (w7,a7);
+	add3_ge5 A8 (w8,a8);
+	add3_ge5 A9 (w9,a9);
+	add3_ge5 A10 (w10,a10);
+	add3_ge5 A11 (w11,a11);
+	add3_ge5 A12 (w12,a12);
+	add3_ge5 A13 (w13,a13);
+	add3_ge5 A14 (w14,a14);
+	add3_ge5 A15 (w15,a15);
+	add3_ge5 A16 (w16,a16);
+	add3_ge5 A17 (w17,a17);
+	add3_ge5 A18 (w18,a18);
+	add3_ge5 A19 (w19,a19);
+	add3_ge5 A20 (w20,a20);
+	add3_ge5 A21 (w21,a21);
+	add3_ge5 A22 (w22,a22);
+	add3_ge5 A23 (w23,a23);
+	add3_ge5 A24 (w24,a24);
+	add3_ge5 A25 (w25,a25);
+	add3_ge5 A26 (w26,a26);
+	add3_ge5 A27 (w27,a27);
+	add3_ge5 A28 (w28,a28);
+	add3_ge5 A29 (w29,a29);
+		
+	// wire the tree of add3 modules together
+	assign  w1 = {B[14:11]};		// wn is the input port to module An
+	assign  w2 = {a1[2:0], B[10]};
+	assign  w3 = {1'b0, B[15], a1[3], a2[3]};
+	assign  w4 = {a2[2:0], B[9]};
+	assign  w5 = {a3[2:0], a4[3]};
+	assign  w6 = {a4[2:0], B[8]};
+	assign  w7 = {a5[2:0], a6[3]};
+	assign  w8 = {a6[2:0], B[7]};
+	assign  w9 = {1'b0, a3[3], a5[3], a7[3]};
+	assign  w10 = {a7[2:0], a8[3]};
+	assign  w11 = {a8[2:0], B[6]};
+	assign  w12 = {a9[2:0], a10[3]};
+	assign  w13 = {a10[2:0], a11[3]};
+	assign  w14 = {a11[2:0], B[5]};
+	assign  w15 = {a12[2:0], a13[3]};
+	assign  w16 = {a13[2:0], a14[3]};
+	assign  w17 = {a14[2:0], B[4]};
+	assign  w18 = {1'b0, a9[3], a12[3], a15[3]};
+	assign  w19 = {a15[2:0], a16[3]};
+	assign  w20 = {a16[2:0], a17[3]};
+	assign  w21 = {a17[2:0], B[3]};
+	assign  w22 = {a18[2:0], a19[3]};
+	assign  w23 = {a19[2:0], a20[3]};
+	assign  w24 = {a20[2:0], a21[3]};
+	assign  w25 = {a21[2:0], B[2]};
+	assign  w26 = {a22[2:0], a23[3]};
+	assign  w27 = {a23[2:0], a24[3]};
+	assign  w28 = {a24[2:0], a25[3]};
+	assign  w29 = {a25[2:0], B[1]};
+	
+	// connect up to four BCD digit outputs	
+	assign BCD_0 = {a29[2:0],B[0]};
+	assign BCD_1 = {a28[2:0],a29[3]};
+	assign BCD_2 = {a27[2:0],a28[3]};
+	assign BCD_3 = {a26[2:0],a27[3]};
+	assign BCD_4 = {1'b0, a18[3], a22[3], a26[3]};	
+endmodule
+
+	
+	
+
diff --git a/part_2/ex9_partially_working/verilog_files/tick_50000.v.bak b/part_3/mylib/tick_5000.v.bak
index 45c4166..97fcf8b 100755
--- a/part_2/ex9_partially_working/verilog_files/tick_50000.v.bak
+++ b/part_3/mylib/tick_5000.v.bak
@@ -11,7 +11,7 @@ module tick_50000(CLOCK_IN, CLK_OUT);
 	
 	initial 
 		begin
-			count = 16'd24999;
+			count = 16'd4999;
 			CLK_OUT = 1'b0;
 		end
 	
@@ -19,12 +19,13 @@ module tick_50000(CLOCK_IN, CLK_OUT);
 		begin
 			if(count == 16'b0)
 				begin
-					CLK_OUT <= ~CLK_OUT;
-					count <= 16'd24999;
+					CLK_OUT <= 1'b1;
+					count <= 16'd49999;
 				end
 			else
 				begin
 					count <= count - 1'b1;
+					CLK_OUT <= 1'b0;
 				end
 		end
 
diff --git a/part_4/ex16/add3_ge5.v b/part_4/ex16/add3_ge5.v
new file mode 100755
index 0000000..0daf78a
--- /dev/null
+++ b/part_4/ex16/add3_ge5.v
@@ -0,0 +1,31 @@
+//------------------------------
+// Module name: add3_ge5
+// Function: Add 3 to input if it is 5 or above
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     21 Jan 2014
+//------------------------------
+
+module add3_ge5(w,a); 
+	input [3:0] w; 
+	output [3:0] a; 
+	reg [3:0] a; 
+ 
+	always @ (w) 
+		case (w) 
+			4'b0000: a <= 4'b0000; 
+			4'b0001: a <= 4'b0001; 
+			4'b0010: a <= 4'b0010; 
+			4'b0011: a <= 4'b0011; 
+			4'b0100: a <= 4'b0100; 
+			4'b0101: a <= 4'b1000; 
+			4'b0110: a <= 4'b1001; 
+			4'b0111: a <= 4'b1010; 
+			4'b1000: a <= 4'b1011; 
+			4'b1001: a <= 4'b1100;
+			4'b1010: a <= 4'b1101;	
+			4'b1011: a <= 4'b1110;	
+			4'b1100: a <= 4'b1111;	
+			default: a <= 4'b0000; // a cannot be 13 or larger, else overflow
+		endcase 
+endmodule 
+\ No newline at end of file
diff --git a/part_4/ex16/allpass.v b/part_4/ex16/allpass.v
new file mode 100755
index 0000000..3535906
--- /dev/null
+++ b/part_4/ex16/allpass.v
@@ -0,0 +1,35 @@
+//------------------------------
+// Module name: allpass processor
+// Function: Simply to pass input to output
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     24 Jan 2014
+//------------------------------
+
+module processor (sysclk, data_in, data_out);
+
+	input				sysclk;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	// This part should include your own processing hardware 
+	// ... that takes x to produce y
+	// ... In this case, it is ALL PASS.
+	assign y = x;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_2/ex9_final/verilog_files/bin2bcd_16.v b/part_4/ex16/bin2bcd_16.v
index b25d0bd..b25d0bd 100755
--- a/part_2/ex9_final/verilog_files/bin2bcd_16.v
+++ b/part_4/ex16/bin2bcd_16.v
diff --git a/part_4/ex16/c5_pin_model_dump.txt b/part_4/ex16/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_4/ex16/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_4/ex16/clktick_16.v b/part_4/ex16/clktick_16.v
new file mode 100755
index 0000000..e6b99eb
--- /dev/null
+++ b/part_4/ex16/clktick_16.v
@@ -0,0 +1,42 @@
+// Design Name : clktick_16
+// File Name : clktick.v
+// Function : divide an input clock signal by n+1
+//-----------------------------------------------------
+
+module clktick_16 (
+  clkin, 	// Clock input to the design
+  enable,	// enable clk divider
+  N,			// Clock division factor is N+1
+  tick		// pulse_out goes high for one cycle (n+1) clock cycles
+); 			// 	End of port list
+
+parameter	N_BIT = 16;
+//-------------Input Ports-----------------------------
+input clkin;
+input enable;
+input [N_BIT-1:0] N;
+
+//-------------Output Ports----------------------------
+output 	tick;
+
+//-------------Output Ports Data Type------------------
+// Output port can be a storage element (reg) or a wire
+reg [N_BIT-1:0] count;
+reg			tick;
+
+initial		tick = 1'b0;
+
+//------------ Main Body of the module ------------------------
+
+	always @ (posedge clkin)  
+		if (enable == 1'b1)
+			if (count == 0)	begin
+				tick <= 1'b1;
+				count <= N;
+				end
+			else	begin
+				tick <= 1'b0;
+				count <= count - 1'b1;
+				end
+		
+endmodule // End of Module clktick
+\ No newline at end of file
diff --git a/part_4/ex16/db/.cmp.kpt b/part_4/ex16/db/.cmp.kpt
new file mode 100755
index 0000000..1b08559
--- /dev/null
+++ b/part_4/ex16/db/.cmp.kpt
diff --git a/part_4/ex16/db/add_sub_a9h.tdf b/part_4/ex16/db/add_sub_a9h.tdf
new file mode 100755
index 0000000..ef3fd5b
--- /dev/null
+++ b/part_4/ex16/db/add_sub_a9h.tdf
@@ -0,0 +1,32 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=15 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+
+--synthesis_resources = lut 15 
+SUBDESIGN add_sub_a9h
+( 
+	dataa[14..0]	:	input;
+	datab[14..0]	:	input;
+	result[14..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_4/ex16/db/add_sub_e9h.tdf b/part_4/ex16/db/add_sub_e9h.tdf
new file mode 100755
index 0000000..b85c02c
--- /dev/null
+++ b/part_4/ex16/db/add_sub_e9h.tdf
@@ -0,0 +1,32 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=19 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+
+--synthesis_resources = lut 19 
+SUBDESIGN add_sub_e9h
+( 
+	dataa[18..0]	:	input;
+	datab[18..0]	:	input;
+	result[18..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_4/ex16/db/add_sub_ffh.tdf b/part_4/ex16/db/add_sub_ffh.tdf
new file mode 100755
index 0000000..b4a4361
--- /dev/null
+++ b/part_4/ex16/db/add_sub_ffh.tdf
@@ -0,0 +1,31 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone III" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=15 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:24:09:15:20:SJ cbx_lpm_add_sub 2013:10:24:09:15:20:SJ cbx_mgl 2013:10:24:09:16:30:SJ cbx_stratix 2013:10:24:09:15:20:SJ cbx_stratixii 2013:10:24:09:15:20:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 15 
+SUBDESIGN add_sub_ffh
+( 
+	dataa[14..0]	:	input;
+	datab[14..0]	:	input;
+	result[14..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_4/ex16/db/add_sub_jfh.tdf b/part_4/ex16/db/add_sub_jfh.tdf
new file mode 100755
index 0000000..5d408b0
--- /dev/null
+++ b/part_4/ex16/db/add_sub_jfh.tdf
@@ -0,0 +1,31 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone III" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=19 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:24:09:15:20:SJ cbx_lpm_add_sub 2013:10:24:09:15:20:SJ cbx_mgl 2013:10:24:09:16:30:SJ cbx_stratix 2013:10:24:09:15:20:SJ cbx_stratixii 2013:10:24:09:15:20:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 19 
+SUBDESIGN add_sub_jfh
+( 
+	dataa[18..0]	:	input;
+	datab[18..0]	:	input;
+	result[18..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_4/ex16/db/altsyncram_ip02.tdf b/part_4/ex16/db/altsyncram_ip02.tdf
new file mode 100755
index 0000000..02ea039
--- /dev/null
+++ b/part_4/ex16/db/altsyncram_ip02.tdf
@@ -0,0 +1,361 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO" NUMWORDS_A=8192 NUMWORDS_B=8192 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=9 WIDTH_B=9 WIDTH_BYTEENA_A=1 WIDTHAD_A=13 WIDTHAD_B=13 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 9 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_ip02
+( 
+	address_a[12..0]	:	input;
+	address_b[12..0]	:	input;
+	clock0	:	input;
+	data_a[8..0]	:	input;
+	q_b[8..0]	:	output;
+	rden_b	:	input;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[12..0]	: WIRE;
+	address_b_wire[12..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[8..0].clk0 = clock0;
+	ram_block1a[8..0].clk1 = clock0;
+	ram_block1a[8..0].ena0 = wren_a;
+	ram_block1a[8..0].ena1 = rden_b;
+	ram_block1a[8..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[8].portadatain[] = ( data_a[8..8]);
+	ram_block1a[8..0].portawe = wren_a;
+	ram_block1a[8..0].portbaddr[] = ( address_b_wire[12..0]);
+	ram_block1a[8..0].portbre = B"111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block1a[8..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_4/ex16/db/altsyncram_phq1.tdf b/part_4/ex16/db/altsyncram_phq1.tdf
new file mode 100755
index 0000000..a908187
--- /dev/null
+++ b/part_4/ex16/db/altsyncram_phq1.tdf
@@ -0,0 +1,363 @@
+--altsyncram ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" NUMWORDS_A=8192 NUMWORDS_B=8192 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=9 WIDTH_B=9 WIDTH_BYTEENA_A=1 WIDTHAD_A=13 WIDTHAD_B=13 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:24:09:15:20:SJ cbx_cycloneii 2013:10:24:09:15:20:SJ cbx_lpm_add_sub 2013:10:24:09:15:20:SJ cbx_lpm_compare 2013:10:24:09:15:20:SJ cbx_lpm_decode 2013:10:24:09:15:20:SJ cbx_lpm_mux 2013:10:24:09:15:20:SJ cbx_mgl 2013:10:24:09:16:30:SJ cbx_stratix 2013:10:24:09:15:20:SJ cbx_stratixii 2013:10:24:09:15:20:SJ cbx_stratixiii 2013:10:24:09:15:20:SJ cbx_stratixv 2013:10:24:09:15:20:SJ cbx_util_mgl 2013:10:24:09:15:20:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 9 reg 1 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_phq1
+( 
+	address_a[12..0]	:	input;
+	address_b[12..0]	:	input;
+	clock0	:	input;
+	data_a[8..0]	:	input;
+	q_b[8..0]	:	output;
+	rden_b	:	input;
+	wren_a	:	input;
+) 
+VARIABLE 
+	rden_b_store : dffe;
+	ram_block1a0 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[12..0]	: WIRE;
+	address_b_wire[12..0]	: WIRE;
+
+BEGIN 
+	rden_b_store.clk = clock0;
+	rden_b_store.d = rden_b;
+	ram_block1a[8..0].clk0 = clock0;
+	ram_block1a[8..0].clk1 = clock0;
+	ram_block1a[8..0].ena0 = wren_a;
+	ram_block1a[8..0].ena1 = (rden_b_store.q # rden_b);
+	ram_block1a[8..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[8].portadatain[] = ( data_a[8..8]);
+	ram_block1a[8..0].portawe = wren_a;
+	ram_block1a[8..0].portbaddr[] = ( address_b_wire[12..0]);
+	ram_block1a[8..0].portbre = rden_b;
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block1a[8..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_4/ex16/db/ex16.map_bb.logdb b/part_4/ex16/db/ex16.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex16/db/ex16.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex16/db/ex16.smp_dump.txt b/part_4/ex16/db/ex16.smp_dump.txt
new file mode 100755
index 0000000..1690c2a
--- /dev/null
+++ b/part_4/ex16/db/ex16.smp_dump.txt
@@ -0,0 +1,12 @@
+
+State Machine - |ex16_top|spi2adc:SPI_ADC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
+
+State Machine - |ex16_top|spi2dac:SPI_DAC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
diff --git a/part_4/ex16/db/ex16_top.(0).cnf.cdb b/part_4/ex16/db/ex16_top.(0).cnf.cdb
new file mode 100755
index 0000000..f8653a8
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(0).cnf.cdb
diff --git a/part_4/ex16/db/ex16_top.(0).cnf.hdb b/part_4/ex16/db/ex16_top.(0).cnf.hdb
new file mode 100755
index 0000000..026fb17
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(0).cnf.hdb
diff --git a/part_4/ex16/db/ex16_top.(1).cnf.cdb b/part_4/ex16/db/ex16_top.(1).cnf.cdb
new file mode 100755
index 0000000..420b157
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(1).cnf.cdb
diff --git a/part_4/ex16/db/ex16_top.(1).cnf.hdb b/part_4/ex16/db/ex16_top.(1).cnf.hdb
new file mode 100755
index 0000000..2acd540
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(1).cnf.hdb
diff --git a/part_4/ex16/db/ex16_top.(2).cnf.cdb b/part_4/ex16/db/ex16_top.(2).cnf.cdb
new file mode 100755
index 0000000..19a56c2
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(2).cnf.cdb
diff --git a/part_4/ex16/db/ex16_top.(2).cnf.hdb b/part_4/ex16/db/ex16_top.(2).cnf.hdb
new file mode 100755
index 0000000..1a2a2b8
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(2).cnf.hdb
diff --git a/part_4/ex16/db/ex16_top.(3).cnf.cdb b/part_4/ex16/db/ex16_top.(3).cnf.cdb
new file mode 100755
index 0000000..fa14721
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(3).cnf.cdb
diff --git a/part_4/ex16/db/ex16_top.(3).cnf.hdb b/part_4/ex16/db/ex16_top.(3).cnf.hdb
new file mode 100755
index 0000000..9516637
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(3).cnf.hdb
diff --git a/part_4/ex16/db/ex16_top.(4).cnf.cdb b/part_4/ex16/db/ex16_top.(4).cnf.cdb
new file mode 100755
index 0000000..d16a8d5
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(4).cnf.cdb
diff --git a/part_4/ex16/db/ex16_top.(4).cnf.hdb b/part_4/ex16/db/ex16_top.(4).cnf.hdb
new file mode 100755
index 0000000..d3f3fab
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(4).cnf.hdb
diff --git a/part_4/ex16/db/ex16_top.(5).cnf.cdb b/part_4/ex16/db/ex16_top.(5).cnf.cdb
new file mode 100755
index 0000000..fd6db4d
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(5).cnf.cdb
diff --git a/part_4/ex16/db/ex16_top.(5).cnf.hdb b/part_4/ex16/db/ex16_top.(5).cnf.hdb
new file mode 100755
index 0000000..c74fa42
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(5).cnf.hdb
diff --git a/part_4/ex16/db/ex16_top.(6).cnf.cdb b/part_4/ex16/db/ex16_top.(6).cnf.cdb
new file mode 100755
index 0000000..a2a01e7
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(6).cnf.cdb
diff --git a/part_4/ex16/db/ex16_top.(6).cnf.hdb b/part_4/ex16/db/ex16_top.(6).cnf.hdb
new file mode 100755
index 0000000..9eaaff2
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(6).cnf.hdb
diff --git a/part_4/ex16/db/ex16_top.(7).cnf.cdb b/part_4/ex16/db/ex16_top.(7).cnf.cdb
new file mode 100755
index 0000000..c020e9a
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(7).cnf.cdb
diff --git a/part_4/ex16/db/ex16_top.(7).cnf.hdb b/part_4/ex16/db/ex16_top.(7).cnf.hdb
new file mode 100755
index 0000000..20c7823
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.(7).cnf.hdb
diff --git a/part_2/ex9_partially_working/db/ex9.asm.qmsg b/part_4/ex16/db/ex16_top.asm.qmsg
index 6d6746e..fc3419f 100755
--- a/part_2/ex9_partially_working/db/ex9.asm.qmsg
+++ b/part_4/ex16/db/ex16_top.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480073276145 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480073276148 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 11:27:55 2016 " "Processing started: Fri Nov 25 11:27:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480073276148 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480073276148 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480073276148 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480073276920 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480073281460 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480073281795 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 11:28:01 2016 " "Processing ended: Fri Nov 25 11:28:01 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480073281795 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480073281795 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480073281795 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480073281795 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480671207894 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480671207896 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:33:27 2016 " "Processing started: Fri Dec 02 09:33:27 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480671207896 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480671207896 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex16 -c ex16_top " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480671207897 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480671208694 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480671213271 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480671213612 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:33:33 2016 " "Processing ended: Fri Dec 02 09:33:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480671213612 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480671213612 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480671213612 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480671213612 ""}
diff --git a/part_4/ex16/db/ex16_top.asm.rdb b/part_4/ex16/db/ex16_top.asm.rdb
new file mode 100755
index 0000000..95864f5
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.asm.rdb
diff --git a/part_4/ex16/db/ex16_top.cbx.xml b/part_4/ex16/db/ex16_top.cbx.xml
new file mode 100755
index 0000000..47f4f93
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ex16_top">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/part_4/ex16/db/ex16_top.cmp.ammdb b/part_4/ex16/db/ex16_top.cmp.ammdb
new file mode 100755
index 0000000..393c412
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cmp.ammdb
diff --git a/part_4/ex16/db/ex16_top.cmp.bpm b/part_4/ex16/db/ex16_top.cmp.bpm
new file mode 100755
index 0000000..1e425dd
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cmp.bpm
diff --git a/part_4/ex16/db/ex16_top.cmp.cdb b/part_4/ex16/db/ex16_top.cmp.cdb
new file mode 100755
index 0000000..f10c8b1
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cmp.cdb
diff --git a/part_4/ex16/db/ex16_top.cmp.hdb b/part_4/ex16/db/ex16_top.cmp.hdb
new file mode 100755
index 0000000..7a67a1d
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cmp.hdb
diff --git a/part_4/ex16/db/ex16_top.cmp.idb b/part_4/ex16/db/ex16_top.cmp.idb
new file mode 100755
index 0000000..306c746
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cmp.idb
diff --git a/part_4/ex16/db/ex16_top.cmp.logdb b/part_4/ex16/db/ex16_top.cmp.logdb
new file mode 100755
index 0000000..e044ed7
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cmp.logdb
@@ -0,0 +1,80 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,41;0;41;0;0;41;41;0;41;41;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;41;0;41;41;0;0;41;0;0;41;41;41;41;41;41;41;41;41;41;41;41;41;41;41;41;41;41,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_LD,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PWM_OUT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDO,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_4/ex16/db/ex16_top.cmp.rdb b/part_4/ex16/db/ex16_top.cmp.rdb
new file mode 100755
index 0000000..d065d27
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cmp.rdb
diff --git a/part_4/ex16/db/ex16_top.cmp_merge.kpt b/part_4/ex16/db/ex16_top.cmp_merge.kpt
new file mode 100755
index 0000000..f7afd56
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cmp_merge.kpt
diff --git a/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..da61997
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..acc52a8
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_4/ex16/db/ex16_top.db_info b/part_4/ex16/db/ex16_top.db_info
new file mode 100755
index 0000000..c4a8cf8
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Dec 02 09:19:56 2016
diff --git a/part_4/ex16/db/ex16_top.eda.qmsg b/part_4/ex16/db/ex16_top.eda.qmsg
new file mode 100755
index 0000000..9355630
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.eda.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480671221051 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480671221053 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:33:40 2016 " "Processing started: Fri Dec 02 09:33:40 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480671221053 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480671221053 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480671221053 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1480671221998 ""}
+{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1480671222032 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ex16_top.vo C:/New folder/ex16/simulation/modelsim/ simulation " "Generated file ex16_top.vo in folder \"C:/New folder/ex16/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1480671222180 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "811 " "Peak virtual memory: 811 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480671222238 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:33:42 2016 " "Processing ended: Fri Dec 02 09:33:42 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480671222238 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480671222238 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480671222238 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1480671222238 ""}
diff --git a/part_4/ex16/db/ex16_top.fit.qmsg b/part_4/ex16/db/ex16_top.fit.qmsg
new file mode 100755
index 0000000..4105fad
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.fit.qmsg
@@ -0,0 +1,46 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480671177278 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480671177279 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex16_top 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex16_top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480671177531 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480671177619 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480671177620 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480671178005 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480671178145 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480671188182 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 57 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 57 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480671188264 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480671188264 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480671188265 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480671188268 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480671188268 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480671188269 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480671188270 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480671188270 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480671188270 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex16_top.sdc " "Reading SDC File: 'ex16_top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1480671188843 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[0\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[0\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671188846 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1480671188846 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[15\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[15\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671188846 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1480671188846 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480671188847 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480671188847 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1480671188848 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1480671188848 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1480671188848 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1480671188848 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1480671188848 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480671188858 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480671188858 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480671188858 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480671188897 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480671188897 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480671188898 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480671193815 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480671194006 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480671194553 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480671195256 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480671195578 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480671195578 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480671196636 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X78_Y0 X89_Y10 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex16/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10"} { { 12 { 0 ""} 78 0 12 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480671201049 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480671201049 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480671201341 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1480671201341 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480671201341 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480671201345 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480671202683 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480671202722 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480671203078 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480671203078 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480671203426 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480671205826 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480671206065 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex16/ex16_top.fit.smsg " "Generated suppressed messages file C:/New folder/ex16/ex16_top.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480671206121 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 46 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 46 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2590 " "Peak virtual memory: 2590 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480671206559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:33:26 2016 " "Processing ended: Fri Dec 02 09:33:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480671206559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480671206559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:52 " "Total CPU time (on all processors): 00:00:52" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480671206559 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480671206559 ""}
diff --git a/part_4/ex16/db/ex16_top.hier_info b/part_4/ex16/db/ex16_top.hier_info
new file mode 100755
index 0000000..b25efc2
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.hier_info
@@ -0,0 +1,276 @@
+|ex16_top
+CLOCK_50 => CLOCK_50.IN5
+SW[0] => ~NO_FANOUT~
+SW[1] => ~NO_FANOUT~
+SW[2] => ~NO_FANOUT~
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => ~NO_FANOUT~
+SW[8] => ~NO_FANOUT~
+SW[9] => ~NO_FANOUT~
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+DAC_SDI << spi2dac:SPI_DAC.port3
+DAC_SCK << spi2dac:SPI_DAC.port5
+DAC_CS << spi2dac:SPI_DAC.port4
+DAC_LD << spi2dac:SPI_DAC.port6
+ADC_SDI << spi2adc:SPI_ADC.sdata_to_adc
+ADC_SCK << spi2adc:SPI_ADC.adc_sck
+ADC_CS << spi2adc:SPI_ADC.adc_cs
+ADC_SDO => ADC_SDO.IN1
+PWM_OUT << pwm:PWM_DC.port3
+
+
+|ex16_top|clktick_16:GEN_10K
+clkin => count[0].CLK
+clkin => count[1].CLK
+clkin => count[2].CLK
+clkin => count[3].CLK
+clkin => count[4].CLK
+clkin => count[5].CLK
+clkin => count[6].CLK
+clkin => count[7].CLK
+clkin => count[8].CLK
+clkin => count[9].CLK
+clkin => count[10].CLK
+clkin => count[11].CLK
+clkin => count[12].CLK
+clkin => count[13].CLK
+clkin => count[14].CLK
+clkin => count[15].CLK
+clkin => tick~reg0.CLK
+enable => count[0].ENA
+enable => count[1].ENA
+enable => count[2].ENA
+enable => count[3].ENA
+enable => count[4].ENA
+enable => count[5].ENA
+enable => count[6].ENA
+enable => count[7].ENA
+enable => count[8].ENA
+enable => count[9].ENA
+enable => count[10].ENA
+enable => count[11].ENA
+enable => count[12].ENA
+enable => count[13].ENA
+enable => count[14].ENA
+enable => count[15].ENA
+enable => tick~reg0.ENA
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => count.DATAB
+N[8] => count.DATAB
+N[9] => count.DATAB
+N[10] => count.DATAB
+N[11] => count.DATAB
+N[12] => count.DATAB
+N[13] => count.DATAB
+N[14] => count.DATAB
+N[15] => count.DATAB
+tick <= tick~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex16_top|spi2dac:SPI_DAC
+clk => dac_start.CLK
+clk => clk_1MHz.CLK
+clk => ctr[0].CLK
+clk => ctr[1].CLK
+clk => ctr[2].CLK
+clk => ctr[3].CLK
+clk => ctr[4].CLK
+clk => sr_state~1.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => Selector1.IN1
+load => dac_start.OUTPUTSELECT
+load => Selector0.IN1
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= dac_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= dac_ld~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex16_top|pwm:PWM_DC
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex16_top|spi2adc:SPI_ADC
+sysclk => adc_start.CLK
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~1.DATAIN
+start => Selector1.IN1
+start => adc_start.OUTPUTSELECT
+start => Selector0.IN1
+channel => Selector6.IN6
+data_from_adc[0] <= data_from_adc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[1] <= data_from_adc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[2] <= data_from_adc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[3] <= data_from_adc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[4] <= data_from_adc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[5] <= data_from_adc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[6] <= data_from_adc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[7] <= data_from_adc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[8] <= data_from_adc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[9] <= data_from_adc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+sdata_to_adc <= adc_din.DB_MAX_OUTPUT_PORT_TYPE
+adc_cs <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+adc_sck <= adc_sck.DB_MAX_OUTPUT_PORT_TYPE
+sdata_from_adc => shift_reg[0].DATAIN
+
+
+|ex16_top|processor:ALLPASS
+sysclk => data_out[0]~reg0.CLK
+sysclk => data_out[1]~reg0.CLK
+sysclk => data_out[2]~reg0.CLK
+sysclk => data_out[3]~reg0.CLK
+sysclk => data_out[4]~reg0.CLK
+sysclk => data_out[5]~reg0.CLK
+sysclk => data_out[6]~reg0.CLK
+sysclk => data_out[7]~reg0.CLK
+sysclk => data_out[8]~reg0.CLK
+sysclk => data_out[9]~reg0.CLK
+data_in[0] => Add0.IN20
+data_in[1] => Add0.IN19
+data_in[2] => Add0.IN18
+data_in[3] => Add0.IN17
+data_in[4] => Add0.IN16
+data_in[5] => Add0.IN15
+data_in[6] => Add0.IN14
+data_in[7] => Add0.IN13
+data_in[8] => Add0.IN12
+data_in[9] => Add0.IN11
+data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex16_top|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex16_top|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex16_top|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_4/ex16/db/ex16_top.hif b/part_4/ex16/db/ex16_top.hif
new file mode 100755
index 0000000..0c4b526
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.hif
diff --git a/part_4/ex16/db/ex16_top.lpc.html b/part_4/ex16/db/ex16_top.lpc.html
new file mode 100755
index 0000000..355a99e
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.lpc.html
@@ -0,0 +1,146 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >7</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_ADC</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >14</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >PWM_DC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_DAC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >GEN_10K</TD>
+<TD >18</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >17</TD>
+<TD >1</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_4/ex16/db/ex16_top.lpc.rdb b/part_4/ex16/db/ex16_top.lpc.rdb
new file mode 100755
index 0000000..900867d
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.lpc.rdb
diff --git a/part_4/ex16/db/ex16_top.lpc.txt b/part_4/ex16/db/ex16_top.lpc.txt
new file mode 100755
index 0000000..293e7b5
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.lpc.txt
@@ -0,0 +1,14 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG2      ; 4     ; 2              ; 0            ; 2              ; 7      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG1      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG0      ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS   ; 11    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_ADC   ; 4     ; 1              ; 0            ; 1              ; 14     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; PWM_DC    ; 12    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_DAC   ; 12    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; GEN_10K   ; 18    ; 17             ; 0            ; 17             ; 1      ; 17              ; 17            ; 17              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_4/ex16/db/ex16_top.map.ammdb b/part_4/ex16/db/ex16_top.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map.ammdb
diff --git a/part_4/ex16/db/ex16_top.map.bpm b/part_4/ex16/db/ex16_top.map.bpm
new file mode 100755
index 0000000..a72f506
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map.bpm
diff --git a/part_4/ex16/db/ex16_top.map.cdb b/part_4/ex16/db/ex16_top.map.cdb
new file mode 100755
index 0000000..7a654a2
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map.cdb
diff --git a/part_4/ex16/db/ex16_top.map.hdb b/part_4/ex16/db/ex16_top.map.hdb
new file mode 100755
index 0000000..afad4bb
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map.hdb
diff --git a/part_4/ex16/db/ex16_top.map.kpt b/part_4/ex16/db/ex16_top.map.kpt
new file mode 100755
index 0000000..2ae2b23
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map.kpt
diff --git a/part_4/ex16/db/ex16_top.map.qmsg b/part_4/ex16/db/ex16_top.map.qmsg
new file mode 100755
index 0000000..ecbe741
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map.qmsg
@@ -0,0 +1,26 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480671166579 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480671166580 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:32:46 2016 " "Processing started: Fri Dec 02 09:32:46 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480671166580 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671166580 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex16 -c ex16_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671166580 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480671167068 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480671167068 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "hex_to_7seg.v" "" { Text "C:/New folder/ex16/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480671174439 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671174439 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" {  } { { "clktick_16.v" "" { Text "C:/New folder/ex16/clktick_16.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480671174441 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671174441 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "spi2dac.v" "" { Text "C:/New folder/ex16/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480671174442 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671174442 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "spi2adc.v" "" { Text "C:/New folder/ex16/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480671174444 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671174444 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "pwm.v" "" { Text "C:/New folder/ex16/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480671174445 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671174445 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "delay_ram.v" "" { Text "C:/New folder/ex16/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480671174447 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671174447 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex16_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ex16_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex16_top " "Found entity 1: ex16_top" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480671174449 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671174449 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult4.v 1 1 " "Found 1 design units, including 1 entities, in source file mult4.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "mult4.v" "" { Text "C:/New folder/ex16/mult4.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480671174450 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671174450 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex16_top " "Elaborating entity \"ex16_top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480671174476 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clktick_16 clktick_16:GEN_10K " "Elaborating entity \"clktick_16\" for hierarchy \"clktick_16:GEN_10K\"" {  } { { "ex16_top.v" "GEN_10K" { Text "C:/New folder/ex16/ex16_top.v" 32 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480671174480 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" {  } { { "ex16_top.v" "SPI_DAC" { Text "C:/New folder/ex16/ex16_top.v" 34 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480671174482 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" {  } { { "ex16_top.v" "PWM_DC" { Text "C:/New folder/ex16/ex16_top.v" 35 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480671174483 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "ex16_top.v" "SPI_ADC" { Text "C:/New folder/ex16/ex16_top.v" 46 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480671174484 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:ALLPASS " "Elaborating entity \"processor\" for hierarchy \"processor:ALLPASS\"" {  } { { "ex16_top.v" "ALLPASS" { Text "C:/New folder/ex16/ex16_top.v" 48 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480671174485 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex16_top.v" "SEG0" { Text "C:/New folder/ex16/ex16_top.v" 50 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480671174491 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 15 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480671174971 "|ex16_top|HEX2[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480671174971 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480671175047 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480671175336 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480671175336 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "10 " "Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "No output dependent on input pin \"SW\[5\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "No output dependent on input pin \"SW\[6\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "No output dependent on input pin \"SW\[7\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[8]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480671175373 "|ex16_top|SW[9]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480671175373 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "178 " "Implemented 178 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480671175374 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480671175374 ""} { "Info" "ICUT_CUT_TM_LCELLS" "137 " "Implemented 137 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480671175374 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480671175374 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "898 " "Peak virtual memory: 898 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480671175385 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:32:55 2016 " "Processing ended: Fri Dec 02 09:32:55 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480671175385 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480671175385 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480671175385 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480671175385 ""}
diff --git a/part_4/ex16/db/ex16_top.map.rdb b/part_4/ex16/db/ex16_top.map.rdb
new file mode 100755
index 0000000..49ac9f8
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map.rdb
diff --git a/part_4/ex16/db/ex16_top.map_bb.cdb b/part_4/ex16/db/ex16_top.map_bb.cdb
new file mode 100755
index 0000000..37f73a6
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map_bb.cdb
diff --git a/part_4/ex16/db/ex16_top.map_bb.hdb b/part_4/ex16/db/ex16_top.map_bb.hdb
new file mode 100755
index 0000000..97dea75
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.map_bb.hdb
diff --git a/part_4/ex16/db/ex16_top.pplq.rdb b/part_4/ex16/db/ex16_top.pplq.rdb
new file mode 100755
index 0000000..8627bdd
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.pplq.rdb
diff --git a/part_4/ex16/db/ex16_top.pre_map.hdb b/part_4/ex16/db/ex16_top.pre_map.hdb
new file mode 100755
index 0000000..8b0bd2d
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.pre_map.hdb
diff --git a/part_4/ex16/db/ex16_top.root_partition.map.reg_db.cdb b/part_4/ex16/db/ex16_top.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..a5fa6c5
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.root_partition.map.reg_db.cdb
diff --git a/part_4/ex16/db/ex16_top.routing.rdb b/part_4/ex16/db/ex16_top.routing.rdb
new file mode 100755
index 0000000..d2de109
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.routing.rdb
diff --git a/part_4/ex16/db/ex16_top.rtlv.hdb b/part_4/ex16/db/ex16_top.rtlv.hdb
new file mode 100755
index 0000000..fb23b1d
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.rtlv.hdb
diff --git a/part_4/ex16/db/ex16_top.rtlv_sg.cdb b/part_4/ex16/db/ex16_top.rtlv_sg.cdb
new file mode 100755
index 0000000..40440c3
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.rtlv_sg.cdb
diff --git a/part_4/ex16/db/ex16_top.rtlv_sg_swap.cdb b/part_4/ex16/db/ex16_top.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..f81a911
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.rtlv_sg_swap.cdb
diff --git a/part_4/ex16/db/ex16_top.sld_design_entry.sci b/part_4/ex16/db/ex16_top.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.sld_design_entry.sci
diff --git a/part_4/ex16/db/ex16_top.sld_design_entry_dsc.sci b/part_4/ex16/db/ex16_top.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.sld_design_entry_dsc.sci
diff --git a/part_4/ex16/db/ex16_top.smart_action.txt b/part_4/ex16/db/ex16_top.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/part_4/ex16/db/ex16_top.sta.qmsg b/part_4/ex16/db/ex16_top.sta.qmsg
new file mode 100755
index 0000000..627bc20
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.sta.qmsg
@@ -0,0 +1,54 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480671215110 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480671215110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:33:34 2016 " "Processing started: Fri Dec 02 09:33:34 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480671215110 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671215110 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex16 -c ex16_top " "Command: quartus_sta ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671215111 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480671215236 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671215804 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671215804 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671215851 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671215851 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex16_top.sdc " "Reading SDC File: 'ex16_top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216371 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[6\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[6\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671216374 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216374 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[15\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[15\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671216374 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216374 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216375 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216375 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480671216376 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480671216383 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 16.666 " "Worst-case setup slack is 16.666" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216390 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216390 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.666               0.000 CLOCK_50  " "   16.666               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216390 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216390 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.384 " "Worst-case hold slack is 0.384" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.384               0.000 CLOCK_50  " "    0.384               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216392 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216392 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216394 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216395 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.792 " "Worst-case minimum pulse width slack is 8.792" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216397 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.792               0.000 CLOCK_50  " "    8.792               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671216397 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216397 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480671216406 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671216443 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217258 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[6\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[6\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671217311 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217311 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[15\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[15\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671217312 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217312 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217312 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 16.665 " "Worst-case setup slack is 16.665" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217318 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.665               0.000 CLOCK_50  " "   16.665               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217318 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217318 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.383 " "Worst-case hold slack is 0.383" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217320 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217320 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.383               0.000 CLOCK_50  " "    0.383               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217320 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217320 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217322 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217324 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.734 " "Worst-case minimum pulse width slack is 8.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217325 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217325 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.734               0.000 CLOCK_50  " "    8.734               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671217325 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217325 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480671217334 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671217479 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218165 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[6\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[6\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671218219 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218219 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[15\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[15\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671218219 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218219 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218220 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.894 " "Worst-case setup slack is 17.894" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.894               0.000 CLOCK_50  " "   17.894               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218222 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218222 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.184 " "Worst-case hold slack is 0.184" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.184               0.000 CLOCK_50  " "    0.184               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218224 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218224 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218226 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218227 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.648 " "Worst-case minimum pulse width slack is 8.648" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.648               0.000 CLOCK_50  " "    8.648               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218229 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218229 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480671218238 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[6\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[6\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671218382 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218382 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[15\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[15\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480671218382 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218382 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218383 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.997 " "Worst-case setup slack is 17.997" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.997               0.000 CLOCK_50  " "   17.997               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218385 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218385 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.176 " "Worst-case hold slack is 0.176" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218388 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.176               0.000 CLOCK_50  " "    0.176               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218388 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218388 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218389 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218391 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.612 " "Worst-case minimum pulse width slack is 8.612" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218393 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.612               0.000 CLOCK_50  " "    8.612               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480671218393 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671218393 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671219739 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671219739 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 9 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1208 " "Peak virtual memory: 1208 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480671219781 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:33:39 2016 " "Processing ended: Fri Dec 02 09:33:39 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480671219781 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480671219781 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480671219781 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480671219781 ""}
diff --git a/part_4/ex16/db/ex16_top.sta.rdb b/part_4/ex16/db/ex16_top.sta.rdb
new file mode 100755
index 0000000..da66661
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.sta.rdb
diff --git a/part_4/ex16/db/ex16_top.sta_cmp.6_slow_1100mv_85c.tdb b/part_4/ex16/db/ex16_top.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..83c64bd
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_4/ex16/db/ex16_top.tis_db_list.ddb b/part_4/ex16/db/ex16_top.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.tis_db_list.ddb
diff --git a/part_4/ex16/db/ex16_top.tiscmp.fast_1100mv_0c.ddb b/part_4/ex16/db/ex16_top.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..65fa028
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_4/ex16/db/ex16_top.tiscmp.fast_1100mv_85c.ddb b/part_4/ex16/db/ex16_top.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..870ffdb
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_4/ex16/db/ex16_top.tiscmp.slow_1100mv_0c.ddb b/part_4/ex16/db/ex16_top.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..f963fee
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_4/ex16/db/ex16_top.tiscmp.slow_1100mv_85c.ddb b/part_4/ex16/db/ex16_top.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..aeba900
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_4/ex16/db/ex16_top.tmw_info b/part_4/ex16/db/ex16_top.tmw_info
new file mode 100755
index 0000000..c1f6658
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:57
+start_analysis_synthesis:s:00:00:10-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:32-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:06-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/part_4/ex16/db/ex16_top.vpr.ammdb b/part_4/ex16/db/ex16_top.vpr.ammdb
new file mode 100755
index 0000000..fbea6da
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.vpr.ammdb
diff --git a/part_4/ex16/db/ex16_top_partition_pins.json b/part_4/ex16/db/ex16_top_partition_pins.json
new file mode 100755
index 0000000..884712b
--- /dev/null
+++ b/part_4/ex16/db/ex16_top_partition_pins.json
@@ -0,0 +1,129 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_LD",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "PWM_OUT",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDO",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
+\ No newline at end of file
diff --git a/part_4/ex16/db/logic_util_heursitic.dat b/part_4/ex16/db/logic_util_heursitic.dat
new file mode 100755
index 0000000..f0e6fa0
--- /dev/null
+++ b/part_4/ex16/db/logic_util_heursitic.dat
diff --git a/part_4/ex16/db/prev_cmp_ex16.qmsg b/part_4/ex16/db/prev_cmp_ex16.qmsg
new file mode 100755
index 0000000..9563fd9
--- /dev/null
+++ b/part_4/ex16/db/prev_cmp_ex16.qmsg
@@ -0,0 +1,147 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480670816941 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480670816943 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:26:56 2016 " "Processing started: Fri Dec 02 09:26:56 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480670816943 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670816943 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex16 -c ex16_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670816944 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480670817483 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480670817483 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "hex_to_7seg.v" "" { Text "C:/New folder/ex16/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480670825753 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670825753 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" {  } { { "clktick_16.v" "" { Text "C:/New folder/ex16/clktick_16.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480670825755 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670825755 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "spi2dac.v" "" { Text "C:/New folder/ex16/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480670825756 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670825756 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "spi2adc.v" "" { Text "C:/New folder/ex16/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480670825758 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670825758 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "pwm.v" "" { Text "C:/New folder/ex16/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480670825759 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670825759 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "delay_ram.v" "" { Text "C:/New folder/ex16/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480670825761 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670825761 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "allpass.v 1 1 " "Found 1 design units, including 1 entities, in source file allpass.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "allpass.v" "" { Text "C:/New folder/ex16/allpass.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480670825763 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670825763 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex16_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ex16_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex16_top " "Found entity 1: ex16_top" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480670825764 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670825764 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex16_top " "Elaborating entity \"ex16_top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480670825801 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clktick_16 clktick_16:GEN_10K " "Elaborating entity \"clktick_16\" for hierarchy \"clktick_16:GEN_10K\"" {  } { { "ex16_top.v" "GEN_10K" { Text "C:/New folder/ex16/ex16_top.v" 32 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480670825820 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" {  } { { "ex16_top.v" "SPI_DAC" { Text "C:/New folder/ex16/ex16_top.v" 34 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480670825828 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" {  } { { "ex16_top.v" "PWM_DC" { Text "C:/New folder/ex16/ex16_top.v" 35 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480670825836 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "ex16_top.v" "SPI_ADC" { Text "C:/New folder/ex16/ex16_top.v" 46 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480670825841 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:ALLPASS " "Elaborating entity \"processor\" for hierarchy \"processor:ALLPASS\"" {  } { { "ex16_top.v" "ALLPASS" { Text "C:/New folder/ex16/ex16_top.v" 48 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480670825848 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex16_top.v" "SEG0" { Text "C:/New folder/ex16/ex16_top.v" 50 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480670825852 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 15 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480670826449 "|ex16_top|HEX2[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480670826449 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480670826535 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480670826904 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480670826904 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "10 " "Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "No output dependent on input pin \"SW\[5\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "No output dependent on input pin \"SW\[6\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "No output dependent on input pin \"SW\[7\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[8]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "ex16_top.v" "" { Text "C:/New folder/ex16/ex16_top.v" 14 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480670827120 "|ex16_top|SW[9]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480670827120 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "189 " "Implemented 189 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480670827121 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480670827121 ""} { "Info" "ICUT_CUT_TM_LCELLS" "148 " "Implemented 148 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480670827121 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480670827121 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480670827133 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:27:07 2016 " "Processing ended: Fri Dec 02 09:27:07 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480670827133 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480670827133 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480670827133 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480670827133 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1480670829197 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480670829198 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:27:08 2016 " "Processing started: Fri Dec 02 09:27:08 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480670829198 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1480670829198 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex16 -c ex16_top " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1480670829198 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1480670829464 ""}
+{ "Info" "0" "" "Project  = ex16" {  } {  } 0 0 "Project  = ex16" 0 0 "Fitter" 0 0 1480670829465 ""}
+{ "Info" "0" "" "Revision = ex16_top" {  } {  } 0 0 "Revision = ex16_top" 0 0 "Fitter" 0 0 1480670829465 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480670829594 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480670829595 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex16_top 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex16_top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480670829877 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480670830007 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480670830007 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480670830416 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480670830737 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480670840916 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 61 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 61 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480670841004 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480670841004 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480670841004 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480670841026 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480670841027 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480670841028 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480670841028 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480670841029 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480670841029 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex16_top.sdc " "Reading SDC File: 'ex16_top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1480670841668 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[0\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[0\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670841671 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1480670841671 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670841671 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1480670841671 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480670841673 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480670841673 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1480670841674 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1480670841674 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1480670841674 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1480670841674 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1480670841674 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480670841685 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480670841685 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480670841685 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480670841750 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480670841750 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480670841751 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480670846806 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480670847016 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480670847746 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480670848489 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480670848833 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480670848833 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480670849945 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X67_Y0 X77_Y10 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex16/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10"} { { 12 { 0 ""} 67 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480670854424 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480670854424 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480670854744 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1480670854744 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480670854744 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480670854748 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480670856282 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480670856328 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480670856710 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480670856710 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480670857059 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480670859473 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480670859715 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex16/ex16_top.fit.smsg " "Generated suppressed messages file C:/New folder/ex16/ex16_top.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480670859797 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 46 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 46 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2589 " "Peak virtual memory: 2589 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480670860255 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:27:40 2016 " "Processing ended: Fri Dec 02 09:27:40 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480670860255 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480670860255 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:54 " "Total CPU time (on all processors): 00:00:54" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480670860255 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480670860255 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1480670862017 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480670862020 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:27:41 2016 " "Processing started: Fri Dec 02 09:27:41 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480670862020 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480670862020 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex16 -c ex16_top " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480670862020 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480670862795 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480670867718 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "891 " "Peak virtual memory: 891 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480670868097 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:27:48 2016 " "Processing ended: Fri Dec 02 09:27:48 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480670868097 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480670868097 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480670868097 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480670868097 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1480670868900 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1480670869814 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480670869815 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:27:49 2016 " "Processing started: Fri Dec 02 09:27:49 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480670869815 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670869815 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex16 -c ex16_top " "Command: quartus_sta ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670869815 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480670869998 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670870618 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670870618 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670870665 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670870665 ""}
+{ "Info" "ISTA_SDC_FOUND" "ex16_top.sdc " "Reading SDC File: 'ex16_top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871195 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[3\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[3\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670871198 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871198 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670871198 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871198 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871199 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871200 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480670871201 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480670871208 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 16.406 " "Worst-case setup slack is 16.406" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871215 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871215 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.406               0.000 CLOCK_50  " "   16.406               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871215 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871215 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.384 " "Worst-case hold slack is 0.384" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871217 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.384               0.000 CLOCK_50  " "    0.384               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871217 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871217 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871220 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871221 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.903 " "Worst-case minimum pulse width slack is 8.903" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.903               0.000 CLOCK_50  " "    8.903               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670871223 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871223 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480670871234 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670871272 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872119 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[3\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[3\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670872173 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872173 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670872173 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872173 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872173 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 16.310 " "Worst-case setup slack is 16.310" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872179 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872179 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.310               0.000 CLOCK_50  " "   16.310               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872179 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872179 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.378 " "Worst-case hold slack is 0.378" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872181 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.378               0.000 CLOCK_50  " "    0.378               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872181 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872181 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872183 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872184 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.841 " "Worst-case minimum pulse width slack is 8.841" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872186 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872186 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.841               0.000 CLOCK_50  " "    8.841               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670872186 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872186 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480670872195 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670872348 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873054 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[3\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[3\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670873114 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873114 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670873114 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873114 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873115 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.639 " "Worst-case setup slack is 17.639" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873118 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873118 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.639               0.000 CLOCK_50  " "   17.639               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873118 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873118 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.189 " "Worst-case hold slack is 0.189" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.189               0.000 CLOCK_50  " "    0.189               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873120 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873120 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873122 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873124 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.768 " "Worst-case minimum pulse width slack is 8.768" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.768               0.000 CLOCK_50  " "    8.768               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873126 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873126 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480670873136 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[3\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[3\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670873280 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873280 "|ex16_top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1480670873281 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873281 "|ex16_top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873281 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 17.754 " "Worst-case setup slack is 17.754" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873284 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873284 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.754               0.000 CLOCK_50  " "   17.754               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873284 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873284 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.181 " "Worst-case hold slack is 0.181" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.181               0.000 CLOCK_50  " "    0.181               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873287 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873287 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873288 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873290 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.708 " "Worst-case minimum pulse width slack is 8.708" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.708               0.000 CLOCK_50  " "    8.708               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480670873292 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670873292 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670874634 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670874642 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 9 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1210 " "Peak virtual memory: 1210 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480670874685 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:27:54 2016 " "Processing ended: Fri Dec 02 09:27:54 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480670874685 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480670874685 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480670874685 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670874685 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480670876135 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480670876136 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 09:27:55 2016 " "Processing started: Fri Dec 02 09:27:55 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480670876136 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480670876136 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top " "Command: quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1480670876136 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1480670877050 ""}
+{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1480670877092 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "ex16_top.vo C:/New folder/ex16/simulation/modelsim/ simulation " "Generated file ex16_top.vo in folder \"C:/New folder/ex16/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1480670877265 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "807 " "Peak virtual memory: 807 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480670877327 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 09:27:57 2016 " "Processing ended: Fri Dec 02 09:27:57 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480670877327 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480670877327 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480670877327 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1480670877327 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 72 s " "Quartus Prime Full Compilation was successful. 0 errors, 72 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1480670877967 ""}
diff --git a/part_4/ex16/db/prev_cmp_top.qmsg b/part_4/ex16/db/prev_cmp_top.qmsg
new file mode 100755
index 0000000..1002da2
--- /dev/null
+++ b/part_4/ex16/db/prev_cmp_top.qmsg
@@ -0,0 +1,228 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1477834980986 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477834981033 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 13:43:00 2016 " "Processing started: Sun Oct 30 13:43:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477834981033 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477834981033 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477834981033 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1477834981751 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Analysis & Synthesis" 0 -1 1477834981751 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "delay DELAY echo_feedback.v(15) " "Verilog HDL Declaration information at echo_feedback.v(15): object \"delay\" differs only in case from object \"DELAY\" in the same scope" {  } { { "echo_feedback.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/echo_feedback.v" 15 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835013877 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "echo_feedback.v 1 1 " "Found 1 design units, including 1 entities, in source file echo_feedback.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "echo_feedback.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/echo_feedback.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835013892 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835013892 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "pwm.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835013908 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835013908 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "edge_detect.v " "Can't analyze file -- file edge_detect.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1477835013908 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" {  } { { "pulse_gen.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/pulse_gen.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835013923 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835013923 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835013970 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835013970 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "ROM.v " "Can't analyze file -- file ROM.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1477835013970 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" {  } { { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835013986 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835013986 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "hex_to_7seg.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835014017 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835014017 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_div.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Found entity 1: clk_div" {  } { { "clk_div.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/clk_div.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835014017 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835014017 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014033 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bin2bcd.v 1 1 " "Found 1 design units, including 1 entities, in source file bin2bcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd " "Found entity 1: bin2bcd" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835014064 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835014064 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "add3_ge5.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835014080 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835014080 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "accumulator.v " "Can't analyze file -- file accumulator.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1477835014080 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "spi2dac.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835014111 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835014111 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "spi2adc.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835014127 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835014127 ""}
+{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "LEDG top.v(66) " "Verilog HDL Implicit Net warning at top.v(66): created implicit net for \"LEDG\"" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 66 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014127 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1477835014455 ""}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "LEDG top.v(66) " "Verilog HDL or VHDL warning at top.v(66): object \"LEDG\" assigned a value but never read" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 66 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1477835014470 "|top"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 1 top.v(66) " "Verilog HDL assignment warning at top.v(66): truncated value with size 10 to match size of target (1)" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1477835014470 "|top"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_div clk_div:GEN_10K " "Elaborating entity \"clk_div\" for hierarchy \"clk_div:GEN_10K\"" {  } { { "top.v" "GEN_10K" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014564 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulse_gen pulse_gen:PULSE " "Elaborating entity \"pulse_gen\" for hierarchy \"pulse_gen:PULSE\"" {  } { { "top.v" "PULSE" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 39 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014564 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" {  } { { "top.v" "SPI_DAC" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 42 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014580 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" {  } { { "top.v" "PWM_DC" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 43 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014580 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "top.v" "SPI_ADC" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 54 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014580 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:ECHO " "Elaborating entity \"processor\" for hierarchy \"processor:ECHO\"" {  } { { "top.v" "ECHO" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 56 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014595 ""}
+{ "Warning" "WSGN_SEARCH_FILE" "delay_ram.v 1 1 " "Using design file delay_ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "delay_ram.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835014643 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1477835014643 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay_ram processor:ECHO\|delay_ram:DELAY " "Elaborating entity \"delay_ram\" for hierarchy \"processor:ECHO\|delay_ram:DELAY\"" {  } { { "echo_feedback.v" "DELAY" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/echo_feedback.v" 47 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014643 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\"" {  } { { "delay_ram.v" "altsyncram_component" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v" 91 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014814 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\"" {  } { { "delay_ram.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v" 91 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014814 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component " "Instantiated megafunction \"processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone III " "Parameter \"intended_device_family\" = \"Cyclone III\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8192 " "Parameter \"numwords_a\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8192 " "Parameter \"numwords_b\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 13 " "Parameter \"widthad_a\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 13 " "Parameter \"widthad_b\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 9 " "Parameter \"width_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835014814 ""}  } { { "delay_ram.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v" 91 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1477835014814 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ip02.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ip02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ip02 " "Found entity 1: altsyncram_ip02" {  } { { "db/altsyncram_ip02.tdf" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/altsyncram_ip02.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835014939 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835014939 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ip02 processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\|altsyncram_ip02:auto_generated " "Elaborating entity \"altsyncram_ip02\" for hierarchy \"processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\|altsyncram_ip02:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014939 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multiply_k multiply_k:SCALER " "Elaborating entity \"multiply_k\" for hierarchy \"multiply_k:SCALER\"" {  } { { "top.v" "SCALER" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 58 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835014939 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "multiply_k.v" "lpm_mult_component" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015002 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015002 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835015002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835015002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835015002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 9 " "Parameter \"lpm_widtha\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835015002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 11 " "Parameter \"lpm_widthb\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835015002 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 20 " "Parameter \"lpm_widthp\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477835015002 ""}  } { { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1477835015002 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multcore multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core " "Elaborating entity \"multcore\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\"" {  } { { "lpm_mult.tdf" "mult_core" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015080 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015080 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder " "Elaborating entity \"mpar_add\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\"" {  } { { "multcore.tdf" "padder" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015111 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "multcore.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015111 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015173 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015189 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_a9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_a9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_a9h " "Found entity 1: add_sub_a9h" {  } { { "db/add_sub_a9h.tdf" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/add_sub_a9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835015267 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835015267 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_a9h multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated " "Elaborating entity \"add_sub_a9h\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015267 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add " "Elaborating entity \"mpar_add\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\"" {  } { { "mpar_add.tdf" "sub_par_add" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015283 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015283 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015298 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015314 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_e9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_e9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_e9h " "Found entity 1: add_sub_e9h" {  } { { "db/add_sub_e9h.tdf" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/add_sub_e9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477835015439 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835015439 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_e9h multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated " "Elaborating entity \"add_sub_e9h\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015439 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift multiply_k:SCALER\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs " "Elaborating entity \"altshift\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\"" {  } { { "lpm_mult.tdf" "external_latency_ffs" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015486 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015501 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd bin2bcd:BCD_CONVERT " "Elaborating entity \"bin2bcd\" for hierarchy \"bin2bcd:BCD_CONVERT\"" {  } { { "top.v" "BCD_CONVERT" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 59 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015501 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd:BCD_CONVERT\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd:BCD_CONVERT\|add3_ge5:A1\"" {  } { { "bin2bcd.v" "A1" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015501 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "top.v" "SEG0" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 61 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835015517 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] GND " "Pin \"HEX3\[1\]\" is stuck at GND" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 18 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1477835017158 "|top|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] GND " "Pin \"HEX3\[2\]\" is stuck at GND" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 18 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1477835017158 "|top|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Pin \"HEX3\[6\]\" is stuck at VCC" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 18 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1477835017158 "|top|HEX3[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1477835017158 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1477835017392 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 " "4 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1477835017877 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.map.smsg " "Generated suppressed messages file Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835018064 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1477835018439 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477835018439 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "326 " "Implemented 326 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1477835018705 ""} { "Info" "ICUT_CUT_TM_OPINS" "36 " "Implemented 36 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1477835018705 ""} { "Info" "ICUT_CUT_TM_LCELLS" "269 " "Implemented 269 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1477835018705 ""} { "Info" "ICUT_CUT_TM_RAMS" "9 " "Implemented 9 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1477835018705 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1477835018705 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "881 " "Peak virtual memory: 881 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477835018783 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 13:43:38 2016 " "Processing ended: Sun Oct 30 13:43:38 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477835018783 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Elapsed time: 00:00:38" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477835018783 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:35 " "Total CPU time (on all processors): 00:00:35" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477835018783 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1477835018783 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1477835021658 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477835021673 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 13:43:41 2016 " "Processing started: Sun Oct 30 13:43:41 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477835021673 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1477835021673 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off top -c top " "Command: quartus_fit --read_settings_files=off --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1477835021673 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1477835021845 ""}
+{ "Info" "0" "" "Project  = top" {  } {  } 0 0 "Project  = top" 0 0 "Fitter" 0 0 1477835021861 ""}
+{ "Info" "0" "" "Revision = top" {  } {  } 0 0 "Revision = top" 0 0 "Fitter" 0 0 1477835021861 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1477835022236 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Fitter" 0 -1 1477835022236 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "top 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1477835022298 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1477835022423 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1477835022423 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1477835023267 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1477835023376 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1477835023689 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1477835023705 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1477835042173 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 79 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 79 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1477835042377 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1477835042377 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477835042392 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1477835042470 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1477835042486 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1477835042486 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1477835042486 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1477835042486 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1477835042486 ""}
+{ "Info" "ISTA_SDC_FOUND" "top.sdc " "Reading SDC File: 'top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1477835044470 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." {  } {  } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1477835044502 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[0\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[0\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835044548 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1477835044548 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[12\] spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[12\] is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835044548 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1477835044548 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835044548 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1477835044548 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1477835044564 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1477835044564 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1477835044564 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1477835044564 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1477835044564 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1477835044564 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1477835044658 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1477835044658 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1477835044658 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477835044845 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1477835044845 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:21 " "Fitter preparation operations ending: elapsed time is 00:00:21" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477835044861 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1477835067736 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1477835068548 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:03 " "Fitter placement preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477835071236 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1477835076127 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1477835076923 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:06 " "Fitter placement operations ending: elapsed time is 00:00:06" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477835076923 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1477835083236 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/" { { 1 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1477835129345 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1477835129345 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1477835133158 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1477835133158 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1477835133158 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:12 " "Fitter routing operations ending: elapsed time is 00:00:12" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477835133549 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 2.17 " "Total time spent on timing analysis during the Fitter is 2.17 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1477835152595 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1477835158127 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1477835171455 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1477835171486 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1477835176658 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:44 " "Fitter post-fit operations ending: elapsed time is 00:00:44" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477835201892 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1477835202830 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.fit.smsg " "Generated suppressed messages file Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1477835205501 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 41 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2130 " "Peak virtual memory: 2130 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477835209908 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 13:46:49 2016 " "Processing ended: Sun Oct 30 13:46:49 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477835209908 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:03:08 " "Elapsed time: 00:03:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477835209908 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:30 " "Total CPU time (on all processors): 00:01:30" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477835209908 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1477835209908 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1477835215111 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477835215111 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 13:46:54 2016 " "Processing started: Sun Oct 30 13:46:54 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477835215111 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1477835215111 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off top -c top " "Command: quartus_asm --read_settings_files=off --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1477835215111 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1477835216533 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1477835227314 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "896 " "Peak virtual memory: 896 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477835228845 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 13:47:08 2016 " "Processing ended: Sun Oct 30 13:47:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477835228845 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477835228845 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477835228845 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1477835228845 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1477835230002 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1477835232283 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477835232298 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 13:47:11 2016 " "Processing started: Sun Oct 30 13:47:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477835232298 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835232298 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta top -c top " "Command: quartus_sta top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835232298 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1477835232533 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835233658 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835233658 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835233752 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835233752 ""}
+{ "Info" "ISTA_SDC_FOUND" "top.sdc " "Reading SDC File: 'top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835234861 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." {  } {  } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835234877 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[8\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[8\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835234877 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835234877 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[2\]~DUPLICATE spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[2\]~DUPLICATE is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835234877 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835234877 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835234877 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835234877 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835234877 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1477835234877 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1477835234955 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.175 " "Worst-case setup slack is 14.175" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235033 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235033 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.175               0.000 CLOCK_50  " "   14.175               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235033 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835235033 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.372 " "Worst-case hold slack is 0.372" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235033 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235033 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.372               0.000 CLOCK_50  " "    0.372               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235033 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835235033 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835235033 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835235048 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.794 " "Worst-case minimum pulse width slack is 8.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.794               0.000 CLOCK_50  " "    8.794               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835235048 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835235048 ""}
+{ "Warning" "WSTA_METASTABILITY_REPORT_DISALLOW_GLOBAL_OFF" "" "Ignoring Synchronizer Identification setting Off, and using Auto instead." {  } {  } 0 18330 "Ignoring Synchronizer Identification setting Off, and using Auto instead." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835235048 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835235080 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 9 " "Number of Synchronizer Chains Found: 9" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835235080 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835235080 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835235080 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 31.891 ns " "Worst Case Available Settling Time: 31.891 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835235080 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835235080 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835235080 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1477835235095 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835235205 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238361 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[8\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[8\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835238595 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238595 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[2\]~DUPLICATE spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[2\]~DUPLICATE is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835238595 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238595 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835238595 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238595 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238595 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.064 " "Worst-case setup slack is 14.064" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.064               0.000 CLOCK_50  " "   14.064               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238611 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238611 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.381 " "Worst-case hold slack is 0.381" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.381               0.000 CLOCK_50  " "    0.381               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238611 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238611 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238689 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238689 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.761 " "Worst-case minimum pulse width slack is 8.761" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.761               0.000 CLOCK_50  " "    8.761               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835238689 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238689 ""}
+{ "Warning" "WSTA_METASTABILITY_REPORT_DISALLOW_GLOBAL_OFF" "" "Ignoring Synchronizer Identification setting Off, and using Auto instead." {  } {  } 0 18330 "Ignoring Synchronizer Identification setting Off, and using Auto instead." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238689 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835238720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 9 " "Number of Synchronizer Chains Found: 9" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835238720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835238720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835238720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 31.751 ns " "Worst Case Available Settling Time: 31.751 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835238720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835238720 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835238720 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1477835238720 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835239095 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835241845 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[8\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[8\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835242033 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242033 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[2\]~DUPLICATE spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[2\]~DUPLICATE is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835242033 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242033 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835242033 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242033 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242033 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 16.618 " "Worst-case setup slack is 16.618" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.618               0.000 CLOCK_50  " "   16.618               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242048 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242048 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.180 " "Worst-case hold slack is 0.180" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.180               0.000 CLOCK_50  " "    0.180               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242048 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242048 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242048 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242048 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.475 " "Worst-case minimum pulse width slack is 8.475" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242064 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242064 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.475               0.000 CLOCK_50  " "    8.475               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242064 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242064 ""}
+{ "Warning" "WSTA_METASTABILITY_REPORT_DISALLOW_GLOBAL_OFF" "" "Ignoring Synchronizer Identification setting Off, and using Auto instead." {  } {  } 0 18330 "Ignoring Synchronizer Identification setting Off, and using Auto instead." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242064 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242095 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 9 " "Number of Synchronizer Chains Found: 9" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242095 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242095 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242095 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 35.199 ns " "Worst Case Available Settling Time: 35.199 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242095 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242095 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242095 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1477835242095 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[8\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[8\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835242517 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242517 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[2\]~DUPLICATE spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[2\]~DUPLICATE is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835242517 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242517 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477835242517 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242517 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242517 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 16.816 " "Worst-case setup slack is 16.816" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242533 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.816               0.000 CLOCK_50  " "   16.816               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242533 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242533 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.172 " "Worst-case hold slack is 0.172" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172               0.000 CLOCK_50  " "    0.172               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242548 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242548 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242548 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242548 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.429 " "Worst-case minimum pulse width slack is 8.429" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242548 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.429               0.000 CLOCK_50  " "    8.429               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477835242548 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242548 ""}
+{ "Warning" "WSTA_METASTABILITY_REPORT_DISALLOW_GLOBAL_OFF" "" "Ignoring Synchronizer Identification setting Off, and using Auto instead." {  } {  } 0 18330 "Ignoring Synchronizer Identification setting Off, and using Auto instead." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242564 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242627 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 9 " "Number of Synchronizer Chains Found: 9" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242627 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242627 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242627 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 35.415 ns " "Worst Case Available Settling Time: 35.415 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242627 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477835242627 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835242627 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835246017 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835246033 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 17 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1191 " "Peak virtual memory: 1191 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477835246470 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 13:47:26 2016 " "Processing ended: Sun Oct 30 13:47:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477835246470 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477835246470 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477835246470 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835246470 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477835250423 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477835250455 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 13:47:30 2016 " "Processing started: Sun Oct 30 13:47:30 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477835250455 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1477835250455 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off top -c top " "Command: quartus_eda --read_settings_files=off --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1477835250455 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1477835252673 ""}
+{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1477835252830 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "top.vo Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/simulation/modelsim/ simulation " "Generated file top.vo in folder \"Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1477835253283 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "812 " "Peak virtual memory: 812 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477835254283 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 13:47:33 2016 " "Processing ended: Sun Oct 30 13:47:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477835254283 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477835254283 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477835254283 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1477835254283 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 73 s " "Quartus Prime Full Compilation was successful. 0 errors, 73 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1477835255626 ""}
diff --git a/part_4/ex16/db/top.(0).cnf.cdb b/part_4/ex16/db/top.(0).cnf.cdb
new file mode 100755
index 0000000..426b495
--- /dev/null
+++ b/part_4/ex16/db/top.(0).cnf.cdb
diff --git a/part_4/ex16/db/top.(0).cnf.hdb b/part_4/ex16/db/top.(0).cnf.hdb
new file mode 100755
index 0000000..849d1f6
--- /dev/null
+++ b/part_4/ex16/db/top.(0).cnf.hdb
diff --git a/part_4/ex16/db/top.(1).cnf.cdb b/part_4/ex16/db/top.(1).cnf.cdb
new file mode 100755
index 0000000..260fdb6
--- /dev/null
+++ b/part_4/ex16/db/top.(1).cnf.cdb
diff --git a/part_4/ex16/db/top.(1).cnf.hdb b/part_4/ex16/db/top.(1).cnf.hdb
new file mode 100755
index 0000000..2b734dc
--- /dev/null
+++ b/part_4/ex16/db/top.(1).cnf.hdb
diff --git a/part_4/ex16/db/top.(10).cnf.cdb b/part_4/ex16/db/top.(10).cnf.cdb
new file mode 100755
index 0000000..bc945e8
--- /dev/null
+++ b/part_4/ex16/db/top.(10).cnf.cdb
diff --git a/part_4/ex16/db/top.(10).cnf.hdb b/part_4/ex16/db/top.(10).cnf.hdb
new file mode 100755
index 0000000..5ec6592
--- /dev/null
+++ b/part_4/ex16/db/top.(10).cnf.hdb
diff --git a/part_4/ex16/db/top.(11).cnf.cdb b/part_4/ex16/db/top.(11).cnf.cdb
new file mode 100755
index 0000000..b53b4f6
--- /dev/null
+++ b/part_4/ex16/db/top.(11).cnf.cdb
diff --git a/part_4/ex16/db/top.(11).cnf.hdb b/part_4/ex16/db/top.(11).cnf.hdb
new file mode 100755
index 0000000..9d82337
--- /dev/null
+++ b/part_4/ex16/db/top.(11).cnf.hdb
diff --git a/part_4/ex16/db/top.(12).cnf.cdb b/part_4/ex16/db/top.(12).cnf.cdb
new file mode 100755
index 0000000..bb4fbfd
--- /dev/null
+++ b/part_4/ex16/db/top.(12).cnf.cdb
diff --git a/part_4/ex16/db/top.(12).cnf.hdb b/part_4/ex16/db/top.(12).cnf.hdb
new file mode 100755
index 0000000..0685e11
--- /dev/null
+++ b/part_4/ex16/db/top.(12).cnf.hdb
diff --git a/part_4/ex16/db/top.(13).cnf.cdb b/part_4/ex16/db/top.(13).cnf.cdb
new file mode 100755
index 0000000..df246d5
--- /dev/null
+++ b/part_4/ex16/db/top.(13).cnf.cdb
diff --git a/part_4/ex16/db/top.(13).cnf.hdb b/part_4/ex16/db/top.(13).cnf.hdb
new file mode 100755
index 0000000..d9bef5d
--- /dev/null
+++ b/part_4/ex16/db/top.(13).cnf.hdb
diff --git a/part_4/ex16/db/top.(14).cnf.cdb b/part_4/ex16/db/top.(14).cnf.cdb
new file mode 100755
index 0000000..461a0da
--- /dev/null
+++ b/part_4/ex16/db/top.(14).cnf.cdb
diff --git a/part_4/ex16/db/top.(14).cnf.hdb b/part_4/ex16/db/top.(14).cnf.hdb
new file mode 100755
index 0000000..d607f87
--- /dev/null
+++ b/part_4/ex16/db/top.(14).cnf.hdb
diff --git a/part_4/ex16/db/top.(15).cnf.cdb b/part_4/ex16/db/top.(15).cnf.cdb
new file mode 100755
index 0000000..4979972
--- /dev/null
+++ b/part_4/ex16/db/top.(15).cnf.cdb
diff --git a/part_4/ex16/db/top.(15).cnf.hdb b/part_4/ex16/db/top.(15).cnf.hdb
new file mode 100755
index 0000000..4ad5d57
--- /dev/null
+++ b/part_4/ex16/db/top.(15).cnf.hdb
diff --git a/part_4/ex16/db/top.(16).cnf.cdb b/part_4/ex16/db/top.(16).cnf.cdb
new file mode 100755
index 0000000..25d5ed4
--- /dev/null
+++ b/part_4/ex16/db/top.(16).cnf.cdb
diff --git a/part_4/ex16/db/top.(16).cnf.hdb b/part_4/ex16/db/top.(16).cnf.hdb
new file mode 100755
index 0000000..bef8f88
--- /dev/null
+++ b/part_4/ex16/db/top.(16).cnf.hdb
diff --git a/part_4/ex16/db/top.(17).cnf.cdb b/part_4/ex16/db/top.(17).cnf.cdb
new file mode 100755
index 0000000..5761bd5
--- /dev/null
+++ b/part_4/ex16/db/top.(17).cnf.cdb
diff --git a/part_4/ex16/db/top.(17).cnf.hdb b/part_4/ex16/db/top.(17).cnf.hdb
new file mode 100755
index 0000000..7eb9b28
--- /dev/null
+++ b/part_4/ex16/db/top.(17).cnf.hdb
diff --git a/part_4/ex16/db/top.(18).cnf.cdb b/part_4/ex16/db/top.(18).cnf.cdb
new file mode 100755
index 0000000..db8d405
--- /dev/null
+++ b/part_4/ex16/db/top.(18).cnf.cdb
diff --git a/part_4/ex16/db/top.(18).cnf.hdb b/part_4/ex16/db/top.(18).cnf.hdb
new file mode 100755
index 0000000..be0a5ea
--- /dev/null
+++ b/part_4/ex16/db/top.(18).cnf.hdb
diff --git a/part_4/ex16/db/top.(19).cnf.cdb b/part_4/ex16/db/top.(19).cnf.cdb
new file mode 100755
index 0000000..f3ffb71
--- /dev/null
+++ b/part_4/ex16/db/top.(19).cnf.cdb
diff --git a/part_4/ex16/db/top.(19).cnf.hdb b/part_4/ex16/db/top.(19).cnf.hdb
new file mode 100755
index 0000000..28fb7b5
--- /dev/null
+++ b/part_4/ex16/db/top.(19).cnf.hdb
diff --git a/part_4/ex16/db/top.(2).cnf.cdb b/part_4/ex16/db/top.(2).cnf.cdb
new file mode 100755
index 0000000..28c3232
--- /dev/null
+++ b/part_4/ex16/db/top.(2).cnf.cdb
diff --git a/part_4/ex16/db/top.(2).cnf.hdb b/part_4/ex16/db/top.(2).cnf.hdb
new file mode 100755
index 0000000..2cf8e9e
--- /dev/null
+++ b/part_4/ex16/db/top.(2).cnf.hdb
diff --git a/part_4/ex16/db/top.(20).cnf.cdb b/part_4/ex16/db/top.(20).cnf.cdb
new file mode 100755
index 0000000..1d47828
--- /dev/null
+++ b/part_4/ex16/db/top.(20).cnf.cdb
diff --git a/part_4/ex16/db/top.(20).cnf.hdb b/part_4/ex16/db/top.(20).cnf.hdb
new file mode 100755
index 0000000..2c751ac
--- /dev/null
+++ b/part_4/ex16/db/top.(20).cnf.hdb
diff --git a/part_4/ex16/db/top.(21).cnf.cdb b/part_4/ex16/db/top.(21).cnf.cdb
new file mode 100755
index 0000000..ee1199e
--- /dev/null
+++ b/part_4/ex16/db/top.(21).cnf.cdb
diff --git a/part_4/ex16/db/top.(21).cnf.hdb b/part_4/ex16/db/top.(21).cnf.hdb
new file mode 100755
index 0000000..af1dffe
--- /dev/null
+++ b/part_4/ex16/db/top.(21).cnf.hdb
diff --git a/part_4/ex16/db/top.(22).cnf.cdb b/part_4/ex16/db/top.(22).cnf.cdb
new file mode 100755
index 0000000..604f553
--- /dev/null
+++ b/part_4/ex16/db/top.(22).cnf.cdb
diff --git a/part_4/ex16/db/top.(22).cnf.hdb b/part_4/ex16/db/top.(22).cnf.hdb
new file mode 100755
index 0000000..36fa706
--- /dev/null
+++ b/part_4/ex16/db/top.(22).cnf.hdb
diff --git a/part_4/ex16/db/top.(23).cnf.cdb b/part_4/ex16/db/top.(23).cnf.cdb
new file mode 100755
index 0000000..162199b
--- /dev/null
+++ b/part_4/ex16/db/top.(23).cnf.cdb
diff --git a/part_4/ex16/db/top.(23).cnf.hdb b/part_4/ex16/db/top.(23).cnf.hdb
new file mode 100755
index 0000000..6ee1b3a
--- /dev/null
+++ b/part_4/ex16/db/top.(23).cnf.hdb
diff --git a/part_4/ex16/db/top.(24).cnf.cdb b/part_4/ex16/db/top.(24).cnf.cdb
new file mode 100755
index 0000000..740f1bd
--- /dev/null
+++ b/part_4/ex16/db/top.(24).cnf.cdb
diff --git a/part_4/ex16/db/top.(24).cnf.hdb b/part_4/ex16/db/top.(24).cnf.hdb
new file mode 100755
index 0000000..9931698
--- /dev/null
+++ b/part_4/ex16/db/top.(24).cnf.hdb
diff --git a/part_4/ex16/db/top.(3).cnf.cdb b/part_4/ex16/db/top.(3).cnf.cdb
new file mode 100755
index 0000000..e535814
--- /dev/null
+++ b/part_4/ex16/db/top.(3).cnf.cdb
diff --git a/part_4/ex16/db/top.(3).cnf.hdb b/part_4/ex16/db/top.(3).cnf.hdb
new file mode 100755
index 0000000..6ca4503
--- /dev/null
+++ b/part_4/ex16/db/top.(3).cnf.hdb
diff --git a/part_4/ex16/db/top.(4).cnf.cdb b/part_4/ex16/db/top.(4).cnf.cdb
new file mode 100755
index 0000000..51872c3
--- /dev/null
+++ b/part_4/ex16/db/top.(4).cnf.cdb
diff --git a/part_4/ex16/db/top.(4).cnf.hdb b/part_4/ex16/db/top.(4).cnf.hdb
new file mode 100755
index 0000000..d85c656
--- /dev/null
+++ b/part_4/ex16/db/top.(4).cnf.hdb
diff --git a/part_4/ex16/db/top.(5).cnf.cdb b/part_4/ex16/db/top.(5).cnf.cdb
new file mode 100755
index 0000000..f9b6719
--- /dev/null
+++ b/part_4/ex16/db/top.(5).cnf.cdb
diff --git a/part_4/ex16/db/top.(5).cnf.hdb b/part_4/ex16/db/top.(5).cnf.hdb
new file mode 100755
index 0000000..045da2d
--- /dev/null
+++ b/part_4/ex16/db/top.(5).cnf.hdb
diff --git a/part_4/ex16/db/top.(6).cnf.cdb b/part_4/ex16/db/top.(6).cnf.cdb
new file mode 100755
index 0000000..e55786f
--- /dev/null
+++ b/part_4/ex16/db/top.(6).cnf.cdb
diff --git a/part_4/ex16/db/top.(6).cnf.hdb b/part_4/ex16/db/top.(6).cnf.hdb
new file mode 100755
index 0000000..0660839
--- /dev/null
+++ b/part_4/ex16/db/top.(6).cnf.hdb
diff --git a/part_4/ex16/db/top.(7).cnf.cdb b/part_4/ex16/db/top.(7).cnf.cdb
new file mode 100755
index 0000000..b612bfe
--- /dev/null
+++ b/part_4/ex16/db/top.(7).cnf.cdb
diff --git a/part_4/ex16/db/top.(7).cnf.hdb b/part_4/ex16/db/top.(7).cnf.hdb
new file mode 100755
index 0000000..aa6a25d
--- /dev/null
+++ b/part_4/ex16/db/top.(7).cnf.hdb
diff --git a/part_4/ex16/db/top.(8).cnf.cdb b/part_4/ex16/db/top.(8).cnf.cdb
new file mode 100755
index 0000000..9a8b3a8
--- /dev/null
+++ b/part_4/ex16/db/top.(8).cnf.cdb
diff --git a/part_4/ex16/db/top.(8).cnf.hdb b/part_4/ex16/db/top.(8).cnf.hdb
new file mode 100755
index 0000000..4d9ccdf
--- /dev/null
+++ b/part_4/ex16/db/top.(8).cnf.hdb
diff --git a/part_4/ex16/db/top.(9).cnf.cdb b/part_4/ex16/db/top.(9).cnf.cdb
new file mode 100755
index 0000000..46596e3
--- /dev/null
+++ b/part_4/ex16/db/top.(9).cnf.cdb
diff --git a/part_4/ex16/db/top.(9).cnf.hdb b/part_4/ex16/db/top.(9).cnf.hdb
new file mode 100755
index 0000000..73850ed
--- /dev/null
+++ b/part_4/ex16/db/top.(9).cnf.hdb
diff --git a/part_4/ex16/db/top.analyze_file.qmsg b/part_4/ex16/db/top.analyze_file.qmsg
new file mode 100755
index 0000000..b571af3
--- /dev/null
+++ b/part_4/ex16/db/top.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1478718600947 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1478718600947 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 19:10:00 2016 " "Processing started: Wed Nov 09 19:10:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1478718600947 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1478718600947 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top --analyze_file=\"Y:/_My Documents/EE2 Digital - New Experiment/VERI/other stuff/Ex15/spi2dac.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top --analyze_file=\"Y:/_My Documents/EE2 Digital - New Experiment/VERI/other stuff/Ex15/spi2dac.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1478718600947 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1478718601806 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Design Software" 0 -1 1478718601806 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "830 " "Peak virtual memory: 830 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1478718634025 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 19:10:34 2016 " "Processing ended: Wed Nov 09 19:10:34 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1478718634025 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1478718634025 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Total CPU time (on all processors): 00:00:30" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1478718634025 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1478718634025 ""}
diff --git a/part_4/ex16/db/top.asm.qmsg b/part_4/ex16/db/top.asm.qmsg
new file mode 100755
index 0000000..82bfc62
--- /dev/null
+++ b/part_4/ex16/db/top.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1477845744403 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477845744419 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 16:42:24 2016 " "Processing started: Sun Oct 30 16:42:24 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477845744419 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1477845744419 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off top -c top " "Command: quartus_asm --read_settings_files=off --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1477845744419 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1477845745903 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1477845755997 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "899 " "Peak virtual memory: 899 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477845757403 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 16:42:37 2016 " "Processing ended: Sun Oct 30 16:42:37 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477845757403 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477845757403 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477845757403 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1477845757403 ""}
diff --git a/part_4/ex16/db/top.asm.rdb b/part_4/ex16/db/top.asm.rdb
new file mode 100755
index 0000000..ad8a486
--- /dev/null
+++ b/part_4/ex16/db/top.asm.rdb
diff --git a/part_4/ex16/db/top.cmp.bpm b/part_4/ex16/db/top.cmp.bpm
new file mode 100755
index 0000000..8b83f36
--- /dev/null
+++ b/part_4/ex16/db/top.cmp.bpm
diff --git a/part_4/ex16/db/top.cmp.cdb b/part_4/ex16/db/top.cmp.cdb
new file mode 100755
index 0000000..36f247c
--- /dev/null
+++ b/part_4/ex16/db/top.cmp.cdb
diff --git a/part_4/ex16/db/top.cmp.hdb b/part_4/ex16/db/top.cmp.hdb
new file mode 100755
index 0000000..a51e23b
--- /dev/null
+++ b/part_4/ex16/db/top.cmp.hdb
diff --git a/part_4/ex16/db/top.cmp.idb b/part_4/ex16/db/top.cmp.idb
new file mode 100755
index 0000000..60d021f
--- /dev/null
+++ b/part_4/ex16/db/top.cmp.idb
diff --git a/part_4/ex16/db/top.cmp.logdb b/part_4/ex16/db/top.cmp.logdb
new file mode 100755
index 0000000..7c9063d
--- /dev/null
+++ b/part_4/ex16/db/top.cmp.logdb
@@ -0,0 +1,87 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,48;0;48;0;0;48;48;0;48;48;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;48;0;48;48;0;0;48;0;0;48;48;48;48;48;48;48;48;48;48;48;48;48;48;48;48;48;48,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_LD,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PWM_OUT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDO,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_4/ex16/db/top.cmp.rdb b/part_4/ex16/db/top.cmp.rdb
new file mode 100755
index 0000000..8e0f08d
--- /dev/null
+++ b/part_4/ex16/db/top.cmp.rdb
diff --git a/part_4/ex16/db/top.cmp_merge.kpt b/part_4/ex16/db/top.cmp_merge.kpt
new file mode 100755
index 0000000..1c503da
--- /dev/null
+++ b/part_4/ex16/db/top.cmp_merge.kpt
diff --git a/part_4/ex16/db/top.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_4/ex16/db/top.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..8c13822
--- /dev/null
+++ b/part_4/ex16/db/top.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_4/ex16/db/top.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_4/ex16/db/top.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..eed5273
--- /dev/null
+++ b/part_4/ex16/db/top.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_4/ex16/db/top.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_4/ex16/db/top.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..09a04fc
--- /dev/null
+++ b/part_4/ex16/db/top.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_4/ex16/db/top.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_4/ex16/db/top.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..36c4abc
--- /dev/null
+++ b/part_4/ex16/db/top.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_4/ex16/db/top.db_info b/part_4/ex16/db/top.db_info
new file mode 100755
index 0000000..9fd1eb0
--- /dev/null
+++ b/part_4/ex16/db/top.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
+Version_Index = 402707200
+Creation_Time = Wed Nov 09 19:08:52 2016
diff --git a/part_4/ex16/db/top.eda.qmsg b/part_4/ex16/db/top.eda.qmsg
new file mode 100755
index 0000000..39cf158
--- /dev/null
+++ b/part_4/ex16/db/top.eda.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1477845777372 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477845777387 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 16:42:57 2016 " "Processing started: Sun Oct 30 16:42:57 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477845777387 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1477845777387 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off top -c top " "Command: quartus_eda --read_settings_files=off --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1477845777387 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1477845779997 ""}
+{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1477845780184 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "top.vo Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/simulation/modelsim/ simulation " "Generated file top.vo in folder \"Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1477845780778 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "812 " "Peak virtual memory: 812 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477845781778 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 16:43:01 2016 " "Processing ended: Sun Oct 30 16:43:01 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477845781778 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477845781778 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477845781778 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1477845781778 ""}
diff --git a/part_4/ex16/db/top.fit.qmsg b/part_4/ex16/db/top.fit.qmsg
new file mode 100755
index 0000000..bb34417
--- /dev/null
+++ b/part_4/ex16/db/top.fit.qmsg
@@ -0,0 +1,49 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1477845637465 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Fitter" 0 -1 1477845637465 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "top 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"top\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1477845637481 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1477845637637 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1477845637637 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1477845638559 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1477845638684 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1477845639075 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1477845639090 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1477845659215 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 79 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 79 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1477845659512 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1477845659512 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477845659512 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1477845659591 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1477845659591 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1477845659591 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1477845659591 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1477845659606 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1477845659622 ""}
+{ "Info" "ISTA_SDC_FOUND" "top.sdc " "Reading SDC File: 'top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1477845661606 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." {  } {  } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1477845661653 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[0\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[0\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845661653 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1477845661653 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[12\] spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[12\] is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845661653 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1477845661653 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845661653 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1477845661653 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1477845661669 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1477845661669 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1477845661669 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1477845661669 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1477845661669 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1477845661669 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1477845661778 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1477845661794 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1477845661794 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1477845662059 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1477845662059 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:24 " "Fitter preparation operations ending: elapsed time is 00:00:24" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477845662075 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1477845687309 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1477845688122 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:03 " "Fitter placement preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477845691059 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1477845695887 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1477845696794 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:06 " "Fitter placement operations ending: elapsed time is 00:00:06" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477845696794 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1477845700841 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/" { { 1 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1477845719528 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1477845719528 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1477845720700 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1477845720700 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1477845720700 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477845720715 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.90 " "Total time spent on timing analysis during the Fitter is 0.90 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1477845726340 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1477845726762 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1477845728497 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1477845728497 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1477845729997 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:09 " "Fitter post-fit operations ending: elapsed time is 00:00:09" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1477845735231 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1477845735934 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.fit.smsg " "Generated suppressed messages file Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1477845736606 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 41 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2134 " "Peak virtual memory: 2134 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477845738919 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 16:42:18 2016 " "Processing ended: Sun Oct 30 16:42:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477845738919 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:42 " "Elapsed time: 00:01:42" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477845738919 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:29 " "Total CPU time (on all processors): 00:01:29" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477845738919 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1477845738919 ""}
diff --git a/part_4/ex16/db/top.hier_info b/part_4/ex16/db/top.hier_info
new file mode 100755
index 0000000..ad7a429
--- /dev/null
+++ b/part_4/ex16/db/top.hier_info
@@ -0,0 +1,2016 @@
+|top
+CLOCK_50 => CLOCK_50.IN6
+SW[0] => SW[0].IN2
+SW[1] => SW[1].IN2
+SW[2] => SW[2].IN2
+SW[3] => SW[3].IN2
+SW[4] => SW[4].IN2
+SW[5] => SW[5].IN2
+SW[6] => SW[6].IN2
+SW[7] => SW[7].IN2
+SW[8] => SW[8].IN2
+SW[9] => SW[9].IN1
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+HEX3[0] << hex_to_7seg:SEG3.port0
+HEX3[1] << hex_to_7seg:SEG3.port0
+HEX3[2] << hex_to_7seg:SEG3.port0
+HEX3[3] << hex_to_7seg:SEG3.port0
+HEX3[4] << hex_to_7seg:SEG3.port0
+HEX3[5] << hex_to_7seg:SEG3.port0
+HEX3[6] << hex_to_7seg:SEG3.port0
+DAC_SDI << spi2dac:SPI_DAC.port3
+DAC_SCK << spi2dac:SPI_DAC.port5
+DAC_CS << spi2dac:SPI_DAC.port4
+DAC_LD << spi2dac:SPI_DAC.port6
+ADC_SDI << spi2adc:SPI_ADC.sdata_to_adc
+ADC_SCK << spi2adc:SPI_ADC.adc_sck
+ADC_CS << spi2adc:SPI_ADC.adc_cs
+ADC_SDO => ADC_SDO.IN1
+PWM_OUT << pwm:PWM_DC.port3
+
+
+|top|clk_div:GEN_10K
+clkin => clkout~reg0.CLK
+clkin => ctr[0].CLK
+clkin => ctr[1].CLK
+clkin => ctr[2].CLK
+clkin => ctr[3].CLK
+clkin => ctr[4].CLK
+clkin => ctr[5].CLK
+clkin => ctr[6].CLK
+clkin => ctr[7].CLK
+clkin => ctr[8].CLK
+clkin => ctr[9].CLK
+clkin => ctr[10].CLK
+clkin => ctr[11].CLK
+clkin => ctr[12].CLK
+clkin => ctr[13].CLK
+clkin => ctr[14].CLK
+clkin => ctr[15].CLK
+clkin => ctr[16].CLK
+clkin => ctr[17].CLK
+clkin => ctr[18].CLK
+clkin => ctr[19].CLK
+clkin => ctr[20].CLK
+tc[0] => ctr.DATAB
+tc[1] => ctr.DATAB
+tc[2] => ctr.DATAB
+tc[3] => ctr.DATAB
+tc[4] => ctr.DATAB
+tc[5] => ctr.DATAB
+tc[6] => ctr.DATAB
+tc[7] => ctr.DATAB
+tc[8] => ctr.DATAB
+tc[9] => ctr.DATAB
+tc[10] => ctr.DATAB
+tc[11] => ctr.DATAB
+tc[12] => ctr.DATAB
+tc[13] => ctr.DATAB
+tc[14] => ctr.DATAB
+tc[15] => ctr.DATAB
+tc[16] => ctr.DATAB
+tc[17] => ctr.DATAB
+tc[18] => ctr.DATAB
+tc[19] => ctr.DATAB
+tc[20] => ctr.DATAB
+clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|pulse_gen:PULSE
+pulse <= pulse~reg0.DB_MAX_OUTPUT_PORT_TYPE
+in => pulse.DATAB
+in => Selector0.IN1
+in => state.IDLE.DATAIN
+clk => pulse~reg0.CLK
+clk => state~1.DATAIN
+
+
+|top|spi2dac:SPI_DAC
+sysclk => dac_start.CLK
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~1.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => Selector1.IN1
+load => dac_start.OUTPUTSELECT
+load => Selector0.IN1
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= dac_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= dac_ld~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|pwm:PWM_DC
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|spi2adc:SPI_ADC
+sysclk => adc_start.CLK
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~1.DATAIN
+start => Selector1.IN1
+start => adc_start.OUTPUTSELECT
+start => Selector0.IN1
+channel => Selector6.IN6
+data_from_adc[0] <= data_from_adc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[1] <= data_from_adc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[2] <= data_from_adc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[3] <= data_from_adc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[4] <= data_from_adc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[5] <= data_from_adc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[6] <= data_from_adc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[7] <= data_from_adc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[8] <= data_from_adc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[9] <= data_from_adc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+sdata_to_adc <= adc_din.DB_MAX_OUTPUT_PORT_TYPE
+adc_cs <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+adc_sck <= adc_sck.DB_MAX_OUTPUT_PORT_TYPE
+sdata_from_adc => shift_reg[0].DATAIN
+
+
+|top|processor:ECHO
+sysclk => sysclk.IN2
+data_in[0] => Add0.IN20
+data_in[1] => Add0.IN19
+data_in[2] => Add0.IN18
+data_in[3] => Add0.IN17
+data_in[4] => Add0.IN16
+data_in[5] => Add0.IN15
+data_in[6] => Add0.IN14
+data_in[7] => Add0.IN13
+data_in[8] => Add0.IN12
+data_in[9] => Add0.IN11
+data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid => data_valid.IN1
+delay[0] => Add2.IN9
+delay[1] => Add2.IN8
+delay[2] => Add2.IN7
+delay[3] => Add2.IN6
+delay[4] => Add2.IN5
+delay[5] => Add2.IN4
+delay[6] => Add2.IN3
+delay[7] => Add2.IN2
+delay[8] => Add2.IN1
+
+
+|top|processor:ECHO|pulse_gen:PULSE2
+pulse <= pulse~reg0.DB_MAX_OUTPUT_PORT_TYPE
+in => pulse.DATAB
+in => Selector0.IN1
+in => state.IDLE.DATAIN
+clk => pulse~reg0.CLK
+clk => state~1.DATAIN
+
+
+|top|processor:ECHO|delay_ram:DELAY
+clock => clock.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+rdaddress[0] => rdaddress[0].IN1
+rdaddress[1] => rdaddress[1].IN1
+rdaddress[2] => rdaddress[2].IN1
+rdaddress[3] => rdaddress[3].IN1
+rdaddress[4] => rdaddress[4].IN1
+rdaddress[5] => rdaddress[5].IN1
+rdaddress[6] => rdaddress[6].IN1
+rdaddress[7] => rdaddress[7].IN1
+rdaddress[8] => rdaddress[8].IN1
+rdaddress[9] => rdaddress[9].IN1
+rdaddress[10] => rdaddress[10].IN1
+rdaddress[11] => rdaddress[11].IN1
+rdaddress[12] => rdaddress[12].IN1
+rden => rden.IN1
+wraddress[0] => wraddress[0].IN1
+wraddress[1] => wraddress[1].IN1
+wraddress[2] => wraddress[2].IN1
+wraddress[3] => wraddress[3].IN1
+wraddress[4] => wraddress[4].IN1
+wraddress[5] => wraddress[5].IN1
+wraddress[6] => wraddress[6].IN1
+wraddress[7] => wraddress[7].IN1
+wraddress[8] => wraddress[8].IN1
+wraddress[9] => wraddress[9].IN1
+wraddress[10] => wraddress[10].IN1
+wraddress[11] => wraddress[11].IN1
+wraddress[12] => wraddress[12].IN1
+wren => wren.IN1
+q[0] <= altsyncram:altsyncram_component.q_b
+q[1] <= altsyncram:altsyncram_component.q_b
+q[2] <= altsyncram:altsyncram_component.q_b
+q[3] <= altsyncram:altsyncram_component.q_b
+q[4] <= altsyncram:altsyncram_component.q_b
+q[5] <= altsyncram:altsyncram_component.q_b
+q[6] <= altsyncram:altsyncram_component.q_b
+q[7] <= altsyncram:altsyncram_component.q_b
+q[8] <= altsyncram:altsyncram_component.q_b
+
+
+|top|processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component
+wren_a => altsyncram_ip02:auto_generated.wren_a
+rden_a => ~NO_FANOUT~
+wren_b => ~NO_FANOUT~
+rden_b => altsyncram_ip02:auto_generated.rden_b
+data_a[0] => altsyncram_ip02:auto_generated.data_a[0]
+data_a[1] => altsyncram_ip02:auto_generated.data_a[1]
+data_a[2] => altsyncram_ip02:auto_generated.data_a[2]
+data_a[3] => altsyncram_ip02:auto_generated.data_a[3]
+data_a[4] => altsyncram_ip02:auto_generated.data_a[4]
+data_a[5] => altsyncram_ip02:auto_generated.data_a[5]
+data_a[6] => altsyncram_ip02:auto_generated.data_a[6]
+data_a[7] => altsyncram_ip02:auto_generated.data_a[7]
+data_a[8] => altsyncram_ip02:auto_generated.data_a[8]
+data_b[0] => ~NO_FANOUT~
+data_b[1] => ~NO_FANOUT~
+data_b[2] => ~NO_FANOUT~
+data_b[3] => ~NO_FANOUT~
+data_b[4] => ~NO_FANOUT~
+data_b[5] => ~NO_FANOUT~
+data_b[6] => ~NO_FANOUT~
+data_b[7] => ~NO_FANOUT~
+data_b[8] => ~NO_FANOUT~
+address_a[0] => altsyncram_ip02:auto_generated.address_a[0]
+address_a[1] => altsyncram_ip02:auto_generated.address_a[1]
+address_a[2] => altsyncram_ip02:auto_generated.address_a[2]
+address_a[3] => altsyncram_ip02:auto_generated.address_a[3]
+address_a[4] => altsyncram_ip02:auto_generated.address_a[4]
+address_a[5] => altsyncram_ip02:auto_generated.address_a[5]
+address_a[6] => altsyncram_ip02:auto_generated.address_a[6]
+address_a[7] => altsyncram_ip02:auto_generated.address_a[7]
+address_a[8] => altsyncram_ip02:auto_generated.address_a[8]
+address_a[9] => altsyncram_ip02:auto_generated.address_a[9]
+address_a[10] => altsyncram_ip02:auto_generated.address_a[10]
+address_a[11] => altsyncram_ip02:auto_generated.address_a[11]
+address_a[12] => altsyncram_ip02:auto_generated.address_a[12]
+address_b[0] => altsyncram_ip02:auto_generated.address_b[0]
+address_b[1] => altsyncram_ip02:auto_generated.address_b[1]
+address_b[2] => altsyncram_ip02:auto_generated.address_b[2]
+address_b[3] => altsyncram_ip02:auto_generated.address_b[3]
+address_b[4] => altsyncram_ip02:auto_generated.address_b[4]
+address_b[5] => altsyncram_ip02:auto_generated.address_b[5]
+address_b[6] => altsyncram_ip02:auto_generated.address_b[6]
+address_b[7] => altsyncram_ip02:auto_generated.address_b[7]
+address_b[8] => altsyncram_ip02:auto_generated.address_b[8]
+address_b[9] => altsyncram_ip02:auto_generated.address_b[9]
+address_b[10] => altsyncram_ip02:auto_generated.address_b[10]
+address_b[11] => altsyncram_ip02:auto_generated.address_b[11]
+address_b[12] => altsyncram_ip02:auto_generated.address_b[12]
+addressstall_a => ~NO_FANOUT~
+addressstall_b => ~NO_FANOUT~
+clock0 => altsyncram_ip02:auto_generated.clock0
+clock1 => ~NO_FANOUT~
+clocken0 => ~NO_FANOUT~
+clocken1 => ~NO_FANOUT~
+clocken2 => ~NO_FANOUT~
+clocken3 => ~NO_FANOUT~
+aclr0 => ~NO_FANOUT~
+aclr1 => ~NO_FANOUT~
+byteena_a[0] => ~NO_FANOUT~
+byteena_b[0] => ~NO_FANOUT~
+q_a[0] <= <GND>
+q_a[1] <= <GND>
+q_a[2] <= <GND>
+q_a[3] <= <GND>
+q_a[4] <= <GND>
+q_a[5] <= <GND>
+q_a[6] <= <GND>
+q_a[7] <= <GND>
+q_a[8] <= <GND>
+q_b[0] <= altsyncram_ip02:auto_generated.q_b[0]
+q_b[1] <= altsyncram_ip02:auto_generated.q_b[1]
+q_b[2] <= altsyncram_ip02:auto_generated.q_b[2]
+q_b[3] <= altsyncram_ip02:auto_generated.q_b[3]
+q_b[4] <= altsyncram_ip02:auto_generated.q_b[4]
+q_b[5] <= altsyncram_ip02:auto_generated.q_b[5]
+q_b[6] <= altsyncram_ip02:auto_generated.q_b[6]
+q_b[7] <= altsyncram_ip02:auto_generated.q_b[7]
+q_b[8] <= altsyncram_ip02:auto_generated.q_b[8]
+eccstatus[0] <= <GND>
+eccstatus[1] <= <GND>
+eccstatus[2] <= <GND>
+
+
+|top|processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated
+address_a[0] => ram_block1a0.PORTAADDR
+address_a[0] => ram_block1a1.PORTAADDR
+address_a[0] => ram_block1a2.PORTAADDR
+address_a[0] => ram_block1a3.PORTAADDR
+address_a[0] => ram_block1a4.PORTAADDR
+address_a[0] => ram_block1a5.PORTAADDR
+address_a[0] => ram_block1a6.PORTAADDR
+address_a[0] => ram_block1a7.PORTAADDR
+address_a[0] => ram_block1a8.PORTAADDR
+address_a[1] => ram_block1a0.PORTAADDR1
+address_a[1] => ram_block1a1.PORTAADDR1
+address_a[1] => ram_block1a2.PORTAADDR1
+address_a[1] => ram_block1a3.PORTAADDR1
+address_a[1] => ram_block1a4.PORTAADDR1
+address_a[1] => ram_block1a5.PORTAADDR1
+address_a[1] => ram_block1a6.PORTAADDR1
+address_a[1] => ram_block1a7.PORTAADDR1
+address_a[1] => ram_block1a8.PORTAADDR1
+address_a[2] => ram_block1a0.PORTAADDR2
+address_a[2] => ram_block1a1.PORTAADDR2
+address_a[2] => ram_block1a2.PORTAADDR2
+address_a[2] => ram_block1a3.PORTAADDR2
+address_a[2] => ram_block1a4.PORTAADDR2
+address_a[2] => ram_block1a5.PORTAADDR2
+address_a[2] => ram_block1a6.PORTAADDR2
+address_a[2] => ram_block1a7.PORTAADDR2
+address_a[2] => ram_block1a8.PORTAADDR2
+address_a[3] => ram_block1a0.PORTAADDR3
+address_a[3] => ram_block1a1.PORTAADDR3
+address_a[3] => ram_block1a2.PORTAADDR3
+address_a[3] => ram_block1a3.PORTAADDR3
+address_a[3] => ram_block1a4.PORTAADDR3
+address_a[3] => ram_block1a5.PORTAADDR3
+address_a[3] => ram_block1a6.PORTAADDR3
+address_a[3] => ram_block1a7.PORTAADDR3
+address_a[3] => ram_block1a8.PORTAADDR3
+address_a[4] => ram_block1a0.PORTAADDR4
+address_a[4] => ram_block1a1.PORTAADDR4
+address_a[4] => ram_block1a2.PORTAADDR4
+address_a[4] => ram_block1a3.PORTAADDR4
+address_a[4] => ram_block1a4.PORTAADDR4
+address_a[4] => ram_block1a5.PORTAADDR4
+address_a[4] => ram_block1a6.PORTAADDR4
+address_a[4] => ram_block1a7.PORTAADDR4
+address_a[4] => ram_block1a8.PORTAADDR4
+address_a[5] => ram_block1a0.PORTAADDR5
+address_a[5] => ram_block1a1.PORTAADDR5
+address_a[5] => ram_block1a2.PORTAADDR5
+address_a[5] => ram_block1a3.PORTAADDR5
+address_a[5] => ram_block1a4.PORTAADDR5
+address_a[5] => ram_block1a5.PORTAADDR5
+address_a[5] => ram_block1a6.PORTAADDR5
+address_a[5] => ram_block1a7.PORTAADDR5
+address_a[5] => ram_block1a8.PORTAADDR5
+address_a[6] => ram_block1a0.PORTAADDR6
+address_a[6] => ram_block1a1.PORTAADDR6
+address_a[6] => ram_block1a2.PORTAADDR6
+address_a[6] => ram_block1a3.PORTAADDR6
+address_a[6] => ram_block1a4.PORTAADDR6
+address_a[6] => ram_block1a5.PORTAADDR6
+address_a[6] => ram_block1a6.PORTAADDR6
+address_a[6] => ram_block1a7.PORTAADDR6
+address_a[6] => ram_block1a8.PORTAADDR6
+address_a[7] => ram_block1a0.PORTAADDR7
+address_a[7] => ram_block1a1.PORTAADDR7
+address_a[7] => ram_block1a2.PORTAADDR7
+address_a[7] => ram_block1a3.PORTAADDR7
+address_a[7] => ram_block1a4.PORTAADDR7
+address_a[7] => ram_block1a5.PORTAADDR7
+address_a[7] => ram_block1a6.PORTAADDR7
+address_a[7] => ram_block1a7.PORTAADDR7
+address_a[7] => ram_block1a8.PORTAADDR7
+address_a[8] => ram_block1a0.PORTAADDR8
+address_a[8] => ram_block1a1.PORTAADDR8
+address_a[8] => ram_block1a2.PORTAADDR8
+address_a[8] => ram_block1a3.PORTAADDR8
+address_a[8] => ram_block1a4.PORTAADDR8
+address_a[8] => ram_block1a5.PORTAADDR8
+address_a[8] => ram_block1a6.PORTAADDR8
+address_a[8] => ram_block1a7.PORTAADDR8
+address_a[8] => ram_block1a8.PORTAADDR8
+address_a[9] => ram_block1a0.PORTAADDR9
+address_a[9] => ram_block1a1.PORTAADDR9
+address_a[9] => ram_block1a2.PORTAADDR9
+address_a[9] => ram_block1a3.PORTAADDR9
+address_a[9] => ram_block1a4.PORTAADDR9
+address_a[9] => ram_block1a5.PORTAADDR9
+address_a[9] => ram_block1a6.PORTAADDR9
+address_a[9] => ram_block1a7.PORTAADDR9
+address_a[9] => ram_block1a8.PORTAADDR9
+address_a[10] => ram_block1a0.PORTAADDR10
+address_a[10] => ram_block1a1.PORTAADDR10
+address_a[10] => ram_block1a2.PORTAADDR10
+address_a[10] => ram_block1a3.PORTAADDR10
+address_a[10] => ram_block1a4.PORTAADDR10
+address_a[10] => ram_block1a5.PORTAADDR10
+address_a[10] => ram_block1a6.PORTAADDR10
+address_a[10] => ram_block1a7.PORTAADDR10
+address_a[10] => ram_block1a8.PORTAADDR10
+address_a[11] => ram_block1a0.PORTAADDR11
+address_a[11] => ram_block1a1.PORTAADDR11
+address_a[11] => ram_block1a2.PORTAADDR11
+address_a[11] => ram_block1a3.PORTAADDR11
+address_a[11] => ram_block1a4.PORTAADDR11
+address_a[11] => ram_block1a5.PORTAADDR11
+address_a[11] => ram_block1a6.PORTAADDR11
+address_a[11] => ram_block1a7.PORTAADDR11
+address_a[11] => ram_block1a8.PORTAADDR11
+address_a[12] => ram_block1a0.PORTAADDR12
+address_a[12] => ram_block1a1.PORTAADDR12
+address_a[12] => ram_block1a2.PORTAADDR12
+address_a[12] => ram_block1a3.PORTAADDR12
+address_a[12] => ram_block1a4.PORTAADDR12
+address_a[12] => ram_block1a5.PORTAADDR12
+address_a[12] => ram_block1a6.PORTAADDR12
+address_a[12] => ram_block1a7.PORTAADDR12
+address_a[12] => ram_block1a8.PORTAADDR12
+address_b[0] => ram_block1a0.PORTBADDR
+address_b[0] => ram_block1a1.PORTBADDR
+address_b[0] => ram_block1a2.PORTBADDR
+address_b[0] => ram_block1a3.PORTBADDR
+address_b[0] => ram_block1a4.PORTBADDR
+address_b[0] => ram_block1a5.PORTBADDR
+address_b[0] => ram_block1a6.PORTBADDR
+address_b[0] => ram_block1a7.PORTBADDR
+address_b[0] => ram_block1a8.PORTBADDR
+address_b[1] => ram_block1a0.PORTBADDR1
+address_b[1] => ram_block1a1.PORTBADDR1
+address_b[1] => ram_block1a2.PORTBADDR1
+address_b[1] => ram_block1a3.PORTBADDR1
+address_b[1] => ram_block1a4.PORTBADDR1
+address_b[1] => ram_block1a5.PORTBADDR1
+address_b[1] => ram_block1a6.PORTBADDR1
+address_b[1] => ram_block1a7.PORTBADDR1
+address_b[1] => ram_block1a8.PORTBADDR1
+address_b[2] => ram_block1a0.PORTBADDR2
+address_b[2] => ram_block1a1.PORTBADDR2
+address_b[2] => ram_block1a2.PORTBADDR2
+address_b[2] => ram_block1a3.PORTBADDR2
+address_b[2] => ram_block1a4.PORTBADDR2
+address_b[2] => ram_block1a5.PORTBADDR2
+address_b[2] => ram_block1a6.PORTBADDR2
+address_b[2] => ram_block1a7.PORTBADDR2
+address_b[2] => ram_block1a8.PORTBADDR2
+address_b[3] => ram_block1a0.PORTBADDR3
+address_b[3] => ram_block1a1.PORTBADDR3
+address_b[3] => ram_block1a2.PORTBADDR3
+address_b[3] => ram_block1a3.PORTBADDR3
+address_b[3] => ram_block1a4.PORTBADDR3
+address_b[3] => ram_block1a5.PORTBADDR3
+address_b[3] => ram_block1a6.PORTBADDR3
+address_b[3] => ram_block1a7.PORTBADDR3
+address_b[3] => ram_block1a8.PORTBADDR3
+address_b[4] => ram_block1a0.PORTBADDR4
+address_b[4] => ram_block1a1.PORTBADDR4
+address_b[4] => ram_block1a2.PORTBADDR4
+address_b[4] => ram_block1a3.PORTBADDR4
+address_b[4] => ram_block1a4.PORTBADDR4
+address_b[4] => ram_block1a5.PORTBADDR4
+address_b[4] => ram_block1a6.PORTBADDR4
+address_b[4] => ram_block1a7.PORTBADDR4
+address_b[4] => ram_block1a8.PORTBADDR4
+address_b[5] => ram_block1a0.PORTBADDR5
+address_b[5] => ram_block1a1.PORTBADDR5
+address_b[5] => ram_block1a2.PORTBADDR5
+address_b[5] => ram_block1a3.PORTBADDR5
+address_b[5] => ram_block1a4.PORTBADDR5
+address_b[5] => ram_block1a5.PORTBADDR5
+address_b[5] => ram_block1a6.PORTBADDR5
+address_b[5] => ram_block1a7.PORTBADDR5
+address_b[5] => ram_block1a8.PORTBADDR5
+address_b[6] => ram_block1a0.PORTBADDR6
+address_b[6] => ram_block1a1.PORTBADDR6
+address_b[6] => ram_block1a2.PORTBADDR6
+address_b[6] => ram_block1a3.PORTBADDR6
+address_b[6] => ram_block1a4.PORTBADDR6
+address_b[6] => ram_block1a5.PORTBADDR6
+address_b[6] => ram_block1a6.PORTBADDR6
+address_b[6] => ram_block1a7.PORTBADDR6
+address_b[6] => ram_block1a8.PORTBADDR6
+address_b[7] => ram_block1a0.PORTBADDR7
+address_b[7] => ram_block1a1.PORTBADDR7
+address_b[7] => ram_block1a2.PORTBADDR7
+address_b[7] => ram_block1a3.PORTBADDR7
+address_b[7] => ram_block1a4.PORTBADDR7
+address_b[7] => ram_block1a5.PORTBADDR7
+address_b[7] => ram_block1a6.PORTBADDR7
+address_b[7] => ram_block1a7.PORTBADDR7
+address_b[7] => ram_block1a8.PORTBADDR7
+address_b[8] => ram_block1a0.PORTBADDR8
+address_b[8] => ram_block1a1.PORTBADDR8
+address_b[8] => ram_block1a2.PORTBADDR8
+address_b[8] => ram_block1a3.PORTBADDR8
+address_b[8] => ram_block1a4.PORTBADDR8
+address_b[8] => ram_block1a5.PORTBADDR8
+address_b[8] => ram_block1a6.PORTBADDR8
+address_b[8] => ram_block1a7.PORTBADDR8
+address_b[8] => ram_block1a8.PORTBADDR8
+address_b[9] => ram_block1a0.PORTBADDR9
+address_b[9] => ram_block1a1.PORTBADDR9
+address_b[9] => ram_block1a2.PORTBADDR9
+address_b[9] => ram_block1a3.PORTBADDR9
+address_b[9] => ram_block1a4.PORTBADDR9
+address_b[9] => ram_block1a5.PORTBADDR9
+address_b[9] => ram_block1a6.PORTBADDR9
+address_b[9] => ram_block1a7.PORTBADDR9
+address_b[9] => ram_block1a8.PORTBADDR9
+address_b[10] => ram_block1a0.PORTBADDR10
+address_b[10] => ram_block1a1.PORTBADDR10
+address_b[10] => ram_block1a2.PORTBADDR10
+address_b[10] => ram_block1a3.PORTBADDR10
+address_b[10] => ram_block1a4.PORTBADDR10
+address_b[10] => ram_block1a5.PORTBADDR10
+address_b[10] => ram_block1a6.PORTBADDR10
+address_b[10] => ram_block1a7.PORTBADDR10
+address_b[10] => ram_block1a8.PORTBADDR10
+address_b[11] => ram_block1a0.PORTBADDR11
+address_b[11] => ram_block1a1.PORTBADDR11
+address_b[11] => ram_block1a2.PORTBADDR11
+address_b[11] => ram_block1a3.PORTBADDR11
+address_b[11] => ram_block1a4.PORTBADDR11
+address_b[11] => ram_block1a5.PORTBADDR11
+address_b[11] => ram_block1a6.PORTBADDR11
+address_b[11] => ram_block1a7.PORTBADDR11
+address_b[11] => ram_block1a8.PORTBADDR11
+address_b[12] => ram_block1a0.PORTBADDR12
+address_b[12] => ram_block1a1.PORTBADDR12
+address_b[12] => ram_block1a2.PORTBADDR12
+address_b[12] => ram_block1a3.PORTBADDR12
+address_b[12] => ram_block1a4.PORTBADDR12
+address_b[12] => ram_block1a5.PORTBADDR12
+address_b[12] => ram_block1a6.PORTBADDR12
+address_b[12] => ram_block1a7.PORTBADDR12
+address_b[12] => ram_block1a8.PORTBADDR12
+clock0 => ram_block1a0.CLK0
+clock0 => ram_block1a0.CLK1
+clock0 => ram_block1a1.CLK0
+clock0 => ram_block1a1.CLK1
+clock0 => ram_block1a2.CLK0
+clock0 => ram_block1a2.CLK1
+clock0 => ram_block1a3.CLK0
+clock0 => ram_block1a3.CLK1
+clock0 => ram_block1a4.CLK0
+clock0 => ram_block1a4.CLK1
+clock0 => ram_block1a5.CLK0
+clock0 => ram_block1a5.CLK1
+clock0 => ram_block1a6.CLK0
+clock0 => ram_block1a6.CLK1
+clock0 => ram_block1a7.CLK0
+clock0 => ram_block1a7.CLK1
+clock0 => ram_block1a8.CLK0
+clock0 => ram_block1a8.CLK1
+data_a[0] => ram_block1a0.PORTADATAIN
+data_a[1] => ram_block1a1.PORTADATAIN
+data_a[2] => ram_block1a2.PORTADATAIN
+data_a[3] => ram_block1a3.PORTADATAIN
+data_a[4] => ram_block1a4.PORTADATAIN
+data_a[5] => ram_block1a5.PORTADATAIN
+data_a[6] => ram_block1a6.PORTADATAIN
+data_a[7] => ram_block1a7.PORTADATAIN
+data_a[8] => ram_block1a8.PORTADATAIN
+q_b[0] <= ram_block1a0.PORTBDATAOUT
+q_b[1] <= ram_block1a1.PORTBDATAOUT
+q_b[2] <= ram_block1a2.PORTBDATAOUT
+q_b[3] <= ram_block1a3.PORTBDATAOUT
+q_b[4] <= ram_block1a4.PORTBDATAOUT
+q_b[5] <= ram_block1a5.PORTBDATAOUT
+q_b[6] <= ram_block1a6.PORTBDATAOUT
+q_b[7] <= ram_block1a7.PORTBDATAOUT
+q_b[8] <= ram_block1a8.PORTBDATAOUT
+rden_b => ram_block1a0.ENA1
+rden_b => ram_block1a1.ENA1
+rden_b => ram_block1a2.ENA1
+rden_b => ram_block1a3.ENA1
+rden_b => ram_block1a4.ENA1
+rden_b => ram_block1a5.ENA1
+rden_b => ram_block1a6.ENA1
+rden_b => ram_block1a7.ENA1
+rden_b => ram_block1a8.ENA1
+wren_a => ram_block1a0.PORTAWE
+wren_a => ram_block1a0.ENA0
+wren_a => ram_block1a1.PORTAWE
+wren_a => ram_block1a1.ENA0
+wren_a => ram_block1a2.PORTAWE
+wren_a => ram_block1a2.ENA0
+wren_a => ram_block1a3.PORTAWE
+wren_a => ram_block1a3.ENA0
+wren_a => ram_block1a4.PORTAWE
+wren_a => ram_block1a4.ENA0
+wren_a => ram_block1a5.PORTAWE
+wren_a => ram_block1a5.ENA0
+wren_a => ram_block1a6.PORTAWE
+wren_a => ram_block1a6.ENA0
+wren_a => ram_block1a7.PORTAWE
+wren_a => ram_block1a7.ENA0
+wren_a => ram_block1a8.PORTAWE
+wren_a => ram_block1a8.ENA0
+
+
+|top|multiply_k:SCALER
+dataa[0] => dataa[0].IN1
+dataa[1] => dataa[1].IN1
+dataa[2] => dataa[2].IN1
+dataa[3] => dataa[3].IN1
+dataa[4] => dataa[4].IN1
+dataa[5] => dataa[5].IN1
+dataa[6] => dataa[6].IN1
+dataa[7] => dataa[7].IN1
+dataa[8] => dataa[8].IN1
+result[0] <= lpm_mult:lpm_mult_component.result
+result[1] <= lpm_mult:lpm_mult_component.result
+result[2] <= lpm_mult:lpm_mult_component.result
+result[3] <= lpm_mult:lpm_mult_component.result
+result[4] <= lpm_mult:lpm_mult_component.result
+result[5] <= lpm_mult:lpm_mult_component.result
+result[6] <= lpm_mult:lpm_mult_component.result
+result[7] <= lpm_mult:lpm_mult_component.result
+result[8] <= lpm_mult:lpm_mult_component.result
+result[9] <= lpm_mult:lpm_mult_component.result
+result[10] <= lpm_mult:lpm_mult_component.result
+result[11] <= lpm_mult:lpm_mult_component.result
+result[12] <= lpm_mult:lpm_mult_component.result
+result[13] <= lpm_mult:lpm_mult_component.result
+result[14] <= lpm_mult:lpm_mult_component.result
+result[15] <= lpm_mult:lpm_mult_component.result
+result[16] <= lpm_mult:lpm_mult_component.result
+result[17] <= lpm_mult:lpm_mult_component.result
+result[18] <= lpm_mult:lpm_mult_component.result
+result[19] <= lpm_mult:lpm_mult_component.result
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component
+dataa[0] => multcore:mult_core.dataa[0]
+dataa[1] => multcore:mult_core.dataa[1]
+dataa[2] => multcore:mult_core.dataa[2]
+dataa[3] => multcore:mult_core.dataa[3]
+dataa[4] => multcore:mult_core.dataa[4]
+dataa[5] => multcore:mult_core.dataa[5]
+dataa[6] => multcore:mult_core.dataa[6]
+dataa[7] => multcore:mult_core.dataa[7]
+dataa[8] => multcore:mult_core.dataa[8]
+datab[0] => multcore:mult_core.datab[0]
+datab[1] => multcore:mult_core.datab[1]
+datab[2] => multcore:mult_core.datab[2]
+datab[3] => multcore:mult_core.datab[3]
+datab[4] => multcore:mult_core.datab[4]
+datab[5] => multcore:mult_core.datab[5]
+datab[6] => multcore:mult_core.datab[6]
+datab[7] => multcore:mult_core.datab[7]
+datab[8] => multcore:mult_core.datab[8]
+datab[9] => multcore:mult_core.datab[9]
+datab[10] => multcore:mult_core.datab[10]
+sum[0] => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+sclr => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= altshift:external_latency_ffs.result[0]
+result[1] <= altshift:external_latency_ffs.result[1]
+result[2] <= altshift:external_latency_ffs.result[2]
+result[3] <= altshift:external_latency_ffs.result[3]
+result[4] <= altshift:external_latency_ffs.result[4]
+result[5] <= altshift:external_latency_ffs.result[5]
+result[6] <= altshift:external_latency_ffs.result[6]
+result[7] <= altshift:external_latency_ffs.result[7]
+result[8] <= altshift:external_latency_ffs.result[8]
+result[9] <= altshift:external_latency_ffs.result[9]
+result[10] <= altshift:external_latency_ffs.result[10]
+result[11] <= altshift:external_latency_ffs.result[11]
+result[12] <= altshift:external_latency_ffs.result[12]
+result[13] <= altshift:external_latency_ffs.result[13]
+result[14] <= altshift:external_latency_ffs.result[14]
+result[15] <= altshift:external_latency_ffs.result[15]
+result[16] <= altshift:external_latency_ffs.result[16]
+result[17] <= altshift:external_latency_ffs.result[17]
+result[18] <= altshift:external_latency_ffs.result[18]
+result[19] <= altshift:external_latency_ffs.result[19]
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component|multcore:mult_core
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[8] => ina_reg_clkd[0].IN0
+datab[0] => op_1.IN28
+datab[0] => op_2.IN29
+datab[0] => op_4.IN29
+datab[0] => op_5.IN29
+datab[0] => op_6.IN29
+datab[0] => op_7.IN29
+datab[0] => op_8.IN29
+datab[0] => op_9.IN29
+datab[0] => op_10.IN29
+datab[0] => op_11.IN29
+datab[0] => romout[0][0].IN1
+datab[0] => romout[1][0].IN1
+datab[0] => op_1.IN27
+datab[0] => op_3.IN27
+datab[0] => romout[0][1].IN1
+datab[0] => romout[1][1].IN1
+datab[0] => op_2.IN24
+datab[0] => op_3.IN24
+datab[0] => romout[0][2].IN1
+datab[0] => romout[1][2].IN1
+datab[0] => op_5.IN22
+datab[0] => romout[0][3].IN1
+datab[0] => romout[1][3].IN1
+datab[0] => romout[2][0].IN1
+datab[0] => romout[2][1].IN1
+datab[0] => romout[2][2].IN1
+datab[0] => romout[2][3].IN1
+datab[1] => op_1.IN26
+datab[1] => op_2.IN27
+datab[1] => op_4.IN27
+datab[1] => op_5.IN27
+datab[1] => op_6.IN27
+datab[1] => op_7.IN27
+datab[1] => op_8.IN27
+datab[1] => op_9.IN27
+datab[1] => op_10.IN27
+datab[1] => op_11.IN27
+datab[1] => romout[0][1].IN1
+datab[1] => romout[1][1].IN1
+datab[1] => op_1.IN25
+datab[1] => op_3.IN25
+datab[1] => romout[0][2].IN1
+datab[1] => romout[1][2].IN1
+datab[1] => op_2.IN22
+datab[1] => op_3.IN22
+datab[1] => romout[0][3].IN1
+datab[1] => romout[1][3].IN1
+datab[1] => op_5.IN20
+datab[1] => romout[0][4].IN1
+datab[1] => romout[1][4].IN1
+datab[1] => romout[2][1].IN1
+datab[1] => romout[2][2].IN1
+datab[1] => romout[2][3].IN1
+datab[1] => romout[2][4].IN1
+datab[2] => op_1.IN24
+datab[2] => op_2.IN25
+datab[2] => op_4.IN25
+datab[2] => op_5.IN25
+datab[2] => op_6.IN25
+datab[2] => op_7.IN25
+datab[2] => op_8.IN25
+datab[2] => op_9.IN25
+datab[2] => op_10.IN25
+datab[2] => op_11.IN25
+datab[2] => romout[0][2].IN1
+datab[2] => romout[1][2].IN1
+datab[2] => op_1.IN23
+datab[2] => op_3.IN23
+datab[2] => romout[0][3].IN1
+datab[2] => romout[1][3].IN1
+datab[2] => op_2.IN20
+datab[2] => op_3.IN20
+datab[2] => romout[0][4].IN1
+datab[2] => romout[1][4].IN1
+datab[2] => op_5.IN18
+datab[2] => romout[0][5].IN1
+datab[2] => romout[1][5].IN1
+datab[2] => romout[2][2].IN1
+datab[2] => romout[2][3].IN1
+datab[2] => romout[2][4].IN1
+datab[2] => romout[2][5].IN1
+datab[3] => op_1.IN22
+datab[3] => op_2.IN23
+datab[3] => op_4.IN23
+datab[3] => op_5.IN23
+datab[3] => op_6.IN23
+datab[3] => op_7.IN23
+datab[3] => op_8.IN23
+datab[3] => op_9.IN23
+datab[3] => op_10.IN23
+datab[3] => op_11.IN23
+datab[3] => romout[0][3].IN1
+datab[3] => romout[1][3].IN1
+datab[3] => op_1.IN21
+datab[3] => op_3.IN21
+datab[3] => romout[0][4].IN1
+datab[3] => romout[1][4].IN1
+datab[3] => op_2.IN18
+datab[3] => op_3.IN18
+datab[3] => romout[0][5].IN1
+datab[3] => romout[1][5].IN1
+datab[3] => op_5.IN16
+datab[3] => romout[0][6].IN1
+datab[3] => romout[1][6].IN1
+datab[3] => romout[2][3].IN1
+datab[3] => romout[2][4].IN1
+datab[3] => romout[2][5].IN1
+datab[3] => romout[2][6].IN1
+datab[4] => op_1.IN20
+datab[4] => op_2.IN21
+datab[4] => op_4.IN21
+datab[4] => op_5.IN21
+datab[4] => op_6.IN21
+datab[4] => op_7.IN21
+datab[4] => op_8.IN21
+datab[4] => op_9.IN21
+datab[4] => op_10.IN21
+datab[4] => op_11.IN21
+datab[4] => romout[0][4].IN1
+datab[4] => romout[1][4].IN1
+datab[4] => op_1.IN19
+datab[4] => op_3.IN19
+datab[4] => romout[0][5].IN1
+datab[4] => romout[1][5].IN1
+datab[4] => op_2.IN16
+datab[4] => op_3.IN16
+datab[4] => romout[0][6].IN1
+datab[4] => romout[1][6].IN1
+datab[4] => op_5.IN14
+datab[4] => romout[0][7].IN1
+datab[4] => romout[1][7].IN1
+datab[4] => romout[2][4].IN1
+datab[4] => romout[2][5].IN1
+datab[4] => romout[2][6].IN1
+datab[4] => romout[2][7].IN1
+datab[5] => op_1.IN18
+datab[5] => op_2.IN19
+datab[5] => op_4.IN19
+datab[5] => op_5.IN19
+datab[5] => op_6.IN19
+datab[5] => op_7.IN19
+datab[5] => op_8.IN19
+datab[5] => op_9.IN19
+datab[5] => op_10.IN19
+datab[5] => op_11.IN19
+datab[5] => romout[0][5].IN1
+datab[5] => romout[1][5].IN1
+datab[5] => op_1.IN17
+datab[5] => op_3.IN17
+datab[5] => romout[0][6].IN1
+datab[5] => romout[1][6].IN1
+datab[5] => op_2.IN14
+datab[5] => op_3.IN14
+datab[5] => romout[0][7].IN1
+datab[5] => romout[1][7].IN1
+datab[5] => op_5.IN12
+datab[5] => romout[0][8].IN1
+datab[5] => romout[1][8].IN1
+datab[5] => romout[2][5].IN1
+datab[5] => romout[2][6].IN1
+datab[5] => romout[2][7].IN1
+datab[5] => romout[2][8].IN1
+datab[6] => op_1.IN16
+datab[6] => op_2.IN17
+datab[6] => op_4.IN17
+datab[6] => op_5.IN17
+datab[6] => op_6.IN17
+datab[6] => op_7.IN17
+datab[6] => op_8.IN17
+datab[6] => op_9.IN17
+datab[6] => op_10.IN17
+datab[6] => op_11.IN17
+datab[6] => romout[0][6].IN1
+datab[6] => romout[1][6].IN1
+datab[6] => op_1.IN15
+datab[6] => op_3.IN15
+datab[6] => romout[0][7].IN1
+datab[6] => romout[1][7].IN1
+datab[6] => op_2.IN12
+datab[6] => op_3.IN12
+datab[6] => romout[0][8].IN1
+datab[6] => romout[1][8].IN1
+datab[6] => op_5.IN10
+datab[6] => romout[0][9].IN1
+datab[6] => romout[1][9].IN1
+datab[6] => romout[2][6].IN1
+datab[6] => romout[2][7].IN1
+datab[6] => romout[2][8].IN1
+datab[6] => romout[2][9].IN1
+datab[7] => op_1.IN14
+datab[7] => op_2.IN15
+datab[7] => op_4.IN15
+datab[7] => op_5.IN15
+datab[7] => op_6.IN15
+datab[7] => op_7.IN15
+datab[7] => op_8.IN15
+datab[7] => op_9.IN15
+datab[7] => op_10.IN15
+datab[7] => op_11.IN15
+datab[7] => romout[0][7].IN1
+datab[7] => romout[1][7].IN1
+datab[7] => op_1.IN13
+datab[7] => op_3.IN13
+datab[7] => romout[0][8].IN1
+datab[7] => romout[1][8].IN1
+datab[7] => op_2.IN10
+datab[7] => op_3.IN10
+datab[7] => romout[0][9].IN1
+datab[7] => romout[1][9].IN1
+datab[7] => op_5.IN8
+datab[7] => romout[0][10].IN1
+datab[7] => romout[1][10].IN1
+datab[7] => romout[2][7].IN1
+datab[7] => romout[2][8].IN1
+datab[7] => romout[2][9].IN1
+datab[7] => romout[2][10].IN1
+datab[8] => op_1.IN12
+datab[8] => op_2.IN13
+datab[8] => op_4.IN13
+datab[8] => op_5.IN13
+datab[8] => op_6.IN13
+datab[8] => op_7.IN13
+datab[8] => op_8.IN13
+datab[8] => op_9.IN13
+datab[8] => op_10.IN13
+datab[8] => op_11.IN13
+datab[8] => romout[0][8].IN1
+datab[8] => romout[1][8].IN1
+datab[8] => op_1.IN11
+datab[8] => op_3.IN11
+datab[8] => romout[0][9].IN1
+datab[8] => romout[1][9].IN1
+datab[8] => op_2.IN8
+datab[8] => op_3.IN8
+datab[8] => romout[0][10].IN1
+datab[8] => romout[1][10].IN1
+datab[8] => op_5.IN6
+datab[8] => romout[0][11].IN1
+datab[8] => romout[1][11].IN1
+datab[8] => romout[2][8].IN1
+datab[8] => romout[2][9].IN1
+datab[8] => romout[2][10].IN1
+datab[8] => romout[2][11].IN1
+datab[9] => op_1.IN10
+datab[9] => op_2.IN11
+datab[9] => op_4.IN11
+datab[9] => op_5.IN11
+datab[9] => op_6.IN11
+datab[9] => op_7.IN11
+datab[9] => op_8.IN11
+datab[9] => op_9.IN11
+datab[9] => op_10.IN11
+datab[9] => op_11.IN11
+datab[9] => romout[0][9].IN1
+datab[9] => romout[1][9].IN1
+datab[9] => op_1.IN9
+datab[9] => op_3.IN9
+datab[9] => romout[0][10].IN1
+datab[9] => romout[1][10].IN1
+datab[9] => op_2.IN6
+datab[9] => op_3.IN6
+datab[9] => romout[0][11].IN1
+datab[9] => romout[1][11].IN1
+datab[9] => op_5.IN4
+datab[9] => romout[0][12].IN1
+datab[9] => romout[1][12].IN1
+datab[9] => romout[2][9].IN1
+datab[9] => romout[2][10].IN1
+datab[9] => romout[2][11].IN1
+datab[9] => romout[2][12].IN1
+datab[10] => op_1.IN8
+datab[10] => op_2.IN9
+datab[10] => op_4.IN9
+datab[10] => op_5.IN9
+datab[10] => op_6.IN9
+datab[10] => op_7.IN9
+datab[10] => op_8.IN9
+datab[10] => op_9.IN9
+datab[10] => op_10.IN9
+datab[10] => op_11.IN9
+datab[10] => romout[0][10].IN1
+datab[10] => romout[1][10].IN1
+datab[10] => op_1.IN7
+datab[10] => op_3.IN7
+datab[10] => romout[0][11].IN1
+datab[10] => romout[1][11].IN1
+datab[10] => op_2.IN4
+datab[10] => op_3.IN4
+datab[10] => romout[0][12].IN1
+datab[10] => romout[1][12].IN1
+datab[10] => op_5.IN2
+datab[10] => romout[0][13].IN1
+datab[10] => romout[1][13].IN1
+datab[10] => romout[2][10].IN1
+datab[10] => romout[2][11].IN1
+datab[10] => romout[2][12].IN1
+datab[10] => romout[2][13].IN1
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mpar_add:padder.result[0]
+result[1] <= mpar_add:padder.result[1]
+result[2] <= mpar_add:padder.result[2]
+result[3] <= mpar_add:padder.result[3]
+result[4] <= mpar_add:padder.result[4]
+result[5] <= mpar_add:padder.result[5]
+result[6] <= mpar_add:padder.result[6]
+result[7] <= mpar_add:padder.result[7]
+result[8] <= mpar_add:padder.result[8]
+result[9] <= mpar_add:padder.result[9]
+result[10] <= mpar_add:padder.result[10]
+result[11] <= mpar_add:padder.result[11]
+result[12] <= mpar_add:padder.result[12]
+result[13] <= mpar_add:padder.result[13]
+result[14] <= mpar_add:padder.result[14]
+result[15] <= mpar_add:padder.result[15]
+result[16] <= mpar_add:padder.result[16]
+result[17] <= mpar_add:padder.result[17]
+result[18] <= mpar_add:padder.result[18]
+result[19] <= mpar_add:padder.result[19]
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder
+data[0][0] => mpar_add:sub_par_add.data[0][0]
+data[0][1] => mpar_add:sub_par_add.data[0][1]
+data[0][2] => mpar_add:sub_par_add.data[0][2]
+data[0][3] => mpar_add:sub_par_add.data[0][3]
+data[0][4] => lpm_add_sub:adder[0].dataa[0]
+data[0][5] => lpm_add_sub:adder[0].dataa[1]
+data[0][6] => lpm_add_sub:adder[0].dataa[2]
+data[0][7] => lpm_add_sub:adder[0].dataa[3]
+data[0][8] => lpm_add_sub:adder[0].dataa[4]
+data[0][9] => lpm_add_sub:adder[0].dataa[5]
+data[0][10] => lpm_add_sub:adder[0].dataa[6]
+data[0][11] => lpm_add_sub:adder[0].dataa[7]
+data[0][12] => lpm_add_sub:adder[0].dataa[8]
+data[0][13] => lpm_add_sub:adder[0].dataa[9]
+data[0][14] => lpm_add_sub:adder[0].dataa[10]
+data[1][0] => lpm_add_sub:adder[0].datab[0]
+data[1][1] => lpm_add_sub:adder[0].datab[1]
+data[1][2] => lpm_add_sub:adder[0].datab[2]
+data[1][3] => lpm_add_sub:adder[0].datab[3]
+data[1][4] => lpm_add_sub:adder[0].datab[4]
+data[1][5] => lpm_add_sub:adder[0].datab[5]
+data[1][6] => lpm_add_sub:adder[0].datab[6]
+data[1][7] => lpm_add_sub:adder[0].datab[7]
+data[1][8] => lpm_add_sub:adder[0].datab[8]
+data[1][9] => lpm_add_sub:adder[0].datab[9]
+data[1][10] => lpm_add_sub:adder[0].datab[10]
+data[1][11] => lpm_add_sub:adder[0].datab[11]
+data[1][12] => lpm_add_sub:adder[0].datab[12]
+data[1][13] => lpm_add_sub:adder[0].datab[13]
+data[1][14] => lpm_add_sub:adder[0].datab[14]
+data[2][0] => mpar_add:sub_par_add.data[1][0]
+data[2][1] => mpar_add:sub_par_add.data[1][1]
+data[2][2] => mpar_add:sub_par_add.data[1][2]
+data[2][3] => mpar_add:sub_par_add.data[1][3]
+data[2][4] => mpar_add:sub_par_add.data[1][4]
+data[2][5] => mpar_add:sub_par_add.data[1][5]
+data[2][6] => mpar_add:sub_par_add.data[1][6]
+data[2][7] => mpar_add:sub_par_add.data[1][7]
+data[2][8] => mpar_add:sub_par_add.data[1][8]
+data[2][9] => mpar_add:sub_par_add.data[1][9]
+data[2][10] => mpar_add:sub_par_add.data[1][10]
+data[2][11] => mpar_add:sub_par_add.data[1][11]
+data[2][12] => mpar_add:sub_par_add.data[1][12]
+data[2][13] => mpar_add:sub_par_add.data[1][13]
+data[2][14] => mpar_add:sub_par_add.data[1][14]
+cin => ~NO_FANOUT~
+clk => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mpar_add:sub_par_add.result[0]
+result[1] <= mpar_add:sub_par_add.result[1]
+result[2] <= mpar_add:sub_par_add.result[2]
+result[3] <= mpar_add:sub_par_add.result[3]
+result[4] <= mpar_add:sub_par_add.result[4]
+result[5] <= mpar_add:sub_par_add.result[5]
+result[6] <= mpar_add:sub_par_add.result[6]
+result[7] <= mpar_add:sub_par_add.result[7]
+result[8] <= mpar_add:sub_par_add.result[8]
+result[9] <= mpar_add:sub_par_add.result[9]
+result[10] <= mpar_add:sub_par_add.result[10]
+result[11] <= mpar_add:sub_par_add.result[11]
+result[12] <= mpar_add:sub_par_add.result[12]
+result[13] <= mpar_add:sub_par_add.result[13]
+result[14] <= mpar_add:sub_par_add.result[14]
+result[15] <= mpar_add:sub_par_add.result[15]
+result[16] <= mpar_add:sub_par_add.result[16]
+result[17] <= mpar_add:sub_par_add.result[17]
+result[18] <= mpar_add:sub_par_add.result[18]
+result[19] <= mpar_add:sub_par_add.result[19]
+result[20] <= mpar_add:sub_par_add.result[20]
+result[21] <= mpar_add:sub_par_add.result[21]
+result[22] <= mpar_add:sub_par_add.result[22]
+result[23] <= mpar_add:sub_par_add.result[23]
+result[24] <= mpar_add:sub_par_add.result[24]
+result[25] <= mpar_add:sub_par_add.result[25]
+result[26] <= mpar_add:sub_par_add.result[26]
+clk_out <= <GND>
+aclr_out <= <GND>
+clken_out <= <GND>
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]
+dataa[0] => add_sub_a9h:auto_generated.dataa[0]
+dataa[1] => add_sub_a9h:auto_generated.dataa[1]
+dataa[2] => add_sub_a9h:auto_generated.dataa[2]
+dataa[3] => add_sub_a9h:auto_generated.dataa[3]
+dataa[4] => add_sub_a9h:auto_generated.dataa[4]
+dataa[5] => add_sub_a9h:auto_generated.dataa[5]
+dataa[6] => add_sub_a9h:auto_generated.dataa[6]
+dataa[7] => add_sub_a9h:auto_generated.dataa[7]
+dataa[8] => add_sub_a9h:auto_generated.dataa[8]
+dataa[9] => add_sub_a9h:auto_generated.dataa[9]
+dataa[10] => add_sub_a9h:auto_generated.dataa[10]
+dataa[11] => add_sub_a9h:auto_generated.dataa[11]
+dataa[12] => add_sub_a9h:auto_generated.dataa[12]
+dataa[13] => add_sub_a9h:auto_generated.dataa[13]
+dataa[14] => add_sub_a9h:auto_generated.dataa[14]
+datab[0] => add_sub_a9h:auto_generated.datab[0]
+datab[1] => add_sub_a9h:auto_generated.datab[1]
+datab[2] => add_sub_a9h:auto_generated.datab[2]
+datab[3] => add_sub_a9h:auto_generated.datab[3]
+datab[4] => add_sub_a9h:auto_generated.datab[4]
+datab[5] => add_sub_a9h:auto_generated.datab[5]
+datab[6] => add_sub_a9h:auto_generated.datab[6]
+datab[7] => add_sub_a9h:auto_generated.datab[7]
+datab[8] => add_sub_a9h:auto_generated.datab[8]
+datab[9] => add_sub_a9h:auto_generated.datab[9]
+datab[10] => add_sub_a9h:auto_generated.datab[10]
+datab[11] => add_sub_a9h:auto_generated.datab[11]
+datab[12] => add_sub_a9h:auto_generated.datab[12]
+datab[13] => add_sub_a9h:auto_generated.datab[13]
+datab[14] => add_sub_a9h:auto_generated.datab[14]
+cin => ~NO_FANOUT~
+add_sub => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= add_sub_a9h:auto_generated.result[0]
+result[1] <= add_sub_a9h:auto_generated.result[1]
+result[2] <= add_sub_a9h:auto_generated.result[2]
+result[3] <= add_sub_a9h:auto_generated.result[3]
+result[4] <= add_sub_a9h:auto_generated.result[4]
+result[5] <= add_sub_a9h:auto_generated.result[5]
+result[6] <= add_sub_a9h:auto_generated.result[6]
+result[7] <= add_sub_a9h:auto_generated.result[7]
+result[8] <= add_sub_a9h:auto_generated.result[8]
+result[9] <= add_sub_a9h:auto_generated.result[9]
+result[10] <= add_sub_a9h:auto_generated.result[10]
+result[11] <= add_sub_a9h:auto_generated.result[11]
+result[12] <= add_sub_a9h:auto_generated.result[12]
+result[13] <= add_sub_a9h:auto_generated.result[13]
+result[14] <= add_sub_a9h:auto_generated.result[14]
+cout <= <GND>
+overflow <= <GND>
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated
+dataa[0] => op_1.IN28
+dataa[1] => op_1.IN26
+dataa[2] => op_1.IN24
+dataa[3] => op_1.IN22
+dataa[4] => op_1.IN20
+dataa[5] => op_1.IN18
+dataa[6] => op_1.IN16
+dataa[7] => op_1.IN14
+dataa[8] => op_1.IN12
+dataa[9] => op_1.IN10
+dataa[10] => op_1.IN8
+dataa[11] => op_1.IN6
+dataa[12] => op_1.IN4
+dataa[13] => op_1.IN2
+dataa[14] => op_1.IN0
+datab[0] => op_1.IN29
+datab[1] => op_1.IN27
+datab[2] => op_1.IN25
+datab[3] => op_1.IN23
+datab[4] => op_1.IN21
+datab[5] => op_1.IN19
+datab[6] => op_1.IN17
+datab[7] => op_1.IN15
+datab[8] => op_1.IN13
+datab[9] => op_1.IN11
+datab[10] => op_1.IN9
+datab[11] => op_1.IN7
+datab[12] => op_1.IN5
+datab[13] => op_1.IN3
+datab[14] => op_1.IN1
+result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add
+data[0][0] => result[0].DATAIN
+data[0][1] => result[1].DATAIN
+data[0][2] => result[2].DATAIN
+data[0][3] => result[3].DATAIN
+data[0][4] => result[4].DATAIN
+data[0][5] => result[5].DATAIN
+data[0][6] => result[6].DATAIN
+data[0][7] => result[7].DATAIN
+data[0][8] => lpm_add_sub:adder[0].dataa[0]
+data[0][9] => lpm_add_sub:adder[0].dataa[1]
+data[0][10] => lpm_add_sub:adder[0].dataa[2]
+data[0][11] => lpm_add_sub:adder[0].dataa[3]
+data[0][12] => lpm_add_sub:adder[0].dataa[4]
+data[0][13] => lpm_add_sub:adder[0].dataa[5]
+data[0][14] => lpm_add_sub:adder[0].dataa[6]
+data[0][15] => lpm_add_sub:adder[0].dataa[7]
+data[0][16] => lpm_add_sub:adder[0].dataa[8]
+data[0][17] => lpm_add_sub:adder[0].dataa[9]
+data[0][18] => lpm_add_sub:adder[0].dataa[10]
+data[1][0] => lpm_add_sub:adder[0].datab[0]
+data[1][1] => lpm_add_sub:adder[0].datab[1]
+data[1][2] => lpm_add_sub:adder[0].datab[2]
+data[1][3] => lpm_add_sub:adder[0].datab[3]
+data[1][4] => lpm_add_sub:adder[0].datab[4]
+data[1][5] => lpm_add_sub:adder[0].datab[5]
+data[1][6] => lpm_add_sub:adder[0].datab[6]
+data[1][7] => lpm_add_sub:adder[0].datab[7]
+data[1][8] => lpm_add_sub:adder[0].datab[8]
+data[1][9] => lpm_add_sub:adder[0].datab[9]
+data[1][10] => lpm_add_sub:adder[0].datab[10]
+data[1][11] => lpm_add_sub:adder[0].datab[11]
+data[1][12] => lpm_add_sub:adder[0].datab[12]
+data[1][13] => lpm_add_sub:adder[0].datab[13]
+data[1][14] => lpm_add_sub:adder[0].datab[14]
+data[1][15] => ~NO_FANOUT~
+data[1][16] => ~NO_FANOUT~
+data[1][17] => ~NO_FANOUT~
+data[1][18] => ~NO_FANOUT~
+cin => ~NO_FANOUT~
+clk => clk_out.IN0
+aclr => aclr_out.IN0
+clken => clken_out.IN0
+result[0] <= data[0][0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= data[0][1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= data[0][2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= data[0][3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= data[0][4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= data[0][5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= data[0][6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= data[0][7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= level_result_node[0][0].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= level_result_node[0][1].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= level_result_node[0][2].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= level_result_node[0][3].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= level_result_node[0][4].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= level_result_node[0][5].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= level_result_node[0][6].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= level_result_node[0][7].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= level_result_node[0][8].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= level_result_node[0][9].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= level_result_node[0][10].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= level_result_node[0][11].DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= level_result_node[0][12].DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= level_result_node[0][13].DB_MAX_OUTPUT_PORT_TYPE
+result[22] <= level_result_node[0][14].DB_MAX_OUTPUT_PORT_TYPE
+result[23] <= level_result_node[0][15].DB_MAX_OUTPUT_PORT_TYPE
+result[24] <= level_result_node[0][16].DB_MAX_OUTPUT_PORT_TYPE
+result[25] <= level_result_node[0][17].DB_MAX_OUTPUT_PORT_TYPE
+result[26] <= level_result_node[0][18].DB_MAX_OUTPUT_PORT_TYPE
+clk_out <= clk_out.DB_MAX_OUTPUT_PORT_TYPE
+aclr_out <= aclr_out.DB_MAX_OUTPUT_PORT_TYPE
+clken_out <= clken_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]
+dataa[0] => add_sub_e9h:auto_generated.dataa[0]
+dataa[1] => add_sub_e9h:auto_generated.dataa[1]
+dataa[2] => add_sub_e9h:auto_generated.dataa[2]
+dataa[3] => add_sub_e9h:auto_generated.dataa[3]
+dataa[4] => add_sub_e9h:auto_generated.dataa[4]
+dataa[5] => add_sub_e9h:auto_generated.dataa[5]
+dataa[6] => add_sub_e9h:auto_generated.dataa[6]
+dataa[7] => add_sub_e9h:auto_generated.dataa[7]
+dataa[8] => add_sub_e9h:auto_generated.dataa[8]
+dataa[9] => add_sub_e9h:auto_generated.dataa[9]
+dataa[10] => add_sub_e9h:auto_generated.dataa[10]
+dataa[11] => add_sub_e9h:auto_generated.dataa[11]
+dataa[12] => add_sub_e9h:auto_generated.dataa[12]
+dataa[13] => add_sub_e9h:auto_generated.dataa[13]
+dataa[14] => add_sub_e9h:auto_generated.dataa[14]
+dataa[15] => add_sub_e9h:auto_generated.dataa[15]
+dataa[16] => add_sub_e9h:auto_generated.dataa[16]
+dataa[17] => add_sub_e9h:auto_generated.dataa[17]
+dataa[18] => add_sub_e9h:auto_generated.dataa[18]
+datab[0] => add_sub_e9h:auto_generated.datab[0]
+datab[1] => add_sub_e9h:auto_generated.datab[1]
+datab[2] => add_sub_e9h:auto_generated.datab[2]
+datab[3] => add_sub_e9h:auto_generated.datab[3]
+datab[4] => add_sub_e9h:auto_generated.datab[4]
+datab[5] => add_sub_e9h:auto_generated.datab[5]
+datab[6] => add_sub_e9h:auto_generated.datab[6]
+datab[7] => add_sub_e9h:auto_generated.datab[7]
+datab[8] => add_sub_e9h:auto_generated.datab[8]
+datab[9] => add_sub_e9h:auto_generated.datab[9]
+datab[10] => add_sub_e9h:auto_generated.datab[10]
+datab[11] => add_sub_e9h:auto_generated.datab[11]
+datab[12] => add_sub_e9h:auto_generated.datab[12]
+datab[13] => add_sub_e9h:auto_generated.datab[13]
+datab[14] => add_sub_e9h:auto_generated.datab[14]
+datab[15] => add_sub_e9h:auto_generated.datab[15]
+datab[16] => add_sub_e9h:auto_generated.datab[16]
+datab[17] => add_sub_e9h:auto_generated.datab[17]
+datab[18] => add_sub_e9h:auto_generated.datab[18]
+cin => ~NO_FANOUT~
+add_sub => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= add_sub_e9h:auto_generated.result[0]
+result[1] <= add_sub_e9h:auto_generated.result[1]
+result[2] <= add_sub_e9h:auto_generated.result[2]
+result[3] <= add_sub_e9h:auto_generated.result[3]
+result[4] <= add_sub_e9h:auto_generated.result[4]
+result[5] <= add_sub_e9h:auto_generated.result[5]
+result[6] <= add_sub_e9h:auto_generated.result[6]
+result[7] <= add_sub_e9h:auto_generated.result[7]
+result[8] <= add_sub_e9h:auto_generated.result[8]
+result[9] <= add_sub_e9h:auto_generated.result[9]
+result[10] <= add_sub_e9h:auto_generated.result[10]
+result[11] <= add_sub_e9h:auto_generated.result[11]
+result[12] <= add_sub_e9h:auto_generated.result[12]
+result[13] <= add_sub_e9h:auto_generated.result[13]
+result[14] <= add_sub_e9h:auto_generated.result[14]
+result[15] <= add_sub_e9h:auto_generated.result[15]
+result[16] <= add_sub_e9h:auto_generated.result[16]
+result[17] <= add_sub_e9h:auto_generated.result[17]
+result[18] <= add_sub_e9h:auto_generated.result[18]
+cout <= <GND>
+overflow <= <GND>
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated
+dataa[0] => op_1.IN36
+dataa[1] => op_1.IN34
+dataa[2] => op_1.IN32
+dataa[3] => op_1.IN30
+dataa[4] => op_1.IN28
+dataa[5] => op_1.IN26
+dataa[6] => op_1.IN24
+dataa[7] => op_1.IN22
+dataa[8] => op_1.IN20
+dataa[9] => op_1.IN18
+dataa[10] => op_1.IN16
+dataa[11] => op_1.IN14
+dataa[12] => op_1.IN12
+dataa[13] => op_1.IN10
+dataa[14] => op_1.IN8
+dataa[15] => op_1.IN6
+dataa[16] => op_1.IN4
+dataa[17] => op_1.IN2
+dataa[18] => op_1.IN0
+datab[0] => op_1.IN37
+datab[1] => op_1.IN35
+datab[2] => op_1.IN33
+datab[3] => op_1.IN31
+datab[4] => op_1.IN29
+datab[5] => op_1.IN27
+datab[6] => op_1.IN25
+datab[7] => op_1.IN23
+datab[8] => op_1.IN21
+datab[9] => op_1.IN19
+datab[10] => op_1.IN17
+datab[11] => op_1.IN15
+datab[12] => op_1.IN13
+datab[13] => op_1.IN11
+datab[14] => op_1.IN9
+datab[15] => op_1.IN7
+datab[16] => op_1.IN5
+datab[17] => op_1.IN3
+datab[18] => op_1.IN1
+result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|multiply_k:SCALER|lpm_mult:lpm_mult_component|altshift:external_latency_ffs
+data[0] => result[0].DATAIN
+data[1] => result[1].DATAIN
+data[2] => result[2].DATAIN
+data[3] => result[3].DATAIN
+data[4] => result[4].DATAIN
+data[5] => result[5].DATAIN
+data[6] => result[6].DATAIN
+data[7] => result[7].DATAIN
+data[8] => result[8].DATAIN
+data[9] => result[9].DATAIN
+data[10] => result[10].DATAIN
+data[11] => result[11].DATAIN
+data[12] => result[12].DATAIN
+data[13] => result[13].DATAIN
+data[14] => result[14].DATAIN
+data[15] => result[15].DATAIN
+data[16] => result[16].DATAIN
+data[17] => result[17].DATAIN
+data[18] => result[18].DATAIN
+data[19] => result[19].DATAIN
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= data[12].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= data[13].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= data[14].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= data[15].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= data[16].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= data[17].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= data[18].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= data[19].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT
+B[0] => BCD_0[0].DATAIN
+B[1] => w25[0].IN1
+B[2] => w21[0].IN1
+B[3] => w18[0].IN1
+B[4] => w15[0].IN1
+B[5] => w12[0].IN1
+B[6] => w9[0].IN1
+B[7] => w7[0].IN1
+B[8] => w5[0].IN1
+B[9] => w3[0].IN1
+B[10] => w2[0].IN1
+B[11] => w1[0].IN1
+B[12] => w1[1].IN1
+B[13] => w1[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A25.port1
+BCD_0[2] <= add3_ge5:A25.port1
+BCD_0[3] <= add3_ge5:A25.port1
+BCD_1[0] <= add3_ge5:A25.port1
+BCD_1[1] <= add3_ge5:A24.port1
+BCD_1[2] <= add3_ge5:A24.port1
+BCD_1[3] <= add3_ge5:A24.port1
+BCD_2[0] <= add3_ge5:A24.port1
+BCD_2[1] <= add3_ge5:A23.port1
+BCD_2[2] <= add3_ge5:A23.port1
+BCD_2[3] <= add3_ge5:A23.port1
+BCD_3[0] <= add3_ge5:A23.port1
+BCD_3[1] <= add3_ge5:A22.port1
+BCD_3[2] <= add3_ge5:A22.port1
+BCD_3[3] <= add3_ge5:A22.port1
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A1
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A2
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A3
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A4
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A5
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A6
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A7
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A8
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A9
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A10
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A11
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A12
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A13
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A14
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A15
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A16
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A17
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A18
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A19
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A20
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A21
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A22
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A23
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A24
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|bin2bcd:BCD_CONVERT|add3_ge5:A25
+iW[0] => Decoder0.IN3
+iW[1] => Decoder0.IN2
+iW[2] => Decoder0.IN1
+iW[3] => Decoder0.IN0
+oA[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oA[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oA[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oA[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|top|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|top|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|top|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|top|hex_to_7seg:SEG3
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_4/ex16/db/top.hif b/part_4/ex16/db/top.hif
new file mode 100755
index 0000000..bc1a51b
--- /dev/null
+++ b/part_4/ex16/db/top.hif
diff --git a/part_4/ex16/db/top.lpc.html b/part_4/ex16/db/top.lpc.html
new file mode 100755
index 0000000..398bec2
--- /dev/null
+++ b/part_4/ex16/db/top.lpc.html
@@ -0,0 +1,690 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A19</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A18</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A10</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A9</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A4</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT|A1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >BCD_CONVERT</TD>
+<TD >14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >16</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated</TD>
+<TD >38</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >19</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >15</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SCALER</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ECHO|DELAY|altsyncram_component|auto_generated</TD>
+<TD >38</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ECHO|DELAY</TD>
+<TD >38</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ECHO|PULSE2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ECHO</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_ADC</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >PWM_DC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_DAC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >PULSE</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >GEN_10K</TD>
+<TD >22</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >21</TD>
+<TD >1</TD>
+<TD >21</TD>
+<TD >21</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_4/ex16/db/top.lpc.rdb b/part_4/ex16/db/top.lpc.rdb
new file mode 100755
index 0000000..37c2bf4
--- /dev/null
+++ b/part_4/ex16/db/top.lpc.rdb
diff --git a/part_4/ex16/db/top.lpc.txt b/part_4/ex16/db/top.lpc.txt
new file mode 100755
index 0000000..c345f94
--- /dev/null
+++ b/part_4/ex16/db/top.lpc.txt
@@ -0,0 +1,48 @@
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                                                          ;
++--------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                                                      ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++--------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG3                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG2                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG1                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG0                                                                           ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A25                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A24                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A23                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A22                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A21                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A20                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A19                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A18                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A17                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A16                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A15                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A14                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A13                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A12                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A11                                                                ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A10                                                                ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A9                                                                 ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A8                                                                 ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A7                                                                 ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A6                                                                 ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A5                                                                 ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A4                                                                 ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A3                                                                 ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A2                                                                 ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT|A1                                                                 ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; BCD_CONVERT                                                                    ; 14    ; 4              ; 0            ; 4              ; 16     ; 4               ; 4             ; 4               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated ; 38    ; 0              ; 0            ; 0              ; 19     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated             ; 30    ; 0              ; 0            ; 0              ; 15     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SCALER                                                                         ; 9     ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ECHO|DELAY|altsyncram_component|auto_generated                                 ; 38    ; 0              ; 0            ; 0              ; 9      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ECHO|DELAY                                                                     ; 38    ; 0              ; 0            ; 0              ; 9      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ECHO|PULSE2                                                                    ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ECHO                                                                           ; 21    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_ADC                                                                        ; 4     ; 0              ; 0            ; 0              ; 14     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; PWM_DC                                                                         ; 12    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_DAC                                                                        ; 12    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; PULSE                                                                          ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; GEN_10K                                                                        ; 22    ; 21             ; 0            ; 21             ; 1      ; 21              ; 21            ; 21              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++--------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_4/ex16/db/top.map.ammdb b/part_4/ex16/db/top.map.ammdb
new file mode 100755
index 0000000..d3c4872
--- /dev/null
+++ b/part_4/ex16/db/top.map.ammdb
diff --git a/part_4/ex16/db/top.map.bpm b/part_4/ex16/db/top.map.bpm
new file mode 100755
index 0000000..c81dd8b
--- /dev/null
+++ b/part_4/ex16/db/top.map.bpm
diff --git a/part_4/ex16/db/top.map.cdb b/part_4/ex16/db/top.map.cdb
new file mode 100755
index 0000000..84a9861
--- /dev/null
+++ b/part_4/ex16/db/top.map.cdb
diff --git a/part_4/ex16/db/top.map.hdb b/part_4/ex16/db/top.map.hdb
new file mode 100755
index 0000000..4ac2d2f
--- /dev/null
+++ b/part_4/ex16/db/top.map.hdb
diff --git a/part_4/ex16/db/top.map.kpt b/part_4/ex16/db/top.map.kpt
new file mode 100755
index 0000000..0e4c021
--- /dev/null
+++ b/part_4/ex16/db/top.map.kpt
diff --git a/part_4/ex16/db/top.map.logdb b/part_4/ex16/db/top.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex16/db/top.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex16/db/top.map.qmsg b/part_4/ex16/db/top.map.qmsg
new file mode 100755
index 0000000..905bb7d
--- /dev/null
+++ b/part_4/ex16/db/top.map.qmsg
@@ -0,0 +1,92 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1477845592481 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477845592481 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 16:39:52 2016 " "Processing started: Sun Oct 30 16:39:52 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477845592481 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845592481 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top -c top " "Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845592481 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1477845593434 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Analysis & Synthesis" 0 -1 1477845593434 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/_my documents/ee2 digital - new experiment/veri/library/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file /_my documents/ee2 digital - new experiment/veri/library/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "../Library/add3_ge5.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Library/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627778 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627778 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "delay DELAY echo_feedback.v(15) " "Verilog HDL Declaration information at echo_feedback.v(15): object \"delay\" differs only in case from object \"DELAY\" in the same scope" {  } { { "echo_feedback.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/echo_feedback.v" 15 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845627778 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "echo_feedback.v 1 1 " "Found 1 design units, including 1 entities, in source file echo_feedback.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "echo_feedback.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/echo_feedback.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627794 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627794 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "pwm.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627809 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627809 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "edge_detect.v " "Can't analyze file -- file edge_detect.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1477845627809 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" {  } { { "pulse_gen.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/pulse_gen.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627825 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627825 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627840 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627840 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "ROM.v " "Can't analyze file -- file ROM.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1477845627856 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" {  } { { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627887 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627887 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_div.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Found entity 1: clk_div" {  } { { "clk_div.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/clk_div.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627903 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627903 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "accumulator.v " "Can't analyze file -- file accumulator.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1477845627919 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "spi2dac.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627934 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627934 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "spi2adc.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845627950 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845627950 ""}
+{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "LEDG top.v(66) " "Verilog HDL Implicit Net warning at top.v(66): created implicit net for \"LEDG\"" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 66 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845627950 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1477845628325 ""}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "LEDG top.v(66) " "Verilog HDL or VHDL warning at top.v(66): object \"LEDG\" assigned a value but never read" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 66 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1477845628325 "|top"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "10 1 top.v(66) " "Verilog HDL assignment warning at top.v(66): truncated value with size 10 to match size of target (1)" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1477845628325 "|top"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_div clk_div:GEN_10K " "Elaborating entity \"clk_div\" for hierarchy \"clk_div:GEN_10K\"" {  } { { "top.v" "GEN_10K" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628341 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pulse_gen pulse_gen:PULSE " "Elaborating entity \"pulse_gen\" for hierarchy \"pulse_gen:PULSE\"" {  } { { "top.v" "PULSE" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 39 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628341 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" {  } { { "top.v" "SPI_DAC" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 42 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628341 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" {  } { { "top.v" "PWM_DC" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 43 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628356 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "top.v" "SPI_ADC" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 54 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628356 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:ECHO " "Elaborating entity \"processor\" for hierarchy \"processor:ECHO\"" {  } { { "top.v" "ECHO" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 56 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628356 ""}
+{ "Warning" "WSGN_SEARCH_FILE" "delay_ram.v 1 1 " "Using design file delay_ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "delay_ram.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845628387 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1477845628387 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay_ram processor:ECHO\|delay_ram:DELAY " "Elaborating entity \"delay_ram\" for hierarchy \"processor:ECHO\|delay_ram:DELAY\"" {  } { { "echo_feedback.v" "DELAY" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/echo_feedback.v" 47 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628387 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\"" {  } { { "delay_ram.v" "altsyncram_component" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v" 91 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628575 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\"" {  } { { "delay_ram.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v" 91 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628575 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component " "Instantiated megafunction \"processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone III " "Parameter \"intended_device_family\" = \"Cyclone III\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8192 " "Parameter \"numwords_a\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8192 " "Parameter \"numwords_b\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 13 " "Parameter \"widthad_a\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 13 " "Parameter \"widthad_b\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 9 " "Parameter \"width_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628575 ""}  } { { "delay_ram.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v" 91 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1477845628575 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ip02.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ip02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ip02 " "Found entity 1: altsyncram_ip02" {  } { { "db/altsyncram_ip02.tdf" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/altsyncram_ip02.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845628684 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845628684 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ip02 processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\|altsyncram_ip02:auto_generated " "Elaborating entity \"altsyncram_ip02\" for hierarchy \"processor:ECHO\|delay_ram:DELAY\|altsyncram:altsyncram_component\|altsyncram_ip02:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628684 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multiply_k multiply_k:SCALER " "Elaborating entity \"multiply_k\" for hierarchy \"multiply_k:SCALER\"" {  } { { "top.v" "SCALER" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 58 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628700 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "multiply_k.v" "lpm_mult_component" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628794 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628794 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 9 " "Parameter \"lpm_widtha\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 11 " "Parameter \"lpm_widthb\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 20 " "Parameter \"lpm_widthp\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1477845628794 ""}  } { { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1477845628794 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multcore multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core " "Elaborating entity \"multcore\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\"" {  } { { "lpm_mult.tdf" "mult_core" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628872 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628872 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder " "Elaborating entity \"mpar_add\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\"" {  } { { "multcore.tdf" "padder" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628903 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "multcore.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628919 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628950 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845628950 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_a9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_a9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_a9h " "Found entity 1: add_sub_a9h" {  } { { "db/add_sub_a9h.tdf" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/add_sub_a9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845629075 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845629075 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_a9h multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated " "Elaborating entity \"add_sub_a9h\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629090 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add " "Elaborating entity \"mpar_add\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\"" {  } { { "mpar_add.tdf" "sub_par_add" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629090 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629090 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629122 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629122 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_e9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_e9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_e9h " "Found entity 1: add_sub_e9h" {  } { { "db/add_sub_e9h.tdf" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/add_sub_e9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845629200 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845629200 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_e9h multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated " "Elaborating entity \"add_sub_e9h\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629200 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift multiply_k:SCALER\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs " "Elaborating entity \"altshift\" for hierarchy \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\"" {  } { { "lpm_mult.tdf" "external_latency_ffs" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629231 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "multiply_k:SCALER\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs multiply_k:SCALER\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"multiply_k:SCALER\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } } { "multiply_k.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v" 57 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629231 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd.v(19) " "Verilog HDL Declaration information at bin2bcd.v(19): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 19 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629247 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629262 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629262 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629262 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629262 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629262 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629262 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629278 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629278 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629309 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629309 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629309 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd.v(20) " "Verilog HDL Declaration information at bin2bcd.v(20): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1477845629309 ""}
+{ "Warning" "WSGN_SEARCH_FILE" "bin2bcd.v 1 1 " "Using design file bin2bcd.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd " "Found entity 1: bin2bcd" {  } { { "bin2bcd.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845629309 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1477845629309 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd bin2bcd:BCD_CONVERT " "Elaborating entity \"bin2bcd\" for hierarchy \"bin2bcd:BCD_CONVERT\"" {  } { { "top.v" "BCD_CONVERT" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 59 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629309 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 bin2bcd:BCD_CONVERT\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"bin2bcd:BCD_CONVERT\|add3_ge5:A1\"" {  } { { "bin2bcd.v" "A1" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629309 ""}
+{ "Warning" "WSGN_SEARCH_FILE" "hex_to_7seg.v 1 1 " "Using design file hex_to_7seg.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "hex_to_7seg.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1477845629481 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1477845629481 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "top.v" "SEG0" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 61 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845629481 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] GND " "Pin \"HEX3\[1\]\" is stuck at GND" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 18 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1477845631325 "|top|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] GND " "Pin \"HEX3\[2\]\" is stuck at GND" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 18 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1477845631325 "|top|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Pin \"HEX3\[6\]\" is stuck at VCC" {  } { { "top.v" "" { Text "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v" 18 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1477845631325 "|top|HEX3[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1477845631325 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1477845631590 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 " "4 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1477845632137 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.map.smsg " "Generated suppressed messages file Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845632340 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1477845632747 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1477845632747 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "326 " "Implemented 326 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1477845633169 ""} { "Info" "ICUT_CUT_TM_OPINS" "36 " "Implemented 36 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1477845633169 ""} { "Info" "ICUT_CUT_TM_LCELLS" "269 " "Implemented 269 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1477845633169 ""} { "Info" "ICUT_CUT_TM_RAMS" "9 " "Implemented 9 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1477845633169 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1477845633169 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "882 " "Peak virtual memory: 882 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477845633309 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 16:40:33 2016 " "Processing ended: Sun Oct 30 16:40:33 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477845633309 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:41 " "Elapsed time: 00:00:41" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477845633309 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477845633309 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1477845633309 ""}
diff --git a/part_4/ex16/db/top.map.rdb b/part_4/ex16/db/top.map.rdb
new file mode 100755
index 0000000..2247163
--- /dev/null
+++ b/part_4/ex16/db/top.map.rdb
diff --git a/part_4/ex16/db/top.map_bb.cdb b/part_4/ex16/db/top.map_bb.cdb
new file mode 100755
index 0000000..cc75cf5
--- /dev/null
+++ b/part_4/ex16/db/top.map_bb.cdb
diff --git a/part_4/ex16/db/top.map_bb.hdb b/part_4/ex16/db/top.map_bb.hdb
new file mode 100755
index 0000000..0cb7ab8
--- /dev/null
+++ b/part_4/ex16/db/top.map_bb.hdb
diff --git a/part_4/ex16/db/top.map_bb.logdb b/part_4/ex16/db/top.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex16/db/top.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex16/db/top.pre_map.hdb b/part_4/ex16/db/top.pre_map.hdb
new file mode 100755
index 0000000..6bfdc68
--- /dev/null
+++ b/part_4/ex16/db/top.pre_map.hdb
diff --git a/part_4/ex16/db/top.root_partition.map.reg_db.cdb b/part_4/ex16/db/top.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..5b10715
--- /dev/null
+++ b/part_4/ex16/db/top.root_partition.map.reg_db.cdb
diff --git a/part_4/ex16/db/top.routing.rdb b/part_4/ex16/db/top.routing.rdb
new file mode 100755
index 0000000..4dbf2a3
--- /dev/null
+++ b/part_4/ex16/db/top.routing.rdb
diff --git a/part_4/ex16/db/top.rtlv.hdb b/part_4/ex16/db/top.rtlv.hdb
new file mode 100755
index 0000000..c4a6c26
--- /dev/null
+++ b/part_4/ex16/db/top.rtlv.hdb
diff --git a/part_4/ex16/db/top.rtlv_sg.cdb b/part_4/ex16/db/top.rtlv_sg.cdb
new file mode 100755
index 0000000..748904e
--- /dev/null
+++ b/part_4/ex16/db/top.rtlv_sg.cdb
diff --git a/part_4/ex16/db/top.rtlv_sg_swap.cdb b/part_4/ex16/db/top.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..51aac31
--- /dev/null
+++ b/part_4/ex16/db/top.rtlv_sg_swap.cdb
diff --git a/part_4/ex16/db/top.sld_design_entry.sci b/part_4/ex16/db/top.sld_design_entry.sci
new file mode 100755
index 0000000..3f06067
--- /dev/null
+++ b/part_4/ex16/db/top.sld_design_entry.sci
diff --git a/part_4/ex16/db/top.sld_design_entry_dsc.sci b/part_4/ex16/db/top.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..3f06067
--- /dev/null
+++ b/part_4/ex16/db/top.sld_design_entry_dsc.sci
diff --git a/part_4/ex16/db/top.smart_action.txt b/part_4/ex16/db/top.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_4/ex16/db/top.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/part_4/ex16/db/top.smp_dump.txt b/part_4/ex16/db/top.smp_dump.txt
new file mode 100755
index 0000000..e7a764e
--- /dev/null
+++ b/part_4/ex16/db/top.smp_dump.txt
@@ -0,0 +1,24 @@
+
+State Machine - |top|processor:ECHO|pulse_gen:PULSE2|state
+Name state.IDLE state.WAIT_LOW state.IN_HIGH 
+state.IDLE 0 0 0 
+state.IN_HIGH 1 0 1 
+state.WAIT_LOW 1 1 0 
+
+State Machine - |top|spi2adc:SPI_ADC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
+
+State Machine - |top|spi2dac:SPI_DAC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
+
+State Machine - |top|pulse_gen:PULSE|state
+Name state.IDLE state.WAIT_LOW state.IN_HIGH 
+state.IDLE 0 0 0 
+state.IN_HIGH 1 0 1 
+state.WAIT_LOW 1 1 0 
diff --git a/part_4/ex16/db/top.sta.qmsg b/part_4/ex16/db/top.sta.qmsg
new file mode 100755
index 0000000..6ad452d
--- /dev/null
+++ b/part_4/ex16/db/top.sta.qmsg
@@ -0,0 +1,66 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1477845761122 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1477845761169 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Oct 30 16:42:39 2016 " "Processing started: Sun Oct 30 16:42:39 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1477845761169 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845761169 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta top -c top " "Command: quartus_sta top -c top" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845761169 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1477845761497 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845762700 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" {  } {  } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845762700 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845762778 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845762778 ""}
+{ "Info" "ISTA_SDC_FOUND" "top.sdc " "Reading SDC File: 'top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845763934 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." {  } {  } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845763950 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[8\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[8\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845763950 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845763950 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[2\]~DUPLICATE spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[2\]~DUPLICATE is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845763950 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845763950 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845763950 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845763950 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845763950 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1477845763950 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1477845763981 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.175 " "Worst-case setup slack is 14.175" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764059 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.175               0.000 CLOCK_50  " "   14.175               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764059 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845764059 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.372 " "Worst-case hold slack is 0.372" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764075 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764075 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.372               0.000 CLOCK_50  " "    0.372               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764075 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845764075 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845764075 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845764075 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.794 " "Worst-case minimum pulse width slack is 8.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.794               0.000 CLOCK_50  " "    8.794               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845764090 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845764090 ""}
+{ "Warning" "WSTA_METASTABILITY_REPORT_DISALLOW_GLOBAL_OFF" "" "Ignoring Synchronizer Identification setting Off, and using Auto instead." {  } {  } 0 18330 "Ignoring Synchronizer Identification setting Off, and using Auto instead." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845764090 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845764137 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 9 " "Number of Synchronizer Chains Found: 9" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845764137 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845764137 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845764137 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 31.891 ns " "Worst Case Available Settling Time: 31.891 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845764137 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845764137 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845764137 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1477845764153 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845764231 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767169 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[8\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[8\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845767372 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767372 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[2\]~DUPLICATE spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[2\]~DUPLICATE is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845767372 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767372 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845767372 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767372 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767372 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.064 " "Worst-case setup slack is 14.064" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767387 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767387 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.064               0.000 CLOCK_50  " "   14.064               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767387 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767387 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.381 " "Worst-case hold slack is 0.381" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.381               0.000 CLOCK_50  " "    0.381               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767403 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767403 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767403 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767403 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.761 " "Worst-case minimum pulse width slack is 8.761" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.761               0.000 CLOCK_50  " "    8.761               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845767403 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767403 ""}
+{ "Warning" "WSTA_METASTABILITY_REPORT_DISALLOW_GLOBAL_OFF" "" "Ignoring Synchronizer Identification setting Off, and using Auto instead." {  } {  } 0 18330 "Ignoring Synchronizer Identification setting Off, and using Auto instead." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767419 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845767481 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 9 " "Number of Synchronizer Chains Found: 9" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845767481 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845767481 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845767481 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 31.751 ns " "Worst Case Available Settling Time: 31.751 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845767481 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845767481 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767481 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1477845767497 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845767809 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770466 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[8\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[8\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845770669 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770669 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[2\]~DUPLICATE spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[2\]~DUPLICATE is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845770669 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770669 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845770669 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770669 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770669 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 16.618 " "Worst-case setup slack is 16.618" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.618               0.000 CLOCK_50  " "   16.618               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770684 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770684 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.180 " "Worst-case hold slack is 0.180" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.180               0.000 CLOCK_50  " "    0.180               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770684 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770684 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770684 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770731 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.475 " "Worst-case minimum pulse width slack is 8.475" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770731 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770731 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.475               0.000 CLOCK_50  " "    8.475               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845770731 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770731 ""}
+{ "Warning" "WSTA_METASTABILITY_REPORT_DISALLOW_GLOBAL_OFF" "" "Ignoring Synchronizer Identification setting Off, and using Auto instead." {  } {  } 0 18330 "Ignoring Synchronizer Identification setting Off, and using Auto instead." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770731 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845770762 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 9 " "Number of Synchronizer Chains Found: 9" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845770762 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845770762 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845770762 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 35.199 ns " "Worst Case Available Settling Time: 35.199 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845770762 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845770762 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845770762 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1477845770778 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|clk_1MHz " "Node: spi2adc:SPI_ADC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2adc:SPI_ADC\|data_from_adc\[8\] spi2adc:SPI_ADC\|clk_1MHz " "Register spi2adc:SPI_ADC\|data_from_adc\[8\] is being clocked by spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845771090 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771090 "|top|spi2adc:SPI_ADC|clk_1MHz"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2adc:SPI_ADC\|adc_cs " "Node: spi2adc:SPI_ADC\|adc_cs was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register processor:ECHO\|ctr\[2\]~DUPLICATE spi2adc:SPI_ADC\|adc_cs " "Register processor:ECHO\|ctr\[2\]~DUPLICATE is being clocked by spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845771090 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771090 "|top|spi2adc:SPI_ADC|adc_cs"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi2dac:SPI_DAC\|clk_1MHz " "Node: spi2dac:SPI_DAC\|clk_1MHz was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi2dac:SPI_DAC\|shift_reg\[11\] spi2dac:SPI_DAC\|clk_1MHz " "Register spi2dac:SPI_DAC\|shift_reg\[11\] is being clocked by spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1477845771090 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771090 "|top|spi2dac:SPI_DAC|clk_1MHz"}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771090 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 16.816 " "Worst-case setup slack is 16.816" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771090 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.816               0.000 CLOCK_50  " "   16.816               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771090 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771090 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.172 " "Worst-case hold slack is 0.172" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172               0.000 CLOCK_50  " "    0.172               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771106 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771106 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771106 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771106 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 8.429 " "Worst-case minimum pulse width slack is 8.429" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    8.429               0.000 CLOCK_50  " "    8.429               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1477845771106 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771106 ""}
+{ "Warning" "WSTA_METASTABILITY_REPORT_DISALLOW_GLOBAL_OFF" "" "Ignoring Synchronizer Identification setting Off, and using Auto instead." {  } {  } 0 18330 "Ignoring Synchronizer Identification setting Off, and using Auto instead." 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771122 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845771169 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 9 " "Number of Synchronizer Chains Found: 9" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845771169 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845771169 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845771169 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 35.415 ns " "Worst Case Available Settling Time: 35.415 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845771169 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1477845771169 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845771169 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845774184 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845774215 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 17 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1193 " "Peak virtual memory: 1193 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1477845774528 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 30 16:42:54 2016 " "Processing ended: Sun Oct 30 16:42:54 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1477845774528 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1477845774528 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1477845774528 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1477845774528 ""}
diff --git a/part_4/ex16/db/top.sta.rdb b/part_4/ex16/db/top.sta.rdb
new file mode 100755
index 0000000..f6eb0fb
--- /dev/null
+++ b/part_4/ex16/db/top.sta.rdb
diff --git a/part_4/ex16/db/top.tis_db_list.ddb b/part_4/ex16/db/top.tis_db_list.ddb
new file mode 100755
index 0000000..3424556
--- /dev/null
+++ b/part_4/ex16/db/top.tis_db_list.ddb
diff --git a/part_4/ex16/db/top.tiscmp.fast_1100mv_0c.ddb b/part_4/ex16/db/top.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..01870dd
--- /dev/null
+++ b/part_4/ex16/db/top.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_4/ex16/db/top.tiscmp.fast_1100mv_85c.ddb b/part_4/ex16/db/top.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..ce2d408
--- /dev/null
+++ b/part_4/ex16/db/top.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_4/ex16/db/top.tiscmp.slow_1100mv_0c.ddb b/part_4/ex16/db/top.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..dc7b19e
--- /dev/null
+++ b/part_4/ex16/db/top.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_4/ex16/db/top.tiscmp.slow_1100mv_85c.ddb b/part_4/ex16/db/top.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..ab1e217
--- /dev/null
+++ b/part_4/ex16/db/top.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_4/ex16/db/top.vpr.ammdb b/part_4/ex16/db/top.vpr.ammdb
new file mode 100755
index 0000000..76001f8
--- /dev/null
+++ b/part_4/ex16/db/top.vpr.ammdb
diff --git a/part_4/ex16/db/top_partition_pins.json b/part_4/ex16/db/top_partition_pins.json
new file mode 100755
index 0000000..b8750be
--- /dev/null
+++ b/part_4/ex16/db/top_partition_pins.json
@@ -0,0 +1,189 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[5]",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_LD",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "PWM_OUT",
+					"strict" : false
+				},
+				{
+					"name" : "SW[8]",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				},
+				{
+					"name" : "SW[9]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[6]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[5]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[4]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[3]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[2]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[1]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[0]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[7]",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDO",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
+\ No newline at end of file
diff --git a/part_4/ex16/delay_ram.v b/part_4/ex16/delay_ram.v
new file mode 100755
index 0000000..23d49af
--- /dev/null
+++ b/part_4/ex16/delay_ram.v
@@ -0,0 +1,220 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: delay_ram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module delay_ram (
+	clock,
+	data,
+	rdaddress,
+	rden,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[8:0]  data;
+	input	[12:0]  rdaddress;
+	input	  rden;
+	input	[12:0]  wraddress;
+	input	  wren;
+	output	[8:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [8:0] sub_wire0;
+	wire [8:0] q = sub_wire0[8:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.rden_b (rden),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({9{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 8192,
+		altsyncram_component.numwords_b = 8192,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "CLOCK0",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.rdcontrol_reg_b = "CLOCK0",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 13,
+		altsyncram_component.widthad_b = 13,
+		altsyncram_component.width_a = 9,
+		altsyncram_component.width_b = 9,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
+// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
+// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex16/ex16.qpf b/part_4/ex16/ex16.qpf
new file mode 100755
index 0000000..5a0c878
--- /dev/null
+++ b/part_4/ex16/ex16.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 132 02/25/2009 SJ Web Edition
+# Date created = 11:14:45  November 20, 2011
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "11:14:45  November 20, 2011"
+
+# Revisions
+
+PROJECT_REVISION = "ex16_top"
diff --git a/part_4/ex16/ex16_top.asm.rpt b/part_4/ex16/ex16_top.asm.rpt
new file mode 100755
index 0000000..55462d7
--- /dev/null
+++ b/part_4/ex16/ex16_top.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex16_top
+Fri Dec 02 09:33:33 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/New folder/ex16/ex16_top.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Dec 02 09:33:33 2016 ;
+; Revision Name         ; ex16_top                              ;
+; Top-level Entity Name ; ex16_top                              ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CSEMA5F31C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++---------------------------------+
+; Assembler Generated Files       ;
++---------------------------------+
+; File Name                       ;
++---------------------------------+
+; C:/New folder/ex16/ex16_top.sof ;
++---------------------------------+
+
+
++-----------------------------------------------------------+
+; Assembler Device Options: C:/New folder/ex16/ex16_top.sof ;
++----------------+------------------------------------------+
+; Option         ; Setting                                  ;
++----------------+------------------------------------------+
+; Device         ; 5CSEMA5F31C6                             ;
+; JTAG usercode  ; 0x00B14F6D                               ;
+; Checksum       ; 0x00B14F6D                               ;
++----------------+------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 09:33:27 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex16 -c ex16_top
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 896 megabytes
+    Info: Processing ended: Fri Dec 02 09:33:33 2016
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/part_4/ex16/ex16_top.done b/part_4/ex16/ex16_top.done
new file mode 100755
index 0000000..4a9565a
--- /dev/null
+++ b/part_4/ex16/ex16_top.done
@@ -0,0 +1 @@
+Fri Dec 02 09:33:42 2016
diff --git a/part_4/ex16/ex16_top.eda.rpt b/part_4/ex16/ex16_top.eda.rpt
new file mode 100755
index 0000000..5be0f7a
--- /dev/null
+++ b/part_4/ex16/ex16_top.eda.rpt
@@ -0,0 +1,96 @@
+EDA Netlist Writer report for ex16_top
+Fri Dec 02 09:33:42 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Fri Dec 02 09:33:42 2016 ;
+; Revision Name             ; ex16_top                              ;
+; Top-level Entity Name     ; ex16_top                              ;
+; Family                    ; Cyclone V                             ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                           ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option                                                                                            ; Setting                   ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
+; Generate functional simulation netlist                                                            ; Off                       ;
+; Time scale                                                                                        ; 1 ps                      ;
+; Truncate long hierarchy paths                                                                     ; Off                       ;
+; Map illegal HDL characters                                                                        ; Off                       ;
+; Flatten buses into individual nodes                                                               ; Off                       ;
+; Maintain hierarchy                                                                                ; Off                       ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
+; Enable glitch filtering                                                                           ; Off                       ;
+; Do not write top level VHDL entity                                                                ; Off                       ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
+; Architecture name in VHDL output netlist                                                          ; structure                 ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++----------------------------------------------------+
+; Simulation Generated Files                         ;
++----------------------------------------------------+
+; Generated Files                                    ;
++----------------------------------------------------+
+; C:/New folder/ex16/simulation/modelsim/ex16_top.vo ;
++----------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 09:33:40 2016
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
+Info (204019): Generated file ex16_top.vo in folder "C:/New folder/ex16/simulation/modelsim/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
+    Info: Peak virtual memory: 811 megabytes
+    Info: Processing ended: Fri Dec 02 09:33:42 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/part_2/ex9_final/output_files/ex9.fit.rpt b/part_4/ex16/ex16_top.fit.rpt
index 06c3ae1..eb4d3c2 100755
--- a/part_2/ex9_final/output_files/ex9.fit.rpt
+++ b/part_4/ex16/ex16_top.fit.rpt
@@ -1,5 +1,5 @@
-Fitter report for ex9
-Fri Nov 25 12:11:01 2016
+Fitter report for ex16_top
+Fri Dec 02 09:33:26 2016
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 
 
@@ -64,16 +64,16 @@ agreement for further details.
 +-----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                    ;
 +---------------------------------+-------------------------------------------------+
-; Fitter Status                   ; Successful - Fri Nov 25 12:11:01 2016           ;
+; Fitter Status                   ; Successful - Fri Dec 02 09:33:26 2016           ;
 ; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
+; Revision Name                   ; ex16_top                                        ;
+; Top-level Entity Name           ; ex16_top                                        ;
 ; Family                          ; Cyclone V                                       ;
 ; Device                          ; 5CSEMA5F31C6                                    ;
 ; Timing Models                   ; Final                                           ;
-; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;
-; Total registers                 ; 95                                              ;
-; Total pins                      ; 57 / 457 ( 12 % )                               ;
+; Logic utilization (in ALMs)     ; 61 / 32,070 ( < 1 % )                           ;
+; Total registers                 ; 114                                             ;
+; Total pins                      ; 41 / 457 ( 9 % )                                ;
 ; Total virtual pins              ; 0                                               ;
 ; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
 ; Total RAM Blocks                ; 0 / 397 ( 0 % )                                 ;
@@ -154,14 +154,14 @@ agreement for further details.
 ; Number detected on machine ; 8           ;
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
-; Average used               ; 1.02        ;
+; Average used               ; 1.01        ;
 ; Maximum used               ; 4           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   0.9%      ;
-;     Processor 3            ;   0.8%      ;
-;     Processor 4            ;   0.8%      ;
+;     Processor 2            ;   0.4%      ;
+;     Processor 3            ;   0.4%      ;
+;     Processor 4            ;   0.4%      ;
 +----------------------------+-------------+
 
 
@@ -191,58 +191,31 @@ agreement for further details.
 ; HEX2[4]  ; Missing drive strength and slew rate ;
 ; HEX2[5]  ; Missing drive strength and slew rate ;
 ; HEX2[6]  ; Missing drive strength and slew rate ;
-; HEX3[0]  ; Missing drive strength and slew rate ;
-; HEX3[1]  ; Missing drive strength and slew rate ;
-; HEX3[2]  ; Missing drive strength and slew rate ;
-; HEX3[3]  ; Missing drive strength and slew rate ;
-; HEX3[4]  ; Missing drive strength and slew rate ;
-; HEX3[5]  ; Missing drive strength and slew rate ;
-; HEX3[6]  ; Missing drive strength and slew rate ;
-; HEX4[0]  ; Missing drive strength and slew rate ;
-; HEX4[1]  ; Missing drive strength and slew rate ;
-; HEX4[2]  ; Missing drive strength and slew rate ;
-; HEX4[3]  ; Missing drive strength and slew rate ;
-; HEX4[4]  ; Missing drive strength and slew rate ;
-; HEX4[5]  ; Missing drive strength and slew rate ;
-; HEX4[6]  ; Missing drive strength and slew rate ;
-; HEX5[0]  ; Missing drive strength and slew rate ;
-; HEX5[1]  ; Missing drive strength and slew rate ;
-; HEX5[2]  ; Missing drive strength and slew rate ;
-; HEX5[3]  ; Missing drive strength and slew rate ;
-; HEX5[4]  ; Missing drive strength and slew rate ;
-; HEX5[5]  ; Missing drive strength and slew rate ;
-; HEX5[6]  ; Missing drive strength and slew rate ;
-; LEDR[0]  ; Missing drive strength and slew rate ;
-; LEDR[1]  ; Missing drive strength and slew rate ;
-; LEDR[2]  ; Missing drive strength and slew rate ;
-; LEDR[3]  ; Missing drive strength and slew rate ;
-; LEDR[4]  ; Missing drive strength and slew rate ;
-; LEDR[5]  ; Missing drive strength and slew rate ;
-; LEDR[6]  ; Missing drive strength and slew rate ;
-; LEDR[7]  ; Missing drive strength and slew rate ;
-; LEDR[8]  ; Missing drive strength and slew rate ;
-; LEDR[9]  ; Missing drive strength and slew rate ;
+; DAC_SDI  ; Missing drive strength and slew rate ;
+; DAC_SCK  ; Missing drive strength and slew rate ;
+; DAC_CS   ; Missing drive strength and slew rate ;
+; DAC_LD   ; Missing drive strength and slew rate ;
+; ADC_SDI  ; Missing drive strength and slew rate ;
+; ADC_SCK  ; Missing drive strength and slew rate ;
+; ADC_CS   ; Missing drive strength and slew rate ;
+; PWM_OUT  ; Missing drive strength and slew rate ;
 +----------+--------------------------------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations                                                                                                                                                                                                            ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; Node                       ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                     ; Destination Port ; Destination Port Name ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0      ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                      ;                  ;                       ;
-; formula_fsm:FSM|count[6]   ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; formula_fsm:FSM|count[6]~DUPLICATE   ;                  ;                       ;
-; tick_50000:TICK0|count[0]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[0]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[1]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[2]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[5]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[8]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[8]~DUPLICATE  ;                  ;                       ;
-; tick_50000:TICK0|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[10]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[11]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[12]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[14]~DUPLICATE ;                  ;                       ;
-; tick_50000:TICK0|count[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; tick_50000:TICK0|count[15]~DUPLICATE ;                  ;                       ;
-+----------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------+------------------+-----------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                                  ;
++-------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------------+------------------+-----------------------+
+; Node                          ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                        ; Destination Port ; Destination Port Name ;
++-------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0         ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                         ;                  ;                       ;
+; clktick_16:GEN_10K|count[11]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[11]~DUPLICATE  ;                  ;                       ;
+; clktick_16:GEN_10K|count[14]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[14]~DUPLICATE  ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[2]        ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[2]~DUPLICATE        ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[4]        ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[4]~DUPLICATE        ;                  ;                       ;
+; spi2adc:SPI_ADC|shift_reg[1]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|shift_reg[1]~DUPLICATE  ;                  ;                       ;
+; spi2adc:SPI_ADC|shift_reg[2]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|shift_reg[2]~DUPLICATE  ;                  ;                       ;
+; spi2dac:SPI_DAC|sr_state.IDLE ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:SPI_DAC|sr_state.IDLE~DUPLICATE ;                  ;                       ;
++-------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+-----------------------------------------+------------------+-----------------------+
 
 
 +--------------------------------------------------------------------------------------------+
@@ -250,54 +223,86 @@ agreement for further details.
 +--------------+----------------+--------------+------------+---------------+----------------+
 ; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
 +--------------+----------------+--------------+------------+---------------+----------------+
-; Location     ;                ;              ; ADC_CS     ; PIN_AG20      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SCK    ; PIN_AF21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDI    ; PIN_AG21      ; QSF Assignment ;
-; Location     ;                ;              ; ADC_SDO    ; PIN_AJ21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_CS     ; PIN_AD20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_LD     ; PIN_AK21      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SCK    ; PIN_AF20      ; QSF Assignment ;
-; Location     ;                ;              ; DAC_SDI    ; PIN_AG18      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[0]    ; PIN_AD26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[1]    ; PIN_AC27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[2]    ; PIN_AD25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[3]    ; PIN_AC25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[4]    ; PIN_AB28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[5]    ; PIN_AB25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[6]    ; PIN_AB22      ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[0]    ; PIN_AA24      ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[1]    ; PIN_Y23       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[2]    ; PIN_Y24       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[3]    ; PIN_W22       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[4]    ; PIN_W24       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[5]    ; PIN_V23       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[6]    ; PIN_W25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[0]     ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]     ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
 ; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
-; Location     ;                ;              ; PWM_OUT    ; PIN_AJ20      ; QSF Assignment ;
-; Location     ;                ;              ; SW[0]      ; PIN_AB12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[1]      ; PIN_AC12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[2]      ; PIN_AF9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[3]      ; PIN_AF10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[4]      ; PIN_AD11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[5]      ; PIN_AD12      ; QSF Assignment ;
-; Location     ;                ;              ; SW[6]      ; PIN_AE11      ; QSF Assignment ;
-; Location     ;                ;              ; SW[7]      ; PIN_AC9       ; QSF Assignment ;
-; Location     ;                ;              ; SW[8]      ; PIN_AD10      ; QSF Assignment ;
-; Location     ;                ;              ; SW[9]      ; PIN_AE12      ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; ADC_SDO    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_CS     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_LD     ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_SCK    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; DAC_SDI    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; PWM_OUT    ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
-; I/O Standard ; ex9            ;              ; SW[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX3[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX3[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX3[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX3[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX3[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX3[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX3[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX4[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX4[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX4[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX4[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX4[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX4[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX4[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; KEY[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; KEY[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex16_top       ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
 +--------------+----------------+--------------+------------+---------------+----------------+
 
 
@@ -307,8 +312,8 @@ agreement for further details.
 ; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
 +---------------------+--------------------+----------------------------+--------------------------+
 ; Placement (by node) ;                    ;                            ;                          ;
-;     -- Requested    ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;
-;     -- Achieved     ; 0.00 % ( 0 / 489 ) ; 0.00 % ( 0 / 489 )         ; 0.00 % ( 0 / 489 )       ;
+;     -- Requested    ; 0.00 % ( 0 / 299 ) ; 0.00 % ( 0 / 299 )         ; 0.00 % ( 0 / 299 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 299 ) ; 0.00 % ( 0 / 299 )         ; 0.00 % ( 0 / 299 )       ;
 ;                     ;                    ;                            ;                          ;
 ; Routing (by net)    ;                    ;                            ;                          ;
 ;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
@@ -331,7 +336,7 @@ agreement for further details.
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
 ; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top                            ; 0.00 % ( 0 / 489 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; Top                            ; 0.00 % ( 0 / 299 )    ; N/A                     ; Source File       ; N/A                 ;       ;
 ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
 +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
 
@@ -339,7 +344,7 @@ agreement for further details.
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
+The pin-out file can be found in C:/New folder/ex16/ex16_top.pin.
 
 
 +------------------------------------------------------------------------------------------+
@@ -347,14 +352,14 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 +-------------------------------------------------------------+--------------------+-------+
 ; Resource                                                    ; Usage              ; %     ;
 +-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32,070       ; < 1 % ;
-; ALMs needed [=A-B+C]                                        ; 159                ;       ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32,070       ; < 1 % ;
-;         [a] ALMs used for LUT logic and registers           ; 36                 ;       ;
-;         [b] ALMs used for LUT logic                         ; 120                ;       ;
-;         [c] ALMs used for registers                         ; 6                  ;       ;
+; Logic utilization (ALMs needed / total ALMs on device)      ; 61 / 32,070        ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 61                 ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 73 / 32,070        ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 42                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 19                 ;       ;
+;         [c] ALMs used for registers                         ; 12                 ;       ;
 ;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32,070         ; < 1 % ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 12 / 32,070        ; < 1 % ;
 ;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
 ;         [a] Due to location constrained logic               ; 0                  ;       ;
 ;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
@@ -363,28 +368,28 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ;                                                             ;                    ;       ;
 ; Difficulty packing design                                   ; Low                ;       ;
 ;                                                             ;                    ;       ;
-; Total LABs:  partially or completely used                   ; 19 / 3,207         ; < 1 % ;
-;     -- Logic LABs                                           ; 19                 ;       ;
+; Total LABs:  partially or completely used                   ; 14 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 14                 ;       ;
 ;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
 ;                                                             ;                    ;       ;
-; Combinational ALUT usage for logic                          ; 290                ;       ;
+; Combinational ALUT usage for logic                          ; 109                ;       ;
 ;     -- 7 input functions                                    ; 0                  ;       ;
-;     -- 6 input functions                                    ; 41                 ;       ;
-;     -- 5 input functions                                    ; 5                  ;       ;
-;     -- 4 input functions                                    ; 157                ;       ;
-;     -- <=3 input functions                                  ; 87                 ;       ;
-; Combinational ALUT usage for route-throughs                 ; 1                  ;       ;
-; Dedicated logic registers                                   ; 95                 ;       ;
+;     -- 6 input functions                                    ; 9                  ;       ;
+;     -- 5 input functions                                    ; 15                 ;       ;
+;     -- 4 input functions                                    ; 30                 ;       ;
+;     -- <=3 input functions                                  ; 55                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 10                 ;       ;
+; Dedicated logic registers                                   ; 114                ;       ;
 ;     -- By type:                                             ;                    ;       ;
-;         -- Primary logic registers                          ; 84 / 64,140        ; < 1 % ;
-;         -- Secondary logic registers                        ; 11 / 64,140        ; < 1 % ;
+;         -- Primary logic registers                          ; 107 / 64,140       ; < 1 % ;
+;         -- Secondary logic registers                        ; 7 / 64,140         ; < 1 % ;
 ;     -- By function:                                         ;                    ;       ;
-;         -- Design implementation registers                  ; 84                 ;       ;
-;         -- Routing optimization registers                   ; 11                 ;       ;
+;         -- Design implementation registers                  ; 107                ;       ;
+;         -- Routing optimization registers                   ; 7                  ;       ;
 ;                                                             ;                    ;       ;
 ; Virtual pins                                                ; 0                  ;       ;
-; I/O pins                                                    ; 57 / 457           ; 12 %  ;
-;     -- Clock pins                                           ; 4 / 8              ; 50 %  ;
+; I/O pins                                                    ; 41 / 457           ; 9 %   ;
+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;
 ;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
 ;                                                             ;                    ;       ;
 ; Hard processor system peripheral utilization                ;                    ;       ;
@@ -435,12 +440,12 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
 ; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
 ; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
-; Average interconnect usage (total/H/V)                      ; 0.1% / 0.1% / 0.1% ;       ;
-; Peak interconnect usage (total/H/V)                         ; 2.7% / 3.0% / 1.9% ;       ;
-; Maximum fan-out                                             ; 68                 ;       ;
-; Highest non-global fan-out                                  ; 68                 ;       ;
-; Total fan-out                                               ; 1448               ;       ;
-; Average fan-out                                             ; 2.89               ;       ;
+; Average interconnect usage (total/H/V)                      ; 0.0% / 0.0% / 0.1% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 0.6% / 0.5% / 0.9% ;       ;
+; Maximum fan-out                                             ; 62                 ;       ;
+; Highest non-global fan-out                                  ; 33                 ;       ;
+; Total fan-out                                               ; 709                ;       ;
+; Average fan-out                                             ; 2.24               ;       ;
 +-------------------------------------------------------------+--------------------+-------+
 
 
@@ -449,14 +454,14 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 +-------------------------------------------------------------+-----------------------+--------------------------------+
 ; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
 +-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device)      ; 159 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-; ALMs needed [=A-B+C]                                        ; 159                   ; 0                              ;
-;     [A] ALMs used in final placement [=a+b+c+d]             ; 162 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
-;         [a] ALMs used for LUT logic and registers           ; 36                    ; 0                              ;
-;         [b] ALMs used for LUT logic                         ; 120                   ; 0                              ;
-;         [c] ALMs used for registers                         ; 6                     ; 0                              ;
+; Logic utilization (ALMs needed / total ALMs on device)      ; 61 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 61                    ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 73 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 42                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 19                    ; 0                              ;
+;         [c] ALMs used for registers                         ; 12                    ; 0                              ;
 ;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
-;     [B] Estimate of ALMs recoverable by dense packing       ; 3 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 12 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
 ;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
 ;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
 ;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
@@ -465,32 +470,32 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ;                                                             ;                       ;                                ;
 ; Difficulty packing design                                   ; Low                   ; Low                            ;
 ;                                                             ;                       ;                                ;
-; Total LABs:  partially or completely used                   ; 19 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
-;     -- Logic LABs                                           ; 19                    ; 0                              ;
+; Total LABs:  partially or completely used                   ; 14 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 14                    ; 0                              ;
 ;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
-; Combinational ALUT usage for logic                          ; 290                   ; 0                              ;
+; Combinational ALUT usage for logic                          ; 109                   ; 0                              ;
 ;     -- 7 input functions                                    ; 0                     ; 0                              ;
-;     -- 6 input functions                                    ; 41                    ; 0                              ;
-;     -- 5 input functions                                    ; 5                     ; 0                              ;
-;     -- 4 input functions                                    ; 157                   ; 0                              ;
-;     -- <=3 input functions                                  ; 87                    ; 0                              ;
-; Combinational ALUT usage for route-throughs                 ; 1                     ; 0                              ;
+;     -- 6 input functions                                    ; 9                     ; 0                              ;
+;     -- 5 input functions                                    ; 15                    ; 0                              ;
+;     -- 4 input functions                                    ; 30                    ; 0                              ;
+;     -- <=3 input functions                                  ; 55                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 10                    ; 0                              ;
 ; Memory ALUT usage                                           ; 0                     ; 0                              ;
 ;     -- 64-address deep                                      ; 0                     ; 0                              ;
 ;     -- 32-address deep                                      ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; Dedicated logic registers                                   ; 0                     ; 0                              ;
 ;     -- By type:                                             ;                       ;                                ;
-;         -- Primary logic registers                          ; 84 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
-;         -- Secondary logic registers                        ; 11 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;         -- Primary logic registers                          ; 107 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 7 / 64140 ( < 1 % )   ; 0 / 64140 ( 0 % )              ;
 ;     -- By function:                                         ;                       ;                                ;
-;         -- Design implementation registers                  ; 84                    ; 0                              ;
-;         -- Routing optimization registers                   ; 11                    ; 0                              ;
+;         -- Design implementation registers                  ; 107                   ; 0                              ;
+;         -- Routing optimization registers                   ; 7                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ;                                                             ;                       ;                                ;
 ; Virtual pins                                                ; 0                     ; 0                              ;
-; I/O pins                                                    ; 57                    ; 0                              ;
+; I/O pins                                                    ; 41                    ; 0                              ;
 ; I/O registers                                               ; 0                     ; 0                              ;
 ; Total block memory bits                                     ; 0                     ; 0                              ;
 ; Total block memory implementation bits                      ; 0                     ; 0                              ;
@@ -503,16 +508,16 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ;     -- Registered Output Connections                        ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; Internal Connections                                        ;                       ;                                ;
-;     -- Total Connections                                    ; 1448                  ; 0                              ;
-;     -- Registered Connections                               ; 438                   ; 0                              ;
+;     -- Total Connections                                    ; 709                   ; 0                              ;
+;     -- Registered Connections                               ; 424                   ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; External Connections                                        ;                       ;                                ;
 ;     -- Top                                                  ; 0                     ; 0                              ;
 ;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; Partition Interface                                         ;                       ;                                ;
-;     -- Input Ports                                          ; 5                     ; 0                              ;
-;     -- Output Ports                                         ; 52                    ; 0                              ;
+;     -- Input Ports                                          ; 12                    ; 0                              ;
+;     -- Output Ports                                         ; 29                    ; 0                              ;
 ;     -- Bidir Ports                                          ; 0                     ; 0                              ;
 ;                                                             ;                       ;                                ;
 ; Registered Ports                                            ;                       ;                                ;
@@ -536,11 +541,18 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
 ; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
 +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 27                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[0]   ; AA14  ; 3B       ; 36           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[1]   ; AA15  ; 3B       ; 36           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[2]   ; W15   ; 3B       ; 40           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
-; KEY[3]   ; Y16   ; 3B       ; 40           ; 0            ; 17           ; 3                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; ADC_SDO  ; AJ21  ; 4A       ; 62           ; 0            ; 51           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 64                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[0]    ; AB12  ; 3A       ; 12           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[1]    ; AC12  ; 3A       ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[2]    ; AF9   ; 3A       ; 8            ; 0            ; 34           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[3]    ; AF10  ; 3A       ; 4            ; 0            ; 51           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[4]    ; AD11  ; 3A       ; 2            ; 0            ; 40           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[5]    ; AD12  ; 3A       ; 16           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[6]    ; AE11  ; 3A       ; 4            ; 0            ; 34           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[7]    ; AC9   ; 3A       ; 4            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[8]    ; AD10  ; 3A       ; 4            ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[9]    ; AE12  ; 3A       ; 2            ; 0            ; 57           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
 +----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
 
 
@@ -549,6 +561,13 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 +---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
 ; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
 +---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; ADC_CS  ; AG20  ; 4A       ; 62           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; ADC_SCK ; AF21  ; 4A       ; 70           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; ADC_SDI ; AG21  ; 4A       ; 54           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_CS  ; AD20  ; 4A       ; 82           ; 0            ; 40           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_LD  ; AK21  ; 4A       ; 68           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SCK ; AF20  ; 4A       ; 70           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SDI ; AG18  ; 4A       ; 58           ; 0            ; 74           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
@@ -570,60 +589,30 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 ; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[0] ; V25   ; 5B       ; 89           ; 20           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[1] ; AA28  ; 5B       ; 89           ; 21           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[2] ; Y27   ; 5B       ; 89           ; 25           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[3] ; AB27  ; 5B       ; 89           ; 23           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[4] ; AB26  ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[5] ; AA26  ; 5B       ; 89           ; 23           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; HEX5[6] ; AA25  ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[0] ; V16   ; 4A       ; 52           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[1] ; W16   ; 4A       ; 52           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[2] ; V17   ; 4A       ; 60           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[3] ; V18   ; 4A       ; 80           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[4] ; W17   ; 4A       ; 60           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[5] ; W19   ; 4A       ; 80           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[6] ; Y19   ; 4A       ; 84           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[7] ; W20   ; 5A       ; 89           ; 6            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[8] ; W21   ; 5A       ; 89           ; 8            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
-; LEDR[9] ; Y21   ; 5A       ; 89           ; 6            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; PWM_OUT ; AJ20  ; 4A       ; 62           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
 +---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
 
 
-+-----------------------------------------------------------------------------+
-; I/O Bank Usage                                                              ;
-+----------+-------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+-------------------+---------------+--------------+---------------+
-; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
-; B1L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
-; 3A       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 3B       ; 5 / 48 ( 10 % )   ; 3.3V          ; --           ; 3.3V          ;
-; 4A       ; 7 / 80 ( 9 % )    ; 3.3V          ; --           ; 3.3V          ;
-; 5A       ; 32 / 32 ( 100 % ) ; 3.3V          ; --           ; 3.3V          ;
-; 5B       ; 13 / 16 ( 81 % )  ; 3.3V          ; --           ; 3.3V          ;
-; 6B       ; 0 / 44 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 6A       ; 0 / 56 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7A       ; 0 / 19 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7B       ; 0 / 22 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7C       ; 0 / 12 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 7D       ; 0 / 14 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-; 8A       ; 0 / 80 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
-+----------+-------------------+---------------+--------------+---------------+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 10 / 32 ( 31 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 3B       ; 1 / 48 ( 2 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 9 / 80 ( 11 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 15 / 32 ( 47 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 6 / 16 ( 38 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
 
 
 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -668,12 +657,12 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AA14     ; 122        ; 3B             ; KEY[0]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; AA15     ; 120        ; 3B             ; KEY[1]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -682,11 +671,11 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
-; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA25     ; 224        ; 5A             ; HEX5[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AA26     ; 252        ; 5B             ; HEX5[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA24     ; 228        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AA28     ; 251        ; 5B             ; HEX5[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -700,7 +689,7 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
 ; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AB12     ; 72         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB12     ; 72         ; 3A             ; SW[0]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -710,13 +699,13 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB22     ; 225        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB26     ; 226        ; 5A             ; HEX5[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB27     ; 254        ; 5B             ; HEX5[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB25     ; 230        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -727,10 +716,10 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
 ; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC9      ; 58         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; AC12     ; 82         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC9      ; 58         ; 3A             ; SW[7]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; SW[1]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
@@ -743,9 +732,9 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
@@ -756,11 +745,11 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD10     ; 56         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD11     ; 54         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD12     ; 80         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; SW[8]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD11     ; 54         ; 3A             ; SW[4]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD12     ; 80         ; 3A             ; SW[5]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -768,13 +757,13 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD20     ; 199        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; DAC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD26     ; 240        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
 ; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
@@ -789,8 +778,8 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
 ; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; AE11     ; 59         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AE12     ; 52         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE11     ; 59         ; 3A             ; SW[6]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE12     ; 52         ; 3A             ; SW[9]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
@@ -815,10 +804,10 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF9      ; 67         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF10     ; 57         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; SW[2]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF10     ; 57         ; 3A             ; SW[3]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -828,8 +817,8 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF20     ; 175        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AF21     ; 173        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; DAC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF21     ; 173        ; 4A             ; ADC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -842,7 +831,7 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -856,10 +845,10 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG18     ; 150        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; DAC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AG20     ; 157        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AG21     ; 143        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG20     ; 157        ; 4A             ; ADC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG21     ; 143        ; 4A             ; ADC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -918,8 +907,8 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ20     ; 158        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; AJ21     ; 156        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; PWM_OUT                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AJ21     ; 156        ; 4A             ; ADC_SDO                         ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
 ; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -948,7 +937,7 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; AK21     ; 171        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK21     ; 171        ; 4A             ; DAC_LD                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
 ; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
@@ -1452,16 +1441,16 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
 ; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; V16      ; 138        ; 4A             ; LEDR[0]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V17      ; 154        ; 4A             ; LEDR[2]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; V18      ; 194        ; 4A             ; LEDR[3]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V23      ; 236        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; V25      ; 246        ; 5B             ; HEX5[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
 ; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
@@ -1481,17 +1470,17 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
 ; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
-; W15      ; 130        ; 3B             ; KEY[2]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W16      ; 136        ; 4A             ; LEDR[1]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W17      ; 152        ; 4A             ; LEDR[4]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; W19      ; 192        ; 4A             ; LEDR[5]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
-; W20      ; 217        ; 5A             ; LEDR[7]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W21      ; 221        ; 5A             ; LEDR[8]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W22      ; 223        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
-; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W24      ; 238        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -1512,18 +1501,18 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 ; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
 ; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y16      ; 128        ; 3B             ; KEY[3]                          ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
-; Y19      ; 202        ; 4A             ; LEDR[6]                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
 ; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
-; Y21      ; 219        ; 5A             ; LEDR[9]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
-; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
-; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y23      ; 232        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y24      ; 234        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
 ; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
-; Y27      ; 258        ; 5B             ; HEX5[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
 ; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
@@ -1531,58 +1520,21 @@ The pin-out file can be found in C:/New folder/ex9/output_files/ex9.pin.
 Note: Pin directions (input, output or bidir) are based on device operating in user mode.
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                               ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name              ; Entity Name ; Library Name ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
-; |ex9                       ; 158.5 (0.5)          ; 161.5 (0.5)                      ; 3.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 290 (1)             ; 95 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 57   ; 0            ; |ex9                             ; ex9         ; work         ;
-;    |LFSR:LFSR0|            ; 3.0 (3.0)            ; 3.3 (3.3)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 7 (7)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|LFSR:LFSR0                  ; LFSR        ; work         ;
-;    |bin2bcd_16:BCD|        ; 67.7 (0.0)           ; 68.0 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 124 (0)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD              ; bin2bcd_16  ; work         ;
-;       |add3_ge5:A1|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A1  ; add3_ge5    ; work         ;
-;       |add3_ge5:A10|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A10 ; add3_ge5    ; work         ;
-;       |add3_ge5:A11|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A11 ; add3_ge5    ; work         ;
-;       |add3_ge5:A12|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A12 ; add3_ge5    ; work         ;
-;       |add3_ge5:A13|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A13 ; add3_ge5    ; work         ;
-;       |add3_ge5:A14|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A14 ; add3_ge5    ; work         ;
-;       |add3_ge5:A15|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A15 ; add3_ge5    ; work         ;
-;       |add3_ge5:A16|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A16 ; add3_ge5    ; work         ;
-;       |add3_ge5:A17|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A17 ; add3_ge5    ; work         ;
-;       |add3_ge5:A18|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A18 ; add3_ge5    ; work         ;
-;       |add3_ge5:A19|       ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A19 ; add3_ge5    ; work         ;
-;       |add3_ge5:A2|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A2  ; add3_ge5    ; work         ;
-;       |add3_ge5:A20|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A20 ; add3_ge5    ; work         ;
-;       |add3_ge5:A21|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A21 ; add3_ge5    ; work         ;
-;       |add3_ge5:A22|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A22 ; add3_ge5    ; work         ;
-;       |add3_ge5:A23|       ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A23 ; add3_ge5    ; work         ;
-;       |add3_ge5:A24|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A24 ; add3_ge5    ; work         ;
-;       |add3_ge5:A25|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A25 ; add3_ge5    ; work         ;
-;       |add3_ge5:A26|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A26 ; add3_ge5    ; work         ;
-;       |add3_ge5:A27|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A27 ; add3_ge5    ; work         ;
-;       |add3_ge5:A28|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A28 ; add3_ge5    ; work         ;
-;       |add3_ge5:A29|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A29 ; add3_ge5    ; work         ;
-;       |add3_ge5:A3|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A3  ; add3_ge5    ; work         ;
-;       |add3_ge5:A30|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A30 ; add3_ge5    ; work         ;
-;       |add3_ge5:A32|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A32 ; add3_ge5    ; work         ;
-;       |add3_ge5:A33|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A33 ; add3_ge5    ; work         ;
-;       |add3_ge5:A34|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A34 ; add3_ge5    ; work         ;
-;       |add3_ge5:A35|       ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A35 ; add3_ge5    ; work         ;
-;       |add3_ge5:A4|        ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A4  ; add3_ge5    ; work         ;
-;       |add3_ge5:A5|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A5  ; add3_ge5    ; work         ;
-;       |add3_ge5:A6|        ; 3.7 (3.7)            ; 4.0 (4.0)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A6  ; add3_ge5    ; work         ;
-;       |add3_ge5:A7|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A7  ; add3_ge5    ; work         ;
-;       |add3_ge5:A8|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A8  ; add3_ge5    ; work         ;
-;       |add3_ge5:A9|        ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|bin2bcd_16:BCD|add3_ge5:A9  ; add3_ge5    ; work         ;
-;    |counter_16:COUNT0|     ; 8.5 (8.5)            ; 8.6 (8.6)                        ; 0.1 (0.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 17 (17)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|counter_16:COUNT0           ; counter_16  ; work         ;
-;    |delay:DEL0|            ; 14.3 (14.3)          ; 15.4 (15.4)                      ; 1.1 (1.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 25 (25)             ; 18 (18)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|delay:DEL0                  ; delay       ; work         ;
-;    |formula_fsm:FSM|       ; 24.5 (24.5)          ; 25.3 (25.3)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 43 (43)             ; 26 (26)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|formula_fsm:FSM             ; formula_fsm ; work         ;
-;    |hex_to_7seg:SEG0|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG0            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG1|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG1            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG2|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG2            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG3|      ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG3            ; hex_to_7seg ; work         ;
-;    |hex_to_7seg:SEG4|      ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|hex_to_7seg:SEG4            ; hex_to_7seg ; work         ;
-;    |tick_50000:TICK0|      ; 18.5 (18.5)          ; 18.9 (18.9)                      ; 0.4 (0.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 36 (36)             ; 27 (27)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex9|tick_50000:TICK0            ; tick_50000  ; work         ;
-+----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+----------------------------------+-------------+--------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                           ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name          ; Entity Name ; Library Name ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------+-------------+--------------+
+; |ex16_top                  ; 61.0 (0.5)           ; 72.0 (0.5)                       ; 11.0 (0.0)                                        ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 109 (1)             ; 114 (0)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 41   ; 0            ; |ex16_top                    ; ex16_top    ; work         ;
+;    |clktick_16:GEN_10K|    ; 11.5 (11.5)          ; 12.0 (12.0)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 20 (20)             ; 19 (19)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex16_top|clktick_16:GEN_10K ; clktick_16  ; work         ;
+;    |hex_to_7seg:SEG0|      ; 2.5 (2.5)            ; 2.5 (2.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex16_top|hex_to_7seg:SEG0   ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 2.3 (2.3)            ; 2.3 (2.3)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex16_top|hex_to_7seg:SEG1   ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 1.0 (1.0)            ; 1.5 (1.5)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex16_top|hex_to_7seg:SEG2   ; hex_to_7seg ; work         ;
+;    |processor:ALLPASS|     ; 4.3 (4.3)            ; 4.5 (4.5)                        ; 0.3 (0.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 9 (9)               ; 8 (8)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex16_top|processor:ALLPASS  ; processor   ; work         ;
+;    |pwm:PWM_DC|            ; 9.5 (9.5)            ; 10.0 (10.0)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 15 (15)             ; 19 (19)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex16_top|pwm:PWM_DC         ; pwm         ; work         ;
+;    |spi2adc:SPI_ADC|       ; 14.9 (14.9)          ; 23.7 (23.7)                      ; 8.8 (8.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 21 (21)             ; 43 (43)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex16_top|spi2adc:SPI_ADC    ; spi2adc     ; work         ;
+;    |spi2dac:SPI_DAC|       ; 14.5 (14.5)          ; 15.0 (15.0)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 26 (26)             ; 25 (25)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex16_top|spi2dac:SPI_DAC    ; spi2dac     ; work         ;
++----------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+------------------------------+-------------+--------------+
 Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
 
 
@@ -1591,8 +1543,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
 ; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
 +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; KEY[1]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[2]   ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[0]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[1]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[2]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[3]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[4]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[5]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[6]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[7]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[8]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[9]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
 ; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
@@ -1614,76 +1574,57 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; HEX5[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[7]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[8]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; LEDR[9]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
-; KEY[0]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; DAC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_LD   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; PWM_OUT  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
 ; CLOCK_50 ; Input    ; -- ; (0)  ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
-; KEY[3]   ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; ADC_SDO  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
 +----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
 
 
-+-------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                                                ;
-+-------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout                             ; Pad To Core Index ; Setting ;
-+-------------------------------------------------+-------------------+---------+
-; KEY[1]                                          ;                   ;         ;
-; KEY[2]                                          ;                   ;         ;
-; KEY[0]                                          ;                   ;         ;
-;      - counter_16:COUNT0|count~0                ; 1                 ; 0       ;
-; CLOCK_50                                        ;                   ;         ;
-;      - tick_50000:TICK0|CLK_OUT                 ; 1                 ; 0       ;
-; KEY[3]                                          ;                   ;         ;
-;      - formula_fsm:FSM|Selector3~0              ; 1                 ; 0       ;
-;      - formula_fsm:FSM|state.WAIT_FOR_TIMEOUT~0 ; 1                 ; 0       ;
-;      - formula_fsm:FSM|Selector2~0              ; 1                 ; 0       ;
-+-------------------------------------------------+-------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                                                                                ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; Name                                ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50                            ; PIN_AF14           ; 2       ; Clock                      ; no     ; --                   ; --               ; --                        ;
-; CLOCK_50                            ; PIN_AF14           ; 26      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
-; counter_16:COUNT0|count~0           ; LABCELL_X60_Y4_N30 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; counter_16:COUNT0|state             ; FF_X59_Y4_N14      ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|count[5]~0               ; LABCELL_X62_Y4_N51 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; delay:DEL0|state.COUNTING           ; FF_X63_Y4_N56      ; 19      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; FF_X62_Y4_N56      ; 26      ; Clock enable, Latch enable ; no     ; --                   ; --               ; --                        ;
-; formula_fsm:FSM|state.WAIT_TRIGGER  ; FF_X61_Y4_N2       ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
-; tick_50000:TICK0|CLK_OUT            ; FF_X60_Y4_N2       ; 68      ; Clock                      ; no     ; --                   ; --               ; --                        ;
-+-------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
++--------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                           ;
++--------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                        ; Pad To Core Index ; Setting ;
++--------------------------------------------+-------------------+---------+
+; SW[0]                                      ;                   ;         ;
+; SW[1]                                      ;                   ;         ;
+; SW[2]                                      ;                   ;         ;
+; SW[3]                                      ;                   ;         ;
+; SW[4]                                      ;                   ;         ;
+; SW[5]                                      ;                   ;         ;
+; SW[6]                                      ;                   ;         ;
+; SW[7]                                      ;                   ;         ;
+; SW[8]                                      ;                   ;         ;
+; SW[9]                                      ;                   ;         ;
+; CLOCK_50                                   ;                   ;         ;
+;      - spi2dac:SPI_DAC|clk_1MHz            ; 1                 ; 0       ;
+;      - spi2adc:SPI_ADC|clk_1MHz            ; 1                 ; 0       ;
+; ADC_SDO                                    ;                   ;         ;
+;      - spi2adc:SPI_ADC|shift_reg[0]~feeder ; 1                 ; 0       ;
++--------------------------------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                           ;
++-----------------------------+---------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name                        ; Location            ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------+---------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                    ; PIN_AF14            ; 3       ; Clock        ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                    ; PIN_AF14            ; 62      ; Clock        ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; clktick_16:GEN_10K|Equal0~3 ; MLABCELL_X78_Y8_N15 ; 12      ; Sync. clear  ; no     ; --                   ; --               ; --                        ;
+; clktick_16:GEN_10K|tick     ; FF_X78_Y8_N32       ; 14      ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|adc_done    ; FF_X79_Y10_N20      ; 10      ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|always3~0   ; LABCELL_X79_Y10_N21 ; 12      ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|clk_1MHz    ; FF_X79_Y11_N11      ; 33      ; Clock        ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|Equal0~0    ; LABCELL_X80_Y11_N33 ; 2       ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|clk_1MHz    ; FF_X79_Y11_N8       ; 21      ; Clock        ; no     ; --                   ; --               ; --                        ;
++-----------------------------+---------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
 
 
 +-----------------------------------------------------------------------------------------------------+
@@ -1691,7 +1632,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------+----------+---------+----------------------+------------------+---------------------------+
 ; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
 +----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AF14 ; 26      ; Global Clock         ; GCLK6            ; --                        ;
+; CLOCK_50 ; PIN_AF14 ; 62      ; Global Clock         ; GCLK6            ; --                        ;
 +----------+----------+---------+----------------------+------------------+---------------------------+
 
 
@@ -1700,14 +1641,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +---------------------------------------------+-------------------------+
 ; Routing Resource Type                       ; Usage                   ;
 +---------------------------------------------+-------------------------+
-; Block interconnects                         ; 375 / 289,320 ( < 1 % ) ;
-; C12 interconnects                           ; 2 / 13,420 ( < 1 % )    ;
-; C2 interconnects                            ; 132 / 119,108 ( < 1 % ) ;
-; C4 interconnects                            ; 84 / 56,300 ( < 1 % )   ;
+; Block interconnects                         ; 154 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 6 / 13,420 ( < 1 % )    ;
+; C2 interconnects                            ; 43 / 119,108 ( < 1 % )  ;
+; C4 interconnects                            ; 41 / 56,300 ( < 1 % )   ;
 ; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
 ; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
 ; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
-; Direct links                                ; 62 / 289,320 ( < 1 % )  ;
+; Direct links                                ; 42 / 289,320 ( < 1 % )  ;
 ; Global clocks                               ; 1 / 16 ( 6 % )          ;
 ; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
 ; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
@@ -1763,12 +1704,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
 ; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
 ; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
-; Local interconnects                         ; 147 / 84,580 ( < 1 % )  ;
+; Local interconnects                         ; 66 / 84,580 ( < 1 % )   ;
 ; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
-; R14 interconnects                           ; 25 / 12,676 ( < 1 % )   ;
-; R14/C12 interconnect drivers                ; 26 / 20,720 ( < 1 % )   ;
-; R3 interconnects                            ; 160 / 130,992 ( < 1 % ) ;
-; R6 interconnects                            ; 252 / 266,960 ( < 1 % ) ;
+; R14 interconnects                           ; 15 / 12,676 ( < 1 % )   ;
+; R14/C12 interconnect drivers                ; 19 / 20,720 ( < 1 % )   ;
+; R3 interconnects                            ; 70 / 130,992 ( < 1 % )  ;
+; R6 interconnects                            ; 64 / 266,960 ( < 1 % )  ;
 ; Spine clocks                                ; 1 / 360 ( < 1 % )       ;
 ; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
 +---------------------------------------------+-------------------------+
@@ -1828,12 +1769,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
 ; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
 +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-; Total Pass         ; 57        ; 0            ; 57        ; 0            ; 0            ; 57        ; 57        ; 0            ; 57        ; 57        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Pass         ; 41        ; 0            ; 41        ; 0            ; 0            ; 41        ; 41        ; 0            ; 41        ; 41        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
 ; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
-; Total Inapplicable ; 0         ; 57           ; 0         ; 57           ; 57           ; 0         ; 0         ; 57           ; 0         ; 0         ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ; 57           ;
+; Total Inapplicable ; 0         ; 41           ; 0         ; 41           ; 41           ; 0         ; 0         ; 41           ; 0         ; 0         ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ;
 ; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
-; KEY[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
@@ -1855,40 +1804,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 ; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; HEX5[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[8]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; LEDR[9]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_LD             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; PWM_OUT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 ; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
-; KEY[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDO            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
 +--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
 
 
@@ -1935,114 +1860,69 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +---------------------------+--------+
 
 
-+-------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary                                                               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; Source Clock(s)                                              ; Destination Clock(s)     ; Delay Added in ns ;
-+--------------------------------------------------------------+--------------------------+-------------------+
-; tick_50000:TICK0|CLK_OUT                                     ; tick_50000:TICK0|CLK_OUT ; 62.3              ;
-; CLOCK_50                                                     ; CLOCK_50                 ; 9.8               ;
-; tick_50000:TICK0|CLK_OUT,formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT ; 3.7               ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS                          ; tick_50000:TICK0|CLK_OUT ; 3.2               ;
-; tick_50000:TICK0|CLK_OUT,I/O                                 ; tick_50000:TICK0|CLK_OUT ; 1.6               ;
-+--------------------------------------------------------------+--------------------------+-------------------+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+; CLOCK_50        ; CLOCK_50             ; 19.0              ;
++-----------------+----------------------+-------------------+
 Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
 This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
 
 
-+--------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details                                                    ;
-+----------------------------------------+-------------------------------------+-------------------+
-; Source Register                        ; Destination Register                ; Delay Added in ns ;
-+----------------------------------------+-------------------------------------+-------------------+
-; formula_fsm:FSM|state.LIGHT_UP_LEDS    ; formula_fsm:FSM|ledr[3]             ; 2.057             ;
-; formula_fsm:FSM|start_delay            ; delay:DEL0|state.IDLE               ; 1.568             ;
-; tick_50000:TICK0|count[5]              ; tick_50000:TICK0|CLK_OUT            ; 1.369             ;
-; tick_50000:TICK0|count[11]             ; tick_50000:TICK0|CLK_OUT            ; 1.341             ;
-; tick_50000:TICK0|count[14]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;
-; tick_50000:TICK0|count[15]             ; tick_50000:TICK0|CLK_OUT            ; 1.313             ;
-; tick_50000:TICK0|count[6]              ; tick_50000:TICK0|CLK_OUT            ; 1.267             ;
-; tick_50000:TICK0|count[12]             ; tick_50000:TICK0|CLK_OUT            ; 1.232             ;
-; tick_50000:TICK0|count[3]              ; tick_50000:TICK0|CLK_OUT            ; 1.227             ;
-; tick_50000:TICK0|count[8]              ; tick_50000:TICK0|CLK_OUT            ; 1.224             ;
-; tick_50000:TICK0|count[13]             ; tick_50000:TICK0|CLK_OUT            ; 1.214             ;
-; tick_50000:TICK0|count[9]              ; tick_50000:TICK0|CLK_OUT            ; 1.207             ;
-; tick_50000:TICK0|count[4]              ; tick_50000:TICK0|CLK_OUT            ; 1.206             ;
-; tick_50000:TICK0|count[7]              ; tick_50000:TICK0|CLK_OUT            ; 1.192             ;
-; tick_50000:TICK0|count[0]              ; tick_50000:TICK0|CLK_OUT            ; 1.189             ;
-; tick_50000:TICK0|count[1]              ; tick_50000:TICK0|CLK_OUT            ; 1.170             ;
-; tick_50000:TICK0|count[2]              ; tick_50000:TICK0|CLK_OUT            ; 1.169             ;
-; tick_50000:TICK0|count[10]             ; tick_50000:TICK0|CLK_OUT            ; 1.155             ;
-; delay:DEL0|count[13]                   ; delay:DEL0|count[11]                ; 0.995             ;
-; formula_fsm:FSM|count[1]               ; formula_fsm:FSM|count[1]            ; 0.879             ;
-; formula_fsm:FSM|count[6]               ; formula_fsm:FSM|count[5]            ; 0.876             ;
-; formula_fsm:FSM|count[9]               ; formula_fsm:FSM|count[5]            ; 0.866             ;
-; formula_fsm:FSM|state.WAIT_FOR_TIMEOUT ; formula_fsm:FSM|ledr[3]             ; 0.865             ;
-; delay:DEL0|state.IDLE                  ; delay:DEL0|state.COUNTING           ; 0.863             ;
-; formula_fsm:FSM|count[0]               ; formula_fsm:FSM|count[1]            ; 0.855             ;
-; formula_fsm:FSM|count[7]               ; formula_fsm:FSM|count[5]            ; 0.852             ;
-; delay:DEL0|count[0]                    ; delay:DEL0|count[11]                ; 0.851             ;
-; delay:DEL0|count[3]                    ; delay:DEL0|count[11]                ; 0.848             ;
-; delay:DEL0|count[9]                    ; delay:DEL0|count[11]                ; 0.836             ;
-; delay:DEL0|count[8]                    ; delay:DEL0|count[11]                ; 0.833             ;
-; delay:DEL0|count[1]                    ; delay:DEL0|count[11]                ; 0.830             ;
-; formula_fsm:FSM|ledr[0]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[1]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[2]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[3]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[4]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[5]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[6]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[7]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[8]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|ledr[9]                ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; KEY[3]                                 ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; formula_fsm:FSM|state.WAIT_TRIGGER     ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; delay:DEL0|state.TIME_OUT              ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.826             ;
-; delay:DEL0|count[6]                    ; delay:DEL0|count[11]                ; 0.820             ;
-; delay:DEL0|state.COUNTING              ; delay:DEL0|state.IDLE               ; 0.805             ;
-; formula_fsm:FSM|count[4]               ; formula_fsm:FSM|count[1]            ; 0.801             ;
-; delay:DEL0|count[7]                    ; delay:DEL0|count[11]                ; 0.800             ;
-; delay:DEL0|state.WAIT_LOW              ; delay:DEL0|state.IDLE               ; 0.784             ;
-; delay:DEL0|count[4]                    ; delay:DEL0|count[11]                ; 0.779             ;
-; formula_fsm:FSM|count[8]               ; formula_fsm:FSM|count[10]           ; 0.751             ;
-; delay:DEL0|count[10]                   ; delay:DEL0|count[11]                ; 0.743             ;
-; formula_fsm:FSM|count[2]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
-; formula_fsm:FSM|count[3]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
-; formula_fsm:FSM|count[5]               ; formula_fsm:FSM|count[1]            ; 0.743             ;
-; formula_fsm:FSM|count[10]              ; formula_fsm:FSM|count[5]            ; 0.741             ;
-; formula_fsm:FSM|count[11]              ; formula_fsm:FSM|count[5]            ; 0.741             ;
-; delay:DEL0|count[11]                   ; delay:DEL0|count[11]                ; 0.720             ;
-; delay:DEL0|count[12]                   ; delay:DEL0|count[11]                ; 0.714             ;
-; delay:DEL0|count[5]                    ; delay:DEL0|count[11]                ; 0.714             ;
-; LFSR:LFSR0|COUNT[1]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;
-; LFSR:LFSR0|COUNT[7]                    ; LFSR:LFSR0|COUNT[1]                 ; 0.700             ;
-; delay:DEL0|count[2]                    ; delay:DEL0|count[11]                ; 0.673             ;
-; LFSR:LFSR0|COUNT[5]                    ; LFSR:LFSR0|COUNT[6]                 ; 0.631             ;
-; LFSR:LFSR0|COUNT[3]                    ; LFSR:LFSR0|COUNT[4]                 ; 0.626             ;
-; LFSR:LFSR0|COUNT[4]                    ; LFSR:LFSR0|COUNT[5]                 ; 0.613             ;
-; LFSR:LFSR0|COUNT[6]                    ; LFSR:LFSR0|COUNT[7]                 ; 0.613             ;
-; LFSR:LFSR0|COUNT[2]                    ; delay:DEL0|count[8]                 ; 0.610             ;
-; counter_16:COUNT0|count[7]             ; counter_16:COUNT0|count[15]         ; 0.249             ;
-; counter_16:COUNT0|count[1]             ; counter_16:COUNT0|count[15]         ; 0.239             ;
-; counter_16:COUNT0|count[12]            ; counter_16:COUNT0|count[15]         ; 0.238             ;
-; counter_16:COUNT0|count[0]             ; counter_16:COUNT0|count[15]         ; 0.237             ;
-; counter_16:COUNT0|count[8]             ; counter_16:COUNT0|count[15]         ; 0.236             ;
-; counter_16:COUNT0|count[5]             ; counter_16:COUNT0|count[15]         ; 0.236             ;
-; counter_16:COUNT0|count[3]             ; counter_16:COUNT0|count[15]         ; 0.232             ;
-; counter_16:COUNT0|count[13]            ; counter_16:COUNT0|count[15]         ; 0.231             ;
-; counter_16:COUNT0|count[6]             ; counter_16:COUNT0|count[15]         ; 0.228             ;
-; counter_16:COUNT0|count[9]             ; counter_16:COUNT0|count[15]         ; 0.227             ;
-; counter_16:COUNT0|state                ; counter_16:COUNT0|state             ; 0.140             ;
-; KEY[0]                                 ; counter_16:COUNT0|state             ; 0.089             ;
-; counter_16:COUNT0|count[11]            ; counter_16:COUNT0|count[15]         ; 0.053             ;
-; counter_16:COUNT0|count[14]            ; counter_16:COUNT0|count[15]         ; 0.047             ;
-; counter_16:COUNT0|count[2]             ; counter_16:COUNT0|count[15]         ; 0.046             ;
-; counter_16:COUNT0|count[10]            ; counter_16:COUNT0|count[15]         ; 0.043             ;
-; counter_16:COUNT0|count[4]             ; counter_16:COUNT0|count[15]         ; 0.043             ;
-; tick_50000:TICK0|CLK_OUT               ; counter_16:COUNT0|state             ; 0.036             ;
-+----------------------------------------+-------------------------------------+-------------------+
-Note: This table only shows the top 86 path(s) that have the largest delay added for hold.
++-----------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                       ;
++----------------------------------------+----------------------------------------+-------------------+
+; Source Register                        ; Destination Register                   ; Delay Added in ns ;
++----------------------------------------+----------------------------------------+-------------------+
+; spi2adc:SPI_ADC|ctr[4]                 ; spi2adc:SPI_ADC|clk_1MHz               ; 1.598             ;
+; spi2adc:SPI_ADC|ctr[2]                 ; spi2adc:SPI_ADC|clk_1MHz               ; 1.578             ;
+; spi2adc:SPI_ADC|ctr[3]                 ; spi2adc:SPI_ADC|clk_1MHz               ; 1.560             ;
+; spi2adc:SPI_ADC|ctr[0]                 ; spi2adc:SPI_ADC|clk_1MHz               ; 1.551             ;
+; spi2adc:SPI_ADC|ctr[1]                 ; spi2adc:SPI_ADC|clk_1MHz               ; 1.523             ;
+; pwm:PWM_DC|d[8]                        ; pwm:PWM_DC|pwm_out                     ; 0.444             ;
+; pwm:PWM_DC|count[9]                    ; pwm:PWM_DC|pwm_out                     ; 0.429             ;
+; spi2dac:SPI_DAC|sr_state.IDLE          ; spi2dac:SPI_DAC|dac_start              ; 0.402             ;
+; pwm:PWM_DC|d[9]                        ; pwm:PWM_DC|pwm_out                     ; 0.378             ;
+; spi2adc:SPI_ADC|sr_state.WAIT_CSB_HIGH ; spi2adc:SPI_ADC|sr_state.IDLE          ; 0.377             ;
+; spi2adc:SPI_ADC|sr_state.IDLE          ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; 0.376             ;
+; clktick_16:GEN_10K|count[15]           ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[13]           ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[12]           ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[11]           ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[9]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[8]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[7]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[6]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[5]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[4]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[3]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[2]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[1]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[0]            ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[14]           ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; clktick_16:GEN_10K|count[10]           ; clktick_16:GEN_10K|tick                ; 0.362             ;
+; spi2dac:SPI_DAC|sr_state.WAIT_CSB_HIGH ; spi2dac:SPI_DAC|sr_state.IDLE          ; 0.362             ;
+; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL ; spi2adc:SPI_ADC|adc_start              ; 0.333             ;
+; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL ; spi2dac:SPI_DAC|dac_start              ; 0.324             ;
+; pwm:PWM_DC|d[4]                        ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|d[3]                        ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|d[2]                        ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|d[7]                        ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|d[6]                        ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|d[5]                        ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[7]                    ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[6]                    ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[5]                    ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[4]                    ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[3]                    ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[2]                    ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[1]                    ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[0]                    ; pwm:PWM_DC|pwm_out                     ; 0.318             ;
+; pwm:PWM_DC|count[8]                    ; pwm:PWM_DC|pwm_out                     ; 0.275             ;
++----------------------------------------+----------------------------------------+-------------------+
+Note: This table only shows the top 45 path(s) that have the largest delay added for hold.
 
 
 +-----------------+
@@ -2050,80 +1930,103 @@ Note: This table only shows the top 86 path(s) that have the largest delay added
 +-----------------+
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "ex9"
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex16_top"
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
 Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
 Info (184020): Starting Fitter periphery placement operations
 Info (11191): Automatically promoted 1 clock (1 global)
-    Info (11162): CLOCK_50~inputCLKENA0 with 16 fanout uses global clock CLKCTRL_G6
+    Info (11162): CLOCK_50~inputCLKENA0 with 57 fanout uses global clock CLKCTRL_G6
 Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
 Info (176233): Starting register packing
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
+Info (332104): Reading SDC File: 'ex16_top.sdc'
+Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2adc:SPI_ADC|data_from_adc[0] is being clocked by spi2adc:SPI_ADC|clk_1MHz
+Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz
 Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 1 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
 Info (176235): Finished register packing
     Extra Info (176219): No registers were packed into other blocks
 Warning (15705): Ignored locations or region assignments to the following nodes
-    Warning (15706): Node "ADC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDI" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "ADC_SDO" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_CS" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_LD" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SCK" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "DAC_SDI" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
     Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "PWM_OUT" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[4]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[5]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[6]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[7]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[8]" is assigned to location or region, but does not exist in design
-    Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:10
 Info (170189): Fitter placement preparation operations beginning
 Info (14951): The Fitter is using Advanced Physical Optimization.
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
 Info (170191): Fitter placement operations beginning
 Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
 Info (170193): Fitter routing operations beginning
 Info (170195): Router estimated average interconnect usage is 0% of the available device resources
-    Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X78_Y0 to location X89_Y10
 Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
     Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
-Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (11888): Total time spent on timing analysis during the Fitter is 0.26 seconds.
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file C:/New folder/ex9/output_files/ex9.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 30 warnings
-    Info: Peak virtual memory: 2592 megabytes
-    Info: Processing ended: Fri Nov 25 12:11:01 2016
-    Info: Elapsed time: 00:00:34
-    Info: Total CPU time (on all processors): 00:01:01
+Info (144001): Generated suppressed messages file C:/New folder/ex16/ex16_top.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 46 warnings
+    Info: Peak virtual memory: 2590 megabytes
+    Info: Processing ended: Fri Dec 02 09:33:26 2016
+    Info: Elapsed time: 00:00:30
+    Info: Total CPU time (on all processors): 00:00:52
 
 
 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in C:/New folder/ex9/output_files/ex9.fit.smsg.
+The suppressed messages can be found in C:/New folder/ex16/ex16_top.fit.smsg.
 
 
diff --git a/part_4/ex16/ex16_top.fit.smsg b/part_4/ex16/ex16_top.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_4/ex16/ex16_top.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex9_final/output_files/ex9.fit.summary b/part_4/ex16/ex16_top.fit.summary
index 34358c6..b7dc627 100755
--- a/part_2/ex9_final/output_files/ex9.fit.summary
+++ b/part_4/ex16/ex16_top.fit.summary
@@ -1,13 +1,13 @@
-Fitter Status : Successful - Fri Nov 25 12:11:01 2016
+Fitter Status : Successful - Fri Dec 02 09:33:26 2016
 Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
+Revision Name : ex16_top
+Top-level Entity Name : ex16_top
 Family : Cyclone V
 Device : 5CSEMA5F31C6
 Timing Models : Final
-Logic utilization (in ALMs) : 159 / 32,070 ( < 1 % )
-Total registers : 95
-Total pins : 57 / 457 ( 12 % )
+Logic utilization (in ALMs) : 61 / 32,070 ( < 1 % )
+Total registers : 114
+Total pins : 41 / 457 ( 9 % )
 Total virtual pins : 0
 Total block memory bits : 0 / 4,065,280 ( 0 % )
 Total RAM Blocks : 0 / 397 ( 0 % )
diff --git a/part_2/ex9_partially_working/output_files/ex9.flow.rpt b/part_4/ex16/ex16_top.flow.rpt
index 834877e..7bc15b8 100755
--- a/part_2/ex9_partially_working/output_files/ex9.flow.rpt
+++ b/part_4/ex16/ex16_top.flow.rpt
@@ -1,5 +1,5 @@
-Flow report for ex9
-Fri Nov 25 11:28:08 2016
+Flow report for ex16_top
+Fri Dec 02 09:33:42 2016
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 
 
@@ -41,16 +41,16 @@ agreement for further details.
 +-----------------------------------------------------------------------------------+
 ; Flow Summary                                                                      ;
 +---------------------------------+-------------------------------------------------+
-; Flow Status                     ; Successful - Fri Nov 25 11:28:01 2016           ;
+; Flow Status                     ; Successful - Fri Dec 02 09:33:42 2016           ;
 ; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
+; Revision Name                   ; ex16_top                                        ;
+; Top-level Entity Name           ; ex16_top                                        ;
 ; Family                          ; Cyclone V                                       ;
 ; Device                          ; 5CSEMA5F31C6                                    ;
 ; Timing Models                   ; Final                                           ;
-; Logic utilization (in ALMs)     ; 154 / 32,070 ( < 1 % )                          ;
-; Total registers                 ; 95                                              ;
-; Total pins                      ; 57 / 457 ( 12 % )                               ;
+; Logic utilization (in ALMs)     ; 61 / 32,070 ( < 1 % )                           ;
+; Total registers                 ; 114                                             ;
+; Total pins                      ; 41 / 457 ( 9 % )                                ;
 ; Total virtual pins              ; 0                                               ;
 ; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
 ; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
@@ -68,9 +68,9 @@ agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 11/25/2016 11:27:08 ;
+; Start date & time ; 12/02/2016 09:32:47 ;
 ; Main task         ; Compilation         ;
-; Revision Name     ; ex9                 ;
+; Revision Name     ; ex16_top            ;
 +-------------------+---------------------+
 
 
@@ -79,7 +79,8 @@ agreement for further details.
 +-------------------------------------+---------------------------------------+---------------+-------------+------------+
 ; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
 +-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID               ; 260248564297095.148007322808280       ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID               ; 260248564297095.148067116607400       ; --            ; --          ; --         ;
+; EDA_SIMULATION_TOOL                 ; ModelSim-Altera (Verilog)             ; <None>        ; --          ; --         ;
 ; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
 ; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
 ; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
@@ -87,7 +88,6 @@ agreement for further details.
 ; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
 ; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
 ; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
-; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
 +-------------------------------------+---------------------------------------+---------------+-------------+------------+
 
 
@@ -96,11 +96,12 @@ agreement for further details.
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:11     ; 1.0                     ; 896 MB              ; 00:00:21                           ;
-; Fitter                    ; 00:00:35     ; 1.0                     ; 2617 MB             ; 00:01:03                           ;
+; Analysis & Synthesis      ; 00:00:09     ; 1.0                     ; 898 MB              ; 00:00:19                           ;
+; Fitter                    ; 00:00:30     ; 1.0                     ; 2590 MB             ; 00:00:52                           ;
 ; Assembler                 ; 00:00:06     ; 1.0                     ; 895 MB              ; 00:00:06                           ;
-; TimeQuest Timing Analyzer ; 00:00:06     ; 1.1                     ; 1211 MB             ; 00:00:06                           ;
-; Total                     ; 00:00:58     ; --                      ; --                  ; 00:01:36                           ;
+; TimeQuest Timing Analyzer ; 00:00:05     ; 1.1                     ; 1208 MB             ; 00:00:05                           ;
+; EDA Netlist Writer        ; 00:00:02     ; 1.0                     ; 811 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:52     ; --                      ; --                  ; 00:01:23                           ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
@@ -113,16 +114,18 @@ agreement for further details.
 ; Fitter                    ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;
 ; Assembler                 ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;
 ; TimeQuest Timing Analyzer ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;
+; EDA Netlist Writer        ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;
 +---------------------------+------------------+-----------+------------+----------------+
 
 
 ------------
 ; Flow Log ;
 ------------
-quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_sta ex9 -c ex9
+quartus_map --read_settings_files=on --write_settings_files=off ex16 -c ex16_top
+quartus_fit --read_settings_files=off --write_settings_files=off ex16 -c ex16_top
+quartus_asm --read_settings_files=off --write_settings_files=off ex16 -c ex16_top
+quartus_sta ex16 -c ex16_top
+quartus_eda --read_settings_files=off --write_settings_files=off ex16 -c ex16_top
 
 
 
diff --git a/part_4/ex16/ex16_top.jdi b/part_4/ex16/ex16_top.jdi
new file mode 100755
index 0000000..35b1b96
--- /dev/null
+++ b/part_4/ex16/ex16_top.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="37d3b5bd4bdec0cdc70b"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex16_top.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_4/ex16/ex16_top.map.rpt b/part_4/ex16/ex16_top.map.rpt
new file mode 100755
index 0000000..98de4e7
--- /dev/null
+++ b/part_4/ex16/ex16_top.map.rpt
@@ -0,0 +1,506 @@
+Analysis & Synthesis report for ex16_top
+Fri Dec 02 09:32:55 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. State Machine - |ex16_top|spi2adc:SPI_ADC|sr_state
+  9. State Machine - |ex16_top|spi2dac:SPI_DAC|sr_state
+ 10. Registers Removed During Synthesis
+ 11. Removed Registers Triggering Further Register Optimizations
+ 12. General Register Statistics
+ 13. Inverted Register Statistics
+ 14. Parameter Settings for User Entity Instance: clktick_16:GEN_10K
+ 15. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC
+ 16. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC
+ 17. Parameter Settings for User Entity Instance: processor:ALLPASS
+ 18. Port Connectivity Checks: "hex_to_7seg:SEG2"
+ 19. Port Connectivity Checks: "spi2adc:SPI_ADC"
+ 20. Port Connectivity Checks: "clktick_16:GEN_10K"
+ 21. Post-Synthesis Netlist Statistics for Top Partition
+ 22. Elapsed Time Per Partition
+ 23. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Fri Dec 02 09:32:55 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex16_top                                        ;
+; Top-level Entity Name           ; ex16_top                                        ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 107                                             ;
+; Total pins                      ; 41                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 0                                               ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex16_top           ; ex16_top           ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                   ;
++----------------------------------+-----------------+------------------------+----------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path     ; Library ;
++----------------------------------+-----------------+------------------------+----------------------------------+---------+
+; hex_to_7seg.v                    ; yes             ; User Verilog HDL File  ; C:/New folder/ex16/hex_to_7seg.v ;         ;
+; clktick_16.v                     ; yes             ; User Verilog HDL File  ; C:/New folder/ex16/clktick_16.v  ;         ;
+; spi2dac.v                        ; yes             ; User Verilog HDL File  ; C:/New folder/ex16/spi2dac.v     ;         ;
+; spi2adc.v                        ; yes             ; User Verilog HDL File  ; C:/New folder/ex16/spi2adc.v     ;         ;
+; pwm.v                            ; yes             ; User Verilog HDL File  ; C:/New folder/ex16/pwm.v         ;         ;
+; ex16_top.v                       ; yes             ; User Verilog HDL File  ; C:/New folder/ex16/ex16_top.v    ;         ;
+; mult4.v                          ; yes             ; User Verilog HDL File  ; C:/New folder/ex16/mult4.v       ;         ;
++----------------------------------+-----------------+------------------------+----------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimate of Logic utilization (ALMs needed) ; 62             ;
+;                                             ;                ;
+; Combinational ALUT usage for logic          ; 108            ;
+;     -- 7 input functions                    ; 0              ;
+;     -- 6 input functions                    ; 9              ;
+;     -- 5 input functions                    ; 15             ;
+;     -- 4 input functions                    ; 30             ;
+;     -- <=3 input functions                  ; 54             ;
+;                                             ;                ;
+; Dedicated logic registers                   ; 107            ;
+;                                             ;                ;
+; I/O pins                                    ; 41             ;
+;                                             ;                ;
+; Total DSP Blocks                            ; 0              ;
+;                                             ;                ;
+; Maximum fan-out node                        ; CLOCK_50~input ;
+; Maximum fan-out                             ; 59             ;
+; Total fan-out                               ; 680            ;
+; Average fan-out                             ; 2.29           ;
++---------------------------------------------+----------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                              ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------+-------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name          ; Entity Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------+-------------+--------------+
+; |ex16_top                  ; 108 (0)           ; 107 (0)      ; 0                 ; 0          ; 41   ; 0            ; |ex16_top                    ; ex16_top    ; work         ;
+;    |clktick_16:GEN_10K|    ; 20 (20)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex16_top|clktick_16:GEN_10K ; clktick_16  ; work         ;
+;    |hex_to_7seg:SEG0|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex16_top|hex_to_7seg:SEG0   ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG1|      ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex16_top|hex_to_7seg:SEG1   ; hex_to_7seg ; work         ;
+;    |hex_to_7seg:SEG2|      ; 3 (3)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex16_top|hex_to_7seg:SEG2   ; hex_to_7seg ; work         ;
+;    |processor:ALLPASS|     ; 9 (9)             ; 8 (8)        ; 0                 ; 0          ; 0    ; 0            ; |ex16_top|processor:ALLPASS  ; processor   ; work         ;
+;    |pwm:PWM_DC|            ; 15 (15)           ; 19 (19)      ; 0                 ; 0          ; 0    ; 0            ; |ex16_top|pwm:PWM_DC         ; pwm         ; work         ;
+;    |spi2adc:SPI_ADC|       ; 21 (21)           ; 39 (39)      ; 0                 ; 0          ; 0    ; 0            ; |ex16_top|spi2adc:SPI_ADC    ; spi2adc     ; work         ;
+;    |spi2dac:SPI_DAC|       ; 26 (26)           ; 24 (24)      ; 0                 ; 0          ; 0    ; 0            ; |ex16_top|spi2dac:SPI_DAC    ; spi2dac     ; work         ;
++----------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------+-------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex16_top|spi2adc:SPI_ADC|sr_state                                       ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex16_top|spi2dac:SPI_DAC|sr_state                                       ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
++---------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                              ;
++----------------------------------------+----------------------------------------+
+; Register name                          ; Reason for Removal                     ;
++----------------------------------------+----------------------------------------+
+; processor:ALLPASS|data_out[0,1]        ; Stuck at GND due to stuck port data_in ;
+; pwm:PWM_DC|d[0,1]                      ; Stuck at GND due to stuck port data_in ;
+; spi2dac:SPI_DAC|shift_reg[0..3]        ; Stuck at GND due to stuck port data_in ;
+; spi2dac:SPI_DAC|ctr[4]                 ; Merged with spi2adc:SPI_ADC|ctr[4]     ;
+; spi2dac:SPI_DAC|ctr[3]                 ; Merged with spi2adc:SPI_ADC|ctr[3]     ;
+; spi2dac:SPI_DAC|ctr[2]                 ; Merged with spi2adc:SPI_ADC|ctr[2]     ;
+; spi2dac:SPI_DAC|ctr[1]                 ; Merged with spi2adc:SPI_ADC|ctr[1]     ;
+; spi2dac:SPI_DAC|ctr[0]                 ; Merged with spi2adc:SPI_ADC|ctr[0]     ;
+; Total Number of Removed Registers = 13 ;                                        ;
++----------------------------------------+----------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                               ;
++-------------------------------+---------------------------+-----------------------------------------------+
+; Register name                 ; Reason for Removal        ; Registers Removed due to This Register        ;
++-------------------------------+---------------------------+-----------------------------------------------+
+; processor:ALLPASS|data_out[0] ; Stuck at GND              ; pwm:PWM_DC|d[0], spi2dac:SPI_DAC|shift_reg[2] ;
+;                               ; due to stuck port data_in ;                                               ;
+; processor:ALLPASS|data_out[1] ; Stuck at GND              ; pwm:PWM_DC|d[1], spi2dac:SPI_DAC|shift_reg[3] ;
+;                               ; due to stuck port data_in ;                                               ;
+; spi2dac:SPI_DAC|shift_reg[0]  ; Stuck at GND              ; spi2dac:SPI_DAC|shift_reg[1]                  ;
+;                               ; due to stuck port data_in ;                                               ;
++-------------------------------+---------------------------+-----------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 107   ;
+; Number of registers using Synchronous Clear  ; 9     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 30    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; spi2dac:SPI_DAC|dac_cs                 ; 18      ;
+; spi2adc:SPI_ADC|adc_cs                 ; 7       ;
+; Total number of inverted registers = 2 ;         ;
++----------------------------------------+---------+
+
+
++-----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ;
++----------------+-------+----------------------------------------+
+; Parameter Name ; Value ; Type                                   ;
++----------------+-------+----------------------------------------+
+; N_BIT          ; 16    ; Signed Integer                         ;
++----------------+-------+----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; BUF            ; 1     ; Unsigned Binary                     ;
+; GA_N           ; 1     ; Unsigned Binary                     ;
+; SHDN_N         ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; SGL            ; 1     ; Unsigned Binary                     ;
+; MSBF           ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:ALLPASS ;
++----------------+------------+----------------------------------+
+; Parameter Name ; Value      ; Type                             ;
++----------------+------------+----------------------------------+
+; ADC_OFFSET     ; 0110000001 ; Unsigned Binary                  ;
+; DAC_OFFSET     ; 1000000000 ; Unsigned Binary                  ;
++----------------+------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------+
+; Port Connectivity Checks: "hex_to_7seg:SEG2" ;
++----------+-------+----------+----------------+
+; Port     ; Type  ; Severity ; Details        ;
++----------+-------+----------+----------------+
+; in[3..2] ; Input ; Info     ; Stuck at GND   ;
++----------+-------+----------+----------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "spi2adc:SPI_ADC"                                                                          ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port       ; Type   ; Severity ; Details                                                                             ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+; channel    ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; data_valid ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------+
+; Port Connectivity Checks: "clktick_16:GEN_10K" ;
++-----------+-------+----------+-----------------+
+; Port      ; Type  ; Severity ; Details         ;
++-----------+-------+----------+-----------------+
+; enable    ; Input ; Info     ; Stuck at VCC    ;
+; N[9..7]   ; Input ; Info     ; Stuck at VCC    ;
+; N[2..0]   ; Input ; Info     ; Stuck at VCC    ;
+; N[15..13] ; Input ; Info     ; Stuck at GND    ;
+; N[11..10] ; Input ; Info     ; Stuck at GND    ;
+; N[6..3]   ; Input ; Info     ; Stuck at GND    ;
+; N[12]     ; Input ; Info     ; Stuck at VCC    ;
++-----------+-------+----------+-----------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 107                         ;
+;     ENA               ; 30                          ;
+;     SCLR              ; 9                           ;
+;     plain             ; 68                          ;
+; arriav_lcell_comb     ; 116                         ;
+;     arith             ; 33                          ;
+;         1 data inputs ; 32                          ;
+;         2 data inputs ; 1                           ;
+;     normal            ; 83                          ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 11                          ;
+;         2 data inputs ; 10                          ;
+;         3 data inputs ; 7                           ;
+;         4 data inputs ; 30                          ;
+;         5 data inputs ; 15                          ;
+;         6 data inputs ; 9                           ;
+; boundary_port         ; 41                          ;
+;                       ;                             ;
+; Max LUT depth         ; 3.00                        ;
+; Average LUT depth     ; 1.47                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 09:32:46 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex16 -c ex16_top
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex16/hex_to_7seg.v Line: 10
+Info (12021): Found 1 design units, including 1 entities, in source file clktick_16.v
+    Info (12023): Found entity 1: clktick_16 File: C:/New folder/ex16/clktick_16.v Line: 6
+Info (12021): Found 1 design units, including 1 entities, in source file spi2dac.v
+    Info (12023): Found entity 1: spi2dac File: C:/New folder/ex16/spi2dac.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file spi2adc.v
+    Info (12023): Found entity 1: spi2adc File: C:/New folder/ex16/spi2adc.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file pwm.v
+    Info (12023): Found entity 1: pwm File: C:/New folder/ex16/pwm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file delay_ram.v
+    Info (12023): Found entity 1: delay_ram File: C:/New folder/ex16/delay_ram.v Line: 39
+Info (12021): Found 1 design units, including 1 entities, in source file ex16_top.v
+    Info (12023): Found entity 1: ex16_top File: C:/New folder/ex16/ex16_top.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file mult4.v
+    Info (12023): Found entity 1: processor File: C:/New folder/ex16/mult4.v Line: 1
+Info (12127): Elaborating entity "ex16_top" for the top level hierarchy
+Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: C:/New folder/ex16/ex16_top.v Line: 32
+Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: C:/New folder/ex16/ex16_top.v Line: 34
+Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: C:/New folder/ex16/ex16_top.v Line: 35
+Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: C:/New folder/ex16/ex16_top.v Line: 46
+Info (12128): Elaborating entity "processor" for hierarchy "processor:ALLPASS" File: C:/New folder/ex16/ex16_top.v Line: 48
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex16/ex16_top.v Line: 50
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX2[1]" is stuck at GND File: C:/New folder/ex16/ex16_top.v Line: 15
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 10 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "SW[0]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[1]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[2]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[3]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[4]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[5]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[6]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[7]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[8]" File: C:/New folder/ex16/ex16_top.v Line: 14
+    Warning (15610): No output dependent on input pin "SW[9]" File: C:/New folder/ex16/ex16_top.v Line: 14
+Info (21057): Implemented 178 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 12 input pins
+    Info (21059): Implemented 29 output pins
+    Info (21061): Implemented 137 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings
+    Info: Peak virtual memory: 898 megabytes
+    Info: Processing ended: Fri Dec 02 09:32:55 2016
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:20
+
+
diff --git a/part_2/ex9_final/output_files/ex9.map.summary b/part_4/ex16/ex16_top.map.summary
index 87824a5..f67f7c9 100755
--- a/part_2/ex9_final/output_files/ex9.map.summary
+++ b/part_4/ex16/ex16_top.map.summary
@@ -1,11 +1,11 @@
-Analysis & Synthesis Status : Successful - Fri Nov 25 12:10:26 2016
+Analysis & Synthesis Status : Successful - Fri Dec 02 09:32:55 2016
 Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
+Revision Name : ex16_top
+Top-level Entity Name : ex16_top
 Family : Cyclone V
 Logic utilization (in ALMs) : N/A
-Total registers : 84
-Total pins : 57
+Total registers : 107
+Total pins : 41
 Total virtual pins : 0
 Total block memory bits : 0
 Total DSP Blocks : 0
diff --git a/part_4/ex16/ex16_top.pin b/part_4/ex16/ex16_top.pin
new file mode 100755
index 0000000..f7d1bc3
--- /dev/null
+++ b/part_4/ex16/ex16_top.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       3.3V
+ --                  Bank 3B:       3.3V
+ --                  Bank 4A:       3.3V
+ --                  Bank 5A:       3.3V
+ --                  Bank 5B:       3.3V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex16_top"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 3.3V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+SW[0]                        : AB12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 5A        :                
+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+SW[7]                        : AC9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3A                      : AC10      : power  :                   : 3.3V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 3.3V    : 3A        :                
+SW[1]                        : AC12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                
+GND                          : AC26      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                
+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+SW[8]                        : AD10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[4]                        : AD11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[5]                        : AD12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+DAC_CS                       : AD20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26      :        :                   :         : 5A        :                
+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+SW[6]                        : AE11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[9]                        : AE12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+SW[2]                        : AF9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[3]                        : AF10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+DAC_SCK                      : AF20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SCK                      : AF21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+DAC_SDI                      : AG18      : output : 3.3-V LVTTL       :         : 4A        : Y              
+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
+ADC_CS                       : AG20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SDI                      : AG21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+PWM_OUT                      : AJ20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SDO                      : AJ21      : input  : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
+DAC_LD                       : AK21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23       :        :                   :         : 5A        :                
+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
+GND                          : W18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5A        :                
+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24       :        :                   :         : 5A        :                
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_4/ex16/ex16_top.qsf b/part_4/ex16/ex16_top.qsf
new file mode 100755
index 0000000..77ffb57
--- /dev/null
+++ b/part_4/ex16/ex16_top.qsf
@@ -0,0 +1,291 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 23:23:49  January 21, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		sine_tone_gen_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex16_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:25:39  OCTOBER 24, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to CLOCK_50
+
+#============================================================
+# Add-on Card Interface Pins
+#============================================================
+#set_location_assignment PIN_AJ20 -to GPIO_0[21] to PWM_OUT
+#set_location_assignment PIN_AK21 -to GPIO_0[23] to DAC_LD
+#set_location_assignment PIN_AD20 -to GPIO_0[25] to DAC_CS
+#set_location_assignment PIN_AF20 -to GPIO_0[28] to DAC_SCK
+#set_location_assignment PIN_AF21 -to GPIO_0[29] to ADC_SCK
+#set_location_assignment PIN_AG21 -to GPIO_0[31] to ADC_SDI
+#set_location_assignment PIN_AG20 -to GPIO_0[33] to ADC_CS
+#set_location_assignment PIN_AG18 -to GPIO_0[34] to DAC_SDI
+#set_location_assignment PIN_AJ21 -to GPIO_0[35] to ADC_SDO
+#set_location_assignment PIN_Y17 -to GPIO_0[1] to OLED_CS
+#set_location_assignment PIN_Y18 -to GPIO_0[3] to OLED_RST
+#set_location_assignment PIN_AK18 -to GPIO_0[5] to OLED_DC
+#set_location_assignment PIN_AJ19 -to GPIO_0[7] to OLED_CLK
+#set_location_assignment PIN_AJ16 -to GPIO_0[9] to OLED_DATA
+
+set_location_assignment PIN_AJ20 -to PWM_OUT
+set_location_assignment PIN_AK21 -to DAC_LD
+set_location_assignment PIN_AD20 -to DAC_CS
+set_location_assignment PIN_AF20 -to DAC_SCK
+set_location_assignment PIN_AF21 -to ADC_SCK
+set_location_assignment PIN_AG21 -to ADC_SDI
+set_location_assignment PIN_AG20 -to ADC_CS
+set_location_assignment PIN_AG18 -to DAC_SDI
+set_location_assignment PIN_AJ21 -to ADC_SDO
+set_location_assignment PIN_Y17 -to OLED_CS
+set_location_assignment PIN_Y18 -to OLED_RST
+set_location_assignment PIN_AK18 -to OLED_DC
+set_location_assignment PIN_AJ19 -to OLED_CLK
+set_location_assignment PIN_AJ16 -to OLED_DATA
+
+
+
+#============================================================
+# HEX0
+#============================================================
+set_location_assignment PIN_AE26 -to HEX0[0]
+set_location_assignment PIN_AE27 -to HEX0[1]
+set_location_assignment PIN_AE28 -to HEX0[2]
+set_location_assignment PIN_AG27 -to HEX0[3]
+set_location_assignment PIN_AF28 -to HEX0[4]
+set_location_assignment PIN_AG28 -to HEX0[5]
+set_location_assignment PIN_AH28 -to HEX0[6]
+
+#============================================================
+# HEX1
+#============================================================
+set_location_assignment PIN_AJ29 -to HEX1[0]
+set_location_assignment PIN_AH29 -to HEX1[1]
+set_location_assignment PIN_AH30 -to HEX1[2]
+set_location_assignment PIN_AG30 -to HEX1[3]
+set_location_assignment PIN_AF29 -to HEX1[4]
+set_location_assignment PIN_AF30 -to HEX1[5]
+set_location_assignment PIN_AD27 -to HEX1[6]
+
+#============================================================
+# HEX2
+#============================================================
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_AE29 -to HEX2[1]
+set_location_assignment PIN_AD29 -to HEX2[2]
+set_location_assignment PIN_AC28 -to HEX2[3]
+set_location_assignment PIN_AD30 -to HEX2[4]
+set_location_assignment PIN_AC29 -to HEX2[5]
+set_location_assignment PIN_AC30 -to HEX2[6]
+
+#============================================================
+# HEX3
+#============================================================
+set_location_assignment PIN_AD26 -to HEX3[0]
+set_location_assignment PIN_AC27 -to HEX3[1]
+set_location_assignment PIN_AD25 -to HEX3[2]
+set_location_assignment PIN_AC25 -to HEX3[3]
+set_location_assignment PIN_AB28 -to HEX3[4]
+set_location_assignment PIN_AB25 -to HEX3[5]
+set_location_assignment PIN_AB22 -to HEX3[6]
+
+#============================================================
+# HEX4
+#============================================================
+set_location_assignment PIN_AA24 -to HEX4[0]
+set_location_assignment PIN_Y23 -to HEX4[1]
+set_location_assignment PIN_Y24 -to HEX4[2]
+set_location_assignment PIN_W22 -to HEX4[3]
+set_location_assignment PIN_W24 -to HEX4[4]
+set_location_assignment PIN_V23 -to HEX4[5]
+set_location_assignment PIN_W25 -to HEX4[6]
+
+#============================================================
+# HEX5
+#============================================================
+set_location_assignment PIN_V25 -to HEX5[0]
+set_location_assignment PIN_AA28 -to HEX5[1]
+set_location_assignment PIN_Y27 -to HEX5[2]
+set_location_assignment PIN_AB27 -to HEX5[3]
+set_location_assignment PIN_AB26 -to HEX5[4]
+set_location_assignment PIN_AA26 -to HEX5[5]
+set_location_assignment PIN_AA25 -to HEX5[6]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AA14 -to KEY[0]
+set_location_assignment PIN_AA15 -to KEY[1]
+set_location_assignment PIN_W15 -to KEY[2]
+set_location_assignment PIN_Y16 -to KEY[3]
+
+#============================================================
+# LEDR
+#============================================================
+set_location_assignment PIN_V16 -to LEDR[0]
+set_location_assignment PIN_W16 -to LEDR[1]
+set_location_assignment PIN_V17 -to LEDR[2]
+set_location_assignment PIN_V18 -to LEDR[3]
+set_location_assignment PIN_W17 -to LEDR[4]
+set_location_assignment PIN_W19 -to LEDR[5]
+set_location_assignment PIN_Y19 -to LEDR[6]
+set_location_assignment PIN_W20 -to LEDR[7]
+set_location_assignment PIN_W21 -to LEDR[8]
+set_location_assignment PIN_Y21 -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB12 -to SW[0]
+set_location_assignment PIN_AC12 -to SW[1]
+set_location_assignment PIN_AF9 -to SW[2]
+set_location_assignment PIN_AF10 -to SW[3]
+set_location_assignment PIN_AD11 -to SW[4]
+set_location_assignment PIN_AD12 -to SW[5]
+set_location_assignment PIN_AE11 -to SW[6]
+set_location_assignment PIN_AC9 -to SW[7]
+set_location_assignment PIN_AD10 -to SW[8]
+set_location_assignment PIN_AE12 -to SW[9]
+
+#============================================================
+# End of pin and io_standard assignments
+#============================================================
+
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_RST
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DC
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OLED_DATA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PWM_OUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_LD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_global_assignment -name SDC_FILE ex16_top.sdc
+set_global_assignment -name VERILOG_FILE hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE clktick_16.v
+set_global_assignment -name VERILOG_FILE spi2dac.v
+set_global_assignment -name VERILOG_FILE spi2adc.v
+set_global_assignment -name VERILOG_FILE pwm.v
+set_global_assignment -name VERILOG_FILE delay_ram.v
+set_global_assignment -name VERILOG_FILE ex16_top.v
+set_global_assignment -name VERILOG_FILE mult4.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/part_4/ex16/ex16_top.qws b/part_4/ex16/ex16_top.qws
new file mode 100755
index 0000000..6e85ee2
--- /dev/null
+++ b/part_4/ex16/ex16_top.qws
diff --git a/part_4/ex16/ex16_top.sdc b/part_4/ex16/ex16_top.sdc
new file mode 100755
index 0000000..c8df2ac
--- /dev/null
+++ b/part_4/ex16/ex16_top.sdc
@@ -0,0 +1 @@
+create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
diff --git a/part_4/ex16/ex16_top.sld b/part_4/ex16/ex16_top.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_4/ex16/ex16_top.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/part_2/ex9_final/output_files/ex9.sof b/part_4/ex16/ex16_top.sof
index a73135f..af0ffed 100755
--- a/part_2/ex9_final/output_files/ex9.sof
+++ b/part_4/ex16/ex16_top.sof
diff --git a/part_4/ex16/ex16_top.sta.rpt b/part_4/ex16/ex16_top.sta.rpt
new file mode 100755
index 0000000..8402ef6
--- /dev/null
+++ b/part_4/ex16/ex16_top.sta.rpt
@@ -0,0 +1,811 @@
+TimeQuest Timing Analyzer report for ex16_top
+Fri Dec 02 09:33:39 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Slow 1100mV 85C Model Fmax Summary
+  7. Timing Closure Recommendations
+  8. Slow 1100mV 85C Model Setup Summary
+  9. Slow 1100mV 85C Model Hold Summary
+ 10. Slow 1100mV 85C Model Recovery Summary
+ 11. Slow 1100mV 85C Model Removal Summary
+ 12. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1100mV 85C Model Metastability Summary
+ 14. Slow 1100mV 0C Model Fmax Summary
+ 15. Slow 1100mV 0C Model Setup Summary
+ 16. Slow 1100mV 0C Model Hold Summary
+ 17. Slow 1100mV 0C Model Recovery Summary
+ 18. Slow 1100mV 0C Model Removal Summary
+ 19. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 20. Slow 1100mV 0C Model Metastability Summary
+ 21. Fast 1100mV 85C Model Setup Summary
+ 22. Fast 1100mV 85C Model Hold Summary
+ 23. Fast 1100mV 85C Model Recovery Summary
+ 24. Fast 1100mV 85C Model Removal Summary
+ 25. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 26. Fast 1100mV 85C Model Metastability Summary
+ 27. Fast 1100mV 0C Model Setup Summary
+ 28. Fast 1100mV 0C Model Hold Summary
+ 29. Fast 1100mV 0C Model Recovery Summary
+ 30. Fast 1100mV 0C Model Removal Summary
+ 31. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 32. Fast 1100mV 0C Model Metastability Summary
+ 33. Multicorner Timing Analysis Summary
+ 34. Board Trace Model Assignments
+ 35. Input Transition Times
+ 36. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 37. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 39. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 40. Setup Transfers
+ 41. Hold Transfers
+ 42. Report TCCS
+ 43. Report RSKM
+ 44. Unconstrained Paths Summary
+ 45. Clock Status Summary
+ 46. Unconstrained Input Ports
+ 47. Unconstrained Output Ports
+ 48. Unconstrained Input Ports
+ 49. Unconstrained Output Ports
+ 50. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex16_top                                                ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CSEMA5F31C6                                            ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.08        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   2.7%      ;
+;     Processor 3            ;   2.7%      ;
+;     Processor 4            ;   2.7%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; ex16_top.sdc  ; OK     ; Fri Dec 02 09:33:36 2016 ;
++---------------+--------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                               ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; Clock Name ; Type ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets      ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+; CLOCK_50   ; Base ; 20.000 ; 50.0 MHz  ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 } ;
++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
+
+
++--------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary               ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 299.94 MHz ; 299.94 MHz      ; CLOCK_50   ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1100mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock    ; Slack  ; End Point TNS   ;
++----------+--------+-----------------+
+; CLOCK_50 ; 16.666 ; 0.000           ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Slow 1100mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock    ; Slack ; End Point TNS   ;
++----------+-------+-----------------+
+; CLOCK_50 ; 0.384 ; 0.000           ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++----------+-------+--------------------------------+
+; Clock    ; Slack ; End Point TNS                  ;
++----------+-------+--------------------------------+
+; CLOCK_50 ; 8.792 ; 0.000                          ;
++----------+-------+--------------------------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                ;
++------------+-----------------+------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note ;
++------------+-----------------+------------+------+
+; 299.85 MHz ; 299.85 MHz      ; CLOCK_50   ;      ;
++------------+-----------------+------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1100mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock    ; Slack  ; End Point TNS  ;
++----------+--------+----------------+
+; CLOCK_50 ; 16.665 ; 0.000          ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Slow 1100mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock    ; Slack ; End Point TNS  ;
++----------+-------+----------------+
+; CLOCK_50 ; 0.383 ; 0.000          ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
++----------+-------+-------------------------------+
+; Clock    ; Slack ; End Point TNS                 ;
++----------+-------+-------------------------------+
+; CLOCK_50 ; 8.734 ; 0.000                         ;
++----------+-------+-------------------------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------+
+; Fast 1100mV 85C Model Setup Summary ;
++----------+--------+-----------------+
+; Clock    ; Slack  ; End Point TNS   ;
++----------+--------+-----------------+
+; CLOCK_50 ; 17.894 ; 0.000           ;
++----------+--------+-----------------+
+
+
++------------------------------------+
+; Fast 1100mV 85C Model Hold Summary ;
++----------+-------+-----------------+
+; Clock    ; Slack ; End Point TNS   ;
++----------+-------+-----------------+
+; CLOCK_50 ; 0.184 ; 0.000           ;
++----------+-------+-----------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++----------+-------+--------------------------------+
+; Clock    ; Slack ; End Point TNS                  ;
++----------+-------+--------------------------------+
+; CLOCK_50 ; 8.648 ; 0.000                          ;
++----------+-------+--------------------------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1100mV 0C Model Setup Summary ;
++----------+--------+----------------+
+; Clock    ; Slack  ; End Point TNS  ;
++----------+--------+----------------+
+; CLOCK_50 ; 17.997 ; 0.000          ;
++----------+--------+----------------+
+
+
++-----------------------------------+
+; Fast 1100mV 0C Model Hold Summary ;
++----------+-------+----------------+
+; Clock    ; Slack ; End Point TNS  ;
++----------+-------+----------------+
+; CLOCK_50 ; 0.176 ; 0.000          ;
++----------+-------+----------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
++----------+-------+-------------------------------+
+; Clock    ; Slack ; End Point TNS                 ;
++----------+-------+-------------------------------+
+; CLOCK_50 ; 8.612 ; 0.000                         ;
++----------+-------+-------------------------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                          ;
++------------------+--------+-------+----------+---------+---------------------+
+; Clock            ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+--------+-------+----------+---------+---------------------+
+; Worst-case Slack ; 16.665 ; 0.176 ; N/A      ; N/A     ; 8.612               ;
+;  CLOCK_50        ; 16.665 ; 0.176 ; N/A      ; N/A     ; 8.612               ;
+; Design-wide TNS  ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
+;  CLOCK_50        ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
++------------------+--------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; SW[0]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ADC_SDO  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------+
+; Setup Transfers                                                   ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50 ; 521      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------+
+; Hold Transfers                                                    ;
++------------+----------+----------+----------+----------+----------+
+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+----------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50 ; 521      ; 0        ; 0        ; 0        ;
++------------+----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 2     ; 2    ;
+; Unconstrained Input Ports       ; 1     ; 1    ;
+; Unconstrained Input Port Paths  ; 1     ; 1    ;
+; Unconstrained Output Ports      ; 28    ; 28   ;
+; Unconstrained Output Port Paths ; 76    ; 76   ;
++---------------------------------+-------+------+
+
+
++------------------------------------------------------------+
+; Clock Status Summary                                       ;
++--------------------------+----------+------+---------------+
+; Target                   ; Clock    ; Type ; Status        ;
++--------------------------+----------+------+---------------+
+; CLOCK_50                 ; CLOCK_50 ; Base ; Constrained   ;
+; spi2adc:SPI_ADC|clk_1MHz ;          ; Base ; Unconstrained ;
+; spi2dac:SPI_DAC|clk_1MHz ;          ; Base ; Unconstrained ;
++--------------------------+----------+------+---------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 09:33:34 2016
+Info: Command: quartus_sta ex16 -c ex16_top
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332104): Reading SDC File: 'ex16_top.sdc'
+Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2adc:SPI_ADC|data_from_adc[6] is being clocked by spi2adc:SPI_ADC|clk_1MHz
+Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Info (332146): Worst-case setup slack is 16.666
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    16.666               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.384
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.384               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.792
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     8.792               0.000 CLOCK_50 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2adc:SPI_ADC|data_from_adc[6] is being clocked by spi2adc:SPI_ADC|clk_1MHz
+Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 16.665
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    16.665               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.383
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.383               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.734
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     8.734               0.000 CLOCK_50 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2adc:SPI_ADC|data_from_adc[6] is being clocked by spi2adc:SPI_ADC|clk_1MHz
+Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 17.894
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    17.894               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.184
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.184               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.648
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     8.648               0.000 CLOCK_50 
+Info: Analyzing Fast 1100mV 0C Model
+Warning (332060): Node: spi2adc:SPI_ADC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2adc:SPI_ADC|data_from_adc[6] is being clocked by spi2adc:SPI_ADC|clk_1MHz
+Warning (332060): Node: spi2dac:SPI_DAC|clk_1MHz was determined to be a clock but was found without an associated clock assignment.
+    Info (13166): Register spi2dac:SPI_DAC|shift_reg[15] is being clocked by spi2dac:SPI_DAC|clk_1MHz
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 17.997
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    17.997               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.176
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.176               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is 8.612
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     8.612               0.000 CLOCK_50 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 9 warnings
+    Info: Peak virtual memory: 1208 megabytes
+    Info: Processing ended: Fri Dec 02 09:33:39 2016
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/part_4/ex16/ex16_top.sta.summary b/part_4/ex16/ex16_top.sta.summary
new file mode 100755
index 0000000..1d80614
--- /dev/null
+++ b/part_4/ex16/ex16_top.sta.summary
@@ -0,0 +1,53 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : 16.666
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.384
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.792
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : 16.665
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.383
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.734
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : 17.894
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.184
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.648
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : 17.997
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.176
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 8.612
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_4/ex16/ex16_top.v b/part_4/ex16/ex16_top.v
new file mode 100755
index 0000000..047114c
--- /dev/null
+++ b/part_4/ex16/ex16_top.v
@@ -0,0 +1,56 @@
+//------------------------------
+// Module name: ex16_top
+// Function: top level module - pass audio input to output directly
+// Creator:  Peter Cheung
+// Version:  2.0
+// Date:     10 Nov 2016
+//------------------------------
+
+module ex16_top (CLOCK_50, SW, HEX0, HEX1, HEX2, 
+					DAC_SDI, DAC_SCK, DAC_CS, DAC_LD,
+					ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT);
+
+	input			CLOCK_50;		// DE0 50MHz system clock
+	input [9:0]	SW;				// 10 slide switches to specify address to ROM
+	output [6:0] HEX0, HEX1, HEX2;
+	output 		DAC_SDI;			//Serial data out to SDI of the DAC
+	output 		DAC_SCK;				//Serial clock signal to both DAC and ADC
+	output		DAC_CS;			//Chip select to the DAC, low active
+	output 		DAC_LD;			//Load new data to DAC, low active	
+	output 		ADC_SDI;			//Serial data out to SDI of the ADC
+	output 		ADC_SCK;		// ADC Clock signal
+	output		ADC_CS;			//Chip select to the ADC, low active
+	input 		ADC_SDO;			//Converted serial data from ADC	
+	output		PWM_OUT;			// PWM output to R channel
+		
+	wire			tick_10k;		// internal clock at 10kHz
+	wire [9:0] 	data_in;		// converted data from ADC
+	wire [9:0] 	data_out;	// processed data to DAC
+	wire			data_valid;
+	wire			DAC_SCK, ADC_SCK;
+	
+	clktick_16  GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k);  	// generate 10KHz sampling clock ticks
+	spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, 		// send processed sample to DAC
+					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);		// order of signals matter
+	pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT);		// output via PWM - R-channel
+					
+	spi2adc SPI_ADC (												// perform a A-to-D conversion
+		.sysclk (CLOCK_50), 										// order of parameters do not matter
+		.channel (1'b1), 											// use only CH1
+		.start (tick_10k),
+		.data_from_adc (data_in),
+		.data_valid (data_valid),
+		.sdata_to_adc (ADC_SDI),
+		.adc_cs (ADC_CS),
+		.adc_sck (ADC_SCK),
+		.sdata_from_adc (ADC_SDO));		
+					
+	processor	ALLPASS (CLOCK_50, data_in, data_out);	// do some processing on the data
+	
+	hex_to_7seg		SEG0 (HEX0, data_in[3:0]);			
+	hex_to_7seg		SEG1 (HEX1, data_in[7:4]);			
+	hex_to_7seg		SEG2 (HEX2, {2'b0,data_in[9:8]});			
+		
+endmodule
+
+
diff --git a/part_4/ex16/greybox_tmp/cbx_args.txt b/part_4/ex16/greybox_tmp/cbx_args.txt
new file mode 100755
index 0000000..9064a76
--- /dev/null
+++ b/part_4/ex16/greybox_tmp/cbx_args.txt
@@ -0,0 +1,19 @@
+ADD_RAM_OUTPUT_REGISTER=OFF
+INTENDED_DEVICE_FAMILY="Cyclone V"
+LPM_NUMWORDS=256
+LPM_SHOWAHEAD=OFF
+LPM_TYPE=scfifo
+LPM_WIDTH=8
+LPM_WIDTHU=8
+OVERFLOW_CHECKING=ON
+UNDERFLOW_CHECKING=ON
+USE_EAB=ON
+DEVICE_FAMILY="Cyclone V"
+clock
+data
+rdreq
+wrreq
+empty
+full
+q
+usedw
diff --git a/part_4/ex16/hex_to_7seg.v b/part_4/ex16/hex_to_7seg.v
new file mode 100755
index 0000000..1c39f02
--- /dev/null
+++ b/part_4/ex16/hex_to_7seg.v
@@ -0,0 +1,38 @@
+//------------------------------
+// Module name: hex_to_7seg
+// Function: convert 4-bit hex value to drive 7 segment display
+//           output is low active - using case statement
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     23 Oct 2011
+//------------------------------
+
+module hex_to_7seg	(out,in);
+
+	output	[6:0]	out;    // low-active output to drive 7 segment display
+	input	[3:0]	in;		// 4-bit binary input of a hexademical number
+	
+	reg		[6:0]	out;	// make out a variable for use in procedural assignment
+	
+	always @ (in)
+	  case (in)
+		4'h0: out = 7'b1000000;
+		4'h1: out = 7'b1111001;		// -- 0 ---
+		4'h2: out = 7'b0100100; 	// |	  |
+		4'h3: out = 7'b0110000; 	// 5      1
+		4'h4: out = 7'b0011001; 	// |	  |
+		4'h5: out = 7'b0010010; 	// -- 6 ---
+		4'h6: out = 7'b0000010; 	// |	  |
+		4'h7: out = 7'b1111000; 	// 4      2
+		4'h8: out = 7'b0000000; 	// |	  |
+		4'h9: out = 7'b0011000; 	// -- 3 ---
+		4'ha: out = 7'b0001000;
+		4'hb: out = 7'b0000011;
+		4'hc: out = 7'b1000110;
+		4'hd: out = 7'b0100001;
+		4'he: out = 7'b0000110;
+		4'hf: out = 7'b0001110;
+	  endcase
+endmodule
+
+
diff --git a/part_4/ex16/incremental_db/README b/part_4/ex16/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_4/ex16/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.db_info b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.db_info
new file mode 100755
index 0000000..c4a8cf8
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Dec 02 09:19:56 2016
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.ammdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.ammdb
new file mode 100755
index 0000000..846e72f
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.ammdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.cdb
new file mode 100755
index 0000000..3e85d5b
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.dfp b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.dfp
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..9b2ed50
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.hdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..8b8f1e3
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.sig b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hdb
new file mode 100755
index 0000000..4b356b8
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.logdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.rcfdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..9c04900
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.cmp.rcfdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.cdb
new file mode 100755
index 0000000..f5bb010
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.dpi b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.dpi
new file mode 100755
index 0000000..d01f8b5
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.dpi
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..3a28304
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.hb_info b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.hb_info
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.hdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..e0e34ca
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.sig b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hdb
new file mode 100755
index 0000000..8eca3e6
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.kpt b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.kpt
new file mode 100755
index 0000000..fa419da
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.kpt
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.olf.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.olf.cdb
new file mode 100755
index 0000000..706bccb
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.olf.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.olm.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.olm.cdb
new file mode 100755
index 0000000..e92abf8
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.olm.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.oln.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.oln.cdb
new file mode 100755
index 0000000..9eb15d0
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.oln.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.opi b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.opi
@@ -0,0 +1 @@
+1
+\ No newline at end of file
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orf.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orf.cdb
new file mode 100755
index 0000000..c3fbc3e
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orf.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orm.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orm.cdb
new file mode 100755
index 0000000..82f4938
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orm.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orn.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orn.cdb
new file mode 100755
index 0000000..86c576d
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.map.orn.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.cdb
new file mode 100755
index 0000000..f5bb010
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hbdb.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..3a28304
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hbdb.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hbdb.hdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..e0e34ca
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hbdb.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hdb
new file mode 100755
index 0000000..8eca3e6
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.kpt b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.kpt
new file mode 100755
index 0000000..fa419da
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.root_partition.rrp.kpt
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.rrp.hdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.rrp.hdb
new file mode 100755
index 0000000..a0a0f09
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.rrp.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/ex16_top.rrs.cdb b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.rrs.cdb
new file mode 100755
index 0000000..f0ea311
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/ex16_top.rrs.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.db_info b/part_4/ex16/incremental_db/compiled_partitions/top.db_info
new file mode 100755
index 0000000..358b49d
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
+Version_Index = 402707200
+Creation_Time = Sun Oct 30 12:37:01 2016
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.ammdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.ammdb
new file mode 100755
index 0000000..16ffb30
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.ammdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.cdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.cdb
new file mode 100755
index 0000000..2b5bcc3
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.dfp b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.dfp
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.cdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..6722318
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.hdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..a4a9ecc
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.sig b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hdb
new file mode 100755
index 0000000..efc23b3
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.logdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.rcfdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..e3b4cd4
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.cmp.rcfdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.cdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.cdb
new file mode 100755
index 0000000..f5ed61e
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.dpi b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.dpi
new file mode 100755
index 0000000..69a847d
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.dpi
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.cdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..5a400c1
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.cdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hb_info b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hb_info
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..6be7d3c
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.sig b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hdb b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hdb
new file mode 100755
index 0000000..6b8518c
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.kpt b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.kpt
new file mode 100755
index 0000000..b33f811
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.root_partition.map.kpt
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.rrp.hdb b/part_4/ex16/incremental_db/compiled_partitions/top.rrp.hdb
new file mode 100755
index 0000000..5616f8e
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.rrp.hdb
diff --git a/part_4/ex16/incremental_db/compiled_partitions/top.rrs.cdb b/part_4/ex16/incremental_db/compiled_partitions/top.rrs.cdb
new file mode 100755
index 0000000..041bf9d
--- /dev/null
+++ b/part_4/ex16/incremental_db/compiled_partitions/top.rrs.cdb
diff --git a/part_4/ex16/mult4.v b/part_4/ex16/mult4.v
new file mode 100755
index 0000000..4ac7f4a
--- /dev/null
+++ b/part_4/ex16/mult4.v
@@ -0,0 +1,27 @@
+module processor (sysclk, data_in, data_out);
+
+	input				sysclk;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	// This part should include your own processing hardware 
+	// ... that takes x to produce y
+	// ... In this case, it is ALL PASS.
+	assign y = x << 2;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex16/multiply_k.v b/part_4/ex16/multiply_k.v
new file mode 100755
index 0000000..8292b58
--- /dev/null
+++ b/part_4/ex16/multiply_k.v
@@ -0,0 +1,107 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: multiply_k.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module multiply_k (
+	dataa,
+	result);
+
+	input	[8:0]  dataa;
+	output	[19:0]  result;
+
+	wire [19:0] sub_wire0;
+	wire [10:0] sub_wire1 = 11'h666;
+	wire [19:0] result = sub_wire0[19:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (sub_wire1),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 9,
+		lpm_mult_component.lpm_widthb = 11,
+		lpm_mult_component.lpm_widthp = 20;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "1638"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "9"
+// Retrieval info: PRIVATE: WidthB NUMERIC "11"
+// Retrieval info: PRIVATE: WidthP NUMERIC "20"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20"
+// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
+// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]"
+// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
+// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0
+// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_4/ex16/pulse_gen.v b/part_4/ex16/pulse_gen.v
new file mode 100755
index 0000000..d82fe49
--- /dev/null
+++ b/part_4/ex16/pulse_gen.v
@@ -0,0 +1,43 @@
+//------------------------------
+// Module name: pulse_gen (Moore)
+// Function: Generate one clock pulse on +ve edge of input
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     29 Jan 2014
+//------------------------------
+
+module pulse_gen(pulse, in, clk);
+
+	output 			pulse;	// output pulse lasting one clk cycle
+	input 			in;		// input, +ve edge to be detected
+	input 			clk;		// clock signal
+
+	reg [1:0]	state;
+	reg	pulse;
+	
+	parameter	IDLE = 2'b0;	// state coding for IDLE state
+	parameter	IN_HIGH = 2'b01;
+	parameter	WAIT_LOW = 2'b10;  
+	
+	initial state = IDLE;
+	
+	always @ (posedge clk) 
+		begin	
+			pulse <= 0;		 // default output
+			case (state)
+			IDLE: 	if (in == 1'b1) begin
+							state <= IN_HIGH;	pulse <= 1'b1; end
+						else 
+							state <= IDLE; 
+			IN_HIGH: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						else 
+							state <= IDLE; 
+			WAIT_LOW: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						 else  
+							state <= IDLE;
+			default: ;
+			endcase
+		end			//... always
+endmodule
diff --git a/part_4/ex16/pwm.v b/part_4/ex16/pwm.v
new file mode 100755
index 0000000..c3b34d9
--- /dev/null
+++ b/part_4/ex16/pwm.v
@@ -0,0 +1,25 @@
+module pwm (clk, data_in, load, pwm_out);
+
+	input				clk;			// system clock
+	input [9:0] 	data_in;		// input data for conversion
+	input 			load;			// high pulse to load new data
+	output			pwm_out;		// PWM output
+
+	reg [9:0]		d;				// internal register
+	reg [9:0]		count;		// internal 10-bit counter
+	reg				pwm_out;
+
+	always @ (posedge clk)
+		if (load == 1'b1) d <= data_in;
+	
+	initial count = 10'b0;	
+	
+	always @ (posedge clk) begin
+		count <= count + 1'b1;
+		if (count > d)
+			pwm_out <= 1'b0;
+		else	
+			pwm_out <= 1'b1;
+		end
+
+endmodule
diff --git a/part_4/ex16/simulation/modelsim/ex16_top.sft b/part_4/ex16/simulation/modelsim/ex16_top.sft
new file mode 100755
index 0000000..f324fea
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/ex16_top.sft
@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (Verilog)"
diff --git a/part_4/ex16/simulation/modelsim/ex16_top.vo b/part_4/ex16/simulation/modelsim/ex16_top.vo
new file mode 100755
index 0000000..2776cac
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/ex16_top.vo
@@ -0,0 +1,6010 @@
+// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, the Altera Quartus Prime License Agreement,
+// the Altera MegaCore Function License Agreement, or other 
+// applicable license agreement, including, without limitation, 
+// that your use is for the sole purpose of programming logic 
+// devices manufactured by Altera and sold by Altera or its 
+// authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition"
+
+// DATE "12/02/2016 09:33:42"
+
+// 
+// Device: Altera 5CSEMA5F31C6 Package FBGA896
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module ex16_top (
+	CLOCK_50,
+	SW,
+	HEX0,
+	HEX1,
+	HEX2,
+	DAC_SDI,
+	DAC_SCK,
+	DAC_CS,
+	DAC_LD,
+	ADC_SDI,
+	ADC_SCK,
+	ADC_CS,
+	ADC_SDO,
+	PWM_OUT);
+input 	CLOCK_50;
+input 	[9:0] SW;
+output 	[6:0] HEX0;
+output 	[6:0] HEX1;
+output 	[6:0] HEX2;
+output 	DAC_SDI;
+output 	DAC_SCK;
+output 	DAC_CS;
+output 	DAC_LD;
+output 	ADC_SDI;
+output 	ADC_SCK;
+output 	ADC_CS;
+input 	ADC_SDO;
+output 	PWM_OUT;
+
+// Design Ports Information
+// SW[0]	=>  Location: PIN_AB12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[1]	=>  Location: PIN_AC12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[2]	=>  Location: PIN_AF9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[3]	=>  Location: PIN_AF10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[4]	=>  Location: PIN_AD11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[5]	=>  Location: PIN_AD12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[6]	=>  Location: PIN_AE11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[7]	=>  Location: PIN_AC9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[8]	=>  Location: PIN_AD10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[9]	=>  Location: PIN_AE12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// HEX0[0]	=>  Location: PIN_AE26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[1]	=>  Location: PIN_AE27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[2]	=>  Location: PIN_AE28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[3]	=>  Location: PIN_AG27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[4]	=>  Location: PIN_AF28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[5]	=>  Location: PIN_AG28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[6]	=>  Location: PIN_AH28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[0]	=>  Location: PIN_AJ29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[1]	=>  Location: PIN_AH29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[2]	=>  Location: PIN_AH30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[3]	=>  Location: PIN_AG30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[4]	=>  Location: PIN_AF29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[5]	=>  Location: PIN_AF30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[6]	=>  Location: PIN_AD27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[0]	=>  Location: PIN_AB23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[1]	=>  Location: PIN_AE29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[2]	=>  Location: PIN_AD29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[3]	=>  Location: PIN_AC28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[4]	=>  Location: PIN_AD30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[5]	=>  Location: PIN_AC29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[6]	=>  Location: PIN_AC30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_SDI	=>  Location: PIN_AG18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_SCK	=>  Location: PIN_AF20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_CS	=>  Location: PIN_AD20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_LD	=>  Location: PIN_AK21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_SDI	=>  Location: PIN_AG21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_SCK	=>  Location: PIN_AF21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_CS	=>  Location: PIN_AG20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// PWM_OUT	=>  Location: PIN_AJ20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// CLOCK_50	=>  Location: PIN_AF14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ADC_SDO	=>  Location: PIN_AJ21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \SW[0]~input_o ;
+wire \SW[1]~input_o ;
+wire \SW[2]~input_o ;
+wire \SW[3]~input_o ;
+wire \SW[4]~input_o ;
+wire \SW[5]~input_o ;
+wire \SW[6]~input_o ;
+wire \SW[7]~input_o ;
+wire \SW[8]~input_o ;
+wire \SW[9]~input_o ;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \CLOCK_50~input_o ;
+wire \SPI_ADC|clk_1MHz~0_combout ;
+wire \SPI_ADC|clk_1MHz~feeder_combout ;
+wire \CLOCK_50~inputCLKENA0_outclk ;
+wire \SPI_ADC|ctr~2_combout ;
+wire \SPI_ADC|ctr~0_combout ;
+wire \SPI_ADC|ctr[2]~DUPLICATE_q ;
+wire \SPI_ADC|Add0~1_combout ;
+wire \SPI_ADC|Add0~0_combout ;
+wire \SPI_ADC|ctr~1_combout ;
+wire \SPI_ADC|ctr[4]~DUPLICATE_q ;
+wire \SPI_DAC|Equal0~0_combout ;
+wire \SPI_ADC|clk_1MHz~q ;
+wire \ADC_SDO~input_o ;
+wire \SPI_ADC|shift_reg[0]~feeder_combout ;
+wire \GEN_10K|Add0~9_sumout ;
+wire \GEN_10K|Add0~10 ;
+wire \GEN_10K|Add0~13_sumout ;
+wire \GEN_10K|Add0~14 ;
+wire \GEN_10K|Add0~17_sumout ;
+wire \GEN_10K|Add0~18 ;
+wire \GEN_10K|Add0~33_sumout ;
+wire \GEN_10K|Add0~34 ;
+wire \GEN_10K|Add0~37_sumout ;
+wire \GEN_10K|Add0~38 ;
+wire \GEN_10K|Add0~41_sumout ;
+wire \GEN_10K|Add0~42 ;
+wire \GEN_10K|Add0~45_sumout ;
+wire \GEN_10K|Add0~46 ;
+wire \GEN_10K|Add0~21_sumout ;
+wire \GEN_10K|Add0~22 ;
+wire \GEN_10K|Add0~25_sumout ;
+wire \GEN_10K|Add0~26 ;
+wire \GEN_10K|Add0~1_sumout ;
+wire \GEN_10K|Add0~2 ;
+wire \GEN_10K|Add0~5_sumout ;
+wire \GEN_10K|Equal0~0_combout ;
+wire \GEN_10K|Add0~6 ;
+wire \GEN_10K|Add0~49_sumout ;
+wire \GEN_10K|Add0~50 ;
+wire \GEN_10K|Add0~29_sumout ;
+wire \GEN_10K|Equal0~1_combout ;
+wire \GEN_10K|Add0~30 ;
+wire \GEN_10K|Add0~53_sumout ;
+wire \GEN_10K|Add0~54 ;
+wire \GEN_10K|Add0~61_sumout ;
+wire \GEN_10K|count[14]~DUPLICATE_q ;
+wire \GEN_10K|count[11]~DUPLICATE_q ;
+wire \GEN_10K|Add0~62 ;
+wire \GEN_10K|Add0~57_sumout ;
+wire \GEN_10K|Equal0~2_combout ;
+wire \GEN_10K|Equal0~3_combout ;
+wire \GEN_10K|tick~feeder_combout ;
+wire \GEN_10K|tick~q ;
+wire \SPI_ADC|Selector2~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_ADC|Selector0~0_combout ;
+wire \SPI_ADC|sr_state.IDLE~q ;
+wire \SPI_ADC|Selector1~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_ADC|adc_start~0_combout ;
+wire \SPI_ADC|adc_start~q ;
+wire \SPI_ADC|state[2]~2_combout ;
+wire \SPI_ADC|state[3]~3_combout ;
+wire \SPI_ADC|state~0_combout ;
+wire \SPI_ADC|Selector5~0_combout ;
+wire \SPI_ADC|state[1]~1_combout ;
+wire \SPI_ADC|Selector4~0_combout ;
+wire \SPI_ADC|adc_cs~q ;
+wire \SPI_ADC|WideOr0~0_combout ;
+wire \SPI_ADC|shift_ena~q ;
+wire \SPI_ADC|always3~0_combout ;
+wire \SPI_ADC|shift_reg[2]~feeder_combout ;
+wire \SPI_ADC|shift_reg[2]~DUPLICATE_q ;
+wire \SPI_ADC|Decoder0~0_combout ;
+wire \SPI_ADC|adc_done~q ;
+wire \SPI_ADC|shift_reg[1]~DUPLICATE_q ;
+wire \SEG0|WideOr6~0_combout ;
+wire \SEG0|WideOr5~0_combout ;
+wire \SEG0|WideOr4~0_combout ;
+wire \SEG0|WideOr3~0_combout ;
+wire \SEG0|WideOr2~0_combout ;
+wire \SEG0|WideOr1~0_combout ;
+wire \SEG0|WideOr0~0_combout ;
+wire \SPI_ADC|shift_reg[5]~feeder_combout ;
+wire \SPI_ADC|shift_reg[6]~feeder_combout ;
+wire \SPI_ADC|shift_reg[7]~feeder_combout ;
+wire \SEG1|WideOr6~0_combout ;
+wire \SEG1|WideOr5~0_combout ;
+wire \SEG1|WideOr4~0_combout ;
+wire \SEG1|WideOr3~0_combout ;
+wire \SEG1|WideOr2~0_combout ;
+wire \SEG1|WideOr1~0_combout ;
+wire \SEG1|WideOr0~0_combout ;
+wire \SPI_ADC|shift_reg[9]~feeder_combout ;
+wire \SPI_ADC|data_from_adc[8]~feeder_combout ;
+wire \SEG2|Decoder0~0_combout ;
+wire \SEG2|Decoder0~1_combout ;
+wire \SEG2|Decoder0~2_combout ;
+wire \SPI_DAC|clk_1MHz~0_combout ;
+wire \SPI_DAC|clk_1MHz~feeder_combout ;
+wire \SPI_DAC|clk_1MHz~q ;
+wire \SPI_DAC|sr_state.IDLE~q ;
+wire \SPI_DAC|Selector2~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_DAC|Selector0~0_combout ;
+wire \SPI_DAC|sr_state.IDLE~DUPLICATE_q ;
+wire \SPI_DAC|Selector1~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_DAC|dac_start~0_combout ;
+wire \SPI_DAC|dac_start~q ;
+wire \SPI_DAC|Selector5~0_combout ;
+wire \SPI_DAC|Selector4~0_combout ;
+wire \SPI_DAC|Selector8~0_combout ;
+wire \SPI_DAC|Selector7~0_combout ;
+wire \SPI_DAC|Selector6~0_combout ;
+wire \SPI_DAC|Selector9~0_combout ;
+wire \SPI_DAC|dac_cs~q ;
+wire \ALLPASS|Add0~18 ;
+wire \ALLPASS|Add0~14 ;
+wire \ALLPASS|Add0~10 ;
+wire \ALLPASS|Add0~30 ;
+wire \ALLPASS|Add0~26 ;
+wire \ALLPASS|Add0~21_sumout ;
+wire \ALLPASS|Add0~25_sumout ;
+wire \ALLPASS|Add0~13_sumout ;
+wire \ALLPASS|Add0~17_sumout ;
+wire \SPI_DAC|shift_reg~11_combout ;
+wire \SPI_DAC|shift_reg~10_combout ;
+wire \ALLPASS|Add0~9_sumout ;
+wire \SPI_DAC|shift_reg~9_combout ;
+wire \ALLPASS|Add0~29_sumout ;
+wire \SPI_DAC|shift_reg~8_combout ;
+wire \SPI_DAC|shift_reg~7_combout ;
+wire \SPI_DAC|shift_reg~6_combout ;
+wire \ALLPASS|Add0~22 ;
+wire \ALLPASS|Add0~5_sumout ;
+wire \SPI_DAC|shift_reg~5_combout ;
+wire \ALLPASS|Add0~6 ;
+wire \ALLPASS|Add0~1_sumout ;
+wire \ALLPASS|data_out[9]~0_combout ;
+wire \SPI_DAC|shift_reg~4_combout ;
+wire \SPI_DAC|shift_reg~3_combout ;
+wire \SPI_DAC|shift_reg~2_combout ;
+wire \SPI_DAC|shift_reg~1_combout ;
+wire \SPI_DAC|shift_reg~0_combout ;
+wire \SPI_DAC|dac_sck~combout ;
+wire \SPI_DAC|Equal2~0_combout ;
+wire \SPI_DAC|dac_ld~q ;
+wire \SPI_ADC|Selector6~0_combout ;
+wire \SPI_ADC|adc_din~q ;
+wire \SPI_ADC|adc_sck~combout ;
+wire \PWM_DC|count[0]~0_combout ;
+wire \PWM_DC|Add0~21_sumout ;
+wire \PWM_DC|Add0~22 ;
+wire \PWM_DC|Add0~17_sumout ;
+wire \PWM_DC|Add0~18 ;
+wire \PWM_DC|Add0~13_sumout ;
+wire \PWM_DC|Add0~14 ;
+wire \PWM_DC|Add0~9_sumout ;
+wire \PWM_DC|Add0~10 ;
+wire \PWM_DC|Add0~33_sumout ;
+wire \PWM_DC|Add0~34 ;
+wire \PWM_DC|Add0~29_sumout ;
+wire \PWM_DC|Add0~30 ;
+wire \PWM_DC|Add0~25_sumout ;
+wire \PWM_DC|Add0~26 ;
+wire \PWM_DC|Add0~5_sumout ;
+wire \PWM_DC|Add0~6 ;
+wire \PWM_DC|Add0~1_sumout ;
+wire \PWM_DC|LessThan0~0_combout ;
+wire \PWM_DC|LessThan0~1_combout ;
+wire \PWM_DC|LessThan0~2_combout ;
+wire \PWM_DC|LessThan0~3_combout ;
+wire \PWM_DC|LessThan0~4_combout ;
+wire \PWM_DC|pwm_out~q ;
+wire [15:0] \GEN_10K|count ;
+wire [9:0] \SPI_ADC|data_from_adc ;
+wire [15:0] \SPI_DAC|shift_reg ;
+wire [9:0] \SPI_ADC|shift_reg ;
+wire [9:0] \PWM_DC|d ;
+wire [4:0] \SPI_ADC|ctr ;
+wire [9:0] \PWM_DC|count ;
+wire [4:0] \SPI_DAC|state ;
+wire [4:0] \SPI_ADC|state ;
+wire [9:0] \ALLPASS|data_out ;
+
+
+// Location: IOOBUF_X89_Y8_N39
+cyclonev_io_obuf \HEX0[0]~output (
+	.i(\SEG0|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[0]~output .bus_hold = "false";
+defparam \HEX0[0]~output .open_drain_output = "false";
+defparam \HEX0[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N79
+cyclonev_io_obuf \HEX0[1]~output (
+	.i(\SEG0|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[1]~output .bus_hold = "false";
+defparam \HEX0[1]~output .open_drain_output = "false";
+defparam \HEX0[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N96
+cyclonev_io_obuf \HEX0[2]~output (
+	.i(\SEG0|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[2]~output .bus_hold = "false";
+defparam \HEX0[2]~output .open_drain_output = "false";
+defparam \HEX0[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N79
+cyclonev_io_obuf \HEX0[3]~output (
+	.i(\SEG0|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[3]~output .bus_hold = "false";
+defparam \HEX0[3]~output .open_drain_output = "false";
+defparam \HEX0[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N56
+cyclonev_io_obuf \HEX0[4]~output (
+	.i(\SEG0|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[4]~output .bus_hold = "false";
+defparam \HEX0[4]~output .open_drain_output = "false";
+defparam \HEX0[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N39
+cyclonev_io_obuf \HEX0[5]~output (
+	.i(\SEG0|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[5]~output .bus_hold = "false";
+defparam \HEX0[5]~output .open_drain_output = "false";
+defparam \HEX0[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N96
+cyclonev_io_obuf \HEX0[6]~output (
+	.i(!\SEG0|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[6]~output .bus_hold = "false";
+defparam \HEX0[6]~output .open_drain_output = "false";
+defparam \HEX0[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y6_N39
+cyclonev_io_obuf \HEX1[0]~output (
+	.i(\SEG1|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[0]~output .bus_hold = "false";
+defparam \HEX1[0]~output .open_drain_output = "false";
+defparam \HEX1[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y6_N56
+cyclonev_io_obuf \HEX1[1]~output (
+	.i(\SEG1|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[1]~output .bus_hold = "false";
+defparam \HEX1[1]~output .open_drain_output = "false";
+defparam \HEX1[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N39
+cyclonev_io_obuf \HEX1[2]~output (
+	.i(\SEG1|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[2]~output .bus_hold = "false";
+defparam \HEX1[2]~output .open_drain_output = "false";
+defparam \HEX1[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N56
+cyclonev_io_obuf \HEX1[3]~output (
+	.i(\SEG1|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[3]~output .bus_hold = "false";
+defparam \HEX1[3]~output .open_drain_output = "false";
+defparam \HEX1[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N39
+cyclonev_io_obuf \HEX1[4]~output (
+	.i(\SEG1|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[4]~output .bus_hold = "false";
+defparam \HEX1[4]~output .open_drain_output = "false";
+defparam \HEX1[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N56
+cyclonev_io_obuf \HEX1[5]~output (
+	.i(\SEG1|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[5]~output .bus_hold = "false";
+defparam \HEX1[5]~output .open_drain_output = "false";
+defparam \HEX1[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N56
+cyclonev_io_obuf \HEX1[6]~output (
+	.i(!\SEG1|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[6]~output .bus_hold = "false";
+defparam \HEX1[6]~output .open_drain_output = "false";
+defparam \HEX1[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N22
+cyclonev_io_obuf \HEX2[0]~output (
+	.i(\SEG2|Decoder0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[0]~output .bus_hold = "false";
+defparam \HEX2[0]~output .open_drain_output = "false";
+defparam \HEX2[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y23_N39
+cyclonev_io_obuf \HEX2[1]~output (
+	.i(gnd),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[1]~output .bus_hold = "false";
+defparam \HEX2[1]~output .open_drain_output = "false";
+defparam \HEX2[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y23_N56
+cyclonev_io_obuf \HEX2[2]~output (
+	.i(\SEG2|Decoder0~1_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[2]~output .bus_hold = "false";
+defparam \HEX2[2]~output .open_drain_output = "false";
+defparam \HEX2[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N79
+cyclonev_io_obuf \HEX2[3]~output (
+	.i(\SEG2|Decoder0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[3]~output .bus_hold = "false";
+defparam \HEX2[3]~output .open_drain_output = "false";
+defparam \HEX2[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y25_N39
+cyclonev_io_obuf \HEX2[4]~output (
+	.i(\SPI_ADC|data_from_adc [8]),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[4]~output .bus_hold = "false";
+defparam \HEX2[4]~output .open_drain_output = "false";
+defparam \HEX2[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N96
+cyclonev_io_obuf \HEX2[5]~output (
+	.i(\SEG2|Decoder0~2_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[5]~output .bus_hold = "false";
+defparam \HEX2[5]~output .open_drain_output = "false";
+defparam \HEX2[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y25_N56
+cyclonev_io_obuf \HEX2[6]~output (
+	.i(!\SPI_ADC|data_from_adc [9]),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[6]~output .bus_hold = "false";
+defparam \HEX2[6]~output .open_drain_output = "false";
+defparam \HEX2[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X58_Y0_N76
+cyclonev_io_obuf \DAC_SDI~output (
+	.i(\SPI_DAC|shift_reg [15]),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_SDI),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SDI~output .bus_hold = "false";
+defparam \DAC_SDI~output .open_drain_output = "false";
+defparam \DAC_SDI~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N2
+cyclonev_io_obuf \DAC_SCK~output (
+	.i(!\SPI_DAC|dac_sck~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_SCK),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SCK~output .bus_hold = "false";
+defparam \DAC_SCK~output .open_drain_output = "false";
+defparam \DAC_SCK~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X82_Y0_N42
+cyclonev_io_obuf \DAC_CS~output (
+	.i(!\SPI_DAC|dac_cs~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_CS),
+	.obar());
+// synopsys translate_off
+defparam \DAC_CS~output .bus_hold = "false";
+defparam \DAC_CS~output .open_drain_output = "false";
+defparam \DAC_CS~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X68_Y0_N36
+cyclonev_io_obuf \DAC_LD~output (
+	.i(\SPI_DAC|dac_ld~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_LD),
+	.obar());
+// synopsys translate_off
+defparam \DAC_LD~output .bus_hold = "false";
+defparam \DAC_LD~output .open_drain_output = "false";
+defparam \DAC_LD~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X54_Y0_N2
+cyclonev_io_obuf \ADC_SDI~output (
+	.i(\SPI_ADC|adc_din~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_SDI),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SDI~output .bus_hold = "false";
+defparam \ADC_SDI~output .open_drain_output = "false";
+defparam \ADC_SDI~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N19
+cyclonev_io_obuf \ADC_SCK~output (
+	.i(!\SPI_ADC|adc_sck~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_SCK),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SCK~output .bus_hold = "false";
+defparam \ADC_SCK~output .open_drain_output = "false";
+defparam \ADC_SCK~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N19
+cyclonev_io_obuf \ADC_CS~output (
+	.i(!\SPI_ADC|adc_cs~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_CS),
+	.obar());
+// synopsys translate_off
+defparam \ADC_CS~output .bus_hold = "false";
+defparam \ADC_CS~output .open_drain_output = "false";
+defparam \ADC_CS~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N36
+cyclonev_io_obuf \PWM_OUT~output (
+	.i(\PWM_DC|pwm_out~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(PWM_OUT),
+	.obar());
+// synopsys translate_off
+defparam \PWM_OUT~output .bus_hold = "false";
+defparam \PWM_OUT~output .open_drain_output = "false";
+defparam \PWM_OUT~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X32_Y0_N1
+cyclonev_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N18
+cyclonev_lcell_comb \SPI_ADC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_ADC|clk_1MHz~0_combout  = ( !\SPI_ADC|clk_1MHz~q  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|clk_1MHz~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|clk_1MHz~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~0 .extended_lut = "off";
+defparam \SPI_ADC|clk_1MHz~0 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \SPI_ADC|clk_1MHz~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N9
+cyclonev_lcell_comb \SPI_ADC|clk_1MHz~feeder (
+// Equation(s):
+// \SPI_ADC|clk_1MHz~feeder_combout  = ( \SPI_ADC|clk_1MHz~0_combout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|clk_1MHz~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|clk_1MHz~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~feeder .extended_lut = "off";
+defparam \SPI_ADC|clk_1MHz~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|clk_1MHz~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: CLKCTRL_G6
+cyclonev_clkena \CLOCK_50~inputCLKENA0 (
+	.inclk(\CLOCK_50~input_o ),
+	.ena(vcc),
+	.outclk(\CLOCK_50~inputCLKENA0_outclk ),
+	.enaout());
+// synopsys translate_off
+defparam \CLOCK_50~inputCLKENA0 .clock_type = "global clock";
+defparam \CLOCK_50~inputCLKENA0 .disable_mode = "low";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_mode = "always enabled";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_power_up = "high";
+defparam \CLOCK_50~inputCLKENA0 .test_syn = "high";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N43
+dffeas \SPI_ADC|ctr[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N24
+cyclonev_lcell_comb \SPI_ADC|ctr~2 (
+// Equation(s):
+// \SPI_ADC|ctr~2_combout  = ( \SPI_ADC|ctr [1] & ( \SPI_ADC|ctr [2] & ( \SPI_ADC|ctr [0] ) ) ) # ( !\SPI_ADC|ctr [1] & ( \SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr [0] ) ) ) # ( \SPI_ADC|ctr [1] & ( !\SPI_ADC|ctr [2] & ( \SPI_ADC|ctr [0] ) ) ) # ( !\SPI_ADC|ctr [1] 
+// & ( !\SPI_ADC|ctr [2] & ( (!\SPI_ADC|ctr [0] & ((\SPI_ADC|ctr [3]) # (\SPI_ADC|ctr [4]))) ) ) )
+
+	.dataa(!\SPI_ADC|ctr [4]),
+	.datab(!\SPI_ADC|ctr [3]),
+	.datac(!\SPI_ADC|ctr [0]),
+	.datad(gnd),
+	.datae(!\SPI_ADC|ctr [1]),
+	.dataf(!\SPI_ADC|ctr [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~2 .extended_lut = "off";
+defparam \SPI_ADC|ctr~2 .lut_mask = 64'h70700F0FF0F00F0F;
+defparam \SPI_ADC|ctr~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N25
+dffeas \SPI_ADC|ctr[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N42
+cyclonev_lcell_comb \SPI_ADC|ctr~0 (
+// Equation(s):
+// \SPI_ADC|ctr~0_combout  = ( \SPI_ADC|ctr [2] & ( \SPI_ADC|ctr [0] ) ) # ( \SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr [0] & ( \SPI_ADC|ctr [1] ) ) ) # ( !\SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr [0] & ( (!\SPI_ADC|ctr [1] & ((\SPI_ADC|ctr [3]) # (\SPI_ADC|ctr [4]))) ) ) 
+// )
+
+	.dataa(!\SPI_ADC|ctr [4]),
+	.datab(!\SPI_ADC|ctr [3]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|ctr [1]),
+	.datae(!\SPI_ADC|ctr [2]),
+	.dataf(!\SPI_ADC|ctr [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~0 .extended_lut = "off";
+defparam \SPI_ADC|ctr~0 .lut_mask = 64'h770000FF0000FFFF;
+defparam \SPI_ADC|ctr~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N44
+dffeas \SPI_ADC|ctr[2]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N39
+cyclonev_lcell_comb \SPI_ADC|Add0~1 (
+// Equation(s):
+// \SPI_ADC|Add0~1_combout  = ( \SPI_ADC|ctr [3] & ( \SPI_ADC|ctr [1] ) ) # ( \SPI_ADC|ctr [3] & ( !\SPI_ADC|ctr [1] & ( (\SPI_ADC|ctr[2]~DUPLICATE_q ) # (\SPI_ADC|ctr [0]) ) ) ) # ( !\SPI_ADC|ctr [3] & ( !\SPI_ADC|ctr [1] & ( (!\SPI_ADC|ctr [0] & 
+// !\SPI_ADC|ctr[2]~DUPLICATE_q ) ) ) )
+
+	.dataa(!\SPI_ADC|ctr [0]),
+	.datab(!\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SPI_ADC|ctr [3]),
+	.dataf(!\SPI_ADC|ctr [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Add0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~1 .extended_lut = "off";
+defparam \SPI_ADC|Add0~1 .lut_mask = 64'h888877770000FFFF;
+defparam \SPI_ADC|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N41
+dffeas \SPI_ADC|ctr[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N3
+cyclonev_lcell_comb \SPI_ADC|Add0~0 (
+// Equation(s):
+// \SPI_ADC|Add0~0_combout  = ( \SPI_ADC|ctr [4] & ( \SPI_ADC|ctr [2] ) ) # ( \SPI_ADC|ctr [4] & ( !\SPI_ADC|ctr [2] & ( ((\SPI_ADC|ctr [1]) # (\SPI_ADC|ctr [3])) # (\SPI_ADC|ctr [0]) ) ) ) # ( !\SPI_ADC|ctr [4] & ( !\SPI_ADC|ctr [2] & ( (!\SPI_ADC|ctr [0] & 
+// (!\SPI_ADC|ctr [3] & !\SPI_ADC|ctr [1])) ) ) )
+
+	.dataa(!\SPI_ADC|ctr [0]),
+	.datab(!\SPI_ADC|ctr [3]),
+	.datac(!\SPI_ADC|ctr [1]),
+	.datad(gnd),
+	.datae(!\SPI_ADC|ctr [4]),
+	.dataf(!\SPI_ADC|ctr [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Add0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~0 .extended_lut = "off";
+defparam \SPI_ADC|Add0~0 .lut_mask = 64'h80807F7F0000FFFF;
+defparam \SPI_ADC|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N5
+dffeas \SPI_ADC|ctr[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N51
+cyclonev_lcell_comb \SPI_ADC|ctr~1 (
+// Equation(s):
+// \SPI_ADC|ctr~1_combout  = ( !\SPI_ADC|ctr [0] & ( \SPI_ADC|ctr [2] ) ) # ( !\SPI_ADC|ctr [0] & ( !\SPI_ADC|ctr [2] & ( ((\SPI_ADC|ctr [1]) # (\SPI_ADC|ctr [3])) # (\SPI_ADC|ctr [4]) ) ) )
+
+	.dataa(!\SPI_ADC|ctr [4]),
+	.datab(!\SPI_ADC|ctr [3]),
+	.datac(!\SPI_ADC|ctr [1]),
+	.datad(gnd),
+	.datae(!\SPI_ADC|ctr [0]),
+	.dataf(!\SPI_ADC|ctr [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~1 .extended_lut = "off";
+defparam \SPI_ADC|ctr~1 .lut_mask = 64'h7F7F0000FFFF0000;
+defparam \SPI_ADC|ctr~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N53
+dffeas \SPI_ADC|ctr[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N4
+dffeas \SPI_ADC|ctr[4]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[4]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[4]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[4]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N33
+cyclonev_lcell_comb \SPI_DAC|Equal0~0 (
+// Equation(s):
+// \SPI_DAC|Equal0~0_combout  = ( !\SPI_ADC|ctr[4]~DUPLICATE_q  & ( (!\SPI_ADC|ctr [0] & (!\SPI_ADC|ctr [2] & (!\SPI_ADC|ctr [3] & !\SPI_ADC|ctr [1]))) ) )
+
+	.dataa(!\SPI_ADC|ctr [0]),
+	.datab(!\SPI_ADC|ctr [2]),
+	.datac(!\SPI_ADC|ctr [3]),
+	.datad(!\SPI_ADC|ctr [1]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|ctr[4]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Equal0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal0~0 .extended_lut = "off";
+defparam \SPI_DAC|Equal0~0 .lut_mask = 64'h8000800000000000;
+defparam \SPI_DAC|Equal0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N11
+dffeas \SPI_ADC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\SPI_ADC|clk_1MHz~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_DAC|Equal0~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_ADC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y0_N52
+cyclonev_io_ibuf \ADC_SDO~input (
+	.i(ADC_SDO),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\ADC_SDO~input_o ));
+// synopsys translate_off
+defparam \ADC_SDO~input .bus_hold = "false";
+defparam \ADC_SDO~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N45
+cyclonev_lcell_comb \SPI_ADC|shift_reg[0]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[0]~feeder_combout  = ( \ADC_SDO~input_o  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ADC_SDO~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[0]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[0]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[0]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N0
+cyclonev_lcell_comb \GEN_10K|Add0~9 (
+// Equation(s):
+// \GEN_10K|Add0~9_sumout  = SUM(( \GEN_10K|count [0] ) + ( VCC ) + ( !VCC ))
+// \GEN_10K|Add0~10  = CARRY(( \GEN_10K|count [0] ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|count [0]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~9_sumout ),
+	.cout(\GEN_10K|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~9 .extended_lut = "off";
+defparam \GEN_10K|Add0~9 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N2
+dffeas \GEN_10K|count[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[0] .is_wysiwyg = "true";
+defparam \GEN_10K|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N3
+cyclonev_lcell_comb \GEN_10K|Add0~13 (
+// Equation(s):
+// \GEN_10K|Add0~13_sumout  = SUM(( \GEN_10K|count [1] ) + ( VCC ) + ( \GEN_10K|Add0~10  ))
+// \GEN_10K|Add0~14  = CARRY(( \GEN_10K|count [1] ) + ( VCC ) + ( \GEN_10K|Add0~10  ))
+
+	.dataa(!\GEN_10K|count [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~13_sumout ),
+	.cout(\GEN_10K|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~13 .extended_lut = "off";
+defparam \GEN_10K|Add0~13 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N5
+dffeas \GEN_10K|count[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[1] .is_wysiwyg = "true";
+defparam \GEN_10K|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N6
+cyclonev_lcell_comb \GEN_10K|Add0~17 (
+// Equation(s):
+// \GEN_10K|Add0~17_sumout  = SUM(( \GEN_10K|count [2] ) + ( VCC ) + ( \GEN_10K|Add0~14  ))
+// \GEN_10K|Add0~18  = CARRY(( \GEN_10K|count [2] ) + ( VCC ) + ( \GEN_10K|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|count [2]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~17_sumout ),
+	.cout(\GEN_10K|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~17 .extended_lut = "off";
+defparam \GEN_10K|Add0~17 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N8
+dffeas \GEN_10K|count[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[2] .is_wysiwyg = "true";
+defparam \GEN_10K|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N9
+cyclonev_lcell_comb \GEN_10K|Add0~33 (
+// Equation(s):
+// \GEN_10K|Add0~33_sumout  = SUM(( \GEN_10K|count [3] ) + ( VCC ) + ( \GEN_10K|Add0~18  ))
+// \GEN_10K|Add0~34  = CARRY(( \GEN_10K|count [3] ) + ( VCC ) + ( \GEN_10K|Add0~18  ))
+
+	.dataa(!\GEN_10K|count [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~33_sumout ),
+	.cout(\GEN_10K|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~33 .extended_lut = "off";
+defparam \GEN_10K|Add0~33 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N10
+dffeas \GEN_10K|count[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[3] .is_wysiwyg = "true";
+defparam \GEN_10K|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N12
+cyclonev_lcell_comb \GEN_10K|Add0~37 (
+// Equation(s):
+// \GEN_10K|Add0~37_sumout  = SUM(( \GEN_10K|count [4] ) + ( VCC ) + ( \GEN_10K|Add0~34  ))
+// \GEN_10K|Add0~38  = CARRY(( \GEN_10K|count [4] ) + ( VCC ) + ( \GEN_10K|Add0~34  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|count [4]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~37_sumout ),
+	.cout(\GEN_10K|Add0~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~37 .extended_lut = "off";
+defparam \GEN_10K|Add0~37 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N14
+dffeas \GEN_10K|count[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~37_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[4] .is_wysiwyg = "true";
+defparam \GEN_10K|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N15
+cyclonev_lcell_comb \GEN_10K|Add0~41 (
+// Equation(s):
+// \GEN_10K|Add0~41_sumout  = SUM(( \GEN_10K|count [5] ) + ( VCC ) + ( \GEN_10K|Add0~38  ))
+// \GEN_10K|Add0~42  = CARRY(( \GEN_10K|count [5] ) + ( VCC ) + ( \GEN_10K|Add0~38  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|count [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~41_sumout ),
+	.cout(\GEN_10K|Add0~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~41 .extended_lut = "off";
+defparam \GEN_10K|Add0~41 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N16
+dffeas \GEN_10K|count[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~41_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[5] .is_wysiwyg = "true";
+defparam \GEN_10K|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N18
+cyclonev_lcell_comb \GEN_10K|Add0~45 (
+// Equation(s):
+// \GEN_10K|Add0~45_sumout  = SUM(( \GEN_10K|count [6] ) + ( VCC ) + ( \GEN_10K|Add0~42  ))
+// \GEN_10K|Add0~46  = CARRY(( \GEN_10K|count [6] ) + ( VCC ) + ( \GEN_10K|Add0~42  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|count [6]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~45_sumout ),
+	.cout(\GEN_10K|Add0~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~45 .extended_lut = "off";
+defparam \GEN_10K|Add0~45 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N20
+dffeas \GEN_10K|count[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~45_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[6] .is_wysiwyg = "true";
+defparam \GEN_10K|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N21
+cyclonev_lcell_comb \GEN_10K|Add0~21 (
+// Equation(s):
+// \GEN_10K|Add0~21_sumout  = SUM(( \GEN_10K|count [7] ) + ( VCC ) + ( \GEN_10K|Add0~46  ))
+// \GEN_10K|Add0~22  = CARRY(( \GEN_10K|count [7] ) + ( VCC ) + ( \GEN_10K|Add0~46  ))
+
+	.dataa(!\GEN_10K|count [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~21_sumout ),
+	.cout(\GEN_10K|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~21 .extended_lut = "off";
+defparam \GEN_10K|Add0~21 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N23
+dffeas \GEN_10K|count[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[7] .is_wysiwyg = "true";
+defparam \GEN_10K|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N24
+cyclonev_lcell_comb \GEN_10K|Add0~25 (
+// Equation(s):
+// \GEN_10K|Add0~25_sumout  = SUM(( \GEN_10K|count [8] ) + ( VCC ) + ( \GEN_10K|Add0~22  ))
+// \GEN_10K|Add0~26  = CARRY(( \GEN_10K|count [8] ) + ( VCC ) + ( \GEN_10K|Add0~22  ))
+
+	.dataa(!\GEN_10K|count [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~25_sumout ),
+	.cout(\GEN_10K|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~25 .extended_lut = "off";
+defparam \GEN_10K|Add0~25 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N26
+dffeas \GEN_10K|count[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[8] .is_wysiwyg = "true";
+defparam \GEN_10K|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N27
+cyclonev_lcell_comb \GEN_10K|Add0~1 (
+// Equation(s):
+// \GEN_10K|Add0~1_sumout  = SUM(( \GEN_10K|count [9] ) + ( VCC ) + ( \GEN_10K|Add0~26  ))
+// \GEN_10K|Add0~2  = CARRY(( \GEN_10K|count [9] ) + ( VCC ) + ( \GEN_10K|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|count [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~1_sumout ),
+	.cout(\GEN_10K|Add0~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~1 .extended_lut = "off";
+defparam \GEN_10K|Add0~1 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N28
+dffeas \GEN_10K|count[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~1_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[9] .is_wysiwyg = "true";
+defparam \GEN_10K|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N30
+cyclonev_lcell_comb \GEN_10K|Add0~5 (
+// Equation(s):
+// \GEN_10K|Add0~5_sumout  = SUM(( \GEN_10K|count [10] ) + ( VCC ) + ( \GEN_10K|Add0~2  ))
+// \GEN_10K|Add0~6  = CARRY(( \GEN_10K|count [10] ) + ( VCC ) + ( \GEN_10K|Add0~2  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|count [10]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~5_sumout ),
+	.cout(\GEN_10K|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~5 .extended_lut = "off";
+defparam \GEN_10K|Add0~5 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N31
+dffeas \GEN_10K|count[10] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[10] .is_wysiwyg = "true";
+defparam \GEN_10K|count[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N48
+cyclonev_lcell_comb \GEN_10K|Equal0~0 (
+// Equation(s):
+// \GEN_10K|Equal0~0_combout  = ( !\GEN_10K|count [0] & ( !\GEN_10K|count [8] & ( (!\GEN_10K|count [1] & (!\GEN_10K|count [2] & !\GEN_10K|count [7])) ) ) )
+
+	.dataa(!\GEN_10K|count [1]),
+	.datab(!\GEN_10K|count [2]),
+	.datac(!\GEN_10K|count [7]),
+	.datad(gnd),
+	.datae(!\GEN_10K|count [0]),
+	.dataf(!\GEN_10K|count [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~0 .extended_lut = "off";
+defparam \GEN_10K|Equal0~0 .lut_mask = 64'h8080000000000000;
+defparam \GEN_10K|Equal0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N33
+cyclonev_lcell_comb \GEN_10K|Add0~49 (
+// Equation(s):
+// \GEN_10K|Add0~49_sumout  = SUM(( \GEN_10K|count [11] ) + ( VCC ) + ( \GEN_10K|Add0~6  ))
+// \GEN_10K|Add0~50  = CARRY(( \GEN_10K|count [11] ) + ( VCC ) + ( \GEN_10K|Add0~6  ))
+
+	.dataa(!\GEN_10K|count [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~49_sumout ),
+	.cout(\GEN_10K|Add0~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~49 .extended_lut = "off";
+defparam \GEN_10K|Add0~49 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N35
+dffeas \GEN_10K|count[11] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~49_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[11] .is_wysiwyg = "true";
+defparam \GEN_10K|count[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N36
+cyclonev_lcell_comb \GEN_10K|Add0~29 (
+// Equation(s):
+// \GEN_10K|Add0~29_sumout  = SUM(( \GEN_10K|count [12] ) + ( VCC ) + ( \GEN_10K|Add0~50  ))
+// \GEN_10K|Add0~30  = CARRY(( \GEN_10K|count [12] ) + ( VCC ) + ( \GEN_10K|Add0~50  ))
+
+	.dataa(!\GEN_10K|count [12]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~29_sumout ),
+	.cout(\GEN_10K|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~29 .extended_lut = "off";
+defparam \GEN_10K|Add0~29 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N38
+dffeas \GEN_10K|count[12] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~29_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[12] .is_wysiwyg = "true";
+defparam \GEN_10K|count[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N54
+cyclonev_lcell_comb \GEN_10K|Equal0~1 (
+// Equation(s):
+// \GEN_10K|Equal0~1_combout  = ( !\GEN_10K|count [12] & ( !\GEN_10K|count [4] & ( (!\GEN_10K|count [6] & (!\GEN_10K|count [5] & !\GEN_10K|count [3])) ) ) )
+
+	.dataa(!\GEN_10K|count [6]),
+	.datab(!\GEN_10K|count [5]),
+	.datac(!\GEN_10K|count [3]),
+	.datad(gnd),
+	.datae(!\GEN_10K|count [12]),
+	.dataf(!\GEN_10K|count [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~1 .extended_lut = "off";
+defparam \GEN_10K|Equal0~1 .lut_mask = 64'h8080000000000000;
+defparam \GEN_10K|Equal0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N44
+dffeas \GEN_10K|count[14] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~61_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[14] .is_wysiwyg = "true";
+defparam \GEN_10K|count[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N39
+cyclonev_lcell_comb \GEN_10K|Add0~53 (
+// Equation(s):
+// \GEN_10K|Add0~53_sumout  = SUM(( \GEN_10K|count [13] ) + ( VCC ) + ( \GEN_10K|Add0~30  ))
+// \GEN_10K|Add0~54  = CARRY(( \GEN_10K|count [13] ) + ( VCC ) + ( \GEN_10K|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|count [13]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~53_sumout ),
+	.cout(\GEN_10K|Add0~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~53 .extended_lut = "off";
+defparam \GEN_10K|Add0~53 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N40
+dffeas \GEN_10K|count[13] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~53_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[13] .is_wysiwyg = "true";
+defparam \GEN_10K|count[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N42
+cyclonev_lcell_comb \GEN_10K|Add0~61 (
+// Equation(s):
+// \GEN_10K|Add0~61_sumout  = SUM(( \GEN_10K|count [14] ) + ( VCC ) + ( \GEN_10K|Add0~54  ))
+// \GEN_10K|Add0~62  = CARRY(( \GEN_10K|count [14] ) + ( VCC ) + ( \GEN_10K|Add0~54  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|count [14]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~61_sumout ),
+	.cout(\GEN_10K|Add0~62 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~61 .extended_lut = "off";
+defparam \GEN_10K|Add0~61 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~61 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N43
+dffeas \GEN_10K|count[14]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~61_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count[14]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[14]~DUPLICATE .is_wysiwyg = "true";
+defparam \GEN_10K|count[14]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N34
+dffeas \GEN_10K|count[11]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~49_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count[11]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[11]~DUPLICATE .is_wysiwyg = "true";
+defparam \GEN_10K|count[11]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X77_Y8_N45
+cyclonev_lcell_comb \GEN_10K|Add0~57 (
+// Equation(s):
+// \GEN_10K|Add0~57_sumout  = SUM(( \GEN_10K|count [15] ) + ( VCC ) + ( \GEN_10K|Add0~62  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|count [15]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~62 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~57_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~57 .extended_lut = "off";
+defparam \GEN_10K|Add0~57 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X77_Y8_N46
+dffeas \GEN_10K|count[15] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~57_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~3_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|count [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|count[15] .is_wysiwyg = "true";
+defparam \GEN_10K|count[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y8_N6
+cyclonev_lcell_comb \GEN_10K|Equal0~2 (
+// Equation(s):
+// \GEN_10K|Equal0~2_combout  = ( !\GEN_10K|count[11]~DUPLICATE_q  & ( !\GEN_10K|count [15] & ( (!\GEN_10K|count[14]~DUPLICATE_q  & !\GEN_10K|count [13]) ) ) )
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|count[14]~DUPLICATE_q ),
+	.datac(!\GEN_10K|count [13]),
+	.datad(gnd),
+	.datae(!\GEN_10K|count[11]~DUPLICATE_q ),
+	.dataf(!\GEN_10K|count [15]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~2 .extended_lut = "off";
+defparam \GEN_10K|Equal0~2 .lut_mask = 64'hC0C0000000000000;
+defparam \GEN_10K|Equal0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y8_N15
+cyclonev_lcell_comb \GEN_10K|Equal0~3 (
+// Equation(s):
+// \GEN_10K|Equal0~3_combout  = ( !\GEN_10K|count [9] & ( \GEN_10K|Equal0~2_combout  & ( (!\GEN_10K|count [10] & (\GEN_10K|Equal0~0_combout  & \GEN_10K|Equal0~1_combout )) ) ) )
+
+	.dataa(!\GEN_10K|count [10]),
+	.datab(gnd),
+	.datac(!\GEN_10K|Equal0~0_combout ),
+	.datad(!\GEN_10K|Equal0~1_combout ),
+	.datae(!\GEN_10K|count [9]),
+	.dataf(!\GEN_10K|Equal0~2_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~3 .extended_lut = "off";
+defparam \GEN_10K|Equal0~3 .lut_mask = 64'h00000000000A0000;
+defparam \GEN_10K|Equal0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y8_N30
+cyclonev_lcell_comb \GEN_10K|tick~feeder (
+// Equation(s):
+// \GEN_10K|tick~feeder_combout  = \GEN_10K|Equal0~3_combout 
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|Equal0~3_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|tick~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|tick~feeder .extended_lut = "off";
+defparam \GEN_10K|tick~feeder .lut_mask = 64'h3333333333333333;
+defparam \GEN_10K|tick~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y8_N32
+dffeas \GEN_10K|tick (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|tick~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|tick~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|tick .is_wysiwyg = "true";
+defparam \GEN_10K|tick .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N51
+cyclonev_lcell_comb \SPI_ADC|Selector2~0 (
+// Equation(s):
+// \SPI_ADC|Selector2~0_combout  = ( \SPI_ADC|sr_state.IDLE~q  & ( \SPI_ADC|adc_cs~q  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|adc_cs~q ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector2~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector2~0 .lut_mask = 64'h000000000F0F0F0F;
+defparam \SPI_ADC|Selector2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N53
+dffeas \SPI_ADC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N48
+cyclonev_lcell_comb \SPI_ADC|Selector0~0 (
+// Equation(s):
+// \SPI_ADC|Selector0~0_combout  = ( \SPI_ADC|adc_cs~q  & ( (\SPI_ADC|sr_state.IDLE~q ) # (\GEN_10K|tick~q ) ) ) # ( !\SPI_ADC|adc_cs~q  & ( (!\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & ((\SPI_ADC|sr_state.IDLE~q ) # (\GEN_10K|tick~q ))) ) )
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|tick~q ),
+	.datac(!\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.datad(!\SPI_ADC|sr_state.IDLE~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector0~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector0~0 .lut_mask = 64'h30F030F033FF33FF;
+defparam \SPI_ADC|Selector0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N50
+dffeas \SPI_ADC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N3
+cyclonev_lcell_comb \SPI_ADC|Selector1~0 (
+// Equation(s):
+// \SPI_ADC|Selector1~0_combout  = ( \SPI_ADC|sr_state.IDLE~q  & ( (!\SPI_ADC|adc_cs~q  & \SPI_ADC|sr_state.WAIT_CSB_FALL~q ) ) ) # ( !\SPI_ADC|sr_state.IDLE~q  & ( ((!\SPI_ADC|adc_cs~q  & \SPI_ADC|sr_state.WAIT_CSB_FALL~q )) # (\GEN_10K|tick~q ) ) )
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|tick~q ),
+	.datac(!\SPI_ADC|adc_cs~q ),
+	.datad(!\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector1~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector1~0 .lut_mask = 64'h33F333F300F000F0;
+defparam \SPI_ADC|Selector1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N5
+dffeas \SPI_ADC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N0
+cyclonev_lcell_comb \SPI_ADC|adc_start~0 (
+// Equation(s):
+// \SPI_ADC|adc_start~0_combout  = ( \SPI_ADC|adc_cs~q  & ( ((!\SPI_ADC|sr_state.IDLE~q  & \GEN_10K|tick~q )) # (\SPI_ADC|adc_start~q ) ) ) # ( !\SPI_ADC|adc_cs~q  & ( (!\SPI_ADC|sr_state.IDLE~q  & (((\SPI_ADC|adc_start~q )) # (\GEN_10K|tick~q ))) # 
+// (\SPI_ADC|sr_state.IDLE~q  & (((\SPI_ADC|sr_state.WAIT_CSB_FALL~q  & \SPI_ADC|adc_start~q )))) ) )
+
+	.dataa(!\SPI_ADC|sr_state.IDLE~q ),
+	.datab(!\GEN_10K|tick~q ),
+	.datac(!\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(!\SPI_ADC|adc_start~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|adc_start~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~0 .extended_lut = "off";
+defparam \SPI_ADC|adc_start~0 .lut_mask = 64'h22AF22AF22FF22FF;
+defparam \SPI_ADC|adc_start~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N1
+dffeas \SPI_ADC|adc_start (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|adc_start~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_start .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_start .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N27
+cyclonev_lcell_comb \SPI_ADC|state[2]~2 (
+// Equation(s):
+// \SPI_ADC|state[2]~2_combout  = !\SPI_ADC|state [2] $ (((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [1])))
+
+	.dataa(!\SPI_ADC|state [0]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|state [1]),
+	.datad(!\SPI_ADC|state [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[2]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[2]~2 .extended_lut = "off";
+defparam \SPI_ADC|state[2]~2 .lut_mask = 64'h05FA05FA05FA05FA;
+defparam \SPI_ADC|state[2]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N53
+dffeas \SPI_ADC|state[2] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[2]~2_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N51
+cyclonev_lcell_comb \SPI_ADC|state[3]~3 (
+// Equation(s):
+// \SPI_ADC|state[3]~3_combout  = ( \SPI_ADC|state [1] & ( !\SPI_ADC|state [3] $ (((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [2]))) ) ) # ( !\SPI_ADC|state [1] & ( \SPI_ADC|state [3] ) )
+
+	.dataa(!\SPI_ADC|state [3]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|state [2]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[3]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[3]~3 .extended_lut = "off";
+defparam \SPI_ADC|state[3]~3 .lut_mask = 64'h5555555555665566;
+defparam \SPI_ADC|state[3]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N26
+dffeas \SPI_ADC|state[3] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[3]~3_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N36
+cyclonev_lcell_comb \SPI_ADC|state~0 (
+// Equation(s):
+// \SPI_ADC|state~0_combout  = ( \SPI_ADC|state [1] & ( !\SPI_ADC|state [4] $ (((!\SPI_ADC|state [2]) # ((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [3])))) ) ) # ( !\SPI_ADC|state [1] & ( (\SPI_ADC|state [4] & (((\SPI_ADC|state [3]) # (\SPI_ADC|state [0])) # 
+// (\SPI_ADC|state [2]))) ) )
+
+	.dataa(!\SPI_ADC|state [2]),
+	.datab(!\SPI_ADC|state [4]),
+	.datac(!\SPI_ADC|state [0]),
+	.datad(!\SPI_ADC|state [3]),
+	.datae(!\SPI_ADC|state [1]),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state~0 .extended_lut = "off";
+defparam \SPI_ADC|state~0 .lut_mask = 64'h1333333613333336;
+defparam \SPI_ADC|state~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N32
+dffeas \SPI_ADC|state[4] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N6
+cyclonev_lcell_comb \SPI_ADC|Selector5~0 (
+// Equation(s):
+// \SPI_ADC|Selector5~0_combout  = ( \SPI_ADC|state [1] & ( !\SPI_ADC|state [0] ) ) # ( !\SPI_ADC|state [1] & ( !\SPI_ADC|state [0] & ( (((\SPI_ADC|adc_start~q  & !\SPI_ADC|state [4])) # (\SPI_ADC|state [2])) # (\SPI_ADC|state [3]) ) ) )
+
+	.dataa(!\SPI_ADC|adc_start~q ),
+	.datab(!\SPI_ADC|state [3]),
+	.datac(!\SPI_ADC|state [2]),
+	.datad(!\SPI_ADC|state [4]),
+	.datae(!\SPI_ADC|state [1]),
+	.dataf(!\SPI_ADC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector5~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector5~0 .lut_mask = 64'h7F3FFFFF00000000;
+defparam \SPI_ADC|Selector5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N20
+dffeas \SPI_ADC|state[0] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|Selector5~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N30
+cyclonev_lcell_comb \SPI_ADC|state[1]~1 (
+// Equation(s):
+// \SPI_ADC|state[1]~1_combout  = ( \SPI_ADC|state [0] & ( !\SPI_ADC|state [1] ) ) # ( !\SPI_ADC|state [0] & ( \SPI_ADC|state [1] ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|state [1]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[1]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[1]~1 .extended_lut = "off";
+defparam \SPI_ADC|state[1]~1 .lut_mask = 64'h33333333CCCCCCCC;
+defparam \SPI_ADC|state[1]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N40
+dffeas \SPI_ADC|state[1] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[1]~1_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N42
+cyclonev_lcell_comb \SPI_ADC|Selector4~0 (
+// Equation(s):
+// \SPI_ADC|Selector4~0_combout  = ( \SPI_ADC|state [2] & ( \SPI_ADC|state [4] ) ) # ( !\SPI_ADC|state [2] & ( \SPI_ADC|state [4] & ( ((\SPI_ADC|state [3]) # (\SPI_ADC|state [0])) # (\SPI_ADC|state [1]) ) ) ) # ( \SPI_ADC|state [2] & ( !\SPI_ADC|state [4] ) 
+// ) # ( !\SPI_ADC|state [2] & ( !\SPI_ADC|state [4] & ( (((\SPI_ADC|state [3]) # (\SPI_ADC|state [0])) # (\SPI_ADC|state [1])) # (\SPI_ADC|adc_start~q ) ) ) )
+
+	.dataa(!\SPI_ADC|adc_start~q ),
+	.datab(!\SPI_ADC|state [1]),
+	.datac(!\SPI_ADC|state [0]),
+	.datad(!\SPI_ADC|state [3]),
+	.datae(!\SPI_ADC|state [2]),
+	.dataf(!\SPI_ADC|state [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector4~0 .lut_mask = 64'h7FFFFFFF3FFFFFFF;
+defparam \SPI_ADC|Selector4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N44
+dffeas \SPI_ADC|adc_cs (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N48
+cyclonev_lcell_comb \SPI_ADC|WideOr0~0 (
+// Equation(s):
+// \SPI_ADC|WideOr0~0_combout  = ( \SPI_ADC|state [2] & ( (!\SPI_ADC|state [3]) # ((!\SPI_ADC|state [0]) # ((!\SPI_ADC|state [1]) # (\SPI_ADC|state [4]))) ) ) # ( !\SPI_ADC|state [2] & ( ((\SPI_ADC|state [4] & ((\SPI_ADC|state [1]) # (\SPI_ADC|state [0])))) 
+// # (\SPI_ADC|state [3]) ) )
+
+	.dataa(!\SPI_ADC|state [3]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(!\SPI_ADC|state [4]),
+	.datad(!\SPI_ADC|state [1]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~0 .extended_lut = "off";
+defparam \SPI_ADC|WideOr0~0 .lut_mask = 64'h575F575FFFEFFFEF;
+defparam \SPI_ADC|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N50
+dffeas \SPI_ADC|shift_ena (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|WideOr0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_ena~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_ena .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_ena .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N21
+cyclonev_lcell_comb \SPI_ADC|always3~0 (
+// Equation(s):
+// \SPI_ADC|always3~0_combout  = ( \SPI_ADC|shift_ena~q  & ( \SPI_ADC|adc_cs~q  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|adc_cs~q ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_ena~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|always3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|always3~0 .extended_lut = "off";
+defparam \SPI_ADC|always3~0 .lut_mask = 64'h000000000F0F0F0F;
+defparam \SPI_ADC|always3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N47
+dffeas \SPI_ADC|shift_reg[0] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N44
+dffeas \SPI_ADC|shift_reg[1] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N57
+cyclonev_lcell_comb \SPI_ADC|shift_reg[2]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[2]~feeder_combout  = ( \SPI_ADC|shift_reg [1] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[2]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[2]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N58
+dffeas \SPI_ADC|shift_reg[2]~DUPLICATE (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N18
+cyclonev_lcell_comb \SPI_ADC|Decoder0~0 (
+// Equation(s):
+// \SPI_ADC|Decoder0~0_combout  = ( \SPI_ADC|state [2] & ( (\SPI_ADC|state [1] & (\SPI_ADC|state [0] & (\SPI_ADC|state [3] & !\SPI_ADC|state [4]))) ) )
+
+	.dataa(!\SPI_ADC|state [1]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(!\SPI_ADC|state [3]),
+	.datad(!\SPI_ADC|state [4]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~0 .extended_lut = "off";
+defparam \SPI_ADC|Decoder0~0 .lut_mask = 64'h0000000001000100;
+defparam \SPI_ADC|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N20
+dffeas \SPI_ADC|adc_done (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Decoder0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_done~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_done .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_done .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N38
+dffeas \SPI_ADC|data_from_adc[2] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg[2]~DUPLICATE_q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N59
+dffeas \SPI_ADC|shift_reg[2] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N55
+dffeas \SPI_ADC|shift_reg[3] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N32
+dffeas \SPI_ADC|data_from_adc[3] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N59
+dffeas \SPI_ADC|data_from_adc[0] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N43
+dffeas \SPI_ADC|shift_reg[1]~DUPLICATE (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg[1]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[1]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N35
+dffeas \SPI_ADC|data_from_adc[1] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg[1]~DUPLICATE_q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N54
+cyclonev_lcell_comb \SEG0|WideOr6~0 (
+// Equation(s):
+// \SEG0|WideOr6~0_combout  = ( \SPI_ADC|data_from_adc [1] & ( (!\SPI_ADC|data_from_adc [2] & (\SPI_ADC|data_from_adc [3] & \SPI_ADC|data_from_adc [0])) ) ) # ( !\SPI_ADC|data_from_adc [1] & ( (!\SPI_ADC|data_from_adc [2] & (!\SPI_ADC|data_from_adc [3] & 
+// \SPI_ADC|data_from_adc [0])) # (\SPI_ADC|data_from_adc [2] & (!\SPI_ADC|data_from_adc [3] $ (\SPI_ADC|data_from_adc [0]))) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [2]),
+	.datab(!\SPI_ADC|data_from_adc [3]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [0]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr6~0 .extended_lut = "off";
+defparam \SEG0|WideOr6~0 .lut_mask = 64'h4499449900220022;
+defparam \SEG0|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N42
+cyclonev_lcell_comb \SEG0|WideOr5~0 (
+// Equation(s):
+// \SEG0|WideOr5~0_combout  = ( \SPI_ADC|data_from_adc [3] & ( (!\SPI_ADC|data_from_adc [0] & ((\SPI_ADC|data_from_adc [2]))) # (\SPI_ADC|data_from_adc [0] & (\SPI_ADC|data_from_adc [1])) ) ) # ( !\SPI_ADC|data_from_adc [3] & ( (\SPI_ADC|data_from_adc [2] & 
+// (!\SPI_ADC|data_from_adc [0] $ (!\SPI_ADC|data_from_adc [1]))) ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [1]),
+	.datad(!\SPI_ADC|data_from_adc [2]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr5~0 .extended_lut = "off";
+defparam \SEG0|WideOr5~0 .lut_mask = 64'h003C003C03CF03CF;
+defparam \SEG0|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N45
+cyclonev_lcell_comb \SEG0|WideOr4~0 (
+// Equation(s):
+// \SEG0|WideOr4~0_combout  = ( \SPI_ADC|data_from_adc [3] & ( (\SPI_ADC|data_from_adc [2] & ((!\SPI_ADC|data_from_adc [0]) # (\SPI_ADC|data_from_adc [1]))) ) ) # ( !\SPI_ADC|data_from_adc [3] & ( (\SPI_ADC|data_from_adc [1] & (!\SPI_ADC|data_from_adc [0] & 
+// !\SPI_ADC|data_from_adc [2])) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [2]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr4~0 .extended_lut = "off";
+defparam \SEG0|WideOr4~0 .lut_mask = 64'h4400440000DD00DD;
+defparam \SEG0|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N57
+cyclonev_lcell_comb \SEG0|WideOr3~0 (
+// Equation(s):
+// \SEG0|WideOr3~0_combout  = ( \SPI_ADC|data_from_adc [1] & ( (!\SPI_ADC|data_from_adc [2] & (\SPI_ADC|data_from_adc [3] & !\SPI_ADC|data_from_adc [0])) # (\SPI_ADC|data_from_adc [2] & ((\SPI_ADC|data_from_adc [0]))) ) ) # ( !\SPI_ADC|data_from_adc [1] & ( 
+// (!\SPI_ADC|data_from_adc [2] & ((\SPI_ADC|data_from_adc [0]))) # (\SPI_ADC|data_from_adc [2] & (!\SPI_ADC|data_from_adc [3] & !\SPI_ADC|data_from_adc [0])) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [2]),
+	.datab(!\SPI_ADC|data_from_adc [3]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [0]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr3~0 .extended_lut = "off";
+defparam \SEG0|WideOr3~0 .lut_mask = 64'h44AA44AA22552255;
+defparam \SEG0|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N33
+cyclonev_lcell_comb \SEG0|WideOr2~0 (
+// Equation(s):
+// \SEG0|WideOr2~0_combout  = ( \SPI_ADC|data_from_adc [3] & ( (!\SPI_ADC|data_from_adc [2] & (\SPI_ADC|data_from_adc [0] & !\SPI_ADC|data_from_adc [1])) ) ) # ( !\SPI_ADC|data_from_adc [3] & ( ((\SPI_ADC|data_from_adc [2] & !\SPI_ADC|data_from_adc [1])) # 
+// (\SPI_ADC|data_from_adc [0]) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [2]),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [1]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr2~0 .extended_lut = "off";
+defparam \SEG0|WideOr2~0 .lut_mask = 64'h7733773322002200;
+defparam \SEG0|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N36
+cyclonev_lcell_comb \SEG0|WideOr1~0 (
+// Equation(s):
+// \SEG0|WideOr1~0_combout  = ( \SPI_ADC|data_from_adc [3] & ( (\SPI_ADC|data_from_adc [0] & (!\SPI_ADC|data_from_adc [1] & \SPI_ADC|data_from_adc [2])) ) ) # ( !\SPI_ADC|data_from_adc [3] & ( (!\SPI_ADC|data_from_adc [0] & (\SPI_ADC|data_from_adc [1] & 
+// !\SPI_ADC|data_from_adc [2])) # (\SPI_ADC|data_from_adc [0] & ((!\SPI_ADC|data_from_adc [2]) # (\SPI_ADC|data_from_adc [1]))) ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [1]),
+	.datad(!\SPI_ADC|data_from_adc [2]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr1~0 .extended_lut = "off";
+defparam \SEG0|WideOr1~0 .lut_mask = 64'h3F033F0300300030;
+defparam \SEG0|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N30
+cyclonev_lcell_comb \SEG0|WideOr0~0 (
+// Equation(s):
+// \SEG0|WideOr0~0_combout  = (!\SPI_ADC|data_from_adc [0] & ((!\SPI_ADC|data_from_adc [2] $ (!\SPI_ADC|data_from_adc [3])) # (\SPI_ADC|data_from_adc [1]))) # (\SPI_ADC|data_from_adc [0] & ((!\SPI_ADC|data_from_adc [2] $ (!\SPI_ADC|data_from_adc [1])) # 
+// (\SPI_ADC|data_from_adc [3])))
+
+	.dataa(!\SPI_ADC|data_from_adc [2]),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(!\SPI_ADC|data_from_adc [1]),
+	.datad(!\SPI_ADC|data_from_adc [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr0~0 .extended_lut = "off";
+defparam \SEG0|WideOr0~0 .lut_mask = 64'h5EBF5EBF5EBF5EBF;
+defparam \SEG0|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N34
+dffeas \SPI_ADC|shift_reg[4] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N30
+cyclonev_lcell_comb \SPI_ADC|shift_reg[5]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[5]~feeder_combout  = ( \SPI_ADC|shift_reg [4] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[5]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N31
+dffeas \SPI_ADC|shift_reg[5] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N39
+cyclonev_lcell_comb \SPI_ADC|shift_reg[6]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[6]~feeder_combout  = ( \SPI_ADC|shift_reg [5] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [5]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N41
+dffeas \SPI_ADC|shift_reg[6] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N50
+dffeas \SPI_ADC|data_from_adc[6] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N36
+cyclonev_lcell_comb \SPI_ADC|shift_reg[7]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[7]~feeder_combout  = ( \SPI_ADC|shift_reg [6] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[7]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[7]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[7]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N38
+dffeas \SPI_ADC|shift_reg[7] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[7]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N2
+dffeas \SPI_ADC|data_from_adc[7] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N5
+dffeas \SPI_ADC|data_from_adc[5] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N53
+dffeas \SPI_ADC|data_from_adc[4] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N39
+cyclonev_lcell_comb \SEG1|WideOr6~0 (
+// Equation(s):
+// \SEG1|WideOr6~0_combout  = ( \SPI_ADC|data_from_adc [4] & ( (!\SPI_ADC|data_from_adc [6] & (!\SPI_ADC|data_from_adc [7] $ (\SPI_ADC|data_from_adc [5]))) # (\SPI_ADC|data_from_adc [6] & (\SPI_ADC|data_from_adc [7] & !\SPI_ADC|data_from_adc [5])) ) ) # ( 
+// !\SPI_ADC|data_from_adc [4] & ( (\SPI_ADC|data_from_adc [6] & (!\SPI_ADC|data_from_adc [7] & !\SPI_ADC|data_from_adc [5])) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [6]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [7]),
+	.datad(!\SPI_ADC|data_from_adc [5]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr6~0 .extended_lut = "off";
+defparam \SEG1|WideOr6~0 .lut_mask = 64'h50005000A50AA50A;
+defparam \SEG1|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N9
+cyclonev_lcell_comb \SEG1|WideOr5~0 (
+// Equation(s):
+// \SEG1|WideOr5~0_combout  = ( \SPI_ADC|data_from_adc [4] & ( (!\SPI_ADC|data_from_adc [7] & (\SPI_ADC|data_from_adc [6] & !\SPI_ADC|data_from_adc [5])) # (\SPI_ADC|data_from_adc [7] & ((\SPI_ADC|data_from_adc [5]))) ) ) # ( !\SPI_ADC|data_from_adc [4] & ( 
+// (\SPI_ADC|data_from_adc [6] & ((\SPI_ADC|data_from_adc [5]) # (\SPI_ADC|data_from_adc [7]))) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [7]),
+	.datab(!\SPI_ADC|data_from_adc [6]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [5]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr5~0 .extended_lut = "off";
+defparam \SEG1|WideOr5~0 .lut_mask = 64'h1133113322552255;
+defparam \SEG1|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N6
+cyclonev_lcell_comb \SEG1|WideOr4~0 (
+// Equation(s):
+// \SEG1|WideOr4~0_combout  = ( \SPI_ADC|data_from_adc [4] & ( (\SPI_ADC|data_from_adc [7] & (\SPI_ADC|data_from_adc [6] & \SPI_ADC|data_from_adc [5])) ) ) # ( !\SPI_ADC|data_from_adc [4] & ( (!\SPI_ADC|data_from_adc [7] & (!\SPI_ADC|data_from_adc [6] & 
+// \SPI_ADC|data_from_adc [5])) # (\SPI_ADC|data_from_adc [7] & (\SPI_ADC|data_from_adc [6])) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [7]),
+	.datab(!\SPI_ADC|data_from_adc [6]),
+	.datac(!\SPI_ADC|data_from_adc [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr4~0 .extended_lut = "off";
+defparam \SEG1|WideOr4~0 .lut_mask = 64'h1919191901010101;
+defparam \SEG1|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N48
+cyclonev_lcell_comb \SEG1|WideOr3~0 (
+// Equation(s):
+// \SEG1|WideOr3~0_combout  = ( \SPI_ADC|data_from_adc [4] & ( !\SPI_ADC|data_from_adc [5] $ (\SPI_ADC|data_from_adc [6]) ) ) # ( !\SPI_ADC|data_from_adc [4] & ( (!\SPI_ADC|data_from_adc [5] & (!\SPI_ADC|data_from_adc [7] & \SPI_ADC|data_from_adc [6])) # 
+// (\SPI_ADC|data_from_adc [5] & (\SPI_ADC|data_from_adc [7] & !\SPI_ADC|data_from_adc [6])) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [5]),
+	.datab(!\SPI_ADC|data_from_adc [7]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [6]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr3~0 .extended_lut = "off";
+defparam \SEG1|WideOr3~0 .lut_mask = 64'h11881188AA55AA55;
+defparam \SEG1|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N51
+cyclonev_lcell_comb \SEG1|WideOr2~0 (
+// Equation(s):
+// \SEG1|WideOr2~0_combout  = ( \SPI_ADC|data_from_adc [6] & ( (!\SPI_ADC|data_from_adc [7] & ((!\SPI_ADC|data_from_adc [5]) # (\SPI_ADC|data_from_adc [4]))) ) ) # ( !\SPI_ADC|data_from_adc [6] & ( (\SPI_ADC|data_from_adc [4] & ((!\SPI_ADC|data_from_adc [5]) 
+// # (!\SPI_ADC|data_from_adc [7]))) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [5]),
+	.datab(!\SPI_ADC|data_from_adc [7]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [4]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr2~0 .extended_lut = "off";
+defparam \SEG1|WideOr2~0 .lut_mask = 64'h00EE00EE88CC88CC;
+defparam \SEG1|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N3
+cyclonev_lcell_comb \SEG1|WideOr1~0 (
+// Equation(s):
+// \SEG1|WideOr1~0_combout  = ( \SPI_ADC|data_from_adc [7] & ( (\SPI_ADC|data_from_adc [4] & (\SPI_ADC|data_from_adc [6] & !\SPI_ADC|data_from_adc [5])) ) ) # ( !\SPI_ADC|data_from_adc [7] & ( (!\SPI_ADC|data_from_adc [4] & (!\SPI_ADC|data_from_adc [6] & 
+// \SPI_ADC|data_from_adc [5])) # (\SPI_ADC|data_from_adc [4] & ((!\SPI_ADC|data_from_adc [6]) # (\SPI_ADC|data_from_adc [5]))) ) )
+
+	.dataa(!\SPI_ADC|data_from_adc [4]),
+	.datab(!\SPI_ADC|data_from_adc [6]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [5]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr1~0 .extended_lut = "off";
+defparam \SEG1|WideOr1~0 .lut_mask = 64'h44DD44DD11001100;
+defparam \SEG1|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N0
+cyclonev_lcell_comb \SEG1|WideOr0~0 (
+// Equation(s):
+// \SEG1|WideOr0~0_combout  = (!\SPI_ADC|data_from_adc [4] & ((!\SPI_ADC|data_from_adc [6] $ (!\SPI_ADC|data_from_adc [7])) # (\SPI_ADC|data_from_adc [5]))) # (\SPI_ADC|data_from_adc [4] & ((!\SPI_ADC|data_from_adc [6] $ (!\SPI_ADC|data_from_adc [5])) # 
+// (\SPI_ADC|data_from_adc [7])))
+
+	.dataa(!\SPI_ADC|data_from_adc [4]),
+	.datab(!\SPI_ADC|data_from_adc [6]),
+	.datac(!\SPI_ADC|data_from_adc [5]),
+	.datad(!\SPI_ADC|data_from_adc [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr0~0 .extended_lut = "off";
+defparam \SEG1|WideOr0~0 .lut_mask = 64'h3EDF3EDF3EDF3EDF;
+defparam \SEG1|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N16
+dffeas \SPI_ADC|shift_reg[8] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N12
+cyclonev_lcell_comb \SPI_ADC|shift_reg[9]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[9]~feeder_combout  = ( \SPI_ADC|shift_reg [8] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[9]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y10_N13
+dffeas \SPI_ADC|shift_reg[9] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N28
+dffeas \SPI_ADC|data_from_adc[9] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N24
+cyclonev_lcell_comb \SPI_ADC|data_from_adc[8]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[8]~feeder_combout  = ( \SPI_ADC|shift_reg [8] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|data_from_adc[8]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[8]~feeder .extended_lut = "off";
+defparam \SPI_ADC|data_from_adc[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|data_from_adc[8]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N25
+dffeas \SPI_ADC|data_from_adc[8] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|data_from_adc[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y21_N3
+cyclonev_lcell_comb \SEG2|Decoder0~0 (
+// Equation(s):
+// \SEG2|Decoder0~0_combout  = ( \SPI_ADC|data_from_adc [8] & ( !\SPI_ADC|data_from_adc [9] ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~0 .extended_lut = "off";
+defparam \SEG2|Decoder0~0 .lut_mask = 64'h00000000F0F0F0F0;
+defparam \SEG2|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X88_Y23_N0
+cyclonev_lcell_comb \SEG2|Decoder0~1 (
+// Equation(s):
+// \SEG2|Decoder0~1_combout  = ( !\SPI_ADC|data_from_adc [8] & ( \SPI_ADC|data_from_adc [9] ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~1 .extended_lut = "off";
+defparam \SEG2|Decoder0~1 .lut_mask = 64'h0F0F0F0F00000000;
+defparam \SEG2|Decoder0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y20_N0
+cyclonev_lcell_comb \SEG2|Decoder0~2 (
+// Equation(s):
+// \SEG2|Decoder0~2_combout  = ( \SPI_ADC|data_from_adc [8] ) # ( !\SPI_ADC|data_from_adc [8] & ( \SPI_ADC|data_from_adc [9] ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~2 .extended_lut = "off";
+defparam \SEG2|Decoder0~2 .lut_mask = 64'h0F0F0F0FFFFFFFFF;
+defparam \SEG2|Decoder0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N30
+cyclonev_lcell_comb \SPI_DAC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_DAC|clk_1MHz~0_combout  = !\SPI_DAC|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_DAC|clk_1MHz~q ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|clk_1MHz~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~0 .extended_lut = "off";
+defparam \SPI_DAC|clk_1MHz~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
+defparam \SPI_DAC|clk_1MHz~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N6
+cyclonev_lcell_comb \SPI_DAC|clk_1MHz~feeder (
+// Equation(s):
+// \SPI_DAC|clk_1MHz~feeder_combout  = ( \SPI_DAC|clk_1MHz~0_combout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|clk_1MHz~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|clk_1MHz~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~feeder .extended_lut = "off";
+defparam \SPI_DAC|clk_1MHz~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_DAC|clk_1MHz~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N8
+dffeas \SPI_DAC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\SPI_DAC|clk_1MHz~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_DAC|Equal0~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_DAC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N16
+dffeas \SPI_DAC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N24
+cyclonev_lcell_comb \SPI_DAC|Selector2~0 (
+// Equation(s):
+// \SPI_DAC|Selector2~0_combout  = (\SPI_DAC|sr_state.IDLE~DUPLICATE_q  & \SPI_DAC|dac_cs~q )
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|sr_state.IDLE~DUPLICATE_q ),
+	.datac(!\SPI_DAC|dac_cs~q ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector2~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector2~0 .lut_mask = 64'h0303030303030303;
+defparam \SPI_DAC|Selector2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N25
+dffeas \SPI_DAC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N15
+cyclonev_lcell_comb \SPI_DAC|Selector0~0 (
+// Equation(s):
+// \SPI_DAC|Selector0~0_combout  = ( \SPI_DAC|sr_state.WAIT_CSB_HIGH~q  & ( (\SPI_DAC|dac_cs~q  & ((\SPI_DAC|sr_state.IDLE~q ) # (\GEN_10K|tick~q ))) ) ) # ( !\SPI_DAC|sr_state.WAIT_CSB_HIGH~q  & ( (\SPI_DAC|sr_state.IDLE~q ) # (\GEN_10K|tick~q ) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(!\GEN_10K|tick~q ),
+	.datad(!\SPI_DAC|sr_state.IDLE~q ),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector0~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector0~0 .lut_mask = 64'h0FFF0FFF05550555;
+defparam \SPI_DAC|Selector0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N17
+dffeas \SPI_DAC|sr_state.IDLE~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.IDLE~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.IDLE~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.IDLE~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N12
+cyclonev_lcell_comb \SPI_DAC|Selector1~0 (
+// Equation(s):
+// \SPI_DAC|Selector1~0_combout  = ( \GEN_10K|tick~q  & ( (!\SPI_DAC|sr_state.IDLE~DUPLICATE_q ) # ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|sr_state.WAIT_CSB_FALL~q )) ) ) # ( !\GEN_10K|tick~q  & ( (!\SPI_DAC|dac_cs~q  & \SPI_DAC|sr_state.WAIT_CSB_FALL~q ) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|sr_state.IDLE~DUPLICATE_q ),
+	.datac(gnd),
+	.datad(!\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datae(gnd),
+	.dataf(!\GEN_10K|tick~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector1~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector1~0 .lut_mask = 64'h00AA00AACCEECCEE;
+defparam \SPI_DAC|Selector1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N14
+dffeas \SPI_DAC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N57
+cyclonev_lcell_comb \SPI_DAC|dac_start~0 (
+// Equation(s):
+// \SPI_DAC|dac_start~0_combout  = ( \SPI_DAC|dac_start~q  & ( \SPI_DAC|sr_state.IDLE~q  & ( (\SPI_DAC|sr_state.WAIT_CSB_FALL~q ) # (\SPI_DAC|dac_cs~q ) ) ) ) # ( \SPI_DAC|dac_start~q  & ( !\SPI_DAC|sr_state.IDLE~q  ) ) # ( !\SPI_DAC|dac_start~q  & ( 
+// !\SPI_DAC|sr_state.IDLE~q  & ( \GEN_10K|tick~q  ) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datac(!\GEN_10K|tick~q ),
+	.datad(gnd),
+	.datae(!\SPI_DAC|dac_start~q ),
+	.dataf(!\SPI_DAC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|dac_start~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_start~0 .extended_lut = "off";
+defparam \SPI_DAC|dac_start~0 .lut_mask = 64'h0F0FFFFF00007777;
+defparam \SPI_DAC|dac_start~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N58
+dffeas \SPI_DAC|dac_start (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|dac_start~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_start .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N51
+cyclonev_lcell_comb \SPI_DAC|Selector5~0 (
+// Equation(s):
+// \SPI_DAC|Selector5~0_combout  = ( \SPI_DAC|state [0] & ( !\SPI_DAC|state [3] $ (((!\SPI_DAC|state [1]) # (!\SPI_DAC|state [2]))) ) ) # ( !\SPI_DAC|state [0] & ( \SPI_DAC|state [3] ) )
+
+	.dataa(!\SPI_DAC|state [3]),
+	.datab(gnd),
+	.datac(!\SPI_DAC|state [1]),
+	.datad(!\SPI_DAC|state [2]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector5~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector5~0 .lut_mask = 64'h55555555555A555A;
+defparam \SPI_DAC|Selector5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N20
+dffeas \SPI_DAC|state[3] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector5~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N54
+cyclonev_lcell_comb \SPI_DAC|Selector4~0 (
+// Equation(s):
+// \SPI_DAC|Selector4~0_combout  = ( \SPI_DAC|state [4] & ( (!\SPI_DAC|state [3] & (((\SPI_DAC|state [0]) # (\SPI_DAC|state [2])) # (\SPI_DAC|state [1]))) # (\SPI_DAC|state [3] & ((!\SPI_DAC|state [1]) # ((!\SPI_DAC|state [2]) # (!\SPI_DAC|state [0])))) ) ) 
+// # ( !\SPI_DAC|state [4] & ( (\SPI_DAC|state [3] & (\SPI_DAC|state [1] & (\SPI_DAC|state [2] & \SPI_DAC|state [0]))) ) )
+
+	.dataa(!\SPI_DAC|state [3]),
+	.datab(!\SPI_DAC|state [1]),
+	.datac(!\SPI_DAC|state [2]),
+	.datad(!\SPI_DAC|state [0]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector4~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector4~0 .lut_mask = 64'h000100017FFE7FFE;
+defparam \SPI_DAC|Selector4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N17
+dffeas \SPI_DAC|state[4] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector4~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N18
+cyclonev_lcell_comb \SPI_DAC|Selector8~0 (
+// Equation(s):
+// \SPI_DAC|Selector8~0_combout  = ( \SPI_DAC|state [3] & ( !\SPI_DAC|state [0] ) ) # ( !\SPI_DAC|state [3] & ( !\SPI_DAC|state [0] & ( (((\SPI_DAC|dac_start~q  & !\SPI_DAC|state [4])) # (\SPI_DAC|state [2])) # (\SPI_DAC|state [1]) ) ) )
+
+	.dataa(!\SPI_DAC|state [1]),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(!\SPI_DAC|state [2]),
+	.datad(!\SPI_DAC|state [4]),
+	.datae(!\SPI_DAC|state [3]),
+	.dataf(!\SPI_DAC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector8~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector8~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector8~0 .lut_mask = 64'h7F5FFFFF00000000;
+defparam \SPI_DAC|Selector8~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N23
+dffeas \SPI_DAC|state[0] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector8~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[0] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N6
+cyclonev_lcell_comb \SPI_DAC|Selector7~0 (
+// Equation(s):
+// \SPI_DAC|Selector7~0_combout  = ( \SPI_DAC|state [1] & ( !\SPI_DAC|state [0] ) ) # ( !\SPI_DAC|state [1] & ( \SPI_DAC|state [0] ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|state [0]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector7~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector7~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector7~0 .lut_mask = 64'h33333333CCCCCCCC;
+defparam \SPI_DAC|Selector7~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N5
+dffeas \SPI_DAC|state[1] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector7~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[1] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N3
+cyclonev_lcell_comb \SPI_DAC|Selector6~0 (
+// Equation(s):
+// \SPI_DAC|Selector6~0_combout  = ( \SPI_DAC|state [0] & ( !\SPI_DAC|state [2] $ (!\SPI_DAC|state [1]) ) ) # ( !\SPI_DAC|state [0] & ( \SPI_DAC|state [2] ) )
+
+	.dataa(!\SPI_DAC|state [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\SPI_DAC|state [1]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector6~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector6~0 .lut_mask = 64'h5555555555AA55AA;
+defparam \SPI_DAC|Selector6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N53
+dffeas \SPI_DAC|state[2] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector6~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N12
+cyclonev_lcell_comb \SPI_DAC|Selector9~0 (
+// Equation(s):
+// \SPI_DAC|Selector9~0_combout  = ( \SPI_DAC|state [1] & ( \SPI_DAC|state [0] ) ) # ( !\SPI_DAC|state [1] & ( \SPI_DAC|state [0] ) ) # ( \SPI_DAC|state [1] & ( !\SPI_DAC|state [0] ) ) # ( !\SPI_DAC|state [1] & ( !\SPI_DAC|state [0] & ( (((!\SPI_DAC|state 
+// [4] & \SPI_DAC|dac_start~q )) # (\SPI_DAC|state [3])) # (\SPI_DAC|state [2]) ) ) )
+
+	.dataa(!\SPI_DAC|state [2]),
+	.datab(!\SPI_DAC|state [4]),
+	.datac(!\SPI_DAC|state [3]),
+	.datad(!\SPI_DAC|dac_start~q ),
+	.datae(!\SPI_DAC|state [1]),
+	.dataf(!\SPI_DAC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector9~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector9~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector9~0 .lut_mask = 64'h5FDFFFFFFFFFFFFF;
+defparam \SPI_DAC|Selector9~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N14
+dffeas \SPI_DAC|dac_cs (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|Selector9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_cs .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N0
+cyclonev_lcell_comb \ALLPASS|Add0~17 (
+// Equation(s):
+// \ALLPASS|Add0~17_sumout  = SUM(( \SPI_ADC|data_from_adc [0] ) + ( VCC ) + ( !VCC ))
+// \ALLPASS|Add0~18  = CARRY(( \SPI_ADC|data_from_adc [0] ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [0]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ALLPASS|Add0~17_sumout ),
+	.cout(\ALLPASS|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|Add0~17 .extended_lut = "off";
+defparam \ALLPASS|Add0~17 .lut_mask = 64'h0000000000003333;
+defparam \ALLPASS|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N3
+cyclonev_lcell_comb \ALLPASS|Add0~13 (
+// Equation(s):
+// \ALLPASS|Add0~13_sumout  = SUM(( \SPI_ADC|data_from_adc [1] ) + ( VCC ) + ( \ALLPASS|Add0~18  ))
+// \ALLPASS|Add0~14  = CARRY(( \SPI_ADC|data_from_adc [1] ) + ( VCC ) + ( \ALLPASS|Add0~18  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ALLPASS|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ALLPASS|Add0~13_sumout ),
+	.cout(\ALLPASS|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|Add0~13 .extended_lut = "off";
+defparam \ALLPASS|Add0~13 .lut_mask = 64'h0000000000005555;
+defparam \ALLPASS|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N6
+cyclonev_lcell_comb \ALLPASS|Add0~9 (
+// Equation(s):
+// \ALLPASS|Add0~9_sumout  = SUM(( \SPI_ADC|data_from_adc [2] ) + ( VCC ) + ( \ALLPASS|Add0~14  ))
+// \ALLPASS|Add0~10  = CARRY(( \SPI_ADC|data_from_adc [2] ) + ( VCC ) + ( \ALLPASS|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [2]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ALLPASS|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ALLPASS|Add0~9_sumout ),
+	.cout(\ALLPASS|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|Add0~9 .extended_lut = "off";
+defparam \ALLPASS|Add0~9 .lut_mask = 64'h0000000000000F0F;
+defparam \ALLPASS|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N9
+cyclonev_lcell_comb \ALLPASS|Add0~29 (
+// Equation(s):
+// \ALLPASS|Add0~29_sumout  = SUM(( \SPI_ADC|data_from_adc [3] ) + ( VCC ) + ( \ALLPASS|Add0~10  ))
+// \ALLPASS|Add0~30  = CARRY(( \SPI_ADC|data_from_adc [3] ) + ( VCC ) + ( \ALLPASS|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [3]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ALLPASS|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ALLPASS|Add0~29_sumout ),
+	.cout(\ALLPASS|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|Add0~29 .extended_lut = "off";
+defparam \ALLPASS|Add0~29 .lut_mask = 64'h0000000000000F0F;
+defparam \ALLPASS|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N12
+cyclonev_lcell_comb \ALLPASS|Add0~25 (
+// Equation(s):
+// \ALLPASS|Add0~25_sumout  = SUM(( \SPI_ADC|data_from_adc [4] ) + ( VCC ) + ( \ALLPASS|Add0~30  ))
+// \ALLPASS|Add0~26  = CARRY(( \SPI_ADC|data_from_adc [4] ) + ( VCC ) + ( \ALLPASS|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ALLPASS|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ALLPASS|Add0~25_sumout ),
+	.cout(\ALLPASS|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|Add0~25 .extended_lut = "off";
+defparam \ALLPASS|Add0~25 .lut_mask = 64'h0000000000000F0F;
+defparam \ALLPASS|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N15
+cyclonev_lcell_comb \ALLPASS|Add0~21 (
+// Equation(s):
+// \ALLPASS|Add0~21_sumout  = SUM(( \SPI_ADC|data_from_adc [5] ) + ( VCC ) + ( \ALLPASS|Add0~26  ))
+// \ALLPASS|Add0~22  = CARRY(( \SPI_ADC|data_from_adc [5] ) + ( VCC ) + ( \ALLPASS|Add0~26  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ALLPASS|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ALLPASS|Add0~21_sumout ),
+	.cout(\ALLPASS|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|Add0~21 .extended_lut = "off";
+defparam \ALLPASS|Add0~21 .lut_mask = 64'h0000000000005555;
+defparam \ALLPASS|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N17
+dffeas \ALLPASS|data_out[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ALLPASS|Add0~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ALLPASS|data_out [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ALLPASS|data_out[7] .is_wysiwyg = "true";
+defparam \ALLPASS|data_out[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N14
+dffeas \ALLPASS|data_out[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ALLPASS|Add0~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ALLPASS|data_out [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ALLPASS|data_out[6] .is_wysiwyg = "true";
+defparam \ALLPASS|data_out[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N5
+dffeas \ALLPASS|data_out[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ALLPASS|Add0~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ALLPASS|data_out [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ALLPASS|data_out[3] .is_wysiwyg = "true";
+defparam \ALLPASS|data_out[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N2
+dffeas \ALLPASS|data_out[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ALLPASS|Add0~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ALLPASS|data_out [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ALLPASS|data_out[2] .is_wysiwyg = "true";
+defparam \ALLPASS|data_out[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N12
+cyclonev_lcell_comb \SPI_DAC|shift_reg~11 (
+// Equation(s):
+// \SPI_DAC|shift_reg~11_combout  = ( !\SPI_DAC|dac_cs~q  & ( (\SPI_DAC|dac_start~q  & \ALLPASS|data_out [2]) ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(!\ALLPASS|data_out [2]),
+	.datad(gnd),
+	.datae(!\SPI_DAC|dac_cs~q ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~11_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~11 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~11 .lut_mask = 64'h0303000003030000;
+defparam \SPI_DAC|shift_reg~11 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N13
+dffeas \SPI_DAC|shift_reg[4] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N48
+cyclonev_lcell_comb \SPI_DAC|shift_reg~10 (
+// Equation(s):
+// \SPI_DAC|shift_reg~10_combout  = ( \SPI_DAC|shift_reg [4] & ( (!\SPI_DAC|dac_start~q ) # ((\SPI_DAC|dac_cs~q ) # (\ALLPASS|data_out [3])) ) ) # ( !\SPI_DAC|shift_reg [4] & ( (\SPI_DAC|dac_start~q  & (\ALLPASS|data_out [3] & !\SPI_DAC|dac_cs~q )) ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(!\ALLPASS|data_out [3]),
+	.datad(!\SPI_DAC|dac_cs~q ),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|shift_reg [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~10_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~10 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~10 .lut_mask = 64'h03000300CFFFCFFF;
+defparam \SPI_DAC|shift_reg~10 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N49
+dffeas \SPI_DAC|shift_reg[5] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N8
+dffeas \ALLPASS|data_out[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ALLPASS|Add0~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ALLPASS|data_out [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ALLPASS|data_out[4] .is_wysiwyg = "true";
+defparam \ALLPASS|data_out[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N45
+cyclonev_lcell_comb \SPI_DAC|shift_reg~9 (
+// Equation(s):
+// \SPI_DAC|shift_reg~9_combout  = ( \ALLPASS|data_out [4] & ( ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q )) # (\SPI_DAC|shift_reg [5]) ) ) # ( !\ALLPASS|data_out [4] & ( (\SPI_DAC|shift_reg [5] & ((!\SPI_DAC|dac_start~q ) # (\SPI_DAC|dac_cs~q ))) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(!\SPI_DAC|shift_reg [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ALLPASS|data_out [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~9_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~9 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~9 .lut_mask = 64'h0D0D0D0D2F2F2F2F;
+defparam \SPI_DAC|shift_reg~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N47
+dffeas \SPI_DAC|shift_reg[6] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N11
+dffeas \ALLPASS|data_out[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ALLPASS|Add0~29_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ALLPASS|data_out [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ALLPASS|data_out[5] .is_wysiwyg = "true";
+defparam \ALLPASS|data_out[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N42
+cyclonev_lcell_comb \SPI_DAC|shift_reg~8 (
+// Equation(s):
+// \SPI_DAC|shift_reg~8_combout  = ( \ALLPASS|data_out [5] & ( ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q )) # (\SPI_DAC|shift_reg [6]) ) ) # ( !\ALLPASS|data_out [5] & ( (\SPI_DAC|shift_reg [6] & ((!\SPI_DAC|dac_start~q ) # (\SPI_DAC|dac_cs~q ))) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(!\SPI_DAC|shift_reg [6]),
+	.datae(gnd),
+	.dataf(!\ALLPASS|data_out [5]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~8_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~8 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~8 .lut_mask = 64'h00DD00DD22FF22FF;
+defparam \SPI_DAC|shift_reg~8 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N44
+dffeas \SPI_DAC|shift_reg[7] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N33
+cyclonev_lcell_comb \SPI_DAC|shift_reg~7 (
+// Equation(s):
+// \SPI_DAC|shift_reg~7_combout  = ( \SPI_DAC|shift_reg [7] & ( ((!\SPI_DAC|dac_start~q ) # (\ALLPASS|data_out [6])) # (\SPI_DAC|dac_cs~q ) ) ) # ( !\SPI_DAC|shift_reg [7] & ( (!\SPI_DAC|dac_cs~q  & (\SPI_DAC|dac_start~q  & \ALLPASS|data_out [6])) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(!\ALLPASS|data_out [6]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|shift_reg [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~7_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~7 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~7 .lut_mask = 64'h00220022DDFFDDFF;
+defparam \SPI_DAC|shift_reg~7 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N35
+dffeas \SPI_DAC|shift_reg[8] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N30
+cyclonev_lcell_comb \SPI_DAC|shift_reg~6 (
+// Equation(s):
+// \SPI_DAC|shift_reg~6_combout  = ( \SPI_DAC|shift_reg [8] & ( ((!\SPI_DAC|dac_start~q ) # (\ALLPASS|data_out [7])) # (\SPI_DAC|dac_cs~q ) ) ) # ( !\SPI_DAC|shift_reg [8] & ( (!\SPI_DAC|dac_cs~q  & (\SPI_DAC|dac_start~q  & \ALLPASS|data_out [7])) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(!\ALLPASS|data_out [7]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|shift_reg [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~6 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~6 .lut_mask = 64'h00220022DDFFDDFF;
+defparam \SPI_DAC|shift_reg~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N31
+dffeas \SPI_DAC|shift_reg[9] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N18
+cyclonev_lcell_comb \ALLPASS|Add0~5 (
+// Equation(s):
+// \ALLPASS|Add0~5_sumout  = SUM(( \SPI_ADC|data_from_adc [6] ) + ( VCC ) + ( \ALLPASS|Add0~22  ))
+// \ALLPASS|Add0~6  = CARRY(( \SPI_ADC|data_from_adc [6] ) + ( VCC ) + ( \ALLPASS|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [6]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ALLPASS|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ALLPASS|Add0~5_sumout ),
+	.cout(\ALLPASS|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|Add0~5 .extended_lut = "off";
+defparam \ALLPASS|Add0~5 .lut_mask = 64'h0000000000000F0F;
+defparam \ALLPASS|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y10_N20
+dffeas \ALLPASS|data_out[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ALLPASS|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ALLPASS|data_out [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ALLPASS|data_out[8] .is_wysiwyg = "true";
+defparam \ALLPASS|data_out[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y11_N9
+cyclonev_lcell_comb \SPI_DAC|shift_reg~5 (
+// Equation(s):
+// \SPI_DAC|shift_reg~5_combout  = ( \ALLPASS|data_out [8] & ( ((\SPI_DAC|dac_start~q  & !\SPI_DAC|dac_cs~q )) # (\SPI_DAC|shift_reg [9]) ) ) # ( !\ALLPASS|data_out [8] & ( (\SPI_DAC|shift_reg [9] & ((!\SPI_DAC|dac_start~q ) # (\SPI_DAC|dac_cs~q ))) ) )
+
+	.dataa(!\SPI_DAC|shift_reg [9]),
+	.datab(gnd),
+	.datac(!\SPI_DAC|dac_start~q ),
+	.datad(!\SPI_DAC|dac_cs~q ),
+	.datae(gnd),
+	.dataf(!\ALLPASS|data_out [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~5 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~5 .lut_mask = 64'h505550555F555F55;
+defparam \SPI_DAC|shift_reg~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X80_Y11_N10
+dffeas \SPI_DAC|shift_reg[10] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[10] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X80_Y10_N21
+cyclonev_lcell_comb \ALLPASS|Add0~1 (
+// Equation(s):
+// \ALLPASS|Add0~1_sumout  = SUM(( \SPI_ADC|data_from_adc [7] ) + ( GND ) + ( \ALLPASS|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [7]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ALLPASS|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ALLPASS|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|Add0~1 .extended_lut = "off";
+defparam \ALLPASS|Add0~1 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \ALLPASS|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X81_Y10_N33
+cyclonev_lcell_comb \ALLPASS|data_out[9]~0 (
+// Equation(s):
+// \ALLPASS|data_out[9]~0_combout  = ( !\ALLPASS|Add0~1_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\ALLPASS|Add0~1_sumout ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ALLPASS|data_out[9]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ALLPASS|data_out[9]~0 .extended_lut = "off";
+defparam \ALLPASS|data_out[9]~0 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \ALLPASS|data_out[9]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X81_Y10_N35
+dffeas \ALLPASS|data_out[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ALLPASS|data_out[9]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ALLPASS|data_out [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ALLPASS|data_out[9] .is_wysiwyg = "true";
+defparam \ALLPASS|data_out[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N0
+cyclonev_lcell_comb \SPI_DAC|shift_reg~4 (
+// Equation(s):
+// \SPI_DAC|shift_reg~4_combout  = ( \ALLPASS|data_out [9] & ( ((\SPI_DAC|dac_start~q  & !\SPI_DAC|dac_cs~q )) # (\SPI_DAC|shift_reg [10]) ) ) # ( !\ALLPASS|data_out [9] & ( (\SPI_DAC|shift_reg [10] & ((!\SPI_DAC|dac_start~q ) # (\SPI_DAC|dac_cs~q ))) ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(!\SPI_DAC|dac_cs~q ),
+	.datad(!\SPI_DAC|shift_reg [10]),
+	.datae(gnd),
+	.dataf(!\ALLPASS|data_out [9]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~4 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~4 .lut_mask = 64'h00CF00CF30FF30FF;
+defparam \SPI_DAC|shift_reg~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N2
+dffeas \SPI_DAC|shift_reg[11] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[11] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N39
+cyclonev_lcell_comb \SPI_DAC|shift_reg~3 (
+// Equation(s):
+// \SPI_DAC|shift_reg~3_combout  = ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q )) # (\SPI_DAC|shift_reg [11])
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(!\SPI_DAC|shift_reg [11]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~3 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~3 .lut_mask = 64'h22FF22FF22FF22FF;
+defparam \SPI_DAC|shift_reg~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N41
+dffeas \SPI_DAC|shift_reg[12] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[12] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N36
+cyclonev_lcell_comb \SPI_DAC|shift_reg~2 (
+// Equation(s):
+// \SPI_DAC|shift_reg~2_combout  = ( \SPI_DAC|shift_reg [12] ) # ( !\SPI_DAC|shift_reg [12] & ( (!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q ) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|shift_reg [12]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~2 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~2 .lut_mask = 64'h22222222FFFFFFFF;
+defparam \SPI_DAC|shift_reg~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N38
+dffeas \SPI_DAC|shift_reg[13] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[13] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N27
+cyclonev_lcell_comb \SPI_DAC|shift_reg~1 (
+// Equation(s):
+// \SPI_DAC|shift_reg~1_combout  = ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q )) # (\SPI_DAC|shift_reg [13])
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(!\SPI_DAC|shift_reg [13]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~1 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~1 .lut_mask = 64'h22FF22FF22FF22FF;
+defparam \SPI_DAC|shift_reg~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N28
+dffeas \SPI_DAC|shift_reg[14] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[14] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N24
+cyclonev_lcell_comb \SPI_DAC|shift_reg~0 (
+// Equation(s):
+// \SPI_DAC|shift_reg~0_combout  = ( \SPI_DAC|shift_reg [14] & ( (!\SPI_DAC|dac_start~q ) # (\SPI_DAC|dac_cs~q ) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|shift_reg [14]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~0 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~0 .lut_mask = 64'h00000000DDDDDDDD;
+defparam \SPI_DAC|shift_reg~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N26
+dffeas \SPI_DAC|shift_reg[15] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[15] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N33
+cyclonev_lcell_comb \SPI_DAC|dac_sck (
+// Equation(s):
+// \SPI_DAC|dac_sck~combout  = (!\SPI_DAC|dac_cs~q ) # (\SPI_DAC|clk_1MHz~q )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\SPI_DAC|clk_1MHz~q ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|dac_sck~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_sck .extended_lut = "off";
+defparam \SPI_DAC|dac_sck .lut_mask = 64'hAAFFAAFFAAFFAAFF;
+defparam \SPI_DAC|dac_sck .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y11_N57
+cyclonev_lcell_comb \SPI_DAC|Equal2~0 (
+// Equation(s):
+// \SPI_DAC|Equal2~0_combout  = ( \SPI_DAC|state [2] ) # ( !\SPI_DAC|state [2] & ( (((!\SPI_DAC|state [4]) # (\SPI_DAC|state [0])) # (\SPI_DAC|state [1])) # (\SPI_DAC|state [3]) ) )
+
+	.dataa(!\SPI_DAC|state [3]),
+	.datab(!\SPI_DAC|state [1]),
+	.datac(!\SPI_DAC|state [0]),
+	.datad(!\SPI_DAC|state [4]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Equal2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal2~0 .extended_lut = "off";
+defparam \SPI_DAC|Equal2~0 .lut_mask = 64'hFF7FFF7FFFFFFFFF;
+defparam \SPI_DAC|Equal2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X79_Y11_N58
+dffeas \SPI_DAC|dac_ld (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|Equal2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_ld~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_ld .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_ld .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y10_N24
+cyclonev_lcell_comb \SPI_ADC|Selector6~0 (
+// Equation(s):
+// \SPI_ADC|Selector6~0_combout  = ( !\SPI_ADC|state [3] & ( !\SPI_ADC|state [2] & ( (!\SPI_ADC|state [4] & (((\SPI_ADC|adc_start~q ) # (\SPI_ADC|state [1])) # (\SPI_ADC|state [0]))) ) ) )
+
+	.dataa(!\SPI_ADC|state [4]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(!\SPI_ADC|state [1]),
+	.datad(!\SPI_ADC|adc_start~q ),
+	.datae(!\SPI_ADC|state [3]),
+	.dataf(!\SPI_ADC|state [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector6~0 .lut_mask = 64'h2AAA000000000000;
+defparam \SPI_ADC|Selector6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y11_N8
+dffeas \SPI_ADC|adc_din (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|Selector6~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_din~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_din .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_din .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y11_N21
+cyclonev_lcell_comb \SPI_ADC|adc_sck (
+// Equation(s):
+// \SPI_ADC|adc_sck~combout  = ( \SPI_ADC|clk_1MHz~q  ) # ( !\SPI_ADC|clk_1MHz~q  & ( !\SPI_ADC|adc_cs~q  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_ADC|adc_cs~q ),
+	.datad(gnd),
+	.datae(!\SPI_ADC|clk_1MHz~q ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|adc_sck~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_sck .extended_lut = "off";
+defparam \SPI_ADC|adc_sck .lut_mask = 64'hF0F0FFFFF0F0FFFF;
+defparam \SPI_ADC|adc_sck .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y10_N0
+cyclonev_lcell_comb \PWM_DC|count[0]~0 (
+// Equation(s):
+// \PWM_DC|count[0]~0_combout  = ( !\PWM_DC|count [0] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\PWM_DC|count [0]),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|count[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|count[0]~0 .extended_lut = "off";
+defparam \PWM_DC|count[0]~0 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \PWM_DC|count[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X75_Y10_N1
+dffeas \PWM_DC|count[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|count[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[0] .is_wysiwyg = "true";
+defparam \PWM_DC|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N0
+cyclonev_lcell_comb \PWM_DC|Add0~21 (
+// Equation(s):
+// \PWM_DC|Add0~21_sumout  = SUM(( \PWM_DC|count [1] ) + ( \PWM_DC|count [0] ) + ( !VCC ))
+// \PWM_DC|Add0~22  = CARRY(( \PWM_DC|count [1] ) + ( \PWM_DC|count [0] ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\PWM_DC|count [0]),
+	.datad(!\PWM_DC|count [1]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~21_sumout ),
+	.cout(\PWM_DC|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~21 .extended_lut = "off";
+defparam \PWM_DC|Add0~21 .lut_mask = 64'h0000F0F0000000FF;
+defparam \PWM_DC|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N2
+dffeas \PWM_DC|count[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[1] .is_wysiwyg = "true";
+defparam \PWM_DC|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N3
+cyclonev_lcell_comb \PWM_DC|Add0~17 (
+// Equation(s):
+// \PWM_DC|Add0~17_sumout  = SUM(( \PWM_DC|count [2] ) + ( GND ) + ( \PWM_DC|Add0~22  ))
+// \PWM_DC|Add0~18  = CARRY(( \PWM_DC|count [2] ) + ( GND ) + ( \PWM_DC|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~17_sumout ),
+	.cout(\PWM_DC|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~17 .extended_lut = "off";
+defparam \PWM_DC|Add0~17 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N5
+dffeas \PWM_DC|count[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[2] .is_wysiwyg = "true";
+defparam \PWM_DC|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N6
+cyclonev_lcell_comb \PWM_DC|Add0~13 (
+// Equation(s):
+// \PWM_DC|Add0~13_sumout  = SUM(( \PWM_DC|count [3] ) + ( GND ) + ( \PWM_DC|Add0~18  ))
+// \PWM_DC|Add0~14  = CARRY(( \PWM_DC|count [3] ) + ( GND ) + ( \PWM_DC|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~13_sumout ),
+	.cout(\PWM_DC|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~13 .extended_lut = "off";
+defparam \PWM_DC|Add0~13 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N8
+dffeas \PWM_DC|count[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[3] .is_wysiwyg = "true";
+defparam \PWM_DC|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N9
+cyclonev_lcell_comb \PWM_DC|Add0~9 (
+// Equation(s):
+// \PWM_DC|Add0~9_sumout  = SUM(( \PWM_DC|count [4] ) + ( GND ) + ( \PWM_DC|Add0~14  ))
+// \PWM_DC|Add0~10  = CARRY(( \PWM_DC|count [4] ) + ( GND ) + ( \PWM_DC|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [4]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~9_sumout ),
+	.cout(\PWM_DC|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~9 .extended_lut = "off";
+defparam \PWM_DC|Add0~9 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N11
+dffeas \PWM_DC|count[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[4] .is_wysiwyg = "true";
+defparam \PWM_DC|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N12
+cyclonev_lcell_comb \PWM_DC|Add0~33 (
+// Equation(s):
+// \PWM_DC|Add0~33_sumout  = SUM(( \PWM_DC|count [5] ) + ( GND ) + ( \PWM_DC|Add0~10  ))
+// \PWM_DC|Add0~34  = CARRY(( \PWM_DC|count [5] ) + ( GND ) + ( \PWM_DC|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [5]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~33_sumout ),
+	.cout(\PWM_DC|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~33 .extended_lut = "off";
+defparam \PWM_DC|Add0~33 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N14
+dffeas \PWM_DC|count[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[5] .is_wysiwyg = "true";
+defparam \PWM_DC|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N15
+cyclonev_lcell_comb \PWM_DC|Add0~29 (
+// Equation(s):
+// \PWM_DC|Add0~29_sumout  = SUM(( \PWM_DC|count [6] ) + ( GND ) + ( \PWM_DC|Add0~34  ))
+// \PWM_DC|Add0~30  = CARRY(( \PWM_DC|count [6] ) + ( GND ) + ( \PWM_DC|Add0~34  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [6]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~29_sumout ),
+	.cout(\PWM_DC|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~29 .extended_lut = "off";
+defparam \PWM_DC|Add0~29 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N17
+dffeas \PWM_DC|count[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~29_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[6] .is_wysiwyg = "true";
+defparam \PWM_DC|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N18
+cyclonev_lcell_comb \PWM_DC|Add0~25 (
+// Equation(s):
+// \PWM_DC|Add0~25_sumout  = SUM(( \PWM_DC|count [7] ) + ( GND ) + ( \PWM_DC|Add0~30  ))
+// \PWM_DC|Add0~26  = CARRY(( \PWM_DC|count [7] ) + ( GND ) + ( \PWM_DC|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~25_sumout ),
+	.cout(\PWM_DC|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~25 .extended_lut = "off";
+defparam \PWM_DC|Add0~25 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N20
+dffeas \PWM_DC|count[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[7] .is_wysiwyg = "true";
+defparam \PWM_DC|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N21
+cyclonev_lcell_comb \PWM_DC|Add0~5 (
+// Equation(s):
+// \PWM_DC|Add0~5_sumout  = SUM(( \PWM_DC|count [8] ) + ( GND ) + ( \PWM_DC|Add0~26  ))
+// \PWM_DC|Add0~6  = CARRY(( \PWM_DC|count [8] ) + ( GND ) + ( \PWM_DC|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [8]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~5_sumout ),
+	.cout(\PWM_DC|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~5 .extended_lut = "off";
+defparam \PWM_DC|Add0~5 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N22
+dffeas \PWM_DC|count[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[8] .is_wysiwyg = "true";
+defparam \PWM_DC|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N24
+cyclonev_lcell_comb \PWM_DC|Add0~1 (
+// Equation(s):
+// \PWM_DC|Add0~1_sumout  = SUM(( \PWM_DC|count [9] ) + ( GND ) + ( \PWM_DC|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [9]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~1 .extended_lut = "off";
+defparam \PWM_DC|Add0~1 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N26
+dffeas \PWM_DC|count[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~1_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[9] .is_wysiwyg = "true";
+defparam \PWM_DC|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N41
+dffeas \PWM_DC|d[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ALLPASS|data_out [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\GEN_10K|tick~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[9] .is_wysiwyg = "true";
+defparam \PWM_DC|d[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N38
+dffeas \PWM_DC|d[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ALLPASS|data_out [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\GEN_10K|tick~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[2] .is_wysiwyg = "true";
+defparam \PWM_DC|d[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N36
+cyclonev_lcell_comb \PWM_DC|LessThan0~0 (
+// Equation(s):
+// \PWM_DC|LessThan0~0_combout  = ( \PWM_DC|d [2] & ( (!\PWM_DC|count [2]) # ((!\PWM_DC|count [1] & !\PWM_DC|count [0])) ) ) # ( !\PWM_DC|d [2] & ( (!\PWM_DC|count [1] & (!\PWM_DC|count [0] & !\PWM_DC|count [2])) ) )
+
+	.dataa(!\PWM_DC|count [1]),
+	.datab(!\PWM_DC|count [0]),
+	.datac(!\PWM_DC|count [2]),
+	.datad(gnd),
+	.datae(!\PWM_DC|d [2]),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~0 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~0 .lut_mask = 64'h8080F8F88080F8F8;
+defparam \PWM_DC|LessThan0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N43
+dffeas \PWM_DC|d[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ALLPASS|data_out [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\GEN_10K|tick~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[7] .is_wysiwyg = "true";
+defparam \PWM_DC|d[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N58
+dffeas \PWM_DC|d[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ALLPASS|data_out [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\GEN_10K|tick~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[6] .is_wysiwyg = "true";
+defparam \PWM_DC|d[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N55
+dffeas \PWM_DC|d[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ALLPASS|data_out [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\GEN_10K|tick~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[5] .is_wysiwyg = "true";
+defparam \PWM_DC|d[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N54
+cyclonev_lcell_comb \PWM_DC|LessThan0~1 (
+// Equation(s):
+// \PWM_DC|LessThan0~1_combout  = ( \PWM_DC|d [5] & ( \PWM_DC|count [6] & ( (\PWM_DC|d [6] & (\PWM_DC|count [5] & (!\PWM_DC|count [7] $ (\PWM_DC|d [7])))) ) ) ) # ( !\PWM_DC|d [5] & ( \PWM_DC|count [6] & ( (\PWM_DC|d [6] & (!\PWM_DC|count [5] & 
+// (!\PWM_DC|count [7] $ (\PWM_DC|d [7])))) ) ) ) # ( \PWM_DC|d [5] & ( !\PWM_DC|count [6] & ( (!\PWM_DC|d [6] & (\PWM_DC|count [5] & (!\PWM_DC|count [7] $ (\PWM_DC|d [7])))) ) ) ) # ( !\PWM_DC|d [5] & ( !\PWM_DC|count [6] & ( (!\PWM_DC|d [6] & 
+// (!\PWM_DC|count [5] & (!\PWM_DC|count [7] $ (\PWM_DC|d [7])))) ) ) )
+
+	.dataa(!\PWM_DC|count [7]),
+	.datab(!\PWM_DC|d [7]),
+	.datac(!\PWM_DC|d [6]),
+	.datad(!\PWM_DC|count [5]),
+	.datae(!\PWM_DC|d [5]),
+	.dataf(!\PWM_DC|count [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~1 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~1 .lut_mask = 64'h9000009009000009;
+defparam \PWM_DC|LessThan0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N52
+dffeas \PWM_DC|d[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ALLPASS|data_out [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\GEN_10K|tick~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[3] .is_wysiwyg = "true";
+defparam \PWM_DC|d[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N50
+dffeas \PWM_DC|d[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ALLPASS|data_out [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\GEN_10K|tick~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[4] .is_wysiwyg = "true";
+defparam \PWM_DC|d[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N48
+cyclonev_lcell_comb \PWM_DC|LessThan0~2 (
+// Equation(s):
+// \PWM_DC|LessThan0~2_combout  = ( \PWM_DC|d [4] & ( \PWM_DC|count [3] & ( (\PWM_DC|count [4] & (\PWM_DC|LessThan0~1_combout  & ((!\PWM_DC|LessThan0~0_combout ) # (!\PWM_DC|d [3])))) ) ) ) # ( !\PWM_DC|d [4] & ( \PWM_DC|count [3] & ( 
+// (\PWM_DC|LessThan0~1_combout  & ((!\PWM_DC|LessThan0~0_combout ) # ((!\PWM_DC|d [3]) # (\PWM_DC|count [4])))) ) ) ) # ( \PWM_DC|d [4] & ( !\PWM_DC|count [3] & ( (!\PWM_DC|LessThan0~0_combout  & (\PWM_DC|count [4] & (\PWM_DC|LessThan0~1_combout  & 
+// !\PWM_DC|d [3]))) ) ) ) # ( !\PWM_DC|d [4] & ( !\PWM_DC|count [3] & ( (\PWM_DC|LessThan0~1_combout  & (((!\PWM_DC|LessThan0~0_combout  & !\PWM_DC|d [3])) # (\PWM_DC|count [4]))) ) ) )
+
+	.dataa(!\PWM_DC|LessThan0~0_combout ),
+	.datab(!\PWM_DC|count [4]),
+	.datac(!\PWM_DC|LessThan0~1_combout ),
+	.datad(!\PWM_DC|d [3]),
+	.datae(!\PWM_DC|d [4]),
+	.dataf(!\PWM_DC|count [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~2 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~2 .lut_mask = 64'h0B0302000F0B0302;
+defparam \PWM_DC|LessThan0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N42
+cyclonev_lcell_comb \PWM_DC|LessThan0~3 (
+// Equation(s):
+// \PWM_DC|LessThan0~3_combout  = ( \PWM_DC|d [7] & ( \PWM_DC|count [5] & ( (\PWM_DC|count [7] & ((!\PWM_DC|d [6] & ((!\PWM_DC|d [5]) # (\PWM_DC|count [6]))) # (\PWM_DC|d [6] & (!\PWM_DC|d [5] & \PWM_DC|count [6])))) ) ) ) # ( !\PWM_DC|d [7] & ( 
+// \PWM_DC|count [5] & ( ((!\PWM_DC|d [6] & ((!\PWM_DC|d [5]) # (\PWM_DC|count [6]))) # (\PWM_DC|d [6] & (!\PWM_DC|d [5] & \PWM_DC|count [6]))) # (\PWM_DC|count [7]) ) ) ) # ( \PWM_DC|d [7] & ( !\PWM_DC|count [5] & ( (!\PWM_DC|d [6] & (\PWM_DC|count [7] & 
+// \PWM_DC|count [6])) ) ) ) # ( !\PWM_DC|d [7] & ( !\PWM_DC|count [5] & ( ((!\PWM_DC|d [6] & \PWM_DC|count [6])) # (\PWM_DC|count [7]) ) ) )
+
+	.dataa(!\PWM_DC|d [6]),
+	.datab(!\PWM_DC|d [5]),
+	.datac(!\PWM_DC|count [7]),
+	.datad(!\PWM_DC|count [6]),
+	.datae(!\PWM_DC|d [7]),
+	.dataf(!\PWM_DC|count [5]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~3 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~3 .lut_mask = 64'h0FAF000A8FEF080E;
+defparam \PWM_DC|LessThan0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N47
+dffeas \PWM_DC|d[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ALLPASS|data_out [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\GEN_10K|tick~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[8] .is_wysiwyg = "true";
+defparam \PWM_DC|d[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X78_Y10_N30
+cyclonev_lcell_comb \PWM_DC|LessThan0~4 (
+// Equation(s):
+// \PWM_DC|LessThan0~4_combout  = ( \PWM_DC|count [8] & ( \PWM_DC|d [8] & ( (!\PWM_DC|count [9] & (((!\PWM_DC|LessThan0~2_combout  & !\PWM_DC|LessThan0~3_combout )) # (\PWM_DC|d [9]))) # (\PWM_DC|count [9] & (\PWM_DC|d [9] & (!\PWM_DC|LessThan0~2_combout  & 
+// !\PWM_DC|LessThan0~3_combout ))) ) ) ) # ( !\PWM_DC|count [8] & ( \PWM_DC|d [8] & ( (!\PWM_DC|count [9]) # (\PWM_DC|d [9]) ) ) ) # ( \PWM_DC|count [8] & ( !\PWM_DC|d [8] & ( (!\PWM_DC|count [9] & \PWM_DC|d [9]) ) ) ) # ( !\PWM_DC|count [8] & ( !\PWM_DC|d 
+// [8] & ( (!\PWM_DC|count [9] & (((!\PWM_DC|LessThan0~2_combout  & !\PWM_DC|LessThan0~3_combout )) # (\PWM_DC|d [9]))) # (\PWM_DC|count [9] & (\PWM_DC|d [9] & (!\PWM_DC|LessThan0~2_combout  & !\PWM_DC|LessThan0~3_combout ))) ) ) )
+
+	.dataa(!\PWM_DC|count [9]),
+	.datab(!\PWM_DC|d [9]),
+	.datac(!\PWM_DC|LessThan0~2_combout ),
+	.datad(!\PWM_DC|LessThan0~3_combout ),
+	.datae(!\PWM_DC|count [8]),
+	.dataf(!\PWM_DC|d [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~4 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~4 .lut_mask = 64'hB2222222BBBBB222;
+defparam \PWM_DC|LessThan0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X78_Y10_N31
+dffeas \PWM_DC|pwm_out (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|LessThan0~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|pwm_out~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|pwm_out .is_wysiwyg = "true";
+defparam \PWM_DC|pwm_out .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X12_Y0_N18
+cyclonev_io_ibuf \SW[0]~input (
+	.i(SW[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[0]~input_o ));
+// synopsys translate_off
+defparam \SW[0]~input .bus_hold = "false";
+defparam \SW[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X16_Y0_N1
+cyclonev_io_ibuf \SW[1]~input (
+	.i(SW[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[1]~input_o ));
+// synopsys translate_off
+defparam \SW[1]~input .bus_hold = "false";
+defparam \SW[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X8_Y0_N35
+cyclonev_io_ibuf \SW[2]~input (
+	.i(SW[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[2]~input_o ));
+// synopsys translate_off
+defparam \SW[2]~input .bus_hold = "false";
+defparam \SW[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N52
+cyclonev_io_ibuf \SW[3]~input (
+	.i(SW[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[3]~input_o ));
+// synopsys translate_off
+defparam \SW[3]~input .bus_hold = "false";
+defparam \SW[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X2_Y0_N41
+cyclonev_io_ibuf \SW[4]~input (
+	.i(SW[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[4]~input_o ));
+// synopsys translate_off
+defparam \SW[4]~input .bus_hold = "false";
+defparam \SW[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X16_Y0_N18
+cyclonev_io_ibuf \SW[5]~input (
+	.i(SW[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[5]~input_o ));
+// synopsys translate_off
+defparam \SW[5]~input .bus_hold = "false";
+defparam \SW[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N35
+cyclonev_io_ibuf \SW[6]~input (
+	.i(SW[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[6]~input_o ));
+// synopsys translate_off
+defparam \SW[6]~input .bus_hold = "false";
+defparam \SW[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N1
+cyclonev_io_ibuf \SW[7]~input (
+	.i(SW[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[7]~input_o ));
+// synopsys translate_off
+defparam \SW[7]~input .bus_hold = "false";
+defparam \SW[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N18
+cyclonev_io_ibuf \SW[8]~input (
+	.i(SW[8]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[8]~input_o ));
+// synopsys translate_off
+defparam \SW[8]~input .bus_hold = "false";
+defparam \SW[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X2_Y0_N58
+cyclonev_io_ibuf \SW[9]~input (
+	.i(SW[9]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[9]~input_o ));
+// synopsys translate_off
+defparam \SW[9]~input .bus_hold = "false";
+defparam \SW[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X42_Y28_N0
+cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\~QUARTUS_CREATED_GND~I_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+endmodule
diff --git a/part_4/ex16/simulation/modelsim/ex16_top_modelsim.xrf b/part_4/ex16/simulation/modelsim/ex16_top_modelsim.xrf
new file mode 100755
index 0000000..5aee938
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/ex16_top_modelsim.xrf
@@ -0,0 +1,287 @@
+vendor_name = ModelSim
+source_file = 1, C:/New folder/ex16/ex16_top.sdc
+source_file = 1, C:/New folder/ex16/hex_to_7seg.v
+source_file = 1, C:/New folder/ex16/clktick_16.v
+source_file = 1, C:/New folder/ex16/spi2dac.v
+source_file = 1, C:/New folder/ex16/spi2adc.v
+source_file = 1, C:/New folder/ex16/pwm.v
+source_file = 1, C:/New folder/ex16/delay_ram.v
+source_file = 1, C:/New folder/ex16/ex16_top.v
+source_file = 1, C:/New folder/ex16/mult4.v
+source_file = 1, C:/New folder/ex16/db/ex16_top.cbx.xml
+design_name = ex16_top
+instance = comp, \HEX0[0]~output , HEX0[0]~output, ex16_top, 1
+instance = comp, \HEX0[1]~output , HEX0[1]~output, ex16_top, 1
+instance = comp, \HEX0[2]~output , HEX0[2]~output, ex16_top, 1
+instance = comp, \HEX0[3]~output , HEX0[3]~output, ex16_top, 1
+instance = comp, \HEX0[4]~output , HEX0[4]~output, ex16_top, 1
+instance = comp, \HEX0[5]~output , HEX0[5]~output, ex16_top, 1
+instance = comp, \HEX0[6]~output , HEX0[6]~output, ex16_top, 1
+instance = comp, \HEX1[0]~output , HEX1[0]~output, ex16_top, 1
+instance = comp, \HEX1[1]~output , HEX1[1]~output, ex16_top, 1
+instance = comp, \HEX1[2]~output , HEX1[2]~output, ex16_top, 1
+instance = comp, \HEX1[3]~output , HEX1[3]~output, ex16_top, 1
+instance = comp, \HEX1[4]~output , HEX1[4]~output, ex16_top, 1
+instance = comp, \HEX1[5]~output , HEX1[5]~output, ex16_top, 1
+instance = comp, \HEX1[6]~output , HEX1[6]~output, ex16_top, 1
+instance = comp, \HEX2[0]~output , HEX2[0]~output, ex16_top, 1
+instance = comp, \HEX2[1]~output , HEX2[1]~output, ex16_top, 1
+instance = comp, \HEX2[2]~output , HEX2[2]~output, ex16_top, 1
+instance = comp, \HEX2[3]~output , HEX2[3]~output, ex16_top, 1
+instance = comp, \HEX2[4]~output , HEX2[4]~output, ex16_top, 1
+instance = comp, \HEX2[5]~output , HEX2[5]~output, ex16_top, 1
+instance = comp, \HEX2[6]~output , HEX2[6]~output, ex16_top, 1
+instance = comp, \DAC_SDI~output , DAC_SDI~output, ex16_top, 1
+instance = comp, \DAC_SCK~output , DAC_SCK~output, ex16_top, 1
+instance = comp, \DAC_CS~output , DAC_CS~output, ex16_top, 1
+instance = comp, \DAC_LD~output , DAC_LD~output, ex16_top, 1
+instance = comp, \ADC_SDI~output , ADC_SDI~output, ex16_top, 1
+instance = comp, \ADC_SCK~output , ADC_SCK~output, ex16_top, 1
+instance = comp, \ADC_CS~output , ADC_CS~output, ex16_top, 1
+instance = comp, \PWM_OUT~output , PWM_OUT~output, ex16_top, 1
+instance = comp, \CLOCK_50~input , CLOCK_50~input, ex16_top, 1
+instance = comp, \SPI_ADC|clk_1MHz~0 , SPI_ADC|clk_1MHz~0, ex16_top, 1
+instance = comp, \SPI_ADC|clk_1MHz~feeder , SPI_ADC|clk_1MHz~feeder, ex16_top, 1
+instance = comp, \CLOCK_50~inputCLKENA0 , CLOCK_50~inputCLKENA0, ex16_top, 1
+instance = comp, \SPI_ADC|ctr[2] , SPI_ADC|ctr[2], ex16_top, 1
+instance = comp, \SPI_ADC|ctr~2 , SPI_ADC|ctr~2, ex16_top, 1
+instance = comp, \SPI_ADC|ctr[1] , SPI_ADC|ctr[1], ex16_top, 1
+instance = comp, \SPI_ADC|ctr~0 , SPI_ADC|ctr~0, ex16_top, 1
+instance = comp, \SPI_ADC|ctr[2]~DUPLICATE , SPI_ADC|ctr[2]~DUPLICATE, ex16_top, 1
+instance = comp, \SPI_ADC|Add0~1 , SPI_ADC|Add0~1, ex16_top, 1
+instance = comp, \SPI_ADC|ctr[3] , SPI_ADC|ctr[3], ex16_top, 1
+instance = comp, \SPI_ADC|Add0~0 , SPI_ADC|Add0~0, ex16_top, 1
+instance = comp, \SPI_ADC|ctr[4] , SPI_ADC|ctr[4], ex16_top, 1
+instance = comp, \SPI_ADC|ctr~1 , SPI_ADC|ctr~1, ex16_top, 1
+instance = comp, \SPI_ADC|ctr[0] , SPI_ADC|ctr[0], ex16_top, 1
+instance = comp, \SPI_ADC|ctr[4]~DUPLICATE , SPI_ADC|ctr[4]~DUPLICATE, ex16_top, 1
+instance = comp, \SPI_DAC|Equal0~0 , SPI_DAC|Equal0~0, ex16_top, 1
+instance = comp, \SPI_ADC|clk_1MHz , SPI_ADC|clk_1MHz, ex16_top, 1
+instance = comp, \ADC_SDO~input , ADC_SDO~input, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[0]~feeder , SPI_ADC|shift_reg[0]~feeder, ex16_top, 1
+instance = comp, \GEN_10K|Add0~9 , GEN_10K|Add0~9, ex16_top, 1
+instance = comp, \GEN_10K|count[0] , GEN_10K|count[0], ex16_top, 1
+instance = comp, \GEN_10K|Add0~13 , GEN_10K|Add0~13, ex16_top, 1
+instance = comp, \GEN_10K|count[1] , GEN_10K|count[1], ex16_top, 1
+instance = comp, \GEN_10K|Add0~17 , GEN_10K|Add0~17, ex16_top, 1
+instance = comp, \GEN_10K|count[2] , GEN_10K|count[2], ex16_top, 1
+instance = comp, \GEN_10K|Add0~33 , GEN_10K|Add0~33, ex16_top, 1
+instance = comp, \GEN_10K|count[3] , GEN_10K|count[3], ex16_top, 1
+instance = comp, \GEN_10K|Add0~37 , GEN_10K|Add0~37, ex16_top, 1
+instance = comp, \GEN_10K|count[4] , GEN_10K|count[4], ex16_top, 1
+instance = comp, \GEN_10K|Add0~41 , GEN_10K|Add0~41, ex16_top, 1
+instance = comp, \GEN_10K|count[5] , GEN_10K|count[5], ex16_top, 1
+instance = comp, \GEN_10K|Add0~45 , GEN_10K|Add0~45, ex16_top, 1
+instance = comp, \GEN_10K|count[6] , GEN_10K|count[6], ex16_top, 1
+instance = comp, \GEN_10K|Add0~21 , GEN_10K|Add0~21, ex16_top, 1
+instance = comp, \GEN_10K|count[7] , GEN_10K|count[7], ex16_top, 1
+instance = comp, \GEN_10K|Add0~25 , GEN_10K|Add0~25, ex16_top, 1
+instance = comp, \GEN_10K|count[8] , GEN_10K|count[8], ex16_top, 1
+instance = comp, \GEN_10K|Add0~1 , GEN_10K|Add0~1, ex16_top, 1
+instance = comp, \GEN_10K|count[9] , GEN_10K|count[9], ex16_top, 1
+instance = comp, \GEN_10K|Add0~5 , GEN_10K|Add0~5, ex16_top, 1
+instance = comp, \GEN_10K|count[10] , GEN_10K|count[10], ex16_top, 1
+instance = comp, \GEN_10K|Equal0~0 , GEN_10K|Equal0~0, ex16_top, 1
+instance = comp, \GEN_10K|Add0~49 , GEN_10K|Add0~49, ex16_top, 1
+instance = comp, \GEN_10K|count[11] , GEN_10K|count[11], ex16_top, 1
+instance = comp, \GEN_10K|Add0~29 , GEN_10K|Add0~29, ex16_top, 1
+instance = comp, \GEN_10K|count[12] , GEN_10K|count[12], ex16_top, 1
+instance = comp, \GEN_10K|Equal0~1 , GEN_10K|Equal0~1, ex16_top, 1
+instance = comp, \GEN_10K|count[14] , GEN_10K|count[14], ex16_top, 1
+instance = comp, \GEN_10K|Add0~53 , GEN_10K|Add0~53, ex16_top, 1
+instance = comp, \GEN_10K|count[13] , GEN_10K|count[13], ex16_top, 1
+instance = comp, \GEN_10K|Add0~61 , GEN_10K|Add0~61, ex16_top, 1
+instance = comp, \GEN_10K|count[14]~DUPLICATE , GEN_10K|count[14]~DUPLICATE, ex16_top, 1
+instance = comp, \GEN_10K|count[11]~DUPLICATE , GEN_10K|count[11]~DUPLICATE, ex16_top, 1
+instance = comp, \GEN_10K|Add0~57 , GEN_10K|Add0~57, ex16_top, 1
+instance = comp, \GEN_10K|count[15] , GEN_10K|count[15], ex16_top, 1
+instance = comp, \GEN_10K|Equal0~2 , GEN_10K|Equal0~2, ex16_top, 1
+instance = comp, \GEN_10K|Equal0~3 , GEN_10K|Equal0~3, ex16_top, 1
+instance = comp, \GEN_10K|tick~feeder , GEN_10K|tick~feeder, ex16_top, 1
+instance = comp, \GEN_10K|tick , GEN_10K|tick, ex16_top, 1
+instance = comp, \SPI_ADC|Selector2~0 , SPI_ADC|Selector2~0, ex16_top, 1
+instance = comp, \SPI_ADC|sr_state.WAIT_CSB_HIGH , SPI_ADC|sr_state.WAIT_CSB_HIGH, ex16_top, 1
+instance = comp, \SPI_ADC|Selector0~0 , SPI_ADC|Selector0~0, ex16_top, 1
+instance = comp, \SPI_ADC|sr_state.IDLE , SPI_ADC|sr_state.IDLE, ex16_top, 1
+instance = comp, \SPI_ADC|Selector1~0 , SPI_ADC|Selector1~0, ex16_top, 1
+instance = comp, \SPI_ADC|sr_state.WAIT_CSB_FALL , SPI_ADC|sr_state.WAIT_CSB_FALL, ex16_top, 1
+instance = comp, \SPI_ADC|adc_start~0 , SPI_ADC|adc_start~0, ex16_top, 1
+instance = comp, \SPI_ADC|adc_start , SPI_ADC|adc_start, ex16_top, 1
+instance = comp, \SPI_ADC|state[2]~2 , SPI_ADC|state[2]~2, ex16_top, 1
+instance = comp, \SPI_ADC|state[2] , SPI_ADC|state[2], ex16_top, 1
+instance = comp, \SPI_ADC|state[3]~3 , SPI_ADC|state[3]~3, ex16_top, 1
+instance = comp, \SPI_ADC|state[3] , SPI_ADC|state[3], ex16_top, 1
+instance = comp, \SPI_ADC|state~0 , SPI_ADC|state~0, ex16_top, 1
+instance = comp, \SPI_ADC|state[4] , SPI_ADC|state[4], ex16_top, 1
+instance = comp, \SPI_ADC|Selector5~0 , SPI_ADC|Selector5~0, ex16_top, 1
+instance = comp, \SPI_ADC|state[0] , SPI_ADC|state[0], ex16_top, 1
+instance = comp, \SPI_ADC|state[1]~1 , SPI_ADC|state[1]~1, ex16_top, 1
+instance = comp, \SPI_ADC|state[1] , SPI_ADC|state[1], ex16_top, 1
+instance = comp, \SPI_ADC|Selector4~0 , SPI_ADC|Selector4~0, ex16_top, 1
+instance = comp, \SPI_ADC|adc_cs , SPI_ADC|adc_cs, ex16_top, 1
+instance = comp, \SPI_ADC|WideOr0~0 , SPI_ADC|WideOr0~0, ex16_top, 1
+instance = comp, \SPI_ADC|shift_ena , SPI_ADC|shift_ena, ex16_top, 1
+instance = comp, \SPI_ADC|always3~0 , SPI_ADC|always3~0, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[0] , SPI_ADC|shift_reg[0], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[1] , SPI_ADC|shift_reg[1], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[2]~feeder , SPI_ADC|shift_reg[2]~feeder, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[2]~DUPLICATE , SPI_ADC|shift_reg[2]~DUPLICATE, ex16_top, 1
+instance = comp, \SPI_ADC|Decoder0~0 , SPI_ADC|Decoder0~0, ex16_top, 1
+instance = comp, \SPI_ADC|adc_done , SPI_ADC|adc_done, ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[2] , SPI_ADC|data_from_adc[2], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[2] , SPI_ADC|shift_reg[2], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[3] , SPI_ADC|shift_reg[3], ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[3] , SPI_ADC|data_from_adc[3], ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[0] , SPI_ADC|data_from_adc[0], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[1]~DUPLICATE , SPI_ADC|shift_reg[1]~DUPLICATE, ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[1] , SPI_ADC|data_from_adc[1], ex16_top, 1
+instance = comp, \SEG0|WideOr6~0 , SEG0|WideOr6~0, ex16_top, 1
+instance = comp, \SEG0|WideOr5~0 , SEG0|WideOr5~0, ex16_top, 1
+instance = comp, \SEG0|WideOr4~0 , SEG0|WideOr4~0, ex16_top, 1
+instance = comp, \SEG0|WideOr3~0 , SEG0|WideOr3~0, ex16_top, 1
+instance = comp, \SEG0|WideOr2~0 , SEG0|WideOr2~0, ex16_top, 1
+instance = comp, \SEG0|WideOr1~0 , SEG0|WideOr1~0, ex16_top, 1
+instance = comp, \SEG0|WideOr0~0 , SEG0|WideOr0~0, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[4] , SPI_ADC|shift_reg[4], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[5]~feeder , SPI_ADC|shift_reg[5]~feeder, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[5] , SPI_ADC|shift_reg[5], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[6]~feeder , SPI_ADC|shift_reg[6]~feeder, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[6] , SPI_ADC|shift_reg[6], ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[6] , SPI_ADC|data_from_adc[6], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[7]~feeder , SPI_ADC|shift_reg[7]~feeder, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[7] , SPI_ADC|shift_reg[7], ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[7] , SPI_ADC|data_from_adc[7], ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[5] , SPI_ADC|data_from_adc[5], ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[4] , SPI_ADC|data_from_adc[4], ex16_top, 1
+instance = comp, \SEG1|WideOr6~0 , SEG1|WideOr6~0, ex16_top, 1
+instance = comp, \SEG1|WideOr5~0 , SEG1|WideOr5~0, ex16_top, 1
+instance = comp, \SEG1|WideOr4~0 , SEG1|WideOr4~0, ex16_top, 1
+instance = comp, \SEG1|WideOr3~0 , SEG1|WideOr3~0, ex16_top, 1
+instance = comp, \SEG1|WideOr2~0 , SEG1|WideOr2~0, ex16_top, 1
+instance = comp, \SEG1|WideOr1~0 , SEG1|WideOr1~0, ex16_top, 1
+instance = comp, \SEG1|WideOr0~0 , SEG1|WideOr0~0, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[8] , SPI_ADC|shift_reg[8], ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[9]~feeder , SPI_ADC|shift_reg[9]~feeder, ex16_top, 1
+instance = comp, \SPI_ADC|shift_reg[9] , SPI_ADC|shift_reg[9], ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[9] , SPI_ADC|data_from_adc[9], ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[8]~feeder , SPI_ADC|data_from_adc[8]~feeder, ex16_top, 1
+instance = comp, \SPI_ADC|data_from_adc[8] , SPI_ADC|data_from_adc[8], ex16_top, 1
+instance = comp, \SEG2|Decoder0~0 , SEG2|Decoder0~0, ex16_top, 1
+instance = comp, \SEG2|Decoder0~1 , SEG2|Decoder0~1, ex16_top, 1
+instance = comp, \SEG2|Decoder0~2 , SEG2|Decoder0~2, ex16_top, 1
+instance = comp, \SPI_DAC|clk_1MHz~0 , SPI_DAC|clk_1MHz~0, ex16_top, 1
+instance = comp, \SPI_DAC|clk_1MHz~feeder , SPI_DAC|clk_1MHz~feeder, ex16_top, 1
+instance = comp, \SPI_DAC|clk_1MHz , SPI_DAC|clk_1MHz, ex16_top, 1
+instance = comp, \SPI_DAC|sr_state.IDLE , SPI_DAC|sr_state.IDLE, ex16_top, 1
+instance = comp, \SPI_DAC|Selector2~0 , SPI_DAC|Selector2~0, ex16_top, 1
+instance = comp, \SPI_DAC|sr_state.WAIT_CSB_HIGH , SPI_DAC|sr_state.WAIT_CSB_HIGH, ex16_top, 1
+instance = comp, \SPI_DAC|Selector0~0 , SPI_DAC|Selector0~0, ex16_top, 1
+instance = comp, \SPI_DAC|sr_state.IDLE~DUPLICATE , SPI_DAC|sr_state.IDLE~DUPLICATE, ex16_top, 1
+instance = comp, \SPI_DAC|Selector1~0 , SPI_DAC|Selector1~0, ex16_top, 1
+instance = comp, \SPI_DAC|sr_state.WAIT_CSB_FALL , SPI_DAC|sr_state.WAIT_CSB_FALL, ex16_top, 1
+instance = comp, \SPI_DAC|dac_start~0 , SPI_DAC|dac_start~0, ex16_top, 1
+instance = comp, \SPI_DAC|dac_start , SPI_DAC|dac_start, ex16_top, 1
+instance = comp, \SPI_DAC|Selector5~0 , SPI_DAC|Selector5~0, ex16_top, 1
+instance = comp, \SPI_DAC|state[3] , SPI_DAC|state[3], ex16_top, 1
+instance = comp, \SPI_DAC|Selector4~0 , SPI_DAC|Selector4~0, ex16_top, 1
+instance = comp, \SPI_DAC|state[4] , SPI_DAC|state[4], ex16_top, 1
+instance = comp, \SPI_DAC|Selector8~0 , SPI_DAC|Selector8~0, ex16_top, 1
+instance = comp, \SPI_DAC|state[0] , SPI_DAC|state[0], ex16_top, 1
+instance = comp, \SPI_DAC|Selector7~0 , SPI_DAC|Selector7~0, ex16_top, 1
+instance = comp, \SPI_DAC|state[1] , SPI_DAC|state[1], ex16_top, 1
+instance = comp, \SPI_DAC|Selector6~0 , SPI_DAC|Selector6~0, ex16_top, 1
+instance = comp, \SPI_DAC|state[2] , SPI_DAC|state[2], ex16_top, 1
+instance = comp, \SPI_DAC|Selector9~0 , SPI_DAC|Selector9~0, ex16_top, 1
+instance = comp, \SPI_DAC|dac_cs , SPI_DAC|dac_cs, ex16_top, 1
+instance = comp, \ALLPASS|Add0~17 , ALLPASS|Add0~17, ex16_top, 1
+instance = comp, \ALLPASS|Add0~13 , ALLPASS|Add0~13, ex16_top, 1
+instance = comp, \ALLPASS|Add0~9 , ALLPASS|Add0~9, ex16_top, 1
+instance = comp, \ALLPASS|Add0~29 , ALLPASS|Add0~29, ex16_top, 1
+instance = comp, \ALLPASS|Add0~25 , ALLPASS|Add0~25, ex16_top, 1
+instance = comp, \ALLPASS|Add0~21 , ALLPASS|Add0~21, ex16_top, 1
+instance = comp, \ALLPASS|data_out[7] , ALLPASS|data_out[7], ex16_top, 1
+instance = comp, \ALLPASS|data_out[6] , ALLPASS|data_out[6], ex16_top, 1
+instance = comp, \ALLPASS|data_out[3] , ALLPASS|data_out[3], ex16_top, 1
+instance = comp, \ALLPASS|data_out[2] , ALLPASS|data_out[2], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~11 , SPI_DAC|shift_reg~11, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[4] , SPI_DAC|shift_reg[4], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~10 , SPI_DAC|shift_reg~10, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[5] , SPI_DAC|shift_reg[5], ex16_top, 1
+instance = comp, \ALLPASS|data_out[4] , ALLPASS|data_out[4], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~9 , SPI_DAC|shift_reg~9, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[6] , SPI_DAC|shift_reg[6], ex16_top, 1
+instance = comp, \ALLPASS|data_out[5] , ALLPASS|data_out[5], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~8 , SPI_DAC|shift_reg~8, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[7] , SPI_DAC|shift_reg[7], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~7 , SPI_DAC|shift_reg~7, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[8] , SPI_DAC|shift_reg[8], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~6 , SPI_DAC|shift_reg~6, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[9] , SPI_DAC|shift_reg[9], ex16_top, 1
+instance = comp, \ALLPASS|Add0~5 , ALLPASS|Add0~5, ex16_top, 1
+instance = comp, \ALLPASS|data_out[8] , ALLPASS|data_out[8], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~5 , SPI_DAC|shift_reg~5, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[10] , SPI_DAC|shift_reg[10], ex16_top, 1
+instance = comp, \ALLPASS|Add0~1 , ALLPASS|Add0~1, ex16_top, 1
+instance = comp, \ALLPASS|data_out[9]~0 , ALLPASS|data_out[9]~0, ex16_top, 1
+instance = comp, \ALLPASS|data_out[9] , ALLPASS|data_out[9], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~4 , SPI_DAC|shift_reg~4, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[11] , SPI_DAC|shift_reg[11], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~3 , SPI_DAC|shift_reg~3, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[12] , SPI_DAC|shift_reg[12], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~2 , SPI_DAC|shift_reg~2, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[13] , SPI_DAC|shift_reg[13], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~1 , SPI_DAC|shift_reg~1, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[14] , SPI_DAC|shift_reg[14], ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg~0 , SPI_DAC|shift_reg~0, ex16_top, 1
+instance = comp, \SPI_DAC|shift_reg[15] , SPI_DAC|shift_reg[15], ex16_top, 1
+instance = comp, \SPI_DAC|dac_sck , SPI_DAC|dac_sck, ex16_top, 1
+instance = comp, \SPI_DAC|Equal2~0 , SPI_DAC|Equal2~0, ex16_top, 1
+instance = comp, \SPI_DAC|dac_ld , SPI_DAC|dac_ld, ex16_top, 1
+instance = comp, \SPI_ADC|Selector6~0 , SPI_ADC|Selector6~0, ex16_top, 1
+instance = comp, \SPI_ADC|adc_din , SPI_ADC|adc_din, ex16_top, 1
+instance = comp, \SPI_ADC|adc_sck , SPI_ADC|adc_sck, ex16_top, 1
+instance = comp, \PWM_DC|count[0]~0 , PWM_DC|count[0]~0, ex16_top, 1
+instance = comp, \PWM_DC|count[0] , PWM_DC|count[0], ex16_top, 1
+instance = comp, \PWM_DC|Add0~21 , PWM_DC|Add0~21, ex16_top, 1
+instance = comp, \PWM_DC|count[1] , PWM_DC|count[1], ex16_top, 1
+instance = comp, \PWM_DC|Add0~17 , PWM_DC|Add0~17, ex16_top, 1
+instance = comp, \PWM_DC|count[2] , PWM_DC|count[2], ex16_top, 1
+instance = comp, \PWM_DC|Add0~13 , PWM_DC|Add0~13, ex16_top, 1
+instance = comp, \PWM_DC|count[3] , PWM_DC|count[3], ex16_top, 1
+instance = comp, \PWM_DC|Add0~9 , PWM_DC|Add0~9, ex16_top, 1
+instance = comp, \PWM_DC|count[4] , PWM_DC|count[4], ex16_top, 1
+instance = comp, \PWM_DC|Add0~33 , PWM_DC|Add0~33, ex16_top, 1
+instance = comp, \PWM_DC|count[5] , PWM_DC|count[5], ex16_top, 1
+instance = comp, \PWM_DC|Add0~29 , PWM_DC|Add0~29, ex16_top, 1
+instance = comp, \PWM_DC|count[6] , PWM_DC|count[6], ex16_top, 1
+instance = comp, \PWM_DC|Add0~25 , PWM_DC|Add0~25, ex16_top, 1
+instance = comp, \PWM_DC|count[7] , PWM_DC|count[7], ex16_top, 1
+instance = comp, \PWM_DC|Add0~5 , PWM_DC|Add0~5, ex16_top, 1
+instance = comp, \PWM_DC|count[8] , PWM_DC|count[8], ex16_top, 1
+instance = comp, \PWM_DC|Add0~1 , PWM_DC|Add0~1, ex16_top, 1
+instance = comp, \PWM_DC|count[9] , PWM_DC|count[9], ex16_top, 1
+instance = comp, \PWM_DC|d[9] , PWM_DC|d[9], ex16_top, 1
+instance = comp, \PWM_DC|d[2] , PWM_DC|d[2], ex16_top, 1
+instance = comp, \PWM_DC|LessThan0~0 , PWM_DC|LessThan0~0, ex16_top, 1
+instance = comp, \PWM_DC|d[7] , PWM_DC|d[7], ex16_top, 1
+instance = comp, \PWM_DC|d[6] , PWM_DC|d[6], ex16_top, 1
+instance = comp, \PWM_DC|d[5] , PWM_DC|d[5], ex16_top, 1
+instance = comp, \PWM_DC|LessThan0~1 , PWM_DC|LessThan0~1, ex16_top, 1
+instance = comp, \PWM_DC|d[3] , PWM_DC|d[3], ex16_top, 1
+instance = comp, \PWM_DC|d[4] , PWM_DC|d[4], ex16_top, 1
+instance = comp, \PWM_DC|LessThan0~2 , PWM_DC|LessThan0~2, ex16_top, 1
+instance = comp, \PWM_DC|LessThan0~3 , PWM_DC|LessThan0~3, ex16_top, 1
+instance = comp, \PWM_DC|d[8] , PWM_DC|d[8], ex16_top, 1
+instance = comp, \PWM_DC|LessThan0~4 , PWM_DC|LessThan0~4, ex16_top, 1
+instance = comp, \PWM_DC|pwm_out , PWM_DC|pwm_out, ex16_top, 1
+instance = comp, \SW[0]~input , SW[0]~input, ex16_top, 1
+instance = comp, \SW[1]~input , SW[1]~input, ex16_top, 1
+instance = comp, \SW[2]~input , SW[2]~input, ex16_top, 1
+instance = comp, \SW[3]~input , SW[3]~input, ex16_top, 1
+instance = comp, \SW[4]~input , SW[4]~input, ex16_top, 1
+instance = comp, \SW[5]~input , SW[5]~input, ex16_top, 1
+instance = comp, \SW[6]~input , SW[6]~input, ex16_top, 1
+instance = comp, \SW[7]~input , SW[7]~input, ex16_top, 1
+instance = comp, \SW[8]~input , SW[8]~input, ex16_top, 1
+instance = comp, \SW[9]~input , SW[9]~input, ex16_top, 1
+instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, ex16_top, 1
diff --git a/part_4/ex16/simulation/modelsim/init.do b/part_4/ex16/simulation/modelsim/init.do
new file mode 100755
index 0000000..c39709a
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/init.do
@@ -0,0 +1,20 @@
+add wave -position end  sim:/top/CLOCK_50
+add wave -position end  sim:/top/clock_25
+add wave -position end  sim:/top/tone_1k
+add wave -position end  sim:/top/ld_pulse
+add wave -position end  sim:/top/reset
+add wave -position end  sim:/top/DAC_SDI
+add wave -position end  sim:/top/DAC_SCK
+add wave -position end  sim:/top/DAC_CS
+add wave -position end  sim:/top/DAC_LD
+add wave -position end  sim:/top/BUTTON0
+add wave -position end -hexadecimal sim:/top/mux_out
+add wave -position end -hexadecimal sim:/top/SPI_1/state
+add wave -position end  sim:/top/SPI_1/sck_ena
+add wave -position end  sim:/top/SPI_1/clk_half
+force CLOCK_50  1 0, 0 {10 ns} -r {20 ns}
+alias ck "run 20ns"
+force BUTTON0 0
+ck
+force BUTTON0 1
+ck
diff --git a/part_4/ex16/simulation/modelsim/init_adc.do b/part_4/ex16/simulation/modelsim/init_adc.do
new file mode 100755
index 0000000..1269f00
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/init_adc.do
@@ -0,0 +1,23 @@
+add wave sysclk
+add wave clk_1MHz
+add wave start
+add wave data_from_adc
+add wave data_valid
+add wave -hexadecimal data_out
+add wave adc_cs
+add wave adc_sck
+add wave adc_done
+add wave adc_din
+add wave -hexadecimal shift_reg
+add wave -hexadecimal state
+add wave shift_ena 
+force sysclk 1 0, 0 {10 ns} -r 20 ns
+force start 0
+run 200ns
+force start 1
+run 200ns
+force start 0
+force data_from_adc 0 @ 1us, 1 @ 6us, 0 @ 8us, 1 @ 10us, 0 @ 13us, 1 @ 15us
+
+run 20us
+
diff --git a/part_4/ex16/simulation/modelsim/init_cal.do b/part_4/ex16/simulation/modelsim/init_cal.do
new file mode 100755
index 0000000..a6d14b9
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/init_cal.do
@@ -0,0 +1,17 @@
+add wave -position end  sim:/top/CLOCK_50
+add wave -position end  sim:/top/clk_10k
+add wave -position end  sim:/top/ld_pulse
+add wave -position end -hexadecimal sim:/top/SW
+add wave -position end -hexadecimal sim:/top/data
+add wave -position end  sim:/top/DAC_SDI
+add wave -position end  sim:/top/DAC_SCK
+add wave -position end  sim:/top/DAC_CS
+add wave -position end  sim:/top/DAC_LD
+add wave -position end  sim:/top/ADC_SDI
+add wave -position end  sim:/top/ADC_SCK
+add wave -position end  sim:/top/ADC_CS
+add wave -position end  sim:/top/ADC_SDO
+force CLOCK_50 1 0, 0 10ns -r 20ns
+force SW 10'h20f
+force ADC_SDO 1
+run 400us
diff --git a/part_4/ex16/simulation/modelsim/init_spi.do b/part_4/ex16/simulation/modelsim/init_spi.do
new file mode 100755
index 0000000..b99ff7a
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/init_spi.do
@@ -0,0 +1,25 @@
+add wave -position end  sim:/spi2dac/sysclk
+add wave -position end  sim:/spi2dac/div2
+add wave -position end  sim:/spi2dac/div4
+add wave -position end  sim:/spi2dac/status_busy
+add wave -position end -hexadecimal sim:/spi2dac/data_in
+add wave -position end  sim:/spi2dac/ld
+add wave -position end -hexadecimal  sim:/spi2dac/state
+add wave -position end  sim:/spi2dac/sck_ena
+add wave -position end  sim:/spi2dac/dac_ld
+add wave -position end -hexadecimal  sim:/spi2dac/shift_reg
+add wave -position end  sim:/spi2dac/spi_sdo
+add wave -position end  sim:/spi2dac/spi_cs
+add wave -position end  sim:/spi2dac/spi_sck
+add wave -position end  sim:/spi2dac/spi_ld
+add wave -position end  sim:/spi2dac/rs_state
+force -freeze sim:/spi2dac/sysclk 1 0, 0 {10 ns} -r 20 ns
+run 20ns
+force data_in 10'h2c3
+force ld 0
+run 20ns
+force ld 1
+run 20ns
+force ld 0
+run 20ns
+ 
+\ No newline at end of file
diff --git a/part_4/ex16/simulation/modelsim/modelsim.ini b/part_4/ex16/simulation/modelsim/modelsim.ini
new file mode 100755
index 0000000..3912feb
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/modelsim.ini
@@ -0,0 +1,324 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+;
+; Verilog Section
+;
+
+work = rtl_work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
diff --git a/part_4/ex16/simulation/modelsim/msim_transcript b/part_4/ex16/simulation/modelsim/msim_transcript
new file mode 100755
index 0000000..7396617
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/msim_transcript
@@ -0,0 +1,23 @@
+# Reading C:/altera/13.1/modelsim_ase/tcl/vsim/pref.tcl 
+# do top_run_msim_rtl_verilog.do 
+# if {[file exists rtl_work]} {
+# 	vdel -lib rtl_work -all
+# }
+# vlib rtl_work
+# vmap work rtl_work
+# Copying C:\altera\13.1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
+# Modifying modelsim.ini
+# ** Warning: Copied C:\altera\13.1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
+#          Updated modelsim.ini.
+# 
+# vlog -vlog01compat -work work +incdir+Z:/Dropbox/_My\ Documents/E2\ Digital/adc_dac {Z:/Dropbox/_My Documents/E2 Digital/adc_dac/spi2adc.v}
+# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
+# -- Compiling module spi2adc
+# 
+# Top level modules:
+# 	spi2adc
+# 
+vsim work.spi2adc
+# vsim work.spi2adc 
+# Loading work.spi2adc
+do init_adc.do
diff --git a/part_4/ex16/simulation/modelsim/rtl_work/_info b/part_4/ex16/simulation/modelsim/rtl_work/_info
new file mode 100755
index 0000000..818e9c7
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/rtl_work/_info
@@ -0,0 +1,25 @@
+m255
+K3
+13
+cModel Technology
+Z0 dZ:\Dropbox\_My Documents\E2 Digital\adc_dac\simulation\modelsim
+vspi2adc
+!i10b 1
+!s100 <>meYdBmJ`WBeDQ4[DA]]2
+IVB=R1?17XcaCoSADk3Gf?3
+V9a1c[dMnkCVEffcZibC4n0
+Z1 dZ:\Dropbox\_My Documents\E2 Digital\adc_dac\simulation\modelsim
+w1390659441
+8Z:/Dropbox/_My Documents/E2 Digital/adc_dac/spi2adc.v
+FZ:/Dropbox/_My Documents/E2 Digital/adc_dac/spi2adc.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1390659465.905000
+!s107 Z:/Dropbox/_My Documents/E2 Digital/adc_dac/spi2adc.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+Z:/Dropbox/_My Documents/E2 Digital/adc_dac|Z:/Dropbox/_My Documents/E2 Digital/adc_dac/spi2adc.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+Z:/Dropbox/_My Documents/E2 Digital/adc_dac} -O0
diff --git a/part_4/ex16/simulation/modelsim/rtl_work/_vmake b/part_4/ex16/simulation/modelsim/rtl_work/_vmake
new file mode 100755
index 0000000..2f7e729
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/rtl_work/_vmake
@@ -0,0 +1,3 @@
+m255
+K3
+cModel Technology
diff --git a/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.dat b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.dat
new file mode 100755
index 0000000..b72ab30
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.dat
diff --git a/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.dbs b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.dbs
new file mode 100755
index 0000000..ca76212
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.dbs
diff --git a/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.vhd b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.vhd
new file mode 100755
index 0000000..825d264
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/_primary.vhd
@@ -0,0 +1,31 @@
+library verilog;
+use verilog.vl_types.all;
+entity spi2adc is
+    generic(
+        SGL             : vl_logic := Hi1;
+        CH              : vl_logic := Hi1;
+        MSBF            : vl_logic := Hi1;
+        TIME_CONSTANT   : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+        IDLE            : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+        WAIT_CSB_FALL   : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+        WAIT_CSB_HIGH   : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+    );
+    port(
+        sysclk          : in     vl_logic;
+        start           : in     vl_logic;
+        data_from_adc   : in     vl_logic;
+        data_out        : out    vl_logic_vector(9 downto 0);
+        data_valid      : out    vl_logic;
+        sdata_to_adc    : out    vl_logic;
+        adc_cs          : out    vl_logic;
+        adc_sck         : out    vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of SGL : constant is 1;
+    attribute mti_svvh_generic_type of CH : constant is 1;
+    attribute mti_svvh_generic_type of MSBF : constant is 1;
+    attribute mti_svvh_generic_type of TIME_CONSTANT : constant is 1;
+    attribute mti_svvh_generic_type of IDLE : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+    attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2adc;
diff --git a/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/verilog.prw b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/verilog.prw
new file mode 100755
index 0000000..9b33b2f
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/verilog.prw
diff --git a/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/verilog.psm b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/verilog.psm
new file mode 100755
index 0000000..5ffba0e
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/rtl_work/spi2adc/verilog.psm
diff --git a/part_4/ex16/simulation/modelsim/top.sft b/part_4/ex16/simulation/modelsim/top.sft
new file mode 100755
index 0000000..f324fea
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top.sft
@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (Verilog)"
diff --git a/part_4/ex16/simulation/modelsim/top.vo b/part_4/ex16/simulation/modelsim/top.vo
new file mode 100755
index 0000000..dba0346
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top.vo
@@ -0,0 +1,10816 @@
+// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, the Altera Quartus Prime License Agreement,
+// the Altera MegaCore Function License Agreement, or other 
+// applicable license agreement, including, without limitation, 
+// that your use is for the sole purpose of programming logic 
+// devices manufactured by Altera and sold by Altera or its 
+// authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition"
+
+// DATE "10/30/2016 16:43:00"
+
+// 
+// Device: Altera 5CSEMA5F31C6 Package FBGA896
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module top (
+	CLOCK_50,
+	SW,
+	HEX0,
+	HEX1,
+	HEX2,
+	HEX3,
+	DAC_SDI,
+	DAC_SCK,
+	DAC_CS,
+	DAC_LD,
+	ADC_SDI,
+	ADC_SCK,
+	ADC_CS,
+	ADC_SDO,
+	PWM_OUT);
+input 	CLOCK_50;
+input 	[9:0] SW;
+output 	[6:0] HEX0;
+output 	[6:0] HEX1;
+output 	[6:0] HEX2;
+output 	[6:0] HEX3;
+output 	DAC_SDI;
+output 	DAC_SCK;
+output 	DAC_CS;
+output 	DAC_LD;
+output 	ADC_SDI;
+output 	ADC_SCK;
+output 	ADC_CS;
+input 	ADC_SDO;
+output 	PWM_OUT;
+
+// Design Ports Information
+// HEX0[0]	=>  Location: PIN_AE26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[1]	=>  Location: PIN_AE27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[2]	=>  Location: PIN_AE28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[3]	=>  Location: PIN_AG27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[4]	=>  Location: PIN_AF28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[5]	=>  Location: PIN_AG28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX0[6]	=>  Location: PIN_AH28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[0]	=>  Location: PIN_AJ29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[1]	=>  Location: PIN_AH29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[2]	=>  Location: PIN_AH30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[3]	=>  Location: PIN_AG30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[4]	=>  Location: PIN_AF29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[5]	=>  Location: PIN_AF30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX1[6]	=>  Location: PIN_AD27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[0]	=>  Location: PIN_AB23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[1]	=>  Location: PIN_AE29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[2]	=>  Location: PIN_AD29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[3]	=>  Location: PIN_AC28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[4]	=>  Location: PIN_AD30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[5]	=>  Location: PIN_AC29,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX2[6]	=>  Location: PIN_AC30,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[0]	=>  Location: PIN_AD26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[1]	=>  Location: PIN_AC27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[2]	=>  Location: PIN_AD25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[3]	=>  Location: PIN_AC25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[4]	=>  Location: PIN_AB28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[5]	=>  Location: PIN_AB25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// HEX3[6]	=>  Location: PIN_AB22,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_SDI	=>  Location: PIN_AG18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_SCK	=>  Location: PIN_AF20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_CS	=>  Location: PIN_AD20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// DAC_LD	=>  Location: PIN_AK21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_SDI	=>  Location: PIN_AG21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_SCK	=>  Location: PIN_AF21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// ADC_CS	=>  Location: PIN_AG20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// PWM_OUT	=>  Location: PIN_AJ20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 16mA
+// SW[8]	=>  Location: PIN_AD10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// CLOCK_50	=>  Location: PIN_AF14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[9]	=>  Location: PIN_AE12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[6]	=>  Location: PIN_AE11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[5]	=>  Location: PIN_AD12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[4]	=>  Location: PIN_AD11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[3]	=>  Location: PIN_AF10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[2]	=>  Location: PIN_AF9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[1]	=>  Location: PIN_AC12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[0]	=>  Location: PIN_AB12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[7]	=>  Location: PIN_AC9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ADC_SDO	=>  Location: PIN_AJ21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+wire \~QUARTUS_CREATED_GND~I_combout ;
+wire \SW[4]~input_o ;
+wire \SW[5]~input_o ;
+wire \SW[6]~input_o ;
+wire \SW[1]~input_o ;
+wire \SW[0]~input_o ;
+wire \SW[2]~input_o ;
+wire \SW[3]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][12]~2_combout ;
+wire \SW[7]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][11]~1_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][9]~5_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][4]~6_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ;
+wire \SW[8]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][14]~4_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][13]~3_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ;
+wire \BCD_CONVERT|A9|WideOr2~0_combout ;
+wire \BCD_CONVERT|A9|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ;
+wire \BCD_CONVERT|A9|WideOr3~0_combout ;
+wire \BCD_CONVERT|A12|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ;
+wire \BCD_CONVERT|A12|WideOr2~0_combout ;
+wire \BCD_CONVERT|A12|WideOr3~0_combout ;
+wire \BCD_CONVERT|A15|WideOr1~0_combout ;
+wire \BCD_CONVERT|A15|WideOr2~0_combout ;
+wire \BCD_CONVERT|A15|WideOr3~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ;
+wire \BCD_CONVERT|A18|WideOr2~0_combout ;
+wire \BCD_CONVERT|A18|WideOr1~0_combout ;
+wire \BCD_CONVERT|A18|WideOr3~0_combout ;
+wire \BCD_CONVERT|A21|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ;
+wire \BCD_CONVERT|A21|WideOr3~0_combout ;
+wire \BCD_CONVERT|A21|WideOr2~0_combout ;
+wire \BCD_CONVERT|A25|WideOr2~0_combout ;
+wire \BCD_CONVERT|A25|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ;
+wire \BCD_CONVERT|A25|WideOr3~0_combout ;
+wire \SEG0|WideOr6~0_combout ;
+wire \SEG0|WideOr5~0_combout ;
+wire \SEG0|WideOr4~0_combout ;
+wire \SEG0|WideOr3~0_combout ;
+wire \SEG0|WideOr2~0_combout ;
+wire \SEG0|WideOr1~0_combout ;
+wire \SEG0|WideOr0~0_combout ;
+wire \BCD_CONVERT|A25|WideOr0~0_combout ;
+wire \BCD_CONVERT|A17|WideOr1~0_combout ;
+wire \BCD_CONVERT|A17|WideOr3~0_combout ;
+wire \BCD_CONVERT|A17|WideOr2~0_combout ;
+wire \BCD_CONVERT|A18|WideOr0~0_combout ;
+wire \BCD_CONVERT|A20|WideOr2~0_combout ;
+wire \BCD_CONVERT|A20|WideOr3~0_combout ;
+wire \BCD_CONVERT|A20|WideOr1~0_combout ;
+wire \BCD_CONVERT|A21|WideOr0~0_combout ;
+wire \BCD_CONVERT|A24|WideOr3~0_combout ;
+wire \BCD_CONVERT|A24|WideOr1~0_combout ;
+wire \BCD_CONVERT|A24|WideOr2~0_combout ;
+wire \SEG1|WideOr6~0_combout ;
+wire \SEG1|WideOr5~0_combout ;
+wire \SEG1|WideOr4~0_combout ;
+wire \SEG1|WideOr3~0_combout ;
+wire \SEG1|WideOr2~0_combout ;
+wire \SEG1|WideOr1~0_combout ;
+wire \SEG1|WideOr0~0_combout ;
+wire \BCD_CONVERT|A24|WideOr0~0_combout ;
+wire \BCD_CONVERT|A20|WideOr0~0_combout ;
+wire \BCD_CONVERT|A17|WideOr0~0_combout ;
+wire \BCD_CONVERT|A7|WideOr0~0_combout ;
+wire \BCD_CONVERT|A9|WideOr0~0_combout ;
+wire \BCD_CONVERT|A12|WideOr0~0_combout ;
+wire \BCD_CONVERT|A14|WideOr0~0_combout ;
+wire \SEG2|Decoder0~1_combout ;
+wire \SEG2|Decoder0~0_combout ;
+wire \SEG2|WideOr6~combout ;
+wire \SEG2|Decoder0~2_combout ;
+wire \SEG2|WideOr5~combout ;
+wire \SEG2|Decoder0~3_combout ;
+wire \SEG2|Decoder0~4_combout ;
+wire \SEG2|Decoder0~5_combout ;
+wire \SEG2|WideOr2~0_combout ;
+wire \SEG2|Decoder0~6_combout ;
+wire \SEG2|WideOr2~combout ;
+wire \SEG2|WideOr1~combout ;
+wire \SEG2|WideOr0~combout ;
+wire \BCD_CONVERT|A23|WideOr0~0_combout ;
+wire \CLOCK_50~input_o ;
+wire \SPI_DAC|clk_1MHz~0_combout ;
+wire \CLOCK_50~inputCLKENA0_outclk ;
+wire \SPI_ADC|Add0~0_combout ;
+wire \SPI_ADC|ctr[4]~DUPLICATE_q ;
+wire \SPI_ADC|ctr~2_combout ;
+wire \SPI_ADC|ctr[1]~DUPLICATE_q ;
+wire \SPI_ADC|ctr~1_combout ;
+wire \SPI_ADC|ctr[0]~DUPLICATE_q ;
+wire \SPI_ADC|ctr~0_combout ;
+wire \SPI_ADC|ctr[2]~DUPLICATE_q ;
+wire \SPI_ADC|Add0~1_combout ;
+wire \SPI_ADC|ctr[3]~DUPLICATE_q ;
+wire \SPI_DAC|Equal0~0_combout ;
+wire \SPI_DAC|clk_1MHz~q ;
+wire \SPI_DAC|Selector6~0_combout ;
+wire \SPI_DAC|Selector5~0_combout ;
+wire \SPI_DAC|state[3]~DUPLICATE_q ;
+wire \SPI_DAC|Selector4~0_combout ;
+wire \SPI_DAC|state[4]~feeder_combout ;
+wire \SPI_DAC|Selector8~0_combout ;
+wire \SPI_DAC|Selector7~0_combout ;
+wire \SPI_DAC|Selector9~0_combout ;
+wire \SPI_DAC|dac_cs~q ;
+wire \GEN_10K|Add0~41_sumout ;
+wire \GEN_10K|Add0~42 ;
+wire \GEN_10K|Add0~45_sumout ;
+wire \GEN_10K|Add0~46 ;
+wire \GEN_10K|Add0~77_sumout ;
+wire \GEN_10K|Add0~54 ;
+wire \GEN_10K|Add0~57_sumout ;
+wire \GEN_10K|Add0~58 ;
+wire \GEN_10K|Add0~21_sumout ;
+wire \GEN_10K|Add0~22 ;
+wire \GEN_10K|Add0~25_sumout ;
+wire \GEN_10K|Add0~26 ;
+wire \GEN_10K|Add0~61_sumout ;
+wire \GEN_10K|Add0~62 ;
+wire \GEN_10K|Add0~29_sumout ;
+wire \GEN_10K|Add0~30 ;
+wire \GEN_10K|Add0~33_sumout ;
+wire \GEN_10K|Add0~34 ;
+wire \GEN_10K|Add0~37_sumout ;
+wire \GEN_10K|Add0~38 ;
+wire \GEN_10K|Add0~5_sumout ;
+wire \GEN_10K|Add0~6 ;
+wire \GEN_10K|Add0~9_sumout ;
+wire \GEN_10K|Add0~10 ;
+wire \GEN_10K|Add0~13_sumout ;
+wire \GEN_10K|Add0~14 ;
+wire \GEN_10K|Add0~65_sumout ;
+wire \GEN_10K|Add0~66 ;
+wire \GEN_10K|Add0~69_sumout ;
+wire \GEN_10K|Equal0~3_combout ;
+wire \GEN_10K|Add0~70 ;
+wire \GEN_10K|Add0~1_sumout ;
+wire \GEN_10K|Equal0~0_combout ;
+wire \GEN_10K|Equal0~1_combout ;
+wire \GEN_10K|Equal0~4_combout ;
+wire \GEN_10K|Add0~78 ;
+wire \GEN_10K|Add0~81_sumout ;
+wire \GEN_10K|Add0~82 ;
+wire \GEN_10K|Add0~73_sumout ;
+wire \GEN_10K|Add0~74 ;
+wire \GEN_10K|Add0~17_sumout ;
+wire \GEN_10K|Add0~18 ;
+wire \GEN_10K|Add0~49_sumout ;
+wire \GEN_10K|Add0~50 ;
+wire \GEN_10K|Add0~53_sumout ;
+wire \GEN_10K|Equal0~2_combout ;
+wire \GEN_10K|clkout~q ;
+wire \GEN_10K|clkout~0_combout ;
+wire \GEN_10K|clkout~DUPLICATE_q ;
+wire \PULSE|state.IDLE~q ;
+wire \PULSE|pulse~1_combout ;
+wire \PULSE|pulse~q ;
+wire \SPI_DAC|Selector2~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_DAC|Selector0~0_combout ;
+wire \SPI_DAC|sr_state.IDLE~q ;
+wire \SPI_DAC|Selector1~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_DAC|dac_start~0_combout ;
+wire \SPI_DAC|dac_start~q ;
+wire \SPI_ADC|clk_1MHz~0_combout ;
+wire \SPI_ADC|clk_1MHz~q ;
+wire \SPI_ADC|state[1]~0_combout ;
+wire \SPI_ADC|state[2]~2_combout ;
+wire \SPI_ADC|Selector2~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_ADC|Selector0~0_combout ;
+wire \SPI_ADC|sr_state.IDLE~q ;
+wire \SPI_ADC|Selector1~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_ADC|adc_start~0_combout ;
+wire \SPI_ADC|adc_start~q ;
+wire \SPI_ADC|Selector5~0_combout ;
+wire \SPI_ADC|state[3]~3_combout ;
+wire \SPI_ADC|state~1_combout ;
+wire \SPI_ADC|adc_start~DUPLICATE_q ;
+wire \SPI_ADC|Selector4~0_combout ;
+wire \SPI_ADC|adc_cs~q ;
+wire \ECHO|PULSE2|state.IDLE~0_combout ;
+wire \ECHO|PULSE2|state.IDLE~q ;
+wire \ECHO|PULSE2|pulse~1_combout ;
+wire \ECHO|PULSE2|pulse~q ;
+wire \ECHO|ctr[0]~0_combout ;
+wire \ECHO|Add1~1_sumout ;
+wire \ECHO|Add1~2 ;
+wire \ECHO|Add1~5_sumout ;
+wire \ECHO|ctr[2]~DUPLICATE_q ;
+wire \ECHO|Add1~6 ;
+wire \ECHO|Add1~9_sumout ;
+wire \ECHO|Add1~10 ;
+wire \ECHO|Add1~13_sumout ;
+wire \ECHO|ctr[4]~DUPLICATE_q ;
+wire \ECHO|Add2~1_sumout ;
+wire \ECHO|Add1~14 ;
+wire \ECHO|Add1~17_sumout ;
+wire \ECHO|Add2~2 ;
+wire \ECHO|Add2~5_sumout ;
+wire \ECHO|Add1~18 ;
+wire \ECHO|Add1~21_sumout ;
+wire \ECHO|Add2~6 ;
+wire \ECHO|Add2~9_sumout ;
+wire \ECHO|Add1~22 ;
+wire \ECHO|Add1~25_sumout ;
+wire \ECHO|Add2~10 ;
+wire \ECHO|Add2~13_sumout ;
+wire \ECHO|Add1~26 ;
+wire \ECHO|Add1~29_sumout ;
+wire \ECHO|Add2~14 ;
+wire \ECHO|Add2~17_sumout ;
+wire \ECHO|Add1~30 ;
+wire \ECHO|Add1~33_sumout ;
+wire \ECHO|Add2~18 ;
+wire \ECHO|Add2~21_sumout ;
+wire \ECHO|Add1~34 ;
+wire \ECHO|Add1~37_sumout ;
+wire \ECHO|Add2~22 ;
+wire \ECHO|Add2~25_sumout ;
+wire \ECHO|Add1~38 ;
+wire \ECHO|Add1~41_sumout ;
+wire \ECHO|ctr[11]~DUPLICATE_q ;
+wire \ECHO|Add2~26 ;
+wire \ECHO|Add2~29_sumout ;
+wire \ECHO|Add1~42 ;
+wire \ECHO|Add1~45_sumout ;
+wire \ECHO|Add2~30 ;
+wire \ECHO|Add2~33_sumout ;
+wire \ECHO|ctr[6]~DUPLICATE_q ;
+wire \ADC_SDO~input_o ;
+wire \SPI_ADC|shift_reg[0]~feeder_combout ;
+wire \SPI_ADC|WideOr0~0_combout ;
+wire \SPI_ADC|shift_ena~q ;
+wire \SPI_ADC|always3~0_combout ;
+wire \SPI_ADC|shift_reg[1]~feeder_combout ;
+wire \SPI_ADC|shift_reg[2]~feeder_combout ;
+wire \SPI_ADC|shift_reg[3]~feeder_combout ;
+wire \SPI_ADC|shift_reg[4]~feeder_combout ;
+wire \SPI_ADC|shift_reg[9]~feeder_combout ;
+wire \SPI_ADC|Decoder0~0_combout ;
+wire \SPI_ADC|adc_done~q ;
+wire \SPI_ADC|data_from_adc[8]~feeder_combout ;
+wire \ECHO|Add0~33_sumout ;
+wire \ECHO|Add3~9_sumout ;
+wire \SPI_ADC|shift_reg[6]~DUPLICATE_q ;
+wire \ECHO|Add0~1_sumout ;
+wire \ECHO|Add0~5_sumout ;
+wire \ECHO|Add0~9_sumout ;
+wire \SPI_ADC|data_from_adc[3]~feeder_combout ;
+wire \SPI_ADC|data_from_adc[2]~feeder_combout ;
+wire \ECHO|Add0~13_sumout ;
+wire \SPI_ADC|data_from_adc[1]~feeder_combout ;
+wire \ECHO|Add0~17_sumout ;
+wire \ECHO|Add0~21_sumout ;
+wire \SPI_ADC|data_from_adc[0]~feeder_combout ;
+wire \ECHO|Add0~26 ;
+wire \ECHO|Add0~22 ;
+wire \ECHO|Add0~18 ;
+wire \ECHO|Add0~14 ;
+wire \ECHO|Add0~10 ;
+wire \ECHO|Add0~6 ;
+wire \ECHO|Add0~2 ;
+wire \ECHO|Add0~37_sumout ;
+wire \ECHO|Add3~10 ;
+wire \ECHO|Add3~5_sumout ;
+wire \ECHO|Add0~38 ;
+wire \ECHO|Add0~34 ;
+wire \ECHO|Add0~29_sumout ;
+wire \ECHO|Add3~6 ;
+wire \ECHO|Add3~1_sumout ;
+wire \ECHO|data_out[9]~0_combout ;
+wire \SPI_DAC|shift_reg[11]~feeder_combout ;
+wire \SPI_DAC|shift_reg[10]~feeder_combout ;
+wire \SPI_DAC|shift_reg[9]~feeder_combout ;
+wire \SPI_DAC|shift_reg[8]~feeder_combout ;
+wire \SPI_DAC|shift_reg[7]~feeder_combout ;
+wire \SPI_DAC|shift_reg[6]~feeder_combout ;
+wire \SPI_DAC|shift_reg[5]~feeder_combout ;
+wire \SPI_DAC|shift_reg[4]~feeder_combout ;
+wire \SPI_DAC|shift_reg[3]~feeder_combout ;
+wire \ECHO|Add0~25_sumout ;
+wire \SPI_DAC|shift_reg~4_combout ;
+wire \SPI_DAC|always3~0_combout ;
+wire \SPI_DAC|shift_reg~3_combout ;
+wire \SPI_DAC|shift_reg~2_combout ;
+wire \SPI_DAC|shift_reg~1_combout ;
+wire \SPI_DAC|shift_reg~0_combout ;
+wire \SPI_DAC|dac_sck~combout ;
+wire \SPI_DAC|Equal2~0_combout ;
+wire \SPI_DAC|dac_ld~q ;
+wire \SW[9]~input_o ;
+wire \SPI_ADC|Selector6~0_combout ;
+wire \SPI_ADC|adc_din~q ;
+wire \SPI_ADC|adc_sck~combout ;
+wire \PWM_DC|count[0]~0_combout ;
+wire \PWM_DC|Add0~33_sumout ;
+wire \PWM_DC|Add0~34 ;
+wire \PWM_DC|Add0~29_sumout ;
+wire \PWM_DC|Add0~30 ;
+wire \PWM_DC|Add0~25_sumout ;
+wire \PWM_DC|Add0~26 ;
+wire \PWM_DC|Add0~21_sumout ;
+wire \PWM_DC|Add0~22 ;
+wire \PWM_DC|Add0~17_sumout ;
+wire \PWM_DC|Add0~18 ;
+wire \PWM_DC|Add0~13_sumout ;
+wire \PWM_DC|Add0~14 ;
+wire \PWM_DC|Add0~9_sumout ;
+wire \PWM_DC|Add0~10 ;
+wire \PWM_DC|Add0~5_sumout ;
+wire \PWM_DC|Add0~6 ;
+wire \PWM_DC|Add0~1_sumout ;
+wire \PWM_DC|LessThan0~0_combout ;
+wire \PWM_DC|LessThan0~1_combout ;
+wire \PWM_DC|d[0]~feeder_combout ;
+wire \PWM_DC|LessThan0~2_combout ;
+wire \PWM_DC|LessThan0~3_combout ;
+wire \PWM_DC|d[6]~feeder_combout ;
+wire \PWM_DC|LessThan0~4_combout ;
+wire \PWM_DC|LessThan0~5_combout ;
+wire \PWM_DC|pwm_out~q ;
+wire [20:0] \GEN_10K|ctr ;
+wire [9:0] \PWM_DC|d ;
+wire [4:0] \SPI_ADC|ctr ;
+wire [15:0] \SPI_DAC|shift_reg ;
+wire [8:0] \ECHO|DELAY|altsyncram_component|auto_generated|q_b ;
+wire [4:0] \SPI_DAC|state ;
+wire [4:0] \SPI_ADC|state ;
+wire [9:0] \PWM_DC|count ;
+wire [9:0] \ECHO|data_out ;
+wire [9:0] \SPI_ADC|data_from_adc ;
+wire [12:0] \ECHO|ctr ;
+wire [9:0] \SPI_ADC|shift_reg ;
+
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ;
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ;
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ;
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ;
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ;
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ;
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ;
+wire [0:0] \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ;
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [6] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0];
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [5] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0];
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [4] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0];
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [3] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0];
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [2] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0];
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [1] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0];
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [0] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [8] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0];
+
+assign \ECHO|DELAY|altsyncram_component|auto_generated|q_b [7] = \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0];
+
+// Location: IOOBUF_X89_Y8_N39
+cyclonev_io_obuf \HEX0[0]~output (
+	.i(\SEG0|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[0]~output .bus_hold = "false";
+defparam \HEX0[0]~output .open_drain_output = "false";
+defparam \HEX0[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N79
+cyclonev_io_obuf \HEX0[1]~output (
+	.i(\SEG0|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[1]~output .bus_hold = "false";
+defparam \HEX0[1]~output .open_drain_output = "false";
+defparam \HEX0[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N96
+cyclonev_io_obuf \HEX0[2]~output (
+	.i(\SEG0|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[2]~output .bus_hold = "false";
+defparam \HEX0[2]~output .open_drain_output = "false";
+defparam \HEX0[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N79
+cyclonev_io_obuf \HEX0[3]~output (
+	.i(\SEG0|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[3]~output .bus_hold = "false";
+defparam \HEX0[3]~output .open_drain_output = "false";
+defparam \HEX0[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N56
+cyclonev_io_obuf \HEX0[4]~output (
+	.i(\SEG0|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[4]~output .bus_hold = "false";
+defparam \HEX0[4]~output .open_drain_output = "false";
+defparam \HEX0[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y13_N39
+cyclonev_io_obuf \HEX0[5]~output (
+	.i(\SEG0|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[5]~output .bus_hold = "false";
+defparam \HEX0[5]~output .open_drain_output = "false";
+defparam \HEX0[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N96
+cyclonev_io_obuf \HEX0[6]~output (
+	.i(!\SEG0|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX0[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX0[6]~output .bus_hold = "false";
+defparam \HEX0[6]~output .open_drain_output = "false";
+defparam \HEX0[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y6_N39
+cyclonev_io_obuf \HEX1[0]~output (
+	.i(!\SEG1|WideOr6~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[0]~output .bus_hold = "false";
+defparam \HEX1[0]~output .open_drain_output = "false";
+defparam \HEX1[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y6_N56
+cyclonev_io_obuf \HEX1[1]~output (
+	.i(\SEG1|WideOr5~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[1]~output .bus_hold = "false";
+defparam \HEX1[1]~output .open_drain_output = "false";
+defparam \HEX1[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N39
+cyclonev_io_obuf \HEX1[2]~output (
+	.i(\SEG1|WideOr4~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[2]~output .bus_hold = "false";
+defparam \HEX1[2]~output .open_drain_output = "false";
+defparam \HEX1[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N56
+cyclonev_io_obuf \HEX1[3]~output (
+	.i(!\SEG1|WideOr3~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[3]~output .bus_hold = "false";
+defparam \HEX1[3]~output .open_drain_output = "false";
+defparam \HEX1[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N39
+cyclonev_io_obuf \HEX1[4]~output (
+	.i(!\SEG1|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[4]~output .bus_hold = "false";
+defparam \HEX1[4]~output .open_drain_output = "false";
+defparam \HEX1[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y15_N56
+cyclonev_io_obuf \HEX1[5]~output (
+	.i(!\SEG1|WideOr1~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[5]~output .bus_hold = "false";
+defparam \HEX1[5]~output .open_drain_output = "false";
+defparam \HEX1[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y8_N56
+cyclonev_io_obuf \HEX1[6]~output (
+	.i(!\SEG1|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX1[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX1[6]~output .bus_hold = "false";
+defparam \HEX1[6]~output .open_drain_output = "false";
+defparam \HEX1[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N22
+cyclonev_io_obuf \HEX2[0]~output (
+	.i(\SEG2|WideOr6~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[0]~output .bus_hold = "false";
+defparam \HEX2[0]~output .open_drain_output = "false";
+defparam \HEX2[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y23_N39
+cyclonev_io_obuf \HEX2[1]~output (
+	.i(\SEG2|WideOr5~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[1]~output .bus_hold = "false";
+defparam \HEX2[1]~output .open_drain_output = "false";
+defparam \HEX2[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y23_N56
+cyclonev_io_obuf \HEX2[2]~output (
+	.i(\SEG2|Decoder0~3_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[2]~output .bus_hold = "false";
+defparam \HEX2[2]~output .open_drain_output = "false";
+defparam \HEX2[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N79
+cyclonev_io_obuf \HEX2[3]~output (
+	.i(!\SEG2|WideOr2~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[3]~output .bus_hold = "false";
+defparam \HEX2[3]~output .open_drain_output = "false";
+defparam \HEX2[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y25_N39
+cyclonev_io_obuf \HEX2[4]~output (
+	.i(\SEG2|WideOr2~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[4]~output .bus_hold = "false";
+defparam \HEX2[4]~output .open_drain_output = "false";
+defparam \HEX2[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y20_N96
+cyclonev_io_obuf \HEX2[5]~output (
+	.i(\SEG2|WideOr1~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[5]~output .bus_hold = "false";
+defparam \HEX2[5]~output .open_drain_output = "false";
+defparam \HEX2[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y25_N56
+cyclonev_io_obuf \HEX2[6]~output (
+	.i(\SEG2|WideOr0~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX2[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX2[6]~output .bus_hold = "false";
+defparam \HEX2[6]~output .open_drain_output = "false";
+defparam \HEX2[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N5
+cyclonev_io_obuf \HEX3[0]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[0]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[0]~output .bus_hold = "false";
+defparam \HEX3[0]~output .open_drain_output = "false";
+defparam \HEX3[0]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y16_N22
+cyclonev_io_obuf \HEX3[1]~output (
+	.i(gnd),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[1]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[1]~output .bus_hold = "false";
+defparam \HEX3[1]~output .open_drain_output = "false";
+defparam \HEX3[1]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N45
+cyclonev_io_obuf \HEX3[2]~output (
+	.i(gnd),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[2]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[2]~output .bus_hold = "false";
+defparam \HEX3[2]~output .open_drain_output = "false";
+defparam \HEX3[2]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y4_N62
+cyclonev_io_obuf \HEX3[3]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[3]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[3]~output .bus_hold = "false";
+defparam \HEX3[3]~output .open_drain_output = "false";
+defparam \HEX3[3]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y21_N39
+cyclonev_io_obuf \HEX3[4]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[4]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[4]~output .bus_hold = "false";
+defparam \HEX3[4]~output .open_drain_output = "false";
+defparam \HEX3[4]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y11_N62
+cyclonev_io_obuf \HEX3[5]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~0_combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[5]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[5]~output .bus_hold = "false";
+defparam \HEX3[5]~output .open_drain_output = "false";
+defparam \HEX3[5]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X89_Y9_N5
+cyclonev_io_obuf \HEX3[6]~output (
+	.i(vcc),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(HEX3[6]),
+	.obar());
+// synopsys translate_off
+defparam \HEX3[6]~output .bus_hold = "false";
+defparam \HEX3[6]~output .open_drain_output = "false";
+defparam \HEX3[6]~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X58_Y0_N76
+cyclonev_io_obuf \DAC_SDI~output (
+	.i(\SPI_DAC|shift_reg [15]),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_SDI),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SDI~output .bus_hold = "false";
+defparam \DAC_SDI~output .open_drain_output = "false";
+defparam \DAC_SDI~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N2
+cyclonev_io_obuf \DAC_SCK~output (
+	.i(!\SPI_DAC|dac_sck~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_SCK),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SCK~output .bus_hold = "false";
+defparam \DAC_SCK~output .open_drain_output = "false";
+defparam \DAC_SCK~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X82_Y0_N42
+cyclonev_io_obuf \DAC_CS~output (
+	.i(!\SPI_DAC|dac_cs~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_CS),
+	.obar());
+// synopsys translate_off
+defparam \DAC_CS~output .bus_hold = "false";
+defparam \DAC_CS~output .open_drain_output = "false";
+defparam \DAC_CS~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X68_Y0_N36
+cyclonev_io_obuf \DAC_LD~output (
+	.i(\SPI_DAC|dac_ld~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(DAC_LD),
+	.obar());
+// synopsys translate_off
+defparam \DAC_LD~output .bus_hold = "false";
+defparam \DAC_LD~output .open_drain_output = "false";
+defparam \DAC_LD~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X54_Y0_N2
+cyclonev_io_obuf \ADC_SDI~output (
+	.i(\SPI_ADC|adc_din~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_SDI),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SDI~output .bus_hold = "false";
+defparam \ADC_SDI~output .open_drain_output = "false";
+defparam \ADC_SDI~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X70_Y0_N19
+cyclonev_io_obuf \ADC_SCK~output (
+	.i(!\SPI_ADC|adc_sck~combout ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_SCK),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SCK~output .bus_hold = "false";
+defparam \ADC_SCK~output .open_drain_output = "false";
+defparam \ADC_SCK~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N19
+cyclonev_io_obuf \ADC_CS~output (
+	.i(!\SPI_ADC|adc_cs~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(ADC_CS),
+	.obar());
+// synopsys translate_off
+defparam \ADC_CS~output .bus_hold = "false";
+defparam \ADC_CS~output .open_drain_output = "false";
+defparam \ADC_CS~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X62_Y0_N36
+cyclonev_io_obuf \PWM_OUT~output (
+	.i(\PWM_DC|pwm_out~q ),
+	.oe(vcc),
+	.dynamicterminationcontrol(gnd),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.parallelterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(PWM_OUT),
+	.obar());
+// synopsys translate_off
+defparam \PWM_OUT~output .bus_hold = "false";
+defparam \PWM_OUT~output .open_drain_output = "false";
+defparam \PWM_OUT~output .shift_series_termination_control = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X2_Y0_N41
+cyclonev_io_ibuf \SW[4]~input (
+	.i(SW[4]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[4]~input_o ));
+// synopsys translate_off
+defparam \SW[4]~input .bus_hold = "false";
+defparam \SW[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X16_Y0_N18
+cyclonev_io_ibuf \SW[5]~input (
+	.i(SW[5]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[5]~input_o ));
+// synopsys translate_off
+defparam \SW[5]~input .bus_hold = "false";
+defparam \SW[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N35
+cyclonev_io_ibuf \SW[6]~input (
+	.i(SW[6]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[6]~input_o ));
+// synopsys translate_off
+defparam \SW[6]~input .bus_hold = "false";
+defparam \SW[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X16_Y0_N1
+cyclonev_io_ibuf \SW[1]~input (
+	.i(SW[1]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[1]~input_o ));
+// synopsys translate_off
+defparam \SW[1]~input .bus_hold = "false";
+defparam \SW[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X12_Y0_N18
+cyclonev_io_ibuf \SW[0]~input (
+	.i(SW[0]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[0]~input_o ));
+// synopsys translate_off
+defparam \SW[0]~input .bus_hold = "false";
+defparam \SW[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X8_Y0_N35
+cyclonev_io_ibuf \SW[2]~input (
+	.i(SW[2]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[2]~input_o ));
+// synopsys translate_off
+defparam \SW[2]~input .bus_hold = "false";
+defparam \SW[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N52
+cyclonev_io_ibuf \SW[3]~input (
+	.i(SW[3]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[3]~input_o ));
+// synopsys translate_off
+defparam \SW[3]~input .bus_hold = "false";
+defparam \SW[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N45
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][12]~2 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][12]~2_combout  = ( \SW[3]~input_o  & ( (!\SW[1]~input_o  & ((!\SW[2]~input_o ) # (\SW[0]~input_o ))) # (\SW[1]~input_o  & ((!\SW[0]~input_o ) # (\SW[2]~input_o ))) ) ) # ( !\SW[3]~input_o  & ( 
+// (!\SW[1]~input_o  & ((\SW[2]~input_o ))) # (\SW[1]~input_o  & (\SW[0]~input_o  & !\SW[2]~input_o )) ) )
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(gnd),
+	.datac(!\SW[0]~input_o ),
+	.datad(!\SW[2]~input_o ),
+	.datae(gnd),
+	.dataf(!\SW[3]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][12]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~2 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~2 .lut_mask = 64'h05AA05AAFA5FFA5F;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N1
+cyclonev_io_ibuf \SW[7]~input (
+	.i(SW[7]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[7]~input_o ));
+// synopsys translate_off
+defparam \SW[7]~input .bus_hold = "false";
+defparam \SW[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N3
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][11]~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][11]~1_combout  = (!\SW[0]~input_o  & ((!\SW[2]~input_o  & (\SW[1]~input_o )) # (\SW[2]~input_o  & ((!\SW[1]~input_o ) # (\SW[3]~input_o ))))) # (\SW[0]~input_o  & (!\SW[2]~input_o  $ (((!\SW[3]~input_o ) # 
+// (\SW[1]~input_o )))))
+
+	.dataa(!\SW[2]~input_o ),
+	.datab(!\SW[0]~input_o ),
+	.datac(!\SW[1]~input_o ),
+	.datad(!\SW[3]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][11]~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~1 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~1 .lut_mask = 64'h596D596D596D596D;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N0
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  = (!\SW[0]~input_o  & (!\SW[1]~input_o  $ (((!\SW[2]~input_o ) # (!\SW[3]~input_o ))))) # (\SW[0]~input_o  & ((!\SW[3]~input_o  & ((!\SW[1]~input_o ) # (\SW[2]~input_o ))) # (\SW[3]~input_o  & 
+// ((\SW[1]~input_o )))))
+
+	.dataa(!\SW[2]~input_o ),
+	.datab(!\SW[0]~input_o ),
+	.datac(!\SW[3]~input_o ),
+	.datad(!\SW[1]~input_o ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .lut_mask = 64'h34DB34DB34DB34DB;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N57
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][9]~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][9]~5_combout  = ( \SW[7]~input_o  & ( (!\SW[4]~input_o  & (!\SW[6]~input_o )) # (\SW[4]~input_o  & ((\SW[5]~input_o ) # (\SW[6]~input_o ))) ) ) # ( !\SW[7]~input_o  & ( !\SW[4]~input_o  $ (((!\SW[6]~input_o ) 
+// # (!\SW[5]~input_o ))) ) )
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[6]~input_o ),
+	.datac(!\SW[5]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][9]~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~5 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~5 .lut_mask = 64'h565656569D9D9D9D;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N54
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][4]~6 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][4]~6_combout  = ( \SW[7]~input_o  & ( (!\SW[6]~input_o  & ((!\SW[4]~input_o ) # (!\SW[5]~input_o ))) # (\SW[6]~input_o  & ((\SW[5]~input_o ))) ) ) # ( !\SW[7]~input_o  & ( (!\SW[6]~input_o  & (\SW[4]~input_o  
+// & \SW[5]~input_o )) # (\SW[6]~input_o  & ((!\SW[5]~input_o ))) ) )
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[6]~input_o ),
+	.datac(gnd),
+	.datad(!\SW[5]~input_o ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][4]~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~6 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~6 .lut_mask = 64'h33443344CCBBCCBB;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N6
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout  = CARRY(( GND ) + ( GND ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .lut_mask = 64'h0000FFFF00000000;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N9
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout  = CARRY(( (!\SW[2]~input_o  & ((!\SW[0]~input_o  & ((\SW[3]~input_o ))) # (\SW[0]~input_o  & ((!\SW[3]~input_o ) # (\SW[1]~input_o ))))) # (\SW[2]~input_o  & 
+// (!\SW[0]~input_o  $ (((!\SW[1]~input_o ) # (\SW[3]~input_o ))))) ) + ( \SW[4]~input_o  ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout  ))
+
+	.dataa(!\SW[2]~input_o ),
+	.datab(!\SW[0]~input_o ),
+	.datac(!\SW[1]~input_o ),
+	.datad(!\SW[3]~input_o ),
+	.datae(gnd),
+	.dataf(!\SW[4]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .lut_mask = 64'h0000FF000000369B;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N12
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50_cout  = CARRY(( \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  ) + ( !\SW[5]~input_o  $ (!\SW[4]~input_o ) ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout  ))
+
+	.dataa(gnd),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[4]~input_o ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50 .lut_mask = 64'h0000C3C3000000FF;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N15
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46_cout  = CARRY(( \SCALER|lpm_mult_component|mult_core|romout[0][11]~1_combout  ) + ( !\SW[6]~input_o  $ (((!\SW[5]~input_o ) # (\SW[4]~input_o ))) ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50_cout  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(gnd),
+	.datac(!\SW[5]~input_o ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|romout[0][11]~1_combout ),
+	.datae(gnd),
+	.dataf(!\SW[6]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 .lut_mask = 64'h0000F50A000000FF;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N18
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42_cout  = CARRY(( \SCALER|lpm_mult_component|mult_core|romout[1][4]~6_combout  ) + ( (!\SW[2]~input_o  & (!\SW[3]~input_o  $ (((!\SW[1]~input_o ) # (!\SW[0]~input_o ))))) # 
+// (\SW[2]~input_o  & ((!\SW[1]~input_o  & ((!\SW[3]~input_o ) # (\SW[0]~input_o ))) # (\SW[1]~input_o  & ((\SW[3]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46_cout  ))
+
+	.dataa(!\SW[2]~input_o ),
+	.datab(!\SW[1]~input_o ),
+	.datac(!\SW[0]~input_o ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|romout[1][4]~6_combout ),
+	.datae(gnd),
+	.dataf(!\SW[3]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 .lut_mask = 64'h0000B942000000FF;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N21
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout  = SUM(( (!\SW[2]~input_o  & ((!\SW[0]~input_o  & ((\SW[3]~input_o ))) # (\SW[0]~input_o  & ((!\SW[3]~input_o ) # (\SW[1]~input_o ))))) # (\SW[2]~input_o  & 
+// (!\SW[0]~input_o  $ (((!\SW[1]~input_o ) # (\SW[3]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|romout[1][9]~5_combout  ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42_cout  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  = CARRY(( (!\SW[2]~input_o  & ((!\SW[0]~input_o  & ((\SW[3]~input_o ))) # (\SW[0]~input_o  & ((!\SW[3]~input_o ) # (\SW[1]~input_o ))))) # (\SW[2]~input_o  & (!\SW[0]~input_o  $ 
+// (((!\SW[1]~input_o ) # (\SW[3]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|romout[1][9]~5_combout  ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42_cout  ))
+
+	.dataa(!\SW[2]~input_o ),
+	.datab(!\SW[1]~input_o ),
+	.datac(!\SW[0]~input_o ),
+	.datad(!\SW[3]~input_o ),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|romout[1][9]~5_combout ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .lut_mask = 64'h0000FF0000001EA7;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N24
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  ) + ( (!\SW[4]~input_o  & (!\SW[5]~input_o  $ (((!\SW[6]~input_o ) # (!\SW[7]~input_o ))))) # 
+// (\SW[4]~input_o  & ((!\SW[5]~input_o  & ((!\SW[7]~input_o ))) # (\SW[5]~input_o  & ((\SW[7]~input_o ) # (\SW[6]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  = CARRY(( \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  ) + ( (!\SW[4]~input_o  & (!\SW[5]~input_o  $ (((!\SW[6]~input_o ) # (!\SW[7]~input_o ))))) # 
+// (\SW[4]~input_o  & ((!\SW[5]~input_o  & ((!\SW[7]~input_o ))) # (\SW[5]~input_o  & ((\SW[7]~input_o ) # (\SW[6]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .lut_mask = 64'h000098C6000000FF;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N27
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|romout[0][11]~1_combout  ) + ( (!\SW[4]~input_o  & ((!\SW[5]~input_o  & (\SW[6]~input_o )) # (\SW[5]~input_o  & 
+// ((!\SW[6]~input_o ) # (\SW[7]~input_o ))))) # (\SW[4]~input_o  & (!\SW[6]~input_o  $ (((!\SW[7]~input_o ) # (\SW[5]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  = CARRY(( \SCALER|lpm_mult_component|mult_core|romout[0][11]~1_combout  ) + ( (!\SW[4]~input_o  & ((!\SW[5]~input_o  & (\SW[6]~input_o )) # (\SW[5]~input_o  & ((!\SW[6]~input_o ) 
+// # (\SW[7]~input_o ))))) # (\SW[4]~input_o  & (!\SW[6]~input_o  $ (((!\SW[7]~input_o ) # (\SW[5]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|romout[0][11]~1_combout ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .lut_mask = 64'h0000D294000000FF;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N30
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|romout[0][12]~2_combout  ) + ( (!\SW[5]~input_o  & ((!\SW[6]~input_o  & ((\SW[7]~input_o ))) # (\SW[6]~input_o  & 
+// ((!\SW[7]~input_o ) # (\SW[4]~input_o ))))) # (\SW[5]~input_o  & (!\SW[7]~input_o  $ (((!\SW[4]~input_o ) # (\SW[6]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10  = CARRY(( \SCALER|lpm_mult_component|mult_core|romout[0][12]~2_combout  ) + ( (!\SW[5]~input_o  & ((!\SW[6]~input_o  & ((\SW[7]~input_o ))) # (\SW[6]~input_o  & ((!\SW[7]~input_o 
+// ) # (\SW[4]~input_o ))))) # (\SW[5]~input_o  & (!\SW[7]~input_o  $ (((!\SW[4]~input_o ) # (\SW[6]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|romout[0][12]~2_combout ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9 .lut_mask = 64'h0000E318000000FF;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X4_Y0_N18
+cyclonev_io_ibuf \SW[8]~input (
+	.i(SW[8]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[8]~input_o ));
+// synopsys translate_off
+defparam \SW[8]~input .bus_hold = "false";
+defparam \SW[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N0
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42_cout  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout  ) + ( \SW[8]~input_o  ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\SW[8]~input_o ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42_cout ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 .lut_mask = 64'h0000CCCC00000F0F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N3
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42_cout  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42_cout  ))
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1_sumout ),
+	.datab(!\SW[8]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42_cout ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .lut_mask = 64'h0000CCCC00005555;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N6
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  ) + ( GND ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout  ) + ( GND ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N9
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9_sumout  ) + ( GND ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9_sumout  ) + ( GND ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6  ))
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .lut_mask = 64'h0000FFFF00005555;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N48
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][14]~4 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][14]~4_combout  = ( \SW[0]~input_o  & ( (\SW[3]~input_o  & ((\SW[2]~input_o ) # (\SW[1]~input_o ))) ) ) # ( !\SW[0]~input_o  & ( (\SW[3]~input_o  & \SW[2]~input_o ) ) )
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(!\SW[3]~input_o ),
+	.datac(!\SW[2]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[0]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][14]~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~4 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~4 .lut_mask = 64'h0303030313131313;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N42
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][13]~3 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][13]~3_combout  = ( \SW[3]~input_o  & ( (!\SW[2]~input_o  & ((!\SW[1]~input_o ) # (!\SW[0]~input_o ))) ) ) # ( !\SW[3]~input_o  & ( (\SW[1]~input_o  & \SW[2]~input_o ) ) )
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(!\SW[0]~input_o ),
+	.datac(!\SW[2]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[3]~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][13]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~3 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~3 .lut_mask = 64'h05050505E0E0E0E0;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N33
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  = SUM(( (!\SW[6]~input_o  & ((!\SW[4]~input_o  & ((\SW[7]~input_o ))) # (\SW[4]~input_o  & ((!\SW[7]~input_o ) # (\SW[5]~input_o ))))) # (\SW[6]~input_o  & 
+// (!\SW[4]~input_o  $ (((!\SW[5]~input_o ) # (\SW[7]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|romout[0][13]~3_combout  ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  = CARRY(( (!\SW[6]~input_o  & ((!\SW[4]~input_o  & ((\SW[7]~input_o ))) # (\SW[4]~input_o  & ((!\SW[7]~input_o ) # (\SW[5]~input_o ))))) # (\SW[6]~input_o  & (!\SW[4]~input_o  $ 
+// (((!\SW[5]~input_o ) # (\SW[7]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|romout[0][13]~3_combout  ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\SW[7]~input_o ),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|romout[0][13]~3_combout ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .lut_mask = 64'h0000FF00000056B5;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N36
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|romout[0][14]~4_combout  ) + ( (!\SW[4]~input_o  & (!\SW[5]~input_o  $ (((!\SW[6]~input_o ) # (!\SW[7]~input_o ))))) # 
+// (\SW[4]~input_o  & ((!\SW[5]~input_o  & ((!\SW[7]~input_o ))) # (\SW[5]~input_o  & ((\SW[7]~input_o ) # (\SW[6]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  = CARRY(( \SCALER|lpm_mult_component|mult_core|romout[0][14]~4_combout  ) + ( (!\SW[4]~input_o  & (!\SW[5]~input_o  $ (((!\SW[6]~input_o ) # (!\SW[7]~input_o ))))) # 
+// (\SW[4]~input_o  & ((!\SW[5]~input_o  & ((!\SW[7]~input_o ))) # (\SW[5]~input_o  & ((\SW[7]~input_o ) # (\SW[6]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|romout[0][14]~4_combout ),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .lut_mask = 64'h000098C6000000FF;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N39
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  = SUM(( GND ) + ( (!\SW[4]~input_o  & ((!\SW[5]~input_o  & (\SW[6]~input_o )) # (\SW[5]~input_o  & ((!\SW[6]~input_o ) # (\SW[7]~input_o ))))) # (\SW[4]~input_o  & 
+// (!\SW[6]~input_o  $ (((!\SW[7]~input_o ) # (\SW[5]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  = CARRY(( GND ) + ( (!\SW[4]~input_o  & ((!\SW[5]~input_o  & (\SW[6]~input_o )) # (\SW[5]~input_o  & ((!\SW[6]~input_o ) # (\SW[7]~input_o ))))) # (\SW[4]~input_o  & 
+// (!\SW[6]~input_o  $ (((!\SW[7]~input_o ) # (\SW[5]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .lut_mask = 64'h0000D29400000000;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N42
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  = SUM(( GND ) + ( (!\SW[5]~input_o  & ((!\SW[6]~input_o  & ((\SW[7]~input_o ))) # (\SW[6]~input_o  & ((!\SW[7]~input_o ) # (\SW[4]~input_o ))))) # (\SW[5]~input_o  & 
+// (!\SW[7]~input_o  $ (((!\SW[4]~input_o ) # (\SW[6]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  = CARRY(( GND ) + ( (!\SW[5]~input_o  & ((!\SW[6]~input_o  & ((\SW[7]~input_o ))) # (\SW[6]~input_o  & ((!\SW[7]~input_o ) # (\SW[4]~input_o ))))) # (\SW[5]~input_o  & 
+// (!\SW[7]~input_o  $ (((!\SW[4]~input_o ) # (\SW[6]~input_o ))))) ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .lut_mask = 64'h0000E31800000000;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N45
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  = SUM(( GND ) + ( (!\SW[6]~input_o  & (\SW[7]~input_o  & ((!\SW[4]~input_o ) # (!\SW[5]~input_o )))) # (\SW[6]~input_o  & (((\SW[5]~input_o  & !\SW[7]~input_o )))) ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  ))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30  = CARRY(( GND ) + ( (!\SW[6]~input_o  & (\SW[7]~input_o  & ((!\SW[4]~input_o ) # (!\SW[5]~input_o )))) # (\SW[6]~input_o  & (((\SW[5]~input_o  & !\SW[7]~input_o )))) ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .lut_mask = 64'h0000FC1F00000000;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N12
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  = SUM(( \SW[8]~input_o  ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  = CARRY(( \SW[8]~input_o  ) + ( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10  ))
+
+	.dataa(gnd),
+	.datab(!\SW[8]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13_sumout ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .lut_mask = 64'h0000FF0000003333;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N15
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14  ))
+
+	.dataa(gnd),
+	.datab(!\SW[8]~input_o ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .lut_mask = 64'h0000CCCC00000F0F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N18
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  ) + ( GND ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout  ) + ( GND ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18  ))
+
+	.dataa(gnd),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .lut_mask = 64'h0000FFFF00003333;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N21
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  ) + ( GND ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout  ) + ( GND ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N24
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26  ))
+
+	.dataa(gnd),
+	.datab(!\SW[8]~input_o ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .lut_mask = 64'h0000CCCC00000F0F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X68_Y4_N48
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  = SUM(( GND ) + ( (\SW[7]~input_o  & (((\SW[4]~input_o  & \SW[5]~input_o )) # (\SW[6]~input_o ))) ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30  ))
+
+	.dataa(!\SW[4]~input_o ),
+	.datab(!\SW[5]~input_o ),
+	.datac(!\SW[6]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[7]~input_o ),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .lut_mask = 64'h0000FFE000000000;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N27
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  = SUM(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  ))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34  = CARRY(( \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout  ) + ( \SW[8]~input_o  ) + ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30  ))
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33_sumout ),
+	.datab(!\SW[8]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .lut_mask = 64'h0000CCCC00005555;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N30
+cyclonev_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  = SUM(( GND ) + ( GND ) + ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .extended_lut = "off";
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .lut_mask = 64'h0000FFFF00000000;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N39
+cyclonev_lcell_comb \BCD_CONVERT|A9|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr2~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  ) ) ) # ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A9|WideOr2~0 .lut_mask = 64'h5500AAAA555500AA;
+defparam \BCD_CONVERT|A9|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N33
+cyclonev_lcell_comb \BCD_CONVERT|A9|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr1~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ) ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A9|WideOr1~0 .lut_mask = 64'h00AA00550000AA00;
+defparam \BCD_CONVERT|A9|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N42
+cyclonev_lcell_comb \BCD_CONVERT|A9|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr3~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  $ (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  ) ) ) # ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ) ) ) ) # ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ) ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datab(gnd),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(gnd),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A9|WideOr3~0 .lut_mask = 64'h0505A0A0AAAA5A5A;
+defparam \BCD_CONVERT|A9|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N12
+cyclonev_lcell_comb \BCD_CONVERT|A12|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr1~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( \BCD_CONVERT|A9|WideOr3~0_combout  & ( (!\BCD_CONVERT|A9|WideOr2~0_combout  & \BCD_CONVERT|A9|WideOr1~0_combout ) ) 
+// ) ) # ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( \BCD_CONVERT|A9|WideOr3~0_combout  & ( (!\BCD_CONVERT|A9|WideOr2~0_combout  & \BCD_CONVERT|A9|WideOr1~0_combout ) ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( !\BCD_CONVERT|A9|WideOr3~0_combout  & ( (!\BCD_CONVERT|A9|WideOr2~0_combout  & \BCD_CONVERT|A9|WideOr1~0_combout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( !\BCD_CONVERT|A9|WideOr3~0_combout  & ( \BCD_CONVERT|A9|WideOr2~0_combout  ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A9|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.dataf(!\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A12|WideOr1~0 .lut_mask = 64'h33330C0C0C0C0C0C;
+defparam \BCD_CONVERT|A12|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N9
+cyclonev_lcell_comb \BCD_CONVERT|A12|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr2~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( \BCD_CONVERT|A9|WideOr3~0_combout  & ( (!\BCD_CONVERT|A9|WideOr1~0_combout ) # (!\BCD_CONVERT|A9|WideOr2~0_combout 
+// ) ) ) ) # ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( \BCD_CONVERT|A9|WideOr3~0_combout  & ( (!\BCD_CONVERT|A9|WideOr1~0_combout  & !\BCD_CONVERT|A9|WideOr2~0_combout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( !\BCD_CONVERT|A9|WideOr3~0_combout  & ( \BCD_CONVERT|A9|WideOr1~0_combout  ) ) )
+
+	.dataa(!\BCD_CONVERT|A9|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.dataf(!\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A12|WideOr2~0 .lut_mask = 64'h55550000A0A0FAFA;
+defparam \BCD_CONVERT|A12|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N0
+cyclonev_lcell_comb \BCD_CONVERT|A12|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr3~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( \BCD_CONVERT|A9|WideOr3~0_combout  & ( (!\BCD_CONVERT|A9|WideOr2~0_combout  & !\BCD_CONVERT|A9|WideOr1~0_combout ) 
+// ) ) ) # ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( \BCD_CONVERT|A9|WideOr3~0_combout  & ( !\BCD_CONVERT|A9|WideOr2~0_combout  $ (!\BCD_CONVERT|A9|WideOr1~0_combout ) ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( !\BCD_CONVERT|A9|WideOr3~0_combout  & ( (!\BCD_CONVERT|A9|WideOr2~0_combout  & !\BCD_CONVERT|A9|WideOr1~0_combout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ( !\BCD_CONVERT|A9|WideOr3~0_combout  & ( \BCD_CONVERT|A9|WideOr1~0_combout  ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A9|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.dataf(!\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A12|WideOr3~0 .lut_mask = 64'h0F0FC0C03C3CC0C0;
+defparam \BCD_CONVERT|A12|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N36
+cyclonev_lcell_comb \BCD_CONVERT|A15|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr1~0_combout  = ( \BCD_CONVERT|A12|WideOr3~0_combout  & ( (\BCD_CONVERT|A12|WideOr1~0_combout  & !\BCD_CONVERT|A12|WideOr2~0_combout ) ) ) # ( !\BCD_CONVERT|A12|WideOr3~0_combout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & ((\BCD_CONVERT|A12|WideOr2~0_combout ))) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & 
+// (\BCD_CONVERT|A12|WideOr1~0_combout  & !\BCD_CONVERT|A12|WideOr2~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datad(!\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A15|WideOr1~0 .lut_mask = 64'h03F003F033003300;
+defparam \BCD_CONVERT|A15|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N33
+cyclonev_lcell_comb \BCD_CONVERT|A15|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr2~0_combout  = ( \BCD_CONVERT|A12|WideOr3~0_combout  & ( (!\BCD_CONVERT|A12|WideOr2~0_combout  & ((!\BCD_CONVERT|A12|WideOr1~0_combout ) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) # (\BCD_CONVERT|A12|WideOr2~0_combout  & (!\BCD_CONVERT|A12|WideOr1~0_combout  & 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) ) # ( !\BCD_CONVERT|A12|WideOr3~0_combout  & ( (\BCD_CONVERT|A12|WideOr1~0_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ) ) )
+
+	.dataa(!\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datab(!\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A15|WideOr2~0 .lut_mask = 64'h3300330088EE88EE;
+defparam \BCD_CONVERT|A15|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N30
+cyclonev_lcell_comb \BCD_CONVERT|A15|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr3~0_combout  = ( \BCD_CONVERT|A12|WideOr3~0_combout  & ( (!\BCD_CONVERT|A12|WideOr2~0_combout  & (!\BCD_CONVERT|A12|WideOr1~0_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) # (\BCD_CONVERT|A12|WideOr2~0_combout  & (!\BCD_CONVERT|A12|WideOr1~0_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) ) ) # ( !\BCD_CONVERT|A12|WideOr3~0_combout  & ( (!\BCD_CONVERT|A12|WideOr1~0_combout  & (!\BCD_CONVERT|A12|WideOr2~0_combout  & 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )) # (\BCD_CONVERT|A12|WideOr1~0_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datab(!\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A15|WideOr3~0 .lut_mask = 64'h3838383868686868;
+defparam \BCD_CONVERT|A15|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N12
+cyclonev_lcell_comb \BCD_CONVERT|A18|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr2~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( (\BCD_CONVERT|A15|WideOr3~0_combout  & ((!\BCD_CONVERT|A15|WideOr1~0_combout ) # 
+// (!\BCD_CONVERT|A15|WideOr2~0_combout ))) ) ) # ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( (!\BCD_CONVERT|A15|WideOr1~0_combout  & (!\BCD_CONVERT|A15|WideOr2~0_combout  & 
+// \BCD_CONVERT|A15|WideOr3~0_combout )) # (\BCD_CONVERT|A15|WideOr1~0_combout  & ((!\BCD_CONVERT|A15|WideOr3~0_combout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A18|WideOr2~0 .lut_mask = 64'h585858580E0E0E0E;
+defparam \BCD_CONVERT|A18|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N15
+cyclonev_lcell_comb \BCD_CONVERT|A18|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr1~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( (\BCD_CONVERT|A15|WideOr1~0_combout  & !\BCD_CONVERT|A15|WideOr2~0_combout ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( (!\BCD_CONVERT|A15|WideOr2~0_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  & \BCD_CONVERT|A15|WideOr3~0_combout )) # (\BCD_CONVERT|A15|WideOr2~0_combout 
+//  & ((!\BCD_CONVERT|A15|WideOr3~0_combout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A18|WideOr1~0 .lut_mask = 64'h3434343444444444;
+defparam \BCD_CONVERT|A18|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N39
+cyclonev_lcell_comb \BCD_CONVERT|A18|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr3~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( (!\BCD_CONVERT|A15|WideOr2~0_combout  & !\BCD_CONVERT|A15|WideOr1~0_combout ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\BCD_CONVERT|A15|WideOr1~0_combout  $ (((!\BCD_CONVERT|A15|WideOr3~0_combout ) # (!\BCD_CONVERT|A15|WideOr2~0_combout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(!\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A18|WideOr3~0 .lut_mask = 64'h05FA05FAF000F000;
+defparam \BCD_CONVERT|A18|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N27
+cyclonev_lcell_comb \BCD_CONVERT|A21|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr1~0_combout  = ( \BCD_CONVERT|A18|WideOr3~0_combout  & ( (!\BCD_CONVERT|A18|WideOr2~0_combout  & \BCD_CONVERT|A18|WideOr1~0_combout ) ) ) # ( !\BCD_CONVERT|A18|WideOr3~0_combout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & (\BCD_CONVERT|A18|WideOr2~0_combout )) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & 
+// (!\BCD_CONVERT|A18|WideOr2~0_combout  & \BCD_CONVERT|A18|WideOr1~0_combout )) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datab(!\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datac(gnd),
+	.datad(!\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A21|WideOr1~0 .lut_mask = 64'h2266226600CC00CC;
+defparam \BCD_CONVERT|A21|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N51
+cyclonev_lcell_comb \BCD_CONVERT|A21|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr3~0_combout  = ( \BCD_CONVERT|A18|WideOr3~0_combout  & ( (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & (!\BCD_CONVERT|A18|WideOr2~0_combout  $ (!\BCD_CONVERT|A18|WideOr1~0_combout 
+// ))) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & (!\BCD_CONVERT|A18|WideOr2~0_combout  & !\BCD_CONVERT|A18|WideOr1~0_combout )) ) ) # ( !\BCD_CONVERT|A18|WideOr3~0_combout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & ((\BCD_CONVERT|A18|WideOr1~0_combout ))) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & 
+// (!\BCD_CONVERT|A18|WideOr2~0_combout  & !\BCD_CONVERT|A18|WideOr1~0_combout )) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(!\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A21|WideOr3~0 .lut_mask = 64'h50AA50AA5AA05AA0;
+defparam \BCD_CONVERT|A21|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N24
+cyclonev_lcell_comb \BCD_CONVERT|A21|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr2~0_combout  = ( \BCD_CONVERT|A18|WideOr3~0_combout  & ( (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & (!\BCD_CONVERT|A18|WideOr2~0_combout  & !\BCD_CONVERT|A18|WideOr1~0_combout 
+// )) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & ((!\BCD_CONVERT|A18|WideOr2~0_combout ) # (!\BCD_CONVERT|A18|WideOr1~0_combout ))) ) ) # ( !\BCD_CONVERT|A18|WideOr3~0_combout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout  & \BCD_CONVERT|A18|WideOr1~0_combout ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datab(!\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A21|WideOr2~0 .lut_mask = 64'h0A0A0A0AD4D4D4D4;
+defparam \BCD_CONVERT|A21|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N6
+cyclonev_lcell_comb \BCD_CONVERT|A25|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr2~0_combout  = ( \BCD_CONVERT|A21|WideOr2~0_combout  & ( (!\BCD_CONVERT|A21|WideOr1~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & \BCD_CONVERT|A21|WideOr3~0_combout )) 
+// # (\BCD_CONVERT|A21|WideOr1~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & !\BCD_CONVERT|A21|WideOr3~0_combout )) ) ) # ( !\BCD_CONVERT|A21|WideOr2~0_combout  & ( 
+// !\BCD_CONVERT|A21|WideOr3~0_combout  $ (((!\BCD_CONVERT|A21|WideOr1~0_combout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datac(!\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A25|WideOr2~0 .lut_mask = 64'h4B4B4B4B42424242;
+defparam \BCD_CONVERT|A25|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N9
+cyclonev_lcell_comb \BCD_CONVERT|A25|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr1~0_combout  = ( \BCD_CONVERT|A21|WideOr2~0_combout  & ( (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & !\BCD_CONVERT|A21|WideOr3~0_combout ) ) ) # ( 
+// !\BCD_CONVERT|A21|WideOr2~0_combout  & ( (\BCD_CONVERT|A21|WideOr1~0_combout  & ((\BCD_CONVERT|A21|WideOr3~0_combout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datac(!\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A25|WideOr1~0 .lut_mask = 64'h15151515C0C0C0C0;
+defparam \BCD_CONVERT|A25|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N3
+cyclonev_lcell_comb \BCD_CONVERT|A25|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr3~0_combout  = ( \BCD_CONVERT|A21|WideOr2~0_combout  & ( (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & (!\BCD_CONVERT|A21|WideOr3~0_combout  $ (!\BCD_CONVERT|A21|WideOr1~0_combout 
+// ))) ) ) # ( !\BCD_CONVERT|A21|WideOr2~0_combout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  $ (!\BCD_CONVERT|A21|WideOr1~0_combout ) ) )
+
+	.dataa(!\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.datab(gnd),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datad(!\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A25|WideOr3~0 .lut_mask = 64'h0FF00FF050A050A0;
+defparam \BCD_CONVERT|A25|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N33
+cyclonev_lcell_comb \SEG0|WideOr6~0 (
+// Equation(s):
+// \SEG0|WideOr6~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr1~0_combout ) ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( !\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr1~0_combout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( (\BCD_CONVERT|A25|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr1~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.dataf(!\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr6~0 .extended_lut = "off";
+defparam \SEG0|WideOr6~0 .lut_mask = 64'h3030C3C300000C0C;
+defparam \SEG0|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N36
+cyclonev_lcell_comb \SEG0|WideOr5~0 (
+// Equation(s):
+// \SEG0|WideOr5~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( \BCD_CONVERT|A25|WideOr1~0_combout  ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( \BCD_CONVERT|A25|WideOr2~0_combout  ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( (!\BCD_CONVERT|A25|WideOr1~0_combout  & \BCD_CONVERT|A25|WideOr2~0_combout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( (\BCD_CONVERT|A25|WideOr1~0_combout  & \BCD_CONVERT|A25|WideOr2~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.dataf(!\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr5~0 .extended_lut = "off";
+defparam \SEG0|WideOr5~0 .lut_mask = 64'h003300CC00FF3333;
+defparam \SEG0|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N45
+cyclonev_lcell_comb \SEG0|WideOr4~0 (
+// Equation(s):
+// \SEG0|WideOr4~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( (\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr1~0_combout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( !\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr1~0_combout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( (\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr1~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.dataf(!\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr4~0 .extended_lut = "off";
+defparam \SEG0|WideOr4~0 .lut_mask = 64'h03030000C3C30303;
+defparam \SEG0|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N48
+cyclonev_lcell_comb \SEG0|WideOr3~0 (
+// Equation(s):
+// \SEG0|WideOr3~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( \BCD_CONVERT|A25|WideOr2~0_combout  ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( (\BCD_CONVERT|A25|WideOr1~0_combout  & !\BCD_CONVERT|A25|WideOr2~0_combout ) ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( !\BCD_CONVERT|A25|WideOr2~0_combout  ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( (!\BCD_CONVERT|A25|WideOr1~0_combout  & \BCD_CONVERT|A25|WideOr2~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.dataf(!\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr3~0 .extended_lut = "off";
+defparam \SEG0|WideOr3~0 .lut_mask = 64'h00CCFF00330000FF;
+defparam \SEG0|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N24
+cyclonev_lcell_comb \SEG0|WideOr2~0 (
+// Equation(s):
+// \SEG0|WideOr2~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( !\BCD_CONVERT|A25|WideOr1~0_combout  ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( (!\BCD_CONVERT|A25|WideOr1~0_combout ) # (!\BCD_CONVERT|A25|WideOr2~0_combout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( (!\BCD_CONVERT|A25|WideOr1~0_combout  & \BCD_CONVERT|A25|WideOr2~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datac(gnd),
+	.datad(!\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.dataf(!\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr2~0 .extended_lut = "off";
+defparam \SEG0|WideOr2~0 .lut_mask = 64'h00CCFFCC0000CCCC;
+defparam \SEG0|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N3
+cyclonev_lcell_comb \SEG0|WideOr1~0 (
+// Equation(s):
+// \SEG0|WideOr1~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( !\BCD_CONVERT|A25|WideOr1~0_combout  ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( (!\BCD_CONVERT|A25|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr1~0_combout ) ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout  & ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( !\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr1~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datad(gnd),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.dataf(!\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr1~0 .extended_lut = "off";
+defparam \SEG0|WideOr1~0 .lut_mask = 64'h0000C3C3C0C0F0F0;
+defparam \SEG0|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N6
+cyclonev_lcell_comb \SEG0|WideOr0~0 (
+// Equation(s):
+// \SEG0|WideOr0~0_combout  = ( \BCD_CONVERT|A25|WideOr3~0_combout  & ( (!\BCD_CONVERT|A25|WideOr2~0_combout ) # ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ) # (\BCD_CONVERT|A25|WideOr1~0_combout )) ) ) # 
+// ( !\BCD_CONVERT|A25|WideOr3~0_combout  & ( (!\BCD_CONVERT|A25|WideOr2~0_combout  & ((\BCD_CONVERT|A25|WideOr1~0_combout ))) # (\BCD_CONVERT|A25|WideOr2~0_combout  & ((!\BCD_CONVERT|A25|WideOr1~0_combout ) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_sumout ),
+	.datad(!\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG0|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG0|WideOr0~0 .extended_lut = "off";
+defparam \SEG0|WideOr0~0 .lut_mask = 64'h33CF33CFFCFFFCFF;
+defparam \SEG0|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N42
+cyclonev_lcell_comb \BCD_CONVERT|A25|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr0~0_combout  = ( \BCD_CONVERT|A21|WideOr2~0_combout  & ( !\BCD_CONVERT|A21|WideOr1~0_combout  $ (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout  & !\BCD_CONVERT|A21|WideOr3~0_combout 
+// ))) ) ) # ( !\BCD_CONVERT|A21|WideOr2~0_combout  & ( \BCD_CONVERT|A21|WideOr1~0_combout  ) )
+
+	.dataa(gnd),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5_sumout ),
+	.datac(!\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.datad(!\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A25|WideOr0~0 .lut_mask = 64'h00FF00FF3FC03FC0;
+defparam \BCD_CONVERT|A25|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N42
+cyclonev_lcell_comb \BCD_CONVERT|A17|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr1~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )))) ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ))) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout )))) ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A17|WideOr1~0 .lut_mask = 64'h000040A00015AA00;
+defparam \BCD_CONVERT|A17|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N54
+cyclonev_lcell_comb \BCD_CONVERT|A17|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr3~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout )) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ))))) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )))) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout )) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout )))) ) ) ) # ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  $ 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) ) ) ) # ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )))) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout )))) ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A17|WideOr3~0 .lut_mask = 64'h50FDAA552B400502;
+defparam \BCD_CONVERT|A17|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N48
+cyclonev_lcell_comb \BCD_CONVERT|A17|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout )))) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) # 
+// ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )))) ) ) ) # ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ))) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout )))) ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A17|WideOr2~0 .lut_mask = 64'h0557AA0055EA0055;
+defparam \BCD_CONVERT|A17|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N48
+cyclonev_lcell_comb \BCD_CONVERT|A18|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr0~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\BCD_CONVERT|A15|WideOr2~0_combout  $ (!\BCD_CONVERT|A15|WideOr1~0_combout ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout  & ( !\BCD_CONVERT|A15|WideOr1~0_combout  $ (((!\BCD_CONVERT|A15|WideOr2~0_combout ) # (!\BCD_CONVERT|A15|WideOr3~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datac(!\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datad(!\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A18|WideOr0~0 .lut_mask = 64'h03FC03FC33CC33CC;
+defparam \BCD_CONVERT|A18|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N18
+cyclonev_lcell_comb \BCD_CONVERT|A20|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr2~0_combout  = ( \BCD_CONVERT|A18|WideOr0~0_combout  & ( (\BCD_CONVERT|A17|WideOr3~0_combout  & ((!\BCD_CONVERT|A17|WideOr1~0_combout ) # (!\BCD_CONVERT|A17|WideOr2~0_combout ))) ) ) # ( !\BCD_CONVERT|A18|WideOr0~0_combout  & ( 
+// (!\BCD_CONVERT|A17|WideOr1~0_combout  & (\BCD_CONVERT|A17|WideOr3~0_combout  & !\BCD_CONVERT|A17|WideOr2~0_combout )) # (\BCD_CONVERT|A17|WideOr1~0_combout  & (!\BCD_CONVERT|A17|WideOr3~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A17|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A20|WideOr2~0 .lut_mask = 64'h6464646432323232;
+defparam \BCD_CONVERT|A20|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N45
+cyclonev_lcell_comb \BCD_CONVERT|A20|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr3~0_combout  = ( \BCD_CONVERT|A18|WideOr0~0_combout  & ( (!\BCD_CONVERT|A17|WideOr1~0_combout  & !\BCD_CONVERT|A17|WideOr2~0_combout ) ) ) # ( !\BCD_CONVERT|A18|WideOr0~0_combout  & ( !\BCD_CONVERT|A17|WideOr1~0_combout  $ 
+// (((!\BCD_CONVERT|A17|WideOr3~0_combout ) # (!\BCD_CONVERT|A17|WideOr2~0_combout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.datad(!\BCD_CONVERT|A17|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A20|WideOr3~0 .lut_mask = 64'h555A555AAA00AA00;
+defparam \BCD_CONVERT|A20|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N21
+cyclonev_lcell_comb \BCD_CONVERT|A20|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr1~0_combout  = ( \BCD_CONVERT|A18|WideOr0~0_combout  & ( (\BCD_CONVERT|A17|WideOr1~0_combout  & !\BCD_CONVERT|A17|WideOr2~0_combout ) ) ) # ( !\BCD_CONVERT|A18|WideOr0~0_combout  & ( (!\BCD_CONVERT|A17|WideOr3~0_combout  & 
+// ((\BCD_CONVERT|A17|WideOr2~0_combout ))) # (\BCD_CONVERT|A17|WideOr3~0_combout  & (\BCD_CONVERT|A17|WideOr1~0_combout  & !\BCD_CONVERT|A17|WideOr2~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A17|WideOr2~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A20|WideOr1~0 .lut_mask = 64'h1C1C1C1C50505050;
+defparam \BCD_CONVERT|A20|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N0
+cyclonev_lcell_comb \BCD_CONVERT|A21|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr0~0_combout  = ( \BCD_CONVERT|A18|WideOr3~0_combout  & ( !\BCD_CONVERT|A18|WideOr2~0_combout  $ (!\BCD_CONVERT|A18|WideOr1~0_combout ) ) ) # ( !\BCD_CONVERT|A18|WideOr3~0_combout  & ( !\BCD_CONVERT|A18|WideOr1~0_combout  $ 
+// (((!\BCD_CONVERT|A18|WideOr2~0_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9_sumout ),
+	.datad(!\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A21|WideOr0~0 .lut_mask = 64'h03FC03FC33CC33CC;
+defparam \BCD_CONVERT|A21|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N57
+cyclonev_lcell_comb \BCD_CONVERT|A24|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr3~0_combout  = ( \BCD_CONVERT|A21|WideOr0~0_combout  & ( (!\BCD_CONVERT|A20|WideOr2~0_combout  & !\BCD_CONVERT|A20|WideOr1~0_combout ) ) ) # ( !\BCD_CONVERT|A21|WideOr0~0_combout  & ( !\BCD_CONVERT|A20|WideOr1~0_combout  $ 
+// (((!\BCD_CONVERT|A20|WideOr2~0_combout ) # (!\BCD_CONVERT|A20|WideOr3~0_combout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.datad(!\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr3~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A24|WideOr3~0 .lut_mask = 64'h05FA05FAAA00AA00;
+defparam \BCD_CONVERT|A24|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N0
+cyclonev_lcell_comb \BCD_CONVERT|A24|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr1~0_combout  = ( \BCD_CONVERT|A20|WideOr1~0_combout  & ( !\BCD_CONVERT|A20|WideOr2~0_combout  $ (((!\BCD_CONVERT|A20|WideOr3~0_combout  & !\BCD_CONVERT|A21|WideOr0~0_combout ))) ) ) # ( !\BCD_CONVERT|A20|WideOr1~0_combout  & ( 
+// (\BCD_CONVERT|A20|WideOr2~0_combout  & (!\BCD_CONVERT|A20|WideOr3~0_combout  & !\BCD_CONVERT|A21|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(!\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr1~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A24|WideOr1~0 .lut_mask = 64'h404040406A6A6A6A;
+defparam \BCD_CONVERT|A24|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N3
+cyclonev_lcell_comb \BCD_CONVERT|A24|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr2~0_combout  = ( \BCD_CONVERT|A20|WideOr1~0_combout  & ( (!\BCD_CONVERT|A20|WideOr3~0_combout  & ((!\BCD_CONVERT|A21|WideOr0~0_combout ))) # (\BCD_CONVERT|A20|WideOr3~0_combout  & (!\BCD_CONVERT|A20|WideOr2~0_combout  & 
+// \BCD_CONVERT|A21|WideOr0~0_combout )) ) ) # ( !\BCD_CONVERT|A20|WideOr1~0_combout  & ( (\BCD_CONVERT|A20|WideOr3~0_combout  & ((!\BCD_CONVERT|A20|WideOr2~0_combout ) # (\BCD_CONVERT|A21|WideOr0~0_combout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(!\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr2~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A24|WideOr2~0 .lut_mask = 64'h23232323C2C2C2C2;
+defparam \BCD_CONVERT|A24|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N9
+cyclonev_lcell_comb \SEG1|WideOr6~0 (
+// Equation(s):
+// \SEG1|WideOr6~0_combout  = ( \BCD_CONVERT|A24|WideOr2~0_combout  & ( (!\BCD_CONVERT|A25|WideOr0~0_combout  $ (!\BCD_CONVERT|A24|WideOr1~0_combout )) # (\BCD_CONVERT|A24|WideOr3~0_combout ) ) ) # ( !\BCD_CONVERT|A24|WideOr2~0_combout  & ( 
+// (!\BCD_CONVERT|A25|WideOr0~0_combout ) # (!\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A24|WideOr1~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datad(!\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr6~0 .extended_lut = "off";
+defparam \SEG1|WideOr6~0 .lut_mask = 64'hAFFAAFFA5FAF5FAF;
+defparam \SEG1|WideOr6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N12
+cyclonev_lcell_comb \SEG1|WideOr5~0 (
+// Equation(s):
+// \SEG1|WideOr5~0_combout  = ( \BCD_CONVERT|A24|WideOr2~0_combout  & ( (!\BCD_CONVERT|A24|WideOr1~0_combout  & (!\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// ((!\BCD_CONVERT|A25|WideOr0~0_combout ) # (\BCD_CONVERT|A24|WideOr3~0_combout ))) ) ) # ( !\BCD_CONVERT|A24|WideOr2~0_combout  & ( (\BCD_CONVERT|A24|WideOr1~0_combout  & (\BCD_CONVERT|A24|WideOr3~0_combout  & \BCD_CONVERT|A25|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr5~0 .extended_lut = "off";
+defparam \SEG1|WideOr5~0 .lut_mask = 64'h0011001177997799;
+defparam \SEG1|WideOr5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N18
+cyclonev_lcell_comb \SEG1|WideOr4~0 (
+// Equation(s):
+// \SEG1|WideOr4~0_combout  = ( \BCD_CONVERT|A24|WideOr2~0_combout  & ( (\BCD_CONVERT|A24|WideOr1~0_combout  & ((!\BCD_CONVERT|A25|WideOr0~0_combout ) # (\BCD_CONVERT|A24|WideOr3~0_combout ))) ) ) # ( !\BCD_CONVERT|A24|WideOr2~0_combout  & ( 
+// (!\BCD_CONVERT|A24|WideOr1~0_combout  & (\BCD_CONVERT|A24|WideOr3~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(gnd),
+	.datad(!\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr4~0 .extended_lut = "off";
+defparam \SEG1|WideOr4~0 .lut_mask = 64'h2200220055115511;
+defparam \SEG1|WideOr4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N21
+cyclonev_lcell_comb \SEG1|WideOr3~0 (
+// Equation(s):
+// \SEG1|WideOr3~0_combout  = ( \BCD_CONVERT|A24|WideOr2~0_combout  & ( (!\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A25|WideOr0~0_combout ) # (\BCD_CONVERT|A24|WideOr1~0_combout ))) # (\BCD_CONVERT|A24|WideOr3~0_combout  & 
+// ((!\BCD_CONVERT|A25|WideOr0~0_combout ))) ) ) # ( !\BCD_CONVERT|A24|WideOr2~0_combout  & ( (!\BCD_CONVERT|A24|WideOr3~0_combout  & ((!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (\BCD_CONVERT|A24|WideOr3~0_combout  & ((!\BCD_CONVERT|A24|WideOr1~0_combout ) # 
+// (\BCD_CONVERT|A25|WideOr0~0_combout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr3~0 .extended_lut = "off";
+defparam \SEG1|WideOr3~0 .lut_mask = 64'hE3E3E3E37C7C7C7C;
+defparam \SEG1|WideOr3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N54
+cyclonev_lcell_comb \SEG1|WideOr2~0 (
+// Equation(s):
+// \SEG1|WideOr2~0_combout  = ( \BCD_CONVERT|A24|WideOr2~0_combout  & ( ((\BCD_CONVERT|A24|WideOr3~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout )) # (\BCD_CONVERT|A24|WideOr1~0_combout ) ) ) # ( !\BCD_CONVERT|A24|WideOr2~0_combout  & ( 
+// (!\BCD_CONVERT|A25|WideOr0~0_combout ) # ((\BCD_CONVERT|A24|WideOr3~0_combout  & \BCD_CONVERT|A24|WideOr1~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datad(!\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr2~0 .extended_lut = "off";
+defparam \SEG1|WideOr2~0 .lut_mask = 64'hFF03FF033F0F3F0F;
+defparam \SEG1|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N57
+cyclonev_lcell_comb \SEG1|WideOr1~0 (
+// Equation(s):
+// \SEG1|WideOr1~0_combout  = ( \BCD_CONVERT|A24|WideOr2~0_combout  & ( (!\BCD_CONVERT|A25|WideOr0~0_combout ) # (!\BCD_CONVERT|A24|WideOr1~0_combout  $ (\BCD_CONVERT|A24|WideOr3~0_combout )) ) ) # ( !\BCD_CONVERT|A24|WideOr2~0_combout  & ( 
+// ((!\BCD_CONVERT|A24|WideOr3~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout )) # (\BCD_CONVERT|A24|WideOr1~0_combout ) ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr1~0 .extended_lut = "off";
+defparam \SEG1|WideOr1~0 .lut_mask = 64'hD5D5D5D5F9F9F9F9;
+defparam \SEG1|WideOr1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X85_Y9_N15
+cyclonev_lcell_comb \SEG1|WideOr0~0 (
+// Equation(s):
+// \SEG1|WideOr0~0_combout  = ( \BCD_CONVERT|A24|WideOr2~0_combout  & ( (!\BCD_CONVERT|A24|WideOr1~0_combout  & ((!\BCD_CONVERT|A24|WideOr3~0_combout ) # (!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A25|WideOr0~0_combout ) # (\BCD_CONVERT|A24|WideOr3~0_combout ))) ) ) # ( !\BCD_CONVERT|A24|WideOr2~0_combout  & ( (\BCD_CONVERT|A24|WideOr3~0_combout ) # (\BCD_CONVERT|A24|WideOr1~0_combout ) ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(!\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG1|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG1|WideOr0~0 .extended_lut = "off";
+defparam \SEG1|WideOr0~0 .lut_mask = 64'h77777777BDBDBDBD;
+defparam \SEG1|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N36
+cyclonev_lcell_comb \BCD_CONVERT|A24|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr0~0_combout  = ( \BCD_CONVERT|A20|WideOr2~0_combout  & ( \BCD_CONVERT|A20|WideOr1~0_combout  & ( (!\BCD_CONVERT|A21|WideOr0~0_combout  & !\BCD_CONVERT|A20|WideOr3~0_combout ) ) ) ) # ( !\BCD_CONVERT|A20|WideOr2~0_combout  & ( 
+// \BCD_CONVERT|A20|WideOr1~0_combout  ) ) # ( \BCD_CONVERT|A20|WideOr2~0_combout  & ( !\BCD_CONVERT|A20|WideOr1~0_combout  & ( (\BCD_CONVERT|A20|WideOr3~0_combout ) # (\BCD_CONVERT|A21|WideOr0~0_combout ) ) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.datae(!\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.dataf(!\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A24|WideOr0~0 .lut_mask = 64'h000033FFFFFFCC00;
+defparam \BCD_CONVERT|A24|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X79_Y9_N54
+cyclonev_lcell_comb \BCD_CONVERT|A20|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr0~0_combout  = ( \BCD_CONVERT|A18|WideOr0~0_combout  & ( !\BCD_CONVERT|A17|WideOr1~0_combout  $ (!\BCD_CONVERT|A17|WideOr2~0_combout ) ) ) # ( !\BCD_CONVERT|A18|WideOr0~0_combout  & ( !\BCD_CONVERT|A17|WideOr1~0_combout  $ 
+// (((!\BCD_CONVERT|A17|WideOr3~0_combout ) # (!\BCD_CONVERT|A17|WideOr2~0_combout ))) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.datac(!\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(!\BCD_CONVERT|A17|WideOr2~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A20|WideOr0~0 .lut_mask = 64'h0F3C0F3C0FF00FF0;
+defparam \BCD_CONVERT|A20|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X74_Y7_N36
+cyclonev_lcell_comb \BCD_CONVERT|A17|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr0~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  ) ) ) # ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout )))) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout )))) ) ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & ( 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17_sumout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datae(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A17|WideOr0~0 .lut_mask = 64'h00FF15A000FF5500;
+defparam \BCD_CONVERT|A17|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N48
+cyclonev_lcell_comb \BCD_CONVERT|A7|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A7|WideOr0~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  ) ) # ( 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout  & 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ) ) )
+
+	.dataa(gnd),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A7|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A7|WideOr0~0 .lut_mask = 64'h0303030333333333;
+defparam \BCD_CONVERT|A7|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N57
+cyclonev_lcell_comb \BCD_CONVERT|A9|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr0~0_combout  = ( \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout )) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ))) ) ) # ( !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout  & ( 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ) ) )
+
+	.dataa(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29_sumout ),
+	.datab(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25_sumout ),
+	.datac(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A9|WideOr0~0 .lut_mask = 64'h0A0A0A0A71717171;
+defparam \BCD_CONVERT|A9|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N51
+cyclonev_lcell_comb \BCD_CONVERT|A12|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr0~0_combout  = ( \BCD_CONVERT|A9|WideOr3~0_combout  & ( !\BCD_CONVERT|A9|WideOr1~0_combout  $ (!\BCD_CONVERT|A9|WideOr2~0_combout ) ) ) # ( !\BCD_CONVERT|A9|WideOr3~0_combout  & ( !\BCD_CONVERT|A9|WideOr1~0_combout  $ 
+// (((!\BCD_CONVERT|A9|WideOr2~0_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ))) ) )
+
+	.dataa(!\BCD_CONVERT|A9|WideOr1~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datad(!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21_sumout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A12|WideOr0~0 .lut_mask = 64'h555A555A5A5A5A5A;
+defparam \BCD_CONVERT|A12|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X75_Y9_N54
+cyclonev_lcell_comb \BCD_CONVERT|A14|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A14|WideOr0~0_combout  = ( \BCD_CONVERT|A12|WideOr0~0_combout  & ( \BCD_CONVERT|A7|WideOr0~0_combout  ) ) # ( !\BCD_CONVERT|A12|WideOr0~0_combout  & ( (\BCD_CONVERT|A7|WideOr0~0_combout  & \BCD_CONVERT|A9|WideOr0~0_combout ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(!\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A14|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A14|WideOr0~0 .lut_mask = 64'h000F000F0F0F0F0F;
+defparam \BCD_CONVERT|A14|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N12
+cyclonev_lcell_comb \SEG2|Decoder0~1 (
+// Equation(s):
+// \SEG2|Decoder0~1_combout  = ( \BCD_CONVERT|A14|WideOr0~0_combout  & ( (\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A20|WideOr0~0_combout  & !\BCD_CONVERT|A17|WideOr0~0_combout )) ) ) # ( !\BCD_CONVERT|A14|WideOr0~0_combout  & ( 
+// (\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A20|WideOr0~0_combout  & !\BCD_CONVERT|A17|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datad(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~1 .extended_lut = "off";
+defparam \SEG2|Decoder0~1 .lut_mask = 64'h5000500005000500;
+defparam \SEG2|Decoder0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N15
+cyclonev_lcell_comb \SEG2|Decoder0~0 (
+// Equation(s):
+// \SEG2|Decoder0~0_combout  = ( \BCD_CONVERT|A20|WideOr0~0_combout  & ( (!\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A14|WideOr0~0_combout  & \BCD_CONVERT|A17|WideOr0~0_combout )) ) ) # ( !\BCD_CONVERT|A20|WideOr0~0_combout  & ( 
+// (!\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A14|WideOr0~0_combout  & \BCD_CONVERT|A17|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datac(gnd),
+	.datad(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~0 .extended_lut = "off";
+defparam \SEG2|Decoder0~0 .lut_mask = 64'h0088008800220022;
+defparam \SEG2|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N18
+cyclonev_lcell_comb \SEG2|WideOr6 (
+// Equation(s):
+// \SEG2|WideOr6~combout  = ( \SEG2|Decoder0~0_combout  ) # ( !\SEG2|Decoder0~0_combout  & ( \SEG2|Decoder0~1_combout  ) )
+
+	.dataa(gnd),
+	.datab(!\SEG2|Decoder0~1_combout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SEG2|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|WideOr6~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|WideOr6 .extended_lut = "off";
+defparam \SEG2|WideOr6 .lut_mask = 64'h33333333FFFFFFFF;
+defparam \SEG2|WideOr6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N57
+cyclonev_lcell_comb \SEG2|Decoder0~2 (
+// Equation(s):
+// \SEG2|Decoder0~2_combout  = ( \BCD_CONVERT|A20|WideOr0~0_combout  & ( (\BCD_CONVERT|A14|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~0_combout  & \BCD_CONVERT|A24|WideOr0~0_combout )) ) ) # ( !\BCD_CONVERT|A20|WideOr0~0_combout  & ( 
+// (!\BCD_CONVERT|A14|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~0_combout  & \BCD_CONVERT|A24|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datad(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~2 .extended_lut = "off";
+defparam \SEG2|Decoder0~2 .lut_mask = 64'h000A000A00050005;
+defparam \SEG2|Decoder0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N30
+cyclonev_lcell_comb \SEG2|WideOr5 (
+// Equation(s):
+// \SEG2|WideOr5~combout  = ( \BCD_CONVERT|A20|WideOr0~0_combout  & ( ((!\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A14|WideOr0~0_combout  & \BCD_CONVERT|A17|WideOr0~0_combout ))) # (\SEG2|Decoder0~2_combout ) ) ) # ( 
+// !\BCD_CONVERT|A20|WideOr0~0_combout  & ( \SEG2|Decoder0~2_combout  ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(!\SEG2|Decoder0~2_combout ),
+	.datac(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datad(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|WideOr5~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|WideOr5 .extended_lut = "off";
+defparam \SEG2|WideOr5 .lut_mask = 64'h3333333333B333B3;
+defparam \SEG2|WideOr5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N6
+cyclonev_lcell_comb \SEG2|Decoder0~3 (
+// Equation(s):
+// \SEG2|Decoder0~3_combout  = ( \BCD_CONVERT|A20|WideOr0~0_combout  & ( (!\BCD_CONVERT|A17|WideOr0~0_combout  & (!\BCD_CONVERT|A14|WideOr0~0_combout  & !\BCD_CONVERT|A24|WideOr0~0_combout )) ) ) # ( !\BCD_CONVERT|A20|WideOr0~0_combout  & ( 
+// (\BCD_CONVERT|A17|WideOr0~0_combout  & (\BCD_CONVERT|A14|WideOr0~0_combout  & !\BCD_CONVERT|A24|WideOr0~0_combout )) ) )
+
+	.dataa(gnd),
+	.datab(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datac(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datad(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~3 .extended_lut = "off";
+defparam \SEG2|Decoder0~3 .lut_mask = 64'h03000300C000C000;
+defparam \SEG2|Decoder0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N33
+cyclonev_lcell_comb \SEG2|Decoder0~4 (
+// Equation(s):
+// \SEG2|Decoder0~4_combout  = ( \BCD_CONVERT|A20|WideOr0~0_combout  & ( (\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A14|WideOr0~0_combout  & \BCD_CONVERT|A17|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datad(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~4 .extended_lut = "off";
+defparam \SEG2|Decoder0~4 .lut_mask = 64'h0000000000500050;
+defparam \SEG2|Decoder0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N42
+cyclonev_lcell_comb \SEG2|Decoder0~5 (
+// Equation(s):
+// \SEG2|Decoder0~5_combout  = ( \BCD_CONVERT|A14|WideOr0~0_combout  & ( (!\BCD_CONVERT|A20|WideOr0~0_combout  & (\BCD_CONVERT|A24|WideOr0~0_combout  & !\BCD_CONVERT|A17|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datad(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~5 .extended_lut = "off";
+defparam \SEG2|Decoder0~5 .lut_mask = 64'h000000000A000A00;
+defparam \SEG2|Decoder0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N9
+cyclonev_lcell_comb \SEG2|WideOr2~0 (
+// Equation(s):
+// \SEG2|WideOr2~0_combout  = ( !\SEG2|Decoder0~0_combout  & ( (!\SEG2|Decoder0~4_combout  & (!\SEG2|Decoder0~1_combout  & !\SEG2|Decoder0~5_combout )) ) )
+
+	.dataa(!\SEG2|Decoder0~4_combout ),
+	.datab(gnd),
+	.datac(!\SEG2|Decoder0~1_combout ),
+	.datad(!\SEG2|Decoder0~5_combout ),
+	.datae(gnd),
+	.dataf(!\SEG2|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|WideOr2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|WideOr2~0 .extended_lut = "off";
+defparam \SEG2|WideOr2~0 .lut_mask = 64'hA000A00000000000;
+defparam \SEG2|WideOr2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N45
+cyclonev_lcell_comb \SEG2|Decoder0~6 (
+// Equation(s):
+// \SEG2|Decoder0~6_combout  = ( \BCD_CONVERT|A14|WideOr0~0_combout  & ( (!\BCD_CONVERT|A20|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~0_combout  & \BCD_CONVERT|A24|WideOr0~0_combout )) ) ) # ( !\BCD_CONVERT|A14|WideOr0~0_combout  & ( 
+// (\BCD_CONVERT|A20|WideOr0~0_combout  & (!\BCD_CONVERT|A17|WideOr0~0_combout  & \BCD_CONVERT|A24|WideOr0~0_combout )) ) )
+
+	.dataa(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datad(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datae(gnd),
+	.dataf(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|Decoder0~6_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~6 .extended_lut = "off";
+defparam \SEG2|Decoder0~6 .lut_mask = 64'h00500050000A000A;
+defparam \SEG2|Decoder0~6 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N48
+cyclonev_lcell_comb \SEG2|WideOr2 (
+// Equation(s):
+// \SEG2|WideOr2~combout  = ( \SEG2|Decoder0~2_combout  & ( \SEG2|Decoder0~0_combout  ) ) # ( !\SEG2|Decoder0~2_combout  & ( \SEG2|Decoder0~0_combout  ) ) # ( \SEG2|Decoder0~2_combout  & ( !\SEG2|Decoder0~0_combout  ) ) # ( !\SEG2|Decoder0~2_combout  & ( 
+// !\SEG2|Decoder0~0_combout  & ( (((\SEG2|Decoder0~1_combout ) # (\SEG2|Decoder0~4_combout )) # (\SEG2|Decoder0~6_combout )) # (\SEG2|Decoder0~5_combout ) ) ) )
+
+	.dataa(!\SEG2|Decoder0~5_combout ),
+	.datab(!\SEG2|Decoder0~6_combout ),
+	.datac(!\SEG2|Decoder0~4_combout ),
+	.datad(!\SEG2|Decoder0~1_combout ),
+	.datae(!\SEG2|Decoder0~2_combout ),
+	.dataf(!\SEG2|Decoder0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|WideOr2~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|WideOr2 .extended_lut = "off";
+defparam \SEG2|WideOr2 .lut_mask = 64'h7FFFFFFFFFFFFFFF;
+defparam \SEG2|WideOr2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N54
+cyclonev_lcell_comb \SEG2|WideOr1 (
+// Equation(s):
+// \SEG2|WideOr1~combout  = ( \SEG2|Decoder0~3_combout  ) # ( !\SEG2|Decoder0~3_combout  & ( ((\SEG2|Decoder0~6_combout ) # (\SEG2|Decoder0~4_combout )) # (\SEG2|Decoder0~1_combout ) ) )
+
+	.dataa(gnd),
+	.datab(!\SEG2|Decoder0~1_combout ),
+	.datac(!\SEG2|Decoder0~4_combout ),
+	.datad(!\SEG2|Decoder0~6_combout ),
+	.datae(gnd),
+	.dataf(!\SEG2|Decoder0~3_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|WideOr1~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|WideOr1 .extended_lut = "off";
+defparam \SEG2|WideOr1 .lut_mask = 64'h3FFF3FFFFFFFFFFF;
+defparam \SEG2|WideOr1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y13_N24
+cyclonev_lcell_comb \SEG2|WideOr0 (
+// Equation(s):
+// \SEG2|WideOr0~combout  = ( \BCD_CONVERT|A24|WideOr0~0_combout  & ( \BCD_CONVERT|A20|WideOr0~0_combout  & ( (\SEG2|Decoder0~1_combout ) # (\SEG2|Decoder0~4_combout ) ) ) ) # ( !\BCD_CONVERT|A24|WideOr0~0_combout  & ( \BCD_CONVERT|A20|WideOr0~0_combout  & ( 
+// (((!\BCD_CONVERT|A17|WideOr0~0_combout  & \BCD_CONVERT|A14|WideOr0~0_combout )) # (\SEG2|Decoder0~1_combout )) # (\SEG2|Decoder0~4_combout ) ) ) ) # ( \BCD_CONVERT|A24|WideOr0~0_combout  & ( !\BCD_CONVERT|A20|WideOr0~0_combout  & ( 
+// (\SEG2|Decoder0~1_combout ) # (\SEG2|Decoder0~4_combout ) ) ) ) # ( !\BCD_CONVERT|A24|WideOr0~0_combout  & ( !\BCD_CONVERT|A20|WideOr0~0_combout  & ( (((!\BCD_CONVERT|A17|WideOr0~0_combout  & !\BCD_CONVERT|A14|WideOr0~0_combout )) # 
+// (\SEG2|Decoder0~1_combout )) # (\SEG2|Decoder0~4_combout ) ) ) )
+
+	.dataa(!\SEG2|Decoder0~4_combout ),
+	.datab(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datac(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.datad(!\SEG2|Decoder0~1_combout ),
+	.datae(!\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.dataf(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SEG2|WideOr0~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SEG2|WideOr0 .extended_lut = "off";
+defparam \SEG2|WideOr0 .lut_mask = 64'hD5FF55FF5DFF55FF;
+defparam \SEG2|WideOr0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X83_Y10_N30
+cyclonev_lcell_comb \BCD_CONVERT|A23|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A23|WideOr0~0_combout  = ( !\BCD_CONVERT|A14|WideOr0~0_combout  & ( \BCD_CONVERT|A20|WideOr0~0_combout  ) ) # ( \BCD_CONVERT|A14|WideOr0~0_combout  & ( !\BCD_CONVERT|A20|WideOr0~0_combout  & ( !\BCD_CONVERT|A17|WideOr0~0_combout  ) ) ) # ( 
+// !\BCD_CONVERT|A14|WideOr0~0_combout  & ( !\BCD_CONVERT|A20|WideOr0~0_combout  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datad(gnd),
+	.datae(!\BCD_CONVERT|A14|WideOr0~0_combout ),
+	.dataf(!\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\BCD_CONVERT|A23|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A23|WideOr0~0 .extended_lut = "off";
+defparam \BCD_CONVERT|A23|WideOr0~0 .lut_mask = 64'hFFFFF0F0FFFF0000;
+defparam \BCD_CONVERT|A23|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: IOIBUF_X32_Y0_N1
+cyclonev_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N57
+cyclonev_lcell_comb \SPI_DAC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_DAC|clk_1MHz~0_combout  = !\SPI_DAC|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_DAC|clk_1MHz~q ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|clk_1MHz~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~0 .extended_lut = "off";
+defparam \SPI_DAC|clk_1MHz~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;
+defparam \SPI_DAC|clk_1MHz~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: CLKCTRL_G6
+cyclonev_clkena \CLOCK_50~inputCLKENA0 (
+	.inclk(\CLOCK_50~input_o ),
+	.ena(vcc),
+	.outclk(\CLOCK_50~inputCLKENA0_outclk ),
+	.enaout());
+// synopsys translate_off
+defparam \CLOCK_50~inputCLKENA0 .clock_type = "global clock";
+defparam \CLOCK_50~inputCLKENA0 .disable_mode = "low";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_mode = "always enabled";
+defparam \CLOCK_50~inputCLKENA0 .ena_register_power_up = "high";
+defparam \CLOCK_50~inputCLKENA0 .test_syn = "high";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N40
+dffeas \SPI_ADC|ctr[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N28
+dffeas \SPI_ADC|ctr[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N39
+cyclonev_lcell_comb \SPI_ADC|Add0~0 (
+// Equation(s):
+// \SPI_ADC|Add0~0_combout  = ( \SPI_ADC|ctr [4] & ( \SPI_ADC|ctr [0] ) ) # ( \SPI_ADC|ctr [4] & ( !\SPI_ADC|ctr [0] & ( ((\SPI_ADC|ctr[2]~DUPLICATE_q ) # (\SPI_ADC|ctr[3]~DUPLICATE_q )) # (\SPI_ADC|ctr[1]~DUPLICATE_q ) ) ) ) # ( !\SPI_ADC|ctr [4] & ( 
+// !\SPI_ADC|ctr [0] & ( (!\SPI_ADC|ctr[1]~DUPLICATE_q  & (!\SPI_ADC|ctr[3]~DUPLICATE_q  & !\SPI_ADC|ctr[2]~DUPLICATE_q )) ) ) )
+
+	.dataa(!\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.datab(!\SPI_ADC|ctr[3]~DUPLICATE_q ),
+	.datac(gnd),
+	.datad(!\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.datae(!\SPI_ADC|ctr [4]),
+	.dataf(!\SPI_ADC|ctr [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Add0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~0 .extended_lut = "off";
+defparam \SPI_ADC|Add0~0 .lut_mask = 64'h880077FF0000FFFF;
+defparam \SPI_ADC|Add0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N41
+dffeas \SPI_ADC|ctr[4]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[4]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[4]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[4]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N32
+dffeas \SPI_ADC|ctr[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N43
+dffeas \SPI_ADC|ctr[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N30
+cyclonev_lcell_comb \SPI_ADC|ctr~2 (
+// Equation(s):
+// \SPI_ADC|ctr~2_combout  = ( \SPI_ADC|ctr [1] & ( \SPI_ADC|ctr [3] & ( \SPI_ADC|ctr[0]~DUPLICATE_q  ) ) ) # ( !\SPI_ADC|ctr [1] & ( \SPI_ADC|ctr [3] & ( !\SPI_ADC|ctr[0]~DUPLICATE_q  ) ) ) # ( \SPI_ADC|ctr [1] & ( !\SPI_ADC|ctr [3] & ( 
+// \SPI_ADC|ctr[0]~DUPLICATE_q  ) ) ) # ( !\SPI_ADC|ctr [1] & ( !\SPI_ADC|ctr [3] & ( (!\SPI_ADC|ctr[0]~DUPLICATE_q  & ((\SPI_ADC|ctr[4]~DUPLICATE_q ) # (\SPI_ADC|ctr[2]~DUPLICATE_q ))) ) ) )
+
+	.dataa(!\SPI_ADC|ctr[0]~DUPLICATE_q ),
+	.datab(gnd),
+	.datac(!\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.datad(!\SPI_ADC|ctr[4]~DUPLICATE_q ),
+	.datae(!\SPI_ADC|ctr [1]),
+	.dataf(!\SPI_ADC|ctr [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~2 .extended_lut = "off";
+defparam \SPI_ADC|ctr~2 .lut_mask = 64'h0AAA5555AAAA5555;
+defparam \SPI_ADC|ctr~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N31
+dffeas \SPI_ADC|ctr[1]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[1]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[1]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N27
+cyclonev_lcell_comb \SPI_ADC|ctr~1 (
+// Equation(s):
+// \SPI_ADC|ctr~1_combout  = ( !\SPI_ADC|ctr [0] & ( \SPI_ADC|ctr [3] ) ) # ( !\SPI_ADC|ctr [0] & ( !\SPI_ADC|ctr [3] & ( ((\SPI_ADC|ctr[2]~DUPLICATE_q ) # (\SPI_ADC|ctr[4]~DUPLICATE_q )) # (\SPI_ADC|ctr[1]~DUPLICATE_q ) ) ) )
+
+	.dataa(!\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.datab(!\SPI_ADC|ctr[4]~DUPLICATE_q ),
+	.datac(gnd),
+	.datad(!\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.datae(!\SPI_ADC|ctr [0]),
+	.dataf(!\SPI_ADC|ctr [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~1 .extended_lut = "off";
+defparam \SPI_ADC|ctr~1 .lut_mask = 64'h77FF0000FFFF0000;
+defparam \SPI_ADC|ctr~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N29
+dffeas \SPI_ADC|ctr[0]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[0]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[0]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[0]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N49
+dffeas \SPI_ADC|ctr[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N48
+cyclonev_lcell_comb \SPI_ADC|ctr~0 (
+// Equation(s):
+// \SPI_ADC|ctr~0_combout  = ( \SPI_ADC|ctr [2] & ( \SPI_ADC|ctr[1]~DUPLICATE_q  ) ) # ( \SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr[1]~DUPLICATE_q  & ( \SPI_ADC|ctr[0]~DUPLICATE_q  ) ) ) # ( !\SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr[1]~DUPLICATE_q  & ( 
+// (!\SPI_ADC|ctr[0]~DUPLICATE_q  & ((\SPI_ADC|ctr[4]~DUPLICATE_q ) # (\SPI_ADC|ctr[3]~DUPLICATE_q ))) ) ) )
+
+	.dataa(!\SPI_ADC|ctr[0]~DUPLICATE_q ),
+	.datab(!\SPI_ADC|ctr[3]~DUPLICATE_q ),
+	.datac(gnd),
+	.datad(!\SPI_ADC|ctr[4]~DUPLICATE_q ),
+	.datae(!\SPI_ADC|ctr [2]),
+	.dataf(!\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|ctr~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~0 .extended_lut = "off";
+defparam \SPI_ADC|ctr~0 .lut_mask = 64'h22AA55550000FFFF;
+defparam \SPI_ADC|ctr~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N50
+dffeas \SPI_ADC|ctr[2]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N42
+cyclonev_lcell_comb \SPI_ADC|Add0~1 (
+// Equation(s):
+// \SPI_ADC|Add0~1_combout  = ( \SPI_ADC|ctr [3] & ( \SPI_ADC|ctr [0] ) ) # ( \SPI_ADC|ctr [3] & ( !\SPI_ADC|ctr [0] & ( (\SPI_ADC|ctr [1]) # (\SPI_ADC|ctr[2]~DUPLICATE_q ) ) ) ) # ( !\SPI_ADC|ctr [3] & ( !\SPI_ADC|ctr [0] & ( (!\SPI_ADC|ctr[2]~DUPLICATE_q  
+// & !\SPI_ADC|ctr [1]) ) ) )
+
+	.dataa(!\SPI_ADC|ctr[2]~DUPLICATE_q ),
+	.datab(!\SPI_ADC|ctr [1]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SPI_ADC|ctr [3]),
+	.dataf(!\SPI_ADC|ctr [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Add0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~1 .extended_lut = "off";
+defparam \SPI_ADC|Add0~1 .lut_mask = 64'h888877770000FFFF;
+defparam \SPI_ADC|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N44
+dffeas \SPI_ADC|ctr[3]~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Add0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr[3]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[3]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[3]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N6
+cyclonev_lcell_comb \SPI_DAC|Equal0~0 (
+// Equation(s):
+// \SPI_DAC|Equal0~0_combout  = ( !\SPI_ADC|ctr [2] & ( !\SPI_ADC|ctr [0] & ( (!\SPI_ADC|ctr[3]~DUPLICATE_q  & (!\SPI_ADC|ctr[1]~DUPLICATE_q  & !\SPI_ADC|ctr [4])) ) ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|ctr[3]~DUPLICATE_q ),
+	.datac(!\SPI_ADC|ctr[1]~DUPLICATE_q ),
+	.datad(!\SPI_ADC|ctr [4]),
+	.datae(!\SPI_ADC|ctr [2]),
+	.dataf(!\SPI_ADC|ctr [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Equal0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal0~0 .extended_lut = "off";
+defparam \SPI_DAC|Equal0~0 .lut_mask = 64'hC000000000000000;
+defparam \SPI_DAC|Equal0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N53
+dffeas \SPI_DAC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(gnd),
+	.asdata(\SPI_DAC|clk_1MHz~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_DAC|Equal0~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_DAC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N48
+cyclonev_lcell_comb \SPI_DAC|Selector6~0 (
+// Equation(s):
+// \SPI_DAC|Selector6~0_combout  = !\SPI_DAC|state [2] $ (((!\SPI_DAC|state [0]) # (!\SPI_DAC|state [1])))
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|state [0]),
+	.datac(!\SPI_DAC|state [1]),
+	.datad(!\SPI_DAC|state [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector6~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector6~0 .lut_mask = 64'h03FC03FC03FC03FC;
+defparam \SPI_DAC|Selector6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N28
+dffeas \SPI_DAC|state[2] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector6~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N36
+cyclonev_lcell_comb \SPI_DAC|Selector5~0 (
+// Equation(s):
+// \SPI_DAC|Selector5~0_combout  = ( \SPI_DAC|state [0] & ( !\SPI_DAC|state[3]~DUPLICATE_q  $ (((!\SPI_DAC|state [2]) # (!\SPI_DAC|state [1]))) ) ) # ( !\SPI_DAC|state [0] & ( \SPI_DAC|state[3]~DUPLICATE_q  ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|state [2]),
+	.datac(!\SPI_DAC|state [1]),
+	.datad(!\SPI_DAC|state[3]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector5~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector5~0 .lut_mask = 64'h00FF00FF03FC03FC;
+defparam \SPI_DAC|Selector5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N10
+dffeas \SPI_DAC|state[3]~DUPLICATE (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector5~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state[3]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[3]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_DAC|state[3]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N30
+cyclonev_lcell_comb \SPI_DAC|Selector4~0 (
+// Equation(s):
+// \SPI_DAC|Selector4~0_combout  = ( \SPI_DAC|state [0] & ( !\SPI_DAC|state [4] $ (((!\SPI_DAC|state [1]) # ((!\SPI_DAC|state [2]) # (!\SPI_DAC|state[3]~DUPLICATE_q )))) ) ) # ( !\SPI_DAC|state [0] & ( (\SPI_DAC|state [4] & (((\SPI_DAC|state[3]~DUPLICATE_q ) 
+// # (\SPI_DAC|state [2])) # (\SPI_DAC|state [1]))) ) )
+
+	.dataa(!\SPI_DAC|state [1]),
+	.datab(!\SPI_DAC|state [2]),
+	.datac(!\SPI_DAC|state [4]),
+	.datad(!\SPI_DAC|state[3]~DUPLICATE_q ),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector4~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector4~0 .lut_mask = 64'h070F070F0F1E0F1E;
+defparam \SPI_DAC|Selector4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: MLABCELL_X59_Y2_N30
+cyclonev_lcell_comb \SPI_DAC|state[4]~feeder (
+// Equation(s):
+// \SPI_DAC|state[4]~feeder_combout  = ( \SPI_DAC|Selector4~0_combout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|Selector4~0_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|state[4]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|state[4]~feeder .extended_lut = "off";
+defparam \SPI_DAC|state[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_DAC|state[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X59_Y2_N31
+dffeas \SPI_DAC|state[4] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|state[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N11
+dffeas \SPI_DAC|state[3] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector5~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N57
+cyclonev_lcell_comb \SPI_DAC|Selector8~0 (
+// Equation(s):
+// \SPI_DAC|Selector8~0_combout  = ( \SPI_DAC|dac_start~q  & ( \SPI_DAC|state [2] & ( !\SPI_DAC|state [0] ) ) ) # ( !\SPI_DAC|dac_start~q  & ( \SPI_DAC|state [2] & ( !\SPI_DAC|state [0] ) ) ) # ( \SPI_DAC|dac_start~q  & ( !\SPI_DAC|state [2] & ( 
+// (!\SPI_DAC|state [0] & ((!\SPI_DAC|state [4]) # ((\SPI_DAC|state [1]) # (\SPI_DAC|state [3])))) ) ) ) # ( !\SPI_DAC|dac_start~q  & ( !\SPI_DAC|state [2] & ( (!\SPI_DAC|state [0] & ((\SPI_DAC|state [1]) # (\SPI_DAC|state [3]))) ) ) )
+
+	.dataa(!\SPI_DAC|state [4]),
+	.datab(!\SPI_DAC|state [0]),
+	.datac(!\SPI_DAC|state [3]),
+	.datad(!\SPI_DAC|state [1]),
+	.datae(!\SPI_DAC|dac_start~q ),
+	.dataf(!\SPI_DAC|state [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector8~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector8~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector8~0 .lut_mask = 64'h0CCC8CCCCCCCCCCC;
+defparam \SPI_DAC|Selector8~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N14
+dffeas \SPI_DAC|state[0] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector8~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[0] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N18
+cyclonev_lcell_comb \SPI_DAC|Selector7~0 (
+// Equation(s):
+// \SPI_DAC|Selector7~0_combout  = ( \SPI_DAC|state [0] & ( !\SPI_DAC|state [1] ) ) # ( !\SPI_DAC|state [0] & ( \SPI_DAC|state [1] ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_DAC|state [1]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector7~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector7~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector7~0 .lut_mask = 64'h0F0F0F0FF0F0F0F0;
+defparam \SPI_DAC|Selector7~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N5
+dffeas \SPI_DAC|state[1] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_DAC|Selector7~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[1] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N6
+cyclonev_lcell_comb \SPI_DAC|Selector9~0 (
+// Equation(s):
+// \SPI_DAC|Selector9~0_combout  = ( \SPI_DAC|dac_start~q  & ( \SPI_DAC|state [2] ) ) # ( !\SPI_DAC|dac_start~q  & ( \SPI_DAC|state [2] ) ) # ( \SPI_DAC|dac_start~q  & ( !\SPI_DAC|state [2] & ( (((!\SPI_DAC|state [4]) # (\SPI_DAC|state [0])) # 
+// (\SPI_DAC|state [3])) # (\SPI_DAC|state [1]) ) ) ) # ( !\SPI_DAC|dac_start~q  & ( !\SPI_DAC|state [2] & ( ((\SPI_DAC|state [0]) # (\SPI_DAC|state [3])) # (\SPI_DAC|state [1]) ) ) )
+
+	.dataa(!\SPI_DAC|state [1]),
+	.datab(!\SPI_DAC|state [3]),
+	.datac(!\SPI_DAC|state [4]),
+	.datad(!\SPI_DAC|state [0]),
+	.datae(!\SPI_DAC|dac_start~q ),
+	.dataf(!\SPI_DAC|state [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector9~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector9~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector9~0 .lut_mask = 64'h77FFF7FFFFFFFFFF;
+defparam \SPI_DAC|Selector9~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N8
+dffeas \SPI_DAC|dac_cs (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|Selector9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_cs .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N30
+cyclonev_lcell_comb \GEN_10K|Add0~41 (
+// Equation(s):
+// \GEN_10K|Add0~41_sumout  = SUM(( \GEN_10K|ctr [0] ) + ( VCC ) + ( !VCC ))
+// \GEN_10K|Add0~42  = CARRY(( \GEN_10K|ctr [0] ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|ctr [0]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~41_sumout ),
+	.cout(\GEN_10K|Add0~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~41 .extended_lut = "off";
+defparam \GEN_10K|Add0~41 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N32
+dffeas \GEN_10K|ctr[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~41_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[0] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N33
+cyclonev_lcell_comb \GEN_10K|Add0~45 (
+// Equation(s):
+// \GEN_10K|Add0~45_sumout  = SUM(( \GEN_10K|ctr [1] ) + ( VCC ) + ( \GEN_10K|Add0~42  ))
+// \GEN_10K|Add0~46  = CARRY(( \GEN_10K|ctr [1] ) + ( VCC ) + ( \GEN_10K|Add0~42  ))
+
+	.dataa(!\GEN_10K|ctr [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~45_sumout ),
+	.cout(\GEN_10K|Add0~46 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~45 .extended_lut = "off";
+defparam \GEN_10K|Add0~45 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N35
+dffeas \GEN_10K|ctr[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~45_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[1] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N36
+cyclonev_lcell_comb \GEN_10K|Add0~77 (
+// Equation(s):
+// \GEN_10K|Add0~77_sumout  = SUM(( \GEN_10K|ctr [2] ) + ( VCC ) + ( \GEN_10K|Add0~46  ))
+// \GEN_10K|Add0~78  = CARRY(( \GEN_10K|ctr [2] ) + ( VCC ) + ( \GEN_10K|Add0~46  ))
+
+	.dataa(!\GEN_10K|ctr [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~46 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~77_sumout ),
+	.cout(\GEN_10K|Add0~78 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~77 .extended_lut = "off";
+defparam \GEN_10K|Add0~77 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~77 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N51
+cyclonev_lcell_comb \GEN_10K|Add0~53 (
+// Equation(s):
+// \GEN_10K|Add0~53_sumout  = SUM(( \GEN_10K|ctr [7] ) + ( VCC ) + ( \GEN_10K|Add0~50  ))
+// \GEN_10K|Add0~54  = CARRY(( \GEN_10K|ctr [7] ) + ( VCC ) + ( \GEN_10K|Add0~50  ))
+
+	.dataa(!\GEN_10K|ctr [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~50 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~53_sumout ),
+	.cout(\GEN_10K|Add0~54 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~53 .extended_lut = "off";
+defparam \GEN_10K|Add0~53 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~53 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N54
+cyclonev_lcell_comb \GEN_10K|Add0~57 (
+// Equation(s):
+// \GEN_10K|Add0~57_sumout  = SUM(( \GEN_10K|ctr [8] ) + ( VCC ) + ( \GEN_10K|Add0~54  ))
+// \GEN_10K|Add0~58  = CARRY(( \GEN_10K|ctr [8] ) + ( VCC ) + ( \GEN_10K|Add0~54  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|ctr [8]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~54 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~57_sumout ),
+	.cout(\GEN_10K|Add0~58 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~57 .extended_lut = "off";
+defparam \GEN_10K|Add0~57 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~57 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N56
+dffeas \GEN_10K|ctr[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~57_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[8] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N57
+cyclonev_lcell_comb \GEN_10K|Add0~21 (
+// Equation(s):
+// \GEN_10K|Add0~21_sumout  = SUM(( \GEN_10K|ctr [9] ) + ( VCC ) + ( \GEN_10K|Add0~58  ))
+// \GEN_10K|Add0~22  = CARRY(( \GEN_10K|ctr [9] ) + ( VCC ) + ( \GEN_10K|Add0~58  ))
+
+	.dataa(!\GEN_10K|ctr [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~58 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~21_sumout ),
+	.cout(\GEN_10K|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~21 .extended_lut = "off";
+defparam \GEN_10K|Add0~21 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N58
+dffeas \GEN_10K|ctr[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[9] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N0
+cyclonev_lcell_comb \GEN_10K|Add0~25 (
+// Equation(s):
+// \GEN_10K|Add0~25_sumout  = SUM(( \GEN_10K|ctr [10] ) + ( VCC ) + ( \GEN_10K|Add0~22  ))
+// \GEN_10K|Add0~26  = CARRY(( \GEN_10K|ctr [10] ) + ( VCC ) + ( \GEN_10K|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|ctr [10]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~25_sumout ),
+	.cout(\GEN_10K|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~25 .extended_lut = "off";
+defparam \GEN_10K|Add0~25 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N2
+dffeas \GEN_10K|ctr[10] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[10] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N3
+cyclonev_lcell_comb \GEN_10K|Add0~61 (
+// Equation(s):
+// \GEN_10K|Add0~61_sumout  = SUM(( \GEN_10K|ctr [11] ) + ( VCC ) + ( \GEN_10K|Add0~26  ))
+// \GEN_10K|Add0~62  = CARRY(( \GEN_10K|ctr [11] ) + ( VCC ) + ( \GEN_10K|Add0~26  ))
+
+	.dataa(!\GEN_10K|ctr [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~61_sumout ),
+	.cout(\GEN_10K|Add0~62 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~61 .extended_lut = "off";
+defparam \GEN_10K|Add0~61 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~61 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N5
+dffeas \GEN_10K|ctr[11] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~61_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[11] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N6
+cyclonev_lcell_comb \GEN_10K|Add0~29 (
+// Equation(s):
+// \GEN_10K|Add0~29_sumout  = SUM(( \GEN_10K|ctr [12] ) + ( VCC ) + ( \GEN_10K|Add0~62  ))
+// \GEN_10K|Add0~30  = CARRY(( \GEN_10K|ctr [12] ) + ( VCC ) + ( \GEN_10K|Add0~62  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|ctr [12]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~62 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~29_sumout ),
+	.cout(\GEN_10K|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~29 .extended_lut = "off";
+defparam \GEN_10K|Add0~29 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N8
+dffeas \GEN_10K|ctr[12] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~29_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[12] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N9
+cyclonev_lcell_comb \GEN_10K|Add0~33 (
+// Equation(s):
+// \GEN_10K|Add0~33_sumout  = SUM(( \GEN_10K|ctr [13] ) + ( VCC ) + ( \GEN_10K|Add0~30  ))
+// \GEN_10K|Add0~34  = CARRY(( \GEN_10K|ctr [13] ) + ( VCC ) + ( \GEN_10K|Add0~30  ))
+
+	.dataa(!\GEN_10K|ctr [13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~33_sumout ),
+	.cout(\GEN_10K|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~33 .extended_lut = "off";
+defparam \GEN_10K|Add0~33 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N10
+dffeas \GEN_10K|ctr[13] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[13] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N12
+cyclonev_lcell_comb \GEN_10K|Add0~37 (
+// Equation(s):
+// \GEN_10K|Add0~37_sumout  = SUM(( \GEN_10K|ctr [14] ) + ( VCC ) + ( \GEN_10K|Add0~34  ))
+// \GEN_10K|Add0~38  = CARRY(( \GEN_10K|ctr [14] ) + ( VCC ) + ( \GEN_10K|Add0~34  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|ctr [14]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~37_sumout ),
+	.cout(\GEN_10K|Add0~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~37 .extended_lut = "off";
+defparam \GEN_10K|Add0~37 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N14
+dffeas \GEN_10K|ctr[14] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~37_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[14] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N15
+cyclonev_lcell_comb \GEN_10K|Add0~5 (
+// Equation(s):
+// \GEN_10K|Add0~5_sumout  = SUM(( \GEN_10K|ctr [15] ) + ( VCC ) + ( \GEN_10K|Add0~38  ))
+// \GEN_10K|Add0~6  = CARRY(( \GEN_10K|ctr [15] ) + ( VCC ) + ( \GEN_10K|Add0~38  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|ctr [15]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~5_sumout ),
+	.cout(\GEN_10K|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~5 .extended_lut = "off";
+defparam \GEN_10K|Add0~5 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N17
+dffeas \GEN_10K|ctr[15] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[15] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N18
+cyclonev_lcell_comb \GEN_10K|Add0~9 (
+// Equation(s):
+// \GEN_10K|Add0~9_sumout  = SUM(( \GEN_10K|ctr [16] ) + ( VCC ) + ( \GEN_10K|Add0~6  ))
+// \GEN_10K|Add0~10  = CARRY(( \GEN_10K|ctr [16] ) + ( VCC ) + ( \GEN_10K|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|ctr [16]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~9_sumout ),
+	.cout(\GEN_10K|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~9 .extended_lut = "off";
+defparam \GEN_10K|Add0~9 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N19
+dffeas \GEN_10K|ctr[16] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[16] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N21
+cyclonev_lcell_comb \GEN_10K|Add0~13 (
+// Equation(s):
+// \GEN_10K|Add0~13_sumout  = SUM(( \GEN_10K|ctr [17] ) + ( VCC ) + ( \GEN_10K|Add0~10  ))
+// \GEN_10K|Add0~14  = CARRY(( \GEN_10K|ctr [17] ) + ( VCC ) + ( \GEN_10K|Add0~10  ))
+
+	.dataa(!\GEN_10K|ctr [17]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~13_sumout ),
+	.cout(\GEN_10K|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~13 .extended_lut = "off";
+defparam \GEN_10K|Add0~13 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N23
+dffeas \GEN_10K|ctr[17] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[17] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N24
+cyclonev_lcell_comb \GEN_10K|Add0~65 (
+// Equation(s):
+// \GEN_10K|Add0~65_sumout  = SUM(( \GEN_10K|ctr [18] ) + ( VCC ) + ( \GEN_10K|Add0~14  ))
+// \GEN_10K|Add0~66  = CARRY(( \GEN_10K|ctr [18] ) + ( VCC ) + ( \GEN_10K|Add0~14  ))
+
+	.dataa(!\GEN_10K|ctr [18]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~65_sumout ),
+	.cout(\GEN_10K|Add0~66 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~65 .extended_lut = "off";
+defparam \GEN_10K|Add0~65 .lut_mask = 64'h0000000000005555;
+defparam \GEN_10K|Add0~65 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N26
+dffeas \GEN_10K|ctr[18] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~65_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[18] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N27
+cyclonev_lcell_comb \GEN_10K|Add0~69 (
+// Equation(s):
+// \GEN_10K|Add0~69_sumout  = SUM(( \GEN_10K|ctr [19] ) + ( VCC ) + ( \GEN_10K|Add0~66  ))
+// \GEN_10K|Add0~70  = CARRY(( \GEN_10K|ctr [19] ) + ( VCC ) + ( \GEN_10K|Add0~66  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|ctr [19]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~66 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~69_sumout ),
+	.cout(\GEN_10K|Add0~70 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~69 .extended_lut = "off";
+defparam \GEN_10K|Add0~69 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~69 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N28
+dffeas \GEN_10K|ctr[19] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~69_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[19] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N9
+cyclonev_lcell_comb \GEN_10K|Equal0~3 (
+// Equation(s):
+// \GEN_10K|Equal0~3_combout  = ( !\GEN_10K|ctr [2] & ( !\GEN_10K|ctr [4] & ( (!\GEN_10K|ctr [19] & (!\GEN_10K|ctr [3] & !\GEN_10K|ctr [18])) ) ) )
+
+	.dataa(!\GEN_10K|ctr [19]),
+	.datab(!\GEN_10K|ctr [3]),
+	.datac(!\GEN_10K|ctr [18]),
+	.datad(gnd),
+	.datae(!\GEN_10K|ctr [2]),
+	.dataf(!\GEN_10K|ctr [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~3 .extended_lut = "off";
+defparam \GEN_10K|Equal0~3 .lut_mask = 64'h8080000000000000;
+defparam \GEN_10K|Equal0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N30
+cyclonev_lcell_comb \GEN_10K|Add0~1 (
+// Equation(s):
+// \GEN_10K|Add0~1_sumout  = SUM(( \GEN_10K|ctr [20] ) + ( VCC ) + ( \GEN_10K|Add0~70  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|ctr [20]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~70 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~1 .extended_lut = "off";
+defparam \GEN_10K|Add0~1 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N32
+dffeas \GEN_10K|ctr[20] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~1_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[20] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N48
+cyclonev_lcell_comb \GEN_10K|Equal0~0 (
+// Equation(s):
+// \GEN_10K|Equal0~0_combout  = ( !\GEN_10K|ctr [16] & ( (!\GEN_10K|ctr [17] & !\GEN_10K|ctr [15]) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|ctr [17]),
+	.datad(!\GEN_10K|ctr [15]),
+	.datae(gnd),
+	.dataf(!\GEN_10K|ctr [16]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~0 .extended_lut = "off";
+defparam \GEN_10K|Equal0~0 .lut_mask = 64'hF000F00000000000;
+defparam \GEN_10K|Equal0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N54
+cyclonev_lcell_comb \GEN_10K|Equal0~1 (
+// Equation(s):
+// \GEN_10K|Equal0~1_combout  = ( !\GEN_10K|ctr [10] & ( !\GEN_10K|ctr [9] & ( (!\GEN_10K|ctr [5] & (!\GEN_10K|ctr [12] & (!\GEN_10K|ctr [13] & !\GEN_10K|ctr [14]))) ) ) )
+
+	.dataa(!\GEN_10K|ctr [5]),
+	.datab(!\GEN_10K|ctr [12]),
+	.datac(!\GEN_10K|ctr [13]),
+	.datad(!\GEN_10K|ctr [14]),
+	.datae(!\GEN_10K|ctr [10]),
+	.dataf(!\GEN_10K|ctr [9]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~1 .extended_lut = "off";
+defparam \GEN_10K|Equal0~1 .lut_mask = 64'h8000000000000000;
+defparam \GEN_10K|Equal0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N51
+cyclonev_lcell_comb \GEN_10K|Equal0~4 (
+// Equation(s):
+// \GEN_10K|Equal0~4_combout  = ( \GEN_10K|Equal0~1_combout  & ( (\GEN_10K|Equal0~3_combout  & (!\GEN_10K|ctr [20] & (\GEN_10K|Equal0~0_combout  & \GEN_10K|Equal0~2_combout ))) ) )
+
+	.dataa(!\GEN_10K|Equal0~3_combout ),
+	.datab(!\GEN_10K|ctr [20]),
+	.datac(!\GEN_10K|Equal0~0_combout ),
+	.datad(!\GEN_10K|Equal0~2_combout ),
+	.datae(gnd),
+	.dataf(!\GEN_10K|Equal0~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~4 .extended_lut = "off";
+defparam \GEN_10K|Equal0~4 .lut_mask = 64'h0000000000040004;
+defparam \GEN_10K|Equal0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N38
+dffeas \GEN_10K|ctr[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~77_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[2] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N39
+cyclonev_lcell_comb \GEN_10K|Add0~81 (
+// Equation(s):
+// \GEN_10K|Add0~81_sumout  = SUM(( \GEN_10K|ctr [3] ) + ( VCC ) + ( \GEN_10K|Add0~78  ))
+// \GEN_10K|Add0~82  = CARRY(( \GEN_10K|ctr [3] ) + ( VCC ) + ( \GEN_10K|Add0~78  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|ctr [3]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~78 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~81_sumout ),
+	.cout(\GEN_10K|Add0~82 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~81 .extended_lut = "off";
+defparam \GEN_10K|Add0~81 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~81 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N41
+dffeas \GEN_10K|ctr[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~81_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[3] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N42
+cyclonev_lcell_comb \GEN_10K|Add0~73 (
+// Equation(s):
+// \GEN_10K|Add0~73_sumout  = SUM(( \GEN_10K|ctr [4] ) + ( VCC ) + ( \GEN_10K|Add0~82  ))
+// \GEN_10K|Add0~74  = CARRY(( \GEN_10K|ctr [4] ) + ( VCC ) + ( \GEN_10K|Add0~82  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|ctr [4]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~82 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~73_sumout ),
+	.cout(\GEN_10K|Add0~74 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~73 .extended_lut = "off";
+defparam \GEN_10K|Add0~73 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~73 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N44
+dffeas \GEN_10K|ctr[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~73_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[4] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N45
+cyclonev_lcell_comb \GEN_10K|Add0~17 (
+// Equation(s):
+// \GEN_10K|Add0~17_sumout  = SUM(( \GEN_10K|ctr [5] ) + ( VCC ) + ( \GEN_10K|Add0~74  ))
+// \GEN_10K|Add0~18  = CARRY(( \GEN_10K|ctr [5] ) + ( VCC ) + ( \GEN_10K|Add0~74  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\GEN_10K|ctr [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~74 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~17_sumout ),
+	.cout(\GEN_10K|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~17 .extended_lut = "off";
+defparam \GEN_10K|Add0~17 .lut_mask = 64'h0000000000000F0F;
+defparam \GEN_10K|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N46
+dffeas \GEN_10K|ctr[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\GEN_10K|Equal0~4_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[5] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N48
+cyclonev_lcell_comb \GEN_10K|Add0~49 (
+// Equation(s):
+// \GEN_10K|Add0~49_sumout  = SUM(( \GEN_10K|ctr [6] ) + ( VCC ) + ( \GEN_10K|Add0~18  ))
+// \GEN_10K|Add0~50  = CARRY(( \GEN_10K|ctr [6] ) + ( VCC ) + ( \GEN_10K|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|ctr [6]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\GEN_10K|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\GEN_10K|Add0~49_sumout ),
+	.cout(\GEN_10K|Add0~50 ),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~49 .extended_lut = "off";
+defparam \GEN_10K|Add0~49 .lut_mask = 64'h0000000000003333;
+defparam \GEN_10K|Add0~49 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N49
+dffeas \GEN_10K|ctr[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~49_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[6] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X61_Y5_N53
+dffeas \GEN_10K|ctr[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|Add0~53_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[7] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y5_N0
+cyclonev_lcell_comb \GEN_10K|Equal0~2 (
+// Equation(s):
+// \GEN_10K|Equal0~2_combout  = ( !\GEN_10K|ctr [6] & ( !\GEN_10K|ctr [1] & ( (!\GEN_10K|ctr [7] & (!\GEN_10K|ctr [11] & (!\GEN_10K|ctr [8] & !\GEN_10K|ctr [0]))) ) ) )
+
+	.dataa(!\GEN_10K|ctr [7]),
+	.datab(!\GEN_10K|ctr [11]),
+	.datac(!\GEN_10K|ctr [8]),
+	.datad(!\GEN_10K|ctr [0]),
+	.datae(!\GEN_10K|ctr [6]),
+	.dataf(!\GEN_10K|ctr [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|Equal0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~2 .extended_lut = "off";
+defparam \GEN_10K|Equal0~2 .lut_mask = 64'h8000000000000000;
+defparam \GEN_10K|Equal0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N43
+dffeas \GEN_10K|clkout (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|clkout~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|clkout~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|clkout .is_wysiwyg = "true";
+defparam \GEN_10K|clkout .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N42
+cyclonev_lcell_comb \GEN_10K|clkout~0 (
+// Equation(s):
+// \GEN_10K|clkout~0_combout  = ( \GEN_10K|clkout~q  & ( \GEN_10K|Equal0~1_combout  & ( (!\GEN_10K|Equal0~2_combout ) # (((!\GEN_10K|Equal0~3_combout ) # (!\GEN_10K|Equal0~0_combout )) # (\GEN_10K|ctr [20])) ) ) ) # ( !\GEN_10K|clkout~q  & ( 
+// \GEN_10K|Equal0~1_combout  & ( (\GEN_10K|Equal0~2_combout  & (!\GEN_10K|ctr [20] & (\GEN_10K|Equal0~3_combout  & \GEN_10K|Equal0~0_combout ))) ) ) ) # ( \GEN_10K|clkout~q  & ( !\GEN_10K|Equal0~1_combout  ) )
+
+	.dataa(!\GEN_10K|Equal0~2_combout ),
+	.datab(!\GEN_10K|ctr [20]),
+	.datac(!\GEN_10K|Equal0~3_combout ),
+	.datad(!\GEN_10K|Equal0~0_combout ),
+	.datae(!\GEN_10K|clkout~q ),
+	.dataf(!\GEN_10K|Equal0~1_combout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\GEN_10K|clkout~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \GEN_10K|clkout~0 .extended_lut = "off";
+defparam \GEN_10K|clkout~0 .lut_mask = 64'h0000FFFF0004FFFB;
+defparam \GEN_10K|clkout~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N44
+dffeas \GEN_10K|clkout~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\GEN_10K|clkout~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|clkout~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|clkout~DUPLICATE .is_wysiwyg = "true";
+defparam \GEN_10K|clkout~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N38
+dffeas \PULSE|state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\GEN_10K|clkout~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PULSE|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PULSE|state.IDLE .is_wysiwyg = "true";
+defparam \PULSE|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y4_N39
+cyclonev_lcell_comb \PULSE|pulse~1 (
+// Equation(s):
+// \PULSE|pulse~1_combout  = ( !\PULSE|state.IDLE~q  & ( \GEN_10K|clkout~DUPLICATE_q  ) )
+
+	.dataa(gnd),
+	.datab(!\GEN_10K|clkout~DUPLICATE_q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\PULSE|state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PULSE|pulse~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PULSE|pulse~1 .extended_lut = "off";
+defparam \PULSE|pulse~1 .lut_mask = 64'h3333333300000000;
+defparam \PULSE|pulse~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y4_N41
+dffeas \PULSE|pulse (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PULSE|pulse~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PULSE|pulse~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PULSE|pulse .is_wysiwyg = "true";
+defparam \PULSE|pulse .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N15
+cyclonev_lcell_comb \SPI_DAC|Selector2~0 (
+// Equation(s):
+// \SPI_DAC|Selector2~0_combout  = ( \SPI_DAC|sr_state.IDLE~q  & ( \SPI_DAC|dac_cs~q  ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector2~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector2~0 .lut_mask = 64'h0000000055555555;
+defparam \SPI_DAC|Selector2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N16
+dffeas \SPI_DAC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N12
+cyclonev_lcell_comb \SPI_DAC|Selector0~0 (
+// Equation(s):
+// \SPI_DAC|Selector0~0_combout  = ( \SPI_DAC|sr_state.WAIT_CSB_HIGH~q  & ( (\SPI_DAC|dac_cs~q  & ((\SPI_DAC|sr_state.IDLE~q ) # (\PULSE|pulse~q ))) ) ) # ( !\SPI_DAC|sr_state.WAIT_CSB_HIGH~q  & ( (\SPI_DAC|sr_state.IDLE~q ) # (\PULSE|pulse~q ) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\PULSE|pulse~q ),
+	.datac(gnd),
+	.datad(!\SPI_DAC|sr_state.IDLE~q ),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector0~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector0~0 .lut_mask = 64'h33FF33FF11551155;
+defparam \SPI_DAC|Selector0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N13
+dffeas \SPI_DAC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N3
+cyclonev_lcell_comb \SPI_DAC|Selector1~0 (
+// Equation(s):
+// \SPI_DAC|Selector1~0_combout  = ( \SPI_DAC|sr_state.IDLE~q  & ( (!\SPI_DAC|dac_cs~q  & \SPI_DAC|sr_state.WAIT_CSB_FALL~q ) ) ) # ( !\SPI_DAC|sr_state.IDLE~q  & ( ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|sr_state.WAIT_CSB_FALL~q )) # (\PULSE|pulse~q ) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\PULSE|pulse~q ),
+	.datac(gnd),
+	.datad(!\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Selector1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector1~0 .extended_lut = "off";
+defparam \SPI_DAC|Selector1~0 .lut_mask = 64'h33BB33BB00AA00AA;
+defparam \SPI_DAC|Selector1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N5
+dffeas \SPI_DAC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N0
+cyclonev_lcell_comb \SPI_DAC|dac_start~0 (
+// Equation(s):
+// \SPI_DAC|dac_start~0_combout  = ( \SPI_DAC|sr_state.IDLE~q  & ( (\SPI_DAC|dac_start~q  & ((\SPI_DAC|sr_state.WAIT_CSB_FALL~q ) # (\SPI_DAC|dac_cs~q ))) ) ) # ( !\SPI_DAC|sr_state.IDLE~q  & ( (\SPI_DAC|dac_start~q ) # (\PULSE|pulse~q ) ) )
+
+	.dataa(!\SPI_DAC|dac_cs~q ),
+	.datab(!\PULSE|pulse~q ),
+	.datac(!\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(!\SPI_DAC|dac_start~q ),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|dac_start~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_start~0 .extended_lut = "off";
+defparam \SPI_DAC|dac_start~0 .lut_mask = 64'h33FF33FF005F005F;
+defparam \SPI_DAC|dac_start~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X64_Y1_N1
+dffeas \SPI_DAC|dac_start (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_DAC|dac_start~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_start .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N33
+cyclonev_lcell_comb \SPI_ADC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_ADC|clk_1MHz~0_combout  = ( !\SPI_ADC|clk_1MHz~q  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|clk_1MHz~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|clk_1MHz~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~0 .extended_lut = "off";
+defparam \SPI_ADC|clk_1MHz~0 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \SPI_ADC|clk_1MHz~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N44
+dffeas \SPI_ADC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(gnd),
+	.asdata(\SPI_ADC|clk_1MHz~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_DAC|Equal0~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_ADC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N6
+cyclonev_lcell_comb \SPI_ADC|state[1]~0 (
+// Equation(s):
+// \SPI_ADC|state[1]~0_combout  = ( !\SPI_ADC|state [1] & ( \SPI_ADC|state [0] ) ) # ( \SPI_ADC|state [1] & ( !\SPI_ADC|state [0] ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SPI_ADC|state [1]),
+	.dataf(!\SPI_ADC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[1]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[1]~0 .extended_lut = "off";
+defparam \SPI_ADC|state[1]~0 .lut_mask = 64'h0000FFFFFFFF0000;
+defparam \SPI_ADC|state[1]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N43
+dffeas \SPI_ADC|state[1] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[1]~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N12
+cyclonev_lcell_comb \SPI_ADC|state[2]~2 (
+// Equation(s):
+// \SPI_ADC|state[2]~2_combout  = !\SPI_ADC|state [2] $ (((!\SPI_ADC|state [1]) # (!\SPI_ADC|state [0])))
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|state [1]),
+	.datac(!\SPI_ADC|state [2]),
+	.datad(!\SPI_ADC|state [0]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[2]~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[2]~2 .extended_lut = "off";
+defparam \SPI_ADC|state[2]~2 .lut_mask = 64'h0F3C0F3C0F3C0F3C;
+defparam \SPI_ADC|state[2]~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N5
+dffeas \SPI_ADC|state[2] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[2]~2_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N39
+cyclonev_lcell_comb \SPI_ADC|Selector2~0 (
+// Equation(s):
+// \SPI_ADC|Selector2~0_combout  = ( \SPI_ADC|sr_state.IDLE~q  & ( \SPI_ADC|adc_cs~q  ) )
+
+	.dataa(!\SPI_ADC|adc_cs~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector2~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector2~0 .lut_mask = 64'h0000000055555555;
+defparam \SPI_ADC|Selector2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N40
+dffeas \SPI_ADC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N36
+cyclonev_lcell_comb \SPI_ADC|Selector0~0 (
+// Equation(s):
+// \SPI_ADC|Selector0~0_combout  = ( \SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & ( (\SPI_ADC|adc_cs~q  & ((\SPI_ADC|sr_state.IDLE~q ) # (\PULSE|pulse~q ))) ) ) # ( !\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & ( (\SPI_ADC|sr_state.IDLE~q ) # (\PULSE|pulse~q ) ) )
+
+	.dataa(!\SPI_ADC|adc_cs~q ),
+	.datab(gnd),
+	.datac(!\PULSE|pulse~q ),
+	.datad(!\SPI_ADC|sr_state.IDLE~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector0~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector0~0 .lut_mask = 64'h0FFF0FFF05550555;
+defparam \SPI_ADC|Selector0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N38
+dffeas \SPI_ADC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N21
+cyclonev_lcell_comb \SPI_ADC|Selector1~0 (
+// Equation(s):
+// \SPI_ADC|Selector1~0_combout  = ( \SPI_ADC|sr_state.IDLE~q  & ( (!\SPI_ADC|adc_cs~q  & \SPI_ADC|sr_state.WAIT_CSB_FALL~q ) ) ) # ( !\SPI_ADC|sr_state.IDLE~q  & ( ((!\SPI_ADC|adc_cs~q  & \SPI_ADC|sr_state.WAIT_CSB_FALL~q )) # (\PULSE|pulse~q ) ) )
+
+	.dataa(!\SPI_ADC|adc_cs~q ),
+	.datab(!\PULSE|pulse~q ),
+	.datac(gnd),
+	.datad(!\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector1~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector1~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector1~0 .lut_mask = 64'h33BB33BB00AA00AA;
+defparam \SPI_ADC|Selector1~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N23
+dffeas \SPI_ADC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N18
+cyclonev_lcell_comb \SPI_ADC|adc_start~0 (
+// Equation(s):
+// \SPI_ADC|adc_start~0_combout  = ( \SPI_ADC|sr_state.IDLE~q  & ( (\SPI_ADC|adc_start~q  & ((\SPI_ADC|sr_state.WAIT_CSB_FALL~q ) # (\SPI_ADC|adc_cs~q ))) ) ) # ( !\SPI_ADC|sr_state.IDLE~q  & ( (\SPI_ADC|adc_start~q ) # (\PULSE|pulse~q ) ) )
+
+	.dataa(!\SPI_ADC|adc_cs~q ),
+	.datab(!\PULSE|pulse~q ),
+	.datac(!\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(!\SPI_ADC|adc_start~q ),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|sr_state.IDLE~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|adc_start~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~0 .extended_lut = "off";
+defparam \SPI_ADC|adc_start~0 .lut_mask = 64'h33FF33FF005F005F;
+defparam \SPI_ADC|adc_start~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N20
+dffeas \SPI_ADC|adc_start (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|adc_start~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_start .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N27
+cyclonev_lcell_comb \SPI_ADC|Selector5~0 (
+// Equation(s):
+// \SPI_ADC|Selector5~0_combout  = ( \SPI_ADC|adc_start~q  & ( !\SPI_ADC|state [0] & ( ((!\SPI_ADC|state [4]) # ((\SPI_ADC|state [2]) # (\SPI_ADC|state [1]))) # (\SPI_ADC|state [3]) ) ) ) # ( !\SPI_ADC|adc_start~q  & ( !\SPI_ADC|state [0] & ( 
+// ((\SPI_ADC|state [2]) # (\SPI_ADC|state [1])) # (\SPI_ADC|state [3]) ) ) )
+
+	.dataa(!\SPI_ADC|state [3]),
+	.datab(!\SPI_ADC|state [4]),
+	.datac(!\SPI_ADC|state [1]),
+	.datad(!\SPI_ADC|state [2]),
+	.datae(!\SPI_ADC|adc_start~q ),
+	.dataf(!\SPI_ADC|state [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector5~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector5~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector5~0 .lut_mask = 64'h5FFFDFFF00000000;
+defparam \SPI_ADC|Selector5~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N11
+dffeas \SPI_ADC|state[0] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|Selector5~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N3
+cyclonev_lcell_comb \SPI_ADC|state[3]~3 (
+// Equation(s):
+// \SPI_ADC|state[3]~3_combout  = ( \SPI_ADC|state [2] & ( !\SPI_ADC|state [3] $ (((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [1]))) ) ) # ( !\SPI_ADC|state [2] & ( \SPI_ADC|state [3] ) )
+
+	.dataa(!\SPI_ADC|state [3]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(!\SPI_ADC|state [1]),
+	.datad(gnd),
+	.datae(!\SPI_ADC|state [2]),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state[3]~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state[3]~3 .extended_lut = "off";
+defparam \SPI_ADC|state[3]~3 .lut_mask = 64'h5555565655555656;
+defparam \SPI_ADC|state[3]~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N1
+dffeas \SPI_ADC|state[3] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state[3]~3_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N45
+cyclonev_lcell_comb \SPI_ADC|state~1 (
+// Equation(s):
+// \SPI_ADC|state~1_combout  = ( \SPI_ADC|state [1] & ( !\SPI_ADC|state [4] $ (((!\SPI_ADC|state [3]) # ((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [2])))) ) ) # ( !\SPI_ADC|state [1] & ( (\SPI_ADC|state [4] & (((\SPI_ADC|state [2]) # (\SPI_ADC|state [0])) # 
+// (\SPI_ADC|state [3]))) ) )
+
+	.dataa(!\SPI_ADC|state [3]),
+	.datab(!\SPI_ADC|state [4]),
+	.datac(!\SPI_ADC|state [0]),
+	.datad(!\SPI_ADC|state [2]),
+	.datae(!\SPI_ADC|state [1]),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|state~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|state~1 .extended_lut = "off";
+defparam \SPI_ADC|state~1 .lut_mask = 64'h1333333613333336;
+defparam \SPI_ADC|state~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N25
+dffeas \SPI_ADC|state[4] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|state~1_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N19
+dffeas \SPI_ADC|adc_start~DUPLICATE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\SPI_ADC|adc_start~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_start~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_start~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N42
+cyclonev_lcell_comb \SPI_ADC|Selector4~0 (
+// Equation(s):
+// \SPI_ADC|Selector4~0_combout  = ( \SPI_ADC|state [3] & ( \SPI_ADC|adc_start~DUPLICATE_q  ) ) # ( !\SPI_ADC|state [3] & ( \SPI_ADC|adc_start~DUPLICATE_q  & ( (!\SPI_ADC|state [4]) # (((\SPI_ADC|state [2]) # (\SPI_ADC|state [1])) # (\SPI_ADC|state [0])) ) ) 
+// ) # ( \SPI_ADC|state [3] & ( !\SPI_ADC|adc_start~DUPLICATE_q  ) ) # ( !\SPI_ADC|state [3] & ( !\SPI_ADC|adc_start~DUPLICATE_q  & ( ((\SPI_ADC|state [2]) # (\SPI_ADC|state [1])) # (\SPI_ADC|state [0]) ) ) )
+
+	.dataa(!\SPI_ADC|state [4]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(!\SPI_ADC|state [1]),
+	.datad(!\SPI_ADC|state [2]),
+	.datae(!\SPI_ADC|state [3]),
+	.dataf(!\SPI_ADC|adc_start~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector4~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~0 .extended_lut = "off";
+defparam \SPI_ADC|Selector4~0 .lut_mask = 64'h3FFFFFFFBFFFFFFF;
+defparam \SPI_ADC|Selector4~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N44
+dffeas \SPI_ADC|adc_cs (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Selector4~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N51
+cyclonev_lcell_comb \ECHO|PULSE2|state.IDLE~0 (
+// Equation(s):
+// \ECHO|PULSE2|state.IDLE~0_combout  = ( !\SPI_ADC|adc_cs~q  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ECHO|PULSE2|state.IDLE~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|PULSE2|state.IDLE~0 .extended_lut = "off";
+defparam \ECHO|PULSE2|state.IDLE~0 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \ECHO|PULSE2|state.IDLE~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N53
+dffeas \ECHO|PULSE2|state.IDLE (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|PULSE2|state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|PULSE2|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|PULSE2|state.IDLE .is_wysiwyg = "true";
+defparam \ECHO|PULSE2|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N48
+cyclonev_lcell_comb \ECHO|PULSE2|pulse~1 (
+// Equation(s):
+// \ECHO|PULSE2|pulse~1_combout  = ( !\SPI_ADC|adc_cs~q  & ( !\ECHO|PULSE2|state.IDLE~q  ) )
+
+	.dataa(!\ECHO|PULSE2|state.IDLE~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|adc_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ECHO|PULSE2|pulse~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|PULSE2|pulse~1 .extended_lut = "off";
+defparam \ECHO|PULSE2|pulse~1 .lut_mask = 64'hAAAAAAAA00000000;
+defparam \ECHO|PULSE2|pulse~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N50
+dffeas \ECHO|PULSE2|pulse (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|PULSE2|pulse~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|PULSE2|pulse~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|PULSE2|pulse .is_wysiwyg = "true";
+defparam \ECHO|PULSE2|pulse .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N57
+cyclonev_lcell_comb \ECHO|ctr[0]~0 (
+// Equation(s):
+// \ECHO|ctr[0]~0_combout  = ( !\ECHO|ctr [0] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ECHO|ctr [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ECHO|ctr[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|ctr[0]~0 .extended_lut = "off";
+defparam \ECHO|ctr[0]~0 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \ECHO|ctr[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y2_N31
+dffeas \ECHO|ctr[0] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(gnd),
+	.asdata(\ECHO|ctr[0]~0_combout ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[0] .is_wysiwyg = "true";
+defparam \ECHO|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N0
+cyclonev_lcell_comb \ECHO|Add1~1 (
+// Equation(s):
+// \ECHO|Add1~1_sumout  = SUM(( \ECHO|ctr [1] ) + ( \ECHO|ctr [0] ) + ( !VCC ))
+// \ECHO|Add1~2  = CARRY(( \ECHO|ctr [1] ) + ( \ECHO|ctr [0] ) + ( !VCC ))
+
+	.dataa(!\ECHO|ctr [1]),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [0]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~1_sumout ),
+	.cout(\ECHO|Add1~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~1 .extended_lut = "off";
+defparam \ECHO|Add1~1 .lut_mask = 64'h0000F0F000005555;
+defparam \ECHO|Add1~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N1
+dffeas \ECHO|ctr[1] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~1_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[1] .is_wysiwyg = "true";
+defparam \ECHO|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N5
+dffeas \ECHO|ctr[2] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[2] .is_wysiwyg = "true";
+defparam \ECHO|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N3
+cyclonev_lcell_comb \ECHO|Add1~5 (
+// Equation(s):
+// \ECHO|Add1~5_sumout  = SUM(( \ECHO|ctr [2] ) + ( GND ) + ( \ECHO|Add1~2  ))
+// \ECHO|Add1~6  = CARRY(( \ECHO|ctr [2] ) + ( GND ) + ( \ECHO|Add1~2  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\ECHO|ctr [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~5_sumout ),
+	.cout(\ECHO|Add1~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~5 .extended_lut = "off";
+defparam \ECHO|Add1~5 .lut_mask = 64'h0000FFFF000000FF;
+defparam \ECHO|Add1~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N4
+dffeas \ECHO|ctr[2]~DUPLICATE (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr[2]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[2]~DUPLICATE .is_wysiwyg = "true";
+defparam \ECHO|ctr[2]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N6
+cyclonev_lcell_comb \ECHO|Add1~9 (
+// Equation(s):
+// \ECHO|Add1~9_sumout  = SUM(( \ECHO|ctr [3] ) + ( GND ) + ( \ECHO|Add1~6  ))
+// \ECHO|Add1~10  = CARRY(( \ECHO|ctr [3] ) + ( GND ) + ( \ECHO|Add1~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [3]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~9_sumout ),
+	.cout(\ECHO|Add1~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~9 .extended_lut = "off";
+defparam \ECHO|Add1~9 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \ECHO|Add1~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N7
+dffeas \ECHO|ctr[3] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[3] .is_wysiwyg = "true";
+defparam \ECHO|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N11
+dffeas \ECHO|ctr[4] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[4] .is_wysiwyg = "true";
+defparam \ECHO|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N9
+cyclonev_lcell_comb \ECHO|Add1~13 (
+// Equation(s):
+// \ECHO|Add1~13_sumout  = SUM(( \ECHO|ctr [4] ) + ( GND ) + ( \ECHO|Add1~10  ))
+// \ECHO|Add1~14  = CARRY(( \ECHO|ctr [4] ) + ( GND ) + ( \ECHO|Add1~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [4]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~13_sumout ),
+	.cout(\ECHO|Add1~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~13 .extended_lut = "off";
+defparam \ECHO|Add1~13 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \ECHO|Add1~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N10
+dffeas \ECHO|ctr[4]~DUPLICATE (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr[4]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[4]~DUPLICATE .is_wysiwyg = "true";
+defparam \ECHO|ctr[4]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N0
+cyclonev_lcell_comb \ECHO|Add2~1 (
+// Equation(s):
+// \ECHO|Add2~1_sumout  = SUM(( \SW[0]~input_o  ) + ( \ECHO|ctr[4]~DUPLICATE_q  ) + ( !VCC ))
+// \ECHO|Add2~2  = CARRY(( \SW[0]~input_o  ) + ( \ECHO|ctr[4]~DUPLICATE_q  ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\SW[0]~input_o ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ECHO|ctr[4]~DUPLICATE_q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~1_sumout ),
+	.cout(\ECHO|Add2~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~1 .extended_lut = "off";
+defparam \ECHO|Add2~1 .lut_mask = 64'h0000FF0000003333;
+defparam \ECHO|Add2~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N12
+cyclonev_lcell_comb \ECHO|Add1~17 (
+// Equation(s):
+// \ECHO|Add1~17_sumout  = SUM(( \ECHO|ctr [5] ) + ( GND ) + ( \ECHO|Add1~14  ))
+// \ECHO|Add1~18  = CARRY(( \ECHO|ctr [5] ) + ( GND ) + ( \ECHO|Add1~14  ))
+
+	.dataa(gnd),
+	.datab(!\ECHO|ctr [5]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~17_sumout ),
+	.cout(\ECHO|Add1~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~17 .extended_lut = "off";
+defparam \ECHO|Add1~17 .lut_mask = 64'h0000FFFF00003333;
+defparam \ECHO|Add1~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N13
+dffeas \ECHO|ctr[5] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[5] .is_wysiwyg = "true";
+defparam \ECHO|ctr[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N3
+cyclonev_lcell_comb \ECHO|Add2~5 (
+// Equation(s):
+// \ECHO|Add2~5_sumout  = SUM(( \ECHO|ctr [5] ) + ( \SW[1]~input_o  ) + ( \ECHO|Add2~2  ))
+// \ECHO|Add2~6  = CARRY(( \ECHO|ctr [5] ) + ( \SW[1]~input_o  ) + ( \ECHO|Add2~2  ))
+
+	.dataa(!\SW[1]~input_o ),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add2~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~5_sumout ),
+	.cout(\ECHO|Add2~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~5 .extended_lut = "off";
+defparam \ECHO|Add2~5 .lut_mask = 64'h0000AAAA00000F0F;
+defparam \ECHO|Add2~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N15
+cyclonev_lcell_comb \ECHO|Add1~21 (
+// Equation(s):
+// \ECHO|Add1~21_sumout  = SUM(( \ECHO|ctr [6] ) + ( GND ) + ( \ECHO|Add1~18  ))
+// \ECHO|Add1~22  = CARRY(( \ECHO|ctr [6] ) + ( GND ) + ( \ECHO|Add1~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [6]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~21_sumout ),
+	.cout(\ECHO|Add1~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~21 .extended_lut = "off";
+defparam \ECHO|Add1~21 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \ECHO|Add1~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N17
+dffeas \ECHO|ctr[6] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[6] .is_wysiwyg = "true";
+defparam \ECHO|ctr[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N6
+cyclonev_lcell_comb \ECHO|Add2~9 (
+// Equation(s):
+// \ECHO|Add2~9_sumout  = SUM(( \ECHO|ctr [6] ) + ( \SW[2]~input_o  ) + ( \ECHO|Add2~6  ))
+// \ECHO|Add2~10  = CARRY(( \ECHO|ctr [6] ) + ( \SW[2]~input_o  ) + ( \ECHO|Add2~6  ))
+
+	.dataa(!\ECHO|ctr [6]),
+	.datab(gnd),
+	.datac(!\SW[2]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add2~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~9_sumout ),
+	.cout(\ECHO|Add2~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~9 .extended_lut = "off";
+defparam \ECHO|Add2~9 .lut_mask = 64'h0000F0F000005555;
+defparam \ECHO|Add2~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N18
+cyclonev_lcell_comb \ECHO|Add1~25 (
+// Equation(s):
+// \ECHO|Add1~25_sumout  = SUM(( \ECHO|ctr [7] ) + ( GND ) + ( \ECHO|Add1~22  ))
+// \ECHO|Add1~26  = CARRY(( \ECHO|ctr [7] ) + ( GND ) + ( \ECHO|Add1~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [7]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~25_sumout ),
+	.cout(\ECHO|Add1~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~25 .extended_lut = "off";
+defparam \ECHO|Add1~25 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \ECHO|Add1~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N19
+dffeas \ECHO|ctr[7] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[7] .is_wysiwyg = "true";
+defparam \ECHO|ctr[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N9
+cyclonev_lcell_comb \ECHO|Add2~13 (
+// Equation(s):
+// \ECHO|Add2~13_sumout  = SUM(( \ECHO|ctr [7] ) + ( \SW[3]~input_o  ) + ( \ECHO|Add2~10  ))
+// \ECHO|Add2~14  = CARRY(( \ECHO|ctr [7] ) + ( \SW[3]~input_o  ) + ( \ECHO|Add2~10  ))
+
+	.dataa(gnd),
+	.datab(!\ECHO|ctr [7]),
+	.datac(!\SW[3]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add2~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~13_sumout ),
+	.cout(\ECHO|Add2~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~13 .extended_lut = "off";
+defparam \ECHO|Add2~13 .lut_mask = 64'h0000F0F000003333;
+defparam \ECHO|Add2~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N21
+cyclonev_lcell_comb \ECHO|Add1~29 (
+// Equation(s):
+// \ECHO|Add1~29_sumout  = SUM(( \ECHO|ctr [8] ) + ( GND ) + ( \ECHO|Add1~26  ))
+// \ECHO|Add1~30  = CARRY(( \ECHO|ctr [8] ) + ( GND ) + ( \ECHO|Add1~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [8]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~29_sumout ),
+	.cout(\ECHO|Add1~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~29 .extended_lut = "off";
+defparam \ECHO|Add1~29 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \ECHO|Add1~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N22
+dffeas \ECHO|ctr[8] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~29_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[8] .is_wysiwyg = "true";
+defparam \ECHO|ctr[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N12
+cyclonev_lcell_comb \ECHO|Add2~17 (
+// Equation(s):
+// \ECHO|Add2~17_sumout  = SUM(( \ECHO|ctr [8] ) + ( \SW[4]~input_o  ) + ( \ECHO|Add2~14  ))
+// \ECHO|Add2~18  = CARRY(( \ECHO|ctr [8] ) + ( \SW[4]~input_o  ) + ( \ECHO|Add2~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [8]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SW[4]~input_o ),
+	.datag(gnd),
+	.cin(\ECHO|Add2~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~17_sumout ),
+	.cout(\ECHO|Add2~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~17 .extended_lut = "off";
+defparam \ECHO|Add2~17 .lut_mask = 64'h0000FF0000000F0F;
+defparam \ECHO|Add2~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N24
+cyclonev_lcell_comb \ECHO|Add1~33 (
+// Equation(s):
+// \ECHO|Add1~33_sumout  = SUM(( \ECHO|ctr [9] ) + ( GND ) + ( \ECHO|Add1~30  ))
+// \ECHO|Add1~34  = CARRY(( \ECHO|ctr [9] ) + ( GND ) + ( \ECHO|Add1~30  ))
+
+	.dataa(gnd),
+	.datab(!\ECHO|ctr [9]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~33_sumout ),
+	.cout(\ECHO|Add1~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~33 .extended_lut = "off";
+defparam \ECHO|Add1~33 .lut_mask = 64'h0000FFFF00003333;
+defparam \ECHO|Add1~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N25
+dffeas \ECHO|ctr[9] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[9] .is_wysiwyg = "true";
+defparam \ECHO|ctr[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N15
+cyclonev_lcell_comb \ECHO|Add2~21 (
+// Equation(s):
+// \ECHO|Add2~21_sumout  = SUM(( \ECHO|ctr [9] ) + ( \SW[5]~input_o  ) + ( \ECHO|Add2~18  ))
+// \ECHO|Add2~22  = CARRY(( \ECHO|ctr [9] ) + ( \SW[5]~input_o  ) + ( \ECHO|Add2~18  ))
+
+	.dataa(!\SW[5]~input_o ),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add2~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~21_sumout ),
+	.cout(\ECHO|Add2~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~21 .extended_lut = "off";
+defparam \ECHO|Add2~21 .lut_mask = 64'h0000AAAA00000F0F;
+defparam \ECHO|Add2~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N27
+cyclonev_lcell_comb \ECHO|Add1~37 (
+// Equation(s):
+// \ECHO|Add1~37_sumout  = SUM(( \ECHO|ctr [10] ) + ( GND ) + ( \ECHO|Add1~34  ))
+// \ECHO|Add1~38  = CARRY(( \ECHO|ctr [10] ) + ( GND ) + ( \ECHO|Add1~34  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [10]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~37_sumout ),
+	.cout(\ECHO|Add1~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~37 .extended_lut = "off";
+defparam \ECHO|Add1~37 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \ECHO|Add1~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N28
+dffeas \ECHO|ctr[10] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~37_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[10] .is_wysiwyg = "true";
+defparam \ECHO|ctr[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N18
+cyclonev_lcell_comb \ECHO|Add2~25 (
+// Equation(s):
+// \ECHO|Add2~25_sumout  = SUM(( \ECHO|ctr [10] ) + ( \SW[6]~input_o  ) + ( \ECHO|Add2~22  ))
+// \ECHO|Add2~26  = CARRY(( \ECHO|ctr [10] ) + ( \SW[6]~input_o  ) + ( \ECHO|Add2~22  ))
+
+	.dataa(gnd),
+	.datab(!\SW[6]~input_o ),
+	.datac(!\ECHO|ctr [10]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add2~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~25_sumout ),
+	.cout(\ECHO|Add2~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~25 .extended_lut = "off";
+defparam \ECHO|Add2~25 .lut_mask = 64'h0000CCCC00000F0F;
+defparam \ECHO|Add2~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N32
+dffeas \ECHO|ctr[11] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~41_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[11] .is_wysiwyg = "true";
+defparam \ECHO|ctr[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N30
+cyclonev_lcell_comb \ECHO|Add1~41 (
+// Equation(s):
+// \ECHO|Add1~41_sumout  = SUM(( \ECHO|ctr [11] ) + ( GND ) + ( \ECHO|Add1~38  ))
+// \ECHO|Add1~42  = CARRY(( \ECHO|ctr [11] ) + ( GND ) + ( \ECHO|Add1~38  ))
+
+	.dataa(gnd),
+	.datab(!\ECHO|ctr [11]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~41_sumout ),
+	.cout(\ECHO|Add1~42 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~41 .extended_lut = "off";
+defparam \ECHO|Add1~41 .lut_mask = 64'h0000FFFF00003333;
+defparam \ECHO|Add1~41 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N31
+dffeas \ECHO|ctr[11]~DUPLICATE (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~41_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr[11]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[11]~DUPLICATE .is_wysiwyg = "true";
+defparam \ECHO|ctr[11]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N21
+cyclonev_lcell_comb \ECHO|Add2~29 (
+// Equation(s):
+// \ECHO|Add2~29_sumout  = SUM(( \ECHO|ctr[11]~DUPLICATE_q  ) + ( \SW[7]~input_o  ) + ( \ECHO|Add2~26  ))
+// \ECHO|Add2~30  = CARRY(( \ECHO|ctr[11]~DUPLICATE_q  ) + ( \SW[7]~input_o  ) + ( \ECHO|Add2~26  ))
+
+	.dataa(!\ECHO|ctr[11]~DUPLICATE_q ),
+	.datab(gnd),
+	.datac(!\SW[7]~input_o ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add2~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~29_sumout ),
+	.cout(\ECHO|Add2~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~29 .extended_lut = "off";
+defparam \ECHO|Add2~29 .lut_mask = 64'h0000F0F000005555;
+defparam \ECHO|Add2~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N33
+cyclonev_lcell_comb \ECHO|Add1~45 (
+// Equation(s):
+// \ECHO|Add1~45_sumout  = SUM(( \ECHO|ctr [12] ) + ( GND ) + ( \ECHO|Add1~42  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|ctr [12]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add1~42 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add1~45_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add1~45 .extended_lut = "off";
+defparam \ECHO|Add1~45 .lut_mask = 64'h0000FFFF00000F0F;
+defparam \ECHO|Add1~45 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N34
+dffeas \ECHO|ctr[12] (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~45_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[12] .is_wysiwyg = "true";
+defparam \ECHO|ctr[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N24
+cyclonev_lcell_comb \ECHO|Add2~33 (
+// Equation(s):
+// \ECHO|Add2~33_sumout  = SUM(( \ECHO|ctr [12] ) + ( \SW[8]~input_o  ) + ( \ECHO|Add2~30  ))
+
+	.dataa(!\SW[8]~input_o ),
+	.datab(!\ECHO|ctr [12]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add2~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add2~33_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add2~33 .extended_lut = "off";
+defparam \ECHO|Add2~33 .lut_mask = 64'h0000AAAA00003333;
+defparam \ECHO|Add2~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X61_Y2_N16
+dffeas \ECHO|ctr[6]~DUPLICATE (
+	.clk(\SPI_ADC|adc_cs~q ),
+	.d(\ECHO|Add1~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|ctr[6]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|ctr[6]~DUPLICATE .is_wysiwyg = "true";
+defparam \ECHO|ctr[6]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: M10K_X69_Y4_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add3~1_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr[6]~DUPLICATE_q ,\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 8;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 8;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: IOIBUF_X62_Y0_N52
+cyclonev_io_ibuf \ADC_SDO~input (
+	.i(ADC_SDO),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\ADC_SDO~input_o ));
+// synopsys translate_off
+defparam \ADC_SDO~input .bus_hold = "false";
+defparam \ADC_SDO~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N24
+cyclonev_lcell_comb \SPI_ADC|shift_reg[0]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[0]~feeder_combout  = ( \ADC_SDO~input_o  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ADC_SDO~input_o ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[0]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[0]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[0]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N57
+cyclonev_lcell_comb \SPI_ADC|WideOr0~0 (
+// Equation(s):
+// \SPI_ADC|WideOr0~0_combout  = ( \SPI_ADC|state [3] & ( (!\SPI_ADC|state [2]) # ((!\SPI_ADC|state [0]) # ((!\SPI_ADC|state [1]) # (\SPI_ADC|state [4]))) ) ) # ( !\SPI_ADC|state [3] & ( ((\SPI_ADC|state [4] & ((\SPI_ADC|state [1]) # (\SPI_ADC|state [0])))) 
+// # (\SPI_ADC|state [2]) ) )
+
+	.dataa(!\SPI_ADC|state [2]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(!\SPI_ADC|state [4]),
+	.datad(!\SPI_ADC|state [1]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|WideOr0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~0 .extended_lut = "off";
+defparam \SPI_ADC|WideOr0~0 .lut_mask = 64'h575F575FFFEFFFEF;
+defparam \SPI_ADC|WideOr0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N58
+dffeas \SPI_ADC|shift_ena (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|WideOr0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_ena~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_ena .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_ena .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N30
+cyclonev_lcell_comb \SPI_ADC|always3~0 (
+// Equation(s):
+// \SPI_ADC|always3~0_combout  = ( \SPI_ADC|shift_ena~q  & ( \SPI_ADC|adc_cs~q  ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|adc_cs~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SPI_ADC|shift_ena~q ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|always3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|always3~0 .extended_lut = "off";
+defparam \SPI_ADC|always3~0 .lut_mask = 64'h0000333300003333;
+defparam \SPI_ADC|always3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N26
+dffeas \SPI_ADC|shift_reg[0] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N18
+cyclonev_lcell_comb \SPI_ADC|shift_reg[1]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[1]~feeder_combout  = ( \SPI_ADC|shift_reg [0] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[1]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N20
+dffeas \SPI_ADC|shift_reg[1] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y1_N0
+cyclonev_lcell_comb \SPI_ADC|shift_reg[2]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[2]~feeder_combout  = ( \SPI_ADC|shift_reg [1] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[2]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[2]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y1_N1
+dffeas \SPI_ADC|shift_reg[2] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N42
+cyclonev_lcell_comb \SPI_ADC|shift_reg[3]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[3]~feeder_combout  = ( \SPI_ADC|shift_reg [2] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N44
+dffeas \SPI_ADC|shift_reg[3] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N39
+cyclonev_lcell_comb \SPI_ADC|shift_reg[4]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[4]~feeder_combout  = ( \SPI_ADC|shift_reg [3] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[4]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[4]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[4]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N40
+dffeas \SPI_ADC|shift_reg[4] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N38
+dffeas \SPI_ADC|shift_reg[5] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N5
+dffeas \SPI_ADC|shift_reg[6] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N2
+dffeas \SPI_ADC|shift_reg[7] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N22
+dffeas \SPI_ADC|shift_reg[8] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N27
+cyclonev_lcell_comb \SPI_ADC|shift_reg[9]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[9]~feeder_combout  = ( \SPI_ADC|shift_reg [8] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9]~feeder .extended_lut = "off";
+defparam \SPI_ADC|shift_reg[9]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|shift_reg[9]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N29
+dffeas \SPI_ADC|shift_reg[9] (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N54
+cyclonev_lcell_comb \SPI_ADC|Decoder0~0 (
+// Equation(s):
+// \SPI_ADC|Decoder0~0_combout  = ( !\SPI_ADC|state [4] & ( (\SPI_ADC|state [2] & (\SPI_ADC|state [0] & (\SPI_ADC|state [3] & \SPI_ADC|state [1]))) ) )
+
+	.dataa(!\SPI_ADC|state [2]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(!\SPI_ADC|state [3]),
+	.datad(!\SPI_ADC|state [1]),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|state [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Decoder0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~0 .extended_lut = "off";
+defparam \SPI_ADC|Decoder0~0 .lut_mask = 64'h0001000100000000;
+defparam \SPI_ADC|Decoder0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N56
+dffeas \SPI_ADC|adc_done (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Decoder0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_done~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_done .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_done .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N58
+dffeas \SPI_ADC|data_from_adc[9] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N54
+cyclonev_lcell_comb \SPI_ADC|data_from_adc[8]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[8]~feeder_combout  = ( \SPI_ADC|shift_reg [8] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [8]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|data_from_adc[8]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[8]~feeder .extended_lut = "off";
+defparam \SPI_ADC|data_from_adc[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|data_from_adc[8]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N56
+dffeas \SPI_ADC|data_from_adc[8] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|data_from_adc[8]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N54
+cyclonev_lcell_comb \ECHO|Add0~33 (
+// Equation(s):
+// \ECHO|Add0~33_sumout  = SUM(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [8] ) + ( \SPI_ADC|data_from_adc [8] ) + ( \ECHO|Add0~38  ))
+// \ECHO|Add0~34  = CARRY(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [8] ) + ( \SPI_ADC|data_from_adc [8] ) + ( \ECHO|Add0~38  ))
+
+	.dataa(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [8]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [8]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add0~38 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~33_sumout ),
+	.cout(\ECHO|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~33 .extended_lut = "off";
+defparam \ECHO|Add0~33 .lut_mask = 64'h0000F0F00000AAAA;
+defparam \ECHO|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N52
+dffeas \SPI_ADC|data_from_adc[7] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N0
+cyclonev_lcell_comb \ECHO|Add3~9 (
+// Equation(s):
+// \ECHO|Add3~9_sumout  = SUM(( \ECHO|Add0~37_sumout  ) + ( VCC ) + ( !VCC ))
+// \ECHO|Add3~10  = CARRY(( \ECHO|Add0~37_sumout  ) + ( VCC ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|Add0~37_sumout ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add3~9_sumout ),
+	.cout(\ECHO|Add3~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add3~9 .extended_lut = "off";
+defparam \ECHO|Add3~9 .lut_mask = 64'h0000000000000F0F;
+defparam \ECHO|Add3~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: M10K_X58_Y4_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add3~9_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr [6],\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N4
+dffeas \SPI_ADC|shift_reg[6]~DUPLICATE (
+	.clk(!\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg[6]~DUPLICATE_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6]~DUPLICATE .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[6]~DUPLICATE .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N16
+dffeas \SPI_ADC|data_from_adc[6] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg[6]~DUPLICATE_q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N48
+cyclonev_lcell_comb \ECHO|Add0~1 (
+// Equation(s):
+// \ECHO|Add0~1_sumout  = SUM(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [6] ) + ( \SPI_ADC|data_from_adc [6] ) + ( \ECHO|Add0~6  ))
+// \ECHO|Add0~2  = CARRY(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [6] ) + ( \SPI_ADC|data_from_adc [6] ) + ( \ECHO|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [6]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [6]),
+	.datag(gnd),
+	.cin(\ECHO|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~1_sumout ),
+	.cout(\ECHO|Add0~2 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~1 .extended_lut = "off";
+defparam \ECHO|Add0~1 .lut_mask = 64'h0000FF000000CCCC;
+defparam \ECHO|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: M10K_X69_Y3_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add0~1_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr[6]~DUPLICATE_q ,\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N34
+dffeas \SPI_ADC|data_from_adc[5] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N45
+cyclonev_lcell_comb \ECHO|Add0~5 (
+// Equation(s):
+// \ECHO|Add0~5_sumout  = SUM(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [5] ) + ( \SPI_ADC|data_from_adc [5] ) + ( \ECHO|Add0~10  ))
+// \ECHO|Add0~6  = CARRY(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [5] ) + ( \SPI_ADC|data_from_adc [5] ) + ( \ECHO|Add0~10  ))
+
+	.dataa(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [5]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [5]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~5_sumout ),
+	.cout(\ECHO|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~5 .extended_lut = "off";
+defparam \ECHO|Add0~5 .lut_mask = 64'h0000F0F00000AAAA;
+defparam \ECHO|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: M10K_X58_Y1_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add0~5_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr[6]~DUPLICATE_q ,\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N13
+dffeas \SPI_ADC|data_from_adc[4] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N42
+cyclonev_lcell_comb \ECHO|Add0~9 (
+// Equation(s):
+// \ECHO|Add0~9_sumout  = SUM(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [4] ) + ( \SPI_ADC|data_from_adc [4] ) + ( \ECHO|Add0~14  ))
+// \ECHO|Add0~10  = CARRY(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [4] ) + ( \SPI_ADC|data_from_adc [4] ) + ( \ECHO|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [4]),
+	.datac(!\SPI_ADC|data_from_adc [4]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~9_sumout ),
+	.cout(\ECHO|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~9 .extended_lut = "off";
+defparam \ECHO|Add0~9 .lut_mask = 64'h0000F0F00000CCCC;
+defparam \ECHO|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: M10K_X58_Y5_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add0~9_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr [6],\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N9
+cyclonev_lcell_comb \SPI_ADC|data_from_adc[3]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[3]~feeder_combout  = ( \SPI_ADC|shift_reg [3] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|data_from_adc[3]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[3]~feeder .extended_lut = "off";
+defparam \SPI_ADC|data_from_adc[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|data_from_adc[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N10
+dffeas \SPI_ADC|data_from_adc[3] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|data_from_adc[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N12
+cyclonev_lcell_comb \SPI_ADC|data_from_adc[2]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[2]~feeder_combout  = ( \SPI_ADC|shift_reg [2] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [2]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|data_from_adc[2]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2]~feeder .extended_lut = "off";
+defparam \SPI_ADC|data_from_adc[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|data_from_adc[2]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N13
+dffeas \SPI_ADC|data_from_adc[2] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|data_from_adc[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N39
+cyclonev_lcell_comb \ECHO|Add0~13 (
+// Equation(s):
+// \ECHO|Add0~13_sumout  = SUM(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [3] ) + ( \SPI_ADC|data_from_adc [3] ) + ( \ECHO|Add0~18  ))
+// \ECHO|Add0~14  = CARRY(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [3] ) + ( \SPI_ADC|data_from_adc [3] ) + ( \ECHO|Add0~18  ))
+
+	.dataa(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [3]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [3]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~13_sumout ),
+	.cout(\ECHO|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~13 .extended_lut = "off";
+defparam \ECHO|Add0~13 .lut_mask = 64'h0000F0F00000AAAA;
+defparam \ECHO|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: M10K_X69_Y1_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add0~13_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr[6]~DUPLICATE_q ,\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N15
+cyclonev_lcell_comb \SPI_ADC|data_from_adc[1]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[1]~feeder_combout  = ( \SPI_ADC|shift_reg [1] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|data_from_adc[1]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[1]~feeder .extended_lut = "off";
+defparam \SPI_ADC|data_from_adc[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|data_from_adc[1]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N16
+dffeas \SPI_ADC|data_from_adc[1] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|data_from_adc[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N36
+cyclonev_lcell_comb \ECHO|Add0~17 (
+// Equation(s):
+// \ECHO|Add0~17_sumout  = SUM(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [2] ) + ( \SPI_ADC|data_from_adc [2] ) + ( \ECHO|Add0~22  ))
+// \ECHO|Add0~18  = CARRY(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [2] ) + ( \SPI_ADC|data_from_adc [2] ) + ( \ECHO|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|data_from_adc [2]),
+	.datac(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [2]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~17_sumout ),
+	.cout(\ECHO|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~17 .extended_lut = "off";
+defparam \ECHO|Add0~17 .lut_mask = 64'h0000CCCC0000F0F0;
+defparam \ECHO|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: M10K_X69_Y2_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add0~17_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr[6]~DUPLICATE_q ,\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N33
+cyclonev_lcell_comb \ECHO|Add0~21 (
+// Equation(s):
+// \ECHO|Add0~21_sumout  = SUM(( \SPI_ADC|data_from_adc [1] ) + ( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [1] ) + ( \ECHO|Add0~26  ))
+// \ECHO|Add0~22  = CARRY(( \SPI_ADC|data_from_adc [1] ) + ( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [1] ) + ( \ECHO|Add0~26  ))
+
+	.dataa(!\SPI_ADC|data_from_adc [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [1]),
+	.datag(gnd),
+	.cin(\ECHO|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~21_sumout ),
+	.cout(\ECHO|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~21 .extended_lut = "off";
+defparam \ECHO|Add0~21 .lut_mask = 64'h000000FF00005555;
+defparam \ECHO|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: M10K_X58_Y2_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add0~21_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr [6],\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y1_N48
+cyclonev_lcell_comb \SPI_ADC|data_from_adc[0]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[0]~feeder_combout  = ( \SPI_ADC|shift_reg [0] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|shift_reg [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|data_from_adc[0]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0]~feeder .extended_lut = "off";
+defparam \SPI_ADC|data_from_adc[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_ADC|data_from_adc[0]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y1_N50
+dffeas \SPI_ADC|data_from_adc[0] (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|data_from_adc[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N30
+cyclonev_lcell_comb \ECHO|Add0~25 (
+// Equation(s):
+// \ECHO|Add0~25_sumout  = SUM(( \SPI_ADC|data_from_adc [0] ) + ( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [0] ) + ( !VCC ))
+// \ECHO|Add0~26  = CARRY(( \SPI_ADC|data_from_adc [0] ) + ( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [0] ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [0]),
+	.datac(gnd),
+	.datad(!\SPI_ADC|data_from_adc [0]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~25_sumout ),
+	.cout(\ECHO|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~25 .extended_lut = "off";
+defparam \ECHO|Add0~25 .lut_mask = 64'h00003333000000FF;
+defparam \ECHO|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N51
+cyclonev_lcell_comb \ECHO|Add0~37 (
+// Equation(s):
+// \ECHO|Add0~37_sumout  = SUM(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [7] ) + ( \SPI_ADC|data_from_adc [7] ) + ( \ECHO|Add0~2  ))
+// \ECHO|Add0~38  = CARRY(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [7] ) + ( \SPI_ADC|data_from_adc [7] ) + ( \ECHO|Add0~2  ))
+
+	.dataa(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_ADC|data_from_adc [7]),
+	.datag(gnd),
+	.cin(\ECHO|Add0~2 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~37_sumout ),
+	.cout(\ECHO|Add0~38 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~37 .extended_lut = "off";
+defparam \ECHO|Add0~37 .lut_mask = 64'h0000FF000000AAAA;
+defparam \ECHO|Add0~37 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N3
+cyclonev_lcell_comb \ECHO|Add3~5 (
+// Equation(s):
+// \ECHO|Add3~5_sumout  = SUM(( \ECHO|Add0~33_sumout  ) + ( GND ) + ( \ECHO|Add3~10  ))
+// \ECHO|Add3~6  = CARRY(( \ECHO|Add0~33_sumout  ) + ( GND ) + ( \ECHO|Add3~10  ))
+
+	.dataa(!\ECHO|Add0~33_sumout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add3~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add3~5_sumout ),
+	.cout(\ECHO|Add3~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add3~5 .extended_lut = "off";
+defparam \ECHO|Add3~5 .lut_mask = 64'h0000FFFF00005555;
+defparam \ECHO|Add3~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: M10K_X58_Y3_N0
+cyclonev_ram_block \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 (
+	.portawe(\ECHO|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(vcc),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputCLKENA0_outclk ),
+	.clk1(gnd),
+	.ena0(\ECHO|PULSE2|pulse~q ),
+	.ena1(vcc),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.nerror(vcc),
+	.portadatain({\ECHO|Add3~5_sumout }),
+	.portaaddr({\ECHO|Add2~33_sumout ,\ECHO|Add2~29_sumout ,\ECHO|Add2~25_sumout ,\ECHO|Add2~21_sumout ,\ECHO|Add2~17_sumout ,\ECHO|Add2~13_sumout ,\ECHO|Add2~9_sumout ,\ECHO|Add2~5_sumout ,\ECHO|Add2~1_sumout ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\ECHO|ctr [12],\ECHO|ctr[11]~DUPLICATE_q ,\ECHO|ctr [10],\ECHO|ctr [9],\ECHO|ctr [8],\ECHO|ctr [7],\ECHO|ctr [6],\ECHO|ctr [5],\ECHO|ctr[4]~DUPLICATE_q ,\ECHO|ctr [3],\ECHO|ctr[2]~DUPLICATE_q ,\ECHO|ctr [1],\ECHO|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ),
+	.eccstatus(),
+	.dftout());
+// synopsys translate_off
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "processor:ECHO|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_ip02:auto_generated|ALTSYNCRAM";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 8192;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 9;
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock0";
+defparam \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M20K";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N57
+cyclonev_lcell_comb \ECHO|Add0~29 (
+// Equation(s):
+// \ECHO|Add0~29_sumout  = SUM(( !\ECHO|DELAY|altsyncram_component|auto_generated|q_b [8] ) + ( \SPI_ADC|data_from_adc [9] ) + ( \ECHO|Add0~34  ))
+
+	.dataa(!\ECHO|DELAY|altsyncram_component|auto_generated|q_b [8]),
+	.datab(gnd),
+	.datac(!\SPI_ADC|data_from_adc [9]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add0~29_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add0~29 .extended_lut = "off";
+defparam \ECHO|Add0~29 .lut_mask = 64'h0000F0F00000AAAA;
+defparam \ECHO|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N6
+cyclonev_lcell_comb \ECHO|Add3~1 (
+// Equation(s):
+// \ECHO|Add3~1_sumout  = SUM(( \ECHO|Add0~29_sumout  ) + ( VCC ) + ( \ECHO|Add3~6  ))
+
+	.dataa(gnd),
+	.datab(!\ECHO|Add0~29_sumout ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\ECHO|Add3~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\ECHO|Add3~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|Add3~1 .extended_lut = "off";
+defparam \ECHO|Add3~1 .lut_mask = 64'h0000000000003333;
+defparam \ECHO|Add3~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N51
+cyclonev_lcell_comb \ECHO|data_out[9]~0 (
+// Equation(s):
+// \ECHO|data_out[9]~0_combout  = ( !\ECHO|Add3~1_sumout  )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ECHO|Add3~1_sumout ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\ECHO|data_out[9]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \ECHO|data_out[9]~0 .extended_lut = "off";
+defparam \ECHO|data_out[9]~0 .lut_mask = 64'hFFFFFFFF00000000;
+defparam \ECHO|data_out[9]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y4_N52
+dffeas \ECHO|data_out[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|data_out[9]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[9] .is_wysiwyg = "true";
+defparam \ECHO|data_out[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N30
+cyclonev_lcell_comb \SPI_DAC|shift_reg[11]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[11]~feeder_combout  = \ECHO|data_out [9]
+
+	.dataa(gnd),
+	.datab(!\ECHO|data_out [9]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[11]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[11]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[11]~feeder .lut_mask = 64'h3333333333333333;
+defparam \SPI_DAC|shift_reg[11]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N5
+dffeas \ECHO|data_out[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add3~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[8] .is_wysiwyg = "true";
+defparam \ECHO|data_out[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N33
+cyclonev_lcell_comb \SPI_DAC|shift_reg[10]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[10]~feeder_combout  = \ECHO|data_out [8]
+
+	.dataa(!\ECHO|data_out [8]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[10]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[10]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[10]~feeder .lut_mask = 64'h5555555555555555;
+defparam \SPI_DAC|shift_reg[10]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N2
+dffeas \ECHO|data_out[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add3~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[7] .is_wysiwyg = "true";
+defparam \ECHO|data_out[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N36
+cyclonev_lcell_comb \SPI_DAC|shift_reg[9]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[9]~feeder_combout  = \ECHO|data_out [7]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|data_out [7]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[9]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[9]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[9]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \SPI_DAC|shift_reg[9]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N50
+dffeas \ECHO|data_out[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add0~1_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[6] .is_wysiwyg = "true";
+defparam \ECHO|data_out[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N15
+cyclonev_lcell_comb \SPI_DAC|shift_reg[8]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[8]~feeder_combout  = ( \ECHO|data_out [6] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ECHO|data_out [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[8]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[8]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[8]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_DAC|shift_reg[8]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N47
+dffeas \ECHO|data_out[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[5] .is_wysiwyg = "true";
+defparam \ECHO|data_out[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N18
+cyclonev_lcell_comb \SPI_DAC|shift_reg[7]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[7]~feeder_combout  = \ECHO|data_out [5]
+
+	.dataa(gnd),
+	.datab(!\ECHO|data_out [5]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[7]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[7]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[7]~feeder .lut_mask = 64'h3333333333333333;
+defparam \SPI_DAC|shift_reg[7]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N44
+dffeas \ECHO|data_out[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add0~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[4] .is_wysiwyg = "true";
+defparam \ECHO|data_out[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N21
+cyclonev_lcell_comb \SPI_DAC|shift_reg[6]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[6]~feeder_combout  = ( \ECHO|data_out [4] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ECHO|data_out [4]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[6]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \SPI_DAC|shift_reg[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N41
+dffeas \ECHO|data_out[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add0~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[3] .is_wysiwyg = "true";
+defparam \ECHO|data_out[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N24
+cyclonev_lcell_comb \SPI_DAC|shift_reg[5]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[5]~feeder_combout  = \ECHO|data_out [3]
+
+	.dataa(gnd),
+	.datab(!\ECHO|data_out [3]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[5]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[5]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[5]~feeder .lut_mask = 64'h3333333333333333;
+defparam \SPI_DAC|shift_reg[5]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N38
+dffeas \ECHO|data_out[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add0~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[2] .is_wysiwyg = "true";
+defparam \ECHO|data_out[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N27
+cyclonev_lcell_comb \SPI_DAC|shift_reg[4]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[4]~feeder_combout  = \ECHO|data_out [2]
+
+	.dataa(!\ECHO|data_out [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[4]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[4]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[4]~feeder .lut_mask = 64'h5555555555555555;
+defparam \SPI_DAC|shift_reg[4]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N35
+dffeas \ECHO|data_out[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add0~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[1] .is_wysiwyg = "true";
+defparam \ECHO|data_out[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y3_N12
+cyclonev_lcell_comb \SPI_DAC|shift_reg[3]~feeder (
+// Equation(s):
+// \SPI_DAC|shift_reg[3]~feeder_combout  = \ECHO|data_out [1]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\ECHO|data_out [1]),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg[3]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[3]~feeder .extended_lut = "off";
+defparam \SPI_DAC|shift_reg[3]~feeder .lut_mask = 64'h0F0F0F0F0F0F0F0F;
+defparam \SPI_DAC|shift_reg[3]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N31
+dffeas \ECHO|data_out[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\ECHO|Add0~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\ECHO|data_out [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \ECHO|data_out[0] .is_wysiwyg = "true";
+defparam \ECHO|data_out[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N24
+cyclonev_lcell_comb \SPI_DAC|shift_reg~4 (
+// Equation(s):
+// \SPI_DAC|shift_reg~4_combout  = ( \ECHO|data_out [0] & ( !\SPI_DAC|dac_cs~q  & ( \SPI_DAC|dac_start~q  ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_DAC|dac_start~q ),
+	.datad(gnd),
+	.datae(!\ECHO|data_out [0]),
+	.dataf(!\SPI_DAC|dac_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~4 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~4 .lut_mask = 64'h00000F0F00000000;
+defparam \SPI_DAC|shift_reg~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N26
+dffeas \SPI_DAC|shift_reg[2] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X64_Y1_N18
+cyclonev_lcell_comb \SPI_DAC|always3~0 (
+// Equation(s):
+// \SPI_DAC|always3~0_combout  = ( \SPI_DAC|dac_start~q  & ( \SPI_DAC|dac_cs~q  ) ) # ( !\SPI_DAC|dac_start~q  & ( \SPI_DAC|dac_cs~q  ) ) # ( !\SPI_DAC|dac_start~q  & ( !\SPI_DAC|dac_cs~q  ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SPI_DAC|dac_start~q ),
+	.dataf(!\SPI_DAC|dac_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|always3~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|always3~0 .extended_lut = "off";
+defparam \SPI_DAC|always3~0 .lut_mask = 64'hFFFF0000FFFFFFFF;
+defparam \SPI_DAC|always3~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N14
+dffeas \SPI_DAC|shift_reg[3] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[3]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N29
+dffeas \SPI_DAC|shift_reg[4] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[4]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N26
+dffeas \SPI_DAC|shift_reg[5] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[5]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N23
+dffeas \SPI_DAC|shift_reg[6] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[6]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N20
+dffeas \SPI_DAC|shift_reg[7] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[7]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y3_N16
+dffeas \SPI_DAC|shift_reg[8] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[8]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y4_N38
+dffeas \SPI_DAC|shift_reg[9] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[9]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y4_N35
+dffeas \SPI_DAC|shift_reg[10] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[10]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[10] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X63_Y4_N32
+dffeas \SPI_DAC|shift_reg[11] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg[11]~feeder_combout ),
+	.asdata(\SPI_DAC|shift_reg [10]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(\SPI_DAC|always3~0_combout ),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[11] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N39
+cyclonev_lcell_comb \SPI_DAC|shift_reg~3 (
+// Equation(s):
+// \SPI_DAC|shift_reg~3_combout  = ( \SPI_DAC|dac_start~q  & ( (!\SPI_DAC|dac_cs~q ) # (\SPI_DAC|shift_reg [11]) ) ) # ( !\SPI_DAC|dac_start~q  & ( \SPI_DAC|shift_reg [11] ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|shift_reg [11]),
+	.datac(!\SPI_DAC|dac_cs~q ),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|dac_start~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~3 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~3 .lut_mask = 64'h33333333F3F3F3F3;
+defparam \SPI_DAC|shift_reg~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y4_N40
+dffeas \SPI_DAC|shift_reg[12] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[12] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y4_N54
+cyclonev_lcell_comb \SPI_DAC|shift_reg~2 (
+// Equation(s):
+// \SPI_DAC|shift_reg~2_combout  = ( \SPI_DAC|dac_start~q  & ( (!\SPI_DAC|dac_cs~q ) # (\SPI_DAC|shift_reg [12]) ) ) # ( !\SPI_DAC|dac_start~q  & ( \SPI_DAC|shift_reg [12] ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_DAC|dac_cs~q ),
+	.datac(gnd),
+	.datad(!\SPI_DAC|shift_reg [12]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|dac_start~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~2 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~2 .lut_mask = 64'h00FF00FFCCFFCCFF;
+defparam \SPI_DAC|shift_reg~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y4_N55
+dffeas \SPI_DAC|shift_reg[13] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[13] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N39
+cyclonev_lcell_comb \SPI_DAC|shift_reg~1 (
+// Equation(s):
+// \SPI_DAC|shift_reg~1_combout  = ( \SPI_DAC|dac_cs~q  & ( \SPI_DAC|shift_reg [13] ) ) # ( !\SPI_DAC|dac_cs~q  & ( (\SPI_DAC|shift_reg [13]) # (\SPI_DAC|dac_start~q ) ) )
+
+	.dataa(!\SPI_DAC|dac_start~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\SPI_DAC|shift_reg [13]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|dac_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~1 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~1 .lut_mask = 64'h55FF55FF00FF00FF;
+defparam \SPI_DAC|shift_reg~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N41
+dffeas \SPI_DAC|shift_reg[14] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[14] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N15
+cyclonev_lcell_comb \SPI_DAC|shift_reg~0 (
+// Equation(s):
+// \SPI_DAC|shift_reg~0_combout  = ( \SPI_DAC|dac_start~q  & ( \SPI_DAC|dac_cs~q  & ( \SPI_DAC|shift_reg [14] ) ) ) # ( !\SPI_DAC|dac_start~q  & ( \SPI_DAC|dac_cs~q  & ( \SPI_DAC|shift_reg [14] ) ) ) # ( !\SPI_DAC|dac_start~q  & ( !\SPI_DAC|dac_cs~q  & ( 
+// \SPI_DAC|shift_reg [14] ) ) )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\SPI_DAC|shift_reg [14]),
+	.datad(gnd),
+	.datae(!\SPI_DAC|dac_start~q ),
+	.dataf(!\SPI_DAC|dac_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|shift_reg~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~0 .extended_lut = "off";
+defparam \SPI_DAC|shift_reg~0 .lut_mask = 64'h0F0F00000F0F0F0F;
+defparam \SPI_DAC|shift_reg~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N16
+dffeas \SPI_DAC|shift_reg[15] (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|shift_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[15] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N21
+cyclonev_lcell_comb \SPI_DAC|dac_sck (
+// Equation(s):
+// \SPI_DAC|dac_sck~combout  = ( \SPI_DAC|dac_cs~q  & ( \SPI_DAC|clk_1MHz~q  ) ) # ( !\SPI_DAC|dac_cs~q  )
+
+	.dataa(!\SPI_DAC|clk_1MHz~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|dac_cs~q ),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|dac_sck~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_sck .extended_lut = "off";
+defparam \SPI_DAC|dac_sck .lut_mask = 64'hFFFFFFFF55555555;
+defparam \SPI_DAC|dac_sck .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X62_Y2_N0
+cyclonev_lcell_comb \SPI_DAC|Equal2~0 (
+// Equation(s):
+// \SPI_DAC|Equal2~0_combout  = ( \SPI_DAC|state [3] ) # ( !\SPI_DAC|state [3] & ( (((!\SPI_DAC|state [4]) # (\SPI_DAC|state [0])) # (\SPI_DAC|state [2])) # (\SPI_DAC|state [1]) ) )
+
+	.dataa(!\SPI_DAC|state [1]),
+	.datab(!\SPI_DAC|state [2]),
+	.datac(!\SPI_DAC|state [4]),
+	.datad(!\SPI_DAC|state [0]),
+	.datae(gnd),
+	.dataf(!\SPI_DAC|state [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_DAC|Equal2~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal2~0 .extended_lut = "off";
+defparam \SPI_DAC|Equal2~0 .lut_mask = 64'hF7FFF7FFFFFFFFFF;
+defparam \SPI_DAC|Equal2~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X62_Y2_N1
+dffeas \SPI_DAC|dac_ld (
+	.clk(\SPI_DAC|clk_1MHz~q ),
+	.d(\SPI_DAC|Equal2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_ld~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_ld .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_ld .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X2_Y0_N58
+cyclonev_io_ibuf \SW[9]~input (
+	.i(SW[9]),
+	.ibar(gnd),
+	.dynamicterminationcontrol(gnd),
+	.o(\SW[9]~input_o ));
+// synopsys translate_off
+defparam \SW[9]~input .bus_hold = "false";
+defparam \SW[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LABCELL_X63_Y2_N30
+cyclonev_lcell_comb \SPI_ADC|Selector6~0 (
+// Equation(s):
+// \SPI_ADC|Selector6~0_combout  = ( !\SPI_ADC|state [1] & ( (!\SPI_ADC|state [2] & (!\SPI_ADC|state [4] & (!\SPI_ADC|state [3] & ((\SPI_ADC|adc_start~q ) # (\SPI_ADC|state [0]))))) ) ) # ( \SPI_ADC|state [1] & ( (!\SPI_ADC|state [2] & (!\SPI_ADC|state [4] & 
+// (!\SPI_ADC|state [3] & ((\SW[9]~input_o ) # (\SPI_ADC|state [0]))))) ) )
+
+	.dataa(!\SPI_ADC|state [2]),
+	.datab(!\SPI_ADC|state [0]),
+	.datac(!\SW[9]~input_o ),
+	.datad(!\SPI_ADC|state [4]),
+	.datae(!\SPI_ADC|state [1]),
+	.dataf(!\SPI_ADC|state [3]),
+	.datag(!\SPI_ADC|adc_start~q ),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|Selector6~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~0 .extended_lut = "on";
+defparam \SPI_ADC|Selector6~0 .lut_mask = 64'h2A002A0000000000;
+defparam \SPI_ADC|Selector6~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X63_Y2_N31
+dffeas \SPI_ADC|adc_din (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Selector6~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_din~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_din .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_din .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X61_Y2_N48
+cyclonev_lcell_comb \SPI_ADC|adc_sck (
+// Equation(s):
+// \SPI_ADC|adc_sck~combout  = ( \SPI_ADC|clk_1MHz~q  ) # ( !\SPI_ADC|clk_1MHz~q  & ( !\SPI_ADC|adc_cs~q  ) )
+
+	.dataa(gnd),
+	.datab(!\SPI_ADC|adc_cs~q ),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\SPI_ADC|clk_1MHz~q ),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\SPI_ADC|adc_sck~combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_sck .extended_lut = "off";
+defparam \SPI_ADC|adc_sck .lut_mask = 64'hCCCCFFFFCCCCFFFF;
+defparam \SPI_ADC|adc_sck .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X55_Y2_N0
+cyclonev_lcell_comb \PWM_DC|count[0]~0 (
+// Equation(s):
+// \PWM_DC|count[0]~0_combout  = ( !\PWM_DC|count [0] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(!\PWM_DC|count [0]),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|count[0]~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|count[0]~0 .extended_lut = "off";
+defparam \PWM_DC|count[0]~0 .lut_mask = 64'hFFFF0000FFFF0000;
+defparam \PWM_DC|count[0]~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X55_Y2_N1
+dffeas \PWM_DC|count[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|count[0]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[0] .is_wysiwyg = "true";
+defparam \PWM_DC|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N0
+cyclonev_lcell_comb \PWM_DC|Add0~33 (
+// Equation(s):
+// \PWM_DC|Add0~33_sumout  = SUM(( \PWM_DC|count [1] ) + ( \PWM_DC|count [0] ) + ( !VCC ))
+// \PWM_DC|Add0~34  = CARRY(( \PWM_DC|count [1] ) + ( \PWM_DC|count [0] ) + ( !VCC ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\PWM_DC|count [0]),
+	.datad(!\PWM_DC|count [1]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~33_sumout ),
+	.cout(\PWM_DC|Add0~34 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~33 .extended_lut = "off";
+defparam \PWM_DC|Add0~33 .lut_mask = 64'h0000F0F0000000FF;
+defparam \PWM_DC|Add0~33 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N2
+dffeas \PWM_DC|count[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~33_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[1] .is_wysiwyg = "true";
+defparam \PWM_DC|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N3
+cyclonev_lcell_comb \PWM_DC|Add0~29 (
+// Equation(s):
+// \PWM_DC|Add0~29_sumout  = SUM(( \PWM_DC|count [2] ) + ( GND ) + ( \PWM_DC|Add0~34  ))
+// \PWM_DC|Add0~30  = CARRY(( \PWM_DC|count [2] ) + ( GND ) + ( \PWM_DC|Add0~34  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [2]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~34 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~29_sumout ),
+	.cout(\PWM_DC|Add0~30 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~29 .extended_lut = "off";
+defparam \PWM_DC|Add0~29 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~29 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N5
+dffeas \PWM_DC|count[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~29_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[2] .is_wysiwyg = "true";
+defparam \PWM_DC|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N6
+cyclonev_lcell_comb \PWM_DC|Add0~25 (
+// Equation(s):
+// \PWM_DC|Add0~25_sumout  = SUM(( \PWM_DC|count [3] ) + ( GND ) + ( \PWM_DC|Add0~30  ))
+// \PWM_DC|Add0~26  = CARRY(( \PWM_DC|count [3] ) + ( GND ) + ( \PWM_DC|Add0~30  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [3]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~30 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~25_sumout ),
+	.cout(\PWM_DC|Add0~26 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~25 .extended_lut = "off";
+defparam \PWM_DC|Add0~25 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~25 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N7
+dffeas \PWM_DC|count[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~25_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[3] .is_wysiwyg = "true";
+defparam \PWM_DC|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N9
+cyclonev_lcell_comb \PWM_DC|Add0~21 (
+// Equation(s):
+// \PWM_DC|Add0~21_sumout  = SUM(( \PWM_DC|count [4] ) + ( GND ) + ( \PWM_DC|Add0~26  ))
+// \PWM_DC|Add0~22  = CARRY(( \PWM_DC|count [4] ) + ( GND ) + ( \PWM_DC|Add0~26  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [4]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~26 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~21_sumout ),
+	.cout(\PWM_DC|Add0~22 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~21 .extended_lut = "off";
+defparam \PWM_DC|Add0~21 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~21 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N10
+dffeas \PWM_DC|count[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~21_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[4] .is_wysiwyg = "true";
+defparam \PWM_DC|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N12
+cyclonev_lcell_comb \PWM_DC|Add0~17 (
+// Equation(s):
+// \PWM_DC|Add0~17_sumout  = SUM(( \PWM_DC|count [5] ) + ( GND ) + ( \PWM_DC|Add0~22  ))
+// \PWM_DC|Add0~18  = CARRY(( \PWM_DC|count [5] ) + ( GND ) + ( \PWM_DC|Add0~22  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [5]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~22 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~17_sumout ),
+	.cout(\PWM_DC|Add0~18 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~17 .extended_lut = "off";
+defparam \PWM_DC|Add0~17 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~17 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N14
+dffeas \PWM_DC|count[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~17_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[5] .is_wysiwyg = "true";
+defparam \PWM_DC|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N15
+cyclonev_lcell_comb \PWM_DC|Add0~13 (
+// Equation(s):
+// \PWM_DC|Add0~13_sumout  = SUM(( \PWM_DC|count [6] ) + ( GND ) + ( \PWM_DC|Add0~18  ))
+// \PWM_DC|Add0~14  = CARRY(( \PWM_DC|count [6] ) + ( GND ) + ( \PWM_DC|Add0~18  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [6]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~18 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~13_sumout ),
+	.cout(\PWM_DC|Add0~14 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~13 .extended_lut = "off";
+defparam \PWM_DC|Add0~13 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~13 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N17
+dffeas \PWM_DC|count[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~13_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[6] .is_wysiwyg = "true";
+defparam \PWM_DC|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N18
+cyclonev_lcell_comb \PWM_DC|Add0~9 (
+// Equation(s):
+// \PWM_DC|Add0~9_sumout  = SUM(( \PWM_DC|count [7] ) + ( GND ) + ( \PWM_DC|Add0~14  ))
+// \PWM_DC|Add0~10  = CARRY(( \PWM_DC|count [7] ) + ( GND ) + ( \PWM_DC|Add0~14  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~14 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~9_sumout ),
+	.cout(\PWM_DC|Add0~10 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~9 .extended_lut = "off";
+defparam \PWM_DC|Add0~9 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~9 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N20
+dffeas \PWM_DC|count[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~9_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[7] .is_wysiwyg = "true";
+defparam \PWM_DC|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N21
+cyclonev_lcell_comb \PWM_DC|Add0~5 (
+// Equation(s):
+// \PWM_DC|Add0~5_sumout  = SUM(( \PWM_DC|count [8] ) + ( GND ) + ( \PWM_DC|Add0~10  ))
+// \PWM_DC|Add0~6  = CARRY(( \PWM_DC|count [8] ) + ( GND ) + ( \PWM_DC|Add0~10  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [8]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~10 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~5_sumout ),
+	.cout(\PWM_DC|Add0~6 ),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~5 .extended_lut = "off";
+defparam \PWM_DC|Add0~5 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N22
+dffeas \PWM_DC|count[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~5_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[8] .is_wysiwyg = "true";
+defparam \PWM_DC|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N24
+cyclonev_lcell_comb \PWM_DC|Add0~1 (
+// Equation(s):
+// \PWM_DC|Add0~1_sumout  = SUM(( \PWM_DC|count [9] ) + ( GND ) + ( \PWM_DC|Add0~6  ))
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(!\PWM_DC|count [9]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(\PWM_DC|Add0~6 ),
+	.sharein(gnd),
+	.combout(),
+	.sumout(\PWM_DC|Add0~1_sumout ),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|Add0~1 .extended_lut = "off";
+defparam \PWM_DC|Add0~1 .lut_mask = 64'h0000FFFF000000FF;
+defparam \PWM_DC|Add0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N26
+dffeas \PWM_DC|count[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|Add0~1_sumout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[9] .is_wysiwyg = "true";
+defparam \PWM_DC|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N52
+dffeas \PWM_DC|d[7] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ECHO|data_out [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[7] .is_wysiwyg = "true";
+defparam \PWM_DC|d[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N54
+cyclonev_lcell_comb \PWM_DC|LessThan0~0 (
+// Equation(s):
+// \PWM_DC|LessThan0~0_combout  = ( \PWM_DC|count [7] & ( !\PWM_DC|d [7] ) )
+
+	.dataa(gnd),
+	.datab(!\PWM_DC|d [7]),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\PWM_DC|count [7]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~0_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~0 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~0 .lut_mask = 64'h00000000CCCCCCCC;
+defparam \PWM_DC|LessThan0~0 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N51
+cyclonev_lcell_comb \PWM_DC|LessThan0~1 (
+// Equation(s):
+// \PWM_DC|LessThan0~1_combout  = !\PWM_DC|count [7] $ (!\PWM_DC|d [7])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(!\PWM_DC|count [7]),
+	.datad(!\PWM_DC|d [7]),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~1_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~1 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~1 .lut_mask = 64'h0FF00FF00FF00FF0;
+defparam \PWM_DC|LessThan0~1 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N57
+cyclonev_lcell_comb \PWM_DC|d[0]~feeder (
+// Equation(s):
+// \PWM_DC|d[0]~feeder_combout  = ( \ECHO|data_out [0] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ECHO|data_out [0]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|d[0]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|d[0]~feeder .extended_lut = "off";
+defparam \PWM_DC|d[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \PWM_DC|d[0]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N59
+dffeas \PWM_DC|d[0] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|d[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[0] .is_wysiwyg = "true";
+defparam \PWM_DC|d[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N44
+dffeas \PWM_DC|d[2] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ECHO|data_out [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[2] .is_wysiwyg = "true";
+defparam \PWM_DC|d[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N58
+dffeas \PWM_DC|d[1] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ECHO|data_out [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[1] .is_wysiwyg = "true";
+defparam \PWM_DC|d[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N42
+cyclonev_lcell_comb \PWM_DC|LessThan0~2 (
+// Equation(s):
+// \PWM_DC|LessThan0~2_combout  = ( \PWM_DC|d [2] & ( \PWM_DC|d [1] & ( (\PWM_DC|count [2] & (!\PWM_DC|d [0] & (\PWM_DC|count [1] & \PWM_DC|count [0]))) ) ) ) # ( !\PWM_DC|d [2] & ( \PWM_DC|d [1] & ( ((!\PWM_DC|d [0] & (\PWM_DC|count [1] & \PWM_DC|count 
+// [0]))) # (\PWM_DC|count [2]) ) ) ) # ( \PWM_DC|d [2] & ( !\PWM_DC|d [1] & ( (\PWM_DC|count [2] & (((!\PWM_DC|d [0] & \PWM_DC|count [0])) # (\PWM_DC|count [1]))) ) ) ) # ( !\PWM_DC|d [2] & ( !\PWM_DC|d [1] & ( (((!\PWM_DC|d [0] & \PWM_DC|count [0])) # 
+// (\PWM_DC|count [1])) # (\PWM_DC|count [2]) ) ) )
+
+	.dataa(!\PWM_DC|count [2]),
+	.datab(!\PWM_DC|d [0]),
+	.datac(!\PWM_DC|count [1]),
+	.datad(!\PWM_DC|count [0]),
+	.datae(!\PWM_DC|d [2]),
+	.dataf(!\PWM_DC|d [1]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~2_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~2 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~2 .lut_mask = 64'h5FDF0545555D0004;
+defparam \PWM_DC|LessThan0~2 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N50
+dffeas \PWM_DC|d[4] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ECHO|data_out [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[4] .is_wysiwyg = "true";
+defparam \PWM_DC|d[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X62_Y3_N2
+dffeas \PWM_DC|d[3] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ECHO|data_out [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[3] .is_wysiwyg = "true";
+defparam \PWM_DC|d[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N48
+cyclonev_lcell_comb \PWM_DC|LessThan0~3 (
+// Equation(s):
+// \PWM_DC|LessThan0~3_combout  = ( \PWM_DC|d [3] & ( (!\PWM_DC|count [4] & (\PWM_DC|count [3] & (\PWM_DC|LessThan0~2_combout  & !\PWM_DC|d [4]))) # (\PWM_DC|count [4] & ((!\PWM_DC|d [4]) # ((\PWM_DC|count [3] & \PWM_DC|LessThan0~2_combout )))) ) ) # ( 
+// !\PWM_DC|d [3] & ( (!\PWM_DC|count [4] & (!\PWM_DC|d [4] & ((\PWM_DC|LessThan0~2_combout ) # (\PWM_DC|count [3])))) # (\PWM_DC|count [4] & (((!\PWM_DC|d [4]) # (\PWM_DC|LessThan0~2_combout )) # (\PWM_DC|count [3]))) ) )
+
+	.dataa(!\PWM_DC|count [3]),
+	.datab(!\PWM_DC|LessThan0~2_combout ),
+	.datac(!\PWM_DC|count [4]),
+	.datad(!\PWM_DC|d [4]),
+	.datae(gnd),
+	.dataf(!\PWM_DC|d [3]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~3_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~3 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~3 .lut_mask = 64'h7F077F071F011F01;
+defparam \PWM_DC|LessThan0~3 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N38
+dffeas \PWM_DC|d[5] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ECHO|data_out [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[5] .is_wysiwyg = "true";
+defparam \PWM_DC|d[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y4_N3
+cyclonev_lcell_comb \PWM_DC|d[6]~feeder (
+// Equation(s):
+// \PWM_DC|d[6]~feeder_combout  = ( \ECHO|data_out [6] )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(!\ECHO|data_out [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|d[6]~feeder_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|d[6]~feeder .extended_lut = "off";
+defparam \PWM_DC|d[6]~feeder .lut_mask = 64'h00000000FFFFFFFF;
+defparam \PWM_DC|d[6]~feeder .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y4_N4
+dffeas \PWM_DC|d[6] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|d[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[6] .is_wysiwyg = "true";
+defparam \PWM_DC|d[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N36
+cyclonev_lcell_comb \PWM_DC|LessThan0~4 (
+// Equation(s):
+// \PWM_DC|LessThan0~4_combout  = ( \PWM_DC|d [5] & ( \PWM_DC|d [6] & ( (!\PWM_DC|LessThan0~1_combout  & (\PWM_DC|count [5] & (\PWM_DC|LessThan0~3_combout  & \PWM_DC|count [6]))) ) ) ) # ( !\PWM_DC|d [5] & ( \PWM_DC|d [6] & ( (!\PWM_DC|LessThan0~1_combout  & 
+// (\PWM_DC|count [6] & ((\PWM_DC|LessThan0~3_combout ) # (\PWM_DC|count [5])))) ) ) ) # ( \PWM_DC|d [5] & ( !\PWM_DC|d [6] & ( (!\PWM_DC|LessThan0~1_combout  & (((\PWM_DC|count [5] & \PWM_DC|LessThan0~3_combout )) # (\PWM_DC|count [6]))) ) ) ) # ( 
+// !\PWM_DC|d [5] & ( !\PWM_DC|d [6] & ( (!\PWM_DC|LessThan0~1_combout  & (((\PWM_DC|count [6]) # (\PWM_DC|LessThan0~3_combout )) # (\PWM_DC|count [5]))) ) ) )
+
+	.dataa(!\PWM_DC|LessThan0~1_combout ),
+	.datab(!\PWM_DC|count [5]),
+	.datac(!\PWM_DC|LessThan0~3_combout ),
+	.datad(!\PWM_DC|count [6]),
+	.datae(!\PWM_DC|d [5]),
+	.dataf(!\PWM_DC|d [6]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~4_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~4 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~4 .lut_mask = 64'h2AAA02AA002A0002;
+defparam \PWM_DC|LessThan0~4 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N46
+dffeas \PWM_DC|d[8] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ECHO|data_out [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[8] .is_wysiwyg = "true";
+defparam \PWM_DC|d[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N41
+dffeas \PWM_DC|d[9] (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(gnd),
+	.asdata(\ECHO|data_out [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[9] .is_wysiwyg = "true";
+defparam \PWM_DC|d[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LABCELL_X60_Y3_N30
+cyclonev_lcell_comb \PWM_DC|LessThan0~5 (
+// Equation(s):
+// \PWM_DC|LessThan0~5_combout  = ( \PWM_DC|d [8] & ( \PWM_DC|d [9] & ( (!\PWM_DC|count [9]) # ((!\PWM_DC|count [8]) # ((!\PWM_DC|LessThan0~0_combout  & !\PWM_DC|LessThan0~4_combout ))) ) ) ) # ( !\PWM_DC|d [8] & ( \PWM_DC|d [9] & ( (!\PWM_DC|count [9]) # 
+// ((!\PWM_DC|count [8] & (!\PWM_DC|LessThan0~0_combout  & !\PWM_DC|LessThan0~4_combout ))) ) ) ) # ( \PWM_DC|d [8] & ( !\PWM_DC|d [9] & ( (!\PWM_DC|count [9] & ((!\PWM_DC|count [8]) # ((!\PWM_DC|LessThan0~0_combout  & !\PWM_DC|LessThan0~4_combout )))) ) ) ) 
+// # ( !\PWM_DC|d [8] & ( !\PWM_DC|d [9] & ( (!\PWM_DC|count [9] & (!\PWM_DC|count [8] & (!\PWM_DC|LessThan0~0_combout  & !\PWM_DC|LessThan0~4_combout ))) ) ) )
+
+	.dataa(!\PWM_DC|count [9]),
+	.datab(!\PWM_DC|count [8]),
+	.datac(!\PWM_DC|LessThan0~0_combout ),
+	.datad(!\PWM_DC|LessThan0~4_combout ),
+	.datae(!\PWM_DC|d [8]),
+	.dataf(!\PWM_DC|d [9]),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\PWM_DC|LessThan0~5_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~5 .extended_lut = "off";
+defparam \PWM_DC|LessThan0~5 .lut_mask = 64'h8000A888EAAAFEEE;
+defparam \PWM_DC|LessThan0~5 .shared_arith = "off";
+// synopsys translate_on
+
+// Location: FF_X60_Y3_N31
+dffeas \PWM_DC|pwm_out (
+	.clk(\CLOCK_50~inputCLKENA0_outclk ),
+	.d(\PWM_DC|LessThan0~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|pwm_out~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|pwm_out .is_wysiwyg = "true";
+defparam \PWM_DC|pwm_out .power_up = "low";
+// synopsys translate_on
+
+// Location: MLABCELL_X21_Y73_N0
+cyclonev_lcell_comb \~QUARTUS_CREATED_GND~I (
+// Equation(s):
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.datae(gnd),
+	.dataf(gnd),
+	.datag(gnd),
+	.cin(gnd),
+	.sharein(gnd),
+	.combout(\~QUARTUS_CREATED_GND~I_combout ),
+	.sumout(),
+	.cout(),
+	.shareout());
+// synopsys translate_off
+defparam \~QUARTUS_CREATED_GND~I .extended_lut = "off";
+defparam \~QUARTUS_CREATED_GND~I .lut_mask = 64'h0000000000000000;
+defparam \~QUARTUS_CREATED_GND~I .shared_arith = "off";
+// synopsys translate_on
+
+endmodule
diff --git a/part_4/ex16/simulation/modelsim/top_6_1200mv_0c_slow.vo b/part_4/ex16/simulation/modelsim/top_6_1200mv_0c_slow.vo
new file mode 100755
index 0000000..3e0db2f
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_6_1200mv_0c_slow.vo
@@ -0,0 +1,9959 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 32-bit"
+// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+// DATE "02/18/2014 18:26:56"
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module top (
+	CLOCK_50,
+	SW,
+	HEX0_D,
+	HEX1_D,
+	HEX2_D,
+	HEX3_D,
+	DAC_SDI,
+	SCK,
+	DAC_CS,
+	DAC_LD,
+	ADC_SDI,
+	ADC_CS,
+	ADC_SDO,
+	LEDG,
+	PWM_OUT);
+input 	CLOCK_50;
+input 	[9:0] SW;
+output 	[6:0] HEX0_D;
+output 	[6:0] HEX1_D;
+output 	[6:0] HEX2_D;
+output 	[6:0] HEX3_D;
+output 	DAC_SDI;
+output 	SCK;
+output 	DAC_CS;
+output 	DAC_LD;
+output 	ADC_SDI;
+output 	ADC_CS;
+input 	ADC_SDO;
+output 	[9:0] LEDG;
+output 	PWM_OUT;
+
+// Design Ports Information
+// HEX0_D[0]	=>  Location: PIN_E11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[1]	=>  Location: PIN_F11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[2]	=>  Location: PIN_H12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[3]	=>  Location: PIN_H13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[4]	=>  Location: PIN_G12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[5]	=>  Location: PIN_F12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[6]	=>  Location: PIN_F13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[0]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[1]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[2]	=>  Location: PIN_C13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[3]	=>  Location: PIN_A14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[4]	=>  Location: PIN_B14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[5]	=>  Location: PIN_E14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[6]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[0]	=>  Location: PIN_D15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[1]	=>  Location: PIN_A16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[2]	=>  Location: PIN_B16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[3]	=>  Location: PIN_E15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[4]	=>  Location: PIN_A17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[5]	=>  Location: PIN_B17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[6]	=>  Location: PIN_F14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[0]	=>  Location: PIN_B18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[1]	=>  Location: PIN_F15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[2]	=>  Location: PIN_A19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[3]	=>  Location: PIN_B19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[4]	=>  Location: PIN_C19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[5]	=>  Location: PIN_D19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[6]	=>  Location: PIN_G15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_SDI	=>  Location: PIN_V5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SCK	=>  Location: PIN_W10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_CS	=>  Location: PIN_V12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_LD	=>  Location: PIN_W13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// ADC_SDI	=>  Location: PIN_V8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// ADC_CS	=>  Location: PIN_W6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[0]	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[1]	=>  Location: PIN_J2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[2]	=>  Location: PIN_J3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[3]	=>  Location: PIN_H1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[4]	=>  Location: PIN_F2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[5]	=>  Location: PIN_E1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[6]	=>  Location: PIN_C1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[7]	=>  Location: PIN_C2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[8]	=>  Location: PIN_B2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[9]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// PWM_OUT	=>  Location: PIN_U14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SW[3]	=>  Location: PIN_G4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[2]	=>  Location: PIN_H6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[1]	=>  Location: PIN_H5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[0]	=>  Location: PIN_J6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[7]	=>  Location: PIN_E3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[6]	=>  Location: PIN_H7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[5]	=>  Location: PIN_J7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[4]	=>  Location: PIN_G5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[8]	=>  Location: PIN_E4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// CLOCK_50	=>  Location: PIN_G21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[9]	=>  Location: PIN_D2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ADC_SDO	=>  Location: PIN_U7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("top_6_1200mv_0c_v_slow.sdo");
+// synopsys translate_on
+
+wire \HEX0_D[0]~output_o ;
+wire \HEX0_D[1]~output_o ;
+wire \HEX0_D[2]~output_o ;
+wire \HEX0_D[3]~output_o ;
+wire \HEX0_D[4]~output_o ;
+wire \HEX0_D[5]~output_o ;
+wire \HEX0_D[6]~output_o ;
+wire \HEX1_D[0]~output_o ;
+wire \HEX1_D[1]~output_o ;
+wire \HEX1_D[2]~output_o ;
+wire \HEX1_D[3]~output_o ;
+wire \HEX1_D[4]~output_o ;
+wire \HEX1_D[5]~output_o ;
+wire \HEX1_D[6]~output_o ;
+wire \HEX2_D[0]~output_o ;
+wire \HEX2_D[1]~output_o ;
+wire \HEX2_D[2]~output_o ;
+wire \HEX2_D[3]~output_o ;
+wire \HEX2_D[4]~output_o ;
+wire \HEX2_D[5]~output_o ;
+wire \HEX2_D[6]~output_o ;
+wire \HEX3_D[0]~output_o ;
+wire \HEX3_D[1]~output_o ;
+wire \HEX3_D[2]~output_o ;
+wire \HEX3_D[3]~output_o ;
+wire \HEX3_D[4]~output_o ;
+wire \HEX3_D[5]~output_o ;
+wire \HEX3_D[6]~output_o ;
+wire \DAC_SDI~output_o ;
+wire \SCK~output_o ;
+wire \DAC_CS~output_o ;
+wire \DAC_LD~output_o ;
+wire \ADC_SDI~output_o ;
+wire \ADC_CS~output_o ;
+wire \LEDG[0]~output_o ;
+wire \LEDG[1]~output_o ;
+wire \LEDG[2]~output_o ;
+wire \LEDG[3]~output_o ;
+wire \LEDG[4]~output_o ;
+wire \LEDG[5]~output_o ;
+wire \LEDG[6]~output_o ;
+wire \LEDG[7]~output_o ;
+wire \LEDG[8]~output_o ;
+wire \LEDG[9]~output_o ;
+wire \PWM_OUT~output_o ;
+wire \SW[8]~input_o ;
+wire \SW[7]~input_o ;
+wire \SW[6]~input_o ;
+wire \SW[5]~input_o ;
+wire \SW[4]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ;
+wire \SW[3]~input_o ;
+wire \SW[2]~input_o ;
+wire \SW[0]~input_o ;
+wire \SW[1]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ;
+wire \BCD_CONVERT|A9|WideOr2~0_combout ;
+wire \BCD_CONVERT|A9|WideOr1~combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ;
+wire \BCD_CONVERT|A9|WideOr3~0_combout ;
+wire \BCD_CONVERT|A12|WideOr1~0_combout ;
+wire \BCD_CONVERT|A12|WideOr2~0_combout ;
+wire \BCD_CONVERT|A12|WideOr3~0_combout ;
+wire \BCD_CONVERT|A15|WideOr1~0_combout ;
+wire \BCD_CONVERT|A15|WideOr3~0_combout ;
+wire \BCD_CONVERT|A15|WideOr2~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ;
+wire \BCD_CONVERT|A18|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ;
+wire \BCD_CONVERT|A18|WideOr2~0_combout ;
+wire \BCD_CONVERT|A18|WideOr3~0_combout ;
+wire \BCD_CONVERT|A21|WideOr1~0_combout ;
+wire \BCD_CONVERT|A21|WideOr2~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ;
+wire \BCD_CONVERT|A21|WideOr3~0_combout ;
+wire \BCD_CONVERT|A25|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ;
+wire \BCD_CONVERT|A25|WideOr2~0_combout ;
+wire \BCD_CONVERT|A25|WideOr3~0_combout ;
+wire \SEG0|WideOr6~0_combout ;
+wire \SEG0|WideOr5~0_combout ;
+wire \SEG0|WideOr4~0_combout ;
+wire \SEG0|WideOr3~0_combout ;
+wire \SEG0|WideOr2~0_combout ;
+wire \SEG0|WideOr1~0_combout ;
+wire \SEG0|WideOr0~0_combout ;
+wire \BCD_CONVERT|A9|Decoder0~0_combout ;
+wire \BCD_CONVERT|A9|WideOr0~0_combout ;
+wire \BCD_CONVERT|A9|WideOr0~1_combout ;
+wire \BCD_CONVERT|A15|WideOr0~0_combout ;
+wire \BCD_CONVERT|A7|WideOr0~0_combout ;
+wire \BCD_CONVERT|A12|WideOr0~0_combout ;
+wire \BCD_CONVERT|A17|Decoder0~5_combout ;
+wire \BCD_CONVERT|A17|WideOr2~3_combout ;
+wire \BCD_CONVERT|A17|WideOr2~7_combout ;
+wire \BCD_CONVERT|A17|Decoder0~3_combout ;
+wire \BCD_CONVERT|A17|WideOr2~6_combout ;
+wire \BCD_CONVERT|A7|WideOr0~1_combout ;
+wire \BCD_CONVERT|A17|WideOr3~0_combout ;
+wire \BCD_CONVERT|A17|Decoder0~4_combout ;
+wire \BCD_CONVERT|A17|WideOr3~1_combout ;
+wire \BCD_CONVERT|A17|Decoder0~2_combout ;
+wire \BCD_CONVERT|A17|Decoder0~6_combout ;
+wire \BCD_CONVERT|A17|WideOr1~0_combout ;
+wire \BCD_CONVERT|A18|WideOr0~0_combout ;
+wire \BCD_CONVERT|A20|WideOr2~0_combout ;
+wire \BCD_CONVERT|A20|WideOr1~0_combout ;
+wire \BCD_CONVERT|A21|WideOr0~0_combout ;
+wire \BCD_CONVERT|A20|WideOr3~0_combout ;
+wire \BCD_CONVERT|A24|WideOr1~0_combout ;
+wire \BCD_CONVERT|A24|WideOr3~0_combout ;
+wire \BCD_CONVERT|A24|WideOr2~0_combout ;
+wire \BCD_CONVERT|A25|WideOr0~0_combout ;
+wire \SEG1|WideOr6~0_combout ;
+wire \SEG1|WideOr5~0_combout ;
+wire \SEG1|WideOr4~0_combout ;
+wire \SEG1|WideOr3~0_combout ;
+wire \SEG1|WideOr2~0_combout ;
+wire \SEG1|WideOr1~0_combout ;
+wire \SEG1|WideOr0~0_combout ;
+wire \BCD_CONVERT|A24|WideOr0~0_combout ;
+wire \BCD_CONVERT|A14|WideOr0~2_combout ;
+wire \BCD_CONVERT|A17|Decoder0~7_combout ;
+wire \BCD_CONVERT|A17|WideOr0~0_combout ;
+wire \BCD_CONVERT|A17|WideOr0~combout ;
+wire \BCD_CONVERT|A20|WideOr0~0_combout ;
+wire \SEG2|Decoder0~0_combout ;
+wire \SEG2|Decoder0~1_combout ;
+wire \SEG2|WideOr6~combout ;
+wire \SEG2|Decoder0~2_combout ;
+wire \SEG2|Decoder0~3_combout ;
+wire \SEG2|WideOr5~combout ;
+wire \SEG2|Decoder0~4_combout ;
+wire \SEG2|Decoder0~5_combout ;
+wire \SEG2|Decoder0~6_combout ;
+wire \SEG2|WideOr2~0_combout ;
+wire \SEG2|Decoder0~7_combout ;
+wire \SEG2|WideOr2~combout ;
+wire \SEG2|WideOr1~combout ;
+wire \SEG2|Decoder0~8_combout ;
+wire \SEG2|WideOr0~combout ;
+wire \BCD_CONVERT|A23|WideOr0~5_combout ;
+wire \BCD_CONVERT|A23|WideOr0~17_combout ;
+wire \CLOCK_50~input_o ;
+wire \SPI_DAC|clk_1MHz~0_combout ;
+wire \CLOCK_50~inputclkctrl_outclk ;
+wire \SPI_ADC|Add0~0_combout ;
+wire \SPI_ADC|Add0~7 ;
+wire \SPI_ADC|Add0~8_combout ;
+wire \SPI_ADC|ctr~0_combout ;
+wire \SPI_ADC|Add0~1 ;
+wire \SPI_ADC|Add0~2_combout ;
+wire \SPI_ADC|ctr~1_combout ;
+wire \SPI_ADC|Add0~3 ;
+wire \SPI_ADC|Add0~4_combout ;
+wire \SPI_ADC|ctr~2_combout ;
+wire \SPI_ADC|Add0~5 ;
+wire \SPI_ADC|Add0~6_combout ;
+wire \SPI_DAC|Equal0~0_combout ;
+wire \SPI_DAC|Equal0~1_combout ;
+wire \SPI_DAC|clk_1MHz~q ;
+wire \SPI_DAC|clk_1MHz~clkctrl_outclk ;
+wire \PWM_DC|count[0]~27_combout ;
+wire \GEN_10K|Add0~23 ;
+wire \GEN_10K|Add0~24_combout ;
+wire \GEN_10K|ctr~6_combout ;
+wire \GEN_10K|Add0~25 ;
+wire \GEN_10K|Add0~26_combout ;
+wire \GEN_10K|ctr~7_combout ;
+wire \GEN_10K|Add0~27 ;
+wire \GEN_10K|Add0~28_combout ;
+wire \GEN_10K|ctr~8_combout ;
+wire \GEN_10K|Add0~29 ;
+wire \GEN_10K|Add0~30_combout ;
+wire \GEN_10K|ctr~9_combout ;
+wire \GEN_10K|Add0~31 ;
+wire \GEN_10K|Add0~32_combout ;
+wire \GEN_10K|ctr~10_combout ;
+wire \GEN_10K|Add0~33 ;
+wire \GEN_10K|Add0~34_combout ;
+wire \GEN_10K|ctr~11_combout ;
+wire \GEN_10K|Add0~35 ;
+wire \GEN_10K|Add0~36_combout ;
+wire \GEN_10K|ctr~12_combout ;
+wire \GEN_10K|Add0~37 ;
+wire \GEN_10K|Add0~38_combout ;
+wire \GEN_10K|ctr~13_combout ;
+wire \GEN_10K|Add0~39 ;
+wire \GEN_10K|Add0~40_combout ;
+wire \GEN_10K|ctr~14_combout ;
+wire \GEN_10K|Equal0~5_combout ;
+wire \GEN_10K|Add0~1_cout ;
+wire \GEN_10K|Add0~2_combout ;
+wire \GEN_10K|Add0~3 ;
+wire \GEN_10K|Add0~4_combout ;
+wire \GEN_10K|ctr~0_combout ;
+wire \GEN_10K|Add0~5 ;
+wire \GEN_10K|Add0~6_combout ;
+wire \GEN_10K|ctr~1_combout ;
+wire \GEN_10K|Add0~7 ;
+wire \GEN_10K|Add0~8_combout ;
+wire \GEN_10K|ctr~2_combout ;
+wire \GEN_10K|Add0~9 ;
+wire \GEN_10K|Add0~10_combout ;
+wire \GEN_10K|ctr~3_combout ;
+wire \GEN_10K|Add0~11 ;
+wire \GEN_10K|Add0~12_combout ;
+wire \GEN_10K|Add0~13 ;
+wire \GEN_10K|Add0~14_combout ;
+wire \GEN_10K|Add0~15 ;
+wire \GEN_10K|Add0~16_combout ;
+wire \GEN_10K|Add0~17 ;
+wire \GEN_10K|Add0~18_combout ;
+wire \GEN_10K|ctr~4_combout ;
+wire \GEN_10K|Add0~19 ;
+wire \GEN_10K|Add0~20_combout ;
+wire \GEN_10K|ctr~5_combout ;
+wire \GEN_10K|Add0~21 ;
+wire \GEN_10K|Add0~22_combout ;
+wire \GEN_10K|Equal0~2_combout ;
+wire \GEN_10K|Equal0~0_combout ;
+wire \GEN_10K|Equal0~1_combout ;
+wire \GEN_10K|Equal0~3_combout ;
+wire \GEN_10K|Equal0~4_combout ;
+wire \GEN_10K|clkout~0_combout ;
+wire \GEN_10K|clkout~q ;
+wire \PULSE|state.IDLE~feeder_combout ;
+wire \PULSE|state.IDLE~q ;
+wire \PULSE|pulse~1_combout ;
+wire \PULSE|pulse~q ;
+wire \SPI_DAC|Selector2~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_DAC|Selector0~0_combout ;
+wire \SPI_DAC|sr_state.IDLE~q ;
+wire \SPI_DAC|Selector1~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_DAC|dac_start~0_combout ;
+wire \SPI_DAC|dac_start~1_combout ;
+wire \SPI_DAC|dac_start~q ;
+wire \SPI_DAC|state[0]~5_combout ;
+wire \SPI_DAC|state[3]~12 ;
+wire \SPI_DAC|state[4]~13_combout ;
+wire \SPI_DAC|Selector8~0_combout ;
+wire \SPI_DAC|state[0]~6 ;
+wire \SPI_DAC|state[1]~7_combout ;
+wire \SPI_DAC|state[1]~8 ;
+wire \SPI_DAC|state[2]~9_combout ;
+wire \SPI_DAC|state[2]~10 ;
+wire \SPI_DAC|state[3]~11_combout ;
+wire \SPI_DAC|Equal1~0_combout ;
+wire \SPI_DAC|Selector9~0_combout ;
+wire \SPI_DAC|dac_cs~q ;
+wire \SPI_ADC|clk_1MHz~0_combout ;
+wire \SPI_ADC|clk_1MHz~q ;
+wire \SPI_ADC|clk_1MHz~clkctrl_outclk ;
+wire \ADC_SDO~input_o ;
+wire \SPI_ADC|Selector2~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_ADC|Selector0~0_combout ;
+wire \SPI_ADC|sr_state.IDLE~q ;
+wire \SPI_ADC|Selector1~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_ADC|adc_start~0_combout ;
+wire \SPI_ADC|adc_start~1_combout ;
+wire \SPI_ADC|adc_start~q ;
+wire \SPI_ADC|Add1~5 ;
+wire \SPI_ADC|Add1~6_combout ;
+wire \SPI_ADC|Add1~7 ;
+wire \SPI_ADC|Add1~8_combout ;
+wire \SPI_ADC|state~1_combout ;
+wire \SPI_ADC|Selector4~2_combout ;
+wire \SPI_ADC|Add1~0_combout ;
+wire \SPI_ADC|Selector5~0_combout ;
+wire \SPI_ADC|Add1~1 ;
+wire \SPI_ADC|Add1~2_combout ;
+wire \SPI_ADC|Add1~3 ;
+wire \SPI_ADC|Add1~4_combout ;
+wire \SPI_ADC|state~0_combout ;
+wire \SPI_ADC|Selector4~3_combout ;
+wire \SPI_ADC|adc_cs~q ;
+wire \SPI_ADC|WideOr0~0_combout ;
+wire \SPI_ADC|WideOr0~1_combout ;
+wire \SPI_ADC|shift_ena~q ;
+wire \SPI_ADC|always3~0_combout ;
+wire \SPI_ADC|shift_reg[1]~feeder_combout ;
+wire \SPI_ADC|shift_reg[3]~feeder_combout ;
+wire \SPI_ADC|shift_reg[5]~feeder_combout ;
+wire \SPI_ADC|shift_reg[6]~feeder_combout ;
+wire \SPI_ADC|Decoder0~0_combout ;
+wire \SPI_ADC|Decoder0~1_combout ;
+wire \SPI_ADC|adc_done~q ;
+wire \DUMMY|PULSE2|state.IDLE~0_combout ;
+wire \DUMMY|PULSE2|state.IDLE~q ;
+wire \DUMMY|PULSE2|pulse~1_combout ;
+wire \DUMMY|PULSE2|pulse~q ;
+wire \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ;
+wire \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ;
+wire \SPI_ADC|shift_reg[9]~feeder_combout ;
+wire \SPI_ADC|adc_cs~clkctrl_outclk ;
+wire \DUMMY|ctr[0]~36_combout ;
+wire \DUMMY|ctr[1]~12_combout ;
+wire \DUMMY|ctr[1]~13 ;
+wire \DUMMY|ctr[2]~14_combout ;
+wire \DUMMY|ctr[2]~15 ;
+wire \DUMMY|ctr[3]~16_combout ;
+wire \DUMMY|ctr[3]~17 ;
+wire \DUMMY|ctr[4]~18_combout ;
+wire \DUMMY|wraddr[4]~0_combout ;
+wire \DUMMY|ctr[4]~19 ;
+wire \DUMMY|ctr[5]~20_combout ;
+wire \DUMMY|wraddr[4]~1 ;
+wire \DUMMY|wraddr[5]~2_combout ;
+wire \DUMMY|ctr[5]~21 ;
+wire \DUMMY|ctr[6]~22_combout ;
+wire \DUMMY|wraddr[5]~3 ;
+wire \DUMMY|wraddr[6]~4_combout ;
+wire \DUMMY|ctr[6]~23 ;
+wire \DUMMY|ctr[7]~24_combout ;
+wire \DUMMY|wraddr[6]~5 ;
+wire \DUMMY|wraddr[7]~6_combout ;
+wire \DUMMY|ctr[7]~25 ;
+wire \DUMMY|ctr[8]~26_combout ;
+wire \DUMMY|wraddr[7]~7 ;
+wire \DUMMY|wraddr[8]~8_combout ;
+wire \DUMMY|ctr[8]~27 ;
+wire \DUMMY|ctr[9]~28_combout ;
+wire \DUMMY|wraddr[8]~9 ;
+wire \DUMMY|wraddr[9]~10_combout ;
+wire \DUMMY|ctr[9]~29 ;
+wire \DUMMY|ctr[10]~30_combout ;
+wire \DUMMY|wraddr[9]~11 ;
+wire \DUMMY|wraddr[10]~12_combout ;
+wire \DUMMY|ctr[10]~31 ;
+wire \DUMMY|ctr[11]~32_combout ;
+wire \DUMMY|wraddr[10]~13 ;
+wire \DUMMY|wraddr[11]~14_combout ;
+wire \DUMMY|ctr[11]~33 ;
+wire \DUMMY|ctr[12]~34_combout ;
+wire \DUMMY|wraddr[11]~15 ;
+wire \DUMMY|wraddr[12]~16_combout ;
+wire \SPI_ADC|data_from_adc[5]~feeder_combout ;
+wire \DUMMY|Add0~12_combout ;
+wire \SPI_ADC|data_from_adc[4]~feeder_combout ;
+wire \DUMMY|Add0~10_combout ;
+wire \DUMMY|Add0~8_combout ;
+wire \SPI_ADC|data_from_adc[2]~feeder_combout ;
+wire \DUMMY|Add0~6_combout ;
+wire \DUMMY|Add0~4_combout ;
+wire \DUMMY|Add0~2_combout ;
+wire \SPI_ADC|data_from_adc[0]~feeder_combout ;
+wire \DUMMY|Add0~1 ;
+wire \DUMMY|Add0~3 ;
+wire \DUMMY|Add0~5 ;
+wire \DUMMY|Add0~7 ;
+wire \DUMMY|Add0~9 ;
+wire \DUMMY|Add0~11 ;
+wire \DUMMY|Add0~13 ;
+wire \DUMMY|Add0~15 ;
+wire \DUMMY|Add0~17 ;
+wire \DUMMY|Add0~18_combout ;
+wire \DUMMY|Add3~1 ;
+wire \DUMMY|Add3~3 ;
+wire \DUMMY|Add3~4_combout ;
+wire \DUMMY|Add0~16_combout ;
+wire \DUMMY|Add3~2_combout ;
+wire \DUMMY|Add0~14_combout ;
+wire \DUMMY|Add3~0_combout ;
+wire \DUMMY|Add0~0_combout ;
+wire \SPI_DAC|shift_reg~13_combout ;
+wire \SPI_DAC|shift_reg~12_combout ;
+wire \SPI_DAC|shift_reg~11_combout ;
+wire \SPI_DAC|shift_reg~10_combout ;
+wire \SPI_DAC|shift_reg~9_combout ;
+wire \SPI_DAC|shift_reg~8_combout ;
+wire \SPI_DAC|shift_reg~7_combout ;
+wire \SPI_DAC|shift_reg~6_combout ;
+wire \SPI_DAC|shift_reg~5_combout ;
+wire \DUMMY|data_out[9]~0_combout ;
+wire \SPI_DAC|shift_reg~4_combout ;
+wire \SPI_DAC|shift_reg~3_combout ;
+wire \SPI_DAC|shift_reg~2_combout ;
+wire \SPI_DAC|shift_reg~1_combout ;
+wire \SPI_DAC|shift_reg~0_combout ;
+wire \SCK~0_combout ;
+wire \SPI_DAC|Equal2~0_combout ;
+wire \SPI_DAC|dac_ld~q ;
+wire \SW[9]~input_o ;
+wire \SPI_ADC|Selector6~0_combout ;
+wire \SPI_ADC|Selector6~1_combout ;
+wire \SPI_ADC|adc_din~q ;
+wire \PWM_DC|count[1]~9_combout ;
+wire \PWM_DC|count[1]~10 ;
+wire \PWM_DC|count[2]~11_combout ;
+wire \PWM_DC|count[2]~12 ;
+wire \PWM_DC|count[3]~13_combout ;
+wire \PWM_DC|count[3]~14 ;
+wire \PWM_DC|count[4]~15_combout ;
+wire \PWM_DC|count[4]~16 ;
+wire \PWM_DC|count[5]~17_combout ;
+wire \PWM_DC|count[5]~18 ;
+wire \PWM_DC|count[6]~19_combout ;
+wire \PWM_DC|count[6]~20 ;
+wire \PWM_DC|count[7]~21_combout ;
+wire \PWM_DC|count[7]~22 ;
+wire \PWM_DC|count[8]~23_combout ;
+wire \PWM_DC|count[8]~24 ;
+wire \PWM_DC|count[9]~25_combout ;
+wire \PWM_DC|LessThan0~1_cout ;
+wire \PWM_DC|LessThan0~3_cout ;
+wire \PWM_DC|LessThan0~5_cout ;
+wire \PWM_DC|LessThan0~7_cout ;
+wire \PWM_DC|LessThan0~9_cout ;
+wire \PWM_DC|LessThan0~11_cout ;
+wire \PWM_DC|LessThan0~13_cout ;
+wire \PWM_DC|LessThan0~15_cout ;
+wire \PWM_DC|LessThan0~17_cout ;
+wire \PWM_DC|LessThan0~18_combout ;
+wire \PWM_DC|pwm_out~0_combout ;
+wire \PWM_DC|pwm_out~q ;
+wire [20:0] \GEN_10K|ctr ;
+wire [4:0] \SPI_DAC|state ;
+wire [15:0] \SPI_DAC|shift_reg ;
+wire [9:0] \PWM_DC|d ;
+wire [9:0] \PWM_DC|count ;
+wire [4:0] \SPI_ADC|state ;
+wire [9:0] \SPI_ADC|shift_reg ;
+wire [9:0] \SPI_ADC|data_from_adc ;
+wire [4:0] \SPI_ADC|ctr ;
+wire [9:0] \DUMMY|data_out ;
+wire [12:0] \DUMMY|ctr ;
+wire [8:0] \DUMMY|DELAY|altsyncram_component|auto_generated|q_b ;
+
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
+
+// Location: IOOBUF_X21_Y29_N23
+cycloneiii_io_obuf \HEX0_D[0]~output (
+	.i(\SEG0|WideOr6~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[0]~output .bus_hold = "false";
+defparam \HEX0_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N30
+cycloneiii_io_obuf \HEX0_D[1]~output (
+	.i(\SEG0|WideOr5~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[1]~output .bus_hold = "false";
+defparam \HEX0_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N2
+cycloneiii_io_obuf \HEX0_D[2]~output (
+	.i(\SEG0|WideOr4~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[2]~output .bus_hold = "false";
+defparam \HEX0_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N30
+cycloneiii_io_obuf \HEX0_D[3]~output (
+	.i(\SEG0|WideOr3~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[3]~output .bus_hold = "false";
+defparam \HEX0_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N9
+cycloneiii_io_obuf \HEX0_D[4]~output (
+	.i(\SEG0|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[4]~output .bus_hold = "false";
+defparam \HEX0_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N23
+cycloneiii_io_obuf \HEX0_D[5]~output (
+	.i(\SEG0|WideOr1~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[5]~output .bus_hold = "false";
+defparam \HEX0_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N16
+cycloneiii_io_obuf \HEX0_D[6]~output (
+	.i(!\SEG0|WideOr0~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[6]~output .bus_hold = "false";
+defparam \HEX0_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N2
+cycloneiii_io_obuf \HEX1_D[0]~output (
+	.i(!\SEG1|WideOr6~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[0]~output .bus_hold = "false";
+defparam \HEX1_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N9
+cycloneiii_io_obuf \HEX1_D[1]~output (
+	.i(\SEG1|WideOr5~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[1]~output .bus_hold = "false";
+defparam \HEX1_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N2
+cycloneiii_io_obuf \HEX1_D[2]~output (
+	.i(\SEG1|WideOr4~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[2]~output .bus_hold = "false";
+defparam \HEX1_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N23
+cycloneiii_io_obuf \HEX1_D[3]~output (
+	.i(!\SEG1|WideOr3~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[3]~output .bus_hold = "false";
+defparam \HEX1_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N30
+cycloneiii_io_obuf \HEX1_D[4]~output (
+	.i(!\SEG1|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[4]~output .bus_hold = "false";
+defparam \HEX1_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N16
+cycloneiii_io_obuf \HEX1_D[5]~output (
+	.i(!\SEG1|WideOr1~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[5]~output .bus_hold = "false";
+defparam \HEX1_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N23
+cycloneiii_io_obuf \HEX1_D[6]~output (
+	.i(!\SEG1|WideOr0~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[6]~output .bus_hold = "false";
+defparam \HEX1_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N30
+cycloneiii_io_obuf \HEX2_D[0]~output (
+	.i(\SEG2|WideOr6~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[0]~output .bus_hold = "false";
+defparam \HEX2_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N30
+cycloneiii_io_obuf \HEX2_D[1]~output (
+	.i(\SEG2|WideOr5~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[1]~output .bus_hold = "false";
+defparam \HEX2_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N2
+cycloneiii_io_obuf \HEX2_D[2]~output (
+	.i(\SEG2|Decoder0~4_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[2]~output .bus_hold = "false";
+defparam \HEX2_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N2
+cycloneiii_io_obuf \HEX2_D[3]~output (
+	.i(!\SEG2|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[3]~output .bus_hold = "false";
+defparam \HEX2_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N16
+cycloneiii_io_obuf \HEX2_D[4]~output (
+	.i(\SEG2|WideOr2~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[4]~output .bus_hold = "false";
+defparam \HEX2_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N23
+cycloneiii_io_obuf \HEX2_D[5]~output (
+	.i(\SEG2|WideOr1~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[5]~output .bus_hold = "false";
+defparam \HEX2_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N2
+cycloneiii_io_obuf \HEX2_D[6]~output (
+	.i(\SEG2|WideOr0~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[6]~output .bus_hold = "false";
+defparam \HEX2_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N23
+cycloneiii_io_obuf \HEX3_D[0]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[0]~output .bus_hold = "false";
+defparam \HEX3_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y29_N16
+cycloneiii_io_obuf \HEX3_D[1]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[1]~output .bus_hold = "false";
+defparam \HEX3_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N9
+cycloneiii_io_obuf \HEX3_D[2]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[2]~output .bus_hold = "false";
+defparam \HEX3_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N2
+cycloneiii_io_obuf \HEX3_D[3]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[3]~output .bus_hold = "false";
+defparam \HEX3_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N23
+cycloneiii_io_obuf \HEX3_D[4]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[4]~output .bus_hold = "false";
+defparam \HEX3_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N30
+cycloneiii_io_obuf \HEX3_D[5]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[5]~output .bus_hold = "false";
+defparam \HEX3_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y29_N30
+cycloneiii_io_obuf \HEX3_D[6]~output (
+	.i(vcc),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[6]~output .bus_hold = "false";
+defparam \HEX3_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X3_Y0_N30
+cycloneiii_io_obuf \DAC_SDI~output (
+	.i(\SPI_DAC|shift_reg [15]),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_SDI~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SDI~output .bus_hold = "false";
+defparam \DAC_SDI~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X19_Y0_N16
+cycloneiii_io_obuf \SCK~output (
+	.i(\SCK~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\SCK~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \SCK~output .bus_hold = "false";
+defparam \SCK~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y0_N2
+cycloneiii_io_obuf \DAC_CS~output (
+	.i(!\SPI_DAC|dac_cs~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_CS~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_CS~output .bus_hold = "false";
+defparam \DAC_CS~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y0_N30
+cycloneiii_io_obuf \DAC_LD~output (
+	.i(\SPI_DAC|dac_ld~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_LD~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_LD~output .bus_hold = "false";
+defparam \DAC_LD~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X11_Y0_N30
+cycloneiii_io_obuf \ADC_SDI~output (
+	.i(\SPI_ADC|adc_din~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\ADC_SDI~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SDI~output .bus_hold = "false";
+defparam \ADC_SDI~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X7_Y0_N23
+cycloneiii_io_obuf \ADC_CS~output (
+	.i(!\SPI_ADC|adc_cs~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\ADC_CS~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \ADC_CS~output .bus_hold = "false";
+defparam \ADC_CS~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N9
+cycloneiii_io_obuf \LEDG[0]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[0]~output .bus_hold = "false";
+defparam \LEDG[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N2
+cycloneiii_io_obuf \LEDG[1]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[1]~output .bus_hold = "false";
+defparam \LEDG[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N23
+cycloneiii_io_obuf \LEDG[2]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[2]~output .bus_hold = "false";
+defparam \LEDG[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N16
+cycloneiii_io_obuf \LEDG[3]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[3]~output .bus_hold = "false";
+defparam \LEDG[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y24_N23
+cycloneiii_io_obuf \LEDG[4]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[4]~output .bus_hold = "false";
+defparam \LEDG[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y24_N16
+cycloneiii_io_obuf \LEDG[5]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[5]~output .bus_hold = "false";
+defparam \LEDG[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N23
+cycloneiii_io_obuf \LEDG[6]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[6]~output .bus_hold = "false";
+defparam \LEDG[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N16
+cycloneiii_io_obuf \LEDG[7]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[7]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[7]~output .bus_hold = "false";
+defparam \LEDG[7]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y27_N9
+cycloneiii_io_obuf \LEDG[8]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[8]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[8]~output .bus_hold = "false";
+defparam \LEDG[8]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y27_N16
+cycloneiii_io_obuf \LEDG[9]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[9]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[9]~output .bus_hold = "false";
+defparam \LEDG[9]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y0_N23
+cycloneiii_io_obuf \PWM_OUT~output (
+	.i(\PWM_DC|pwm_out~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\PWM_OUT~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \PWM_OUT~output .bus_hold = "false";
+defparam \PWM_OUT~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y26_N1
+cycloneiii_io_ibuf \SW[8]~input (
+	.i(SW[8]),
+	.ibar(gnd),
+	.o(\SW[8]~input_o ));
+// synopsys translate_off
+defparam \SW[8]~input .bus_hold = "false";
+defparam \SW[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y26_N8
+cycloneiii_io_ibuf \SW[7]~input (
+	.i(SW[7]),
+	.ibar(gnd),
+	.o(\SW[7]~input_o ));
+// synopsys translate_off
+defparam \SW[7]~input .bus_hold = "false";
+defparam \SW[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N15
+cycloneiii_io_ibuf \SW[6]~input (
+	.i(SW[6]),
+	.ibar(gnd),
+	.o(\SW[6]~input_o ));
+// synopsys translate_off
+defparam \SW[6]~input .bus_hold = "false";
+defparam \SW[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y22_N15
+cycloneiii_io_ibuf \SW[5]~input (
+	.i(SW[5]),
+	.ibar(gnd),
+	.o(\SW[5]~input_o ));
+// synopsys translate_off
+defparam \SW[5]~input .bus_hold = "false";
+defparam \SW[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y27_N22
+cycloneiii_io_ibuf \SW[4]~input (
+	.i(SW[4]),
+	.ibar(gnd),
+	.o(\SW[4]~input_o ));
+// synopsys translate_off
+defparam \SW[4]~input .bus_hold = "false";
+defparam \SW[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  = (\SW[7]~input_o  & (\SW[5]~input_o  $ (((\SW[6]~input_o  & !\SW[4]~input_o ))))) # (!\SW[7]~input_o  & ((\SW[5]~input_o  & ((\SW[6]~input_o ) # (!\SW[4]~input_o ))) # (!\SW[5]~input_o  & 
+// ((\SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 .lut_mask = 16'hE578;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y23_N8
+cycloneiii_io_ibuf \SW[3]~input (
+	.i(SW[3]),
+	.ibar(gnd),
+	.o(\SW[3]~input_o ));
+// synopsys translate_off
+defparam \SW[3]~input .bus_hold = "false";
+defparam \SW[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N22
+cycloneiii_io_ibuf \SW[2]~input (
+	.i(SW[2]),
+	.ibar(gnd),
+	.o(\SW[2]~input_o ));
+// synopsys translate_off
+defparam \SW[2]~input .bus_hold = "false";
+defparam \SW[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y24_N1
+cycloneiii_io_ibuf \SW[0]~input (
+	.i(SW[0]),
+	.ibar(gnd),
+	.o(\SW[0]~input_o ));
+// synopsys translate_off
+defparam \SW[0]~input .bus_hold = "false";
+defparam \SW[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y27_N1
+cycloneiii_io_ibuf \SW[1]~input (
+	.i(SW[1]),
+	.ibar(gnd),
+	.o(\SW[1]~input_o ));
+// synopsys translate_off
+defparam \SW[1]~input .bus_hold = "false";
+defparam \SW[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N28
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  = (\SW[3]~input_o  & ((\SW[2]~input_o ) # ((\SW[0]~input_o  & \SW[1]~input_o ))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 .lut_mask = 16'hA888;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N2
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  = (\SW[3]~input_o  & (!\SW[2]~input_o  & ((!\SW[1]~input_o ) # (!\SW[0]~input_o )))) # (!\SW[3]~input_o  & (\SW[2]~input_o  & ((\SW[1]~input_o ))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 .lut_mask = 16'h4622;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  = (\SW[7]~input_o  & ((\SW[6]~input_o  & ((\SW[4]~input_o ))) # (!\SW[6]~input_o  & ((\SW[5]~input_o ) # (!\SW[4]~input_o ))))) # (!\SW[7]~input_o  & (\SW[4]~input_o  $ (((\SW[6]~input_o  & 
+// \SW[5]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 .lut_mask = 16'hBD62;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  = (\SW[2]~input_o  & ((\SW[3]~input_o  & ((\SW[0]~input_o ) # (\SW[1]~input_o ))) # (!\SW[3]~input_o  & ((!\SW[1]~input_o ))))) # (!\SW[2]~input_o  & (\SW[3]~input_o  $ (((\SW[0]~input_o  & 
+// \SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 .lut_mask = 16'h9AE6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  = (\SW[6]~input_o  & ((\SW[7]~input_o  & ((\SW[5]~input_o ) # (\SW[4]~input_o ))) # (!\SW[7]~input_o  & (!\SW[5]~input_o )))) # (!\SW[6]~input_o  & (\SW[7]~input_o  $ (((\SW[5]~input_o  & 
+// \SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 .lut_mask = 16'h9EA6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  = (\SW[5]~input_o  & ((\SW[6]~input_o  & ((\SW[7]~input_o ) # (\SW[4]~input_o ))) # (!\SW[6]~input_o  & ((!\SW[4]~input_o ))))) # (!\SW[5]~input_o  & (\SW[6]~input_o  $ (((\SW[7]~input_o  & 
+// \SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 .lut_mask = 16'hC6BC;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  = (\SW[0]~input_o  & (\SW[2]~input_o  $ (((\SW[3]~input_o  & !\SW[1]~input_o ))))) # (!\SW[0]~input_o  & ((\SW[2]~input_o  & ((\SW[3]~input_o ) # (!\SW[1]~input_o ))) # (!\SW[2]~input_o  & 
+// ((\SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 .lut_mask = 16'hCB6C;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N0
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  = (\SW[3]~input_o  & (\SW[1]~input_o  $ (((\SW[2]~input_o  & !\SW[0]~input_o ))))) # (!\SW[3]~input_o  & ((\SW[0]~input_o  & ((\SW[2]~input_o ) # (!\SW[1]~input_o ))) # (!\SW[0]~input_o  & 
+// ((\SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .lut_mask = 16'hE758;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N26
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  = (\SW[3]~input_o  & ((\SW[2]~input_o  & (\SW[0]~input_o )) # (!\SW[2]~input_o  & ((\SW[1]~input_o ) # (!\SW[0]~input_o ))))) # (!\SW[3]~input_o  & (\SW[0]~input_o  $ (((\SW[2]~input_o  & 
+// \SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 .lut_mask = 16'hB6D2;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout  = \SW[7]~input_o  $ (((\SW[6]~input_o  & (!\SW[5]~input_o )) # (!\SW[6]~input_o  & (\SW[5]~input_o  & \SW[4]~input_o ))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 .lut_mask = 16'h96A6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  = \SW[6]~input_o  $ (((\SW[5]~input_o  & !\SW[4]~input_o )))
+
+	.dataa(gnd),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 .lut_mask = 16'hCC3C;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  = \SW[5]~input_o  $ (\SW[4]~input_o )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 .lut_mask = 16'h0FF0;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & \SW[4]~input_o ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.datab(\SW[4]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 .lut_mask = 16'h0088;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 .lut_mask = 16'h0017;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ))) # (!\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  & (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 .lut_mask = 16'h008E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout )) # (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 .lut_mask = 16'h0017;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ))) # (!\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N14
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ))) # (!\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  = (\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )) # (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ))) # (!\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  & (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout  & \SW[8]~input_o ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ),
+	.datab(\SW[8]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .lut_mask = 16'h0088;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  $ (GND))) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'hA50A;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h3C3F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout  = ((\SW[8]~input_o  $ (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9  = CARRY((\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) # (!\SW[8]~input_o  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N14
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  = (\SW[7]~input_o  & (!\SW[6]~input_o  & ((!\SW[4]~input_o ) # (!\SW[5]~input_o )))) # (!\SW[7]~input_o  & (\SW[6]~input_o  & (\SW[5]~input_o )))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 .lut_mask = 16'h4262;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  $ (GND))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 .lut_mask = 16'hA50A;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N26
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ) # (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 .lut_mask = 16'h3C3F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N28
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  $ (GND))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 .lut_mask = 16'hC30C;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  $ (GND))) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hC30C;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 .lut_mask = 16'h5A5F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  = ((\SW[8]~input_o  $ (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17  = CARRY((\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ))) # (!\SW[8]~input_o  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 )))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout  = (\SW[7]~input_o  & ((\SW[6]~input_o ) # ((\SW[5]~input_o  & \SW[4]~input_o ))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 .lut_mask = 16'hA888;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N30
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  = \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25  $ (\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 .lut_mask = 16'h0FF0;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  = !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 .lut_mask = 16'h0F0F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr2~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr2~0 .lut_mask = 16'h6426;
+defparam \BCD_CONVERT|A9|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr1 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr1~combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  $ (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr1 .lut_mask = 16'h0940;
+defparam \BCD_CONVERT|A9|WideOr1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  $ 
+// (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr3~0 .lut_mask = 16'h42B4;
+defparam \BCD_CONVERT|A9|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr1~0_combout  = (\BCD_CONVERT|A9|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & !\BCD_CONVERT|A9|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A9|WideOr2~0_combout  & (\BCD_CONVERT|A9|WideOr1~combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (\BCD_CONVERT|A9|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr1~0 .lut_mask = 16'h444A;
+defparam \BCD_CONVERT|A12|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr2~0_combout  = (\BCD_CONVERT|A9|WideOr1~combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & (!\BCD_CONVERT|A9|WideOr2~0_combout  & \BCD_CONVERT|A9|WideOr3~0_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & ((!\BCD_CONVERT|A9|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A9|WideOr1~combout  & (\BCD_CONVERT|A9|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (!\BCD_CONVERT|A9|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr2~0 .lut_mask = 16'h710C;
+defparam \BCD_CONVERT|A12|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr3~0_combout  = (\BCD_CONVERT|A9|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & (\BCD_CONVERT|A9|WideOr1~combout  $ (\BCD_CONVERT|A9|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A9|WideOr2~0_combout  & (\BCD_CONVERT|A9|WideOr1~combout  $ ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr3~0 .lut_mask = 16'h161C;
+defparam \BCD_CONVERT|A12|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr1~0_combout  = (\BCD_CONVERT|A12|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & ((!\BCD_CONVERT|A12|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A12|WideOr2~0_combout  & (\BCD_CONVERT|A12|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ) # (\BCD_CONVERT|A12|WideOr3~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr1~0 .lut_mask = 16'h0C58;
+defparam \BCD_CONVERT|A15|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N30
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (!\BCD_CONVERT|A12|WideOr1~0_combout  & (!\BCD_CONVERT|A12|WideOr2~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (\BCD_CONVERT|A12|WideOr1~0_combout  $ (((\BCD_CONVERT|A12|WideOr2~0_combout  & \BCD_CONVERT|A12|WideOr3~0_combout )))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr3~0 .lut_mask = 16'h1646;
+defparam \BCD_CONVERT|A15|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr2~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (\BCD_CONVERT|A12|WideOr3~0_combout  & ((!\BCD_CONVERT|A12|WideOr2~0_combout ) # (!\BCD_CONVERT|A12|WideOr1~0_combout 
+// )))) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & ((\BCD_CONVERT|A12|WideOr1~0_combout  & ((!\BCD_CONVERT|A12|WideOr3~0_combout ))) # (!\BCD_CONVERT|A12|WideOr1~0_combout  & 
+// (!\BCD_CONVERT|A12|WideOr2~0_combout  & \BCD_CONVERT|A12|WideOr3~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr2~0 .lut_mask = 16'h2B44;
+defparam \BCD_CONVERT|A15|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr1~0_combout  = (\BCD_CONVERT|A15|WideOr2~0_combout  & (((!\BCD_CONVERT|A15|WideOr3~0_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )))) # 
+// (!\BCD_CONVERT|A15|WideOr2~0_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr1~0 .lut_mask = 16'h0A38;
+defparam \BCD_CONVERT|A18|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr2~0_combout  = (\BCD_CONVERT|A15|WideOr1~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout  & (!\BCD_CONVERT|A15|WideOr2~0_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )) 
+// # (!\BCD_CONVERT|A15|WideOr3~0_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ))))) # (!\BCD_CONVERT|A15|WideOr1~0_combout  & (\BCD_CONVERT|A15|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ) # (!\BCD_CONVERT|A15|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr2~0 .lut_mask = 16'h4C26;
+defparam \BCD_CONVERT|A18|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr3~0_combout  = (\BCD_CONVERT|A15|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  $ (\BCD_CONVERT|A15|WideOr3~0_combout 
+// )))) # (!\BCD_CONVERT|A15|WideOr2~0_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  $ (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr3~0 .lut_mask = 16'h056A;
+defparam \BCD_CONVERT|A18|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr1~0_combout  = (\BCD_CONVERT|A18|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & !\BCD_CONVERT|A18|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A18|WideOr2~0_combout  & (\BCD_CONVERT|A18|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (\BCD_CONVERT|A18|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr1~0 .lut_mask = 16'h0A38;
+defparam \BCD_CONVERT|A21|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr2~0_combout  = (\BCD_CONVERT|A18|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (!\BCD_CONVERT|A18|WideOr2~0_combout  & \BCD_CONVERT|A18|WideOr3~0_combout )) 
+// # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & ((!\BCD_CONVERT|A18|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A18|WideOr1~0_combout  & (\BCD_CONVERT|A18|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (!\BCD_CONVERT|A18|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr2~0 .lut_mask = 16'h4D22;
+defparam \BCD_CONVERT|A21|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (!\BCD_CONVERT|A18|WideOr1~0_combout  & (!\BCD_CONVERT|A18|WideOr2~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (\BCD_CONVERT|A18|WideOr1~0_combout  $ (((\BCD_CONVERT|A18|WideOr2~0_combout  & \BCD_CONVERT|A18|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr3~0 .lut_mask = 16'h1626;
+defparam \BCD_CONVERT|A21|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr1~0_combout  = (\BCD_CONVERT|A21|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & !\BCD_CONVERT|A21|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A21|WideOr2~0_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (\BCD_CONVERT|A21|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr1~0 .lut_mask = 16'h222C;
+defparam \BCD_CONVERT|A25|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr2~0_combout  = (\BCD_CONVERT|A21|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & (!\BCD_CONVERT|A21|WideOr2~0_combout  & \BCD_CONVERT|A21|WideOr3~0_combout )) 
+// # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & ((!\BCD_CONVERT|A21|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A21|WideOr1~0_combout  & (\BCD_CONVERT|A21|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (!\BCD_CONVERT|A21|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr2~0 .lut_mask = 16'h710A;
+defparam \BCD_CONVERT|A25|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr3~0_combout  = (\BCD_CONVERT|A21|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  $ (\BCD_CONVERT|A21|WideOr3~0_combout 
+// )))) # (!\BCD_CONVERT|A21|WideOr2~0_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  $ ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr3~0 .lut_mask = 16'h161A;
+defparam \BCD_CONVERT|A25|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N22
+cycloneiii_lcell_comb \SEG0|WideOr6~0 (
+// Equation(s):
+// \SEG0|WideOr6~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr3~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  $ (\BCD_CONVERT|A25|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr6~0 .lut_mask = 16'h0894;
+defparam \SEG0|WideOr6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N0
+cycloneiii_lcell_comb \SEG0|WideOr5~0 (
+// Equation(s):
+// \SEG0|WideOr5~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr5~0 .lut_mask = 16'hB860;
+defparam \SEG0|WideOr5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N10
+cycloneiii_lcell_comb \SEG0|WideOr4~0 (
+// Equation(s):
+// \SEG0|WideOr4~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout )))) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr4~0 .lut_mask = 16'hA120;
+defparam \SEG0|WideOr4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N28
+cycloneiii_lcell_comb \SEG0|WideOr3~0 (
+// Equation(s):
+// \SEG0|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr2~0_combout  $ (!\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr3~0 .lut_mask = 16'hC21C;
+defparam \SEG0|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N6
+cycloneiii_lcell_comb \SEG0|WideOr2~0 (
+// Equation(s):
+// \SEG0|WideOr2~0_combout  = (\BCD_CONVERT|A25|WideOr3~0_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ))) # (!\BCD_CONVERT|A25|WideOr3~0_combout  & 
+// ((\BCD_CONVERT|A25|WideOr2~0_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout )) # (!\BCD_CONVERT|A25|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout )))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr2~0 .lut_mask = 16'h445C;
+defparam \SEG0|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N16
+cycloneiii_lcell_comb \SEG0|WideOr1~0 (
+// Equation(s):
+// \SEG0|WideOr1~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr1~0_combout  $ (((\BCD_CONVERT|A25|WideOr3~0_combout ) # (!\BCD_CONVERT|A25|WideOr2~0_combout ))))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr1~0 .lut_mask = 16'h4584;
+defparam \SEG0|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N2
+cycloneiii_lcell_comb \SEG0|WideOr0~0 (
+// Equation(s):
+// \SEG0|WideOr0~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr1~0_combout ) # (\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ) # (\BCD_CONVERT|A25|WideOr1~0_combout  $ (\BCD_CONVERT|A25|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr0~0 .lut_mask = 16'hBFDA;
+defparam \SEG0|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A9|Decoder0~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|Decoder0~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  $ (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|Decoder0~0 .lut_mask = 16'hFFF6;
+defparam \BCD_CONVERT|A9|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr0~0_combout  = \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  $ (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr0~0 .lut_mask = 16'h4DB2;
+defparam \BCD_CONVERT|A9|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr0~1 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr0~1_combout  = (\BCD_CONVERT|A9|WideOr0~0_combout ) # (!\BCD_CONVERT|A9|Decoder0~0_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr0~1 .lut_mask = 16'hFF0F;
+defparam \BCD_CONVERT|A9|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr0~0_combout  = \BCD_CONVERT|A12|WideOr1~0_combout  $ (((\BCD_CONVERT|A12|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ) # (\BCD_CONVERT|A12|WideOr3~0_combout 
+// )))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr0~0 .lut_mask = 16'h3C6C;
+defparam \BCD_CONVERT|A15|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A7|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A7|WideOr0~0_combout  = ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A7|WideOr0~0 .lut_mask = 16'h3377;
+defparam \BCD_CONVERT|A7|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr0~0_combout  = \BCD_CONVERT|A9|WideOr1~combout  $ (((\BCD_CONVERT|A9|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (\BCD_CONVERT|A9|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr0~0 .lut_mask = 16'h666C;
+defparam \BCD_CONVERT|A12|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~5 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~5_combout  = (!\BCD_CONVERT|A15|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  & \BCD_CONVERT|A12|WideOr0~0_combout )) # (!\BCD_CONVERT|A9|WideOr0~1_combout  & 
+// (!\BCD_CONVERT|A7|WideOr0~0_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~5 .lut_mask = 16'h2001;
+defparam \BCD_CONVERT|A17|Decoder0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~3 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~3_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ) # 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~3 .lut_mask = 16'h1FF8;
+defparam \BCD_CONVERT|A17|WideOr2~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~7 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~7_combout  = (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// \BCD_CONVERT|A17|WideOr2~3_combout ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(gnd),
+	.datad(\BCD_CONVERT|A17|WideOr2~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~7 .lut_mask = 16'h4400;
+defparam \BCD_CONVERT|A17|WideOr2~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~3 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~3_combout  = (\BCD_CONVERT|A15|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  & \BCD_CONVERT|A12|WideOr0~0_combout )) # (!\BCD_CONVERT|A9|WideOr0~1_combout  & 
+// (!\BCD_CONVERT|A7|WideOr0~0_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~3 .lut_mask = 16'h8004;
+defparam \BCD_CONVERT|A17|Decoder0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~6 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~6_combout  = (\BCD_CONVERT|A17|Decoder0~5_combout ) # ((\BCD_CONVERT|A17|WideOr2~7_combout ) # (\BCD_CONVERT|A17|Decoder0~3_combout ))
+
+	.dataa(gnd),
+	.datab(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr2~7_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~6 .lut_mask = 16'hFFFC;
+defparam \BCD_CONVERT|A17|WideOr2~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A7|WideOr0~1 (
+// Equation(s):
+// \BCD_CONVERT|A7|WideOr0~1_combout  = (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A7|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A7|WideOr0~1 .lut_mask = 16'h0055;
+defparam \BCD_CONVERT|A7|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr3~0_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A7|WideOr0~1_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))) 
+// # (!\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A12|WideOr0~0_combout  & ((\BCD_CONVERT|A7|WideOr0~1_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A7|WideOr0~1_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr3~0 .lut_mask = 16'h4520;
+defparam \BCD_CONVERT|A17|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N0
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~4 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~4_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~4 .lut_mask = 16'h0880;
+defparam \BCD_CONVERT|A17|Decoder0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr3~1 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr3~1_combout  = (\BCD_CONVERT|A17|Decoder0~4_combout ) # ((\BCD_CONVERT|A17|Decoder0~3_combout ) # ((!\BCD_CONVERT|A15|WideOr0~0_combout  & \BCD_CONVERT|A17|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr3~1 .lut_mask = 16'hFFF4;
+defparam \BCD_CONVERT|A17|WideOr3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~2 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~2_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~2 .lut_mask = 16'h01AA;
+defparam \BCD_CONVERT|A17|Decoder0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~6 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~6_combout  = (!\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~6 .lut_mask = 16'h0110;
+defparam \BCD_CONVERT|A17|Decoder0~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N30
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr1~0_combout  = (\BCD_CONVERT|A17|Decoder0~6_combout ) # ((\BCD_CONVERT|A15|WideOr0~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & \BCD_CONVERT|A17|Decoder0~2_combout 
+// )))
+
+	.dataa(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~2_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr1~0 .lut_mask = 16'hFF80;
+defparam \BCD_CONVERT|A17|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr0~0_combout  = \BCD_CONVERT|A15|WideOr1~0_combout  $ (((\BCD_CONVERT|A15|WideOr2~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr0~0 .lut_mask = 16'h5A6A;
+defparam \BCD_CONVERT|A18|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr2~0_combout  = (\BCD_CONVERT|A17|WideOr3~1_combout  & ((\BCD_CONVERT|A17|WideOr2~6_combout  & (!\BCD_CONVERT|A17|WideOr1~0_combout  & \BCD_CONVERT|A18|WideOr0~0_combout )) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & 
+// ((\BCD_CONVERT|A18|WideOr0~0_combout ) # (!\BCD_CONVERT|A17|WideOr1~0_combout ))))) # (!\BCD_CONVERT|A17|WideOr3~1_combout  & (((\BCD_CONVERT|A17|WideOr1~0_combout  & !\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr2~0 .lut_mask = 16'h4C34;
+defparam \BCD_CONVERT|A20|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N0
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr1~0_combout  = (\BCD_CONVERT|A17|WideOr2~6_combout  & (!\BCD_CONVERT|A17|WideOr3~1_combout  & ((!\BCD_CONVERT|A18|WideOr0~0_combout )))) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & (\BCD_CONVERT|A17|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A17|WideOr3~1_combout ) # (\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr1~0 .lut_mask = 16'h5062;
+defparam \BCD_CONVERT|A20|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr0~0_combout  = \BCD_CONVERT|A18|WideOr1~0_combout  $ (((\BCD_CONVERT|A18|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (\BCD_CONVERT|A18|WideOr3~0_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr0~0 .lut_mask = 16'h5A6A;
+defparam \BCD_CONVERT|A21|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr3~0_combout  = (\BCD_CONVERT|A17|WideOr2~6_combout  & ((\BCD_CONVERT|A18|WideOr0~0_combout ) # (\BCD_CONVERT|A17|WideOr3~1_combout  $ (!\BCD_CONVERT|A17|WideOr1~0_combout )))) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & 
+// ((\BCD_CONVERT|A17|WideOr1~0_combout  $ (!\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr3~0 .lut_mask = 16'hFA87;
+defparam \BCD_CONVERT|A20|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr1~0_combout  = (\BCD_CONVERT|A20|WideOr2~0_combout  & (((!\BCD_CONVERT|A21|WideOr0~0_combout  & \BCD_CONVERT|A20|WideOr3~0_combout )))) # (!\BCD_CONVERT|A20|WideOr2~0_combout  & (\BCD_CONVERT|A20|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr1~0 .lut_mask = 16'h4A44;
+defparam \BCD_CONVERT|A24|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr3~0_combout  = (\BCD_CONVERT|A20|WideOr2~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (\BCD_CONVERT|A20|WideOr1~0_combout  $ (\BCD_CONVERT|A20|WideOr3~0_combout )))) # (!\BCD_CONVERT|A20|WideOr2~0_combout  & 
+// (\BCD_CONVERT|A20|WideOr1~0_combout  $ ((!\BCD_CONVERT|A21|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr3~0 .lut_mask = 16'hE3E9;
+defparam \BCD_CONVERT|A24|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr2~0_combout  = (\BCD_CONVERT|A20|WideOr1~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout  & (!\BCD_CONVERT|A20|WideOr2~0_combout  & !\BCD_CONVERT|A20|WideOr3~0_combout )) # (!\BCD_CONVERT|A21|WideOr0~0_combout  & 
+// ((\BCD_CONVERT|A20|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A20|WideOr1~0_combout  & (!\BCD_CONVERT|A20|WideOr3~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr2~0 .lut_mask = 16'h0C71;
+defparam \BCD_CONVERT|A24|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr0~0_combout  = \BCD_CONVERT|A21|WideOr1~0_combout  $ (((\BCD_CONVERT|A21|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (\BCD_CONVERT|A21|WideOr3~0_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr0~0 .lut_mask = 16'h666A;
+defparam \BCD_CONVERT|A25|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N22
+cycloneiii_lcell_comb \SEG1|WideOr6~0 (
+// Equation(s):
+// \SEG1|WideOr6~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & ((\BCD_CONVERT|A24|WideOr3~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr2~0_combout  $ (!\BCD_CONVERT|A25|WideOr0~0_combout )) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr6~0 .lut_mask = 16'h79BF;
+defparam \SEG1|WideOr6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N16
+cycloneiii_lcell_comb \SEG1|WideOr5~0 (
+// Equation(s):
+// \SEG1|WideOr5~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & ((\BCD_CONVERT|A25|WideOr0~0_combout  & (!\BCD_CONVERT|A24|WideOr3~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr2~0_combout ))))) # 
+// (!\BCD_CONVERT|A24|WideOr1~0_combout  & (\BCD_CONVERT|A24|WideOr2~0_combout  & (\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr5~0 .lut_mask = 16'h62B0;
+defparam \SEG1|WideOr5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N2
+cycloneiii_lcell_comb \SEG1|WideOr4~0 (
+// Equation(s):
+// \SEG1|WideOr4~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & (\BCD_CONVERT|A24|WideOr2~0_combout  & ((!\BCD_CONVERT|A25|WideOr0~0_combout ) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// (!\BCD_CONVERT|A24|WideOr3~0_combout  & (!\BCD_CONVERT|A24|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr4~0 .lut_mask = 16'h20A1;
+defparam \SEG1|WideOr4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N4
+cycloneiii_lcell_comb \SEG1|WideOr3~0 (
+// Equation(s):
+// \SEG1|WideOr3~0_combout  = (\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A24|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr3~0_combout ) # (\BCD_CONVERT|A24|WideOr2~0_combout ))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & ((!\BCD_CONVERT|A24|WideOr2~0_combout ) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr3~0 .lut_mask = 16'hC3BD;
+defparam \SEG1|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N6
+cycloneiii_lcell_comb \SEG1|WideOr2~0 (
+// Equation(s):
+// \SEG1|WideOr2~0_combout  = (\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr2~0_combout  & (\BCD_CONVERT|A24|WideOr1~0_combout )) # (!\BCD_CONVERT|A24|WideOr2~0_combout  & ((!\BCD_CONVERT|A25|WideOr0~0_combout ))))) # 
+// (!\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout ) # ((!\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr2~0 .lut_mask = 16'hA2BF;
+defparam \SEG1|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N0
+cycloneiii_lcell_comb \SEG1|WideOr1~0 (
+// Equation(s):
+// \SEG1|WideOr1~0_combout  = (\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (!\BCD_CONVERT|A24|WideOr3~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr1~0_combout ) # ((\BCD_CONVERT|A24|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr1~0 .lut_mask = 16'h6AFE;
+defparam \SEG1|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N10
+cycloneiii_lcell_comb \SEG1|WideOr0~0 (
+// Equation(s):
+// \SEG1|WideOr0~0_combout  = (\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout ) # (\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A24|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr1~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr0~0 .lut_mask = 16'hEB7B;
+defparam \SEG1|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr0~0_combout  = \BCD_CONVERT|A20|WideOr1~0_combout  $ (((\BCD_CONVERT|A20|WideOr2~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr0~0 .lut_mask = 16'h6C66;
+defparam \BCD_CONVERT|A24|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A14|WideOr0~2 (
+// Equation(s):
+// \BCD_CONVERT|A14|WideOr0~2_combout  = (\BCD_CONVERT|A7|WideOr0~0_combout ) # ((!\BCD_CONVERT|A12|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~0_combout ) # (!\BCD_CONVERT|A9|Decoder0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A14|WideOr0~2 .lut_mask = 16'hF0FB;
+defparam \BCD_CONVERT|A14|WideOr0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~7 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~7_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~7 .lut_mask = 16'h0220;
+defparam \BCD_CONVERT|A17|Decoder0~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr0~0_combout  = (\BCD_CONVERT|A17|Decoder0~6_combout ) # ((\BCD_CONVERT|A17|Decoder0~5_combout ) # ((\BCD_CONVERT|A17|Decoder0~4_combout ) # (\BCD_CONVERT|A17|Decoder0~3_combout )))
+
+	.dataa(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.datab(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr0~0 .lut_mask = 16'hFFFE;
+defparam \BCD_CONVERT|A17|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr0~combout  = (\BCD_CONVERT|A17|Decoder0~7_combout ) # (\BCD_CONVERT|A17|WideOr0~0_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.datad(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr0 .lut_mask = 16'hFFF0;
+defparam \BCD_CONVERT|A17|WideOr0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr0~0_combout  = \BCD_CONVERT|A17|WideOr1~0_combout  $ (((\BCD_CONVERT|A17|WideOr2~6_combout  & ((\BCD_CONVERT|A17|WideOr3~1_combout ) # (\BCD_CONVERT|A18|WideOr0~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr0~0 .lut_mask = 16'h5A78;
+defparam \BCD_CONVERT|A20|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N10
+cycloneiii_lcell_comb \SEG2|Decoder0~0 (
+// Equation(s):
+// \SEG2|Decoder0~0_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~0 .lut_mask = 16'h0104;
+defparam \SEG2|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N20
+cycloneiii_lcell_comb \SEG2|Decoder0~1 (
+// Equation(s):
+// \SEG2|Decoder0~1_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~1 .lut_mask = 16'h2080;
+defparam \SEG2|Decoder0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N22
+cycloneiii_lcell_comb \SEG2|WideOr6 (
+// Equation(s):
+// \SEG2|WideOr6~combout  = (\SEG2|Decoder0~0_combout ) # (\SEG2|Decoder0~1_combout )
+
+	.dataa(\SEG2|Decoder0~0_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr6 .lut_mask = 16'hFFAA;
+defparam \SEG2|WideOr6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N24
+cycloneiii_lcell_comb \SEG2|Decoder0~2 (
+// Equation(s):
+// \SEG2|Decoder0~2_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~2 .lut_mask = 16'h0208;
+defparam \SEG2|Decoder0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N18
+cycloneiii_lcell_comb \SEG2|Decoder0~3 (
+// Equation(s):
+// \SEG2|Decoder0~3_combout  = (!\BCD_CONVERT|A17|WideOr0~0_combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  & (!\BCD_CONVERT|A17|Decoder0~7_combout  & \BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~3 .lut_mask = 16'h0400;
+defparam \SEG2|Decoder0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N12
+cycloneiii_lcell_comb \SEG2|WideOr5 (
+// Equation(s):
+// \SEG2|WideOr5~combout  = (\SEG2|Decoder0~2_combout ) # ((!\BCD_CONVERT|A24|WideOr0~0_combout  & \SEG2|Decoder0~3_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~2_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datad(\SEG2|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr5 .lut_mask = 16'hCFCC;
+defparam \SEG2|WideOr5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N6
+cycloneiii_lcell_comb \SEG2|Decoder0~4 (
+// Equation(s):
+// \SEG2|Decoder0~4_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & ((\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )) # (!\BCD_CONVERT|A14|WideOr0~2_combout  & 
+// (!\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~4 .lut_mask = 16'h4001;
+defparam \SEG2|Decoder0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N16
+cycloneiii_lcell_comb \SEG2|Decoder0~5 (
+// Equation(s):
+// \SEG2|Decoder0~5_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~5 .lut_mask = 16'h0800;
+defparam \SEG2|Decoder0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N26
+cycloneiii_lcell_comb \SEG2|Decoder0~6 (
+// Equation(s):
+// \SEG2|Decoder0~6_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~6 .lut_mask = 16'h0020;
+defparam \SEG2|Decoder0~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N4
+cycloneiii_lcell_comb \SEG2|WideOr2~0 (
+// Equation(s):
+// \SEG2|WideOr2~0_combout  = (!\SEG2|Decoder0~0_combout  & (!\SEG2|Decoder0~5_combout  & (!\SEG2|Decoder0~6_combout  & !\SEG2|Decoder0~1_combout )))
+
+	.dataa(\SEG2|Decoder0~0_combout ),
+	.datab(\SEG2|Decoder0~5_combout ),
+	.datac(\SEG2|Decoder0~6_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr2~0 .lut_mask = 16'h0001;
+defparam \SEG2|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N30
+cycloneiii_lcell_comb \SEG2|Decoder0~7 (
+// Equation(s):
+// \SEG2|Decoder0~7_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & ((\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )) # (!\BCD_CONVERT|A14|WideOr0~2_combout  & 
+// (!\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~7 .lut_mask = 16'h8002;
+defparam \SEG2|Decoder0~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N0
+cycloneiii_lcell_comb \SEG2|WideOr2 (
+// Equation(s):
+// \SEG2|WideOr2~combout  = (\SEG2|Decoder0~2_combout ) # ((\SEG2|Decoder0~7_combout ) # (!\SEG2|WideOr2~0_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~2_combout ),
+	.datac(\SEG2|Decoder0~7_combout ),
+	.datad(\SEG2|WideOr2~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr2 .lut_mask = 16'hFCFF;
+defparam \SEG2|WideOr2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N2
+cycloneiii_lcell_comb \SEG2|WideOr1 (
+// Equation(s):
+// \SEG2|WideOr1~combout  = (\SEG2|Decoder0~4_combout ) # ((\SEG2|Decoder0~5_combout ) # ((\SEG2|Decoder0~7_combout ) # (\SEG2|Decoder0~1_combout )))
+
+	.dataa(\SEG2|Decoder0~4_combout ),
+	.datab(\SEG2|Decoder0~5_combout ),
+	.datac(\SEG2|Decoder0~7_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr1 .lut_mask = 16'hFFFE;
+defparam \SEG2|WideOr1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N28
+cycloneiii_lcell_comb \SEG2|Decoder0~8 (
+// Equation(s):
+// \SEG2|Decoder0~8_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~8 .lut_mask = 16'h1040;
+defparam \SEG2|Decoder0~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N14
+cycloneiii_lcell_comb \SEG2|WideOr0 (
+// Equation(s):
+// \SEG2|WideOr0~combout  = (\SEG2|Decoder0~8_combout ) # ((\SEG2|Decoder0~5_combout ) # (\SEG2|Decoder0~1_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~8_combout ),
+	.datac(\SEG2|Decoder0~5_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr0 .lut_mask = 16'hFFFC;
+defparam \SEG2|WideOr0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A23|WideOr0~5 (
+// Equation(s):
+// \BCD_CONVERT|A23|WideOr0~5_combout  = (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A23|WideOr0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A23|WideOr0~5 .lut_mask = 16'h1FFF;
+defparam \BCD_CONVERT|A23|WideOr0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A23|WideOr0~17 (
+// Equation(s):
+// \BCD_CONVERT|A23|WideOr0~17_combout  = (((\BCD_CONVERT|A23|WideOr0~5_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\BCD_CONVERT|A23|WideOr0~5_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A23|WideOr0~17 .lut_mask = 16'hF7FF;
+defparam \BCD_CONVERT|A23|WideOr0~17 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y15_N1
+cycloneiii_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N2
+cycloneiii_lcell_comb \SPI_DAC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_DAC|clk_1MHz~0_combout  = !\SPI_DAC|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_DAC|clk_1MHz~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|clk_1MHz~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~0 .lut_mask = 16'h0F0F;
+defparam \SPI_DAC|clk_1MHz~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneiii_clkctrl \CLOCK_50~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLOCK_50~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
+defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N16
+cycloneiii_lcell_comb \SPI_ADC|Add0~0 (
+// Equation(s):
+// \SPI_ADC|Add0~0_combout  = \SPI_ADC|ctr [0] $ (VCC)
+// \SPI_ADC|Add0~1  = CARRY(\SPI_ADC|ctr [0])
+
+	.dataa(\SPI_ADC|ctr [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_ADC|Add0~0_combout ),
+	.cout(\SPI_ADC|Add0~1 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~0 .lut_mask = 16'h55AA;
+defparam \SPI_ADC|Add0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N22
+cycloneiii_lcell_comb \SPI_ADC|Add0~6 (
+// Equation(s):
+// \SPI_ADC|Add0~6_combout  = (\SPI_ADC|ctr [3] & (\SPI_ADC|Add0~5  & VCC)) # (!\SPI_ADC|ctr [3] & (!\SPI_ADC|Add0~5 ))
+// \SPI_ADC|Add0~7  = CARRY((!\SPI_ADC|ctr [3] & !\SPI_ADC|Add0~5 ))
+
+	.dataa(\SPI_ADC|ctr [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~5 ),
+	.combout(\SPI_ADC|Add0~6_combout ),
+	.cout(\SPI_ADC|Add0~7 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~6 .lut_mask = 16'hA505;
+defparam \SPI_ADC|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N24
+cycloneiii_lcell_comb \SPI_ADC|Add0~8 (
+// Equation(s):
+// \SPI_ADC|Add0~8_combout  = \SPI_ADC|Add0~7  $ (\SPI_ADC|ctr [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|ctr [4]),
+	.cin(\SPI_ADC|Add0~7 ),
+	.combout(\SPI_ADC|Add0~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~8 .lut_mask = 16'h0FF0;
+defparam \SPI_ADC|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N25
+dffeas \SPI_ADC|ctr[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Add0~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N6
+cycloneiii_lcell_comb \SPI_ADC|ctr~0 (
+// Equation(s):
+// \SPI_ADC|ctr~0_combout  = (\SPI_ADC|Add0~0_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~0_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~0 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N7
+dffeas \SPI_ADC|ctr[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N18
+cycloneiii_lcell_comb \SPI_ADC|Add0~2 (
+// Equation(s):
+// \SPI_ADC|Add0~2_combout  = (\SPI_ADC|ctr [1] & (\SPI_ADC|Add0~1  & VCC)) # (!\SPI_ADC|ctr [1] & (!\SPI_ADC|Add0~1 ))
+// \SPI_ADC|Add0~3  = CARRY((!\SPI_ADC|ctr [1] & !\SPI_ADC|Add0~1 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|ctr [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~1 ),
+	.combout(\SPI_ADC|Add0~2_combout ),
+	.cout(\SPI_ADC|Add0~3 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~2 .lut_mask = 16'hC303;
+defparam \SPI_ADC|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N4
+cycloneiii_lcell_comb \SPI_ADC|ctr~1 (
+// Equation(s):
+// \SPI_ADC|ctr~1_combout  = (\SPI_ADC|Add0~2_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~2_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~1 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N5
+dffeas \SPI_ADC|ctr[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N20
+cycloneiii_lcell_comb \SPI_ADC|Add0~4 (
+// Equation(s):
+// \SPI_ADC|Add0~4_combout  = (\SPI_ADC|ctr [2] & ((GND) # (!\SPI_ADC|Add0~3 ))) # (!\SPI_ADC|ctr [2] & (\SPI_ADC|Add0~3  $ (GND)))
+// \SPI_ADC|Add0~5  = CARRY((\SPI_ADC|ctr [2]) # (!\SPI_ADC|Add0~3 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~3 ),
+	.combout(\SPI_ADC|Add0~4_combout ),
+	.cout(\SPI_ADC|Add0~5 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~4 .lut_mask = 16'h3CCF;
+defparam \SPI_ADC|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N28
+cycloneiii_lcell_comb \SPI_ADC|ctr~2 (
+// Equation(s):
+// \SPI_ADC|ctr~2_combout  = (\SPI_ADC|Add0~4_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~4_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~2 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N29
+dffeas \SPI_ADC|ctr[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N23
+dffeas \SPI_ADC|ctr[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Add0~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N0
+cycloneiii_lcell_comb \SPI_DAC|Equal0~0 (
+// Equation(s):
+// \SPI_DAC|Equal0~0_combout  = (!\SPI_ADC|ctr [3] & (!\SPI_ADC|ctr [2] & (!\SPI_ADC|ctr [1] & !\SPI_ADC|ctr [0])))
+
+	.dataa(\SPI_ADC|ctr [3]),
+	.datab(\SPI_ADC|ctr [2]),
+	.datac(\SPI_ADC|ctr [1]),
+	.datad(\SPI_ADC|ctr [0]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal0~0 .lut_mask = 16'h0001;
+defparam \SPI_DAC|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N26
+cycloneiii_lcell_comb \SPI_DAC|Equal0~1 (
+// Equation(s):
+// \SPI_DAC|Equal0~1_combout  = (\SPI_DAC|Equal0~0_combout  & !\SPI_ADC|ctr [4])
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|Equal0~0_combout ),
+	.datac(gnd),
+	.datad(\SPI_ADC|ctr [4]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal0~1 .lut_mask = 16'h00CC;
+defparam \SPI_DAC|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N3
+dffeas \SPI_DAC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\SPI_DAC|clk_1MHz~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_DAC|Equal0~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_DAC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G11
+cycloneiii_clkctrl \SPI_DAC|clk_1MHz~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_DAC|clk_1MHz~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_DAC|clk_1MHz~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~clkctrl .clock_type = "global clock";
+defparam \SPI_DAC|clk_1MHz~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N0
+cycloneiii_lcell_comb \PWM_DC|count[0]~27 (
+// Equation(s):
+// \PWM_DC|count[0]~27_combout  = !\PWM_DC|count [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\PWM_DC|count [0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\PWM_DC|count[0]~27_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|count[0]~27 .lut_mask = 16'h0F0F;
+defparam \PWM_DC|count[0]~27 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N1
+dffeas \PWM_DC|count[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[0]~27_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[0] .is_wysiwyg = "true";
+defparam \PWM_DC|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N2
+cycloneiii_lcell_comb \GEN_10K|Add0~22 (
+// Equation(s):
+// \GEN_10K|Add0~22_combout  = (\GEN_10K|ctr [11] & (\GEN_10K|Add0~21  & VCC)) # (!\GEN_10K|ctr [11] & (!\GEN_10K|Add0~21 ))
+// \GEN_10K|Add0~23  = CARRY((!\GEN_10K|ctr [11] & !\GEN_10K|Add0~21 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~21 ),
+	.combout(\GEN_10K|Add0~22_combout ),
+	.cout(\GEN_10K|Add0~23 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~22 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N4
+cycloneiii_lcell_comb \GEN_10K|Add0~24 (
+// Equation(s):
+// \GEN_10K|Add0~24_combout  = (\GEN_10K|ctr [12] & ((GND) # (!\GEN_10K|Add0~23 ))) # (!\GEN_10K|ctr [12] & (\GEN_10K|Add0~23  $ (GND)))
+// \GEN_10K|Add0~25  = CARRY((\GEN_10K|ctr [12]) # (!\GEN_10K|Add0~23 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~23 ),
+	.combout(\GEN_10K|Add0~24_combout ),
+	.cout(\GEN_10K|Add0~25 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~24 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N24
+cycloneiii_lcell_comb \GEN_10K|ctr~6 (
+// Equation(s):
+// \GEN_10K|ctr~6_combout  = (\GEN_10K|Add0~24_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Equal0~5_combout ),
+	.datab(\GEN_10K|Equal0~4_combout ),
+	.datac(\GEN_10K|Add0~24_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~6 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N25
+dffeas \GEN_10K|ctr[12] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[12] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N6
+cycloneiii_lcell_comb \GEN_10K|Add0~26 (
+// Equation(s):
+// \GEN_10K|Add0~26_combout  = (\GEN_10K|ctr [13] & (\GEN_10K|Add0~25  & VCC)) # (!\GEN_10K|ctr [13] & (!\GEN_10K|Add0~25 ))
+// \GEN_10K|Add0~27  = CARRY((!\GEN_10K|ctr [13] & !\GEN_10K|Add0~25 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [13]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~25 ),
+	.combout(\GEN_10K|Add0~26_combout ),
+	.cout(\GEN_10K|Add0~27 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~26 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N8
+cycloneiii_lcell_comb \GEN_10K|ctr~7 (
+// Equation(s):
+// \GEN_10K|ctr~7_combout  = (\GEN_10K|Add0~26_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~26_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~7 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N9
+dffeas \GEN_10K|ctr[13] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[13] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N8
+cycloneiii_lcell_comb \GEN_10K|Add0~28 (
+// Equation(s):
+// \GEN_10K|Add0~28_combout  = (\GEN_10K|ctr [14] & ((GND) # (!\GEN_10K|Add0~27 ))) # (!\GEN_10K|ctr [14] & (\GEN_10K|Add0~27  $ (GND)))
+// \GEN_10K|Add0~29  = CARRY((\GEN_10K|ctr [14]) # (!\GEN_10K|Add0~27 ))
+
+	.dataa(\GEN_10K|ctr [14]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~27 ),
+	.combout(\GEN_10K|Add0~28_combout ),
+	.cout(\GEN_10K|Add0~29 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~28 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N2
+cycloneiii_lcell_comb \GEN_10K|ctr~8 (
+// Equation(s):
+// \GEN_10K|ctr~8_combout  = (\GEN_10K|Add0~28_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~28_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~8 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N3
+dffeas \GEN_10K|ctr[14] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[14] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N10
+cycloneiii_lcell_comb \GEN_10K|Add0~30 (
+// Equation(s):
+// \GEN_10K|Add0~30_combout  = (\GEN_10K|ctr [15] & (\GEN_10K|Add0~29  & VCC)) # (!\GEN_10K|ctr [15] & (!\GEN_10K|Add0~29 ))
+// \GEN_10K|Add0~31  = CARRY((!\GEN_10K|ctr [15] & !\GEN_10K|Add0~29 ))
+
+	.dataa(\GEN_10K|ctr [15]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~29 ),
+	.combout(\GEN_10K|Add0~30_combout ),
+	.cout(\GEN_10K|Add0~31 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~30 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N20
+cycloneiii_lcell_comb \GEN_10K|ctr~9 (
+// Equation(s):
+// \GEN_10K|ctr~9_combout  = (\GEN_10K|Add0~30_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~30_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~9 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N21
+dffeas \GEN_10K|ctr[15] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[15] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N12
+cycloneiii_lcell_comb \GEN_10K|Add0~32 (
+// Equation(s):
+// \GEN_10K|Add0~32_combout  = (\GEN_10K|ctr [16] & ((GND) # (!\GEN_10K|Add0~31 ))) # (!\GEN_10K|ctr [16] & (\GEN_10K|Add0~31  $ (GND)))
+// \GEN_10K|Add0~33  = CARRY((\GEN_10K|ctr [16]) # (!\GEN_10K|Add0~31 ))
+
+	.dataa(\GEN_10K|ctr [16]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~31 ),
+	.combout(\GEN_10K|Add0~32_combout ),
+	.cout(\GEN_10K|Add0~33 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~32 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N6
+cycloneiii_lcell_comb \GEN_10K|ctr~10 (
+// Equation(s):
+// \GEN_10K|ctr~10_combout  = (\GEN_10K|Add0~32_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~32_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~10 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N7
+dffeas \GEN_10K|ctr[16] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[16] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N14
+cycloneiii_lcell_comb \GEN_10K|Add0~34 (
+// Equation(s):
+// \GEN_10K|Add0~34_combout  = (\GEN_10K|ctr [17] & (\GEN_10K|Add0~33  & VCC)) # (!\GEN_10K|ctr [17] & (!\GEN_10K|Add0~33 ))
+// \GEN_10K|Add0~35  = CARRY((!\GEN_10K|ctr [17] & !\GEN_10K|Add0~33 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [17]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~33 ),
+	.combout(\GEN_10K|Add0~34_combout ),
+	.cout(\GEN_10K|Add0~35 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~34 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N18
+cycloneiii_lcell_comb \GEN_10K|ctr~11 (
+// Equation(s):
+// \GEN_10K|ctr~11_combout  = (\GEN_10K|Add0~34_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~34_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~11 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N19
+dffeas \GEN_10K|ctr[17] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[17] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N16
+cycloneiii_lcell_comb \GEN_10K|Add0~36 (
+// Equation(s):
+// \GEN_10K|Add0~36_combout  = (\GEN_10K|ctr [18] & ((GND) # (!\GEN_10K|Add0~35 ))) # (!\GEN_10K|ctr [18] & (\GEN_10K|Add0~35  $ (GND)))
+// \GEN_10K|Add0~37  = CARRY((\GEN_10K|ctr [18]) # (!\GEN_10K|Add0~35 ))
+
+	.dataa(\GEN_10K|ctr [18]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~35 ),
+	.combout(\GEN_10K|Add0~36_combout ),
+	.cout(\GEN_10K|Add0~37 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~36 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~36 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N4
+cycloneiii_lcell_comb \GEN_10K|ctr~12 (
+// Equation(s):
+// \GEN_10K|ctr~12_combout  = (\GEN_10K|Add0~36_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~36_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~12 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N5
+dffeas \GEN_10K|ctr[18] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[18] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N18
+cycloneiii_lcell_comb \GEN_10K|Add0~38 (
+// Equation(s):
+// \GEN_10K|Add0~38_combout  = (\GEN_10K|ctr [19] & (\GEN_10K|Add0~37  & VCC)) # (!\GEN_10K|ctr [19] & (!\GEN_10K|Add0~37 ))
+// \GEN_10K|Add0~39  = CARRY((!\GEN_10K|ctr [19] & !\GEN_10K|Add0~37 ))
+
+	.dataa(\GEN_10K|ctr [19]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~37 ),
+	.combout(\GEN_10K|Add0~38_combout ),
+	.cout(\GEN_10K|Add0~39 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~38 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~38 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N26
+cycloneiii_lcell_comb \GEN_10K|ctr~13 (
+// Equation(s):
+// \GEN_10K|ctr~13_combout  = (\GEN_10K|Add0~38_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~38_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~13 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N27
+dffeas \GEN_10K|ctr[19] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[19] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N20
+cycloneiii_lcell_comb \GEN_10K|Add0~40 (
+// Equation(s):
+// \GEN_10K|Add0~40_combout  = \GEN_10K|Add0~39  $ (\GEN_10K|ctr [20])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\GEN_10K|ctr [20]),
+	.cin(\GEN_10K|Add0~39 ),
+	.combout(\GEN_10K|Add0~40_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~40 .lut_mask = 16'h0FF0;
+defparam \GEN_10K|Add0~40 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N28
+cycloneiii_lcell_comb \GEN_10K|ctr~14 (
+// Equation(s):
+// \GEN_10K|ctr~14_combout  = (\GEN_10K|Add0~40_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~40_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~14 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N29
+dffeas \GEN_10K|ctr[20] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[20] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N30
+cycloneiii_lcell_comb \GEN_10K|Equal0~5 (
+// Equation(s):
+// \GEN_10K|Equal0~5_combout  = (!\GEN_10K|ctr [18] & (!\GEN_10K|ctr [20] & (!\GEN_10K|ctr [19] & !\GEN_10K|ctr [17])))
+
+	.dataa(\GEN_10K|ctr [18]),
+	.datab(\GEN_10K|ctr [20]),
+	.datac(\GEN_10K|ctr [19]),
+	.datad(\GEN_10K|ctr [17]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~5 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N12
+cycloneiii_lcell_comb \GEN_10K|Add0~1 (
+// Equation(s):
+// \GEN_10K|Add0~1_cout  = CARRY(\PWM_DC|count [0])
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\GEN_10K|Add0~1_cout ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~1 .lut_mask = 16'h00AA;
+defparam \GEN_10K|Add0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N14
+cycloneiii_lcell_comb \GEN_10K|Add0~2 (
+// Equation(s):
+// \GEN_10K|Add0~2_combout  = (\GEN_10K|ctr [1] & (\GEN_10K|Add0~1_cout  & VCC)) # (!\GEN_10K|ctr [1] & (!\GEN_10K|Add0~1_cout ))
+// \GEN_10K|Add0~3  = CARRY((!\GEN_10K|ctr [1] & !\GEN_10K|Add0~1_cout ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~1_cout ),
+	.combout(\GEN_10K|Add0~2_combout ),
+	.cout(\GEN_10K|Add0~3 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~2 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N15
+dffeas \GEN_10K|ctr[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[1] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N16
+cycloneiii_lcell_comb \GEN_10K|Add0~4 (
+// Equation(s):
+// \GEN_10K|Add0~4_combout  = (\GEN_10K|ctr [2] & ((GND) # (!\GEN_10K|Add0~3 ))) # (!\GEN_10K|ctr [2] & (\GEN_10K|Add0~3  $ (GND)))
+// \GEN_10K|Add0~5  = CARRY((\GEN_10K|ctr [2]) # (!\GEN_10K|Add0~3 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~3 ),
+	.combout(\GEN_10K|Add0~4_combout ),
+	.cout(\GEN_10K|Add0~5 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~4 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N10
+cycloneiii_lcell_comb \GEN_10K|ctr~0 (
+// Equation(s):
+// \GEN_10K|ctr~0_combout  = (\GEN_10K|Add0~4_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~0 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N11
+dffeas \GEN_10K|ctr[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[2] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N18
+cycloneiii_lcell_comb \GEN_10K|Add0~6 (
+// Equation(s):
+// \GEN_10K|Add0~6_combout  = (\GEN_10K|ctr [3] & (\GEN_10K|Add0~5  & VCC)) # (!\GEN_10K|ctr [3] & (!\GEN_10K|Add0~5 ))
+// \GEN_10K|Add0~7  = CARRY((!\GEN_10K|ctr [3] & !\GEN_10K|Add0~5 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~5 ),
+	.combout(\GEN_10K|Add0~6_combout ),
+	.cout(\GEN_10K|Add0~7 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~6 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N0
+cycloneiii_lcell_comb \GEN_10K|ctr~1 (
+// Equation(s):
+// \GEN_10K|ctr~1_combout  = (\GEN_10K|Add0~6_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\PWM_DC|count [0]),
+	.datad(\GEN_10K|Add0~6_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~1 .lut_mask = 16'hF700;
+defparam \GEN_10K|ctr~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N1
+dffeas \GEN_10K|ctr[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[3] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N20
+cycloneiii_lcell_comb \GEN_10K|Add0~8 (
+// Equation(s):
+// \GEN_10K|Add0~8_combout  = (\GEN_10K|ctr [4] & ((GND) # (!\GEN_10K|Add0~7 ))) # (!\GEN_10K|ctr [4] & (\GEN_10K|Add0~7  $ (GND)))
+// \GEN_10K|Add0~9  = CARRY((\GEN_10K|ctr [4]) # (!\GEN_10K|Add0~7 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~7 ),
+	.combout(\GEN_10K|Add0~8_combout ),
+	.cout(\GEN_10K|Add0~9 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~8 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N12
+cycloneiii_lcell_comb \GEN_10K|ctr~2 (
+// Equation(s):
+// \GEN_10K|ctr~2_combout  = (\GEN_10K|Add0~8_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~8_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~2 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N13
+dffeas \GEN_10K|ctr[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[4] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N22
+cycloneiii_lcell_comb \GEN_10K|Add0~10 (
+// Equation(s):
+// \GEN_10K|Add0~10_combout  = (\GEN_10K|ctr [5] & (\GEN_10K|Add0~9  & VCC)) # (!\GEN_10K|ctr [5] & (!\GEN_10K|Add0~9 ))
+// \GEN_10K|Add0~11  = CARRY((!\GEN_10K|ctr [5] & !\GEN_10K|Add0~9 ))
+
+	.dataa(\GEN_10K|ctr [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~9 ),
+	.combout(\GEN_10K|Add0~10_combout ),
+	.cout(\GEN_10K|Add0~11 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~10 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N14
+cycloneiii_lcell_comb \GEN_10K|ctr~3 (
+// Equation(s):
+// \GEN_10K|ctr~3_combout  = (\GEN_10K|Add0~10_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~10_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~3 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N15
+dffeas \GEN_10K|ctr[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[5] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N24
+cycloneiii_lcell_comb \GEN_10K|Add0~12 (
+// Equation(s):
+// \GEN_10K|Add0~12_combout  = (\GEN_10K|ctr [6] & ((GND) # (!\GEN_10K|Add0~11 ))) # (!\GEN_10K|ctr [6] & (\GEN_10K|Add0~11  $ (GND)))
+// \GEN_10K|Add0~13  = CARRY((\GEN_10K|ctr [6]) # (!\GEN_10K|Add0~11 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~11 ),
+	.combout(\GEN_10K|Add0~12_combout ),
+	.cout(\GEN_10K|Add0~13 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~12 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N25
+dffeas \GEN_10K|ctr[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[6] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N26
+cycloneiii_lcell_comb \GEN_10K|Add0~14 (
+// Equation(s):
+// \GEN_10K|Add0~14_combout  = (\GEN_10K|ctr [7] & (\GEN_10K|Add0~13  & VCC)) # (!\GEN_10K|ctr [7] & (!\GEN_10K|Add0~13 ))
+// \GEN_10K|Add0~15  = CARRY((!\GEN_10K|ctr [7] & !\GEN_10K|Add0~13 ))
+
+	.dataa(\GEN_10K|ctr [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~13 ),
+	.combout(\GEN_10K|Add0~14_combout ),
+	.cout(\GEN_10K|Add0~15 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~14 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N27
+dffeas \GEN_10K|ctr[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[7] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N28
+cycloneiii_lcell_comb \GEN_10K|Add0~16 (
+// Equation(s):
+// \GEN_10K|Add0~16_combout  = (\GEN_10K|ctr [8] & ((GND) # (!\GEN_10K|Add0~15 ))) # (!\GEN_10K|ctr [8] & (\GEN_10K|Add0~15  $ (GND)))
+// \GEN_10K|Add0~17  = CARRY((\GEN_10K|ctr [8]) # (!\GEN_10K|Add0~15 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~15 ),
+	.combout(\GEN_10K|Add0~16_combout ),
+	.cout(\GEN_10K|Add0~17 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~16 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N29
+dffeas \GEN_10K|ctr[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~16_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[8] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N30
+cycloneiii_lcell_comb \GEN_10K|Add0~18 (
+// Equation(s):
+// \GEN_10K|Add0~18_combout  = (\GEN_10K|ctr [9] & (\GEN_10K|Add0~17  & VCC)) # (!\GEN_10K|ctr [9] & (!\GEN_10K|Add0~17 ))
+// \GEN_10K|Add0~19  = CARRY((!\GEN_10K|ctr [9] & !\GEN_10K|Add0~17 ))
+
+	.dataa(\GEN_10K|ctr [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~17 ),
+	.combout(\GEN_10K|Add0~18_combout ),
+	.cout(\GEN_10K|Add0~19 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~18 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N6
+cycloneiii_lcell_comb \GEN_10K|ctr~4 (
+// Equation(s):
+// \GEN_10K|ctr~4_combout  = (\GEN_10K|Add0~18_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~18_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\PWM_DC|count [0]),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~4 .lut_mask = 16'hA2AA;
+defparam \GEN_10K|ctr~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N7
+dffeas \GEN_10K|ctr[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[9] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N0
+cycloneiii_lcell_comb \GEN_10K|Add0~20 (
+// Equation(s):
+// \GEN_10K|Add0~20_combout  = (\GEN_10K|ctr [10] & ((GND) # (!\GEN_10K|Add0~19 ))) # (!\GEN_10K|ctr [10] & (\GEN_10K|Add0~19  $ (GND)))
+// \GEN_10K|Add0~21  = CARRY((\GEN_10K|ctr [10]) # (!\GEN_10K|Add0~19 ))
+
+	.dataa(\GEN_10K|ctr [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~19 ),
+	.combout(\GEN_10K|Add0~20_combout ),
+	.cout(\GEN_10K|Add0~21 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~20 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N22
+cycloneiii_lcell_comb \GEN_10K|ctr~5 (
+// Equation(s):
+// \GEN_10K|ctr~5_combout  = (\GEN_10K|Add0~20_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~20_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~5 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N23
+dffeas \GEN_10K|ctr[10] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[10] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N3
+dffeas \GEN_10K|ctr[11] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~22_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[11] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N8
+cycloneiii_lcell_comb \GEN_10K|Equal0~2 (
+// Equation(s):
+// \GEN_10K|Equal0~2_combout  = (!\GEN_10K|ctr [11] & (!\GEN_10K|ctr [10] & (!\GEN_10K|ctr [12] & !\GEN_10K|ctr [9])))
+
+	.dataa(\GEN_10K|ctr [11]),
+	.datab(\GEN_10K|ctr [10]),
+	.datac(\GEN_10K|ctr [12]),
+	.datad(\GEN_10K|ctr [9]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~2 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N2
+cycloneiii_lcell_comb \GEN_10K|Equal0~0 (
+// Equation(s):
+// \GEN_10K|Equal0~0_combout  = (!\GEN_10K|ctr [1] & (!\GEN_10K|ctr [2] & (!\GEN_10K|ctr [4] & !\GEN_10K|ctr [3])))
+
+	.dataa(\GEN_10K|ctr [1]),
+	.datab(\GEN_10K|ctr [2]),
+	.datac(\GEN_10K|ctr [4]),
+	.datad(\GEN_10K|ctr [3]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~0 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N4
+cycloneiii_lcell_comb \GEN_10K|Equal0~1 (
+// Equation(s):
+// \GEN_10K|Equal0~1_combout  = (!\GEN_10K|ctr [5] & (!\GEN_10K|ctr [6] & (!\GEN_10K|ctr [7] & !\GEN_10K|ctr [8])))
+
+	.dataa(\GEN_10K|ctr [5]),
+	.datab(\GEN_10K|ctr [6]),
+	.datac(\GEN_10K|ctr [7]),
+	.datad(\GEN_10K|ctr [8]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~1 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N16
+cycloneiii_lcell_comb \GEN_10K|Equal0~3 (
+// Equation(s):
+// \GEN_10K|Equal0~3_combout  = (!\GEN_10K|ctr [16] & (!\GEN_10K|ctr [14] & (!\GEN_10K|ctr [13] & !\GEN_10K|ctr [15])))
+
+	.dataa(\GEN_10K|ctr [16]),
+	.datab(\GEN_10K|ctr [14]),
+	.datac(\GEN_10K|ctr [13]),
+	.datad(\GEN_10K|ctr [15]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~3 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N10
+cycloneiii_lcell_comb \GEN_10K|Equal0~4 (
+// Equation(s):
+// \GEN_10K|Equal0~4_combout  = (\GEN_10K|Equal0~2_combout  & (\GEN_10K|Equal0~0_combout  & (\GEN_10K|Equal0~1_combout  & \GEN_10K|Equal0~3_combout )))
+
+	.dataa(\GEN_10K|Equal0~2_combout ),
+	.datab(\GEN_10K|Equal0~0_combout ),
+	.datac(\GEN_10K|Equal0~1_combout ),
+	.datad(\GEN_10K|Equal0~3_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~4 .lut_mask = 16'h8000;
+defparam \GEN_10K|Equal0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N28
+cycloneiii_lcell_comb \GEN_10K|clkout~0 (
+// Equation(s):
+// \GEN_10K|clkout~0_combout  = \GEN_10K|clkout~q  $ (((\GEN_10K|Equal0~4_combout  & (\GEN_10K|Equal0~5_combout  & !\PWM_DC|count [0]))))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|clkout~q ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|clkout~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|clkout~0 .lut_mask = 16'hF078;
+defparam \GEN_10K|clkout~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N29
+dffeas \GEN_10K|clkout (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|clkout~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|clkout~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|clkout .is_wysiwyg = "true";
+defparam \GEN_10K|clkout .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N22
+cycloneiii_lcell_comb \PULSE|state.IDLE~feeder (
+// Equation(s):
+// \PULSE|state.IDLE~feeder_combout  = \GEN_10K|clkout~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\GEN_10K|clkout~q ),
+	.cin(gnd),
+	.combout(\PULSE|state.IDLE~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PULSE|state.IDLE~feeder .lut_mask = 16'hFF00;
+defparam \PULSE|state.IDLE~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N23
+dffeas \PULSE|state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PULSE|state.IDLE~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PULSE|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PULSE|state.IDLE .is_wysiwyg = "true";
+defparam \PULSE|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N0
+cycloneiii_lcell_comb \PULSE|pulse~1 (
+// Equation(s):
+// \PULSE|pulse~1_combout  = (!\PULSE|state.IDLE~q  & \GEN_10K|clkout~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\PULSE|state.IDLE~q ),
+	.datad(\GEN_10K|clkout~q ),
+	.cin(gnd),
+	.combout(\PULSE|pulse~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PULSE|pulse~1 .lut_mask = 16'h0F00;
+defparam \PULSE|pulse~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N1
+dffeas \PULSE|pulse (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PULSE|pulse~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PULSE|pulse~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PULSE|pulse .is_wysiwyg = "true";
+defparam \PULSE|pulse .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N0
+cycloneiii_lcell_comb \SPI_DAC|Selector2~0 (
+// Equation(s):
+// \SPI_DAC|Selector2~0_combout  = (\SPI_DAC|dac_cs~q  & \SPI_DAC|sr_state.IDLE~q )
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector2~0 .lut_mask = 16'hAA00;
+defparam \SPI_DAC|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N1
+dffeas \SPI_DAC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N2
+cycloneiii_lcell_comb \SPI_DAC|Selector0~0 (
+// Equation(s):
+// \SPI_DAC|Selector0~0_combout  = (\SPI_DAC|dac_cs~q  & ((\PULSE|pulse~q ) # ((\SPI_DAC|sr_state.IDLE~q )))) # (!\SPI_DAC|dac_cs~q  & (!\SPI_DAC|sr_state.WAIT_CSB_HIGH~q  & ((\PULSE|pulse~q ) # (\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|sr_state.IDLE~q ),
+	.datad(\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector0~0 .lut_mask = 16'hA8FC;
+defparam \SPI_DAC|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N3
+dffeas \SPI_DAC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N24
+cycloneiii_lcell_comb \SPI_DAC|Selector1~0 (
+// Equation(s):
+// \SPI_DAC|Selector1~0_combout  = (\SPI_DAC|dac_cs~q  & (\PULSE|pulse~q  & ((!\SPI_DAC|sr_state.IDLE~q )))) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|sr_state.WAIT_CSB_FALL~q ) # ((\PULSE|pulse~q  & !\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector1~0 .lut_mask = 16'h50DC;
+defparam \SPI_DAC|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N25
+dffeas \SPI_DAC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N4
+cycloneiii_lcell_comb \SPI_DAC|dac_start~0 (
+// Equation(s):
+// \SPI_DAC|dac_start~0_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q ) # ((\SPI_DAC|sr_state.WAIT_CSB_FALL~q ) # (!\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|sr_state.IDLE~q ),
+	.datac(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|dac_start~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_start~0 .lut_mask = 16'hFB00;
+defparam \SPI_DAC|dac_start~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N20
+cycloneiii_lcell_comb \SPI_DAC|dac_start~1 (
+// Equation(s):
+// \SPI_DAC|dac_start~1_combout  = (\SPI_DAC|dac_start~0_combout ) # ((\PULSE|pulse~q  & !\SPI_DAC|sr_state.IDLE~q ))
+
+	.dataa(gnd),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|dac_start~0_combout ),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|dac_start~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_start~1 .lut_mask = 16'hF0FC;
+defparam \SPI_DAC|dac_start~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N21
+dffeas \SPI_DAC|dac_start (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|dac_start~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_start .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N0
+cycloneiii_lcell_comb \SPI_DAC|state[0]~5 (
+// Equation(s):
+// \SPI_DAC|state[0]~5_combout  = \SPI_DAC|state [0] $ (VCC)
+// \SPI_DAC|state[0]~6  = CARRY(\SPI_DAC|state [0])
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_DAC|state[0]~5_combout ),
+	.cout(\SPI_DAC|state[0]~6 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[0]~5 .lut_mask = 16'h33CC;
+defparam \SPI_DAC|state[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N6
+cycloneiii_lcell_comb \SPI_DAC|state[3]~11 (
+// Equation(s):
+// \SPI_DAC|state[3]~11_combout  = (\SPI_DAC|state [3] & (!\SPI_DAC|state[2]~10 )) # (!\SPI_DAC|state [3] & ((\SPI_DAC|state[2]~10 ) # (GND)))
+// \SPI_DAC|state[3]~12  = CARRY((!\SPI_DAC|state[2]~10 ) # (!\SPI_DAC|state [3]))
+
+	.dataa(\SPI_DAC|state [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[2]~10 ),
+	.combout(\SPI_DAC|state[3]~11_combout ),
+	.cout(\SPI_DAC|state[3]~12 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[3]~11 .lut_mask = 16'h5A5F;
+defparam \SPI_DAC|state[3]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N8
+cycloneiii_lcell_comb \SPI_DAC|state[4]~13 (
+// Equation(s):
+// \SPI_DAC|state[4]~13_combout  = \SPI_DAC|state [4] $ (!\SPI_DAC|state[3]~12 )
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [4]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\SPI_DAC|state[3]~12 ),
+	.combout(\SPI_DAC|state[4]~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|state[4]~13 .lut_mask = 16'hC3C3;
+defparam \SPI_DAC|state[4]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N9
+dffeas \SPI_DAC|state[4] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[4]~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N24
+cycloneiii_lcell_comb \SPI_DAC|Selector8~0 (
+// Equation(s):
+// \SPI_DAC|Selector8~0_combout  = (\SPI_DAC|Equal1~0_combout  & ((\SPI_DAC|state [4]) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_start~q ),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector8~0 .lut_mask = 16'hC4C4;
+defparam \SPI_DAC|Selector8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N1
+dffeas \SPI_DAC|state[0] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[0]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[0] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N2
+cycloneiii_lcell_comb \SPI_DAC|state[1]~7 (
+// Equation(s):
+// \SPI_DAC|state[1]~7_combout  = (\SPI_DAC|state [1] & (!\SPI_DAC|state[0]~6 )) # (!\SPI_DAC|state [1] & ((\SPI_DAC|state[0]~6 ) # (GND)))
+// \SPI_DAC|state[1]~8  = CARRY((!\SPI_DAC|state[0]~6 ) # (!\SPI_DAC|state [1]))
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[0]~6 ),
+	.combout(\SPI_DAC|state[1]~7_combout ),
+	.cout(\SPI_DAC|state[1]~8 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[1]~7 .lut_mask = 16'h3C3F;
+defparam \SPI_DAC|state[1]~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N3
+dffeas \SPI_DAC|state[1] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[1]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[1] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N4
+cycloneiii_lcell_comb \SPI_DAC|state[2]~9 (
+// Equation(s):
+// \SPI_DAC|state[2]~9_combout  = (\SPI_DAC|state [2] & (\SPI_DAC|state[1]~8  $ (GND))) # (!\SPI_DAC|state [2] & (!\SPI_DAC|state[1]~8  & VCC))
+// \SPI_DAC|state[2]~10  = CARRY((\SPI_DAC|state [2] & !\SPI_DAC|state[1]~8 ))
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[1]~8 ),
+	.combout(\SPI_DAC|state[2]~9_combout ),
+	.cout(\SPI_DAC|state[2]~10 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[2]~9 .lut_mask = 16'hC30C;
+defparam \SPI_DAC|state[2]~9 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N5
+dffeas \SPI_DAC|state[2] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[2]~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N7
+dffeas \SPI_DAC|state[3] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[3]~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N14
+cycloneiii_lcell_comb \SPI_DAC|Equal1~0 (
+// Equation(s):
+// \SPI_DAC|Equal1~0_combout  = (!\SPI_DAC|state [3] & (!\SPI_DAC|state [1] & (!\SPI_DAC|state [2] & !\SPI_DAC|state [0])))
+
+	.dataa(\SPI_DAC|state [3]),
+	.datab(\SPI_DAC|state [1]),
+	.datac(\SPI_DAC|state [2]),
+	.datad(\SPI_DAC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal1~0 .lut_mask = 16'h0001;
+defparam \SPI_DAC|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N10
+cycloneiii_lcell_comb \SPI_DAC|Selector9~0 (
+// Equation(s):
+// \SPI_DAC|Selector9~0_combout  = ((\SPI_DAC|dac_start~q  & !\SPI_DAC|state [4])) # (!\SPI_DAC|Equal1~0_combout )
+
+	.dataa(\SPI_DAC|dac_start~q ),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector9~0 .lut_mask = 16'h3B3B;
+defparam \SPI_DAC|Selector9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N11
+dffeas \SPI_DAC|dac_cs (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|Selector9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_cs .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N8
+cycloneiii_lcell_comb \SPI_ADC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_ADC|clk_1MHz~0_combout  = !\SPI_ADC|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_ADC|clk_1MHz~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|clk_1MHz~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~0 .lut_mask = 16'h0F0F;
+defparam \SPI_ADC|clk_1MHz~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N9
+dffeas \SPI_ADC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\SPI_ADC|clk_1MHz~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_DAC|Equal0~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_ADC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G12
+cycloneiii_clkctrl \SPI_ADC|clk_1MHz~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_ADC|clk_1MHz~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_ADC|clk_1MHz~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~clkctrl .clock_type = "global clock";
+defparam \SPI_ADC|clk_1MHz~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: IOIBUF_X3_Y0_N22
+cycloneiii_io_ibuf \ADC_SDO~input (
+	.i(ADC_SDO),
+	.ibar(gnd),
+	.o(\ADC_SDO~input_o ));
+// synopsys translate_off
+defparam \ADC_SDO~input .bus_hold = "false";
+defparam \ADC_SDO~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N24
+cycloneiii_lcell_comb \SPI_ADC|Selector2~0 (
+// Equation(s):
+// \SPI_ADC|Selector2~0_combout  = (\SPI_ADC|sr_state.IDLE~q  & \SPI_ADC|adc_cs~q )
+
+	.dataa(\SPI_ADC|sr_state.IDLE~q ),
+	.datab(gnd),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector2~0 .lut_mask = 16'hA0A0;
+defparam \SPI_ADC|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N25
+dffeas \SPI_ADC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N26
+cycloneiii_lcell_comb \SPI_ADC|Selector0~0 (
+// Equation(s):
+// \SPI_ADC|Selector0~0_combout  = (\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & (\SPI_ADC|adc_cs~q  & ((\SPI_ADC|sr_state.IDLE~q ) # (\PULSE|pulse~q )))) # (!\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & (((\SPI_ADC|sr_state.IDLE~q ) # (\PULSE|pulse~q ))))
+
+	.dataa(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(\SPI_ADC|sr_state.IDLE~q ),
+	.datad(\PULSE|pulse~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector0~0 .lut_mask = 16'hDDD0;
+defparam \SPI_ADC|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N27
+dffeas \SPI_ADC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N12
+cycloneiii_lcell_comb \SPI_ADC|Selector1~0 (
+// Equation(s):
+// \SPI_ADC|Selector1~0_combout  = (\PULSE|pulse~q  & (((!\SPI_ADC|adc_cs~q  & \SPI_ADC|sr_state.WAIT_CSB_FALL~q )) # (!\SPI_ADC|sr_state.IDLE~q ))) # (!\PULSE|pulse~q  & (!\SPI_ADC|adc_cs~q  & (\SPI_ADC|sr_state.WAIT_CSB_FALL~q )))
+
+	.dataa(\PULSE|pulse~q ),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_ADC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector1~0 .lut_mask = 16'h30BA;
+defparam \SPI_ADC|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N13
+dffeas \SPI_ADC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N30
+cycloneiii_lcell_comb \SPI_ADC|adc_start~0 (
+// Equation(s):
+// \SPI_ADC|adc_start~0_combout  = (\SPI_ADC|adc_start~q  & ((\SPI_ADC|sr_state.WAIT_CSB_FALL~q ) # ((\SPI_ADC|adc_cs~q ) # (!\SPI_ADC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datab(\SPI_ADC|sr_state.IDLE~q ),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_ADC|adc_start~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|adc_start~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~0 .lut_mask = 16'hFB00;
+defparam \SPI_ADC|adc_start~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N10
+cycloneiii_lcell_comb \SPI_ADC|adc_start~1 (
+// Equation(s):
+// \SPI_ADC|adc_start~1_combout  = (\SPI_ADC|adc_start~0_combout ) # ((!\SPI_ADC|sr_state.IDLE~q  & \PULSE|pulse~q ))
+
+	.dataa(\SPI_ADC|adc_start~0_combout ),
+	.datab(\SPI_ADC|sr_state.IDLE~q ),
+	.datac(\PULSE|pulse~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|adc_start~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~1 .lut_mask = 16'hBABA;
+defparam \SPI_ADC|adc_start~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N11
+dffeas \SPI_ADC|adc_start (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|adc_start~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_start .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N24
+cycloneiii_lcell_comb \SPI_ADC|Add1~4 (
+// Equation(s):
+// \SPI_ADC|Add1~4_combout  = (\SPI_ADC|state [2] & (\SPI_ADC|Add1~3  $ (GND))) # (!\SPI_ADC|state [2] & (!\SPI_ADC|Add1~3  & VCC))
+// \SPI_ADC|Add1~5  = CARRY((\SPI_ADC|state [2] & !\SPI_ADC|Add1~3 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~3 ),
+	.combout(\SPI_ADC|Add1~4_combout ),
+	.cout(\SPI_ADC|Add1~5 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~4 .lut_mask = 16'hC30C;
+defparam \SPI_ADC|Add1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N26
+cycloneiii_lcell_comb \SPI_ADC|Add1~6 (
+// Equation(s):
+// \SPI_ADC|Add1~6_combout  = (\SPI_ADC|state [3] & (!\SPI_ADC|Add1~5 )) # (!\SPI_ADC|state [3] & ((\SPI_ADC|Add1~5 ) # (GND)))
+// \SPI_ADC|Add1~7  = CARRY((!\SPI_ADC|Add1~5 ) # (!\SPI_ADC|state [3]))
+
+	.dataa(\SPI_ADC|state [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~5 ),
+	.combout(\SPI_ADC|Add1~6_combout ),
+	.cout(\SPI_ADC|Add1~7 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~6 .lut_mask = 16'h5A5F;
+defparam \SPI_ADC|Add1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N27
+dffeas \SPI_ADC|state[3] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N28
+cycloneiii_lcell_comb \SPI_ADC|Add1~8 (
+// Equation(s):
+// \SPI_ADC|Add1~8_combout  = \SPI_ADC|Add1~7  $ (!\SPI_ADC|state [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(\SPI_ADC|Add1~7 ),
+	.combout(\SPI_ADC|Add1~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Add1~8 .lut_mask = 16'hF00F;
+defparam \SPI_ADC|Add1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N0
+cycloneiii_lcell_comb \SPI_ADC|state~1 (
+// Equation(s):
+// \SPI_ADC|state~1_combout  = (\SPI_ADC|Add1~8_combout  & ((\SPI_ADC|state [1]) # (!\SPI_ADC|state~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|Add1~8_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|state~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|state~1 .lut_mask = 16'hF300;
+defparam \SPI_ADC|state~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N1
+dffeas \SPI_ADC|state[4] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|state~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N10
+cycloneiii_lcell_comb \SPI_ADC|Selector4~2 (
+// Equation(s):
+// \SPI_ADC|Selector4~2_combout  = (\SPI_ADC|state [4]) # (!\SPI_ADC|adc_start~q )
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~2 .lut_mask = 16'hFF55;
+defparam \SPI_ADC|Selector4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N20
+cycloneiii_lcell_comb \SPI_ADC|Add1~0 (
+// Equation(s):
+// \SPI_ADC|Add1~0_combout  = \SPI_ADC|state [0] $ (VCC)
+// \SPI_ADC|Add1~1  = CARRY(\SPI_ADC|state [0])
+
+	.dataa(\SPI_ADC|state [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_ADC|Add1~0_combout ),
+	.cout(\SPI_ADC|Add1~1 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~0 .lut_mask = 16'h55AA;
+defparam \SPI_ADC|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N12
+cycloneiii_lcell_comb \SPI_ADC|Selector5~0 (
+// Equation(s):
+// \SPI_ADC|Selector5~0_combout  = (\SPI_ADC|state~0_combout  & (((\SPI_ADC|state [1])) # (!\SPI_ADC|Selector4~2_combout ))) # (!\SPI_ADC|state~0_combout  & (((\SPI_ADC|Add1~0_combout ))))
+
+	.dataa(\SPI_ADC|Selector4~2_combout ),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|Add1~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector5~0 .lut_mask = 16'hF7C4;
+defparam \SPI_ADC|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N13
+dffeas \SPI_ADC|state[0] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N22
+cycloneiii_lcell_comb \SPI_ADC|Add1~2 (
+// Equation(s):
+// \SPI_ADC|Add1~2_combout  = (\SPI_ADC|state [1] & (!\SPI_ADC|Add1~1 )) # (!\SPI_ADC|state [1] & ((\SPI_ADC|Add1~1 ) # (GND)))
+// \SPI_ADC|Add1~3  = CARRY((!\SPI_ADC|Add1~1 ) # (!\SPI_ADC|state [1]))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~1 ),
+	.combout(\SPI_ADC|Add1~2_combout ),
+	.cout(\SPI_ADC|Add1~3 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~2 .lut_mask = 16'h5A5F;
+defparam \SPI_ADC|Add1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N23
+dffeas \SPI_ADC|state[1] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N25
+dffeas \SPI_ADC|state[2] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N2
+cycloneiii_lcell_comb \SPI_ADC|state~0 (
+// Equation(s):
+// \SPI_ADC|state~0_combout  = (!\SPI_ADC|state [2] & (!\SPI_ADC|state [3] & !\SPI_ADC|state [0]))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|state~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|state~0 .lut_mask = 16'h0003;
+defparam \SPI_ADC|state~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N6
+cycloneiii_lcell_comb \SPI_ADC|Selector4~3 (
+// Equation(s):
+// \SPI_ADC|Selector4~3_combout  = ((\SPI_ADC|state [1]) # ((\SPI_ADC|adc_start~q  & !\SPI_ADC|state [4]))) # (!\SPI_ADC|state~0_combout )
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector4~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~3 .lut_mask = 16'hF3FB;
+defparam \SPI_ADC|Selector4~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N7
+dffeas \SPI_ADC|adc_cs (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Selector4~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N16
+cycloneiii_lcell_comb \SPI_ADC|WideOr0~0 (
+// Equation(s):
+// \SPI_ADC|WideOr0~0_combout  = (\SPI_ADC|state [2] & (((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [3])) # (!\SPI_ADC|state [1]))) # (!\SPI_ADC|state [2] & (((\SPI_ADC|state [3]))))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~0 .lut_mask = 16'h7CFC;
+defparam \SPI_ADC|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N14
+cycloneiii_lcell_comb \SPI_ADC|WideOr0~1 (
+// Equation(s):
+// \SPI_ADC|WideOr0~1_combout  = (\SPI_ADC|state [4] & (((\SPI_ADC|state [1])) # (!\SPI_ADC|state~0_combout ))) # (!\SPI_ADC|state [4] & (((\SPI_ADC|WideOr0~0_combout ))))
+
+	.dataa(\SPI_ADC|state~0_combout ),
+	.datab(\SPI_ADC|WideOr0~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~1 .lut_mask = 16'hF5CC;
+defparam \SPI_ADC|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N15
+dffeas \SPI_ADC|shift_ena (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|WideOr0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_ena~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_ena .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_ena .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N14
+cycloneiii_lcell_comb \SPI_ADC|always3~0 (
+// Equation(s):
+// \SPI_ADC|always3~0_combout  = (\SPI_ADC|adc_cs~q  & \SPI_ADC|shift_ena~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_ADC|shift_ena~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|always3~0 .lut_mask = 16'hF000;
+defparam \SPI_ADC|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N21
+dffeas \SPI_ADC|shift_reg[0] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\ADC_SDO~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N26
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[1]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[1]~feeder_combout  = \SPI_ADC|shift_reg [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N27
+dffeas \SPI_ADC|shift_reg[1] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N17
+dffeas \SPI_ADC|shift_reg[2] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N22
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[3]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[3]~feeder_combout  = \SPI_ADC|shift_reg [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [2]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N23
+dffeas \SPI_ADC|shift_reg[3] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N29
+dffeas \SPI_ADC|shift_reg[4] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N18
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[5]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[5]~feeder_combout  = \SPI_ADC|shift_reg [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N19
+dffeas \SPI_ADC|shift_reg[5] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N8
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[6]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[6]~feeder_combout  = \SPI_ADC|shift_reg [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [5]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N9
+dffeas \SPI_ADC|shift_reg[6] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N31
+dffeas \SPI_ADC|shift_reg[7] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N18
+cycloneiii_lcell_comb \SPI_ADC|Decoder0~0 (
+// Equation(s):
+// \SPI_ADC|Decoder0~0_combout  = (\SPI_ADC|state [1] & (\SPI_ADC|state [2] & (\SPI_ADC|state [3] & \SPI_ADC|state [0])))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~0 .lut_mask = 16'h8000;
+defparam \SPI_ADC|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N4
+cycloneiii_lcell_comb \SPI_ADC|Decoder0~1 (
+// Equation(s):
+// \SPI_ADC|Decoder0~1_combout  = (\SPI_ADC|Decoder0~0_combout  & !\SPI_ADC|state [4])
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Decoder0~0_combout ),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Decoder0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~1 .lut_mask = 16'h00CC;
+defparam \SPI_ADC|Decoder0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N5
+dffeas \SPI_ADC|adc_done (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Decoder0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_done~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_done .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_done .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N19
+dffeas \SPI_ADC|data_from_adc[7] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y20_N2
+cycloneiii_lcell_comb \DUMMY|PULSE2|state.IDLE~0 (
+// Equation(s):
+// \DUMMY|PULSE2|state.IDLE~0_combout  = !\SPI_ADC|adc_cs~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|adc_cs~q ),
+	.cin(gnd),
+	.combout(\DUMMY|PULSE2|state.IDLE~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|PULSE2|state.IDLE~0 .lut_mask = 16'h00FF;
+defparam \DUMMY|PULSE2|state.IDLE~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y20_N3
+dffeas \DUMMY|PULSE2|state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|PULSE2|state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|PULSE2|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|PULSE2|state.IDLE .is_wysiwyg = "true";
+defparam \DUMMY|PULSE2|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y20_N0
+cycloneiii_lcell_comb \DUMMY|PULSE2|pulse~1 (
+// Equation(s):
+// \DUMMY|PULSE2|pulse~1_combout  = (!\SPI_ADC|adc_cs~q  & !\DUMMY|PULSE2|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(gnd),
+	.datad(\DUMMY|PULSE2|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\DUMMY|PULSE2|pulse~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|PULSE2|pulse~1 .lut_mask = 16'h0033;
+defparam \DUMMY|PULSE2|pulse~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y20_N1
+dffeas \DUMMY|PULSE2|pulse (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|PULSE2|pulse~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|PULSE2|pulse~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|PULSE2|pulse .is_wysiwyg = "true";
+defparam \DUMMY|PULSE2|pulse .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N25
+dffeas \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|PULSE2|pulse~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store .is_wysiwyg = "true";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N24
+cycloneiii_lcell_comb \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 (
+// Equation(s):
+// \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout  = (\DUMMY|PULSE2|pulse~q ) # (\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q )
+
+	.dataa(gnd),
+	.datab(\DUMMY|PULSE2|pulse~q ),
+	.datac(\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 .lut_mask = 16'hFCFC;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N13
+dffeas \SPI_ADC|shift_reg[8] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N21
+dffeas \SPI_ADC|data_from_adc[8] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N10
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[9]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[9]~feeder_combout  = \SPI_ADC|shift_reg [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [8]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N11
+dffeas \SPI_ADC|shift_reg[9] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N23
+dffeas \SPI_ADC|data_from_adc[9] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G10
+cycloneiii_clkctrl \SPI_ADC|adc_cs~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_ADC|adc_cs~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_ADC|adc_cs~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs~clkctrl .clock_type = "global clock";
+defparam \SPI_ADC|adc_cs~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N0
+cycloneiii_lcell_comb \DUMMY|ctr[0]~36 (
+// Equation(s):
+// \DUMMY|ctr[0]~36_combout  = !\DUMMY|ctr [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\DUMMY|ctr [0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|ctr[0]~36_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|ctr[0]~36 .lut_mask = 16'h0F0F;
+defparam \DUMMY|ctr[0]~36 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N1
+dffeas \DUMMY|ctr[0] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[0]~36_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[0] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N6
+cycloneiii_lcell_comb \DUMMY|ctr[1]~12 (
+// Equation(s):
+// \DUMMY|ctr[1]~12_combout  = (\DUMMY|ctr [1] & (\DUMMY|ctr [0] $ (VCC))) # (!\DUMMY|ctr [1] & (\DUMMY|ctr [0] & VCC))
+// \DUMMY|ctr[1]~13  = CARRY((\DUMMY|ctr [1] & \DUMMY|ctr [0]))
+
+	.dataa(\DUMMY|ctr [1]),
+	.datab(\DUMMY|ctr [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|ctr[1]~12_combout ),
+	.cout(\DUMMY|ctr[1]~13 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[1]~12 .lut_mask = 16'h6688;
+defparam \DUMMY|ctr[1]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N7
+dffeas \DUMMY|ctr[1] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[1]~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[1] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N8
+cycloneiii_lcell_comb \DUMMY|ctr[2]~14 (
+// Equation(s):
+// \DUMMY|ctr[2]~14_combout  = (\DUMMY|ctr [2] & (!\DUMMY|ctr[1]~13 )) # (!\DUMMY|ctr [2] & ((\DUMMY|ctr[1]~13 ) # (GND)))
+// \DUMMY|ctr[2]~15  = CARRY((!\DUMMY|ctr[1]~13 ) # (!\DUMMY|ctr [2]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[1]~13 ),
+	.combout(\DUMMY|ctr[2]~14_combout ),
+	.cout(\DUMMY|ctr[2]~15 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[2]~14 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[2]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N9
+dffeas \DUMMY|ctr[2] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[2]~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[2] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N10
+cycloneiii_lcell_comb \DUMMY|ctr[3]~16 (
+// Equation(s):
+// \DUMMY|ctr[3]~16_combout  = (\DUMMY|ctr [3] & (\DUMMY|ctr[2]~15  $ (GND))) # (!\DUMMY|ctr [3] & (!\DUMMY|ctr[2]~15  & VCC))
+// \DUMMY|ctr[3]~17  = CARRY((\DUMMY|ctr [3] & !\DUMMY|ctr[2]~15 ))
+
+	.dataa(\DUMMY|ctr [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[2]~15 ),
+	.combout(\DUMMY|ctr[3]~16_combout ),
+	.cout(\DUMMY|ctr[3]~17 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[3]~16 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[3]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N11
+dffeas \DUMMY|ctr[3] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[3]~16_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[3] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N12
+cycloneiii_lcell_comb \DUMMY|ctr[4]~18 (
+// Equation(s):
+// \DUMMY|ctr[4]~18_combout  = (\DUMMY|ctr [4] & (!\DUMMY|ctr[3]~17 )) # (!\DUMMY|ctr [4] & ((\DUMMY|ctr[3]~17 ) # (GND)))
+// \DUMMY|ctr[4]~19  = CARRY((!\DUMMY|ctr[3]~17 ) # (!\DUMMY|ctr [4]))
+
+	.dataa(\DUMMY|ctr [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[3]~17 ),
+	.combout(\DUMMY|ctr[4]~18_combout ),
+	.cout(\DUMMY|ctr[4]~19 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[4]~18 .lut_mask = 16'h5A5F;
+defparam \DUMMY|ctr[4]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N13
+dffeas \DUMMY|ctr[4] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[4]~18_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[4] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N8
+cycloneiii_lcell_comb \DUMMY|wraddr[4]~0 (
+// Equation(s):
+// \DUMMY|wraddr[4]~0_combout  = (\SW[0]~input_o  & (\DUMMY|ctr [4] $ (VCC))) # (!\SW[0]~input_o  & (\DUMMY|ctr [4] & VCC))
+// \DUMMY|wraddr[4]~1  = CARRY((\SW[0]~input_o  & \DUMMY|ctr [4]))
+
+	.dataa(\SW[0]~input_o ),
+	.datab(\DUMMY|ctr [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|wraddr[4]~0_combout ),
+	.cout(\DUMMY|wraddr[4]~1 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[4]~0 .lut_mask = 16'h6688;
+defparam \DUMMY|wraddr[4]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N14
+cycloneiii_lcell_comb \DUMMY|ctr[5]~20 (
+// Equation(s):
+// \DUMMY|ctr[5]~20_combout  = (\DUMMY|ctr [5] & (\DUMMY|ctr[4]~19  $ (GND))) # (!\DUMMY|ctr [5] & (!\DUMMY|ctr[4]~19  & VCC))
+// \DUMMY|ctr[5]~21  = CARRY((\DUMMY|ctr [5] & !\DUMMY|ctr[4]~19 ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[4]~19 ),
+	.combout(\DUMMY|ctr[5]~20_combout ),
+	.cout(\DUMMY|ctr[5]~21 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[5]~20 .lut_mask = 16'hC30C;
+defparam \DUMMY|ctr[5]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N15
+dffeas \DUMMY|ctr[5] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[5]~20_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[5] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N10
+cycloneiii_lcell_comb \DUMMY|wraddr[5]~2 (
+// Equation(s):
+// \DUMMY|wraddr[5]~2_combout  = (\DUMMY|ctr [5] & ((\SW[1]~input_o  & (\DUMMY|wraddr[4]~1  & VCC)) # (!\SW[1]~input_o  & (!\DUMMY|wraddr[4]~1 )))) # (!\DUMMY|ctr [5] & ((\SW[1]~input_o  & (!\DUMMY|wraddr[4]~1 )) # (!\SW[1]~input_o  & ((\DUMMY|wraddr[4]~1 ) 
+// # (GND)))))
+// \DUMMY|wraddr[5]~3  = CARRY((\DUMMY|ctr [5] & (!\SW[1]~input_o  & !\DUMMY|wraddr[4]~1 )) # (!\DUMMY|ctr [5] & ((!\DUMMY|wraddr[4]~1 ) # (!\SW[1]~input_o ))))
+
+	.dataa(\DUMMY|ctr [5]),
+	.datab(\SW[1]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[4]~1 ),
+	.combout(\DUMMY|wraddr[5]~2_combout ),
+	.cout(\DUMMY|wraddr[5]~3 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[5]~2 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[5]~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N16
+cycloneiii_lcell_comb \DUMMY|ctr[6]~22 (
+// Equation(s):
+// \DUMMY|ctr[6]~22_combout  = (\DUMMY|ctr [6] & (!\DUMMY|ctr[5]~21 )) # (!\DUMMY|ctr [6] & ((\DUMMY|ctr[5]~21 ) # (GND)))
+// \DUMMY|ctr[6]~23  = CARRY((!\DUMMY|ctr[5]~21 ) # (!\DUMMY|ctr [6]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[5]~21 ),
+	.combout(\DUMMY|ctr[6]~22_combout ),
+	.cout(\DUMMY|ctr[6]~23 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[6]~22 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[6]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N17
+dffeas \DUMMY|ctr[6] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[6]~22_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[6] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N12
+cycloneiii_lcell_comb \DUMMY|wraddr[6]~4 (
+// Equation(s):
+// \DUMMY|wraddr[6]~4_combout  = ((\DUMMY|ctr [6] $ (\SW[2]~input_o  $ (!\DUMMY|wraddr[5]~3 )))) # (GND)
+// \DUMMY|wraddr[6]~5  = CARRY((\DUMMY|ctr [6] & ((\SW[2]~input_o ) # (!\DUMMY|wraddr[5]~3 ))) # (!\DUMMY|ctr [6] & (\SW[2]~input_o  & !\DUMMY|wraddr[5]~3 )))
+
+	.dataa(\DUMMY|ctr [6]),
+	.datab(\SW[2]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[5]~3 ),
+	.combout(\DUMMY|wraddr[6]~4_combout ),
+	.cout(\DUMMY|wraddr[6]~5 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[6]~4 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[6]~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N18
+cycloneiii_lcell_comb \DUMMY|ctr[7]~24 (
+// Equation(s):
+// \DUMMY|ctr[7]~24_combout  = (\DUMMY|ctr [7] & (\DUMMY|ctr[6]~23  $ (GND))) # (!\DUMMY|ctr [7] & (!\DUMMY|ctr[6]~23  & VCC))
+// \DUMMY|ctr[7]~25  = CARRY((\DUMMY|ctr [7] & !\DUMMY|ctr[6]~23 ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[6]~23 ),
+	.combout(\DUMMY|ctr[7]~24_combout ),
+	.cout(\DUMMY|ctr[7]~25 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[7]~24 .lut_mask = 16'hC30C;
+defparam \DUMMY|ctr[7]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N19
+dffeas \DUMMY|ctr[7] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[7]~24_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[7] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N14
+cycloneiii_lcell_comb \DUMMY|wraddr[7]~6 (
+// Equation(s):
+// \DUMMY|wraddr[7]~6_combout  = (\DUMMY|ctr [7] & ((\SW[3]~input_o  & (\DUMMY|wraddr[6]~5  & VCC)) # (!\SW[3]~input_o  & (!\DUMMY|wraddr[6]~5 )))) # (!\DUMMY|ctr [7] & ((\SW[3]~input_o  & (!\DUMMY|wraddr[6]~5 )) # (!\SW[3]~input_o  & ((\DUMMY|wraddr[6]~5 ) 
+// # (GND)))))
+// \DUMMY|wraddr[7]~7  = CARRY((\DUMMY|ctr [7] & (!\SW[3]~input_o  & !\DUMMY|wraddr[6]~5 )) # (!\DUMMY|ctr [7] & ((!\DUMMY|wraddr[6]~5 ) # (!\SW[3]~input_o ))))
+
+	.dataa(\DUMMY|ctr [7]),
+	.datab(\SW[3]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[6]~5 ),
+	.combout(\DUMMY|wraddr[7]~6_combout ),
+	.cout(\DUMMY|wraddr[7]~7 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[7]~6 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[7]~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N20
+cycloneiii_lcell_comb \DUMMY|ctr[8]~26 (
+// Equation(s):
+// \DUMMY|ctr[8]~26_combout  = (\DUMMY|ctr [8] & (!\DUMMY|ctr[7]~25 )) # (!\DUMMY|ctr [8] & ((\DUMMY|ctr[7]~25 ) # (GND)))
+// \DUMMY|ctr[8]~27  = CARRY((!\DUMMY|ctr[7]~25 ) # (!\DUMMY|ctr [8]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[7]~25 ),
+	.combout(\DUMMY|ctr[8]~26_combout ),
+	.cout(\DUMMY|ctr[8]~27 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[8]~26 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[8]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N21
+dffeas \DUMMY|ctr[8] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[8]~26_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[8] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N16
+cycloneiii_lcell_comb \DUMMY|wraddr[8]~8 (
+// Equation(s):
+// \DUMMY|wraddr[8]~8_combout  = ((\SW[4]~input_o  $ (\DUMMY|ctr [8] $ (!\DUMMY|wraddr[7]~7 )))) # (GND)
+// \DUMMY|wraddr[8]~9  = CARRY((\SW[4]~input_o  & ((\DUMMY|ctr [8]) # (!\DUMMY|wraddr[7]~7 ))) # (!\SW[4]~input_o  & (\DUMMY|ctr [8] & !\DUMMY|wraddr[7]~7 )))
+
+	.dataa(\SW[4]~input_o ),
+	.datab(\DUMMY|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[7]~7 ),
+	.combout(\DUMMY|wraddr[8]~8_combout ),
+	.cout(\DUMMY|wraddr[8]~9 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[8]~8 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[8]~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N22
+cycloneiii_lcell_comb \DUMMY|ctr[9]~28 (
+// Equation(s):
+// \DUMMY|ctr[9]~28_combout  = (\DUMMY|ctr [9] & (\DUMMY|ctr[8]~27  $ (GND))) # (!\DUMMY|ctr [9] & (!\DUMMY|ctr[8]~27  & VCC))
+// \DUMMY|ctr[9]~29  = CARRY((\DUMMY|ctr [9] & !\DUMMY|ctr[8]~27 ))
+
+	.dataa(\DUMMY|ctr [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[8]~27 ),
+	.combout(\DUMMY|ctr[9]~28_combout ),
+	.cout(\DUMMY|ctr[9]~29 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[9]~28 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[9]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N23
+dffeas \DUMMY|ctr[9] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[9]~28_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[9] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N18
+cycloneiii_lcell_comb \DUMMY|wraddr[9]~10 (
+// Equation(s):
+// \DUMMY|wraddr[9]~10_combout  = (\DUMMY|ctr [9] & ((\SW[5]~input_o  & (\DUMMY|wraddr[8]~9  & VCC)) # (!\SW[5]~input_o  & (!\DUMMY|wraddr[8]~9 )))) # (!\DUMMY|ctr [9] & ((\SW[5]~input_o  & (!\DUMMY|wraddr[8]~9 )) # (!\SW[5]~input_o  & ((\DUMMY|wraddr[8]~9 ) 
+// # (GND)))))
+// \DUMMY|wraddr[9]~11  = CARRY((\DUMMY|ctr [9] & (!\SW[5]~input_o  & !\DUMMY|wraddr[8]~9 )) # (!\DUMMY|ctr [9] & ((!\DUMMY|wraddr[8]~9 ) # (!\SW[5]~input_o ))))
+
+	.dataa(\DUMMY|ctr [9]),
+	.datab(\SW[5]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[8]~9 ),
+	.combout(\DUMMY|wraddr[9]~10_combout ),
+	.cout(\DUMMY|wraddr[9]~11 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[9]~10 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[9]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N24
+cycloneiii_lcell_comb \DUMMY|ctr[10]~30 (
+// Equation(s):
+// \DUMMY|ctr[10]~30_combout  = (\DUMMY|ctr [10] & (!\DUMMY|ctr[9]~29 )) # (!\DUMMY|ctr [10] & ((\DUMMY|ctr[9]~29 ) # (GND)))
+// \DUMMY|ctr[10]~31  = CARRY((!\DUMMY|ctr[9]~29 ) # (!\DUMMY|ctr [10]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[9]~29 ),
+	.combout(\DUMMY|ctr[10]~30_combout ),
+	.cout(\DUMMY|ctr[10]~31 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[10]~30 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[10]~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N25
+dffeas \DUMMY|ctr[10] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[10]~30_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[10] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N20
+cycloneiii_lcell_comb \DUMMY|wraddr[10]~12 (
+// Equation(s):
+// \DUMMY|wraddr[10]~12_combout  = ((\DUMMY|ctr [10] $ (\SW[6]~input_o  $ (!\DUMMY|wraddr[9]~11 )))) # (GND)
+// \DUMMY|wraddr[10]~13  = CARRY((\DUMMY|ctr [10] & ((\SW[6]~input_o ) # (!\DUMMY|wraddr[9]~11 ))) # (!\DUMMY|ctr [10] & (\SW[6]~input_o  & !\DUMMY|wraddr[9]~11 )))
+
+	.dataa(\DUMMY|ctr [10]),
+	.datab(\SW[6]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[9]~11 ),
+	.combout(\DUMMY|wraddr[10]~12_combout ),
+	.cout(\DUMMY|wraddr[10]~13 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[10]~12 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[10]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N26
+cycloneiii_lcell_comb \DUMMY|ctr[11]~32 (
+// Equation(s):
+// \DUMMY|ctr[11]~32_combout  = (\DUMMY|ctr [11] & (\DUMMY|ctr[10]~31  $ (GND))) # (!\DUMMY|ctr [11] & (!\DUMMY|ctr[10]~31  & VCC))
+// \DUMMY|ctr[11]~33  = CARRY((\DUMMY|ctr [11] & !\DUMMY|ctr[10]~31 ))
+
+	.dataa(\DUMMY|ctr [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[10]~31 ),
+	.combout(\DUMMY|ctr[11]~32_combout ),
+	.cout(\DUMMY|ctr[11]~33 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[11]~32 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[11]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N27
+dffeas \DUMMY|ctr[11] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[11]~32_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[11] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N22
+cycloneiii_lcell_comb \DUMMY|wraddr[11]~14 (
+// Equation(s):
+// \DUMMY|wraddr[11]~14_combout  = (\SW[7]~input_o  & ((\DUMMY|ctr [11] & (\DUMMY|wraddr[10]~13  & VCC)) # (!\DUMMY|ctr [11] & (!\DUMMY|wraddr[10]~13 )))) # (!\SW[7]~input_o  & ((\DUMMY|ctr [11] & (!\DUMMY|wraddr[10]~13 )) # (!\DUMMY|ctr [11] & 
+// ((\DUMMY|wraddr[10]~13 ) # (GND)))))
+// \DUMMY|wraddr[11]~15  = CARRY((\SW[7]~input_o  & (!\DUMMY|ctr [11] & !\DUMMY|wraddr[10]~13 )) # (!\SW[7]~input_o  & ((!\DUMMY|wraddr[10]~13 ) # (!\DUMMY|ctr [11]))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\DUMMY|ctr [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[10]~13 ),
+	.combout(\DUMMY|wraddr[11]~14_combout ),
+	.cout(\DUMMY|wraddr[11]~15 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[11]~14 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[11]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N28
+cycloneiii_lcell_comb \DUMMY|ctr[12]~34 (
+// Equation(s):
+// \DUMMY|ctr[12]~34_combout  = \DUMMY|ctr[11]~33  $ (\DUMMY|ctr [12])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\DUMMY|ctr [12]),
+	.cin(\DUMMY|ctr[11]~33 ),
+	.combout(\DUMMY|ctr[12]~34_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|ctr[12]~34 .lut_mask = 16'h0FF0;
+defparam \DUMMY|ctr[12]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N29
+dffeas \DUMMY|ctr[12] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[12]~34_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[12] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N24
+cycloneiii_lcell_comb \DUMMY|wraddr[12]~16 (
+// Equation(s):
+// \DUMMY|wraddr[12]~16_combout  = \SW[8]~input_o  $ (\DUMMY|wraddr[11]~15  $ (!\DUMMY|ctr [12]))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\DUMMY|ctr [12]),
+	.cin(\DUMMY|wraddr[11]~15 ),
+	.combout(\DUMMY|wraddr[12]~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|wraddr[12]~16 .lut_mask = 16'h5AA5;
+defparam \DUMMY|wraddr[12]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y21_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~0_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N3
+dffeas \SPI_ADC|data_from_adc[6] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N24
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[5]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[5]~feeder_combout  = \SPI_ADC|shift_reg [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [5]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N25
+dffeas \SPI_ADC|data_from_adc[5] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N16
+cycloneiii_lcell_comb \DUMMY|Add0~12 (
+// Equation(s):
+// \DUMMY|Add0~12_combout  = ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] $ (\SPI_ADC|data_from_adc [6] $ (\DUMMY|Add0~11 )))) # (GND)
+// \DUMMY|Add0~13  = CARRY((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] & (\SPI_ADC|data_from_adc [6] & !\DUMMY|Add0~11 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] & ((\SPI_ADC|data_from_adc [6]) # (!\DUMMY|Add0~11 ))))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6]),
+	.datab(\SPI_ADC|data_from_adc [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~11 ),
+	.combout(\DUMMY|Add0~12_combout ),
+	.cout(\DUMMY|Add0~13 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~12 .lut_mask = 16'h964D;
+defparam \DUMMY|Add0~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y20_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~12_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N0
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[4]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[4]~feeder_combout  = \SPI_ADC|shift_reg [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N1
+dffeas \SPI_ADC|data_from_adc[4] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N14
+cycloneiii_lcell_comb \DUMMY|Add0~10 (
+// Equation(s):
+// \DUMMY|Add0~10_combout  = (\SPI_ADC|data_from_adc [5] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (!\DUMMY|Add0~9 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (\DUMMY|Add0~9  & VCC)))) # (!\SPI_ADC|data_from_adc [5] 
+// & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & ((\DUMMY|Add0~9 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (!\DUMMY|Add0~9 ))))
+// \DUMMY|Add0~11  = CARRY((\SPI_ADC|data_from_adc [5] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & !\DUMMY|Add0~9 )) # (!\SPI_ADC|data_from_adc [5] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5]) # (!\DUMMY|Add0~9 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [5]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~9 ),
+	.combout(\DUMMY|Add0~10_combout ),
+	.cout(\DUMMY|Add0~11 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~10 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y22_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~10_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N12
+cycloneiii_lcell_comb \DUMMY|Add0~8 (
+// Equation(s):
+// \DUMMY|Add0~8_combout  = ((\SPI_ADC|data_from_adc [4] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] $ (\DUMMY|Add0~7 )))) # (GND)
+// \DUMMY|Add0~9  = CARRY((\SPI_ADC|data_from_adc [4] & ((!\DUMMY|Add0~7 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4]))) # (!\SPI_ADC|data_from_adc [4] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] & !\DUMMY|Add0~7 )))
+
+	.dataa(\SPI_ADC|data_from_adc [4]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~7 ),
+	.combout(\DUMMY|Add0~8_combout ),
+	.cout(\DUMMY|Add0~9 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~8 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y21_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~8_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N3
+dffeas \SPI_ADC|data_from_adc[3] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N4
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[2]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[2]~feeder_combout  = \SPI_ADC|shift_reg [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [2]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N5
+dffeas \SPI_ADC|data_from_adc[2] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N10
+cycloneiii_lcell_comb \DUMMY|Add0~6 (
+// Equation(s):
+// \DUMMY|Add0~6_combout  = (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & ((\SPI_ADC|data_from_adc [3] & (!\DUMMY|Add0~5 )) # (!\SPI_ADC|data_from_adc [3] & ((\DUMMY|Add0~5 ) # (GND))))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b 
+// [3] & ((\SPI_ADC|data_from_adc [3] & (\DUMMY|Add0~5  & VCC)) # (!\SPI_ADC|data_from_adc [3] & (!\DUMMY|Add0~5 ))))
+// \DUMMY|Add0~7  = CARRY((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & ((!\DUMMY|Add0~5 ) # (!\SPI_ADC|data_from_adc [3]))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & (!\SPI_ADC|data_from_adc [3] & !\DUMMY|Add0~5 )))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3]),
+	.datab(\SPI_ADC|data_from_adc [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~5 ),
+	.combout(\DUMMY|Add0~6_combout ),
+	.cout(\DUMMY|Add0~7 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~6 .lut_mask = 16'h692B;
+defparam \DUMMY|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y22_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~6_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N7
+dffeas \SPI_ADC|data_from_adc[1] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N8
+cycloneiii_lcell_comb \DUMMY|Add0~4 (
+// Equation(s):
+// \DUMMY|Add0~4_combout  = ((\SPI_ADC|data_from_adc [2] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] $ (\DUMMY|Add0~3 )))) # (GND)
+// \DUMMY|Add0~5  = CARRY((\SPI_ADC|data_from_adc [2] & ((!\DUMMY|Add0~3 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2]))) # (!\SPI_ADC|data_from_adc [2] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] & !\DUMMY|Add0~3 )))
+
+	.dataa(\SPI_ADC|data_from_adc [2]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~3 ),
+	.combout(\DUMMY|Add0~4_combout ),
+	.cout(\DUMMY|Add0~5 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~4 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y20_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~4_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N6
+cycloneiii_lcell_comb \DUMMY|Add0~2 (
+// Equation(s):
+// \DUMMY|Add0~2_combout  = (\SPI_ADC|data_from_adc [1] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (!\DUMMY|Add0~1 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (\DUMMY|Add0~1  & VCC)))) # (!\SPI_ADC|data_from_adc [1] 
+// & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & ((\DUMMY|Add0~1 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (!\DUMMY|Add0~1 ))))
+// \DUMMY|Add0~3  = CARRY((\SPI_ADC|data_from_adc [1] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & !\DUMMY|Add0~1 )) # (!\SPI_ADC|data_from_adc [1] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1]) # (!\DUMMY|Add0~1 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [1]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~1 ),
+	.combout(\DUMMY|Add0~2_combout ),
+	.cout(\DUMMY|Add0~3 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~2 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y23_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~2_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N0
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[0]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[0]~feeder_combout  = \SPI_ADC|shift_reg [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N1
+dffeas \SPI_ADC|data_from_adc[0] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N4
+cycloneiii_lcell_comb \DUMMY|Add0~0 (
+// Equation(s):
+// \DUMMY|Add0~0_combout  = (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & (\SPI_ADC|data_from_adc [0] & VCC)) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & (\SPI_ADC|data_from_adc [0] $ (VCC)))
+// \DUMMY|Add0~1  = CARRY((!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & \SPI_ADC|data_from_adc [0]))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0]),
+	.datab(\SPI_ADC|data_from_adc [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|Add0~0_combout ),
+	.cout(\DUMMY|Add0~1 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~0 .lut_mask = 16'h9944;
+defparam \DUMMY|Add0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N18
+cycloneiii_lcell_comb \DUMMY|Add0~14 (
+// Equation(s):
+// \DUMMY|Add0~14_combout  = (\SPI_ADC|data_from_adc [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (!\DUMMY|Add0~13 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (\DUMMY|Add0~13  & VCC)))) # (!\SPI_ADC|data_from_adc 
+// [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & ((\DUMMY|Add0~13 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (!\DUMMY|Add0~13 ))))
+// \DUMMY|Add0~15  = CARRY((\SPI_ADC|data_from_adc [7] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & !\DUMMY|Add0~13 )) # (!\SPI_ADC|data_from_adc [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7]) # (!\DUMMY|Add0~13 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [7]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~13 ),
+	.combout(\DUMMY|Add0~14_combout ),
+	.cout(\DUMMY|Add0~15 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~14 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N20
+cycloneiii_lcell_comb \DUMMY|Add0~16 (
+// Equation(s):
+// \DUMMY|Add0~16_combout  = ((\SPI_ADC|data_from_adc [8] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] $ (\DUMMY|Add0~15 )))) # (GND)
+// \DUMMY|Add0~17  = CARRY((\SPI_ADC|data_from_adc [8] & ((!\DUMMY|Add0~15 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]))) # (!\SPI_ADC|data_from_adc [8] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] & !\DUMMY|Add0~15 )))
+
+	.dataa(\SPI_ADC|data_from_adc [8]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~15 ),
+	.combout(\DUMMY|Add0~16_combout ),
+	.cout(\DUMMY|Add0~17 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~16 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N22
+cycloneiii_lcell_comb \DUMMY|Add0~18 (
+// Equation(s):
+// \DUMMY|Add0~18_combout  = \SPI_ADC|data_from_adc [9] $ (\DUMMY|Add0~17  $ (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|data_from_adc [9]),
+	.datac(gnd),
+	.datad(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]),
+	.cin(\DUMMY|Add0~17 ),
+	.combout(\DUMMY|Add0~18_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|Add0~18 .lut_mask = 16'h3CC3;
+defparam \DUMMY|Add0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N26
+cycloneiii_lcell_comb \DUMMY|Add3~0 (
+// Equation(s):
+// \DUMMY|Add3~0_combout  = \DUMMY|Add0~14_combout  $ (VCC)
+// \DUMMY|Add3~1  = CARRY(\DUMMY|Add0~14_combout )
+
+	.dataa(gnd),
+	.datab(\DUMMY|Add0~14_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|Add3~0_combout ),
+	.cout(\DUMMY|Add3~1 ));
+// synopsys translate_off
+defparam \DUMMY|Add3~0 .lut_mask = 16'h33CC;
+defparam \DUMMY|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N28
+cycloneiii_lcell_comb \DUMMY|Add3~2 (
+// Equation(s):
+// \DUMMY|Add3~2_combout  = (\DUMMY|Add0~16_combout  & (!\DUMMY|Add3~1 )) # (!\DUMMY|Add0~16_combout  & ((\DUMMY|Add3~1 ) # (GND)))
+// \DUMMY|Add3~3  = CARRY((!\DUMMY|Add3~1 ) # (!\DUMMY|Add0~16_combout ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|Add0~16_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add3~1 ),
+	.combout(\DUMMY|Add3~2_combout ),
+	.cout(\DUMMY|Add3~3 ));
+// synopsys translate_off
+defparam \DUMMY|Add3~2 .lut_mask = 16'h3C3F;
+defparam \DUMMY|Add3~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N30
+cycloneiii_lcell_comb \DUMMY|Add3~4 (
+// Equation(s):
+// \DUMMY|Add3~4_combout  = \DUMMY|Add0~18_combout  $ (\DUMMY|Add3~3 )
+
+	.dataa(\DUMMY|Add0~18_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\DUMMY|Add3~3 ),
+	.combout(\DUMMY|Add3~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|Add3~4 .lut_mask = 16'h5A5A;
+defparam \DUMMY|Add3~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y23_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~4_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 8;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 8;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: M9K_X25_Y19_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~2_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N27
+dffeas \DUMMY|data_out[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[7] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N9
+dffeas \DUMMY|data_out[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[2] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N5
+dffeas \DUMMY|data_out[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[0] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N28
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~13 (
+// Equation(s):
+// \SPI_DAC|shift_reg~13_combout  = (!\SPI_DAC|dac_cs~q  & (\DUMMY|data_out [0] & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\DUMMY|data_out [0]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~13 .lut_mask = 16'h5000;
+defparam \SPI_DAC|shift_reg~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N29
+dffeas \SPI_DAC|shift_reg[2] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N7
+dffeas \DUMMY|data_out[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[1] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N26
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~12 (
+// Equation(s):
+// \SPI_DAC|shift_reg~12_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [2])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [1]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [2]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [2]),
+	.datac(\DUMMY|data_out [1]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~12 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N27
+dffeas \SPI_DAC|shift_reg[3] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N4
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~11 (
+// Equation(s):
+// \SPI_DAC|shift_reg~11_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q  & ((\SPI_DAC|shift_reg [3]))) # (!\SPI_DAC|dac_cs~q  & (\DUMMY|data_out [2])))) # (!\SPI_DAC|dac_start~q  & (((\SPI_DAC|shift_reg [3]))))
+
+	.dataa(\DUMMY|data_out [2]),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(\SPI_DAC|shift_reg [3]),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~11 .lut_mask = 16'hF0B8;
+defparam \SPI_DAC|shift_reg~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N5
+dffeas \SPI_DAC|shift_reg[4] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N11
+dffeas \DUMMY|data_out[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[3] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N2
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~10 (
+// Equation(s):
+// \SPI_DAC|shift_reg~10_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [4])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [3]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [4]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [4]),
+	.datac(\DUMMY|data_out [3]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~10 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N3
+dffeas \SPI_DAC|shift_reg[5] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N13
+dffeas \DUMMY|data_out[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[4] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N0
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~9 (
+// Equation(s):
+// \SPI_DAC|shift_reg~9_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [5])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [4]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [5]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [5]),
+	.datac(\DUMMY|data_out [4]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~9 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N1
+dffeas \SPI_DAC|shift_reg[6] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N15
+dffeas \DUMMY|data_out[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[5] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N18
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~8 (
+// Equation(s):
+// \SPI_DAC|shift_reg~8_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [6])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [5]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [6]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [6]),
+	.datac(\DUMMY|data_out [5]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~8 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N19
+dffeas \SPI_DAC|shift_reg[7] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N17
+dffeas \DUMMY|data_out[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[6] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N8
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~7 (
+// Equation(s):
+// \SPI_DAC|shift_reg~7_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [7])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [6]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [7]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [7]),
+	.datac(\DUMMY|data_out [6]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~7 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N9
+dffeas \SPI_DAC|shift_reg[8] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N14
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~6 (
+// Equation(s):
+// \SPI_DAC|shift_reg~6_combout  = (\SPI_DAC|dac_cs~q  & (((\SPI_DAC|shift_reg [8])))) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & (\DUMMY|data_out [7])) # (!\SPI_DAC|dac_start~q  & ((\SPI_DAC|shift_reg [8])))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\DUMMY|data_out [7]),
+	.datac(\SPI_DAC|shift_reg [8]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~6 .lut_mask = 16'hE4F0;
+defparam \SPI_DAC|shift_reg~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N15
+dffeas \SPI_DAC|shift_reg[9] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N29
+dffeas \DUMMY|data_out[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add3~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[8] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N12
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~5 (
+// Equation(s):
+// \SPI_DAC|shift_reg~5_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [9])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [8]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [9]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [9]),
+	.datac(\DUMMY|data_out [8]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~5 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N13
+dffeas \SPI_DAC|shift_reg[10] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[10] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N24
+cycloneiii_lcell_comb \DUMMY|data_out[9]~0 (
+// Equation(s):
+// \DUMMY|data_out[9]~0_combout  = !\DUMMY|Add3~4_combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\DUMMY|Add3~4_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|data_out[9]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|data_out[9]~0 .lut_mask = 16'h0F0F;
+defparam \DUMMY|data_out[9]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N25
+dffeas \DUMMY|data_out[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|data_out[9]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[9] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N26
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~4 (
+// Equation(s):
+// \SPI_DAC|shift_reg~4_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [10])) # (!\SPI_DAC|dac_cs~q  & ((\DUMMY|data_out [9]))))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [10]))
+
+	.dataa(\SPI_DAC|shift_reg [10]),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(\DUMMY|data_out [9]),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~4 .lut_mask = 16'hAAE2;
+defparam \SPI_DAC|shift_reg~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N27
+dffeas \SPI_DAC|shift_reg[11] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[11] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N22
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~3 (
+// Equation(s):
+// \SPI_DAC|shift_reg~3_combout  = (\SPI_DAC|shift_reg [11]) # ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [11]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~3 .lut_mask = 16'hF5F0;
+defparam \SPI_DAC|shift_reg~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N23
+dffeas \SPI_DAC|shift_reg[12] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[12] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N30
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~2 (
+// Equation(s):
+// \SPI_DAC|shift_reg~2_combout  = (\SPI_DAC|shift_reg [12] & ((\SPI_DAC|dac_cs~q ) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [12]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~2 .lut_mask = 16'hA0F0;
+defparam \SPI_DAC|shift_reg~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N31
+dffeas \SPI_DAC|shift_reg[13] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[13] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N10
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~1 (
+// Equation(s):
+// \SPI_DAC|shift_reg~1_combout  = (\SPI_DAC|shift_reg [13]) # ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [13]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~1 .lut_mask = 16'hF5F0;
+defparam \SPI_DAC|shift_reg~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N11
+dffeas \SPI_DAC|shift_reg[14] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[14] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N16
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~0 (
+// Equation(s):
+// \SPI_DAC|shift_reg~0_combout  = (\SPI_DAC|shift_reg [14] & ((\SPI_DAC|dac_cs~q ) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(\SPI_DAC|shift_reg [14]),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~0 .lut_mask = 16'hBB00;
+defparam \SPI_DAC|shift_reg~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N17
+dffeas \SPI_DAC|shift_reg[15] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[15] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N14
+cycloneiii_lcell_comb \SCK~0 (
+// Equation(s):
+// \SCK~0_combout  = (\SPI_ADC|clk_1MHz~q  & (!\SPI_DAC|clk_1MHz~q  & ((\SPI_DAC|dac_cs~q )))) # (!\SPI_ADC|clk_1MHz~q  & ((\SPI_ADC|adc_cs~q ) # ((!\SPI_DAC|clk_1MHz~q  & \SPI_DAC|dac_cs~q ))))
+
+	.dataa(\SPI_ADC|clk_1MHz~q ),
+	.datab(\SPI_DAC|clk_1MHz~q ),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SCK~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCK~0 .lut_mask = 16'h7350;
+defparam \SCK~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N28
+cycloneiii_lcell_comb \SPI_DAC|Equal2~0 (
+// Equation(s):
+// \SPI_DAC|Equal2~0_combout  = (!\SPI_DAC|state [4]) # (!\SPI_DAC|Equal1~0_combout )
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal2~0 .lut_mask = 16'h3F3F;
+defparam \SPI_DAC|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N29
+dffeas \SPI_DAC|dac_ld (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|Equal2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_ld~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_ld .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_ld .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N1
+cycloneiii_io_ibuf \SW[9]~input (
+	.i(SW[9]),
+	.ibar(gnd),
+	.o(\SW[9]~input_o ));
+// synopsys translate_off
+defparam \SW[9]~input .bus_hold = "false";
+defparam \SW[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N8
+cycloneiii_lcell_comb \SPI_ADC|Selector6~0 (
+// Equation(s):
+// \SPI_ADC|Selector6~0_combout  = (\SPI_ADC|state [0]) # ((\SPI_ADC|state [1] & ((\SW[9]~input_o ))) # (!\SPI_ADC|state [1] & (\SPI_ADC|adc_start~q )))
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(\SW[9]~input_o ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~0 .lut_mask = 16'hFFCA;
+defparam \SPI_ADC|Selector6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N30
+cycloneiii_lcell_comb \SPI_ADC|Selector6~1 (
+// Equation(s):
+// \SPI_ADC|Selector6~1_combout  = (!\SPI_ADC|state [3] & (!\SPI_ADC|state [2] & (\SPI_ADC|Selector6~0_combout  & !\SPI_ADC|state [4])))
+
+	.dataa(\SPI_ADC|state [3]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|Selector6~0_combout ),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~1 .lut_mask = 16'h0010;
+defparam \SPI_ADC|Selector6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N31
+dffeas \SPI_ADC|adc_din (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Selector6~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_din~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_din .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_din .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N4
+cycloneiii_lcell_comb \PWM_DC|count[1]~9 (
+// Equation(s):
+// \PWM_DC|count[1]~9_combout  = (\PWM_DC|count [0] & (\PWM_DC|count [1] $ (VCC))) # (!\PWM_DC|count [0] & (\PWM_DC|count [1] & VCC))
+// \PWM_DC|count[1]~10  = CARRY((\PWM_DC|count [0] & \PWM_DC|count [1]))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\PWM_DC|count [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\PWM_DC|count[1]~9_combout ),
+	.cout(\PWM_DC|count[1]~10 ));
+// synopsys translate_off
+defparam \PWM_DC|count[1]~9 .lut_mask = 16'h6688;
+defparam \PWM_DC|count[1]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N5
+dffeas \PWM_DC|count[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[1]~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[1] .is_wysiwyg = "true";
+defparam \PWM_DC|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N6
+cycloneiii_lcell_comb \PWM_DC|count[2]~11 (
+// Equation(s):
+// \PWM_DC|count[2]~11_combout  = (\PWM_DC|count [2] & (!\PWM_DC|count[1]~10 )) # (!\PWM_DC|count [2] & ((\PWM_DC|count[1]~10 ) # (GND)))
+// \PWM_DC|count[2]~12  = CARRY((!\PWM_DC|count[1]~10 ) # (!\PWM_DC|count [2]))
+
+	.dataa(\PWM_DC|count [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[1]~10 ),
+	.combout(\PWM_DC|count[2]~11_combout ),
+	.cout(\PWM_DC|count[2]~12 ));
+// synopsys translate_off
+defparam \PWM_DC|count[2]~11 .lut_mask = 16'h5A5F;
+defparam \PWM_DC|count[2]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N7
+dffeas \PWM_DC|count[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[2]~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[2] .is_wysiwyg = "true";
+defparam \PWM_DC|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N8
+cycloneiii_lcell_comb \PWM_DC|count[3]~13 (
+// Equation(s):
+// \PWM_DC|count[3]~13_combout  = (\PWM_DC|count [3] & (\PWM_DC|count[2]~12  $ (GND))) # (!\PWM_DC|count [3] & (!\PWM_DC|count[2]~12  & VCC))
+// \PWM_DC|count[3]~14  = CARRY((\PWM_DC|count [3] & !\PWM_DC|count[2]~12 ))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[2]~12 ),
+	.combout(\PWM_DC|count[3]~13_combout ),
+	.cout(\PWM_DC|count[3]~14 ));
+// synopsys translate_off
+defparam \PWM_DC|count[3]~13 .lut_mask = 16'hC30C;
+defparam \PWM_DC|count[3]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N9
+dffeas \PWM_DC|count[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[3]~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[3] .is_wysiwyg = "true";
+defparam \PWM_DC|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N10
+cycloneiii_lcell_comb \PWM_DC|count[4]~15 (
+// Equation(s):
+// \PWM_DC|count[4]~15_combout  = (\PWM_DC|count [4] & (!\PWM_DC|count[3]~14 )) # (!\PWM_DC|count [4] & ((\PWM_DC|count[3]~14 ) # (GND)))
+// \PWM_DC|count[4]~16  = CARRY((!\PWM_DC|count[3]~14 ) # (!\PWM_DC|count [4]))
+
+	.dataa(\PWM_DC|count [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[3]~14 ),
+	.combout(\PWM_DC|count[4]~15_combout ),
+	.cout(\PWM_DC|count[4]~16 ));
+// synopsys translate_off
+defparam \PWM_DC|count[4]~15 .lut_mask = 16'h5A5F;
+defparam \PWM_DC|count[4]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N11
+dffeas \PWM_DC|count[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[4]~15_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[4] .is_wysiwyg = "true";
+defparam \PWM_DC|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N12
+cycloneiii_lcell_comb \PWM_DC|count[5]~17 (
+// Equation(s):
+// \PWM_DC|count[5]~17_combout  = (\PWM_DC|count [5] & (\PWM_DC|count[4]~16  $ (GND))) # (!\PWM_DC|count [5] & (!\PWM_DC|count[4]~16  & VCC))
+// \PWM_DC|count[5]~18  = CARRY((\PWM_DC|count [5] & !\PWM_DC|count[4]~16 ))
+
+	.dataa(\PWM_DC|count [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[4]~16 ),
+	.combout(\PWM_DC|count[5]~17_combout ),
+	.cout(\PWM_DC|count[5]~18 ));
+// synopsys translate_off
+defparam \PWM_DC|count[5]~17 .lut_mask = 16'hA50A;
+defparam \PWM_DC|count[5]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N13
+dffeas \PWM_DC|count[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[5]~17_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[5] .is_wysiwyg = "true";
+defparam \PWM_DC|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N14
+cycloneiii_lcell_comb \PWM_DC|count[6]~19 (
+// Equation(s):
+// \PWM_DC|count[6]~19_combout  = (\PWM_DC|count [6] & (!\PWM_DC|count[5]~18 )) # (!\PWM_DC|count [6] & ((\PWM_DC|count[5]~18 ) # (GND)))
+// \PWM_DC|count[6]~20  = CARRY((!\PWM_DC|count[5]~18 ) # (!\PWM_DC|count [6]))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[5]~18 ),
+	.combout(\PWM_DC|count[6]~19_combout ),
+	.cout(\PWM_DC|count[6]~20 ));
+// synopsys translate_off
+defparam \PWM_DC|count[6]~19 .lut_mask = 16'h3C3F;
+defparam \PWM_DC|count[6]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N15
+dffeas \PWM_DC|count[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[6]~19_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[6] .is_wysiwyg = "true";
+defparam \PWM_DC|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N16
+cycloneiii_lcell_comb \PWM_DC|count[7]~21 (
+// Equation(s):
+// \PWM_DC|count[7]~21_combout  = (\PWM_DC|count [7] & (\PWM_DC|count[6]~20  $ (GND))) # (!\PWM_DC|count [7] & (!\PWM_DC|count[6]~20  & VCC))
+// \PWM_DC|count[7]~22  = CARRY((\PWM_DC|count [7] & !\PWM_DC|count[6]~20 ))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[6]~20 ),
+	.combout(\PWM_DC|count[7]~21_combout ),
+	.cout(\PWM_DC|count[7]~22 ));
+// synopsys translate_off
+defparam \PWM_DC|count[7]~21 .lut_mask = 16'hC30C;
+defparam \PWM_DC|count[7]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N17
+dffeas \PWM_DC|count[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[7]~21_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[7] .is_wysiwyg = "true";
+defparam \PWM_DC|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N18
+cycloneiii_lcell_comb \PWM_DC|count[8]~23 (
+// Equation(s):
+// \PWM_DC|count[8]~23_combout  = (\PWM_DC|count [8] & (!\PWM_DC|count[7]~22 )) # (!\PWM_DC|count [8] & ((\PWM_DC|count[7]~22 ) # (GND)))
+// \PWM_DC|count[8]~24  = CARRY((!\PWM_DC|count[7]~22 ) # (!\PWM_DC|count [8]))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[7]~22 ),
+	.combout(\PWM_DC|count[8]~23_combout ),
+	.cout(\PWM_DC|count[8]~24 ));
+// synopsys translate_off
+defparam \PWM_DC|count[8]~23 .lut_mask = 16'h3C3F;
+defparam \PWM_DC|count[8]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N19
+dffeas \PWM_DC|count[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[8]~23_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[8] .is_wysiwyg = "true";
+defparam \PWM_DC|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N20
+cycloneiii_lcell_comb \PWM_DC|count[9]~25 (
+// Equation(s):
+// \PWM_DC|count[9]~25_combout  = \PWM_DC|count[8]~24  $ (!\PWM_DC|count [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\PWM_DC|count [9]),
+	.cin(\PWM_DC|count[8]~24 ),
+	.combout(\PWM_DC|count[9]~25_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|count[9]~25 .lut_mask = 16'hF00F;
+defparam \PWM_DC|count[9]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N21
+dffeas \PWM_DC|count[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[9]~25_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[9] .is_wysiwyg = "true";
+defparam \PWM_DC|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N25
+dffeas \PWM_DC|d[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[9] .is_wysiwyg = "true";
+defparam \PWM_DC|d[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N23
+dffeas \PWM_DC|d[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[8] .is_wysiwyg = "true";
+defparam \PWM_DC|d[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N21
+dffeas \PWM_DC|d[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[7] .is_wysiwyg = "true";
+defparam \PWM_DC|d[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N19
+dffeas \PWM_DC|d[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[6] .is_wysiwyg = "true";
+defparam \PWM_DC|d[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N17
+dffeas \PWM_DC|d[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[5] .is_wysiwyg = "true";
+defparam \PWM_DC|d[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N15
+dffeas \PWM_DC|d[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[4] .is_wysiwyg = "true";
+defparam \PWM_DC|d[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N13
+dffeas \PWM_DC|d[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[3] .is_wysiwyg = "true";
+defparam \PWM_DC|d[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N11
+dffeas \PWM_DC|d[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[2] .is_wysiwyg = "true";
+defparam \PWM_DC|d[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N9
+dffeas \PWM_DC|d[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[1] .is_wysiwyg = "true";
+defparam \PWM_DC|d[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N7
+dffeas \PWM_DC|d[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[0] .is_wysiwyg = "true";
+defparam \PWM_DC|d[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N6
+cycloneiii_lcell_comb \PWM_DC|LessThan0~1 (
+// Equation(s):
+// \PWM_DC|LessThan0~1_cout  = CARRY((!\PWM_DC|d [0] & \PWM_DC|count [0]))
+
+	.dataa(\PWM_DC|d [0]),
+	.datab(\PWM_DC|count [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~1_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~1 .lut_mask = 16'h0044;
+defparam \PWM_DC|LessThan0~1 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N8
+cycloneiii_lcell_comb \PWM_DC|LessThan0~3 (
+// Equation(s):
+// \PWM_DC|LessThan0~3_cout  = CARRY((\PWM_DC|count [1] & (\PWM_DC|d [1] & !\PWM_DC|LessThan0~1_cout )) # (!\PWM_DC|count [1] & ((\PWM_DC|d [1]) # (!\PWM_DC|LessThan0~1_cout ))))
+
+	.dataa(\PWM_DC|count [1]),
+	.datab(\PWM_DC|d [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~1_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~3_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~3 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~3 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N10
+cycloneiii_lcell_comb \PWM_DC|LessThan0~5 (
+// Equation(s):
+// \PWM_DC|LessThan0~5_cout  = CARRY((\PWM_DC|d [2] & (\PWM_DC|count [2] & !\PWM_DC|LessThan0~3_cout )) # (!\PWM_DC|d [2] & ((\PWM_DC|count [2]) # (!\PWM_DC|LessThan0~3_cout ))))
+
+	.dataa(\PWM_DC|d [2]),
+	.datab(\PWM_DC|count [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~3_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~5_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~5 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~5 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N12
+cycloneiii_lcell_comb \PWM_DC|LessThan0~7 (
+// Equation(s):
+// \PWM_DC|LessThan0~7_cout  = CARRY((\PWM_DC|d [3] & ((!\PWM_DC|LessThan0~5_cout ) # (!\PWM_DC|count [3]))) # (!\PWM_DC|d [3] & (!\PWM_DC|count [3] & !\PWM_DC|LessThan0~5_cout )))
+
+	.dataa(\PWM_DC|d [3]),
+	.datab(\PWM_DC|count [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~5_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~7_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~7 .lut_mask = 16'h002B;
+defparam \PWM_DC|LessThan0~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N14
+cycloneiii_lcell_comb \PWM_DC|LessThan0~9 (
+// Equation(s):
+// \PWM_DC|LessThan0~9_cout  = CARRY((\PWM_DC|d [4] & (\PWM_DC|count [4] & !\PWM_DC|LessThan0~7_cout )) # (!\PWM_DC|d [4] & ((\PWM_DC|count [4]) # (!\PWM_DC|LessThan0~7_cout ))))
+
+	.dataa(\PWM_DC|d [4]),
+	.datab(\PWM_DC|count [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~7_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~9_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~9 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~9 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N16
+cycloneiii_lcell_comb \PWM_DC|LessThan0~11 (
+// Equation(s):
+// \PWM_DC|LessThan0~11_cout  = CARRY((\PWM_DC|count [5] & (\PWM_DC|d [5] & !\PWM_DC|LessThan0~9_cout )) # (!\PWM_DC|count [5] & ((\PWM_DC|d [5]) # (!\PWM_DC|LessThan0~9_cout ))))
+
+	.dataa(\PWM_DC|count [5]),
+	.datab(\PWM_DC|d [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~9_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~11_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~11 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N18
+cycloneiii_lcell_comb \PWM_DC|LessThan0~13 (
+// Equation(s):
+// \PWM_DC|LessThan0~13_cout  = CARRY((\PWM_DC|count [6] & ((!\PWM_DC|LessThan0~11_cout ) # (!\PWM_DC|d [6]))) # (!\PWM_DC|count [6] & (!\PWM_DC|d [6] & !\PWM_DC|LessThan0~11_cout )))
+
+	.dataa(\PWM_DC|count [6]),
+	.datab(\PWM_DC|d [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~11_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~13_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~13 .lut_mask = 16'h002B;
+defparam \PWM_DC|LessThan0~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N20
+cycloneiii_lcell_comb \PWM_DC|LessThan0~15 (
+// Equation(s):
+// \PWM_DC|LessThan0~15_cout  = CARRY((\PWM_DC|count [7] & (\PWM_DC|d [7] & !\PWM_DC|LessThan0~13_cout )) # (!\PWM_DC|count [7] & ((\PWM_DC|d [7]) # (!\PWM_DC|LessThan0~13_cout ))))
+
+	.dataa(\PWM_DC|count [7]),
+	.datab(\PWM_DC|d [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~13_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~15_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~15 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N22
+cycloneiii_lcell_comb \PWM_DC|LessThan0~17 (
+// Equation(s):
+// \PWM_DC|LessThan0~17_cout  = CARRY((\PWM_DC|d [8] & (\PWM_DC|count [8] & !\PWM_DC|LessThan0~15_cout )) # (!\PWM_DC|d [8] & ((\PWM_DC|count [8]) # (!\PWM_DC|LessThan0~15_cout ))))
+
+	.dataa(\PWM_DC|d [8]),
+	.datab(\PWM_DC|count [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~15_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~17_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~17 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N24
+cycloneiii_lcell_comb \PWM_DC|LessThan0~18 (
+// Equation(s):
+// \PWM_DC|LessThan0~18_combout  = (\PWM_DC|count [9] & ((\PWM_DC|LessThan0~17_cout ) # (!\PWM_DC|d [9]))) # (!\PWM_DC|count [9] & (!\PWM_DC|d [9] & \PWM_DC|LessThan0~17_cout ))
+
+	.dataa(\PWM_DC|count [9]),
+	.datab(\PWM_DC|d [9]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\PWM_DC|LessThan0~17_cout ),
+	.combout(\PWM_DC|LessThan0~18_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~18 .lut_mask = 16'hB2B2;
+defparam \PWM_DC|LessThan0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y21_N8
+cycloneiii_lcell_comb \PWM_DC|pwm_out~0 (
+// Equation(s):
+// \PWM_DC|pwm_out~0_combout  = !\PWM_DC|LessThan0~18_combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\PWM_DC|LessThan0~18_combout ),
+	.cin(gnd),
+	.combout(\PWM_DC|pwm_out~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|pwm_out~0 .lut_mask = 16'h00FF;
+defparam \PWM_DC|pwm_out~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y21_N9
+dffeas \PWM_DC|pwm_out (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|pwm_out~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|pwm_out~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|pwm_out .is_wysiwyg = "true";
+defparam \PWM_DC|pwm_out .power_up = "low";
+// synopsys translate_on
+
+assign HEX0_D[0] = \HEX0_D[0]~output_o ;
+
+assign HEX0_D[1] = \HEX0_D[1]~output_o ;
+
+assign HEX0_D[2] = \HEX0_D[2]~output_o ;
+
+assign HEX0_D[3] = \HEX0_D[3]~output_o ;
+
+assign HEX0_D[4] = \HEX0_D[4]~output_o ;
+
+assign HEX0_D[5] = \HEX0_D[5]~output_o ;
+
+assign HEX0_D[6] = \HEX0_D[6]~output_o ;
+
+assign HEX1_D[0] = \HEX1_D[0]~output_o ;
+
+assign HEX1_D[1] = \HEX1_D[1]~output_o ;
+
+assign HEX1_D[2] = \HEX1_D[2]~output_o ;
+
+assign HEX1_D[3] = \HEX1_D[3]~output_o ;
+
+assign HEX1_D[4] = \HEX1_D[4]~output_o ;
+
+assign HEX1_D[5] = \HEX1_D[5]~output_o ;
+
+assign HEX1_D[6] = \HEX1_D[6]~output_o ;
+
+assign HEX2_D[0] = \HEX2_D[0]~output_o ;
+
+assign HEX2_D[1] = \HEX2_D[1]~output_o ;
+
+assign HEX2_D[2] = \HEX2_D[2]~output_o ;
+
+assign HEX2_D[3] = \HEX2_D[3]~output_o ;
+
+assign HEX2_D[4] = \HEX2_D[4]~output_o ;
+
+assign HEX2_D[5] = \HEX2_D[5]~output_o ;
+
+assign HEX2_D[6] = \HEX2_D[6]~output_o ;
+
+assign HEX3_D[0] = \HEX3_D[0]~output_o ;
+
+assign HEX3_D[1] = \HEX3_D[1]~output_o ;
+
+assign HEX3_D[2] = \HEX3_D[2]~output_o ;
+
+assign HEX3_D[3] = \HEX3_D[3]~output_o ;
+
+assign HEX3_D[4] = \HEX3_D[4]~output_o ;
+
+assign HEX3_D[5] = \HEX3_D[5]~output_o ;
+
+assign HEX3_D[6] = \HEX3_D[6]~output_o ;
+
+assign DAC_SDI = \DAC_SDI~output_o ;
+
+assign SCK = \SCK~output_o ;
+
+assign DAC_CS = \DAC_CS~output_o ;
+
+assign DAC_LD = \DAC_LD~output_o ;
+
+assign ADC_SDI = \ADC_SDI~output_o ;
+
+assign ADC_CS = \ADC_CS~output_o ;
+
+assign LEDG[0] = \LEDG[0]~output_o ;
+
+assign LEDG[1] = \LEDG[1]~output_o ;
+
+assign LEDG[2] = \LEDG[2]~output_o ;
+
+assign LEDG[3] = \LEDG[3]~output_o ;
+
+assign LEDG[4] = \LEDG[4]~output_o ;
+
+assign LEDG[5] = \LEDG[5]~output_o ;
+
+assign LEDG[6] = \LEDG[6]~output_o ;
+
+assign LEDG[7] = \LEDG[7]~output_o ;
+
+assign LEDG[8] = \LEDG[8]~output_o ;
+
+assign LEDG[9] = \LEDG[9]~output_o ;
+
+assign PWM_OUT = \PWM_OUT~output_o ;
+
+endmodule
diff --git a/part_4/ex16/simulation/modelsim/top_6_1200mv_0c_v_slow.sdo b/part_4/ex16/simulation/modelsim/top_6_1200mv_0c_v_slow.sdo
new file mode 100755
index 0000000..8099d1e
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_6_1200mv_0c_v_slow.sdo
@@ -0,0 +1,8658 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "top")
+  (DATE "02/18/2014 18:26:56")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (670:670:670) (624:624:624))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (634:634:634) (576:576:576))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (751:751:751) (725:725:725))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (709:709:709) (677:677:677))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (709:709:709) (689:689:689))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (727:727:727) (698:698:698))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (686:686:686) (715:715:715))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (425:425:425) (456:456:456))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (428:428:428) (400:400:400))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (441:441:441) (406:406:406))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (398:398:398) (426:426:426))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (394:394:394) (425:425:425))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (826:826:826) (891:891:891))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (663:663:663) (695:695:695))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (609:609:609) (566:566:566))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (452:452:452) (417:417:417))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (532:532:532) (525:525:525))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (431:431:431) (464:464:464))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (438:438:438) (403:403:403))
+        (IOPATH i o (2035:2035:2035) (1911:1911:1911))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (524:524:524) (514:514:514))
+        (IOPATH i o (2045:2045:2045) (1921:1921:1921))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (838:838:838) (771:771:771))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1036:1036:1036) (1093:1093:1093))
+        (IOPATH i o (1921:1921:1921) (2045:2045:2045))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1025:1025:1025) (1080:1080:1080))
+        (IOPATH i o (1921:1921:1921) (2045:2045:2045))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1222:1222:1222) (1303:1303:1303))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1222:1222:1222) (1303:1303:1303))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_SDI\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1753:1753:1753) (1830:1830:1830))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE SCK\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1900:1900:1900) (1884:1884:1884))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_CS\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1174:1174:1174) (1137:1137:1137))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_LD\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1350:1350:1350) (1371:1371:1371))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE ADC_SDI\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2528:2528:2528) (2594:2594:2594))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE ADC_CS\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2683:2683:2683) (2724:2724:2724))
+        (IOPATH i o (1891:1891:1891) (2015:2015:2015))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1329:1329:1329) (1334:1334:1334))
+        (IOPATH i o (2271:2271:2271) (2135:2135:2135))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1449:1449:1449) (1400:1400:1400))
+        (IOPATH i o (2271:2271:2271) (2135:2135:2135))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1505:1505:1505) (1476:1476:1476))
+        (IOPATH i o (4139:4139:4139) (3839:3839:3839))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1073:1073:1073) (1096:1096:1096))
+        (IOPATH i o (2281:2281:2281) (2145:2145:2145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1235:1235:1235) (1199:1199:1199))
+        (IOPATH i o (2291:2291:2291) (2155:2155:2155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1370:1370:1370) (1312:1312:1312))
+        (IOPATH i o (2291:2291:2291) (2155:2155:2155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1170:1170:1170) (1110:1110:1110))
+        (IOPATH i o (2301:2301:2301) (2165:2165:2165))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[7\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1009:1009:1009) (979:979:979))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[8\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1045:1045:1045) (1024:1024:1024))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[9\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1179:1179:1179) (1134:1134:1134))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE PWM_OUT\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2565:2565:2565) (2579:2579:2579))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[8\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[7\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[6\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[5\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[4\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[10\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2678:2678:2678) (2908:2908:2908))
+        (PORT datab (2741:2741:2741) (2939:2939:2939))
+        (PORT datac (2664:2664:2664) (2880:2880:2880))
+        (PORT datad (2750:2750:2750) (2964:2964:2964))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[3\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[2\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[0\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[1\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[14\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2670:2670:2670) (2891:2891:2891))
+        (PORT datab (2697:2697:2697) (2919:2919:2919))
+        (PORT datac (2661:2661:2661) (2850:2850:2850))
+        (PORT datad (2735:2735:2735) (2951:2951:2951))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[13\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2672:2672:2672) (2889:2889:2889))
+        (PORT datab (2692:2692:2692) (2911:2911:2911))
+        (PORT datac (2664:2664:2664) (2854:2854:2854))
+        (PORT datad (2739:2739:2739) (2956:2956:2956))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[9\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2676:2676:2676) (2909:2909:2909))
+        (PORT datab (2740:2740:2740) (2942:2942:2942))
+        (PORT datac (2673:2673:2673) (2878:2878:2878))
+        (PORT datad (2762:2762:2762) (2962:2962:2962))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[12\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2671:2671:2671) (2888:2888:2888))
+        (PORT datab (2692:2692:2692) (2913:2913:2913))
+        (PORT datac (2662:2662:2662) (2853:2853:2853))
+        (PORT datad (2738:2738:2738) (2955:2955:2955))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[12\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2676:2676:2676) (2910:2910:2910))
+        (PORT datab (2741:2741:2741) (2943:2943:2943))
+        (PORT datac (2672:2672:2672) (2878:2878:2878))
+        (PORT datad (2761:2761:2761) (2963:2963:2963))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[11\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2672:2672:2672) (2903:2903:2903))
+        (PORT datab (2743:2743:2743) (2946:2946:2946))
+        (PORT datac (2672:2672:2672) (2888:2888:2888))
+        (PORT datad (2761:2761:2761) (2972:2972:2972))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[11\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2671:2671:2671) (2888:2888:2888))
+        (PORT datab (2693:2693:2693) (2914:2914:2914))
+        (PORT datac (2662:2662:2662) (2852:2852:2852))
+        (PORT datad (2738:2738:2738) (2954:2954:2954))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[10\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2672:2672:2672) (2889:2889:2889))
+        (PORT datab (2692:2692:2692) (2912:2912:2912))
+        (PORT datac (2665:2665:2665) (2855:2855:2855))
+        (PORT datad (2739:2739:2739) (2957:2957:2957))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[9\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2673:2673:2673) (2891:2891:2891))
+        (PORT datab (2697:2697:2697) (2919:2919:2919))
+        (PORT datac (2661:2661:2661) (2850:2850:2850))
+        (PORT datad (2735:2735:2735) (2950:2950:2950))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[4\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2673:2673:2673) (2903:2903:2903))
+        (PORT datab (2743:2743:2743) (2944:2944:2944))
+        (PORT datac (2673:2673:2673) (2887:2887:2887))
+        (PORT datad (2762:2762:2762) (2971:2971:2971))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[3\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (2743:2743:2743) (2941:2941:2941))
+        (PORT datac (2679:2679:2679) (2891:2891:2891))
+        (PORT datad (2767:2767:2767) (2976:2976:2976))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[2\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (2679:2679:2679) (2891:2891:2891))
+        (PORT datad (2767:2767:2767) (2976:2976:2976))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[1\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (625:625:625) (640:640:640))
+        (PORT datab (2752:2752:2752) (2966:2966:2966))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[2\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (616:616:616) (625:625:625))
+        (PORT datab (607:607:607) (608:608:608))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[3\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (649:649:649) (659:659:659))
+        (PORT datab (593:593:593) (619:619:619))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[4\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (621:621:621) (635:635:635))
+        (PORT datab (612:612:612) (619:619:619))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[5\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (623:623:623) (641:641:641))
+        (PORT datab (659:659:659) (673:673:673))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[6\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (627:627:627) (644:644:644))
+        (PORT datab (608:608:608) (610:610:610))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[7\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (622:622:622) (649:649:649))
+        (PORT datab (594:594:594) (621:621:621))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[8\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (622:622:622) (639:639:639))
+        (PORT datab (657:657:657) (669:669:669))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[9\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (568:568:568) (582:582:582))
+        (PORT datab (659:659:659) (674:674:674))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[10\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (625:625:625) (642:642:642))
+        (PORT datab (771:771:771) (752:752:752))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (352:352:352) (356:356:356))
+        (PORT datab (2616:2616:2616) (2795:2795:2795))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2627:2627:2627) (2823:2823:2823))
+        (PORT datab (503:503:503) (493:493:493))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (326:326:326) (338:338:338))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (314:314:314) (333:333:333))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2623:2623:2623) (2825:2825:2825))
+        (PORT datab (535:535:535) (524:524:524))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2623:2623:2623) (2827:2827:2827))
+        (PORT datab (315:315:315) (332:332:332))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[13\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2678:2678:2678) (2908:2908:2908))
+        (PORT datab (2741:2741:2741) (2940:2940:2940))
+        (PORT datac (2664:2664:2664) (2882:2882:2882))
+        (PORT datad (2750:2750:2750) (2966:2966:2966))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[11\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (624:624:624) (649:649:649))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[12\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (657:657:657) (668:668:668))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[13\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (578:578:578) (596:596:596))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (347:347:347) (355:355:355))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (354:354:354) (362:362:362))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2625:2625:2625) (2825:2825:2825))
+        (PORT datab (346:346:346) (353:353:353))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[14\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2676:2676:2676) (2909:2909:2909))
+        (PORT datab (2742:2742:2742) (2945:2945:2945))
+        (PORT datac (2675:2675:2675) (2884:2884:2884))
+        (PORT datad (2763:2763:2763) (2968:2968:2968))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[14\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (568:568:568) (570:570:570))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2625:2625:2625) (2822:2822:2822))
+        (PORT datab (310:310:310) (329:329:329))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~20)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1183:1183:1183) (1216:1216:1216))
+        (PORT datab (1012:1012:1012) (1007:1007:1007))
+        (PORT datac (984:984:984) (977:977:977))
+        (PORT datad (1156:1156:1156) (1167:1167:1167))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1188:1188:1188) (1224:1224:1224))
+        (PORT datab (1008:1008:1008) (996:996:996))
+        (PORT datac (983:983:983) (971:971:971))
+        (PORT datad (1158:1158:1158) (1165:1165:1165))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (308:308:308) (281:281:281))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1182:1182:1182) (1215:1215:1215))
+        (PORT datab (1014:1014:1014) (1003:1003:1003))
+        (PORT datac (986:986:986) (975:975:975))
+        (PORT datad (1153:1153:1153) (1163:1163:1163))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (312:312:312))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (392:392:392))
+        (PORT datab (369:369:369) (379:379:379))
+        (PORT datac (963:963:963) (951:951:951))
+        (PORT datad (315:315:315) (323:323:323))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (308:308:308) (281:281:281))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (391:391:391))
+        (PORT datab (367:367:367) (378:378:378))
+        (PORT datac (962:962:962) (950:950:950))
+        (PORT datad (314:314:314) (323:323:323))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (391:391:391))
+        (PORT datab (367:367:367) (382:382:382))
+        (PORT datac (962:962:962) (947:947:947))
+        (PORT datad (313:313:313) (318:318:318))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1019:1019:1019) (1005:1005:1005))
+        (PORT datab (206:206:206) (253:253:253))
+        (PORT datac (179:179:179) (220:220:220))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1023:1023:1023) (1012:1012:1012))
+        (PORT datab (202:202:202) (246:246:246))
+        (PORT datac (176:176:176) (214:214:214))
+        (PORT datad (180:180:180) (206:206:206))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1022:1022:1022) (1011:1011:1011))
+        (PORT datab (203:203:203) (250:250:250))
+        (PORT datac (177:177:177) (217:217:217))
+        (PORT datad (181:181:181) (210:210:210))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (390:390:390))
+        (PORT datab (335:335:335) (364:364:364))
+        (PORT datac (317:317:317) (332:332:332))
+        (PORT datad (930:930:930) (914:914:914))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (374:374:374) (393:393:393))
+        (PORT datab (332:332:332) (357:357:357))
+        (PORT datac (319:319:319) (330:330:330))
+        (PORT datad (933:933:933) (918:918:918))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (392:392:392))
+        (PORT datab (335:335:335) (362:362:362))
+        (PORT datac (319:319:319) (331:331:331))
+        (PORT datad (930:930:930) (918:918:918))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (208:208:208) (257:257:257))
+        (PORT datab (1045:1045:1045) (1039:1039:1039))
+        (PORT datac (180:180:180) (221:221:221))
+        (PORT datad (182:182:182) (212:212:212))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (209:209:209) (258:258:258))
+        (PORT datab (1044:1044:1044) (1034:1034:1034))
+        (PORT datac (178:178:178) (217:217:217))
+        (PORT datad (181:181:181) (208:208:208))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (209:209:209) (260:260:260))
+        (PORT datab (1043:1043:1043) (1035:1035:1035))
+        (PORT datac (177:177:177) (217:217:217))
+        (PORT datad (181:181:181) (209:209:209))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (390:390:390))
+        (PORT datab (555:555:555) (554:554:554))
+        (PORT datac (1202:1202:1202) (1172:1172:1172))
+        (PORT datad (320:320:320) (320:320:320))
+        (IOPATH dataa combout (307:307:307) (280:280:280))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (374:374:374) (394:394:394))
+        (PORT datab (558:558:558) (557:557:557))
+        (PORT datac (1201:1201:1201) (1167:1167:1167))
+        (PORT datad (323:323:323) (321:321:321))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (374:374:374) (394:394:394))
+        (PORT datab (558:558:558) (554:554:554))
+        (PORT datac (1201:1201:1201) (1168:1168:1168))
+        (PORT datad (323:323:323) (318:318:318))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (292:292:292))
+        (PORT datab (1173:1173:1173) (1222:1222:1222))
+        (PORT datac (193:193:193) (239:239:239))
+        (PORT datad (198:198:198) (230:230:230))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (312:312:312))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (292:292:292))
+        (PORT datab (1178:1178:1178) (1226:1226:1226))
+        (PORT datac (199:199:199) (246:246:246))
+        (PORT datad (204:204:204) (236:236:236))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (296:296:296))
+        (PORT datab (1174:1174:1174) (1226:1226:1226))
+        (PORT datac (198:198:198) (244:244:244))
+        (PORT datad (203:203:203) (235:235:235))
+        (IOPATH dataa combout (307:307:307) (280:280:280))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (297:297:297))
+        (PORT datab (1174:1174:1174) (1221:1221:1221))
+        (PORT datac (191:191:191) (237:237:237))
+        (PORT datad (197:197:197) (228:228:228))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (293:293:293))
+        (PORT datab (1175:1175:1175) (1224:1224:1224))
+        (PORT datac (195:195:195) (244:244:244))
+        (PORT datad (200:200:200) (235:235:235))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (295:295:295))
+        (PORT datab (1173:1173:1173) (1224:1224:1224))
+        (PORT datac (195:195:195) (242:242:242))
+        (PORT datad (200:200:200) (233:233:233))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (292:292:292))
+        (PORT datab (1177:1177:1177) (1226:1226:1226))
+        (PORT datac (199:199:199) (245:245:245))
+        (PORT datad (204:204:204) (236:236:236))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1187:1187:1187) (1223:1223:1223))
+        (PORT datab (1012:1012:1012) (1004:1004:1004))
+        (PORT datac (986:986:986) (974:974:974))
+        (PORT datad (1159:1159:1159) (1168:1168:1168))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1185:1185:1185) (1220:1220:1220))
+        (PORT datab (1012:1012:1012) (1000:1000:1000))
+        (PORT datac (986:986:986) (976:976:976))
+        (PORT datad (1160:1160:1160) (1169:1169:1169))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (303:303:303) (313:313:313))
+        (PORT datad (308:308:308) (309:309:309))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1020:1020:1020) (1007:1007:1007))
+        (PORT datab (203:203:203) (249:249:249))
+        (PORT datac (177:177:177) (217:217:217))
+        (PORT datad (181:181:181) (208:208:208))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A7\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1188:1188:1188) (1224:1224:1224))
+        (PORT datab (1007:1007:1007) (995:995:995))
+        (PORT datad (1157:1157:1157) (1165:1165:1165))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (387:387:387))
+        (PORT datab (372:372:372) (385:385:385))
+        (PORT datac (960:960:960) (946:946:946))
+        (PORT datad (310:310:310) (316:316:316))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (225:225:225) (284:284:284))
+        (PORT datab (230:230:230) (281:281:281))
+        (PORT datac (345:345:345) (374:374:374))
+        (PORT datad (200:200:200) (235:235:235))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (958:958:958) (944:944:944))
+        (PORT datab (958:958:958) (951:951:951))
+        (PORT datac (987:987:987) (975:975:975))
+        (PORT datad (1133:1133:1133) (1168:1168:1168))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1184:1184:1184) (1207:1207:1207))
+        (PORT datab (1006:1006:1006) (1000:1000:1000))
+        (PORT datad (161:161:161) (183:183:183))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (283:283:283))
+        (PORT datab (227:227:227) (277:277:277))
+        (PORT datac (343:343:343) (371:371:371))
+        (PORT datad (202:202:202) (230:230:230))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (355:355:355) (365:365:365))
+        (PORT datac (509:509:509) (494:494:494))
+        (PORT datad (307:307:307) (315:315:315))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A7\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1188:1188:1188) (1223:1223:1223))
+        (PORT datad (1157:1157:1157) (1169:1169:1169))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (283:283:283))
+        (PORT datab (347:347:347) (355:355:355))
+        (PORT datac (943:943:943) (917:917:917))
+        (PORT datad (200:200:200) (235:235:235))
+        (IOPATH dataa combout (307:307:307) (289:289:289))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (220:220:220) (279:279:279))
+        (PORT datab (228:228:228) (277:277:277))
+        (PORT datac (350:350:350) (379:379:379))
+        (PORT datad (197:197:197) (231:231:231))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (344:344:344) (364:364:364))
+        (PORT datab (313:313:313) (331:331:331))
+        (PORT datac (320:320:320) (331:331:331))
+        (PORT datad (305:305:305) (313:313:313))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1180:1180:1180) (1211:1211:1211))
+        (PORT datab (959:959:959) (952:952:952))
+        (PORT datac (988:988:988) (976:976:976))
+        (PORT datad (1154:1154:1154) (1164:1164:1164))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (283:283:283))
+        (PORT datab (228:228:228) (279:279:279))
+        (PORT datac (349:349:349) (371:371:371))
+        (PORT datad (200:200:200) (234:234:234))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (345:345:345) (367:367:367))
+        (PORT datab (1219:1219:1219) (1167:1167:1167))
+        (PORT datac (541:541:541) (539:539:539))
+        (PORT datad (311:311:311) (309:309:309))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (388:388:388))
+        (PORT datab (337:337:337) (361:361:361))
+        (PORT datac (318:318:318) (330:330:330))
+        (PORT datad (931:931:931) (915:915:915))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (208:208:208) (258:258:258))
+        (PORT datab (202:202:202) (247:247:247))
+        (PORT datac (175:175:175) (215:215:215))
+        (PORT datad (181:181:181) (209:209:209))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (208:208:208) (257:257:257))
+        (PORT datab (205:205:205) (251:251:251))
+        (PORT datac (180:180:180) (220:220:220))
+        (PORT datad (180:180:180) (206:206:206))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (208:208:208) (257:257:257))
+        (PORT datab (1045:1045:1045) (1034:1034:1034))
+        (PORT datac (177:177:177) (217:217:217))
+        (PORT datad (180:180:180) (208:208:208))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (211:211:211) (263:263:263))
+        (PORT datab (202:202:202) (246:246:246))
+        (PORT datac (176:176:176) (214:214:214))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (583:583:583) (584:584:584))
+        (PORT datab (342:342:342) (373:373:373))
+        (PORT datac (510:510:510) (503:503:503))
+        (PORT datad (526:526:526) (520:520:520))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (584:584:584) (582:582:582))
+        (PORT datab (339:339:339) (369:369:369))
+        (PORT datac (512:512:512) (506:506:506))
+        (PORT datad (530:530:530) (522:522:522))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (583:583:583) (587:587:587))
+        (PORT datab (342:342:342) (373:373:373))
+        (PORT datac (512:512:512) (505:505:505))
+        (PORT datad (527:527:527) (526:526:526))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (387:387:387))
+        (PORT datab (554:554:554) (552:552:552))
+        (PORT datac (1204:1204:1204) (1170:1170:1170))
+        (PORT datad (320:320:320) (317:317:317))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (292:292:292))
+        (PORT datab (219:219:219) (276:276:276))
+        (PORT datac (336:336:336) (357:357:357))
+        (PORT datad (518:518:518) (502:502:502))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (293:293:293))
+        (PORT datab (221:221:221) (280:280:280))
+        (PORT datac (338:338:338) (360:360:360))
+        (PORT datad (518:518:518) (505:505:505))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (292:292:292))
+        (PORT datab (224:224:224) (284:284:284))
+        (PORT datac (343:343:343) (363:363:363))
+        (PORT datad (514:514:514) (499:499:499))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (290:290:290))
+        (PORT datab (221:221:221) (282:282:282))
+        (PORT datac (342:342:342) (361:361:361))
+        (PORT datad (515:515:515) (500:500:500))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (291:291:291))
+        (PORT datab (222:222:222) (282:282:282))
+        (PORT datac (342:342:342) (361:361:361))
+        (PORT datad (515:515:515) (500:500:500))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (293:293:293))
+        (PORT datab (225:225:225) (285:285:285))
+        (PORT datac (343:343:343) (363:363:363))
+        (PORT datad (514:514:514) (498:498:498))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (294:294:294))
+        (PORT datab (223:223:223) (283:283:283))
+        (PORT datac (339:339:339) (363:363:363))
+        (PORT datad (516:516:516) (501:501:501))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (583:583:583) (587:587:587))
+        (PORT datab (342:342:342) (373:373:373))
+        (PORT datac (512:512:512) (505:505:505))
+        (PORT datad (527:527:527) (527:527:527))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A14\|WideOr0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (344:344:344))
+        (PORT datab (547:547:547) (546:546:546))
+        (PORT datac (349:349:349) (373:373:373))
+        (PORT datad (199:199:199) (230:230:230))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (278:278:278))
+        (PORT datab (226:226:226) (276:276:276))
+        (PORT datac (349:349:349) (373:373:373))
+        (PORT datad (198:198:198) (229:229:229))
+        (IOPATH dataa combout (307:307:307) (280:280:280))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (347:347:347))
+        (PORT datab (354:354:354) (366:366:366))
+        (PORT datac (320:320:320) (330:330:330))
+        (PORT datad (305:305:305) (316:316:316))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (927:927:927) (893:893:893))
+        (PORT datad (1016:1016:1016) (984:984:984))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (210:210:210) (262:262:262))
+        (PORT datab (203:203:203) (250:250:250))
+        (PORT datac (177:177:177) (217:217:217))
+        (PORT datad (182:182:182) (211:211:211))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (830:830:830) (846:846:846))
+        (PORT datab (996:996:996) (989:989:989))
+        (PORT datac (198:198:198) (251:251:251))
+        (PORT datad (1024:1024:1024) (984:984:984))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (830:830:830) (842:842:842))
+        (PORT datab (992:992:992) (988:988:988))
+        (PORT datac (203:203:203) (254:254:254))
+        (PORT datad (1025:1025:1025) (984:984:984))
+        (IOPATH dataa combout (290:290:290) (306:306:306))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (194:194:194) (235:235:235))
+        (PORT datad (179:179:179) (207:207:207))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (828:828:828) (840:840:840))
+        (PORT datab (990:990:990) (987:987:987))
+        (PORT datac (203:203:203) (251:251:251))
+        (PORT datad (1026:1026:1026) (985:985:985))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1064:1064:1064) (1030:1030:1030))
+        (PORT datab (992:992:992) (986:986:986))
+        (PORT datac (927:927:927) (895:895:895))
+        (PORT datad (1026:1026:1026) (983:983:983))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (273:273:273) (275:275:275))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (192:192:192) (231:231:231))
+        (PORT datac (800:800:800) (808:808:808))
+        (PORT datad (161:161:161) (183:183:183))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (833:833:833) (842:842:842))
+        (PORT datab (996:996:996) (990:990:990))
+        (PORT datac (198:198:198) (246:246:246))
+        (PORT datad (1022:1022:1022) (979:979:979))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (831:831:831) (843:843:843))
+        (PORT datab (993:993:993) (990:990:990))
+        (PORT datac (201:201:201) (252:252:252))
+        (PORT datad (1027:1027:1027) (987:987:987))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (828:828:828) (837:837:837))
+        (PORT datab (989:989:989) (984:984:984))
+        (PORT datac (203:203:203) (254:254:254))
+        (PORT datad (1027:1027:1027) (982:982:982))
+        (IOPATH dataa combout (307:307:307) (280:280:280))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (192:192:192) (233:233:233))
+        (PORT datab (210:210:210) (248:248:248))
+        (PORT datac (159:159:159) (190:190:190))
+        (PORT datad (180:180:180) (208:208:208))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (829:829:829) (838:838:838))
+        (PORT datab (987:987:987) (985:985:985))
+        (PORT datac (204:204:204) (255:255:255))
+        (PORT datad (1028:1028:1028) (983:983:983))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (193:193:193) (232:232:232))
+        (PORT datac (168:168:168) (203:203:203))
+        (PORT datad (303:303:303) (304:304:304))
+        (IOPATH datab combout (273:273:273) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (204:204:204) (242:242:242))
+        (PORT datab (211:211:211) (250:250:250))
+        (PORT datac (168:168:168) (203:203:203))
+        (PORT datad (183:183:183) (212:212:212))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (829:829:829) (837:837:837))
+        (PORT datab (988:988:988) (985:985:985))
+        (PORT datac (203:203:203) (254:254:254))
+        (PORT datad (1028:1028:1028) (983:983:983))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (308:308:308) (281:281:281))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (185:185:185) (219:219:219))
+        (PORT datac (340:340:340) (350:350:350))
+        (PORT datad (181:181:181) (209:209:209))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A23\|WideOr0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (961:961:961) (946:946:946))
+        (PORT datab (1226:1226:1226) (1199:1199:1199))
+        (PORT datac (982:982:982) (971:971:971))
+        (PORT datad (978:978:978) (963:963:963))
+        (IOPATH dataa combout (267:267:267) (269:269:269))
+        (IOPATH datab combout (267:267:267) (275:275:275))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A23\|WideOr0\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1184:1184:1184) (1219:1219:1219))
+        (PORT datab (958:958:958) (953:953:953))
+        (PORT datac (159:159:159) (191:191:191))
+        (PORT datad (1158:1158:1158) (1166:1166:1166))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE CLOCK_50\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (736:736:736) (991:991:991))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|clk_1MHz\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE CLOCK_50\~inputclkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (140:140:140) (130:130:130))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (305:305:305))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (307:307:307))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (224:224:224) (283:283:283))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1308:1308:1308) (1326:1326:1326))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (184:184:184) (216:216:216))
+        (PORT datac (371:371:371) (411:411:411))
+        (PORT datad (177:177:177) (208:208:208))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1308:1308:1308) (1326:1326:1326))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (229:229:229) (301:301:301))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (183:183:183) (216:216:216))
+        (PORT datac (371:371:371) (411:411:411))
+        (PORT datad (177:177:177) (207:207:207))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1308:1308:1308) (1326:1326:1326))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (228:228:228) (301:301:301))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (183:183:183) (215:215:215))
+        (PORT datac (368:368:368) (408:408:408))
+        (PORT datad (182:182:182) (214:214:214))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1308:1308:1308) (1326:1326:1326))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1308:1308:1308) (1326:1326:1326))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (232:232:232) (311:311:311))
+        (PORT datab (230:230:230) (305:305:305))
+        (PORT datac (200:200:200) (271:271:271))
+        (PORT datad (205:205:205) (266:266:266))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (207:207:207) (247:247:247))
+        (PORT datad (224:224:224) (283:283:283))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|clk_1MHz)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1899:1899:1899) (1900:1900:1900))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (721:721:721) (723:723:723))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_DAC\|clk_1MHz\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (771:771:771) (815:815:815))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[0\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (238:238:238) (306:306:306))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (240:240:240) (309:309:309))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (286:286:286))
+        (PORT datab (633:633:633) (626:626:626))
+        (PORT datac (157:157:157) (188:188:188))
+        (PORT datad (855:855:855) (897:897:897))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (415:415:415) (446:446:446))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (654:654:654) (673:673:673))
+        (PORT datab (414:414:414) (463:463:463))
+        (PORT datac (292:292:292) (295:295:295))
+        (PORT datad (883:883:883) (920:920:920))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (383:383:383) (429:429:429))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (310:310:310) (328:328:328))
+        (PORT datab (416:416:416) (463:463:463))
+        (PORT datac (623:623:623) (643:643:643))
+        (PORT datad (885:885:885) (919:919:919))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (429:429:429))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (350:350:350) (356:356:356))
+        (PORT datab (408:408:408) (454:454:454))
+        (PORT datac (618:618:618) (638:638:638))
+        (PORT datad (884:884:884) (924:924:924))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (382:382:382) (429:429:429))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (353:353:353))
+        (PORT datab (415:415:415) (463:463:463))
+        (PORT datac (622:622:622) (642:642:642))
+        (PORT datad (884:884:884) (919:919:919))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (399:399:399) (437:437:437))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (322:322:322) (332:332:332))
+        (PORT datab (409:409:409) (453:453:453))
+        (PORT datac (619:619:619) (638:638:638))
+        (PORT datad (884:884:884) (923:923:923))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~36)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (408:408:408) (446:446:446))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (655:655:655) (674:674:674))
+        (PORT datab (415:415:415) (464:464:464))
+        (PORT datac (296:296:296) (301:301:301))
+        (PORT datad (885:885:885) (917:917:917))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~38)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (306:306:306))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (881:881:881) (937:937:937))
+        (PORT datab (182:182:182) (214:214:214))
+        (PORT datac (211:211:211) (251:251:251))
+        (PORT datad (595:595:595) (588:588:588))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~40)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (204:204:204) (267:267:267))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (881:881:881) (937:937:937))
+        (PORT datab (182:182:182) (214:214:214))
+        (PORT datac (211:211:211) (251:251:251))
+        (PORT datad (594:594:594) (589:589:589))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (411:411:411) (450:450:450))
+        (PORT datab (228:228:228) (298:298:298))
+        (PORT datac (202:202:202) (273:273:273))
+        (PORT datad (363:363:363) (400:400:400))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (677:677:677) (738:738:738))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (239:239:239) (309:309:309))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1304:1304:1304) (1322:1322:1322))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (804:804:804) (812:812:812))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (653:653:653) (674:674:674))
+        (PORT datab (416:416:416) (461:461:461))
+        (PORT datac (569:569:569) (567:567:567))
+        (PORT datad (880:880:880) (918:918:918))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (229:229:229) (300:300:300))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (210:210:210) (249:249:249))
+        (PORT datab (627:627:627) (624:624:624))
+        (PORT datac (645:645:645) (707:707:707))
+        (PORT datad (161:161:161) (182:182:182))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1304:1304:1304) (1322:1322:1322))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (628:628:628) (670:670:670))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (652:652:652) (679:679:679))
+        (PORT datab (415:415:415) (460:460:460))
+        (PORT datac (548:548:548) (542:542:542))
+        (PORT datad (881:881:881) (917:917:917))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (602:602:602) (638:638:638))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (651:651:651) (673:673:673))
+        (PORT datab (414:414:414) (461:461:461))
+        (PORT datac (555:555:555) (549:549:549))
+        (PORT datad (881:881:881) (916:916:916))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (226:226:226) (298:298:298))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1304:1304:1304) (1322:1322:1322))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (302:302:302))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1304:1304:1304) (1322:1322:1322))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (226:226:226) (296:296:296))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1304:1304:1304) (1322:1322:1322))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (306:306:306))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (185:185:185) (222:222:222))
+        (PORT datab (627:627:627) (623:623:623))
+        (PORT datac (644:644:644) (703:703:703))
+        (PORT datad (185:185:185) (211:211:211))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1304:1304:1304) (1322:1322:1322))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (242:242:242) (316:316:316))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (880:880:880) (935:935:935))
+        (PORT datab (185:185:185) (218:218:218))
+        (PORT datac (214:214:214) (256:256:256))
+        (PORT datad (596:596:596) (591:591:591))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (626:626:626) (665:665:665))
+        (PORT datab (671:671:671) (695:695:695))
+        (PORT datac (639:639:639) (665:665:665))
+        (PORT datad (204:204:204) (266:266:266))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (381:381:381) (421:421:421))
+        (PORT datab (802:802:802) (808:808:808))
+        (PORT datac (601:601:601) (640:640:640))
+        (PORT datad (201:201:201) (263:263:263))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (599:599:599) (636:636:636))
+        (PORT datab (227:227:227) (301:301:301))
+        (PORT datac (202:202:202) (274:274:274))
+        (PORT datad (204:204:204) (266:266:266))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (314:314:314))
+        (PORT datab (240:240:240) (310:310:310))
+        (PORT datac (214:214:214) (281:281:281))
+        (PORT datad (217:217:217) (274:274:274))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (320:320:320) (334:334:334))
+        (PORT datab (182:182:182) (216:216:216))
+        (PORT datac (156:156:156) (188:188:188))
+        (PORT datad (553:553:553) (547:547:547))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|clkout\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (646:646:646) (668:668:668))
+        (PORT datab (402:402:402) (445:445:445))
+        (PORT datad (884:884:884) (920:920:920))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|clkout)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PULSE\|state\.IDLE\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (264:264:264))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PULSE\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PULSE\|pulse\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (198:198:198) (266:266:266))
+        (PORT datad (208:208:208) (269:269:269))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PULSE\|pulse)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (906:906:906) (1031:1031:1031))
+        (PORT datad (217:217:217) (282:282:282))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.WAIT_CSB_HIGH)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1330:1330:1330))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (905:905:905) (1030:1030:1030))
+        (PORT datab (660:660:660) (688:688:688))
+        (PORT datad (197:197:197) (254:254:254))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1330:1330:1330))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (902:902:902) (1033:1033:1033))
+        (PORT datab (656:656:656) (683:683:683))
+        (PORT datad (220:220:220) (287:287:287))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.WAIT_CSB_FALL)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1330:1330:1330))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|dac_start\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (903:903:903) (1025:1025:1025))
+        (PORT datab (241:241:241) (316:316:316))
+        (PORT datac (541:541:541) (553:553:553))
+        (PORT datad (273:273:273) (353:353:353))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|dac_start\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (657:657:657) (686:686:686))
+        (PORT datac (158:158:158) (190:190:190))
+        (PORT datad (220:220:220) (287:287:287))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_start)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1311:1311:1311) (1330:1330:1330))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (226:226:226) (297:297:297))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[3\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (307:307:307))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[4\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (319:319:319))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1319:1319:1319))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (612:612:612) (667:667:667))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (661:661:661) (720:720:720))
+        (PORT datab (195:195:195) (236:236:236))
+        (PORT datac (214:214:214) (291:291:291))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1319:1319:1319))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (612:612:612) (667:667:667))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[1\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (226:226:226) (299:299:299))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1319:1319:1319))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (612:612:612) (667:667:667))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[2\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (227:227:227) (299:299:299))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1319:1319:1319))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (612:612:612) (667:667:667))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1319:1319:1319))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT sclr (612:612:612) (667:667:667))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD sclr (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (309:309:309))
+        (PORT datab (228:228:228) (302:302:302))
+        (PORT datac (202:202:202) (273:273:273))
+        (PORT datad (205:205:205) (266:266:266))
+        (IOPATH dataa combout (309:309:309) (326:326:326))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (661:661:661) (724:724:724))
+        (PORT datab (196:196:196) (238:238:238))
+        (PORT datac (215:215:215) (293:293:293))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_cs)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1319:1319:1319))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|clk_1MHz\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|clk_1MHz)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1899:1899:1899) (1900:1900:1900))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (721:721:721) (723:723:723))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_ADC\|clk_1MHz\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (777:777:777) (819:819:819))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE ADC_SDO\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (649:649:649) (908:908:908))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (242:242:242) (315:315:315))
+        (PORT datac (817:817:817) (850:850:850))
+        (IOPATH dataa combout (307:307:307) (306:306:306))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.WAIT_CSB_HIGH)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (569:569:569) (602:602:602))
+        (PORT datab (845:845:845) (880:880:880))
+        (PORT datad (238:238:238) (297:297:297))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (295:295:295) (300:300:300))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (683:683:683) (733:733:733))
+        (PORT datab (607:607:607) (651:651:651))
+        (PORT datad (789:789:789) (870:870:870))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.WAIT_CSB_FALL)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1308:1308:1308) (1326:1326:1326))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|adc_start\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (225:225:225) (299:299:299))
+        (PORT datab (811:811:811) (899:899:899))
+        (PORT datac (581:581:581) (627:627:627))
+        (PORT datad (219:219:219) (277:277:277))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|adc_start\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (186:186:186) (224:224:224))
+        (PORT datab (814:814:814) (905:905:905))
+        (PORT datac (645:645:645) (698:698:698))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_start)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1308:1308:1308) (1326:1326:1326))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (244:244:244) (329:329:329))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (250:250:250) (333:333:333))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (236:236:236) (303:303:303))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|state\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (214:214:214) (256:256:256))
+        (PORT datac (243:243:243) (334:334:334))
+        (PORT datad (162:162:162) (184:184:184))
+        (IOPATH datab combout (295:295:295) (285:285:285))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (455:455:455) (514:514:514))
+        (PORT datad (231:231:231) (299:299:299))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (333:333:333))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (185:185:185) (222:222:222))
+        (PORT datab (215:215:215) (257:257:257))
+        (PORT datac (243:243:243) (335:335:335))
+        (PORT datad (161:161:161) (183:183:183))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (269:269:269) (361:361:361))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|state\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (248:248:248) (334:334:334))
+        (PORT datac (225:225:225) (305:305:305))
+        (PORT datad (226:226:226) (293:293:293))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector4\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (457:457:457) (515:515:515))
+        (PORT datab (214:214:214) (255:255:255))
+        (PORT datac (244:244:244) (336:336:336))
+        (PORT datad (229:229:229) (296:296:296))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (309:309:309) (328:328:328))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_cs)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (883:883:883) (958:958:958))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (271:271:271) (367:367:367))
+        (PORT datab (247:247:247) (333:333:333))
+        (PORT datac (223:223:223) (304:304:304))
+        (PORT datad (226:226:226) (294:294:294))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (426:426:426))
+        (PORT datab (184:184:184) (218:218:218))
+        (PORT datac (242:242:242) (332:332:332))
+        (PORT datad (232:232:232) (300:300:300))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_ena)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (580:580:580) (637:637:637))
+        (PORT datad (585:585:585) (615:615:615))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT asdata (3480:3480:3480) (3720:3720:3720))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (264:264:264))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT asdata (512:512:512) (578:578:578))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (264:264:264))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT asdata (511:511:511) (575:575:575))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (217:217:217) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (206:206:206) (265:265:265))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT asdata (526:526:526) (589:589:589))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (267:267:267) (360:360:360))
+        (PORT datab (247:247:247) (334:334:334))
+        (PORT datac (223:223:223) (305:305:305))
+        (PORT datad (227:227:227) (295:295:295))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (265:265:265) (275:275:275))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Decoder0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (184:184:184) (217:217:217))
+        (PORT datad (229:229:229) (296:296:296))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_done)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT asdata (695:695:695) (725:725:725))
+        (PORT ena (1380:1380:1380) (1435:1435:1435))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|PULSE2\|state\.IDLE\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1475:1475:1475) (1455:1455:1455))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|PULSE2\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|PULSE2\|pulse\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1499:1499:1499) (1489:1489:1489))
+        (PORT datad (198:198:198) (255:255:255))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|PULSE2\|pulse)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1320:1320:1320))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|rden_b_store)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1301:1301:1301) (1319:1319:1319))
+        (PORT asdata (1112:1112:1112) (1124:1124:1124))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (828:828:828) (845:845:845))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT asdata (526:526:526) (588:588:588))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT asdata (695:695:695) (724:724:724))
+        (PORT ena (1380:1380:1380) (1435:1435:1435))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (218:218:218) (276:276:276))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1314:1314:1314))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (746:746:746) (752:752:752))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT asdata (647:647:647) (683:683:683))
+        (PORT ena (1380:1380:1380) (1435:1435:1435))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_ADC\|adc_cs\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (1020:1020:1020) (1053:1053:1053))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[0\]\~36)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[1\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (240:240:240) (313:313:313))
+        (PORT datab (239:239:239) (308:308:308))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[2\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (240:240:240) (308:308:308))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[3\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (315:315:315))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[4\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (315:315:315))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[4\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2691:2691:2691) (2885:2885:2885))
+        (PORT datab (1287:1287:1287) (1296:1296:1296))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[5\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (310:310:310))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[5\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1325:1325:1325) (1345:1345:1345))
+        (PORT datab (2776:2776:2776) (2993:2993:2993))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[6\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (310:310:310))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[6\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1359:1359:1359) (1379:1379:1379))
+        (PORT datab (2694:2694:2694) (2911:2911:2911))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[7\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (240:240:240) (310:310:310))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[7\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1331:1331:1331) (1376:1376:1376))
+        (PORT datab (2688:2688:2688) (2878:2878:2878))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[8\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (311:311:311))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[8\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2761:2761:2761) (2995:2995:2995))
+        (PORT datab (1326:1326:1326) (1358:1358:1358))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[9\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (242:242:242) (314:314:314))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[9\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1278:1278:1278) (1290:1290:1290))
+        (PORT datab (2940:2940:2940) (3126:3126:3126))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[10\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (258:258:258) (327:327:327))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[10\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1126:1126:1126) (1144:1144:1144))
+        (PORT datab (2966:2966:2966) (3179:3179:3179))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[11\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (314:314:314))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[11\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2707:2707:2707) (2896:2896:2896))
+        (PORT datab (1354:1354:1354) (1371:1371:1371))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[12\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (216:216:216) (273:273:273))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1318:1318:1318))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[12\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2689:2689:2689) (2885:2885:2885))
+        (PORT datad (1278:1278:1278) (1304:1304:1304))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (628:628:628) (637:637:637))
+        (PORT clk (1601:1601:1601) (1626:1626:1626))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (971:971:971) (990:990:990))
+        (PORT d[1] (941:941:941) (981:981:981))
+        (PORT d[2] (960:960:960) (983:983:983))
+        (PORT d[3] (1453:1453:1453) (1471:1471:1471))
+        (PORT d[4] (1317:1317:1317) (1302:1302:1302))
+        (PORT d[5] (1321:1321:1321) (1294:1294:1294))
+        (PORT d[6] (1826:1826:1826) (1762:1762:1762))
+        (PORT d[7] (1346:1346:1346) (1332:1332:1332))
+        (PORT d[8] (1528:1528:1528) (1487:1487:1487))
+        (PORT d[9] (1320:1320:1320) (1318:1318:1318))
+        (PORT d[10] (1466:1466:1466) (1483:1483:1483))
+        (PORT d[11] (1524:1524:1524) (1501:1501:1501))
+        (PORT d[12] (1351:1351:1351) (1351:1351:1351))
+        (PORT clk (1598:1598:1598) (1624:1624:1624))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1135:1135:1135) (1107:1107:1107))
+        (PORT clk (1598:1598:1598) (1624:1624:1624))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1601:1601:1601) (1626:1626:1626))
+        (PORT d[0] (1591:1591:1591) (1573:1573:1573))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1602:1602:1602) (1627:1627:1627))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1602:1602:1602) (1627:1627:1627))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1602:1602:1602) (1627:1627:1627))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1602:1602:1602) (1627:1627:1627))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (931:931:931) (955:955:955))
+        (PORT d[1] (942:942:942) (984:984:984))
+        (PORT d[2] (982:982:982) (1004:1004:1004))
+        (PORT d[3] (1454:1454:1454) (1472:1472:1472))
+        (PORT d[4] (905:905:905) (929:929:929))
+        (PORT d[5] (1189:1189:1189) (1246:1246:1246))
+        (PORT d[6] (926:926:926) (953:953:953))
+        (PORT d[7] (1219:1219:1219) (1262:1262:1262))
+        (PORT d[8] (971:971:971) (1017:1017:1017))
+        (PORT d[9] (960:960:960) (980:980:980))
+        (PORT d[10] (1303:1303:1303) (1364:1364:1364))
+        (PORT d[11] (1196:1196:1196) (1238:1238:1238))
+        (PORT d[12] (932:932:932) (964:964:964))
+        (PORT clk (1565:1565:1565) (1560:1560:1560))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1135:1135:1135) (1108:1108:1108))
+        (PORT clk (1565:1565:1565) (1560:1560:1560))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1565:1565:1565) (1560:1560:1560))
+        (PORT d[0] (1936:1936:1936) (1859:1859:1859))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1566:1566:1566) (1561:1561:1561))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1566:1566:1566) (1561:1561:1561))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1566:1566:1566) (1561:1561:1561))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1561:1561:1561) (1557:1557:1557))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT asdata (694:694:694) (721:721:721))
+        (PORT ena (1380:1380:1380) (1435:1435:1435))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (264:264:264))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (1198:1198:1198) (1221:1221:1221))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (817:817:817) (801:801:801))
+        (PORT datab (222:222:222) (291:291:291))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1251:1251:1251) (1242:1242:1242))
+        (PORT clk (1595:1595:1595) (1623:1623:1623))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1832:1832:1832) (1852:1852:1852))
+        (PORT d[1] (1942:1942:1942) (1982:1982:1982))
+        (PORT d[2] (1117:1117:1117) (1145:1145:1145))
+        (PORT d[3] (2239:2239:2239) (2245:2245:2245))
+        (PORT d[4] (911:911:911) (930:930:930))
+        (PORT d[5] (681:681:681) (704:704:704))
+        (PORT d[6] (1050:1050:1050) (1027:1027:1027))
+        (PORT d[7] (645:645:645) (663:663:663))
+        (PORT d[8] (1368:1368:1368) (1395:1395:1395))
+        (PORT d[9] (664:664:664) (678:678:678))
+        (PORT d[10] (1553:1553:1553) (1565:1565:1565))
+        (PORT d[11] (900:900:900) (920:920:920))
+        (PORT d[12] (674:674:674) (692:692:692))
+        (PORT clk (1592:1592:1592) (1621:1621:1621))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1171:1171:1171) (1123:1123:1123))
+        (PORT clk (1592:1592:1592) (1621:1621:1621))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1595:1595:1595) (1623:1623:1623))
+        (PORT d[0] (1627:1627:1627) (1589:1589:1589))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1596:1596:1596) (1624:1624:1624))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1596:1596:1596) (1624:1624:1624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1596:1596:1596) (1624:1624:1624))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1596:1596:1596) (1624:1624:1624))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1813:1813:1813) (1831:1831:1831))
+        (PORT d[1] (1943:1943:1943) (1977:1977:1977))
+        (PORT d[2] (1139:1139:1139) (1167:1167:1167))
+        (PORT d[3] (2240:2240:2240) (2246:2246:2246))
+        (PORT d[4] (1134:1134:1134) (1142:1142:1142))
+        (PORT d[5] (1657:1657:1657) (1699:1699:1699))
+        (PORT d[6] (1888:1888:1888) (1916:1916:1916))
+        (PORT d[7] (2088:2088:2088) (2084:2084:2084))
+        (PORT d[8] (1863:1863:1863) (1860:1860:1860))
+        (PORT d[9] (1136:1136:1136) (1149:1149:1149))
+        (PORT d[10] (1633:1633:1633) (1641:1641:1641))
+        (PORT d[11] (1619:1619:1619) (1635:1635:1635))
+        (PORT d[12] (1623:1623:1623) (1654:1654:1654))
+        (PORT clk (1559:1559:1559) (1557:1557:1557))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1171:1171:1171) (1124:1124:1124))
+        (PORT clk (1559:1559:1559) (1557:1557:1557))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1559:1559:1559) (1557:1557:1557))
+        (PORT d[0] (1328:1328:1328) (1287:1287:1287))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1560:1560:1560) (1558:1558:1558))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1560:1560:1560) (1558:1558:1558))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1560:1560:1560) (1558:1558:1558))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1555:1555:1555) (1554:1554:1554))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (364:364:364) (399:399:399))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (1380:1380:1380) (1435:1435:1435))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (561:561:561) (586:586:586))
+        (PORT datab (1042:1042:1042) (992:992:992))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (866:866:866) (848:848:848))
+        (PORT clk (1604:1604:1604) (1632:1632:1632))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (934:934:934) (968:968:968))
+        (PORT d[1] (962:962:962) (1005:1005:1005))
+        (PORT d[2] (935:935:935) (969:969:969))
+        (PORT d[3] (974:974:974) (1005:1005:1005))
+        (PORT d[4] (1308:1308:1308) (1287:1287:1287))
+        (PORT d[5] (1312:1312:1312) (1276:1276:1276))
+        (PORT d[6] (2350:2350:2350) (2294:2294:2294))
+        (PORT d[7] (1335:1335:1335) (1311:1311:1311))
+        (PORT d[8] (1498:1498:1498) (1445:1445:1445))
+        (PORT d[9] (1310:1310:1310) (1293:1293:1293))
+        (PORT d[10] (1657:1657:1657) (1675:1675:1675))
+        (PORT d[11] (1544:1544:1544) (1506:1506:1506))
+        (PORT d[12] (1810:1810:1810) (1767:1767:1767))
+        (PORT clk (1601:1601:1601) (1630:1630:1630))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1353:1353:1353) (1308:1308:1308))
+        (PORT clk (1601:1601:1601) (1630:1630:1630))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1604:1604:1604) (1632:1632:1632))
+        (PORT d[0] (1809:1809:1809) (1774:1774:1774))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (942:942:942) (962:962:962))
+        (PORT d[1] (963:963:963) (999:999:999))
+        (PORT d[2] (957:957:957) (992:992:992))
+        (PORT d[3] (975:975:975) (1006:1006:1006))
+        (PORT d[4] (955:955:955) (989:989:989))
+        (PORT d[5] (1207:1207:1207) (1262:1262:1262))
+        (PORT d[6] (1160:1160:1160) (1182:1182:1182))
+        (PORT d[7] (952:952:952) (993:993:993))
+        (PORT d[8] (981:981:981) (1038:1038:1038))
+        (PORT d[9] (1213:1213:1213) (1238:1238:1238))
+        (PORT d[10] (983:983:983) (1037:1037:1037))
+        (PORT d[11] (939:939:939) (978:978:978))
+        (PORT d[12] (965:965:965) (1005:1005:1005))
+        (PORT clk (1568:1568:1568) (1566:1566:1566))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1353:1353:1353) (1309:1309:1309))
+        (PORT clk (1568:1568:1568) (1566:1566:1566))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1568:1568:1568) (1566:1566:1566))
+        (PORT d[0] (1971:1971:1971) (1913:1913:1913))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1564:1564:1564) (1563:1563:1563))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (426:426:426) (476:476:476))
+        (PORT datab (864:864:864) (850:850:850))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (880:880:880) (867:867:867))
+        (PORT clk (1592:1592:1592) (1618:1618:1618))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1121:1121:1121) (1113:1113:1113))
+        (PORT d[1] (1909:1909:1909) (1936:1936:1936))
+        (PORT d[2] (1433:1433:1433) (1445:1445:1445))
+        (PORT d[3] (1918:1918:1918) (1918:1918:1918))
+        (PORT d[4] (914:914:914) (926:926:926))
+        (PORT d[5] (1234:1234:1234) (1248:1248:1248))
+        (PORT d[6] (1077:1077:1077) (1057:1057:1057))
+        (PORT d[7] (666:666:666) (677:677:677))
+        (PORT d[8] (1549:1549:1549) (1553:1553:1553))
+        (PORT d[9] (669:669:669) (683:683:683))
+        (PORT d[10] (1352:1352:1352) (1361:1361:1361))
+        (PORT d[11] (685:685:685) (707:707:707))
+        (PORT d[12] (648:648:648) (666:666:666))
+        (PORT clk (1589:1589:1589) (1616:1616:1616))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1560:1560:1560) (1528:1528:1528))
+        (PORT clk (1589:1589:1589) (1616:1616:1616))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1592:1592:1592) (1618:1618:1618))
+        (PORT d[0] (2016:2016:2016) (1994:1994:1994))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1593:1593:1593) (1619:1619:1619))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1593:1593:1593) (1619:1619:1619))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1593:1593:1593) (1619:1619:1619))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1593:1593:1593) (1619:1619:1619))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1115:1115:1115) (1121:1121:1121))
+        (PORT d[1] (1931:1931:1931) (1958:1958:1958))
+        (PORT d[2] (1414:1414:1414) (1430:1430:1430))
+        (PORT d[3] (1919:1919:1919) (1919:1919:1919))
+        (PORT d[4] (1362:1362:1362) (1359:1359:1359))
+        (PORT d[5] (1626:1626:1626) (1672:1672:1672))
+        (PORT d[6] (1864:1864:1864) (1889:1889:1889))
+        (PORT d[7] (1845:1845:1845) (1857:1857:1857))
+        (PORT d[8] (1580:1580:1580) (1587:1587:1587))
+        (PORT d[9] (1307:1307:1307) (1307:1307:1307))
+        (PORT d[10] (1905:1905:1905) (1920:1920:1920))
+        (PORT d[11] (1854:1854:1854) (1859:1859:1859))
+        (PORT d[12] (1600:1600:1600) (1626:1626:1626))
+        (PORT clk (1556:1556:1556) (1552:1552:1552))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1560:1560:1560) (1529:1529:1529))
+        (PORT clk (1556:1556:1556) (1552:1552:1552))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1556:1556:1556) (1552:1552:1552))
+        (PORT d[0] (1573:1573:1573) (1527:1527:1527))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1557:1557:1557) (1553:1553:1553))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1557:1557:1557) (1553:1553:1553))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1557:1557:1557) (1553:1553:1553))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1552:1552:1552) (1549:1549:1549))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT asdata (513:513:513) (579:579:579))
+        (PORT ena (1198:1198:1198) (1221:1221:1221))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (205:205:205) (264:264:264))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (1198:1198:1198) (1221:1221:1221))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (780:780:780) (748:748:748))
+        (PORT datab (564:564:564) (597:597:597))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1256:1256:1256) (1248:1248:1248))
+        (PORT clk (1595:1595:1595) (1623:1623:1623))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1406:1406:1406) (1392:1392:1392))
+        (PORT d[1] (1946:1946:1946) (1973:1973:1973))
+        (PORT d[2] (1434:1434:1434) (1449:1449:1449))
+        (PORT d[3] (1871:1871:1871) (1879:1879:1879))
+        (PORT d[4] (906:906:906) (911:911:911))
+        (PORT d[5] (644:644:644) (650:650:650))
+        (PORT d[6] (1046:1046:1046) (1014:1014:1014))
+        (PORT d[7] (634:634:634) (637:637:637))
+        (PORT d[8] (1300:1300:1300) (1319:1319:1319))
+        (PORT d[9] (637:637:637) (638:638:638))
+        (PORT d[10] (1343:1343:1343) (1357:1357:1357))
+        (PORT d[11] (675:675:675) (683:683:683))
+        (PORT d[12] (890:890:890) (893:893:893))
+        (PORT clk (1592:1592:1592) (1621:1621:1621))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1581:1581:1581) (1543:1543:1543))
+        (PORT clk (1592:1592:1592) (1621:1621:1621))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1595:1595:1595) (1623:1623:1623))
+        (PORT d[0] (2037:2037:2037) (2009:2009:2009))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1596:1596:1596) (1624:1624:1624))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1596:1596:1596) (1624:1624:1624))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1596:1596:1596) (1624:1624:1624))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1596:1596:1596) (1624:1624:1624))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1401:1401:1401) (1395:1395:1395))
+        (PORT d[1] (1927:1927:1927) (1953:1953:1953))
+        (PORT d[2] (1414:1414:1414) (1428:1428:1428))
+        (PORT d[3] (1872:1872:1872) (1880:1880:1880))
+        (PORT d[4] (1351:1351:1351) (1359:1359:1359))
+        (PORT d[5] (1617:1617:1617) (1651:1651:1651))
+        (PORT d[6] (1887:1887:1887) (1870:1870:1870))
+        (PORT d[7] (1649:1649:1649) (1684:1684:1684))
+        (PORT d[8] (2081:2081:2081) (2107:2107:2107))
+        (PORT d[9] (1278:1278:1278) (1291:1291:1291))
+        (PORT d[10] (1613:1613:1613) (1615:1615:1615))
+        (PORT d[11] (1601:1601:1601) (1601:1601:1601))
+        (PORT d[12] (1355:1355:1355) (1374:1374:1374))
+        (PORT clk (1559:1559:1559) (1557:1557:1557))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1581:1581:1581) (1544:1544:1544))
+        (PORT clk (1559:1559:1559) (1557:1557:1557))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1559:1559:1559) (1557:1557:1557))
+        (PORT d[0] (1552:1552:1552) (1517:1517:1517))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1560:1560:1560) (1558:1558:1558))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1560:1560:1560) (1558:1558:1558))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1560:1560:1560) (1558:1558:1558))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1555:1555:1555) (1554:1554:1554))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT asdata (512:512:512) (578:578:578))
+        (PORT ena (1198:1198:1198) (1221:1221:1221))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (400:400:400) (433:433:433))
+        (PORT datab (1222:1222:1222) (1212:1212:1212))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (847:847:847) (828:828:828))
+        (PORT clk (1604:1604:1604) (1632:1632:1632))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1213:1213:1213) (1254:1254:1254))
+        (PORT d[1] (699:699:699) (742:742:742))
+        (PORT d[2] (1215:1215:1215) (1254:1254:1254))
+        (PORT d[3] (1444:1444:1444) (1459:1459:1459))
+        (PORT d[4] (1330:1330:1330) (1314:1314:1314))
+        (PORT d[5] (1346:1346:1346) (1322:1322:1322))
+        (PORT d[6] (1826:1826:1826) (1762:1762:1762))
+        (PORT d[7] (1332:1332:1332) (1312:1312:1312))
+        (PORT d[8] (1544:1544:1544) (1504:1504:1504))
+        (PORT d[9] (1297:1297:1297) (1296:1296:1296))
+        (PORT d[10] (1468:1468:1468) (1487:1487:1487))
+        (PORT d[11] (1584:1584:1584) (1554:1554:1554))
+        (PORT d[12] (1337:1337:1337) (1332:1332:1332))
+        (PORT clk (1601:1601:1601) (1630:1630:1630))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1640:1640:1640) (1590:1590:1590))
+        (PORT clk (1601:1601:1601) (1630:1630:1630))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1604:1604:1604) (1632:1632:1632))
+        (PORT d[0] (2096:2096:2096) (2056:2056:2056))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1213:1213:1213) (1255:1255:1255))
+        (PORT d[1] (721:721:721) (764:764:764))
+        (PORT d[2] (1182:1182:1182) (1211:1211:1211))
+        (PORT d[3] (1445:1445:1445) (1460:1460:1460))
+        (PORT d[4] (703:703:703) (735:735:735))
+        (PORT d[5] (703:703:703) (742:742:742))
+        (PORT d[6] (682:682:682) (716:716:716))
+        (PORT d[7] (678:678:678) (709:709:709))
+        (PORT d[8] (693:693:693) (727:727:727))
+        (PORT d[9] (909:909:909) (928:928:928))
+        (PORT d[10] (694:694:694) (736:736:736))
+        (PORT d[11] (1205:1205:1205) (1258:1258:1258))
+        (PORT d[12] (897:897:897) (907:907:907))
+        (PORT clk (1568:1568:1568) (1566:1566:1566))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1640:1640:1640) (1591:1591:1591))
+        (PORT clk (1568:1568:1568) (1566:1566:1566))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1568:1568:1568) (1566:1566:1566))
+        (PORT d[0] (1714:1714:1714) (1633:1633:1633))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1564:1564:1564) (1563:1563:1563))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (360:360:360) (408:408:408))
+        (PORT datab (1081:1081:1081) (1048:1048:1048))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1309:1309:1309) (1287:1287:1287))
+        (PORT clk (1597:1597:1597) (1625:1625:1625))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1406:1406:1406) (1412:1412:1412))
+        (PORT d[1] (1426:1426:1426) (1462:1462:1462))
+        (PORT d[2] (1422:1422:1422) (1433:1433:1433))
+        (PORT d[3] (1393:1393:1393) (1409:1409:1409))
+        (PORT d[4] (655:655:655) (663:663:663))
+        (PORT d[5] (390:390:390) (404:404:404))
+        (PORT d[6] (383:383:383) (391:391:391))
+        (PORT d[7] (388:388:388) (400:400:400))
+        (PORT d[8] (383:383:383) (389:389:389))
+        (PORT d[9] (392:392:392) (407:407:407))
+        (PORT d[10] (381:381:381) (387:387:387))
+        (PORT d[11] (375:375:375) (390:390:390))
+        (PORT d[12] (392:392:392) (404:404:404))
+        (PORT clk (1594:1594:1594) (1623:1623:1623))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1550:1550:1550) (1533:1533:1533))
+        (PORT clk (1594:1594:1594) (1623:1623:1623))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1597:1597:1597) (1625:1625:1625))
+        (PORT d[0] (2006:2006:2006) (1999:1999:1999))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1598:1598:1598) (1626:1626:1626))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1598:1598:1598) (1626:1626:1626))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1598:1598:1598) (1626:1626:1626))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1598:1598:1598) (1626:1626:1626))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1427:1427:1427) (1429:1429:1429))
+        (PORT d[1] (1426:1426:1426) (1462:1462:1462))
+        (PORT d[2] (1436:1436:1436) (1457:1457:1457))
+        (PORT d[3] (1394:1394:1394) (1410:1410:1410))
+        (PORT d[4] (1377:1377:1377) (1388:1388:1388))
+        (PORT d[5] (1380:1380:1380) (1415:1415:1415))
+        (PORT d[6] (1399:1399:1399) (1417:1417:1417))
+        (PORT d[7] (1412:1412:1412) (1459:1459:1459))
+        (PORT d[8] (1432:1432:1432) (1453:1453:1453))
+        (PORT d[9] (1327:1327:1327) (1336:1336:1336))
+        (PORT d[10] (1382:1382:1382) (1384:1384:1384))
+        (PORT d[11] (1395:1395:1395) (1416:1416:1416))
+        (PORT d[12] (1380:1380:1380) (1409:1409:1409))
+        (PORT clk (1561:1561:1561) (1559:1559:1559))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1550:1550:1550) (1534:1534:1534))
+        (PORT clk (1561:1561:1561) (1559:1559:1559))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1561:1561:1561) (1559:1559:1559))
+        (PORT d[0] (1559:1559:1559) (1527:1527:1527))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1562:1562:1562) (1560:1560:1560))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1562:1562:1562) (1560:1560:1560))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1562:1562:1562) (1560:1560:1560))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1557:1557:1557) (1556:1556:1556))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (207:207:207) (267:267:267))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (PORT ena (1198:1198:1198) (1221:1221:1221))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1179:1179:1179) (1168:1168:1168))
+        (PORT datab (393:393:393) (425:425:425))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (319:319:319) (307:307:307))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (412:412:412))
+        (PORT datab (1131:1131:1131) (1103:1103:1103))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (308:308:308) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (393:393:393) (449:449:449))
+        (PORT datab (886:886:886) (869:869:869))
+        (IOPATH dataa combout (307:307:307) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (383:383:383) (446:446:446))
+        (PORT datad (847:847:847) (832:832:832))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (181:181:181) (213:213:213))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (181:181:181) (213:213:213))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (183:183:183) (219:219:219))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (902:902:902) (899:899:899))
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (988:988:988) (1017:1017:1017))
+        (PORT d[1] (982:982:982) (1026:1026:1026))
+        (PORT d[2] (991:991:991) (1030:1030:1030))
+        (PORT d[3] (1433:1433:1433) (1459:1459:1459))
+        (PORT d[4] (1067:1067:1067) (1029:1029:1029))
+        (PORT d[5] (1071:1071:1071) (1041:1041:1041))
+        (PORT d[6] (2356:2356:2356) (2287:2287:2287))
+        (PORT d[7] (1076:1076:1076) (1034:1034:1034))
+        (PORT d[8] (1077:1077:1077) (1043:1043:1043))
+        (PORT d[9] (1048:1048:1048) (1019:1019:1019))
+        (PORT d[10] (1130:1130:1130) (1141:1141:1141))
+        (PORT d[11] (1844:1844:1844) (1836:1836:1836))
+        (PORT d[12] (1030:1030:1030) (1001:1001:1001))
+        (PORT clk (1602:1602:1602) (1631:1631:1631))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1381:1381:1381) (1344:1344:1344))
+        (PORT clk (1602:1602:1602) (1631:1631:1631))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+        (PORT d[0] (1837:1837:1837) (1810:1810:1810))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1606:1606:1606) (1634:1634:1634))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1606:1606:1606) (1634:1634:1634))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1606:1606:1606) (1634:1634:1634))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1606:1606:1606) (1634:1634:1634))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (983:983:983) (1020:1020:1020))
+        (PORT d[1] (983:983:983) (1027:1027:1027))
+        (PORT d[2] (951:951:951) (989:989:989))
+        (PORT d[3] (1434:1434:1434) (1460:1460:1460))
+        (PORT d[4] (957:957:957) (994:994:994))
+        (PORT d[5] (950:950:950) (993:993:993))
+        (PORT d[6] (948:948:948) (986:986:986))
+        (PORT d[7] (930:930:930) (967:967:967))
+        (PORT d[8] (991:991:991) (1044:1044:1044))
+        (PORT d[9] (1172:1172:1172) (1195:1195:1195))
+        (PORT d[10] (1015:1015:1015) (1069:1069:1069))
+        (PORT d[11] (1149:1149:1149) (1168:1168:1168))
+        (PORT d[12] (942:942:942) (991:991:991))
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1381:1381:1381) (1345:1345:1345))
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+        (PORT d[0] (1948:1948:1948) (1883:1883:1883))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1570:1570:1570) (1568:1568:1568))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1570:1570:1570) (1568:1568:1568))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1570:1570:1570) (1568:1568:1568))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1565:1565:1565) (1564:1564:1564))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (893:893:893) (888:888:888))
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1204:1204:1204) (1240:1240:1240))
+        (PORT d[1] (940:940:940) (967:967:967))
+        (PORT d[2] (1199:1199:1199) (1240:1240:1240))
+        (PORT d[3] (1424:1424:1424) (1438:1438:1438))
+        (PORT d[4] (1584:1584:1584) (1548:1548:1548))
+        (PORT d[5] (1372:1372:1372) (1351:1351:1351))
+        (PORT d[6] (2584:2584:2584) (2527:2527:2527))
+        (PORT d[7] (1358:1358:1358) (1342:1342:1342))
+        (PORT d[8] (1545:1545:1545) (1505:1505:1505))
+        (PORT d[9] (1298:1298:1298) (1297:1297:1297))
+        (PORT d[10] (1405:1405:1405) (1425:1425:1425))
+        (PORT d[11] (1511:1511:1511) (1474:1474:1474))
+        (PORT d[12] (1338:1338:1338) (1332:1332:1332))
+        (PORT clk (1602:1602:1602) (1631:1631:1631))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1367:1367:1367) (1332:1332:1332))
+        (PORT clk (1602:1602:1602) (1631:1631:1631))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1605:1605:1605) (1633:1633:1633))
+        (PORT d[0] (1860:1860:1860) (1820:1820:1820))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1606:1606:1606) (1634:1634:1634))
+        (IOPATH (posedge clk) pulse (0:0:0) (1851:1851:1851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1606:1606:1606) (1634:1634:1634))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1606:1606:1606) (1634:1634:1634))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1606:1606:1606) (1634:1634:1634))
+        (IOPATH (posedge clk) pulse (0:0:0) (2360:2360:2360))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1225:1225:1225) (1263:1263:1263))
+        (PORT d[1] (928:928:928) (940:940:940))
+        (PORT d[2] (1200:1200:1200) (1241:1241:1241))
+        (PORT d[3] (1425:1425:1425) (1439:1439:1439))
+        (PORT d[4] (943:943:943) (968:968:968))
+        (PORT d[5] (921:921:921) (954:954:954))
+        (PORT d[6] (1213:1213:1213) (1243:1243:1243))
+        (PORT d[7] (1234:1234:1234) (1292:1292:1292))
+        (PORT d[8] (924:924:924) (955:955:955))
+        (PORT d[9] (1157:1157:1157) (1163:1163:1163))
+        (PORT d[10] (938:938:938) (981:981:981))
+        (PORT d[11] (1232:1232:1232) (1283:1283:1283))
+        (PORT d[12] (942:942:942) (975:975:975))
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1404:1404:1404) (1355:1355:1355))
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (169:169:169))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1569:1569:1569) (1567:1567:1567))
+        (PORT d[0] (2170:2170:2170) (2128:2128:2128))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1570:1570:1570) (1568:1568:1568))
+        (IOPATH (posedge clk) pulse (0:0:0) (2178:2178:2178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1570:1570:1570) (1568:1568:1568))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1570:1570:1570) (1568:1568:1568))
+        (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1565:1565:1565) (1564:1564:1564))
+        (IOPATH (posedge clk) q (268:268:268) (268:268:268))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (42:42:42))
+      (HOLD d (posedge clk) (142:142:142))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (877:877:877) (957:957:957))
+        (PORT datac (1262:1262:1262) (1297:1297:1297))
+        (PORT datad (664:664:664) (699:699:699))
+        (IOPATH dataa combout (287:287:287) (289:289:289))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1297:1297:1297) (1315:1315:1315))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (877:877:877) (957:957:957))
+        (PORT datab (222:222:222) (291:291:291))
+        (PORT datac (1058:1058:1058) (1055:1055:1055))
+        (PORT datad (664:664:664) (699:699:699))
+        (IOPATH dataa combout (267:267:267) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1297:1297:1297) (1315:1315:1315))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1006:1006:1006) (1058:1058:1058))
+        (PORT datab (709:709:709) (743:743:743))
+        (PORT datac (197:197:197) (265:265:265))
+        (PORT datad (826:826:826) (908:908:908))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1297:1297:1297) (1315:1315:1315))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (872:872:872) (951:951:951))
+        (PORT datab (222:222:222) (291:291:291))
+        (PORT datac (952:952:952) (980:980:980))
+        (PORT datad (670:670:670) (707:707:707))
+        (IOPATH dataa combout (267:267:267) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1297:1297:1297) (1315:1315:1315))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (872:872:872) (949:949:949))
+        (PORT datab (222:222:222) (291:291:291))
+        (PORT datac (797:797:797) (803:803:803))
+        (PORT datad (671:671:671) (708:708:708))
+        (IOPATH dataa combout (267:267:267) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1297:1297:1297) (1315:1315:1315))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (904:904:904) (1032:1032:1032))
+        (PORT datab (390:390:390) (451:451:451))
+        (PORT datac (972:972:972) (1027:1027:1027))
+        (PORT datad (273:273:273) (356:356:356))
+        (IOPATH dataa combout (267:267:267) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (902:902:902) (1030:1030:1030))
+        (PORT datab (224:224:224) (292:292:292))
+        (PORT datac (640:640:640) (684:684:684))
+        (PORT datad (277:277:277) (353:353:353))
+        (IOPATH dataa combout (267:267:267) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (900:900:900) (1034:1034:1034))
+        (PORT datab (649:649:649) (683:683:683))
+        (PORT datac (197:197:197) (264:264:264))
+        (PORT datad (275:275:275) (357:357:357))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datab combout (275:275:275) (275:275:275))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (897:897:897) (1037:1037:1037))
+        (PORT datab (223:223:223) (293:293:293))
+        (PORT datac (799:799:799) (864:864:864))
+        (PORT datad (276:276:276) (355:355:355))
+        (IOPATH dataa combout (267:267:267) (269:269:269))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datac combout (218:218:218) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|data_out\[9\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (174:174:174) (205:205:205))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1307:1307:1307) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (225:225:225) (299:299:299))
+        (PORT datab (298:298:298) (388:388:388))
+        (PORT datac (1173:1173:1173) (1200:1200:1200))
+        (PORT datad (876:876:876) (984:984:984))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (901:901:901) (1032:1032:1032))
+        (PORT datac (196:196:196) (263:263:263))
+        (PORT datad (275:275:275) (351:351:351))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (905:905:905) (1030:1030:1030))
+        (PORT datac (196:196:196) (263:263:263))
+        (PORT datad (270:270:270) (350:350:350))
+        (IOPATH dataa combout (273:273:273) (269:269:269))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (896:896:896) (1033:1033:1033))
+        (PORT datac (198:198:198) (266:266:266))
+        (PORT datad (277:277:277) (356:356:356))
+        (IOPATH dataa combout (287:287:287) (280:280:280))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (906:906:906) (1035:1035:1035))
+        (PORT datab (303:303:303) (392:392:392))
+        (PORT datad (200:200:200) (257:257:257))
+        (IOPATH dataa combout (265:265:265) (269:269:269))
+        (IOPATH datab combout (267:267:267) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1316:1316:1316))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCK\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (377:377:377) (433:433:433))
+        (PORT datab (239:239:239) (308:308:308))
+        (PORT datac (576:576:576) (623:623:623))
+        (PORT datad (1179:1179:1179) (1286:1286:1286))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH datab combout (295:295:295) (294:294:294))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (197:197:197) (239:239:239))
+        (PORT datac (217:217:217) (295:295:295))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datac combout (218:218:218) (215:215:215))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_ld)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1300:1300:1300) (1319:1319:1319))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[9\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (736:736:736) (991:991:991))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (456:456:456) (514:514:514))
+        (PORT datab (2660:2660:2660) (2855:2855:2855))
+        (PORT datac (245:245:245) (336:336:336))
+        (PORT datad (225:225:225) (293:293:293))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH datab combout (308:308:308) (300:300:300))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (335:335:335))
+        (PORT datab (247:247:247) (331:331:331))
+        (PORT datac (159:159:159) (190:190:190))
+        (PORT datad (236:236:236) (303:303:303))
+        (IOPATH dataa combout (299:299:299) (304:304:304))
+        (IOPATH datab combout (300:300:300) (312:312:312))
+        (IOPATH datac combout (220:220:220) (215:215:215))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_din)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1302:1302:1302) (1323:1323:1323))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[1\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (412:412:412) (449:449:449))
+        (PORT datab (239:239:239) (308:308:308))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[2\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (313:313:313))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[3\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (240:240:240) (309:309:309))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[4\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (242:242:242) (316:316:316))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[5\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (242:242:242) (316:316:316))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[6\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (311:311:311))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[7\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (311:311:311))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[8\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (311:311:311))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[9\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (218:218:218) (276:276:276))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1327:1327:1327))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1111:1111:1111) (1122:1122:1122))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1668:1668:1668) (1717:1717:1717))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (921:921:921) (938:938:938))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1097:1097:1097) (1098:1098:1098))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1667:1667:1667) (1722:1722:1722))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1108:1108:1108) (1109:1109:1109))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1261:1261:1261) (1286:1286:1286))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1276:1276:1276) (1329:1329:1329))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1370:1370:1370) (1363:1363:1363))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1310:1310:1310) (1328:1328:1328))
+        (PORT asdata (1571:1571:1571) (1599:1599:1599))
+        (PORT ena (980:980:980) (1011:1011:1011))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (144:144:144))
+      (HOLD ena (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (293:293:293))
+        (PORT datab (851:851:851) (862:862:862))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (420:420:420) (451:451:451))
+        (PORT datab (221:221:221) (289:289:289))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (296:296:296))
+        (PORT datab (586:586:586) (619:619:619))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (295:295:295))
+        (PORT datab (412:412:412) (444:444:444))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (393:393:393) (448:448:448))
+        (PORT datab (379:379:379) (423:423:423))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (632:632:632) (653:653:653))
+        (PORT datab (221:221:221) (290:290:290))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (631:631:631) (654:654:654))
+        (PORT datab (221:221:221) (290:290:290))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (598:598:598) (630:630:630))
+        (PORT datab (221:221:221) (291:291:291))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (294:294:294))
+        (PORT datab (411:411:411) (443:443:443))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (380:380:380) (427:427:427))
+        (PORT datab (221:221:221) (289:289:289))
+        (IOPATH dataa combout (318:318:318) (307:307:307))
+        (IOPATH datab combout (336:336:336) (337:337:337))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|pwm_out\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (786:786:786) (774:774:774))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|pwm_out)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1306:1306:1306) (1322:1322:1322))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+)
diff --git a/part_4/ex16/simulation/modelsim/top_6_1200mv_85c_slow.vo b/part_4/ex16/simulation/modelsim/top_6_1200mv_85c_slow.vo
new file mode 100755
index 0000000..707d2b5
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_6_1200mv_85c_slow.vo
@@ -0,0 +1,9959 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 32-bit"
+// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+// DATE "02/18/2014 18:26:56"
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module top (
+	CLOCK_50,
+	SW,
+	HEX0_D,
+	HEX1_D,
+	HEX2_D,
+	HEX3_D,
+	DAC_SDI,
+	SCK,
+	DAC_CS,
+	DAC_LD,
+	ADC_SDI,
+	ADC_CS,
+	ADC_SDO,
+	LEDG,
+	PWM_OUT);
+input 	CLOCK_50;
+input 	[9:0] SW;
+output 	[6:0] HEX0_D;
+output 	[6:0] HEX1_D;
+output 	[6:0] HEX2_D;
+output 	[6:0] HEX3_D;
+output 	DAC_SDI;
+output 	SCK;
+output 	DAC_CS;
+output 	DAC_LD;
+output 	ADC_SDI;
+output 	ADC_CS;
+input 	ADC_SDO;
+output 	[9:0] LEDG;
+output 	PWM_OUT;
+
+// Design Ports Information
+// HEX0_D[0]	=>  Location: PIN_E11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[1]	=>  Location: PIN_F11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[2]	=>  Location: PIN_H12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[3]	=>  Location: PIN_H13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[4]	=>  Location: PIN_G12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[5]	=>  Location: PIN_F12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[6]	=>  Location: PIN_F13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[0]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[1]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[2]	=>  Location: PIN_C13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[3]	=>  Location: PIN_A14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[4]	=>  Location: PIN_B14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[5]	=>  Location: PIN_E14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[6]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[0]	=>  Location: PIN_D15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[1]	=>  Location: PIN_A16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[2]	=>  Location: PIN_B16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[3]	=>  Location: PIN_E15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[4]	=>  Location: PIN_A17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[5]	=>  Location: PIN_B17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[6]	=>  Location: PIN_F14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[0]	=>  Location: PIN_B18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[1]	=>  Location: PIN_F15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[2]	=>  Location: PIN_A19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[3]	=>  Location: PIN_B19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[4]	=>  Location: PIN_C19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[5]	=>  Location: PIN_D19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[6]	=>  Location: PIN_G15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_SDI	=>  Location: PIN_V5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SCK	=>  Location: PIN_W10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_CS	=>  Location: PIN_V12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_LD	=>  Location: PIN_W13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// ADC_SDI	=>  Location: PIN_V8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// ADC_CS	=>  Location: PIN_W6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[0]	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[1]	=>  Location: PIN_J2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[2]	=>  Location: PIN_J3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[3]	=>  Location: PIN_H1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[4]	=>  Location: PIN_F2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[5]	=>  Location: PIN_E1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[6]	=>  Location: PIN_C1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[7]	=>  Location: PIN_C2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[8]	=>  Location: PIN_B2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[9]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// PWM_OUT	=>  Location: PIN_U14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SW[3]	=>  Location: PIN_G4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[2]	=>  Location: PIN_H6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[1]	=>  Location: PIN_H5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[0]	=>  Location: PIN_J6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[7]	=>  Location: PIN_E3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[6]	=>  Location: PIN_H7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[5]	=>  Location: PIN_J7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[4]	=>  Location: PIN_G5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[8]	=>  Location: PIN_E4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// CLOCK_50	=>  Location: PIN_G21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[9]	=>  Location: PIN_D2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ADC_SDO	=>  Location: PIN_U7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("top_6_1200mv_85c_v_slow.sdo");
+// synopsys translate_on
+
+wire \HEX0_D[0]~output_o ;
+wire \HEX0_D[1]~output_o ;
+wire \HEX0_D[2]~output_o ;
+wire \HEX0_D[3]~output_o ;
+wire \HEX0_D[4]~output_o ;
+wire \HEX0_D[5]~output_o ;
+wire \HEX0_D[6]~output_o ;
+wire \HEX1_D[0]~output_o ;
+wire \HEX1_D[1]~output_o ;
+wire \HEX1_D[2]~output_o ;
+wire \HEX1_D[3]~output_o ;
+wire \HEX1_D[4]~output_o ;
+wire \HEX1_D[5]~output_o ;
+wire \HEX1_D[6]~output_o ;
+wire \HEX2_D[0]~output_o ;
+wire \HEX2_D[1]~output_o ;
+wire \HEX2_D[2]~output_o ;
+wire \HEX2_D[3]~output_o ;
+wire \HEX2_D[4]~output_o ;
+wire \HEX2_D[5]~output_o ;
+wire \HEX2_D[6]~output_o ;
+wire \HEX3_D[0]~output_o ;
+wire \HEX3_D[1]~output_o ;
+wire \HEX3_D[2]~output_o ;
+wire \HEX3_D[3]~output_o ;
+wire \HEX3_D[4]~output_o ;
+wire \HEX3_D[5]~output_o ;
+wire \HEX3_D[6]~output_o ;
+wire \DAC_SDI~output_o ;
+wire \SCK~output_o ;
+wire \DAC_CS~output_o ;
+wire \DAC_LD~output_o ;
+wire \ADC_SDI~output_o ;
+wire \ADC_CS~output_o ;
+wire \LEDG[0]~output_o ;
+wire \LEDG[1]~output_o ;
+wire \LEDG[2]~output_o ;
+wire \LEDG[3]~output_o ;
+wire \LEDG[4]~output_o ;
+wire \LEDG[5]~output_o ;
+wire \LEDG[6]~output_o ;
+wire \LEDG[7]~output_o ;
+wire \LEDG[8]~output_o ;
+wire \LEDG[9]~output_o ;
+wire \PWM_OUT~output_o ;
+wire \SW[8]~input_o ;
+wire \SW[7]~input_o ;
+wire \SW[6]~input_o ;
+wire \SW[5]~input_o ;
+wire \SW[4]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ;
+wire \SW[3]~input_o ;
+wire \SW[2]~input_o ;
+wire \SW[0]~input_o ;
+wire \SW[1]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ;
+wire \BCD_CONVERT|A9|WideOr2~0_combout ;
+wire \BCD_CONVERT|A9|WideOr1~combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ;
+wire \BCD_CONVERT|A9|WideOr3~0_combout ;
+wire \BCD_CONVERT|A12|WideOr1~0_combout ;
+wire \BCD_CONVERT|A12|WideOr2~0_combout ;
+wire \BCD_CONVERT|A12|WideOr3~0_combout ;
+wire \BCD_CONVERT|A15|WideOr1~0_combout ;
+wire \BCD_CONVERT|A15|WideOr3~0_combout ;
+wire \BCD_CONVERT|A15|WideOr2~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ;
+wire \BCD_CONVERT|A18|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ;
+wire \BCD_CONVERT|A18|WideOr2~0_combout ;
+wire \BCD_CONVERT|A18|WideOr3~0_combout ;
+wire \BCD_CONVERT|A21|WideOr1~0_combout ;
+wire \BCD_CONVERT|A21|WideOr2~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ;
+wire \BCD_CONVERT|A21|WideOr3~0_combout ;
+wire \BCD_CONVERT|A25|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ;
+wire \BCD_CONVERT|A25|WideOr2~0_combout ;
+wire \BCD_CONVERT|A25|WideOr3~0_combout ;
+wire \SEG0|WideOr6~0_combout ;
+wire \SEG0|WideOr5~0_combout ;
+wire \SEG0|WideOr4~0_combout ;
+wire \SEG0|WideOr3~0_combout ;
+wire \SEG0|WideOr2~0_combout ;
+wire \SEG0|WideOr1~0_combout ;
+wire \SEG0|WideOr0~0_combout ;
+wire \BCD_CONVERT|A9|Decoder0~0_combout ;
+wire \BCD_CONVERT|A9|WideOr0~0_combout ;
+wire \BCD_CONVERT|A9|WideOr0~1_combout ;
+wire \BCD_CONVERT|A15|WideOr0~0_combout ;
+wire \BCD_CONVERT|A7|WideOr0~0_combout ;
+wire \BCD_CONVERT|A12|WideOr0~0_combout ;
+wire \BCD_CONVERT|A17|Decoder0~5_combout ;
+wire \BCD_CONVERT|A17|WideOr2~3_combout ;
+wire \BCD_CONVERT|A17|WideOr2~7_combout ;
+wire \BCD_CONVERT|A17|Decoder0~3_combout ;
+wire \BCD_CONVERT|A17|WideOr2~6_combout ;
+wire \BCD_CONVERT|A7|WideOr0~1_combout ;
+wire \BCD_CONVERT|A17|WideOr3~0_combout ;
+wire \BCD_CONVERT|A17|Decoder0~4_combout ;
+wire \BCD_CONVERT|A17|WideOr3~1_combout ;
+wire \BCD_CONVERT|A17|Decoder0~2_combout ;
+wire \BCD_CONVERT|A17|Decoder0~6_combout ;
+wire \BCD_CONVERT|A17|WideOr1~0_combout ;
+wire \BCD_CONVERT|A18|WideOr0~0_combout ;
+wire \BCD_CONVERT|A20|WideOr2~0_combout ;
+wire \BCD_CONVERT|A20|WideOr1~0_combout ;
+wire \BCD_CONVERT|A21|WideOr0~0_combout ;
+wire \BCD_CONVERT|A20|WideOr3~0_combout ;
+wire \BCD_CONVERT|A24|WideOr1~0_combout ;
+wire \BCD_CONVERT|A24|WideOr3~0_combout ;
+wire \BCD_CONVERT|A24|WideOr2~0_combout ;
+wire \BCD_CONVERT|A25|WideOr0~0_combout ;
+wire \SEG1|WideOr6~0_combout ;
+wire \SEG1|WideOr5~0_combout ;
+wire \SEG1|WideOr4~0_combout ;
+wire \SEG1|WideOr3~0_combout ;
+wire \SEG1|WideOr2~0_combout ;
+wire \SEG1|WideOr1~0_combout ;
+wire \SEG1|WideOr0~0_combout ;
+wire \BCD_CONVERT|A24|WideOr0~0_combout ;
+wire \BCD_CONVERT|A14|WideOr0~2_combout ;
+wire \BCD_CONVERT|A17|Decoder0~7_combout ;
+wire \BCD_CONVERT|A17|WideOr0~0_combout ;
+wire \BCD_CONVERT|A17|WideOr0~combout ;
+wire \BCD_CONVERT|A20|WideOr0~0_combout ;
+wire \SEG2|Decoder0~0_combout ;
+wire \SEG2|Decoder0~1_combout ;
+wire \SEG2|WideOr6~combout ;
+wire \SEG2|Decoder0~2_combout ;
+wire \SEG2|Decoder0~3_combout ;
+wire \SEG2|WideOr5~combout ;
+wire \SEG2|Decoder0~4_combout ;
+wire \SEG2|Decoder0~5_combout ;
+wire \SEG2|Decoder0~6_combout ;
+wire \SEG2|WideOr2~0_combout ;
+wire \SEG2|Decoder0~7_combout ;
+wire \SEG2|WideOr2~combout ;
+wire \SEG2|WideOr1~combout ;
+wire \SEG2|Decoder0~8_combout ;
+wire \SEG2|WideOr0~combout ;
+wire \BCD_CONVERT|A23|WideOr0~5_combout ;
+wire \BCD_CONVERT|A23|WideOr0~17_combout ;
+wire \CLOCK_50~input_o ;
+wire \SPI_DAC|clk_1MHz~0_combout ;
+wire \CLOCK_50~inputclkctrl_outclk ;
+wire \SPI_ADC|Add0~0_combout ;
+wire \SPI_ADC|Add0~7 ;
+wire \SPI_ADC|Add0~8_combout ;
+wire \SPI_ADC|ctr~0_combout ;
+wire \SPI_ADC|Add0~1 ;
+wire \SPI_ADC|Add0~2_combout ;
+wire \SPI_ADC|ctr~1_combout ;
+wire \SPI_ADC|Add0~3 ;
+wire \SPI_ADC|Add0~4_combout ;
+wire \SPI_ADC|ctr~2_combout ;
+wire \SPI_ADC|Add0~5 ;
+wire \SPI_ADC|Add0~6_combout ;
+wire \SPI_DAC|Equal0~0_combout ;
+wire \SPI_DAC|Equal0~1_combout ;
+wire \SPI_DAC|clk_1MHz~q ;
+wire \SPI_DAC|clk_1MHz~clkctrl_outclk ;
+wire \PWM_DC|count[0]~27_combout ;
+wire \GEN_10K|Add0~23 ;
+wire \GEN_10K|Add0~24_combout ;
+wire \GEN_10K|ctr~6_combout ;
+wire \GEN_10K|Add0~25 ;
+wire \GEN_10K|Add0~26_combout ;
+wire \GEN_10K|ctr~7_combout ;
+wire \GEN_10K|Add0~27 ;
+wire \GEN_10K|Add0~28_combout ;
+wire \GEN_10K|ctr~8_combout ;
+wire \GEN_10K|Add0~29 ;
+wire \GEN_10K|Add0~30_combout ;
+wire \GEN_10K|ctr~9_combout ;
+wire \GEN_10K|Add0~31 ;
+wire \GEN_10K|Add0~32_combout ;
+wire \GEN_10K|ctr~10_combout ;
+wire \GEN_10K|Add0~33 ;
+wire \GEN_10K|Add0~34_combout ;
+wire \GEN_10K|ctr~11_combout ;
+wire \GEN_10K|Add0~35 ;
+wire \GEN_10K|Add0~36_combout ;
+wire \GEN_10K|ctr~12_combout ;
+wire \GEN_10K|Add0~37 ;
+wire \GEN_10K|Add0~38_combout ;
+wire \GEN_10K|ctr~13_combout ;
+wire \GEN_10K|Add0~39 ;
+wire \GEN_10K|Add0~40_combout ;
+wire \GEN_10K|ctr~14_combout ;
+wire \GEN_10K|Equal0~5_combout ;
+wire \GEN_10K|Add0~1_cout ;
+wire \GEN_10K|Add0~2_combout ;
+wire \GEN_10K|Add0~3 ;
+wire \GEN_10K|Add0~4_combout ;
+wire \GEN_10K|ctr~0_combout ;
+wire \GEN_10K|Add0~5 ;
+wire \GEN_10K|Add0~6_combout ;
+wire \GEN_10K|ctr~1_combout ;
+wire \GEN_10K|Add0~7 ;
+wire \GEN_10K|Add0~8_combout ;
+wire \GEN_10K|ctr~2_combout ;
+wire \GEN_10K|Add0~9 ;
+wire \GEN_10K|Add0~10_combout ;
+wire \GEN_10K|ctr~3_combout ;
+wire \GEN_10K|Add0~11 ;
+wire \GEN_10K|Add0~12_combout ;
+wire \GEN_10K|Add0~13 ;
+wire \GEN_10K|Add0~14_combout ;
+wire \GEN_10K|Add0~15 ;
+wire \GEN_10K|Add0~16_combout ;
+wire \GEN_10K|Add0~17 ;
+wire \GEN_10K|Add0~18_combout ;
+wire \GEN_10K|ctr~4_combout ;
+wire \GEN_10K|Add0~19 ;
+wire \GEN_10K|Add0~20_combout ;
+wire \GEN_10K|ctr~5_combout ;
+wire \GEN_10K|Add0~21 ;
+wire \GEN_10K|Add0~22_combout ;
+wire \GEN_10K|Equal0~2_combout ;
+wire \GEN_10K|Equal0~0_combout ;
+wire \GEN_10K|Equal0~1_combout ;
+wire \GEN_10K|Equal0~3_combout ;
+wire \GEN_10K|Equal0~4_combout ;
+wire \GEN_10K|clkout~0_combout ;
+wire \GEN_10K|clkout~q ;
+wire \PULSE|state.IDLE~feeder_combout ;
+wire \PULSE|state.IDLE~q ;
+wire \PULSE|pulse~1_combout ;
+wire \PULSE|pulse~q ;
+wire \SPI_DAC|Selector2~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_DAC|Selector0~0_combout ;
+wire \SPI_DAC|sr_state.IDLE~q ;
+wire \SPI_DAC|Selector1~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_DAC|dac_start~0_combout ;
+wire \SPI_DAC|dac_start~1_combout ;
+wire \SPI_DAC|dac_start~q ;
+wire \SPI_DAC|state[0]~5_combout ;
+wire \SPI_DAC|state[3]~12 ;
+wire \SPI_DAC|state[4]~13_combout ;
+wire \SPI_DAC|Selector8~0_combout ;
+wire \SPI_DAC|state[0]~6 ;
+wire \SPI_DAC|state[1]~7_combout ;
+wire \SPI_DAC|state[1]~8 ;
+wire \SPI_DAC|state[2]~9_combout ;
+wire \SPI_DAC|state[2]~10 ;
+wire \SPI_DAC|state[3]~11_combout ;
+wire \SPI_DAC|Equal1~0_combout ;
+wire \SPI_DAC|Selector9~0_combout ;
+wire \SPI_DAC|dac_cs~q ;
+wire \SPI_ADC|clk_1MHz~0_combout ;
+wire \SPI_ADC|clk_1MHz~q ;
+wire \SPI_ADC|clk_1MHz~clkctrl_outclk ;
+wire \ADC_SDO~input_o ;
+wire \SPI_ADC|Selector2~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_ADC|Selector0~0_combout ;
+wire \SPI_ADC|sr_state.IDLE~q ;
+wire \SPI_ADC|Selector1~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_ADC|adc_start~0_combout ;
+wire \SPI_ADC|adc_start~1_combout ;
+wire \SPI_ADC|adc_start~q ;
+wire \SPI_ADC|Add1~5 ;
+wire \SPI_ADC|Add1~6_combout ;
+wire \SPI_ADC|Add1~7 ;
+wire \SPI_ADC|Add1~8_combout ;
+wire \SPI_ADC|state~1_combout ;
+wire \SPI_ADC|Selector4~2_combout ;
+wire \SPI_ADC|Add1~0_combout ;
+wire \SPI_ADC|Selector5~0_combout ;
+wire \SPI_ADC|Add1~1 ;
+wire \SPI_ADC|Add1~2_combout ;
+wire \SPI_ADC|Add1~3 ;
+wire \SPI_ADC|Add1~4_combout ;
+wire \SPI_ADC|state~0_combout ;
+wire \SPI_ADC|Selector4~3_combout ;
+wire \SPI_ADC|adc_cs~q ;
+wire \SPI_ADC|WideOr0~0_combout ;
+wire \SPI_ADC|WideOr0~1_combout ;
+wire \SPI_ADC|shift_ena~q ;
+wire \SPI_ADC|always3~0_combout ;
+wire \SPI_ADC|shift_reg[1]~feeder_combout ;
+wire \SPI_ADC|shift_reg[3]~feeder_combout ;
+wire \SPI_ADC|shift_reg[5]~feeder_combout ;
+wire \SPI_ADC|shift_reg[6]~feeder_combout ;
+wire \SPI_ADC|Decoder0~0_combout ;
+wire \SPI_ADC|Decoder0~1_combout ;
+wire \SPI_ADC|adc_done~q ;
+wire \DUMMY|PULSE2|state.IDLE~0_combout ;
+wire \DUMMY|PULSE2|state.IDLE~q ;
+wire \DUMMY|PULSE2|pulse~1_combout ;
+wire \DUMMY|PULSE2|pulse~q ;
+wire \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ;
+wire \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ;
+wire \SPI_ADC|shift_reg[9]~feeder_combout ;
+wire \SPI_ADC|adc_cs~clkctrl_outclk ;
+wire \DUMMY|ctr[0]~36_combout ;
+wire \DUMMY|ctr[1]~12_combout ;
+wire \DUMMY|ctr[1]~13 ;
+wire \DUMMY|ctr[2]~14_combout ;
+wire \DUMMY|ctr[2]~15 ;
+wire \DUMMY|ctr[3]~16_combout ;
+wire \DUMMY|ctr[3]~17 ;
+wire \DUMMY|ctr[4]~18_combout ;
+wire \DUMMY|wraddr[4]~0_combout ;
+wire \DUMMY|ctr[4]~19 ;
+wire \DUMMY|ctr[5]~20_combout ;
+wire \DUMMY|wraddr[4]~1 ;
+wire \DUMMY|wraddr[5]~2_combout ;
+wire \DUMMY|ctr[5]~21 ;
+wire \DUMMY|ctr[6]~22_combout ;
+wire \DUMMY|wraddr[5]~3 ;
+wire \DUMMY|wraddr[6]~4_combout ;
+wire \DUMMY|ctr[6]~23 ;
+wire \DUMMY|ctr[7]~24_combout ;
+wire \DUMMY|wraddr[6]~5 ;
+wire \DUMMY|wraddr[7]~6_combout ;
+wire \DUMMY|ctr[7]~25 ;
+wire \DUMMY|ctr[8]~26_combout ;
+wire \DUMMY|wraddr[7]~7 ;
+wire \DUMMY|wraddr[8]~8_combout ;
+wire \DUMMY|ctr[8]~27 ;
+wire \DUMMY|ctr[9]~28_combout ;
+wire \DUMMY|wraddr[8]~9 ;
+wire \DUMMY|wraddr[9]~10_combout ;
+wire \DUMMY|ctr[9]~29 ;
+wire \DUMMY|ctr[10]~30_combout ;
+wire \DUMMY|wraddr[9]~11 ;
+wire \DUMMY|wraddr[10]~12_combout ;
+wire \DUMMY|ctr[10]~31 ;
+wire \DUMMY|ctr[11]~32_combout ;
+wire \DUMMY|wraddr[10]~13 ;
+wire \DUMMY|wraddr[11]~14_combout ;
+wire \DUMMY|ctr[11]~33 ;
+wire \DUMMY|ctr[12]~34_combout ;
+wire \DUMMY|wraddr[11]~15 ;
+wire \DUMMY|wraddr[12]~16_combout ;
+wire \SPI_ADC|data_from_adc[5]~feeder_combout ;
+wire \DUMMY|Add0~12_combout ;
+wire \SPI_ADC|data_from_adc[4]~feeder_combout ;
+wire \DUMMY|Add0~10_combout ;
+wire \DUMMY|Add0~8_combout ;
+wire \SPI_ADC|data_from_adc[2]~feeder_combout ;
+wire \DUMMY|Add0~6_combout ;
+wire \DUMMY|Add0~4_combout ;
+wire \DUMMY|Add0~2_combout ;
+wire \SPI_ADC|data_from_adc[0]~feeder_combout ;
+wire \DUMMY|Add0~1 ;
+wire \DUMMY|Add0~3 ;
+wire \DUMMY|Add0~5 ;
+wire \DUMMY|Add0~7 ;
+wire \DUMMY|Add0~9 ;
+wire \DUMMY|Add0~11 ;
+wire \DUMMY|Add0~13 ;
+wire \DUMMY|Add0~15 ;
+wire \DUMMY|Add0~17 ;
+wire \DUMMY|Add0~18_combout ;
+wire \DUMMY|Add3~1 ;
+wire \DUMMY|Add3~3 ;
+wire \DUMMY|Add3~4_combout ;
+wire \DUMMY|Add0~16_combout ;
+wire \DUMMY|Add3~2_combout ;
+wire \DUMMY|Add0~14_combout ;
+wire \DUMMY|Add3~0_combout ;
+wire \DUMMY|Add0~0_combout ;
+wire \SPI_DAC|shift_reg~13_combout ;
+wire \SPI_DAC|shift_reg~12_combout ;
+wire \SPI_DAC|shift_reg~11_combout ;
+wire \SPI_DAC|shift_reg~10_combout ;
+wire \SPI_DAC|shift_reg~9_combout ;
+wire \SPI_DAC|shift_reg~8_combout ;
+wire \SPI_DAC|shift_reg~7_combout ;
+wire \SPI_DAC|shift_reg~6_combout ;
+wire \SPI_DAC|shift_reg~5_combout ;
+wire \DUMMY|data_out[9]~0_combout ;
+wire \SPI_DAC|shift_reg~4_combout ;
+wire \SPI_DAC|shift_reg~3_combout ;
+wire \SPI_DAC|shift_reg~2_combout ;
+wire \SPI_DAC|shift_reg~1_combout ;
+wire \SPI_DAC|shift_reg~0_combout ;
+wire \SCK~0_combout ;
+wire \SPI_DAC|Equal2~0_combout ;
+wire \SPI_DAC|dac_ld~q ;
+wire \SW[9]~input_o ;
+wire \SPI_ADC|Selector6~0_combout ;
+wire \SPI_ADC|Selector6~1_combout ;
+wire \SPI_ADC|adc_din~q ;
+wire \PWM_DC|count[1]~9_combout ;
+wire \PWM_DC|count[1]~10 ;
+wire \PWM_DC|count[2]~11_combout ;
+wire \PWM_DC|count[2]~12 ;
+wire \PWM_DC|count[3]~13_combout ;
+wire \PWM_DC|count[3]~14 ;
+wire \PWM_DC|count[4]~15_combout ;
+wire \PWM_DC|count[4]~16 ;
+wire \PWM_DC|count[5]~17_combout ;
+wire \PWM_DC|count[5]~18 ;
+wire \PWM_DC|count[6]~19_combout ;
+wire \PWM_DC|count[6]~20 ;
+wire \PWM_DC|count[7]~21_combout ;
+wire \PWM_DC|count[7]~22 ;
+wire \PWM_DC|count[8]~23_combout ;
+wire \PWM_DC|count[8]~24 ;
+wire \PWM_DC|count[9]~25_combout ;
+wire \PWM_DC|LessThan0~1_cout ;
+wire \PWM_DC|LessThan0~3_cout ;
+wire \PWM_DC|LessThan0~5_cout ;
+wire \PWM_DC|LessThan0~7_cout ;
+wire \PWM_DC|LessThan0~9_cout ;
+wire \PWM_DC|LessThan0~11_cout ;
+wire \PWM_DC|LessThan0~13_cout ;
+wire \PWM_DC|LessThan0~15_cout ;
+wire \PWM_DC|LessThan0~17_cout ;
+wire \PWM_DC|LessThan0~18_combout ;
+wire \PWM_DC|pwm_out~0_combout ;
+wire \PWM_DC|pwm_out~q ;
+wire [20:0] \GEN_10K|ctr ;
+wire [4:0] \SPI_DAC|state ;
+wire [15:0] \SPI_DAC|shift_reg ;
+wire [9:0] \PWM_DC|d ;
+wire [9:0] \PWM_DC|count ;
+wire [4:0] \SPI_ADC|state ;
+wire [9:0] \SPI_ADC|shift_reg ;
+wire [9:0] \SPI_ADC|data_from_adc ;
+wire [4:0] \SPI_ADC|ctr ;
+wire [9:0] \DUMMY|data_out ;
+wire [12:0] \DUMMY|ctr ;
+wire [8:0] \DUMMY|DELAY|altsyncram_component|auto_generated|q_b ;
+
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
+
+// Location: IOOBUF_X21_Y29_N23
+cycloneiii_io_obuf \HEX0_D[0]~output (
+	.i(\SEG0|WideOr6~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[0]~output .bus_hold = "false";
+defparam \HEX0_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N30
+cycloneiii_io_obuf \HEX0_D[1]~output (
+	.i(\SEG0|WideOr5~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[1]~output .bus_hold = "false";
+defparam \HEX0_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N2
+cycloneiii_io_obuf \HEX0_D[2]~output (
+	.i(\SEG0|WideOr4~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[2]~output .bus_hold = "false";
+defparam \HEX0_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N30
+cycloneiii_io_obuf \HEX0_D[3]~output (
+	.i(\SEG0|WideOr3~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[3]~output .bus_hold = "false";
+defparam \HEX0_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N9
+cycloneiii_io_obuf \HEX0_D[4]~output (
+	.i(\SEG0|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[4]~output .bus_hold = "false";
+defparam \HEX0_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N23
+cycloneiii_io_obuf \HEX0_D[5]~output (
+	.i(\SEG0|WideOr1~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[5]~output .bus_hold = "false";
+defparam \HEX0_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N16
+cycloneiii_io_obuf \HEX0_D[6]~output (
+	.i(!\SEG0|WideOr0~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[6]~output .bus_hold = "false";
+defparam \HEX0_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N2
+cycloneiii_io_obuf \HEX1_D[0]~output (
+	.i(!\SEG1|WideOr6~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[0]~output .bus_hold = "false";
+defparam \HEX1_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N9
+cycloneiii_io_obuf \HEX1_D[1]~output (
+	.i(\SEG1|WideOr5~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[1]~output .bus_hold = "false";
+defparam \HEX1_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N2
+cycloneiii_io_obuf \HEX1_D[2]~output (
+	.i(\SEG1|WideOr4~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[2]~output .bus_hold = "false";
+defparam \HEX1_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N23
+cycloneiii_io_obuf \HEX1_D[3]~output (
+	.i(!\SEG1|WideOr3~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[3]~output .bus_hold = "false";
+defparam \HEX1_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N30
+cycloneiii_io_obuf \HEX1_D[4]~output (
+	.i(!\SEG1|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[4]~output .bus_hold = "false";
+defparam \HEX1_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N16
+cycloneiii_io_obuf \HEX1_D[5]~output (
+	.i(!\SEG1|WideOr1~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[5]~output .bus_hold = "false";
+defparam \HEX1_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N23
+cycloneiii_io_obuf \HEX1_D[6]~output (
+	.i(!\SEG1|WideOr0~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[6]~output .bus_hold = "false";
+defparam \HEX1_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N30
+cycloneiii_io_obuf \HEX2_D[0]~output (
+	.i(\SEG2|WideOr6~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[0]~output .bus_hold = "false";
+defparam \HEX2_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N30
+cycloneiii_io_obuf \HEX2_D[1]~output (
+	.i(\SEG2|WideOr5~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[1]~output .bus_hold = "false";
+defparam \HEX2_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N2
+cycloneiii_io_obuf \HEX2_D[2]~output (
+	.i(\SEG2|Decoder0~4_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[2]~output .bus_hold = "false";
+defparam \HEX2_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N2
+cycloneiii_io_obuf \HEX2_D[3]~output (
+	.i(!\SEG2|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[3]~output .bus_hold = "false";
+defparam \HEX2_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N16
+cycloneiii_io_obuf \HEX2_D[4]~output (
+	.i(\SEG2|WideOr2~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[4]~output .bus_hold = "false";
+defparam \HEX2_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N23
+cycloneiii_io_obuf \HEX2_D[5]~output (
+	.i(\SEG2|WideOr1~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[5]~output .bus_hold = "false";
+defparam \HEX2_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N2
+cycloneiii_io_obuf \HEX2_D[6]~output (
+	.i(\SEG2|WideOr0~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[6]~output .bus_hold = "false";
+defparam \HEX2_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N23
+cycloneiii_io_obuf \HEX3_D[0]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[0]~output .bus_hold = "false";
+defparam \HEX3_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y29_N16
+cycloneiii_io_obuf \HEX3_D[1]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[1]~output .bus_hold = "false";
+defparam \HEX3_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N9
+cycloneiii_io_obuf \HEX3_D[2]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[2]~output .bus_hold = "false";
+defparam \HEX3_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N2
+cycloneiii_io_obuf \HEX3_D[3]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[3]~output .bus_hold = "false";
+defparam \HEX3_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N23
+cycloneiii_io_obuf \HEX3_D[4]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[4]~output .bus_hold = "false";
+defparam \HEX3_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N30
+cycloneiii_io_obuf \HEX3_D[5]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[5]~output .bus_hold = "false";
+defparam \HEX3_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y29_N30
+cycloneiii_io_obuf \HEX3_D[6]~output (
+	.i(vcc),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[6]~output .bus_hold = "false";
+defparam \HEX3_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X3_Y0_N30
+cycloneiii_io_obuf \DAC_SDI~output (
+	.i(\SPI_DAC|shift_reg [15]),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_SDI~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SDI~output .bus_hold = "false";
+defparam \DAC_SDI~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X19_Y0_N16
+cycloneiii_io_obuf \SCK~output (
+	.i(\SCK~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\SCK~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \SCK~output .bus_hold = "false";
+defparam \SCK~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y0_N2
+cycloneiii_io_obuf \DAC_CS~output (
+	.i(!\SPI_DAC|dac_cs~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_CS~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_CS~output .bus_hold = "false";
+defparam \DAC_CS~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y0_N30
+cycloneiii_io_obuf \DAC_LD~output (
+	.i(\SPI_DAC|dac_ld~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_LD~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_LD~output .bus_hold = "false";
+defparam \DAC_LD~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X11_Y0_N30
+cycloneiii_io_obuf \ADC_SDI~output (
+	.i(\SPI_ADC|adc_din~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\ADC_SDI~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SDI~output .bus_hold = "false";
+defparam \ADC_SDI~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X7_Y0_N23
+cycloneiii_io_obuf \ADC_CS~output (
+	.i(!\SPI_ADC|adc_cs~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\ADC_CS~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \ADC_CS~output .bus_hold = "false";
+defparam \ADC_CS~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N9
+cycloneiii_io_obuf \LEDG[0]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[0]~output .bus_hold = "false";
+defparam \LEDG[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N2
+cycloneiii_io_obuf \LEDG[1]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[1]~output .bus_hold = "false";
+defparam \LEDG[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N23
+cycloneiii_io_obuf \LEDG[2]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[2]~output .bus_hold = "false";
+defparam \LEDG[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N16
+cycloneiii_io_obuf \LEDG[3]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[3]~output .bus_hold = "false";
+defparam \LEDG[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y24_N23
+cycloneiii_io_obuf \LEDG[4]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[4]~output .bus_hold = "false";
+defparam \LEDG[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y24_N16
+cycloneiii_io_obuf \LEDG[5]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[5]~output .bus_hold = "false";
+defparam \LEDG[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N23
+cycloneiii_io_obuf \LEDG[6]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[6]~output .bus_hold = "false";
+defparam \LEDG[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N16
+cycloneiii_io_obuf \LEDG[7]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[7]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[7]~output .bus_hold = "false";
+defparam \LEDG[7]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y27_N9
+cycloneiii_io_obuf \LEDG[8]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[8]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[8]~output .bus_hold = "false";
+defparam \LEDG[8]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y27_N16
+cycloneiii_io_obuf \LEDG[9]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[9]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[9]~output .bus_hold = "false";
+defparam \LEDG[9]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y0_N23
+cycloneiii_io_obuf \PWM_OUT~output (
+	.i(\PWM_DC|pwm_out~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\PWM_OUT~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \PWM_OUT~output .bus_hold = "false";
+defparam \PWM_OUT~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y26_N1
+cycloneiii_io_ibuf \SW[8]~input (
+	.i(SW[8]),
+	.ibar(gnd),
+	.o(\SW[8]~input_o ));
+// synopsys translate_off
+defparam \SW[8]~input .bus_hold = "false";
+defparam \SW[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y26_N8
+cycloneiii_io_ibuf \SW[7]~input (
+	.i(SW[7]),
+	.ibar(gnd),
+	.o(\SW[7]~input_o ));
+// synopsys translate_off
+defparam \SW[7]~input .bus_hold = "false";
+defparam \SW[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N15
+cycloneiii_io_ibuf \SW[6]~input (
+	.i(SW[6]),
+	.ibar(gnd),
+	.o(\SW[6]~input_o ));
+// synopsys translate_off
+defparam \SW[6]~input .bus_hold = "false";
+defparam \SW[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y22_N15
+cycloneiii_io_ibuf \SW[5]~input (
+	.i(SW[5]),
+	.ibar(gnd),
+	.o(\SW[5]~input_o ));
+// synopsys translate_off
+defparam \SW[5]~input .bus_hold = "false";
+defparam \SW[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y27_N22
+cycloneiii_io_ibuf \SW[4]~input (
+	.i(SW[4]),
+	.ibar(gnd),
+	.o(\SW[4]~input_o ));
+// synopsys translate_off
+defparam \SW[4]~input .bus_hold = "false";
+defparam \SW[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  = (\SW[7]~input_o  & (\SW[5]~input_o  $ (((\SW[6]~input_o  & !\SW[4]~input_o ))))) # (!\SW[7]~input_o  & ((\SW[5]~input_o  & ((\SW[6]~input_o ) # (!\SW[4]~input_o ))) # (!\SW[5]~input_o  & 
+// ((\SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 .lut_mask = 16'hE578;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y23_N8
+cycloneiii_io_ibuf \SW[3]~input (
+	.i(SW[3]),
+	.ibar(gnd),
+	.o(\SW[3]~input_o ));
+// synopsys translate_off
+defparam \SW[3]~input .bus_hold = "false";
+defparam \SW[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N22
+cycloneiii_io_ibuf \SW[2]~input (
+	.i(SW[2]),
+	.ibar(gnd),
+	.o(\SW[2]~input_o ));
+// synopsys translate_off
+defparam \SW[2]~input .bus_hold = "false";
+defparam \SW[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y24_N1
+cycloneiii_io_ibuf \SW[0]~input (
+	.i(SW[0]),
+	.ibar(gnd),
+	.o(\SW[0]~input_o ));
+// synopsys translate_off
+defparam \SW[0]~input .bus_hold = "false";
+defparam \SW[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y27_N1
+cycloneiii_io_ibuf \SW[1]~input (
+	.i(SW[1]),
+	.ibar(gnd),
+	.o(\SW[1]~input_o ));
+// synopsys translate_off
+defparam \SW[1]~input .bus_hold = "false";
+defparam \SW[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N28
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  = (\SW[3]~input_o  & ((\SW[2]~input_o ) # ((\SW[0]~input_o  & \SW[1]~input_o ))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 .lut_mask = 16'hA888;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N2
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  = (\SW[3]~input_o  & (!\SW[2]~input_o  & ((!\SW[1]~input_o ) # (!\SW[0]~input_o )))) # (!\SW[3]~input_o  & (\SW[2]~input_o  & ((\SW[1]~input_o ))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 .lut_mask = 16'h4622;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  = (\SW[7]~input_o  & ((\SW[6]~input_o  & ((\SW[4]~input_o ))) # (!\SW[6]~input_o  & ((\SW[5]~input_o ) # (!\SW[4]~input_o ))))) # (!\SW[7]~input_o  & (\SW[4]~input_o  $ (((\SW[6]~input_o  & 
+// \SW[5]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 .lut_mask = 16'hBD62;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  = (\SW[2]~input_o  & ((\SW[3]~input_o  & ((\SW[0]~input_o ) # (\SW[1]~input_o ))) # (!\SW[3]~input_o  & ((!\SW[1]~input_o ))))) # (!\SW[2]~input_o  & (\SW[3]~input_o  $ (((\SW[0]~input_o  & 
+// \SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 .lut_mask = 16'h9AE6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  = (\SW[6]~input_o  & ((\SW[7]~input_o  & ((\SW[5]~input_o ) # (\SW[4]~input_o ))) # (!\SW[7]~input_o  & (!\SW[5]~input_o )))) # (!\SW[6]~input_o  & (\SW[7]~input_o  $ (((\SW[5]~input_o  & 
+// \SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 .lut_mask = 16'h9EA6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  = (\SW[5]~input_o  & ((\SW[6]~input_o  & ((\SW[7]~input_o ) # (\SW[4]~input_o ))) # (!\SW[6]~input_o  & ((!\SW[4]~input_o ))))) # (!\SW[5]~input_o  & (\SW[6]~input_o  $ (((\SW[7]~input_o  & 
+// \SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 .lut_mask = 16'hC6BC;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  = (\SW[0]~input_o  & (\SW[2]~input_o  $ (((\SW[3]~input_o  & !\SW[1]~input_o ))))) # (!\SW[0]~input_o  & ((\SW[2]~input_o  & ((\SW[3]~input_o ) # (!\SW[1]~input_o ))) # (!\SW[2]~input_o  & 
+// ((\SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 .lut_mask = 16'hCB6C;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N0
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  = (\SW[3]~input_o  & (\SW[1]~input_o  $ (((\SW[2]~input_o  & !\SW[0]~input_o ))))) # (!\SW[3]~input_o  & ((\SW[0]~input_o  & ((\SW[2]~input_o ) # (!\SW[1]~input_o ))) # (!\SW[0]~input_o  & 
+// ((\SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .lut_mask = 16'hE758;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N26
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  = (\SW[3]~input_o  & ((\SW[2]~input_o  & (\SW[0]~input_o )) # (!\SW[2]~input_o  & ((\SW[1]~input_o ) # (!\SW[0]~input_o ))))) # (!\SW[3]~input_o  & (\SW[0]~input_o  $ (((\SW[2]~input_o  & 
+// \SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 .lut_mask = 16'hB6D2;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout  = \SW[7]~input_o  $ (((\SW[6]~input_o  & (!\SW[5]~input_o )) # (!\SW[6]~input_o  & (\SW[5]~input_o  & \SW[4]~input_o ))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 .lut_mask = 16'h96A6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  = \SW[6]~input_o  $ (((\SW[5]~input_o  & !\SW[4]~input_o )))
+
+	.dataa(gnd),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 .lut_mask = 16'hCC3C;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  = \SW[5]~input_o  $ (\SW[4]~input_o )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 .lut_mask = 16'h0FF0;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & \SW[4]~input_o ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.datab(\SW[4]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 .lut_mask = 16'h0088;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 .lut_mask = 16'h0017;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ))) # (!\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  & (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 .lut_mask = 16'h008E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout )) # (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 .lut_mask = 16'h0017;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ))) # (!\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N14
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ))) # (!\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  = (\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )) # (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ))) # (!\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  & (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout  & \SW[8]~input_o ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ),
+	.datab(\SW[8]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .lut_mask = 16'h0088;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  $ (GND))) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'hA50A;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h3C3F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout  = ((\SW[8]~input_o  $ (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9  = CARRY((\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) # (!\SW[8]~input_o  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N14
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  = (\SW[7]~input_o  & (!\SW[6]~input_o  & ((!\SW[4]~input_o ) # (!\SW[5]~input_o )))) # (!\SW[7]~input_o  & (\SW[6]~input_o  & (\SW[5]~input_o )))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 .lut_mask = 16'h4262;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  $ (GND))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 .lut_mask = 16'hA50A;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N26
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ) # (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 .lut_mask = 16'h3C3F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N28
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  $ (GND))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 .lut_mask = 16'hC30C;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  $ (GND))) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hC30C;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 .lut_mask = 16'h5A5F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  = ((\SW[8]~input_o  $ (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17  = CARRY((\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ))) # (!\SW[8]~input_o  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 )))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout  = (\SW[7]~input_o  & ((\SW[6]~input_o ) # ((\SW[5]~input_o  & \SW[4]~input_o ))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 .lut_mask = 16'hA888;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N30
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  = \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25  $ (\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 .lut_mask = 16'h0FF0;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  = !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 .lut_mask = 16'h0F0F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr2~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr2~0 .lut_mask = 16'h6426;
+defparam \BCD_CONVERT|A9|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr1 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr1~combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  $ (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr1 .lut_mask = 16'h0940;
+defparam \BCD_CONVERT|A9|WideOr1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  $ 
+// (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr3~0 .lut_mask = 16'h42B4;
+defparam \BCD_CONVERT|A9|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr1~0_combout  = (\BCD_CONVERT|A9|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & !\BCD_CONVERT|A9|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A9|WideOr2~0_combout  & (\BCD_CONVERT|A9|WideOr1~combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (\BCD_CONVERT|A9|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr1~0 .lut_mask = 16'h444A;
+defparam \BCD_CONVERT|A12|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr2~0_combout  = (\BCD_CONVERT|A9|WideOr1~combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & (!\BCD_CONVERT|A9|WideOr2~0_combout  & \BCD_CONVERT|A9|WideOr3~0_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & ((!\BCD_CONVERT|A9|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A9|WideOr1~combout  & (\BCD_CONVERT|A9|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (!\BCD_CONVERT|A9|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr2~0 .lut_mask = 16'h710C;
+defparam \BCD_CONVERT|A12|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr3~0_combout  = (\BCD_CONVERT|A9|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & (\BCD_CONVERT|A9|WideOr1~combout  $ (\BCD_CONVERT|A9|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A9|WideOr2~0_combout  & (\BCD_CONVERT|A9|WideOr1~combout  $ ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr3~0 .lut_mask = 16'h161C;
+defparam \BCD_CONVERT|A12|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr1~0_combout  = (\BCD_CONVERT|A12|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & ((!\BCD_CONVERT|A12|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A12|WideOr2~0_combout  & (\BCD_CONVERT|A12|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ) # (\BCD_CONVERT|A12|WideOr3~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr1~0 .lut_mask = 16'h0C58;
+defparam \BCD_CONVERT|A15|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N30
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (!\BCD_CONVERT|A12|WideOr1~0_combout  & (!\BCD_CONVERT|A12|WideOr2~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (\BCD_CONVERT|A12|WideOr1~0_combout  $ (((\BCD_CONVERT|A12|WideOr2~0_combout  & \BCD_CONVERT|A12|WideOr3~0_combout )))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr3~0 .lut_mask = 16'h1646;
+defparam \BCD_CONVERT|A15|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr2~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (\BCD_CONVERT|A12|WideOr3~0_combout  & ((!\BCD_CONVERT|A12|WideOr2~0_combout ) # (!\BCD_CONVERT|A12|WideOr1~0_combout 
+// )))) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & ((\BCD_CONVERT|A12|WideOr1~0_combout  & ((!\BCD_CONVERT|A12|WideOr3~0_combout ))) # (!\BCD_CONVERT|A12|WideOr1~0_combout  & 
+// (!\BCD_CONVERT|A12|WideOr2~0_combout  & \BCD_CONVERT|A12|WideOr3~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr2~0 .lut_mask = 16'h2B44;
+defparam \BCD_CONVERT|A15|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr1~0_combout  = (\BCD_CONVERT|A15|WideOr2~0_combout  & (((!\BCD_CONVERT|A15|WideOr3~0_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )))) # 
+// (!\BCD_CONVERT|A15|WideOr2~0_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr1~0 .lut_mask = 16'h0A38;
+defparam \BCD_CONVERT|A18|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr2~0_combout  = (\BCD_CONVERT|A15|WideOr1~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout  & (!\BCD_CONVERT|A15|WideOr2~0_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )) 
+// # (!\BCD_CONVERT|A15|WideOr3~0_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ))))) # (!\BCD_CONVERT|A15|WideOr1~0_combout  & (\BCD_CONVERT|A15|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ) # (!\BCD_CONVERT|A15|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr2~0 .lut_mask = 16'h4C26;
+defparam \BCD_CONVERT|A18|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr3~0_combout  = (\BCD_CONVERT|A15|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  $ (\BCD_CONVERT|A15|WideOr3~0_combout 
+// )))) # (!\BCD_CONVERT|A15|WideOr2~0_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  $ (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr3~0 .lut_mask = 16'h056A;
+defparam \BCD_CONVERT|A18|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr1~0_combout  = (\BCD_CONVERT|A18|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & !\BCD_CONVERT|A18|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A18|WideOr2~0_combout  & (\BCD_CONVERT|A18|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (\BCD_CONVERT|A18|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr1~0 .lut_mask = 16'h0A38;
+defparam \BCD_CONVERT|A21|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr2~0_combout  = (\BCD_CONVERT|A18|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (!\BCD_CONVERT|A18|WideOr2~0_combout  & \BCD_CONVERT|A18|WideOr3~0_combout )) 
+// # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & ((!\BCD_CONVERT|A18|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A18|WideOr1~0_combout  & (\BCD_CONVERT|A18|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (!\BCD_CONVERT|A18|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr2~0 .lut_mask = 16'h4D22;
+defparam \BCD_CONVERT|A21|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (!\BCD_CONVERT|A18|WideOr1~0_combout  & (!\BCD_CONVERT|A18|WideOr2~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (\BCD_CONVERT|A18|WideOr1~0_combout  $ (((\BCD_CONVERT|A18|WideOr2~0_combout  & \BCD_CONVERT|A18|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr3~0 .lut_mask = 16'h1626;
+defparam \BCD_CONVERT|A21|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr1~0_combout  = (\BCD_CONVERT|A21|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & !\BCD_CONVERT|A21|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A21|WideOr2~0_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (\BCD_CONVERT|A21|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr1~0 .lut_mask = 16'h222C;
+defparam \BCD_CONVERT|A25|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr2~0_combout  = (\BCD_CONVERT|A21|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & (!\BCD_CONVERT|A21|WideOr2~0_combout  & \BCD_CONVERT|A21|WideOr3~0_combout )) 
+// # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & ((!\BCD_CONVERT|A21|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A21|WideOr1~0_combout  & (\BCD_CONVERT|A21|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (!\BCD_CONVERT|A21|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr2~0 .lut_mask = 16'h710A;
+defparam \BCD_CONVERT|A25|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr3~0_combout  = (\BCD_CONVERT|A21|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  $ (\BCD_CONVERT|A21|WideOr3~0_combout 
+// )))) # (!\BCD_CONVERT|A21|WideOr2~0_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  $ ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr3~0 .lut_mask = 16'h161A;
+defparam \BCD_CONVERT|A25|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N22
+cycloneiii_lcell_comb \SEG0|WideOr6~0 (
+// Equation(s):
+// \SEG0|WideOr6~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr3~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  $ (\BCD_CONVERT|A25|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr6~0 .lut_mask = 16'h0894;
+defparam \SEG0|WideOr6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N0
+cycloneiii_lcell_comb \SEG0|WideOr5~0 (
+// Equation(s):
+// \SEG0|WideOr5~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr5~0 .lut_mask = 16'hB860;
+defparam \SEG0|WideOr5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N10
+cycloneiii_lcell_comb \SEG0|WideOr4~0 (
+// Equation(s):
+// \SEG0|WideOr4~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout )))) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr4~0 .lut_mask = 16'hA120;
+defparam \SEG0|WideOr4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N28
+cycloneiii_lcell_comb \SEG0|WideOr3~0 (
+// Equation(s):
+// \SEG0|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr2~0_combout  $ (!\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr3~0 .lut_mask = 16'hC21C;
+defparam \SEG0|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N6
+cycloneiii_lcell_comb \SEG0|WideOr2~0 (
+// Equation(s):
+// \SEG0|WideOr2~0_combout  = (\BCD_CONVERT|A25|WideOr3~0_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ))) # (!\BCD_CONVERT|A25|WideOr3~0_combout  & 
+// ((\BCD_CONVERT|A25|WideOr2~0_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout )) # (!\BCD_CONVERT|A25|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout )))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr2~0 .lut_mask = 16'h445C;
+defparam \SEG0|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N16
+cycloneiii_lcell_comb \SEG0|WideOr1~0 (
+// Equation(s):
+// \SEG0|WideOr1~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr1~0_combout  $ (((\BCD_CONVERT|A25|WideOr3~0_combout ) # (!\BCD_CONVERT|A25|WideOr2~0_combout ))))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr1~0 .lut_mask = 16'h4584;
+defparam \SEG0|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N2
+cycloneiii_lcell_comb \SEG0|WideOr0~0 (
+// Equation(s):
+// \SEG0|WideOr0~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr1~0_combout ) # (\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ) # (\BCD_CONVERT|A25|WideOr1~0_combout  $ (\BCD_CONVERT|A25|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr0~0 .lut_mask = 16'hBFDA;
+defparam \SEG0|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A9|Decoder0~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|Decoder0~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  $ (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|Decoder0~0 .lut_mask = 16'hFFF6;
+defparam \BCD_CONVERT|A9|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr0~0_combout  = \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  $ (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr0~0 .lut_mask = 16'h4DB2;
+defparam \BCD_CONVERT|A9|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr0~1 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr0~1_combout  = (\BCD_CONVERT|A9|WideOr0~0_combout ) # (!\BCD_CONVERT|A9|Decoder0~0_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr0~1 .lut_mask = 16'hFF0F;
+defparam \BCD_CONVERT|A9|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr0~0_combout  = \BCD_CONVERT|A12|WideOr1~0_combout  $ (((\BCD_CONVERT|A12|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ) # (\BCD_CONVERT|A12|WideOr3~0_combout 
+// )))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr0~0 .lut_mask = 16'h3C6C;
+defparam \BCD_CONVERT|A15|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A7|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A7|WideOr0~0_combout  = ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A7|WideOr0~0 .lut_mask = 16'h3377;
+defparam \BCD_CONVERT|A7|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr0~0_combout  = \BCD_CONVERT|A9|WideOr1~combout  $ (((\BCD_CONVERT|A9|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (\BCD_CONVERT|A9|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr0~0 .lut_mask = 16'h666C;
+defparam \BCD_CONVERT|A12|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~5 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~5_combout  = (!\BCD_CONVERT|A15|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  & \BCD_CONVERT|A12|WideOr0~0_combout )) # (!\BCD_CONVERT|A9|WideOr0~1_combout  & 
+// (!\BCD_CONVERT|A7|WideOr0~0_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~5 .lut_mask = 16'h2001;
+defparam \BCD_CONVERT|A17|Decoder0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~3 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~3_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ) # 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~3 .lut_mask = 16'h1FF8;
+defparam \BCD_CONVERT|A17|WideOr2~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~7 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~7_combout  = (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// \BCD_CONVERT|A17|WideOr2~3_combout ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(gnd),
+	.datad(\BCD_CONVERT|A17|WideOr2~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~7 .lut_mask = 16'h4400;
+defparam \BCD_CONVERT|A17|WideOr2~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~3 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~3_combout  = (\BCD_CONVERT|A15|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  & \BCD_CONVERT|A12|WideOr0~0_combout )) # (!\BCD_CONVERT|A9|WideOr0~1_combout  & 
+// (!\BCD_CONVERT|A7|WideOr0~0_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~3 .lut_mask = 16'h8004;
+defparam \BCD_CONVERT|A17|Decoder0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~6 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~6_combout  = (\BCD_CONVERT|A17|Decoder0~5_combout ) # ((\BCD_CONVERT|A17|WideOr2~7_combout ) # (\BCD_CONVERT|A17|Decoder0~3_combout ))
+
+	.dataa(gnd),
+	.datab(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr2~7_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~6 .lut_mask = 16'hFFFC;
+defparam \BCD_CONVERT|A17|WideOr2~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A7|WideOr0~1 (
+// Equation(s):
+// \BCD_CONVERT|A7|WideOr0~1_combout  = (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A7|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A7|WideOr0~1 .lut_mask = 16'h0055;
+defparam \BCD_CONVERT|A7|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr3~0_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A7|WideOr0~1_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))) 
+// # (!\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A12|WideOr0~0_combout  & ((\BCD_CONVERT|A7|WideOr0~1_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A7|WideOr0~1_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr3~0 .lut_mask = 16'h4520;
+defparam \BCD_CONVERT|A17|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N0
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~4 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~4_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~4 .lut_mask = 16'h0880;
+defparam \BCD_CONVERT|A17|Decoder0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr3~1 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr3~1_combout  = (\BCD_CONVERT|A17|Decoder0~4_combout ) # ((\BCD_CONVERT|A17|Decoder0~3_combout ) # ((!\BCD_CONVERT|A15|WideOr0~0_combout  & \BCD_CONVERT|A17|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr3~1 .lut_mask = 16'hFFF4;
+defparam \BCD_CONVERT|A17|WideOr3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~2 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~2_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~2 .lut_mask = 16'h01AA;
+defparam \BCD_CONVERT|A17|Decoder0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~6 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~6_combout  = (!\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~6 .lut_mask = 16'h0110;
+defparam \BCD_CONVERT|A17|Decoder0~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N30
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr1~0_combout  = (\BCD_CONVERT|A17|Decoder0~6_combout ) # ((\BCD_CONVERT|A15|WideOr0~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & \BCD_CONVERT|A17|Decoder0~2_combout 
+// )))
+
+	.dataa(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~2_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr1~0 .lut_mask = 16'hFF80;
+defparam \BCD_CONVERT|A17|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr0~0_combout  = \BCD_CONVERT|A15|WideOr1~0_combout  $ (((\BCD_CONVERT|A15|WideOr2~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr0~0 .lut_mask = 16'h5A6A;
+defparam \BCD_CONVERT|A18|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr2~0_combout  = (\BCD_CONVERT|A17|WideOr3~1_combout  & ((\BCD_CONVERT|A17|WideOr2~6_combout  & (!\BCD_CONVERT|A17|WideOr1~0_combout  & \BCD_CONVERT|A18|WideOr0~0_combout )) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & 
+// ((\BCD_CONVERT|A18|WideOr0~0_combout ) # (!\BCD_CONVERT|A17|WideOr1~0_combout ))))) # (!\BCD_CONVERT|A17|WideOr3~1_combout  & (((\BCD_CONVERT|A17|WideOr1~0_combout  & !\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr2~0 .lut_mask = 16'h4C34;
+defparam \BCD_CONVERT|A20|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N0
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr1~0_combout  = (\BCD_CONVERT|A17|WideOr2~6_combout  & (!\BCD_CONVERT|A17|WideOr3~1_combout  & ((!\BCD_CONVERT|A18|WideOr0~0_combout )))) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & (\BCD_CONVERT|A17|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A17|WideOr3~1_combout ) # (\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr1~0 .lut_mask = 16'h5062;
+defparam \BCD_CONVERT|A20|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr0~0_combout  = \BCD_CONVERT|A18|WideOr1~0_combout  $ (((\BCD_CONVERT|A18|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (\BCD_CONVERT|A18|WideOr3~0_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr0~0 .lut_mask = 16'h5A6A;
+defparam \BCD_CONVERT|A21|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr3~0_combout  = (\BCD_CONVERT|A17|WideOr2~6_combout  & ((\BCD_CONVERT|A18|WideOr0~0_combout ) # (\BCD_CONVERT|A17|WideOr3~1_combout  $ (!\BCD_CONVERT|A17|WideOr1~0_combout )))) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & 
+// ((\BCD_CONVERT|A17|WideOr1~0_combout  $ (!\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr3~0 .lut_mask = 16'hFA87;
+defparam \BCD_CONVERT|A20|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr1~0_combout  = (\BCD_CONVERT|A20|WideOr2~0_combout  & (((!\BCD_CONVERT|A21|WideOr0~0_combout  & \BCD_CONVERT|A20|WideOr3~0_combout )))) # (!\BCD_CONVERT|A20|WideOr2~0_combout  & (\BCD_CONVERT|A20|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr1~0 .lut_mask = 16'h4A44;
+defparam \BCD_CONVERT|A24|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr3~0_combout  = (\BCD_CONVERT|A20|WideOr2~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (\BCD_CONVERT|A20|WideOr1~0_combout  $ (\BCD_CONVERT|A20|WideOr3~0_combout )))) # (!\BCD_CONVERT|A20|WideOr2~0_combout  & 
+// (\BCD_CONVERT|A20|WideOr1~0_combout  $ ((!\BCD_CONVERT|A21|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr3~0 .lut_mask = 16'hE3E9;
+defparam \BCD_CONVERT|A24|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr2~0_combout  = (\BCD_CONVERT|A20|WideOr1~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout  & (!\BCD_CONVERT|A20|WideOr2~0_combout  & !\BCD_CONVERT|A20|WideOr3~0_combout )) # (!\BCD_CONVERT|A21|WideOr0~0_combout  & 
+// ((\BCD_CONVERT|A20|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A20|WideOr1~0_combout  & (!\BCD_CONVERT|A20|WideOr3~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr2~0 .lut_mask = 16'h0C71;
+defparam \BCD_CONVERT|A24|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr0~0_combout  = \BCD_CONVERT|A21|WideOr1~0_combout  $ (((\BCD_CONVERT|A21|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (\BCD_CONVERT|A21|WideOr3~0_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr0~0 .lut_mask = 16'h666A;
+defparam \BCD_CONVERT|A25|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N22
+cycloneiii_lcell_comb \SEG1|WideOr6~0 (
+// Equation(s):
+// \SEG1|WideOr6~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & ((\BCD_CONVERT|A24|WideOr3~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr2~0_combout  $ (!\BCD_CONVERT|A25|WideOr0~0_combout )) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr6~0 .lut_mask = 16'h79BF;
+defparam \SEG1|WideOr6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N16
+cycloneiii_lcell_comb \SEG1|WideOr5~0 (
+// Equation(s):
+// \SEG1|WideOr5~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & ((\BCD_CONVERT|A25|WideOr0~0_combout  & (!\BCD_CONVERT|A24|WideOr3~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr2~0_combout ))))) # 
+// (!\BCD_CONVERT|A24|WideOr1~0_combout  & (\BCD_CONVERT|A24|WideOr2~0_combout  & (\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr5~0 .lut_mask = 16'h62B0;
+defparam \SEG1|WideOr5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N2
+cycloneiii_lcell_comb \SEG1|WideOr4~0 (
+// Equation(s):
+// \SEG1|WideOr4~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & (\BCD_CONVERT|A24|WideOr2~0_combout  & ((!\BCD_CONVERT|A25|WideOr0~0_combout ) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// (!\BCD_CONVERT|A24|WideOr3~0_combout  & (!\BCD_CONVERT|A24|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr4~0 .lut_mask = 16'h20A1;
+defparam \SEG1|WideOr4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N4
+cycloneiii_lcell_comb \SEG1|WideOr3~0 (
+// Equation(s):
+// \SEG1|WideOr3~0_combout  = (\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A24|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr3~0_combout ) # (\BCD_CONVERT|A24|WideOr2~0_combout ))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & ((!\BCD_CONVERT|A24|WideOr2~0_combout ) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr3~0 .lut_mask = 16'hC3BD;
+defparam \SEG1|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N6
+cycloneiii_lcell_comb \SEG1|WideOr2~0 (
+// Equation(s):
+// \SEG1|WideOr2~0_combout  = (\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr2~0_combout  & (\BCD_CONVERT|A24|WideOr1~0_combout )) # (!\BCD_CONVERT|A24|WideOr2~0_combout  & ((!\BCD_CONVERT|A25|WideOr0~0_combout ))))) # 
+// (!\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout ) # ((!\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr2~0 .lut_mask = 16'hA2BF;
+defparam \SEG1|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N0
+cycloneiii_lcell_comb \SEG1|WideOr1~0 (
+// Equation(s):
+// \SEG1|WideOr1~0_combout  = (\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (!\BCD_CONVERT|A24|WideOr3~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr1~0_combout ) # ((\BCD_CONVERT|A24|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr1~0 .lut_mask = 16'h6AFE;
+defparam \SEG1|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N10
+cycloneiii_lcell_comb \SEG1|WideOr0~0 (
+// Equation(s):
+// \SEG1|WideOr0~0_combout  = (\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout ) # (\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A24|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr1~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr0~0 .lut_mask = 16'hEB7B;
+defparam \SEG1|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr0~0_combout  = \BCD_CONVERT|A20|WideOr1~0_combout  $ (((\BCD_CONVERT|A20|WideOr2~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr0~0 .lut_mask = 16'h6C66;
+defparam \BCD_CONVERT|A24|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A14|WideOr0~2 (
+// Equation(s):
+// \BCD_CONVERT|A14|WideOr0~2_combout  = (\BCD_CONVERT|A7|WideOr0~0_combout ) # ((!\BCD_CONVERT|A12|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~0_combout ) # (!\BCD_CONVERT|A9|Decoder0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A14|WideOr0~2 .lut_mask = 16'hF0FB;
+defparam \BCD_CONVERT|A14|WideOr0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~7 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~7_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~7 .lut_mask = 16'h0220;
+defparam \BCD_CONVERT|A17|Decoder0~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr0~0_combout  = (\BCD_CONVERT|A17|Decoder0~6_combout ) # ((\BCD_CONVERT|A17|Decoder0~5_combout ) # ((\BCD_CONVERT|A17|Decoder0~4_combout ) # (\BCD_CONVERT|A17|Decoder0~3_combout )))
+
+	.dataa(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.datab(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr0~0 .lut_mask = 16'hFFFE;
+defparam \BCD_CONVERT|A17|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr0~combout  = (\BCD_CONVERT|A17|Decoder0~7_combout ) # (\BCD_CONVERT|A17|WideOr0~0_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.datad(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr0 .lut_mask = 16'hFFF0;
+defparam \BCD_CONVERT|A17|WideOr0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr0~0_combout  = \BCD_CONVERT|A17|WideOr1~0_combout  $ (((\BCD_CONVERT|A17|WideOr2~6_combout  & ((\BCD_CONVERT|A17|WideOr3~1_combout ) # (\BCD_CONVERT|A18|WideOr0~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr0~0 .lut_mask = 16'h5A78;
+defparam \BCD_CONVERT|A20|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N10
+cycloneiii_lcell_comb \SEG2|Decoder0~0 (
+// Equation(s):
+// \SEG2|Decoder0~0_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~0 .lut_mask = 16'h0104;
+defparam \SEG2|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N20
+cycloneiii_lcell_comb \SEG2|Decoder0~1 (
+// Equation(s):
+// \SEG2|Decoder0~1_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~1 .lut_mask = 16'h2080;
+defparam \SEG2|Decoder0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N22
+cycloneiii_lcell_comb \SEG2|WideOr6 (
+// Equation(s):
+// \SEG2|WideOr6~combout  = (\SEG2|Decoder0~0_combout ) # (\SEG2|Decoder0~1_combout )
+
+	.dataa(\SEG2|Decoder0~0_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr6 .lut_mask = 16'hFFAA;
+defparam \SEG2|WideOr6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N24
+cycloneiii_lcell_comb \SEG2|Decoder0~2 (
+// Equation(s):
+// \SEG2|Decoder0~2_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~2 .lut_mask = 16'h0208;
+defparam \SEG2|Decoder0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N18
+cycloneiii_lcell_comb \SEG2|Decoder0~3 (
+// Equation(s):
+// \SEG2|Decoder0~3_combout  = (!\BCD_CONVERT|A17|WideOr0~0_combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  & (!\BCD_CONVERT|A17|Decoder0~7_combout  & \BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~3 .lut_mask = 16'h0400;
+defparam \SEG2|Decoder0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N12
+cycloneiii_lcell_comb \SEG2|WideOr5 (
+// Equation(s):
+// \SEG2|WideOr5~combout  = (\SEG2|Decoder0~2_combout ) # ((!\BCD_CONVERT|A24|WideOr0~0_combout  & \SEG2|Decoder0~3_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~2_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datad(\SEG2|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr5 .lut_mask = 16'hCFCC;
+defparam \SEG2|WideOr5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N6
+cycloneiii_lcell_comb \SEG2|Decoder0~4 (
+// Equation(s):
+// \SEG2|Decoder0~4_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & ((\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )) # (!\BCD_CONVERT|A14|WideOr0~2_combout  & 
+// (!\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~4 .lut_mask = 16'h4001;
+defparam \SEG2|Decoder0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N16
+cycloneiii_lcell_comb \SEG2|Decoder0~5 (
+// Equation(s):
+// \SEG2|Decoder0~5_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~5 .lut_mask = 16'h0800;
+defparam \SEG2|Decoder0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N26
+cycloneiii_lcell_comb \SEG2|Decoder0~6 (
+// Equation(s):
+// \SEG2|Decoder0~6_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~6 .lut_mask = 16'h0020;
+defparam \SEG2|Decoder0~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N4
+cycloneiii_lcell_comb \SEG2|WideOr2~0 (
+// Equation(s):
+// \SEG2|WideOr2~0_combout  = (!\SEG2|Decoder0~0_combout  & (!\SEG2|Decoder0~5_combout  & (!\SEG2|Decoder0~6_combout  & !\SEG2|Decoder0~1_combout )))
+
+	.dataa(\SEG2|Decoder0~0_combout ),
+	.datab(\SEG2|Decoder0~5_combout ),
+	.datac(\SEG2|Decoder0~6_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr2~0 .lut_mask = 16'h0001;
+defparam \SEG2|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N30
+cycloneiii_lcell_comb \SEG2|Decoder0~7 (
+// Equation(s):
+// \SEG2|Decoder0~7_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & ((\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )) # (!\BCD_CONVERT|A14|WideOr0~2_combout  & 
+// (!\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~7 .lut_mask = 16'h8002;
+defparam \SEG2|Decoder0~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N0
+cycloneiii_lcell_comb \SEG2|WideOr2 (
+// Equation(s):
+// \SEG2|WideOr2~combout  = (\SEG2|Decoder0~2_combout ) # ((\SEG2|Decoder0~7_combout ) # (!\SEG2|WideOr2~0_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~2_combout ),
+	.datac(\SEG2|Decoder0~7_combout ),
+	.datad(\SEG2|WideOr2~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr2 .lut_mask = 16'hFCFF;
+defparam \SEG2|WideOr2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N2
+cycloneiii_lcell_comb \SEG2|WideOr1 (
+// Equation(s):
+// \SEG2|WideOr1~combout  = (\SEG2|Decoder0~4_combout ) # ((\SEG2|Decoder0~5_combout ) # ((\SEG2|Decoder0~7_combout ) # (\SEG2|Decoder0~1_combout )))
+
+	.dataa(\SEG2|Decoder0~4_combout ),
+	.datab(\SEG2|Decoder0~5_combout ),
+	.datac(\SEG2|Decoder0~7_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr1 .lut_mask = 16'hFFFE;
+defparam \SEG2|WideOr1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N28
+cycloneiii_lcell_comb \SEG2|Decoder0~8 (
+// Equation(s):
+// \SEG2|Decoder0~8_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~8 .lut_mask = 16'h1040;
+defparam \SEG2|Decoder0~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N14
+cycloneiii_lcell_comb \SEG2|WideOr0 (
+// Equation(s):
+// \SEG2|WideOr0~combout  = (\SEG2|Decoder0~8_combout ) # ((\SEG2|Decoder0~5_combout ) # (\SEG2|Decoder0~1_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~8_combout ),
+	.datac(\SEG2|Decoder0~5_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr0 .lut_mask = 16'hFFFC;
+defparam \SEG2|WideOr0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A23|WideOr0~5 (
+// Equation(s):
+// \BCD_CONVERT|A23|WideOr0~5_combout  = (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A23|WideOr0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A23|WideOr0~5 .lut_mask = 16'h1FFF;
+defparam \BCD_CONVERT|A23|WideOr0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A23|WideOr0~17 (
+// Equation(s):
+// \BCD_CONVERT|A23|WideOr0~17_combout  = (((\BCD_CONVERT|A23|WideOr0~5_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\BCD_CONVERT|A23|WideOr0~5_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A23|WideOr0~17 .lut_mask = 16'hF7FF;
+defparam \BCD_CONVERT|A23|WideOr0~17 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y15_N1
+cycloneiii_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N2
+cycloneiii_lcell_comb \SPI_DAC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_DAC|clk_1MHz~0_combout  = !\SPI_DAC|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_DAC|clk_1MHz~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|clk_1MHz~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~0 .lut_mask = 16'h0F0F;
+defparam \SPI_DAC|clk_1MHz~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneiii_clkctrl \CLOCK_50~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLOCK_50~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
+defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N16
+cycloneiii_lcell_comb \SPI_ADC|Add0~0 (
+// Equation(s):
+// \SPI_ADC|Add0~0_combout  = \SPI_ADC|ctr [0] $ (VCC)
+// \SPI_ADC|Add0~1  = CARRY(\SPI_ADC|ctr [0])
+
+	.dataa(\SPI_ADC|ctr [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_ADC|Add0~0_combout ),
+	.cout(\SPI_ADC|Add0~1 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~0 .lut_mask = 16'h55AA;
+defparam \SPI_ADC|Add0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N22
+cycloneiii_lcell_comb \SPI_ADC|Add0~6 (
+// Equation(s):
+// \SPI_ADC|Add0~6_combout  = (\SPI_ADC|ctr [3] & (\SPI_ADC|Add0~5  & VCC)) # (!\SPI_ADC|ctr [3] & (!\SPI_ADC|Add0~5 ))
+// \SPI_ADC|Add0~7  = CARRY((!\SPI_ADC|ctr [3] & !\SPI_ADC|Add0~5 ))
+
+	.dataa(\SPI_ADC|ctr [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~5 ),
+	.combout(\SPI_ADC|Add0~6_combout ),
+	.cout(\SPI_ADC|Add0~7 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~6 .lut_mask = 16'hA505;
+defparam \SPI_ADC|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N24
+cycloneiii_lcell_comb \SPI_ADC|Add0~8 (
+// Equation(s):
+// \SPI_ADC|Add0~8_combout  = \SPI_ADC|Add0~7  $ (\SPI_ADC|ctr [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|ctr [4]),
+	.cin(\SPI_ADC|Add0~7 ),
+	.combout(\SPI_ADC|Add0~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~8 .lut_mask = 16'h0FF0;
+defparam \SPI_ADC|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N25
+dffeas \SPI_ADC|ctr[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Add0~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N6
+cycloneiii_lcell_comb \SPI_ADC|ctr~0 (
+// Equation(s):
+// \SPI_ADC|ctr~0_combout  = (\SPI_ADC|Add0~0_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~0_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~0 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N7
+dffeas \SPI_ADC|ctr[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N18
+cycloneiii_lcell_comb \SPI_ADC|Add0~2 (
+// Equation(s):
+// \SPI_ADC|Add0~2_combout  = (\SPI_ADC|ctr [1] & (\SPI_ADC|Add0~1  & VCC)) # (!\SPI_ADC|ctr [1] & (!\SPI_ADC|Add0~1 ))
+// \SPI_ADC|Add0~3  = CARRY((!\SPI_ADC|ctr [1] & !\SPI_ADC|Add0~1 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|ctr [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~1 ),
+	.combout(\SPI_ADC|Add0~2_combout ),
+	.cout(\SPI_ADC|Add0~3 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~2 .lut_mask = 16'hC303;
+defparam \SPI_ADC|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N4
+cycloneiii_lcell_comb \SPI_ADC|ctr~1 (
+// Equation(s):
+// \SPI_ADC|ctr~1_combout  = (\SPI_ADC|Add0~2_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~2_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~1 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N5
+dffeas \SPI_ADC|ctr[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N20
+cycloneiii_lcell_comb \SPI_ADC|Add0~4 (
+// Equation(s):
+// \SPI_ADC|Add0~4_combout  = (\SPI_ADC|ctr [2] & ((GND) # (!\SPI_ADC|Add0~3 ))) # (!\SPI_ADC|ctr [2] & (\SPI_ADC|Add0~3  $ (GND)))
+// \SPI_ADC|Add0~5  = CARRY((\SPI_ADC|ctr [2]) # (!\SPI_ADC|Add0~3 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~3 ),
+	.combout(\SPI_ADC|Add0~4_combout ),
+	.cout(\SPI_ADC|Add0~5 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~4 .lut_mask = 16'h3CCF;
+defparam \SPI_ADC|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N28
+cycloneiii_lcell_comb \SPI_ADC|ctr~2 (
+// Equation(s):
+// \SPI_ADC|ctr~2_combout  = (\SPI_ADC|Add0~4_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~4_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~2 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N29
+dffeas \SPI_ADC|ctr[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N23
+dffeas \SPI_ADC|ctr[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Add0~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N0
+cycloneiii_lcell_comb \SPI_DAC|Equal0~0 (
+// Equation(s):
+// \SPI_DAC|Equal0~0_combout  = (!\SPI_ADC|ctr [3] & (!\SPI_ADC|ctr [2] & (!\SPI_ADC|ctr [1] & !\SPI_ADC|ctr [0])))
+
+	.dataa(\SPI_ADC|ctr [3]),
+	.datab(\SPI_ADC|ctr [2]),
+	.datac(\SPI_ADC|ctr [1]),
+	.datad(\SPI_ADC|ctr [0]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal0~0 .lut_mask = 16'h0001;
+defparam \SPI_DAC|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N26
+cycloneiii_lcell_comb \SPI_DAC|Equal0~1 (
+// Equation(s):
+// \SPI_DAC|Equal0~1_combout  = (\SPI_DAC|Equal0~0_combout  & !\SPI_ADC|ctr [4])
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|Equal0~0_combout ),
+	.datac(gnd),
+	.datad(\SPI_ADC|ctr [4]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal0~1 .lut_mask = 16'h00CC;
+defparam \SPI_DAC|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N3
+dffeas \SPI_DAC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\SPI_DAC|clk_1MHz~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_DAC|Equal0~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_DAC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G11
+cycloneiii_clkctrl \SPI_DAC|clk_1MHz~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_DAC|clk_1MHz~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_DAC|clk_1MHz~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~clkctrl .clock_type = "global clock";
+defparam \SPI_DAC|clk_1MHz~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N0
+cycloneiii_lcell_comb \PWM_DC|count[0]~27 (
+// Equation(s):
+// \PWM_DC|count[0]~27_combout  = !\PWM_DC|count [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\PWM_DC|count [0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\PWM_DC|count[0]~27_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|count[0]~27 .lut_mask = 16'h0F0F;
+defparam \PWM_DC|count[0]~27 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N1
+dffeas \PWM_DC|count[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[0]~27_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[0] .is_wysiwyg = "true";
+defparam \PWM_DC|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N2
+cycloneiii_lcell_comb \GEN_10K|Add0~22 (
+// Equation(s):
+// \GEN_10K|Add0~22_combout  = (\GEN_10K|ctr [11] & (\GEN_10K|Add0~21  & VCC)) # (!\GEN_10K|ctr [11] & (!\GEN_10K|Add0~21 ))
+// \GEN_10K|Add0~23  = CARRY((!\GEN_10K|ctr [11] & !\GEN_10K|Add0~21 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~21 ),
+	.combout(\GEN_10K|Add0~22_combout ),
+	.cout(\GEN_10K|Add0~23 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~22 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N4
+cycloneiii_lcell_comb \GEN_10K|Add0~24 (
+// Equation(s):
+// \GEN_10K|Add0~24_combout  = (\GEN_10K|ctr [12] & ((GND) # (!\GEN_10K|Add0~23 ))) # (!\GEN_10K|ctr [12] & (\GEN_10K|Add0~23  $ (GND)))
+// \GEN_10K|Add0~25  = CARRY((\GEN_10K|ctr [12]) # (!\GEN_10K|Add0~23 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~23 ),
+	.combout(\GEN_10K|Add0~24_combout ),
+	.cout(\GEN_10K|Add0~25 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~24 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N24
+cycloneiii_lcell_comb \GEN_10K|ctr~6 (
+// Equation(s):
+// \GEN_10K|ctr~6_combout  = (\GEN_10K|Add0~24_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Equal0~5_combout ),
+	.datab(\GEN_10K|Equal0~4_combout ),
+	.datac(\GEN_10K|Add0~24_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~6 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N25
+dffeas \GEN_10K|ctr[12] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[12] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N6
+cycloneiii_lcell_comb \GEN_10K|Add0~26 (
+// Equation(s):
+// \GEN_10K|Add0~26_combout  = (\GEN_10K|ctr [13] & (\GEN_10K|Add0~25  & VCC)) # (!\GEN_10K|ctr [13] & (!\GEN_10K|Add0~25 ))
+// \GEN_10K|Add0~27  = CARRY((!\GEN_10K|ctr [13] & !\GEN_10K|Add0~25 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [13]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~25 ),
+	.combout(\GEN_10K|Add0~26_combout ),
+	.cout(\GEN_10K|Add0~27 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~26 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N8
+cycloneiii_lcell_comb \GEN_10K|ctr~7 (
+// Equation(s):
+// \GEN_10K|ctr~7_combout  = (\GEN_10K|Add0~26_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~26_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~7 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N9
+dffeas \GEN_10K|ctr[13] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[13] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N8
+cycloneiii_lcell_comb \GEN_10K|Add0~28 (
+// Equation(s):
+// \GEN_10K|Add0~28_combout  = (\GEN_10K|ctr [14] & ((GND) # (!\GEN_10K|Add0~27 ))) # (!\GEN_10K|ctr [14] & (\GEN_10K|Add0~27  $ (GND)))
+// \GEN_10K|Add0~29  = CARRY((\GEN_10K|ctr [14]) # (!\GEN_10K|Add0~27 ))
+
+	.dataa(\GEN_10K|ctr [14]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~27 ),
+	.combout(\GEN_10K|Add0~28_combout ),
+	.cout(\GEN_10K|Add0~29 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~28 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N2
+cycloneiii_lcell_comb \GEN_10K|ctr~8 (
+// Equation(s):
+// \GEN_10K|ctr~8_combout  = (\GEN_10K|Add0~28_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~28_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~8 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N3
+dffeas \GEN_10K|ctr[14] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[14] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N10
+cycloneiii_lcell_comb \GEN_10K|Add0~30 (
+// Equation(s):
+// \GEN_10K|Add0~30_combout  = (\GEN_10K|ctr [15] & (\GEN_10K|Add0~29  & VCC)) # (!\GEN_10K|ctr [15] & (!\GEN_10K|Add0~29 ))
+// \GEN_10K|Add0~31  = CARRY((!\GEN_10K|ctr [15] & !\GEN_10K|Add0~29 ))
+
+	.dataa(\GEN_10K|ctr [15]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~29 ),
+	.combout(\GEN_10K|Add0~30_combout ),
+	.cout(\GEN_10K|Add0~31 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~30 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N20
+cycloneiii_lcell_comb \GEN_10K|ctr~9 (
+// Equation(s):
+// \GEN_10K|ctr~9_combout  = (\GEN_10K|Add0~30_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~30_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~9 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N21
+dffeas \GEN_10K|ctr[15] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[15] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N12
+cycloneiii_lcell_comb \GEN_10K|Add0~32 (
+// Equation(s):
+// \GEN_10K|Add0~32_combout  = (\GEN_10K|ctr [16] & ((GND) # (!\GEN_10K|Add0~31 ))) # (!\GEN_10K|ctr [16] & (\GEN_10K|Add0~31  $ (GND)))
+// \GEN_10K|Add0~33  = CARRY((\GEN_10K|ctr [16]) # (!\GEN_10K|Add0~31 ))
+
+	.dataa(\GEN_10K|ctr [16]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~31 ),
+	.combout(\GEN_10K|Add0~32_combout ),
+	.cout(\GEN_10K|Add0~33 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~32 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N6
+cycloneiii_lcell_comb \GEN_10K|ctr~10 (
+// Equation(s):
+// \GEN_10K|ctr~10_combout  = (\GEN_10K|Add0~32_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~32_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~10 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N7
+dffeas \GEN_10K|ctr[16] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[16] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N14
+cycloneiii_lcell_comb \GEN_10K|Add0~34 (
+// Equation(s):
+// \GEN_10K|Add0~34_combout  = (\GEN_10K|ctr [17] & (\GEN_10K|Add0~33  & VCC)) # (!\GEN_10K|ctr [17] & (!\GEN_10K|Add0~33 ))
+// \GEN_10K|Add0~35  = CARRY((!\GEN_10K|ctr [17] & !\GEN_10K|Add0~33 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [17]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~33 ),
+	.combout(\GEN_10K|Add0~34_combout ),
+	.cout(\GEN_10K|Add0~35 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~34 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N18
+cycloneiii_lcell_comb \GEN_10K|ctr~11 (
+// Equation(s):
+// \GEN_10K|ctr~11_combout  = (\GEN_10K|Add0~34_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~34_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~11 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N19
+dffeas \GEN_10K|ctr[17] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[17] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N16
+cycloneiii_lcell_comb \GEN_10K|Add0~36 (
+// Equation(s):
+// \GEN_10K|Add0~36_combout  = (\GEN_10K|ctr [18] & ((GND) # (!\GEN_10K|Add0~35 ))) # (!\GEN_10K|ctr [18] & (\GEN_10K|Add0~35  $ (GND)))
+// \GEN_10K|Add0~37  = CARRY((\GEN_10K|ctr [18]) # (!\GEN_10K|Add0~35 ))
+
+	.dataa(\GEN_10K|ctr [18]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~35 ),
+	.combout(\GEN_10K|Add0~36_combout ),
+	.cout(\GEN_10K|Add0~37 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~36 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~36 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N4
+cycloneiii_lcell_comb \GEN_10K|ctr~12 (
+// Equation(s):
+// \GEN_10K|ctr~12_combout  = (\GEN_10K|Add0~36_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~36_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~12 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N5
+dffeas \GEN_10K|ctr[18] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[18] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N18
+cycloneiii_lcell_comb \GEN_10K|Add0~38 (
+// Equation(s):
+// \GEN_10K|Add0~38_combout  = (\GEN_10K|ctr [19] & (\GEN_10K|Add0~37  & VCC)) # (!\GEN_10K|ctr [19] & (!\GEN_10K|Add0~37 ))
+// \GEN_10K|Add0~39  = CARRY((!\GEN_10K|ctr [19] & !\GEN_10K|Add0~37 ))
+
+	.dataa(\GEN_10K|ctr [19]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~37 ),
+	.combout(\GEN_10K|Add0~38_combout ),
+	.cout(\GEN_10K|Add0~39 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~38 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~38 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N26
+cycloneiii_lcell_comb \GEN_10K|ctr~13 (
+// Equation(s):
+// \GEN_10K|ctr~13_combout  = (\GEN_10K|Add0~38_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~38_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~13 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N27
+dffeas \GEN_10K|ctr[19] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[19] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N20
+cycloneiii_lcell_comb \GEN_10K|Add0~40 (
+// Equation(s):
+// \GEN_10K|Add0~40_combout  = \GEN_10K|Add0~39  $ (\GEN_10K|ctr [20])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\GEN_10K|ctr [20]),
+	.cin(\GEN_10K|Add0~39 ),
+	.combout(\GEN_10K|Add0~40_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~40 .lut_mask = 16'h0FF0;
+defparam \GEN_10K|Add0~40 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N28
+cycloneiii_lcell_comb \GEN_10K|ctr~14 (
+// Equation(s):
+// \GEN_10K|ctr~14_combout  = (\GEN_10K|Add0~40_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~40_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~14 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N29
+dffeas \GEN_10K|ctr[20] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[20] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N30
+cycloneiii_lcell_comb \GEN_10K|Equal0~5 (
+// Equation(s):
+// \GEN_10K|Equal0~5_combout  = (!\GEN_10K|ctr [18] & (!\GEN_10K|ctr [20] & (!\GEN_10K|ctr [19] & !\GEN_10K|ctr [17])))
+
+	.dataa(\GEN_10K|ctr [18]),
+	.datab(\GEN_10K|ctr [20]),
+	.datac(\GEN_10K|ctr [19]),
+	.datad(\GEN_10K|ctr [17]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~5 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N12
+cycloneiii_lcell_comb \GEN_10K|Add0~1 (
+// Equation(s):
+// \GEN_10K|Add0~1_cout  = CARRY(\PWM_DC|count [0])
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\GEN_10K|Add0~1_cout ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~1 .lut_mask = 16'h00AA;
+defparam \GEN_10K|Add0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N14
+cycloneiii_lcell_comb \GEN_10K|Add0~2 (
+// Equation(s):
+// \GEN_10K|Add0~2_combout  = (\GEN_10K|ctr [1] & (\GEN_10K|Add0~1_cout  & VCC)) # (!\GEN_10K|ctr [1] & (!\GEN_10K|Add0~1_cout ))
+// \GEN_10K|Add0~3  = CARRY((!\GEN_10K|ctr [1] & !\GEN_10K|Add0~1_cout ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~1_cout ),
+	.combout(\GEN_10K|Add0~2_combout ),
+	.cout(\GEN_10K|Add0~3 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~2 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N15
+dffeas \GEN_10K|ctr[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[1] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N16
+cycloneiii_lcell_comb \GEN_10K|Add0~4 (
+// Equation(s):
+// \GEN_10K|Add0~4_combout  = (\GEN_10K|ctr [2] & ((GND) # (!\GEN_10K|Add0~3 ))) # (!\GEN_10K|ctr [2] & (\GEN_10K|Add0~3  $ (GND)))
+// \GEN_10K|Add0~5  = CARRY((\GEN_10K|ctr [2]) # (!\GEN_10K|Add0~3 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~3 ),
+	.combout(\GEN_10K|Add0~4_combout ),
+	.cout(\GEN_10K|Add0~5 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~4 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N10
+cycloneiii_lcell_comb \GEN_10K|ctr~0 (
+// Equation(s):
+// \GEN_10K|ctr~0_combout  = (\GEN_10K|Add0~4_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~0 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N11
+dffeas \GEN_10K|ctr[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[2] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N18
+cycloneiii_lcell_comb \GEN_10K|Add0~6 (
+// Equation(s):
+// \GEN_10K|Add0~6_combout  = (\GEN_10K|ctr [3] & (\GEN_10K|Add0~5  & VCC)) # (!\GEN_10K|ctr [3] & (!\GEN_10K|Add0~5 ))
+// \GEN_10K|Add0~7  = CARRY((!\GEN_10K|ctr [3] & !\GEN_10K|Add0~5 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~5 ),
+	.combout(\GEN_10K|Add0~6_combout ),
+	.cout(\GEN_10K|Add0~7 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~6 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N0
+cycloneiii_lcell_comb \GEN_10K|ctr~1 (
+// Equation(s):
+// \GEN_10K|ctr~1_combout  = (\GEN_10K|Add0~6_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\PWM_DC|count [0]),
+	.datad(\GEN_10K|Add0~6_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~1 .lut_mask = 16'hF700;
+defparam \GEN_10K|ctr~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N1
+dffeas \GEN_10K|ctr[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[3] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N20
+cycloneiii_lcell_comb \GEN_10K|Add0~8 (
+// Equation(s):
+// \GEN_10K|Add0~8_combout  = (\GEN_10K|ctr [4] & ((GND) # (!\GEN_10K|Add0~7 ))) # (!\GEN_10K|ctr [4] & (\GEN_10K|Add0~7  $ (GND)))
+// \GEN_10K|Add0~9  = CARRY((\GEN_10K|ctr [4]) # (!\GEN_10K|Add0~7 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~7 ),
+	.combout(\GEN_10K|Add0~8_combout ),
+	.cout(\GEN_10K|Add0~9 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~8 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N12
+cycloneiii_lcell_comb \GEN_10K|ctr~2 (
+// Equation(s):
+// \GEN_10K|ctr~2_combout  = (\GEN_10K|Add0~8_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~8_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~2 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N13
+dffeas \GEN_10K|ctr[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[4] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N22
+cycloneiii_lcell_comb \GEN_10K|Add0~10 (
+// Equation(s):
+// \GEN_10K|Add0~10_combout  = (\GEN_10K|ctr [5] & (\GEN_10K|Add0~9  & VCC)) # (!\GEN_10K|ctr [5] & (!\GEN_10K|Add0~9 ))
+// \GEN_10K|Add0~11  = CARRY((!\GEN_10K|ctr [5] & !\GEN_10K|Add0~9 ))
+
+	.dataa(\GEN_10K|ctr [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~9 ),
+	.combout(\GEN_10K|Add0~10_combout ),
+	.cout(\GEN_10K|Add0~11 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~10 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N14
+cycloneiii_lcell_comb \GEN_10K|ctr~3 (
+// Equation(s):
+// \GEN_10K|ctr~3_combout  = (\GEN_10K|Add0~10_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~10_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~3 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N15
+dffeas \GEN_10K|ctr[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[5] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N24
+cycloneiii_lcell_comb \GEN_10K|Add0~12 (
+// Equation(s):
+// \GEN_10K|Add0~12_combout  = (\GEN_10K|ctr [6] & ((GND) # (!\GEN_10K|Add0~11 ))) # (!\GEN_10K|ctr [6] & (\GEN_10K|Add0~11  $ (GND)))
+// \GEN_10K|Add0~13  = CARRY((\GEN_10K|ctr [6]) # (!\GEN_10K|Add0~11 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~11 ),
+	.combout(\GEN_10K|Add0~12_combout ),
+	.cout(\GEN_10K|Add0~13 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~12 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N25
+dffeas \GEN_10K|ctr[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[6] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N26
+cycloneiii_lcell_comb \GEN_10K|Add0~14 (
+// Equation(s):
+// \GEN_10K|Add0~14_combout  = (\GEN_10K|ctr [7] & (\GEN_10K|Add0~13  & VCC)) # (!\GEN_10K|ctr [7] & (!\GEN_10K|Add0~13 ))
+// \GEN_10K|Add0~15  = CARRY((!\GEN_10K|ctr [7] & !\GEN_10K|Add0~13 ))
+
+	.dataa(\GEN_10K|ctr [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~13 ),
+	.combout(\GEN_10K|Add0~14_combout ),
+	.cout(\GEN_10K|Add0~15 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~14 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N27
+dffeas \GEN_10K|ctr[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[7] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N28
+cycloneiii_lcell_comb \GEN_10K|Add0~16 (
+// Equation(s):
+// \GEN_10K|Add0~16_combout  = (\GEN_10K|ctr [8] & ((GND) # (!\GEN_10K|Add0~15 ))) # (!\GEN_10K|ctr [8] & (\GEN_10K|Add0~15  $ (GND)))
+// \GEN_10K|Add0~17  = CARRY((\GEN_10K|ctr [8]) # (!\GEN_10K|Add0~15 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~15 ),
+	.combout(\GEN_10K|Add0~16_combout ),
+	.cout(\GEN_10K|Add0~17 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~16 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N29
+dffeas \GEN_10K|ctr[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~16_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[8] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N30
+cycloneiii_lcell_comb \GEN_10K|Add0~18 (
+// Equation(s):
+// \GEN_10K|Add0~18_combout  = (\GEN_10K|ctr [9] & (\GEN_10K|Add0~17  & VCC)) # (!\GEN_10K|ctr [9] & (!\GEN_10K|Add0~17 ))
+// \GEN_10K|Add0~19  = CARRY((!\GEN_10K|ctr [9] & !\GEN_10K|Add0~17 ))
+
+	.dataa(\GEN_10K|ctr [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~17 ),
+	.combout(\GEN_10K|Add0~18_combout ),
+	.cout(\GEN_10K|Add0~19 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~18 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N6
+cycloneiii_lcell_comb \GEN_10K|ctr~4 (
+// Equation(s):
+// \GEN_10K|ctr~4_combout  = (\GEN_10K|Add0~18_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~18_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\PWM_DC|count [0]),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~4 .lut_mask = 16'hA2AA;
+defparam \GEN_10K|ctr~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N7
+dffeas \GEN_10K|ctr[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[9] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N0
+cycloneiii_lcell_comb \GEN_10K|Add0~20 (
+// Equation(s):
+// \GEN_10K|Add0~20_combout  = (\GEN_10K|ctr [10] & ((GND) # (!\GEN_10K|Add0~19 ))) # (!\GEN_10K|ctr [10] & (\GEN_10K|Add0~19  $ (GND)))
+// \GEN_10K|Add0~21  = CARRY((\GEN_10K|ctr [10]) # (!\GEN_10K|Add0~19 ))
+
+	.dataa(\GEN_10K|ctr [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~19 ),
+	.combout(\GEN_10K|Add0~20_combout ),
+	.cout(\GEN_10K|Add0~21 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~20 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N22
+cycloneiii_lcell_comb \GEN_10K|ctr~5 (
+// Equation(s):
+// \GEN_10K|ctr~5_combout  = (\GEN_10K|Add0~20_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~20_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~5 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N23
+dffeas \GEN_10K|ctr[10] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[10] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N3
+dffeas \GEN_10K|ctr[11] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~22_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[11] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N8
+cycloneiii_lcell_comb \GEN_10K|Equal0~2 (
+// Equation(s):
+// \GEN_10K|Equal0~2_combout  = (!\GEN_10K|ctr [11] & (!\GEN_10K|ctr [10] & (!\GEN_10K|ctr [12] & !\GEN_10K|ctr [9])))
+
+	.dataa(\GEN_10K|ctr [11]),
+	.datab(\GEN_10K|ctr [10]),
+	.datac(\GEN_10K|ctr [12]),
+	.datad(\GEN_10K|ctr [9]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~2 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N2
+cycloneiii_lcell_comb \GEN_10K|Equal0~0 (
+// Equation(s):
+// \GEN_10K|Equal0~0_combout  = (!\GEN_10K|ctr [1] & (!\GEN_10K|ctr [2] & (!\GEN_10K|ctr [4] & !\GEN_10K|ctr [3])))
+
+	.dataa(\GEN_10K|ctr [1]),
+	.datab(\GEN_10K|ctr [2]),
+	.datac(\GEN_10K|ctr [4]),
+	.datad(\GEN_10K|ctr [3]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~0 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N4
+cycloneiii_lcell_comb \GEN_10K|Equal0~1 (
+// Equation(s):
+// \GEN_10K|Equal0~1_combout  = (!\GEN_10K|ctr [5] & (!\GEN_10K|ctr [6] & (!\GEN_10K|ctr [7] & !\GEN_10K|ctr [8])))
+
+	.dataa(\GEN_10K|ctr [5]),
+	.datab(\GEN_10K|ctr [6]),
+	.datac(\GEN_10K|ctr [7]),
+	.datad(\GEN_10K|ctr [8]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~1 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N16
+cycloneiii_lcell_comb \GEN_10K|Equal0~3 (
+// Equation(s):
+// \GEN_10K|Equal0~3_combout  = (!\GEN_10K|ctr [16] & (!\GEN_10K|ctr [14] & (!\GEN_10K|ctr [13] & !\GEN_10K|ctr [15])))
+
+	.dataa(\GEN_10K|ctr [16]),
+	.datab(\GEN_10K|ctr [14]),
+	.datac(\GEN_10K|ctr [13]),
+	.datad(\GEN_10K|ctr [15]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~3 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N10
+cycloneiii_lcell_comb \GEN_10K|Equal0~4 (
+// Equation(s):
+// \GEN_10K|Equal0~4_combout  = (\GEN_10K|Equal0~2_combout  & (\GEN_10K|Equal0~0_combout  & (\GEN_10K|Equal0~1_combout  & \GEN_10K|Equal0~3_combout )))
+
+	.dataa(\GEN_10K|Equal0~2_combout ),
+	.datab(\GEN_10K|Equal0~0_combout ),
+	.datac(\GEN_10K|Equal0~1_combout ),
+	.datad(\GEN_10K|Equal0~3_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~4 .lut_mask = 16'h8000;
+defparam \GEN_10K|Equal0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N28
+cycloneiii_lcell_comb \GEN_10K|clkout~0 (
+// Equation(s):
+// \GEN_10K|clkout~0_combout  = \GEN_10K|clkout~q  $ (((\GEN_10K|Equal0~4_combout  & (\GEN_10K|Equal0~5_combout  & !\PWM_DC|count [0]))))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|clkout~q ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|clkout~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|clkout~0 .lut_mask = 16'hF078;
+defparam \GEN_10K|clkout~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N29
+dffeas \GEN_10K|clkout (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|clkout~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|clkout~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|clkout .is_wysiwyg = "true";
+defparam \GEN_10K|clkout .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N22
+cycloneiii_lcell_comb \PULSE|state.IDLE~feeder (
+// Equation(s):
+// \PULSE|state.IDLE~feeder_combout  = \GEN_10K|clkout~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\GEN_10K|clkout~q ),
+	.cin(gnd),
+	.combout(\PULSE|state.IDLE~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PULSE|state.IDLE~feeder .lut_mask = 16'hFF00;
+defparam \PULSE|state.IDLE~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N23
+dffeas \PULSE|state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PULSE|state.IDLE~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PULSE|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PULSE|state.IDLE .is_wysiwyg = "true";
+defparam \PULSE|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N0
+cycloneiii_lcell_comb \PULSE|pulse~1 (
+// Equation(s):
+// \PULSE|pulse~1_combout  = (!\PULSE|state.IDLE~q  & \GEN_10K|clkout~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\PULSE|state.IDLE~q ),
+	.datad(\GEN_10K|clkout~q ),
+	.cin(gnd),
+	.combout(\PULSE|pulse~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PULSE|pulse~1 .lut_mask = 16'h0F00;
+defparam \PULSE|pulse~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N1
+dffeas \PULSE|pulse (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PULSE|pulse~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PULSE|pulse~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PULSE|pulse .is_wysiwyg = "true";
+defparam \PULSE|pulse .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N0
+cycloneiii_lcell_comb \SPI_DAC|Selector2~0 (
+// Equation(s):
+// \SPI_DAC|Selector2~0_combout  = (\SPI_DAC|dac_cs~q  & \SPI_DAC|sr_state.IDLE~q )
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector2~0 .lut_mask = 16'hAA00;
+defparam \SPI_DAC|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N1
+dffeas \SPI_DAC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N2
+cycloneiii_lcell_comb \SPI_DAC|Selector0~0 (
+// Equation(s):
+// \SPI_DAC|Selector0~0_combout  = (\SPI_DAC|dac_cs~q  & ((\PULSE|pulse~q ) # ((\SPI_DAC|sr_state.IDLE~q )))) # (!\SPI_DAC|dac_cs~q  & (!\SPI_DAC|sr_state.WAIT_CSB_HIGH~q  & ((\PULSE|pulse~q ) # (\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|sr_state.IDLE~q ),
+	.datad(\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector0~0 .lut_mask = 16'hA8FC;
+defparam \SPI_DAC|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N3
+dffeas \SPI_DAC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N24
+cycloneiii_lcell_comb \SPI_DAC|Selector1~0 (
+// Equation(s):
+// \SPI_DAC|Selector1~0_combout  = (\SPI_DAC|dac_cs~q  & (\PULSE|pulse~q  & ((!\SPI_DAC|sr_state.IDLE~q )))) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|sr_state.WAIT_CSB_FALL~q ) # ((\PULSE|pulse~q  & !\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector1~0 .lut_mask = 16'h50DC;
+defparam \SPI_DAC|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N25
+dffeas \SPI_DAC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N4
+cycloneiii_lcell_comb \SPI_DAC|dac_start~0 (
+// Equation(s):
+// \SPI_DAC|dac_start~0_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q ) # ((\SPI_DAC|sr_state.WAIT_CSB_FALL~q ) # (!\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|sr_state.IDLE~q ),
+	.datac(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|dac_start~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_start~0 .lut_mask = 16'hFB00;
+defparam \SPI_DAC|dac_start~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N20
+cycloneiii_lcell_comb \SPI_DAC|dac_start~1 (
+// Equation(s):
+// \SPI_DAC|dac_start~1_combout  = (\SPI_DAC|dac_start~0_combout ) # ((\PULSE|pulse~q  & !\SPI_DAC|sr_state.IDLE~q ))
+
+	.dataa(gnd),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|dac_start~0_combout ),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|dac_start~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_start~1 .lut_mask = 16'hF0FC;
+defparam \SPI_DAC|dac_start~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N21
+dffeas \SPI_DAC|dac_start (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|dac_start~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_start .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N0
+cycloneiii_lcell_comb \SPI_DAC|state[0]~5 (
+// Equation(s):
+// \SPI_DAC|state[0]~5_combout  = \SPI_DAC|state [0] $ (VCC)
+// \SPI_DAC|state[0]~6  = CARRY(\SPI_DAC|state [0])
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_DAC|state[0]~5_combout ),
+	.cout(\SPI_DAC|state[0]~6 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[0]~5 .lut_mask = 16'h33CC;
+defparam \SPI_DAC|state[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N6
+cycloneiii_lcell_comb \SPI_DAC|state[3]~11 (
+// Equation(s):
+// \SPI_DAC|state[3]~11_combout  = (\SPI_DAC|state [3] & (!\SPI_DAC|state[2]~10 )) # (!\SPI_DAC|state [3] & ((\SPI_DAC|state[2]~10 ) # (GND)))
+// \SPI_DAC|state[3]~12  = CARRY((!\SPI_DAC|state[2]~10 ) # (!\SPI_DAC|state [3]))
+
+	.dataa(\SPI_DAC|state [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[2]~10 ),
+	.combout(\SPI_DAC|state[3]~11_combout ),
+	.cout(\SPI_DAC|state[3]~12 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[3]~11 .lut_mask = 16'h5A5F;
+defparam \SPI_DAC|state[3]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N8
+cycloneiii_lcell_comb \SPI_DAC|state[4]~13 (
+// Equation(s):
+// \SPI_DAC|state[4]~13_combout  = \SPI_DAC|state [4] $ (!\SPI_DAC|state[3]~12 )
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [4]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\SPI_DAC|state[3]~12 ),
+	.combout(\SPI_DAC|state[4]~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|state[4]~13 .lut_mask = 16'hC3C3;
+defparam \SPI_DAC|state[4]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N9
+dffeas \SPI_DAC|state[4] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[4]~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N24
+cycloneiii_lcell_comb \SPI_DAC|Selector8~0 (
+// Equation(s):
+// \SPI_DAC|Selector8~0_combout  = (\SPI_DAC|Equal1~0_combout  & ((\SPI_DAC|state [4]) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_start~q ),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector8~0 .lut_mask = 16'hC4C4;
+defparam \SPI_DAC|Selector8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N1
+dffeas \SPI_DAC|state[0] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[0]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[0] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N2
+cycloneiii_lcell_comb \SPI_DAC|state[1]~7 (
+// Equation(s):
+// \SPI_DAC|state[1]~7_combout  = (\SPI_DAC|state [1] & (!\SPI_DAC|state[0]~6 )) # (!\SPI_DAC|state [1] & ((\SPI_DAC|state[0]~6 ) # (GND)))
+// \SPI_DAC|state[1]~8  = CARRY((!\SPI_DAC|state[0]~6 ) # (!\SPI_DAC|state [1]))
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[0]~6 ),
+	.combout(\SPI_DAC|state[1]~7_combout ),
+	.cout(\SPI_DAC|state[1]~8 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[1]~7 .lut_mask = 16'h3C3F;
+defparam \SPI_DAC|state[1]~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N3
+dffeas \SPI_DAC|state[1] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[1]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[1] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N4
+cycloneiii_lcell_comb \SPI_DAC|state[2]~9 (
+// Equation(s):
+// \SPI_DAC|state[2]~9_combout  = (\SPI_DAC|state [2] & (\SPI_DAC|state[1]~8  $ (GND))) # (!\SPI_DAC|state [2] & (!\SPI_DAC|state[1]~8  & VCC))
+// \SPI_DAC|state[2]~10  = CARRY((\SPI_DAC|state [2] & !\SPI_DAC|state[1]~8 ))
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[1]~8 ),
+	.combout(\SPI_DAC|state[2]~9_combout ),
+	.cout(\SPI_DAC|state[2]~10 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[2]~9 .lut_mask = 16'hC30C;
+defparam \SPI_DAC|state[2]~9 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N5
+dffeas \SPI_DAC|state[2] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[2]~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N7
+dffeas \SPI_DAC|state[3] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[3]~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N14
+cycloneiii_lcell_comb \SPI_DAC|Equal1~0 (
+// Equation(s):
+// \SPI_DAC|Equal1~0_combout  = (!\SPI_DAC|state [3] & (!\SPI_DAC|state [1] & (!\SPI_DAC|state [2] & !\SPI_DAC|state [0])))
+
+	.dataa(\SPI_DAC|state [3]),
+	.datab(\SPI_DAC|state [1]),
+	.datac(\SPI_DAC|state [2]),
+	.datad(\SPI_DAC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal1~0 .lut_mask = 16'h0001;
+defparam \SPI_DAC|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N10
+cycloneiii_lcell_comb \SPI_DAC|Selector9~0 (
+// Equation(s):
+// \SPI_DAC|Selector9~0_combout  = ((\SPI_DAC|dac_start~q  & !\SPI_DAC|state [4])) # (!\SPI_DAC|Equal1~0_combout )
+
+	.dataa(\SPI_DAC|dac_start~q ),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector9~0 .lut_mask = 16'h3B3B;
+defparam \SPI_DAC|Selector9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N11
+dffeas \SPI_DAC|dac_cs (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|Selector9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_cs .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N8
+cycloneiii_lcell_comb \SPI_ADC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_ADC|clk_1MHz~0_combout  = !\SPI_ADC|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_ADC|clk_1MHz~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|clk_1MHz~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~0 .lut_mask = 16'h0F0F;
+defparam \SPI_ADC|clk_1MHz~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N9
+dffeas \SPI_ADC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\SPI_ADC|clk_1MHz~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_DAC|Equal0~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_ADC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G12
+cycloneiii_clkctrl \SPI_ADC|clk_1MHz~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_ADC|clk_1MHz~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_ADC|clk_1MHz~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~clkctrl .clock_type = "global clock";
+defparam \SPI_ADC|clk_1MHz~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: IOIBUF_X3_Y0_N22
+cycloneiii_io_ibuf \ADC_SDO~input (
+	.i(ADC_SDO),
+	.ibar(gnd),
+	.o(\ADC_SDO~input_o ));
+// synopsys translate_off
+defparam \ADC_SDO~input .bus_hold = "false";
+defparam \ADC_SDO~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N24
+cycloneiii_lcell_comb \SPI_ADC|Selector2~0 (
+// Equation(s):
+// \SPI_ADC|Selector2~0_combout  = (\SPI_ADC|sr_state.IDLE~q  & \SPI_ADC|adc_cs~q )
+
+	.dataa(\SPI_ADC|sr_state.IDLE~q ),
+	.datab(gnd),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector2~0 .lut_mask = 16'hA0A0;
+defparam \SPI_ADC|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N25
+dffeas \SPI_ADC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N26
+cycloneiii_lcell_comb \SPI_ADC|Selector0~0 (
+// Equation(s):
+// \SPI_ADC|Selector0~0_combout  = (\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & (\SPI_ADC|adc_cs~q  & ((\SPI_ADC|sr_state.IDLE~q ) # (\PULSE|pulse~q )))) # (!\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & (((\SPI_ADC|sr_state.IDLE~q ) # (\PULSE|pulse~q ))))
+
+	.dataa(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(\SPI_ADC|sr_state.IDLE~q ),
+	.datad(\PULSE|pulse~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector0~0 .lut_mask = 16'hDDD0;
+defparam \SPI_ADC|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N27
+dffeas \SPI_ADC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N12
+cycloneiii_lcell_comb \SPI_ADC|Selector1~0 (
+// Equation(s):
+// \SPI_ADC|Selector1~0_combout  = (\PULSE|pulse~q  & (((!\SPI_ADC|adc_cs~q  & \SPI_ADC|sr_state.WAIT_CSB_FALL~q )) # (!\SPI_ADC|sr_state.IDLE~q ))) # (!\PULSE|pulse~q  & (!\SPI_ADC|adc_cs~q  & (\SPI_ADC|sr_state.WAIT_CSB_FALL~q )))
+
+	.dataa(\PULSE|pulse~q ),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_ADC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector1~0 .lut_mask = 16'h30BA;
+defparam \SPI_ADC|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N13
+dffeas \SPI_ADC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N30
+cycloneiii_lcell_comb \SPI_ADC|adc_start~0 (
+// Equation(s):
+// \SPI_ADC|adc_start~0_combout  = (\SPI_ADC|adc_start~q  & ((\SPI_ADC|sr_state.WAIT_CSB_FALL~q ) # ((\SPI_ADC|adc_cs~q ) # (!\SPI_ADC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datab(\SPI_ADC|sr_state.IDLE~q ),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_ADC|adc_start~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|adc_start~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~0 .lut_mask = 16'hFB00;
+defparam \SPI_ADC|adc_start~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N10
+cycloneiii_lcell_comb \SPI_ADC|adc_start~1 (
+// Equation(s):
+// \SPI_ADC|adc_start~1_combout  = (\SPI_ADC|adc_start~0_combout ) # ((!\SPI_ADC|sr_state.IDLE~q  & \PULSE|pulse~q ))
+
+	.dataa(\SPI_ADC|adc_start~0_combout ),
+	.datab(\SPI_ADC|sr_state.IDLE~q ),
+	.datac(\PULSE|pulse~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|adc_start~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~1 .lut_mask = 16'hBABA;
+defparam \SPI_ADC|adc_start~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N11
+dffeas \SPI_ADC|adc_start (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|adc_start~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_start .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N24
+cycloneiii_lcell_comb \SPI_ADC|Add1~4 (
+// Equation(s):
+// \SPI_ADC|Add1~4_combout  = (\SPI_ADC|state [2] & (\SPI_ADC|Add1~3  $ (GND))) # (!\SPI_ADC|state [2] & (!\SPI_ADC|Add1~3  & VCC))
+// \SPI_ADC|Add1~5  = CARRY((\SPI_ADC|state [2] & !\SPI_ADC|Add1~3 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~3 ),
+	.combout(\SPI_ADC|Add1~4_combout ),
+	.cout(\SPI_ADC|Add1~5 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~4 .lut_mask = 16'hC30C;
+defparam \SPI_ADC|Add1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N26
+cycloneiii_lcell_comb \SPI_ADC|Add1~6 (
+// Equation(s):
+// \SPI_ADC|Add1~6_combout  = (\SPI_ADC|state [3] & (!\SPI_ADC|Add1~5 )) # (!\SPI_ADC|state [3] & ((\SPI_ADC|Add1~5 ) # (GND)))
+// \SPI_ADC|Add1~7  = CARRY((!\SPI_ADC|Add1~5 ) # (!\SPI_ADC|state [3]))
+
+	.dataa(\SPI_ADC|state [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~5 ),
+	.combout(\SPI_ADC|Add1~6_combout ),
+	.cout(\SPI_ADC|Add1~7 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~6 .lut_mask = 16'h5A5F;
+defparam \SPI_ADC|Add1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N27
+dffeas \SPI_ADC|state[3] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N28
+cycloneiii_lcell_comb \SPI_ADC|Add1~8 (
+// Equation(s):
+// \SPI_ADC|Add1~8_combout  = \SPI_ADC|Add1~7  $ (!\SPI_ADC|state [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(\SPI_ADC|Add1~7 ),
+	.combout(\SPI_ADC|Add1~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Add1~8 .lut_mask = 16'hF00F;
+defparam \SPI_ADC|Add1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N0
+cycloneiii_lcell_comb \SPI_ADC|state~1 (
+// Equation(s):
+// \SPI_ADC|state~1_combout  = (\SPI_ADC|Add1~8_combout  & ((\SPI_ADC|state [1]) # (!\SPI_ADC|state~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|Add1~8_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|state~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|state~1 .lut_mask = 16'hF300;
+defparam \SPI_ADC|state~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N1
+dffeas \SPI_ADC|state[4] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|state~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N10
+cycloneiii_lcell_comb \SPI_ADC|Selector4~2 (
+// Equation(s):
+// \SPI_ADC|Selector4~2_combout  = (\SPI_ADC|state [4]) # (!\SPI_ADC|adc_start~q )
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~2 .lut_mask = 16'hFF55;
+defparam \SPI_ADC|Selector4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N20
+cycloneiii_lcell_comb \SPI_ADC|Add1~0 (
+// Equation(s):
+// \SPI_ADC|Add1~0_combout  = \SPI_ADC|state [0] $ (VCC)
+// \SPI_ADC|Add1~1  = CARRY(\SPI_ADC|state [0])
+
+	.dataa(\SPI_ADC|state [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_ADC|Add1~0_combout ),
+	.cout(\SPI_ADC|Add1~1 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~0 .lut_mask = 16'h55AA;
+defparam \SPI_ADC|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N12
+cycloneiii_lcell_comb \SPI_ADC|Selector5~0 (
+// Equation(s):
+// \SPI_ADC|Selector5~0_combout  = (\SPI_ADC|state~0_combout  & (((\SPI_ADC|state [1])) # (!\SPI_ADC|Selector4~2_combout ))) # (!\SPI_ADC|state~0_combout  & (((\SPI_ADC|Add1~0_combout ))))
+
+	.dataa(\SPI_ADC|Selector4~2_combout ),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|Add1~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector5~0 .lut_mask = 16'hF7C4;
+defparam \SPI_ADC|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N13
+dffeas \SPI_ADC|state[0] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N22
+cycloneiii_lcell_comb \SPI_ADC|Add1~2 (
+// Equation(s):
+// \SPI_ADC|Add1~2_combout  = (\SPI_ADC|state [1] & (!\SPI_ADC|Add1~1 )) # (!\SPI_ADC|state [1] & ((\SPI_ADC|Add1~1 ) # (GND)))
+// \SPI_ADC|Add1~3  = CARRY((!\SPI_ADC|Add1~1 ) # (!\SPI_ADC|state [1]))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~1 ),
+	.combout(\SPI_ADC|Add1~2_combout ),
+	.cout(\SPI_ADC|Add1~3 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~2 .lut_mask = 16'h5A5F;
+defparam \SPI_ADC|Add1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N23
+dffeas \SPI_ADC|state[1] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N25
+dffeas \SPI_ADC|state[2] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N2
+cycloneiii_lcell_comb \SPI_ADC|state~0 (
+// Equation(s):
+// \SPI_ADC|state~0_combout  = (!\SPI_ADC|state [2] & (!\SPI_ADC|state [3] & !\SPI_ADC|state [0]))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|state~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|state~0 .lut_mask = 16'h0003;
+defparam \SPI_ADC|state~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N6
+cycloneiii_lcell_comb \SPI_ADC|Selector4~3 (
+// Equation(s):
+// \SPI_ADC|Selector4~3_combout  = ((\SPI_ADC|state [1]) # ((\SPI_ADC|adc_start~q  & !\SPI_ADC|state [4]))) # (!\SPI_ADC|state~0_combout )
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector4~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~3 .lut_mask = 16'hF3FB;
+defparam \SPI_ADC|Selector4~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N7
+dffeas \SPI_ADC|adc_cs (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Selector4~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N16
+cycloneiii_lcell_comb \SPI_ADC|WideOr0~0 (
+// Equation(s):
+// \SPI_ADC|WideOr0~0_combout  = (\SPI_ADC|state [2] & (((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [3])) # (!\SPI_ADC|state [1]))) # (!\SPI_ADC|state [2] & (((\SPI_ADC|state [3]))))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~0 .lut_mask = 16'h7CFC;
+defparam \SPI_ADC|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N14
+cycloneiii_lcell_comb \SPI_ADC|WideOr0~1 (
+// Equation(s):
+// \SPI_ADC|WideOr0~1_combout  = (\SPI_ADC|state [4] & (((\SPI_ADC|state [1])) # (!\SPI_ADC|state~0_combout ))) # (!\SPI_ADC|state [4] & (((\SPI_ADC|WideOr0~0_combout ))))
+
+	.dataa(\SPI_ADC|state~0_combout ),
+	.datab(\SPI_ADC|WideOr0~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~1 .lut_mask = 16'hF5CC;
+defparam \SPI_ADC|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N15
+dffeas \SPI_ADC|shift_ena (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|WideOr0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_ena~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_ena .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_ena .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N14
+cycloneiii_lcell_comb \SPI_ADC|always3~0 (
+// Equation(s):
+// \SPI_ADC|always3~0_combout  = (\SPI_ADC|adc_cs~q  & \SPI_ADC|shift_ena~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_ADC|shift_ena~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|always3~0 .lut_mask = 16'hF000;
+defparam \SPI_ADC|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N21
+dffeas \SPI_ADC|shift_reg[0] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\ADC_SDO~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N26
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[1]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[1]~feeder_combout  = \SPI_ADC|shift_reg [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N27
+dffeas \SPI_ADC|shift_reg[1] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N17
+dffeas \SPI_ADC|shift_reg[2] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N22
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[3]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[3]~feeder_combout  = \SPI_ADC|shift_reg [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [2]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N23
+dffeas \SPI_ADC|shift_reg[3] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N29
+dffeas \SPI_ADC|shift_reg[4] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N18
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[5]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[5]~feeder_combout  = \SPI_ADC|shift_reg [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N19
+dffeas \SPI_ADC|shift_reg[5] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N8
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[6]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[6]~feeder_combout  = \SPI_ADC|shift_reg [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [5]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N9
+dffeas \SPI_ADC|shift_reg[6] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N31
+dffeas \SPI_ADC|shift_reg[7] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N18
+cycloneiii_lcell_comb \SPI_ADC|Decoder0~0 (
+// Equation(s):
+// \SPI_ADC|Decoder0~0_combout  = (\SPI_ADC|state [1] & (\SPI_ADC|state [2] & (\SPI_ADC|state [3] & \SPI_ADC|state [0])))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~0 .lut_mask = 16'h8000;
+defparam \SPI_ADC|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N4
+cycloneiii_lcell_comb \SPI_ADC|Decoder0~1 (
+// Equation(s):
+// \SPI_ADC|Decoder0~1_combout  = (\SPI_ADC|Decoder0~0_combout  & !\SPI_ADC|state [4])
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Decoder0~0_combout ),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Decoder0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~1 .lut_mask = 16'h00CC;
+defparam \SPI_ADC|Decoder0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N5
+dffeas \SPI_ADC|adc_done (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Decoder0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_done~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_done .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_done .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N19
+dffeas \SPI_ADC|data_from_adc[7] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y20_N2
+cycloneiii_lcell_comb \DUMMY|PULSE2|state.IDLE~0 (
+// Equation(s):
+// \DUMMY|PULSE2|state.IDLE~0_combout  = !\SPI_ADC|adc_cs~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|adc_cs~q ),
+	.cin(gnd),
+	.combout(\DUMMY|PULSE2|state.IDLE~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|PULSE2|state.IDLE~0 .lut_mask = 16'h00FF;
+defparam \DUMMY|PULSE2|state.IDLE~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y20_N3
+dffeas \DUMMY|PULSE2|state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|PULSE2|state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|PULSE2|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|PULSE2|state.IDLE .is_wysiwyg = "true";
+defparam \DUMMY|PULSE2|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y20_N0
+cycloneiii_lcell_comb \DUMMY|PULSE2|pulse~1 (
+// Equation(s):
+// \DUMMY|PULSE2|pulse~1_combout  = (!\SPI_ADC|adc_cs~q  & !\DUMMY|PULSE2|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(gnd),
+	.datad(\DUMMY|PULSE2|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\DUMMY|PULSE2|pulse~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|PULSE2|pulse~1 .lut_mask = 16'h0033;
+defparam \DUMMY|PULSE2|pulse~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y20_N1
+dffeas \DUMMY|PULSE2|pulse (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|PULSE2|pulse~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|PULSE2|pulse~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|PULSE2|pulse .is_wysiwyg = "true";
+defparam \DUMMY|PULSE2|pulse .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N25
+dffeas \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|PULSE2|pulse~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store .is_wysiwyg = "true";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N24
+cycloneiii_lcell_comb \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 (
+// Equation(s):
+// \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout  = (\DUMMY|PULSE2|pulse~q ) # (\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q )
+
+	.dataa(gnd),
+	.datab(\DUMMY|PULSE2|pulse~q ),
+	.datac(\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 .lut_mask = 16'hFCFC;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N13
+dffeas \SPI_ADC|shift_reg[8] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N21
+dffeas \SPI_ADC|data_from_adc[8] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N10
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[9]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[9]~feeder_combout  = \SPI_ADC|shift_reg [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [8]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N11
+dffeas \SPI_ADC|shift_reg[9] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N23
+dffeas \SPI_ADC|data_from_adc[9] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G10
+cycloneiii_clkctrl \SPI_ADC|adc_cs~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_ADC|adc_cs~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_ADC|adc_cs~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs~clkctrl .clock_type = "global clock";
+defparam \SPI_ADC|adc_cs~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N0
+cycloneiii_lcell_comb \DUMMY|ctr[0]~36 (
+// Equation(s):
+// \DUMMY|ctr[0]~36_combout  = !\DUMMY|ctr [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\DUMMY|ctr [0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|ctr[0]~36_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|ctr[0]~36 .lut_mask = 16'h0F0F;
+defparam \DUMMY|ctr[0]~36 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N1
+dffeas \DUMMY|ctr[0] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[0]~36_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[0] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N6
+cycloneiii_lcell_comb \DUMMY|ctr[1]~12 (
+// Equation(s):
+// \DUMMY|ctr[1]~12_combout  = (\DUMMY|ctr [1] & (\DUMMY|ctr [0] $ (VCC))) # (!\DUMMY|ctr [1] & (\DUMMY|ctr [0] & VCC))
+// \DUMMY|ctr[1]~13  = CARRY((\DUMMY|ctr [1] & \DUMMY|ctr [0]))
+
+	.dataa(\DUMMY|ctr [1]),
+	.datab(\DUMMY|ctr [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|ctr[1]~12_combout ),
+	.cout(\DUMMY|ctr[1]~13 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[1]~12 .lut_mask = 16'h6688;
+defparam \DUMMY|ctr[1]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N7
+dffeas \DUMMY|ctr[1] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[1]~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[1] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N8
+cycloneiii_lcell_comb \DUMMY|ctr[2]~14 (
+// Equation(s):
+// \DUMMY|ctr[2]~14_combout  = (\DUMMY|ctr [2] & (!\DUMMY|ctr[1]~13 )) # (!\DUMMY|ctr [2] & ((\DUMMY|ctr[1]~13 ) # (GND)))
+// \DUMMY|ctr[2]~15  = CARRY((!\DUMMY|ctr[1]~13 ) # (!\DUMMY|ctr [2]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[1]~13 ),
+	.combout(\DUMMY|ctr[2]~14_combout ),
+	.cout(\DUMMY|ctr[2]~15 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[2]~14 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[2]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N9
+dffeas \DUMMY|ctr[2] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[2]~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[2] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N10
+cycloneiii_lcell_comb \DUMMY|ctr[3]~16 (
+// Equation(s):
+// \DUMMY|ctr[3]~16_combout  = (\DUMMY|ctr [3] & (\DUMMY|ctr[2]~15  $ (GND))) # (!\DUMMY|ctr [3] & (!\DUMMY|ctr[2]~15  & VCC))
+// \DUMMY|ctr[3]~17  = CARRY((\DUMMY|ctr [3] & !\DUMMY|ctr[2]~15 ))
+
+	.dataa(\DUMMY|ctr [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[2]~15 ),
+	.combout(\DUMMY|ctr[3]~16_combout ),
+	.cout(\DUMMY|ctr[3]~17 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[3]~16 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[3]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N11
+dffeas \DUMMY|ctr[3] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[3]~16_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[3] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N12
+cycloneiii_lcell_comb \DUMMY|ctr[4]~18 (
+// Equation(s):
+// \DUMMY|ctr[4]~18_combout  = (\DUMMY|ctr [4] & (!\DUMMY|ctr[3]~17 )) # (!\DUMMY|ctr [4] & ((\DUMMY|ctr[3]~17 ) # (GND)))
+// \DUMMY|ctr[4]~19  = CARRY((!\DUMMY|ctr[3]~17 ) # (!\DUMMY|ctr [4]))
+
+	.dataa(\DUMMY|ctr [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[3]~17 ),
+	.combout(\DUMMY|ctr[4]~18_combout ),
+	.cout(\DUMMY|ctr[4]~19 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[4]~18 .lut_mask = 16'h5A5F;
+defparam \DUMMY|ctr[4]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N13
+dffeas \DUMMY|ctr[4] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[4]~18_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[4] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N8
+cycloneiii_lcell_comb \DUMMY|wraddr[4]~0 (
+// Equation(s):
+// \DUMMY|wraddr[4]~0_combout  = (\SW[0]~input_o  & (\DUMMY|ctr [4] $ (VCC))) # (!\SW[0]~input_o  & (\DUMMY|ctr [4] & VCC))
+// \DUMMY|wraddr[4]~1  = CARRY((\SW[0]~input_o  & \DUMMY|ctr [4]))
+
+	.dataa(\SW[0]~input_o ),
+	.datab(\DUMMY|ctr [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|wraddr[4]~0_combout ),
+	.cout(\DUMMY|wraddr[4]~1 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[4]~0 .lut_mask = 16'h6688;
+defparam \DUMMY|wraddr[4]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N14
+cycloneiii_lcell_comb \DUMMY|ctr[5]~20 (
+// Equation(s):
+// \DUMMY|ctr[5]~20_combout  = (\DUMMY|ctr [5] & (\DUMMY|ctr[4]~19  $ (GND))) # (!\DUMMY|ctr [5] & (!\DUMMY|ctr[4]~19  & VCC))
+// \DUMMY|ctr[5]~21  = CARRY((\DUMMY|ctr [5] & !\DUMMY|ctr[4]~19 ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[4]~19 ),
+	.combout(\DUMMY|ctr[5]~20_combout ),
+	.cout(\DUMMY|ctr[5]~21 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[5]~20 .lut_mask = 16'hC30C;
+defparam \DUMMY|ctr[5]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N15
+dffeas \DUMMY|ctr[5] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[5]~20_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[5] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N10
+cycloneiii_lcell_comb \DUMMY|wraddr[5]~2 (
+// Equation(s):
+// \DUMMY|wraddr[5]~2_combout  = (\DUMMY|ctr [5] & ((\SW[1]~input_o  & (\DUMMY|wraddr[4]~1  & VCC)) # (!\SW[1]~input_o  & (!\DUMMY|wraddr[4]~1 )))) # (!\DUMMY|ctr [5] & ((\SW[1]~input_o  & (!\DUMMY|wraddr[4]~1 )) # (!\SW[1]~input_o  & ((\DUMMY|wraddr[4]~1 ) 
+// # (GND)))))
+// \DUMMY|wraddr[5]~3  = CARRY((\DUMMY|ctr [5] & (!\SW[1]~input_o  & !\DUMMY|wraddr[4]~1 )) # (!\DUMMY|ctr [5] & ((!\DUMMY|wraddr[4]~1 ) # (!\SW[1]~input_o ))))
+
+	.dataa(\DUMMY|ctr [5]),
+	.datab(\SW[1]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[4]~1 ),
+	.combout(\DUMMY|wraddr[5]~2_combout ),
+	.cout(\DUMMY|wraddr[5]~3 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[5]~2 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[5]~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N16
+cycloneiii_lcell_comb \DUMMY|ctr[6]~22 (
+// Equation(s):
+// \DUMMY|ctr[6]~22_combout  = (\DUMMY|ctr [6] & (!\DUMMY|ctr[5]~21 )) # (!\DUMMY|ctr [6] & ((\DUMMY|ctr[5]~21 ) # (GND)))
+// \DUMMY|ctr[6]~23  = CARRY((!\DUMMY|ctr[5]~21 ) # (!\DUMMY|ctr [6]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[5]~21 ),
+	.combout(\DUMMY|ctr[6]~22_combout ),
+	.cout(\DUMMY|ctr[6]~23 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[6]~22 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[6]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N17
+dffeas \DUMMY|ctr[6] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[6]~22_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[6] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N12
+cycloneiii_lcell_comb \DUMMY|wraddr[6]~4 (
+// Equation(s):
+// \DUMMY|wraddr[6]~4_combout  = ((\DUMMY|ctr [6] $ (\SW[2]~input_o  $ (!\DUMMY|wraddr[5]~3 )))) # (GND)
+// \DUMMY|wraddr[6]~5  = CARRY((\DUMMY|ctr [6] & ((\SW[2]~input_o ) # (!\DUMMY|wraddr[5]~3 ))) # (!\DUMMY|ctr [6] & (\SW[2]~input_o  & !\DUMMY|wraddr[5]~3 )))
+
+	.dataa(\DUMMY|ctr [6]),
+	.datab(\SW[2]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[5]~3 ),
+	.combout(\DUMMY|wraddr[6]~4_combout ),
+	.cout(\DUMMY|wraddr[6]~5 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[6]~4 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[6]~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N18
+cycloneiii_lcell_comb \DUMMY|ctr[7]~24 (
+// Equation(s):
+// \DUMMY|ctr[7]~24_combout  = (\DUMMY|ctr [7] & (\DUMMY|ctr[6]~23  $ (GND))) # (!\DUMMY|ctr [7] & (!\DUMMY|ctr[6]~23  & VCC))
+// \DUMMY|ctr[7]~25  = CARRY((\DUMMY|ctr [7] & !\DUMMY|ctr[6]~23 ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[6]~23 ),
+	.combout(\DUMMY|ctr[7]~24_combout ),
+	.cout(\DUMMY|ctr[7]~25 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[7]~24 .lut_mask = 16'hC30C;
+defparam \DUMMY|ctr[7]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N19
+dffeas \DUMMY|ctr[7] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[7]~24_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[7] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N14
+cycloneiii_lcell_comb \DUMMY|wraddr[7]~6 (
+// Equation(s):
+// \DUMMY|wraddr[7]~6_combout  = (\DUMMY|ctr [7] & ((\SW[3]~input_o  & (\DUMMY|wraddr[6]~5  & VCC)) # (!\SW[3]~input_o  & (!\DUMMY|wraddr[6]~5 )))) # (!\DUMMY|ctr [7] & ((\SW[3]~input_o  & (!\DUMMY|wraddr[6]~5 )) # (!\SW[3]~input_o  & ((\DUMMY|wraddr[6]~5 ) 
+// # (GND)))))
+// \DUMMY|wraddr[7]~7  = CARRY((\DUMMY|ctr [7] & (!\SW[3]~input_o  & !\DUMMY|wraddr[6]~5 )) # (!\DUMMY|ctr [7] & ((!\DUMMY|wraddr[6]~5 ) # (!\SW[3]~input_o ))))
+
+	.dataa(\DUMMY|ctr [7]),
+	.datab(\SW[3]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[6]~5 ),
+	.combout(\DUMMY|wraddr[7]~6_combout ),
+	.cout(\DUMMY|wraddr[7]~7 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[7]~6 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[7]~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N20
+cycloneiii_lcell_comb \DUMMY|ctr[8]~26 (
+// Equation(s):
+// \DUMMY|ctr[8]~26_combout  = (\DUMMY|ctr [8] & (!\DUMMY|ctr[7]~25 )) # (!\DUMMY|ctr [8] & ((\DUMMY|ctr[7]~25 ) # (GND)))
+// \DUMMY|ctr[8]~27  = CARRY((!\DUMMY|ctr[7]~25 ) # (!\DUMMY|ctr [8]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[7]~25 ),
+	.combout(\DUMMY|ctr[8]~26_combout ),
+	.cout(\DUMMY|ctr[8]~27 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[8]~26 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[8]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N21
+dffeas \DUMMY|ctr[8] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[8]~26_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[8] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N16
+cycloneiii_lcell_comb \DUMMY|wraddr[8]~8 (
+// Equation(s):
+// \DUMMY|wraddr[8]~8_combout  = ((\SW[4]~input_o  $ (\DUMMY|ctr [8] $ (!\DUMMY|wraddr[7]~7 )))) # (GND)
+// \DUMMY|wraddr[8]~9  = CARRY((\SW[4]~input_o  & ((\DUMMY|ctr [8]) # (!\DUMMY|wraddr[7]~7 ))) # (!\SW[4]~input_o  & (\DUMMY|ctr [8] & !\DUMMY|wraddr[7]~7 )))
+
+	.dataa(\SW[4]~input_o ),
+	.datab(\DUMMY|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[7]~7 ),
+	.combout(\DUMMY|wraddr[8]~8_combout ),
+	.cout(\DUMMY|wraddr[8]~9 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[8]~8 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[8]~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N22
+cycloneiii_lcell_comb \DUMMY|ctr[9]~28 (
+// Equation(s):
+// \DUMMY|ctr[9]~28_combout  = (\DUMMY|ctr [9] & (\DUMMY|ctr[8]~27  $ (GND))) # (!\DUMMY|ctr [9] & (!\DUMMY|ctr[8]~27  & VCC))
+// \DUMMY|ctr[9]~29  = CARRY((\DUMMY|ctr [9] & !\DUMMY|ctr[8]~27 ))
+
+	.dataa(\DUMMY|ctr [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[8]~27 ),
+	.combout(\DUMMY|ctr[9]~28_combout ),
+	.cout(\DUMMY|ctr[9]~29 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[9]~28 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[9]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N23
+dffeas \DUMMY|ctr[9] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[9]~28_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[9] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N18
+cycloneiii_lcell_comb \DUMMY|wraddr[9]~10 (
+// Equation(s):
+// \DUMMY|wraddr[9]~10_combout  = (\DUMMY|ctr [9] & ((\SW[5]~input_o  & (\DUMMY|wraddr[8]~9  & VCC)) # (!\SW[5]~input_o  & (!\DUMMY|wraddr[8]~9 )))) # (!\DUMMY|ctr [9] & ((\SW[5]~input_o  & (!\DUMMY|wraddr[8]~9 )) # (!\SW[5]~input_o  & ((\DUMMY|wraddr[8]~9 ) 
+// # (GND)))))
+// \DUMMY|wraddr[9]~11  = CARRY((\DUMMY|ctr [9] & (!\SW[5]~input_o  & !\DUMMY|wraddr[8]~9 )) # (!\DUMMY|ctr [9] & ((!\DUMMY|wraddr[8]~9 ) # (!\SW[5]~input_o ))))
+
+	.dataa(\DUMMY|ctr [9]),
+	.datab(\SW[5]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[8]~9 ),
+	.combout(\DUMMY|wraddr[9]~10_combout ),
+	.cout(\DUMMY|wraddr[9]~11 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[9]~10 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[9]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N24
+cycloneiii_lcell_comb \DUMMY|ctr[10]~30 (
+// Equation(s):
+// \DUMMY|ctr[10]~30_combout  = (\DUMMY|ctr [10] & (!\DUMMY|ctr[9]~29 )) # (!\DUMMY|ctr [10] & ((\DUMMY|ctr[9]~29 ) # (GND)))
+// \DUMMY|ctr[10]~31  = CARRY((!\DUMMY|ctr[9]~29 ) # (!\DUMMY|ctr [10]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[9]~29 ),
+	.combout(\DUMMY|ctr[10]~30_combout ),
+	.cout(\DUMMY|ctr[10]~31 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[10]~30 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[10]~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N25
+dffeas \DUMMY|ctr[10] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[10]~30_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[10] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N20
+cycloneiii_lcell_comb \DUMMY|wraddr[10]~12 (
+// Equation(s):
+// \DUMMY|wraddr[10]~12_combout  = ((\DUMMY|ctr [10] $ (\SW[6]~input_o  $ (!\DUMMY|wraddr[9]~11 )))) # (GND)
+// \DUMMY|wraddr[10]~13  = CARRY((\DUMMY|ctr [10] & ((\SW[6]~input_o ) # (!\DUMMY|wraddr[9]~11 ))) # (!\DUMMY|ctr [10] & (\SW[6]~input_o  & !\DUMMY|wraddr[9]~11 )))
+
+	.dataa(\DUMMY|ctr [10]),
+	.datab(\SW[6]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[9]~11 ),
+	.combout(\DUMMY|wraddr[10]~12_combout ),
+	.cout(\DUMMY|wraddr[10]~13 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[10]~12 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[10]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N26
+cycloneiii_lcell_comb \DUMMY|ctr[11]~32 (
+// Equation(s):
+// \DUMMY|ctr[11]~32_combout  = (\DUMMY|ctr [11] & (\DUMMY|ctr[10]~31  $ (GND))) # (!\DUMMY|ctr [11] & (!\DUMMY|ctr[10]~31  & VCC))
+// \DUMMY|ctr[11]~33  = CARRY((\DUMMY|ctr [11] & !\DUMMY|ctr[10]~31 ))
+
+	.dataa(\DUMMY|ctr [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[10]~31 ),
+	.combout(\DUMMY|ctr[11]~32_combout ),
+	.cout(\DUMMY|ctr[11]~33 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[11]~32 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[11]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N27
+dffeas \DUMMY|ctr[11] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[11]~32_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[11] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N22
+cycloneiii_lcell_comb \DUMMY|wraddr[11]~14 (
+// Equation(s):
+// \DUMMY|wraddr[11]~14_combout  = (\SW[7]~input_o  & ((\DUMMY|ctr [11] & (\DUMMY|wraddr[10]~13  & VCC)) # (!\DUMMY|ctr [11] & (!\DUMMY|wraddr[10]~13 )))) # (!\SW[7]~input_o  & ((\DUMMY|ctr [11] & (!\DUMMY|wraddr[10]~13 )) # (!\DUMMY|ctr [11] & 
+// ((\DUMMY|wraddr[10]~13 ) # (GND)))))
+// \DUMMY|wraddr[11]~15  = CARRY((\SW[7]~input_o  & (!\DUMMY|ctr [11] & !\DUMMY|wraddr[10]~13 )) # (!\SW[7]~input_o  & ((!\DUMMY|wraddr[10]~13 ) # (!\DUMMY|ctr [11]))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\DUMMY|ctr [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[10]~13 ),
+	.combout(\DUMMY|wraddr[11]~14_combout ),
+	.cout(\DUMMY|wraddr[11]~15 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[11]~14 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[11]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N28
+cycloneiii_lcell_comb \DUMMY|ctr[12]~34 (
+// Equation(s):
+// \DUMMY|ctr[12]~34_combout  = \DUMMY|ctr[11]~33  $ (\DUMMY|ctr [12])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\DUMMY|ctr [12]),
+	.cin(\DUMMY|ctr[11]~33 ),
+	.combout(\DUMMY|ctr[12]~34_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|ctr[12]~34 .lut_mask = 16'h0FF0;
+defparam \DUMMY|ctr[12]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N29
+dffeas \DUMMY|ctr[12] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[12]~34_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[12] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N24
+cycloneiii_lcell_comb \DUMMY|wraddr[12]~16 (
+// Equation(s):
+// \DUMMY|wraddr[12]~16_combout  = \SW[8]~input_o  $ (\DUMMY|wraddr[11]~15  $ (!\DUMMY|ctr [12]))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\DUMMY|ctr [12]),
+	.cin(\DUMMY|wraddr[11]~15 ),
+	.combout(\DUMMY|wraddr[12]~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|wraddr[12]~16 .lut_mask = 16'h5AA5;
+defparam \DUMMY|wraddr[12]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y21_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~0_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N3
+dffeas \SPI_ADC|data_from_adc[6] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N24
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[5]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[5]~feeder_combout  = \SPI_ADC|shift_reg [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [5]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N25
+dffeas \SPI_ADC|data_from_adc[5] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N16
+cycloneiii_lcell_comb \DUMMY|Add0~12 (
+// Equation(s):
+// \DUMMY|Add0~12_combout  = ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] $ (\SPI_ADC|data_from_adc [6] $ (\DUMMY|Add0~11 )))) # (GND)
+// \DUMMY|Add0~13  = CARRY((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] & (\SPI_ADC|data_from_adc [6] & !\DUMMY|Add0~11 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] & ((\SPI_ADC|data_from_adc [6]) # (!\DUMMY|Add0~11 ))))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6]),
+	.datab(\SPI_ADC|data_from_adc [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~11 ),
+	.combout(\DUMMY|Add0~12_combout ),
+	.cout(\DUMMY|Add0~13 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~12 .lut_mask = 16'h964D;
+defparam \DUMMY|Add0~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y20_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~12_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N0
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[4]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[4]~feeder_combout  = \SPI_ADC|shift_reg [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N1
+dffeas \SPI_ADC|data_from_adc[4] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N14
+cycloneiii_lcell_comb \DUMMY|Add0~10 (
+// Equation(s):
+// \DUMMY|Add0~10_combout  = (\SPI_ADC|data_from_adc [5] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (!\DUMMY|Add0~9 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (\DUMMY|Add0~9  & VCC)))) # (!\SPI_ADC|data_from_adc [5] 
+// & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & ((\DUMMY|Add0~9 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (!\DUMMY|Add0~9 ))))
+// \DUMMY|Add0~11  = CARRY((\SPI_ADC|data_from_adc [5] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & !\DUMMY|Add0~9 )) # (!\SPI_ADC|data_from_adc [5] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5]) # (!\DUMMY|Add0~9 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [5]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~9 ),
+	.combout(\DUMMY|Add0~10_combout ),
+	.cout(\DUMMY|Add0~11 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~10 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y22_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~10_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N12
+cycloneiii_lcell_comb \DUMMY|Add0~8 (
+// Equation(s):
+// \DUMMY|Add0~8_combout  = ((\SPI_ADC|data_from_adc [4] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] $ (\DUMMY|Add0~7 )))) # (GND)
+// \DUMMY|Add0~9  = CARRY((\SPI_ADC|data_from_adc [4] & ((!\DUMMY|Add0~7 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4]))) # (!\SPI_ADC|data_from_adc [4] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] & !\DUMMY|Add0~7 )))
+
+	.dataa(\SPI_ADC|data_from_adc [4]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~7 ),
+	.combout(\DUMMY|Add0~8_combout ),
+	.cout(\DUMMY|Add0~9 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~8 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y21_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~8_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N3
+dffeas \SPI_ADC|data_from_adc[3] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N4
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[2]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[2]~feeder_combout  = \SPI_ADC|shift_reg [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [2]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N5
+dffeas \SPI_ADC|data_from_adc[2] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N10
+cycloneiii_lcell_comb \DUMMY|Add0~6 (
+// Equation(s):
+// \DUMMY|Add0~6_combout  = (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & ((\SPI_ADC|data_from_adc [3] & (!\DUMMY|Add0~5 )) # (!\SPI_ADC|data_from_adc [3] & ((\DUMMY|Add0~5 ) # (GND))))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b 
+// [3] & ((\SPI_ADC|data_from_adc [3] & (\DUMMY|Add0~5  & VCC)) # (!\SPI_ADC|data_from_adc [3] & (!\DUMMY|Add0~5 ))))
+// \DUMMY|Add0~7  = CARRY((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & ((!\DUMMY|Add0~5 ) # (!\SPI_ADC|data_from_adc [3]))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & (!\SPI_ADC|data_from_adc [3] & !\DUMMY|Add0~5 )))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3]),
+	.datab(\SPI_ADC|data_from_adc [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~5 ),
+	.combout(\DUMMY|Add0~6_combout ),
+	.cout(\DUMMY|Add0~7 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~6 .lut_mask = 16'h692B;
+defparam \DUMMY|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y22_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~6_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N7
+dffeas \SPI_ADC|data_from_adc[1] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N8
+cycloneiii_lcell_comb \DUMMY|Add0~4 (
+// Equation(s):
+// \DUMMY|Add0~4_combout  = ((\SPI_ADC|data_from_adc [2] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] $ (\DUMMY|Add0~3 )))) # (GND)
+// \DUMMY|Add0~5  = CARRY((\SPI_ADC|data_from_adc [2] & ((!\DUMMY|Add0~3 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2]))) # (!\SPI_ADC|data_from_adc [2] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] & !\DUMMY|Add0~3 )))
+
+	.dataa(\SPI_ADC|data_from_adc [2]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~3 ),
+	.combout(\DUMMY|Add0~4_combout ),
+	.cout(\DUMMY|Add0~5 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~4 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y20_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~4_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N6
+cycloneiii_lcell_comb \DUMMY|Add0~2 (
+// Equation(s):
+// \DUMMY|Add0~2_combout  = (\SPI_ADC|data_from_adc [1] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (!\DUMMY|Add0~1 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (\DUMMY|Add0~1  & VCC)))) # (!\SPI_ADC|data_from_adc [1] 
+// & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & ((\DUMMY|Add0~1 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (!\DUMMY|Add0~1 ))))
+// \DUMMY|Add0~3  = CARRY((\SPI_ADC|data_from_adc [1] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & !\DUMMY|Add0~1 )) # (!\SPI_ADC|data_from_adc [1] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1]) # (!\DUMMY|Add0~1 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [1]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~1 ),
+	.combout(\DUMMY|Add0~2_combout ),
+	.cout(\DUMMY|Add0~3 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~2 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y23_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~2_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N0
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[0]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[0]~feeder_combout  = \SPI_ADC|shift_reg [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N1
+dffeas \SPI_ADC|data_from_adc[0] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N4
+cycloneiii_lcell_comb \DUMMY|Add0~0 (
+// Equation(s):
+// \DUMMY|Add0~0_combout  = (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & (\SPI_ADC|data_from_adc [0] & VCC)) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & (\SPI_ADC|data_from_adc [0] $ (VCC)))
+// \DUMMY|Add0~1  = CARRY((!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & \SPI_ADC|data_from_adc [0]))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0]),
+	.datab(\SPI_ADC|data_from_adc [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|Add0~0_combout ),
+	.cout(\DUMMY|Add0~1 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~0 .lut_mask = 16'h9944;
+defparam \DUMMY|Add0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N18
+cycloneiii_lcell_comb \DUMMY|Add0~14 (
+// Equation(s):
+// \DUMMY|Add0~14_combout  = (\SPI_ADC|data_from_adc [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (!\DUMMY|Add0~13 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (\DUMMY|Add0~13  & VCC)))) # (!\SPI_ADC|data_from_adc 
+// [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & ((\DUMMY|Add0~13 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (!\DUMMY|Add0~13 ))))
+// \DUMMY|Add0~15  = CARRY((\SPI_ADC|data_from_adc [7] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & !\DUMMY|Add0~13 )) # (!\SPI_ADC|data_from_adc [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7]) # (!\DUMMY|Add0~13 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [7]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~13 ),
+	.combout(\DUMMY|Add0~14_combout ),
+	.cout(\DUMMY|Add0~15 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~14 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N20
+cycloneiii_lcell_comb \DUMMY|Add0~16 (
+// Equation(s):
+// \DUMMY|Add0~16_combout  = ((\SPI_ADC|data_from_adc [8] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] $ (\DUMMY|Add0~15 )))) # (GND)
+// \DUMMY|Add0~17  = CARRY((\SPI_ADC|data_from_adc [8] & ((!\DUMMY|Add0~15 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]))) # (!\SPI_ADC|data_from_adc [8] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] & !\DUMMY|Add0~15 )))
+
+	.dataa(\SPI_ADC|data_from_adc [8]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~15 ),
+	.combout(\DUMMY|Add0~16_combout ),
+	.cout(\DUMMY|Add0~17 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~16 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N22
+cycloneiii_lcell_comb \DUMMY|Add0~18 (
+// Equation(s):
+// \DUMMY|Add0~18_combout  = \SPI_ADC|data_from_adc [9] $ (\DUMMY|Add0~17  $ (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|data_from_adc [9]),
+	.datac(gnd),
+	.datad(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]),
+	.cin(\DUMMY|Add0~17 ),
+	.combout(\DUMMY|Add0~18_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|Add0~18 .lut_mask = 16'h3CC3;
+defparam \DUMMY|Add0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N26
+cycloneiii_lcell_comb \DUMMY|Add3~0 (
+// Equation(s):
+// \DUMMY|Add3~0_combout  = \DUMMY|Add0~14_combout  $ (VCC)
+// \DUMMY|Add3~1  = CARRY(\DUMMY|Add0~14_combout )
+
+	.dataa(gnd),
+	.datab(\DUMMY|Add0~14_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|Add3~0_combout ),
+	.cout(\DUMMY|Add3~1 ));
+// synopsys translate_off
+defparam \DUMMY|Add3~0 .lut_mask = 16'h33CC;
+defparam \DUMMY|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N28
+cycloneiii_lcell_comb \DUMMY|Add3~2 (
+// Equation(s):
+// \DUMMY|Add3~2_combout  = (\DUMMY|Add0~16_combout  & (!\DUMMY|Add3~1 )) # (!\DUMMY|Add0~16_combout  & ((\DUMMY|Add3~1 ) # (GND)))
+// \DUMMY|Add3~3  = CARRY((!\DUMMY|Add3~1 ) # (!\DUMMY|Add0~16_combout ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|Add0~16_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add3~1 ),
+	.combout(\DUMMY|Add3~2_combout ),
+	.cout(\DUMMY|Add3~3 ));
+// synopsys translate_off
+defparam \DUMMY|Add3~2 .lut_mask = 16'h3C3F;
+defparam \DUMMY|Add3~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N30
+cycloneiii_lcell_comb \DUMMY|Add3~4 (
+// Equation(s):
+// \DUMMY|Add3~4_combout  = \DUMMY|Add0~18_combout  $ (\DUMMY|Add3~3 )
+
+	.dataa(\DUMMY|Add0~18_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\DUMMY|Add3~3 ),
+	.combout(\DUMMY|Add3~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|Add3~4 .lut_mask = 16'h5A5A;
+defparam \DUMMY|Add3~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y23_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~4_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 8;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 8;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: M9K_X25_Y19_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~2_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N27
+dffeas \DUMMY|data_out[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[7] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N9
+dffeas \DUMMY|data_out[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[2] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N5
+dffeas \DUMMY|data_out[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[0] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N28
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~13 (
+// Equation(s):
+// \SPI_DAC|shift_reg~13_combout  = (!\SPI_DAC|dac_cs~q  & (\DUMMY|data_out [0] & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\DUMMY|data_out [0]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~13 .lut_mask = 16'h5000;
+defparam \SPI_DAC|shift_reg~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N29
+dffeas \SPI_DAC|shift_reg[2] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N7
+dffeas \DUMMY|data_out[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[1] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N26
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~12 (
+// Equation(s):
+// \SPI_DAC|shift_reg~12_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [2])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [1]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [2]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [2]),
+	.datac(\DUMMY|data_out [1]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~12 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N27
+dffeas \SPI_DAC|shift_reg[3] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N4
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~11 (
+// Equation(s):
+// \SPI_DAC|shift_reg~11_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q  & ((\SPI_DAC|shift_reg [3]))) # (!\SPI_DAC|dac_cs~q  & (\DUMMY|data_out [2])))) # (!\SPI_DAC|dac_start~q  & (((\SPI_DAC|shift_reg [3]))))
+
+	.dataa(\DUMMY|data_out [2]),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(\SPI_DAC|shift_reg [3]),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~11 .lut_mask = 16'hF0B8;
+defparam \SPI_DAC|shift_reg~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N5
+dffeas \SPI_DAC|shift_reg[4] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N11
+dffeas \DUMMY|data_out[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[3] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N2
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~10 (
+// Equation(s):
+// \SPI_DAC|shift_reg~10_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [4])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [3]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [4]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [4]),
+	.datac(\DUMMY|data_out [3]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~10 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N3
+dffeas \SPI_DAC|shift_reg[5] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N13
+dffeas \DUMMY|data_out[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[4] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N0
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~9 (
+// Equation(s):
+// \SPI_DAC|shift_reg~9_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [5])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [4]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [5]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [5]),
+	.datac(\DUMMY|data_out [4]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~9 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N1
+dffeas \SPI_DAC|shift_reg[6] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N15
+dffeas \DUMMY|data_out[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[5] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N18
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~8 (
+// Equation(s):
+// \SPI_DAC|shift_reg~8_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [6])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [5]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [6]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [6]),
+	.datac(\DUMMY|data_out [5]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~8 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N19
+dffeas \SPI_DAC|shift_reg[7] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N17
+dffeas \DUMMY|data_out[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[6] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N8
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~7 (
+// Equation(s):
+// \SPI_DAC|shift_reg~7_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [7])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [6]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [7]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [7]),
+	.datac(\DUMMY|data_out [6]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~7 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N9
+dffeas \SPI_DAC|shift_reg[8] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N14
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~6 (
+// Equation(s):
+// \SPI_DAC|shift_reg~6_combout  = (\SPI_DAC|dac_cs~q  & (((\SPI_DAC|shift_reg [8])))) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & (\DUMMY|data_out [7])) # (!\SPI_DAC|dac_start~q  & ((\SPI_DAC|shift_reg [8])))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\DUMMY|data_out [7]),
+	.datac(\SPI_DAC|shift_reg [8]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~6 .lut_mask = 16'hE4F0;
+defparam \SPI_DAC|shift_reg~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N15
+dffeas \SPI_DAC|shift_reg[9] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N29
+dffeas \DUMMY|data_out[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add3~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[8] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N12
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~5 (
+// Equation(s):
+// \SPI_DAC|shift_reg~5_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [9])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [8]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [9]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [9]),
+	.datac(\DUMMY|data_out [8]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~5 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N13
+dffeas \SPI_DAC|shift_reg[10] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[10] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N24
+cycloneiii_lcell_comb \DUMMY|data_out[9]~0 (
+// Equation(s):
+// \DUMMY|data_out[9]~0_combout  = !\DUMMY|Add3~4_combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\DUMMY|Add3~4_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|data_out[9]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|data_out[9]~0 .lut_mask = 16'h0F0F;
+defparam \DUMMY|data_out[9]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N25
+dffeas \DUMMY|data_out[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|data_out[9]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[9] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N26
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~4 (
+// Equation(s):
+// \SPI_DAC|shift_reg~4_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [10])) # (!\SPI_DAC|dac_cs~q  & ((\DUMMY|data_out [9]))))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [10]))
+
+	.dataa(\SPI_DAC|shift_reg [10]),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(\DUMMY|data_out [9]),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~4 .lut_mask = 16'hAAE2;
+defparam \SPI_DAC|shift_reg~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N27
+dffeas \SPI_DAC|shift_reg[11] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[11] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N22
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~3 (
+// Equation(s):
+// \SPI_DAC|shift_reg~3_combout  = (\SPI_DAC|shift_reg [11]) # ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [11]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~3 .lut_mask = 16'hF5F0;
+defparam \SPI_DAC|shift_reg~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N23
+dffeas \SPI_DAC|shift_reg[12] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[12] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N30
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~2 (
+// Equation(s):
+// \SPI_DAC|shift_reg~2_combout  = (\SPI_DAC|shift_reg [12] & ((\SPI_DAC|dac_cs~q ) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [12]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~2 .lut_mask = 16'hA0F0;
+defparam \SPI_DAC|shift_reg~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N31
+dffeas \SPI_DAC|shift_reg[13] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[13] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N10
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~1 (
+// Equation(s):
+// \SPI_DAC|shift_reg~1_combout  = (\SPI_DAC|shift_reg [13]) # ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [13]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~1 .lut_mask = 16'hF5F0;
+defparam \SPI_DAC|shift_reg~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N11
+dffeas \SPI_DAC|shift_reg[14] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[14] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N16
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~0 (
+// Equation(s):
+// \SPI_DAC|shift_reg~0_combout  = (\SPI_DAC|shift_reg [14] & ((\SPI_DAC|dac_cs~q ) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(\SPI_DAC|shift_reg [14]),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~0 .lut_mask = 16'hBB00;
+defparam \SPI_DAC|shift_reg~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N17
+dffeas \SPI_DAC|shift_reg[15] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[15] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N14
+cycloneiii_lcell_comb \SCK~0 (
+// Equation(s):
+// \SCK~0_combout  = (\SPI_ADC|clk_1MHz~q  & (!\SPI_DAC|clk_1MHz~q  & ((\SPI_DAC|dac_cs~q )))) # (!\SPI_ADC|clk_1MHz~q  & ((\SPI_ADC|adc_cs~q ) # ((!\SPI_DAC|clk_1MHz~q  & \SPI_DAC|dac_cs~q ))))
+
+	.dataa(\SPI_ADC|clk_1MHz~q ),
+	.datab(\SPI_DAC|clk_1MHz~q ),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SCK~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCK~0 .lut_mask = 16'h7350;
+defparam \SCK~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N28
+cycloneiii_lcell_comb \SPI_DAC|Equal2~0 (
+// Equation(s):
+// \SPI_DAC|Equal2~0_combout  = (!\SPI_DAC|state [4]) # (!\SPI_DAC|Equal1~0_combout )
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal2~0 .lut_mask = 16'h3F3F;
+defparam \SPI_DAC|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N29
+dffeas \SPI_DAC|dac_ld (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|Equal2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_ld~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_ld .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_ld .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N1
+cycloneiii_io_ibuf \SW[9]~input (
+	.i(SW[9]),
+	.ibar(gnd),
+	.o(\SW[9]~input_o ));
+// synopsys translate_off
+defparam \SW[9]~input .bus_hold = "false";
+defparam \SW[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N8
+cycloneiii_lcell_comb \SPI_ADC|Selector6~0 (
+// Equation(s):
+// \SPI_ADC|Selector6~0_combout  = (\SPI_ADC|state [0]) # ((\SPI_ADC|state [1] & ((\SW[9]~input_o ))) # (!\SPI_ADC|state [1] & (\SPI_ADC|adc_start~q )))
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(\SW[9]~input_o ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~0 .lut_mask = 16'hFFCA;
+defparam \SPI_ADC|Selector6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N30
+cycloneiii_lcell_comb \SPI_ADC|Selector6~1 (
+// Equation(s):
+// \SPI_ADC|Selector6~1_combout  = (!\SPI_ADC|state [3] & (!\SPI_ADC|state [2] & (\SPI_ADC|Selector6~0_combout  & !\SPI_ADC|state [4])))
+
+	.dataa(\SPI_ADC|state [3]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|Selector6~0_combout ),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~1 .lut_mask = 16'h0010;
+defparam \SPI_ADC|Selector6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N31
+dffeas \SPI_ADC|adc_din (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Selector6~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_din~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_din .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_din .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N4
+cycloneiii_lcell_comb \PWM_DC|count[1]~9 (
+// Equation(s):
+// \PWM_DC|count[1]~9_combout  = (\PWM_DC|count [0] & (\PWM_DC|count [1] $ (VCC))) # (!\PWM_DC|count [0] & (\PWM_DC|count [1] & VCC))
+// \PWM_DC|count[1]~10  = CARRY((\PWM_DC|count [0] & \PWM_DC|count [1]))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\PWM_DC|count [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\PWM_DC|count[1]~9_combout ),
+	.cout(\PWM_DC|count[1]~10 ));
+// synopsys translate_off
+defparam \PWM_DC|count[1]~9 .lut_mask = 16'h6688;
+defparam \PWM_DC|count[1]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N5
+dffeas \PWM_DC|count[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[1]~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[1] .is_wysiwyg = "true";
+defparam \PWM_DC|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N6
+cycloneiii_lcell_comb \PWM_DC|count[2]~11 (
+// Equation(s):
+// \PWM_DC|count[2]~11_combout  = (\PWM_DC|count [2] & (!\PWM_DC|count[1]~10 )) # (!\PWM_DC|count [2] & ((\PWM_DC|count[1]~10 ) # (GND)))
+// \PWM_DC|count[2]~12  = CARRY((!\PWM_DC|count[1]~10 ) # (!\PWM_DC|count [2]))
+
+	.dataa(\PWM_DC|count [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[1]~10 ),
+	.combout(\PWM_DC|count[2]~11_combout ),
+	.cout(\PWM_DC|count[2]~12 ));
+// synopsys translate_off
+defparam \PWM_DC|count[2]~11 .lut_mask = 16'h5A5F;
+defparam \PWM_DC|count[2]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N7
+dffeas \PWM_DC|count[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[2]~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[2] .is_wysiwyg = "true";
+defparam \PWM_DC|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N8
+cycloneiii_lcell_comb \PWM_DC|count[3]~13 (
+// Equation(s):
+// \PWM_DC|count[3]~13_combout  = (\PWM_DC|count [3] & (\PWM_DC|count[2]~12  $ (GND))) # (!\PWM_DC|count [3] & (!\PWM_DC|count[2]~12  & VCC))
+// \PWM_DC|count[3]~14  = CARRY((\PWM_DC|count [3] & !\PWM_DC|count[2]~12 ))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[2]~12 ),
+	.combout(\PWM_DC|count[3]~13_combout ),
+	.cout(\PWM_DC|count[3]~14 ));
+// synopsys translate_off
+defparam \PWM_DC|count[3]~13 .lut_mask = 16'hC30C;
+defparam \PWM_DC|count[3]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N9
+dffeas \PWM_DC|count[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[3]~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[3] .is_wysiwyg = "true";
+defparam \PWM_DC|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N10
+cycloneiii_lcell_comb \PWM_DC|count[4]~15 (
+// Equation(s):
+// \PWM_DC|count[4]~15_combout  = (\PWM_DC|count [4] & (!\PWM_DC|count[3]~14 )) # (!\PWM_DC|count [4] & ((\PWM_DC|count[3]~14 ) # (GND)))
+// \PWM_DC|count[4]~16  = CARRY((!\PWM_DC|count[3]~14 ) # (!\PWM_DC|count [4]))
+
+	.dataa(\PWM_DC|count [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[3]~14 ),
+	.combout(\PWM_DC|count[4]~15_combout ),
+	.cout(\PWM_DC|count[4]~16 ));
+// synopsys translate_off
+defparam \PWM_DC|count[4]~15 .lut_mask = 16'h5A5F;
+defparam \PWM_DC|count[4]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N11
+dffeas \PWM_DC|count[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[4]~15_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[4] .is_wysiwyg = "true";
+defparam \PWM_DC|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N12
+cycloneiii_lcell_comb \PWM_DC|count[5]~17 (
+// Equation(s):
+// \PWM_DC|count[5]~17_combout  = (\PWM_DC|count [5] & (\PWM_DC|count[4]~16  $ (GND))) # (!\PWM_DC|count [5] & (!\PWM_DC|count[4]~16  & VCC))
+// \PWM_DC|count[5]~18  = CARRY((\PWM_DC|count [5] & !\PWM_DC|count[4]~16 ))
+
+	.dataa(\PWM_DC|count [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[4]~16 ),
+	.combout(\PWM_DC|count[5]~17_combout ),
+	.cout(\PWM_DC|count[5]~18 ));
+// synopsys translate_off
+defparam \PWM_DC|count[5]~17 .lut_mask = 16'hA50A;
+defparam \PWM_DC|count[5]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N13
+dffeas \PWM_DC|count[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[5]~17_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[5] .is_wysiwyg = "true";
+defparam \PWM_DC|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N14
+cycloneiii_lcell_comb \PWM_DC|count[6]~19 (
+// Equation(s):
+// \PWM_DC|count[6]~19_combout  = (\PWM_DC|count [6] & (!\PWM_DC|count[5]~18 )) # (!\PWM_DC|count [6] & ((\PWM_DC|count[5]~18 ) # (GND)))
+// \PWM_DC|count[6]~20  = CARRY((!\PWM_DC|count[5]~18 ) # (!\PWM_DC|count [6]))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[5]~18 ),
+	.combout(\PWM_DC|count[6]~19_combout ),
+	.cout(\PWM_DC|count[6]~20 ));
+// synopsys translate_off
+defparam \PWM_DC|count[6]~19 .lut_mask = 16'h3C3F;
+defparam \PWM_DC|count[6]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N15
+dffeas \PWM_DC|count[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[6]~19_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[6] .is_wysiwyg = "true";
+defparam \PWM_DC|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N16
+cycloneiii_lcell_comb \PWM_DC|count[7]~21 (
+// Equation(s):
+// \PWM_DC|count[7]~21_combout  = (\PWM_DC|count [7] & (\PWM_DC|count[6]~20  $ (GND))) # (!\PWM_DC|count [7] & (!\PWM_DC|count[6]~20  & VCC))
+// \PWM_DC|count[7]~22  = CARRY((\PWM_DC|count [7] & !\PWM_DC|count[6]~20 ))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[6]~20 ),
+	.combout(\PWM_DC|count[7]~21_combout ),
+	.cout(\PWM_DC|count[7]~22 ));
+// synopsys translate_off
+defparam \PWM_DC|count[7]~21 .lut_mask = 16'hC30C;
+defparam \PWM_DC|count[7]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N17
+dffeas \PWM_DC|count[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[7]~21_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[7] .is_wysiwyg = "true";
+defparam \PWM_DC|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N18
+cycloneiii_lcell_comb \PWM_DC|count[8]~23 (
+// Equation(s):
+// \PWM_DC|count[8]~23_combout  = (\PWM_DC|count [8] & (!\PWM_DC|count[7]~22 )) # (!\PWM_DC|count [8] & ((\PWM_DC|count[7]~22 ) # (GND)))
+// \PWM_DC|count[8]~24  = CARRY((!\PWM_DC|count[7]~22 ) # (!\PWM_DC|count [8]))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[7]~22 ),
+	.combout(\PWM_DC|count[8]~23_combout ),
+	.cout(\PWM_DC|count[8]~24 ));
+// synopsys translate_off
+defparam \PWM_DC|count[8]~23 .lut_mask = 16'h3C3F;
+defparam \PWM_DC|count[8]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N19
+dffeas \PWM_DC|count[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[8]~23_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[8] .is_wysiwyg = "true";
+defparam \PWM_DC|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N20
+cycloneiii_lcell_comb \PWM_DC|count[9]~25 (
+// Equation(s):
+// \PWM_DC|count[9]~25_combout  = \PWM_DC|count[8]~24  $ (!\PWM_DC|count [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\PWM_DC|count [9]),
+	.cin(\PWM_DC|count[8]~24 ),
+	.combout(\PWM_DC|count[9]~25_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|count[9]~25 .lut_mask = 16'hF00F;
+defparam \PWM_DC|count[9]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N21
+dffeas \PWM_DC|count[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[9]~25_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[9] .is_wysiwyg = "true";
+defparam \PWM_DC|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N25
+dffeas \PWM_DC|d[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[9] .is_wysiwyg = "true";
+defparam \PWM_DC|d[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N23
+dffeas \PWM_DC|d[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[8] .is_wysiwyg = "true";
+defparam \PWM_DC|d[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N21
+dffeas \PWM_DC|d[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[7] .is_wysiwyg = "true";
+defparam \PWM_DC|d[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N19
+dffeas \PWM_DC|d[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[6] .is_wysiwyg = "true";
+defparam \PWM_DC|d[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N17
+dffeas \PWM_DC|d[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[5] .is_wysiwyg = "true";
+defparam \PWM_DC|d[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N15
+dffeas \PWM_DC|d[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[4] .is_wysiwyg = "true";
+defparam \PWM_DC|d[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N13
+dffeas \PWM_DC|d[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[3] .is_wysiwyg = "true";
+defparam \PWM_DC|d[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N11
+dffeas \PWM_DC|d[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[2] .is_wysiwyg = "true";
+defparam \PWM_DC|d[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N9
+dffeas \PWM_DC|d[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[1] .is_wysiwyg = "true";
+defparam \PWM_DC|d[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N7
+dffeas \PWM_DC|d[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[0] .is_wysiwyg = "true";
+defparam \PWM_DC|d[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N6
+cycloneiii_lcell_comb \PWM_DC|LessThan0~1 (
+// Equation(s):
+// \PWM_DC|LessThan0~1_cout  = CARRY((!\PWM_DC|d [0] & \PWM_DC|count [0]))
+
+	.dataa(\PWM_DC|d [0]),
+	.datab(\PWM_DC|count [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~1_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~1 .lut_mask = 16'h0044;
+defparam \PWM_DC|LessThan0~1 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N8
+cycloneiii_lcell_comb \PWM_DC|LessThan0~3 (
+// Equation(s):
+// \PWM_DC|LessThan0~3_cout  = CARRY((\PWM_DC|count [1] & (\PWM_DC|d [1] & !\PWM_DC|LessThan0~1_cout )) # (!\PWM_DC|count [1] & ((\PWM_DC|d [1]) # (!\PWM_DC|LessThan0~1_cout ))))
+
+	.dataa(\PWM_DC|count [1]),
+	.datab(\PWM_DC|d [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~1_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~3_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~3 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~3 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N10
+cycloneiii_lcell_comb \PWM_DC|LessThan0~5 (
+// Equation(s):
+// \PWM_DC|LessThan0~5_cout  = CARRY((\PWM_DC|d [2] & (\PWM_DC|count [2] & !\PWM_DC|LessThan0~3_cout )) # (!\PWM_DC|d [2] & ((\PWM_DC|count [2]) # (!\PWM_DC|LessThan0~3_cout ))))
+
+	.dataa(\PWM_DC|d [2]),
+	.datab(\PWM_DC|count [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~3_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~5_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~5 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~5 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N12
+cycloneiii_lcell_comb \PWM_DC|LessThan0~7 (
+// Equation(s):
+// \PWM_DC|LessThan0~7_cout  = CARRY((\PWM_DC|d [3] & ((!\PWM_DC|LessThan0~5_cout ) # (!\PWM_DC|count [3]))) # (!\PWM_DC|d [3] & (!\PWM_DC|count [3] & !\PWM_DC|LessThan0~5_cout )))
+
+	.dataa(\PWM_DC|d [3]),
+	.datab(\PWM_DC|count [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~5_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~7_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~7 .lut_mask = 16'h002B;
+defparam \PWM_DC|LessThan0~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N14
+cycloneiii_lcell_comb \PWM_DC|LessThan0~9 (
+// Equation(s):
+// \PWM_DC|LessThan0~9_cout  = CARRY((\PWM_DC|d [4] & (\PWM_DC|count [4] & !\PWM_DC|LessThan0~7_cout )) # (!\PWM_DC|d [4] & ((\PWM_DC|count [4]) # (!\PWM_DC|LessThan0~7_cout ))))
+
+	.dataa(\PWM_DC|d [4]),
+	.datab(\PWM_DC|count [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~7_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~9_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~9 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~9 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N16
+cycloneiii_lcell_comb \PWM_DC|LessThan0~11 (
+// Equation(s):
+// \PWM_DC|LessThan0~11_cout  = CARRY((\PWM_DC|count [5] & (\PWM_DC|d [5] & !\PWM_DC|LessThan0~9_cout )) # (!\PWM_DC|count [5] & ((\PWM_DC|d [5]) # (!\PWM_DC|LessThan0~9_cout ))))
+
+	.dataa(\PWM_DC|count [5]),
+	.datab(\PWM_DC|d [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~9_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~11_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~11 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N18
+cycloneiii_lcell_comb \PWM_DC|LessThan0~13 (
+// Equation(s):
+// \PWM_DC|LessThan0~13_cout  = CARRY((\PWM_DC|count [6] & ((!\PWM_DC|LessThan0~11_cout ) # (!\PWM_DC|d [6]))) # (!\PWM_DC|count [6] & (!\PWM_DC|d [6] & !\PWM_DC|LessThan0~11_cout )))
+
+	.dataa(\PWM_DC|count [6]),
+	.datab(\PWM_DC|d [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~11_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~13_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~13 .lut_mask = 16'h002B;
+defparam \PWM_DC|LessThan0~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N20
+cycloneiii_lcell_comb \PWM_DC|LessThan0~15 (
+// Equation(s):
+// \PWM_DC|LessThan0~15_cout  = CARRY((\PWM_DC|count [7] & (\PWM_DC|d [7] & !\PWM_DC|LessThan0~13_cout )) # (!\PWM_DC|count [7] & ((\PWM_DC|d [7]) # (!\PWM_DC|LessThan0~13_cout ))))
+
+	.dataa(\PWM_DC|count [7]),
+	.datab(\PWM_DC|d [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~13_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~15_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~15 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N22
+cycloneiii_lcell_comb \PWM_DC|LessThan0~17 (
+// Equation(s):
+// \PWM_DC|LessThan0~17_cout  = CARRY((\PWM_DC|d [8] & (\PWM_DC|count [8] & !\PWM_DC|LessThan0~15_cout )) # (!\PWM_DC|d [8] & ((\PWM_DC|count [8]) # (!\PWM_DC|LessThan0~15_cout ))))
+
+	.dataa(\PWM_DC|d [8]),
+	.datab(\PWM_DC|count [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~15_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~17_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~17 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N24
+cycloneiii_lcell_comb \PWM_DC|LessThan0~18 (
+// Equation(s):
+// \PWM_DC|LessThan0~18_combout  = (\PWM_DC|count [9] & ((\PWM_DC|LessThan0~17_cout ) # (!\PWM_DC|d [9]))) # (!\PWM_DC|count [9] & (!\PWM_DC|d [9] & \PWM_DC|LessThan0~17_cout ))
+
+	.dataa(\PWM_DC|count [9]),
+	.datab(\PWM_DC|d [9]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\PWM_DC|LessThan0~17_cout ),
+	.combout(\PWM_DC|LessThan0~18_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~18 .lut_mask = 16'hB2B2;
+defparam \PWM_DC|LessThan0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y21_N8
+cycloneiii_lcell_comb \PWM_DC|pwm_out~0 (
+// Equation(s):
+// \PWM_DC|pwm_out~0_combout  = !\PWM_DC|LessThan0~18_combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\PWM_DC|LessThan0~18_combout ),
+	.cin(gnd),
+	.combout(\PWM_DC|pwm_out~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|pwm_out~0 .lut_mask = 16'h00FF;
+defparam \PWM_DC|pwm_out~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y21_N9
+dffeas \PWM_DC|pwm_out (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|pwm_out~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|pwm_out~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|pwm_out .is_wysiwyg = "true";
+defparam \PWM_DC|pwm_out .power_up = "low";
+// synopsys translate_on
+
+assign HEX0_D[0] = \HEX0_D[0]~output_o ;
+
+assign HEX0_D[1] = \HEX0_D[1]~output_o ;
+
+assign HEX0_D[2] = \HEX0_D[2]~output_o ;
+
+assign HEX0_D[3] = \HEX0_D[3]~output_o ;
+
+assign HEX0_D[4] = \HEX0_D[4]~output_o ;
+
+assign HEX0_D[5] = \HEX0_D[5]~output_o ;
+
+assign HEX0_D[6] = \HEX0_D[6]~output_o ;
+
+assign HEX1_D[0] = \HEX1_D[0]~output_o ;
+
+assign HEX1_D[1] = \HEX1_D[1]~output_o ;
+
+assign HEX1_D[2] = \HEX1_D[2]~output_o ;
+
+assign HEX1_D[3] = \HEX1_D[3]~output_o ;
+
+assign HEX1_D[4] = \HEX1_D[4]~output_o ;
+
+assign HEX1_D[5] = \HEX1_D[5]~output_o ;
+
+assign HEX1_D[6] = \HEX1_D[6]~output_o ;
+
+assign HEX2_D[0] = \HEX2_D[0]~output_o ;
+
+assign HEX2_D[1] = \HEX2_D[1]~output_o ;
+
+assign HEX2_D[2] = \HEX2_D[2]~output_o ;
+
+assign HEX2_D[3] = \HEX2_D[3]~output_o ;
+
+assign HEX2_D[4] = \HEX2_D[4]~output_o ;
+
+assign HEX2_D[5] = \HEX2_D[5]~output_o ;
+
+assign HEX2_D[6] = \HEX2_D[6]~output_o ;
+
+assign HEX3_D[0] = \HEX3_D[0]~output_o ;
+
+assign HEX3_D[1] = \HEX3_D[1]~output_o ;
+
+assign HEX3_D[2] = \HEX3_D[2]~output_o ;
+
+assign HEX3_D[3] = \HEX3_D[3]~output_o ;
+
+assign HEX3_D[4] = \HEX3_D[4]~output_o ;
+
+assign HEX3_D[5] = \HEX3_D[5]~output_o ;
+
+assign HEX3_D[6] = \HEX3_D[6]~output_o ;
+
+assign DAC_SDI = \DAC_SDI~output_o ;
+
+assign SCK = \SCK~output_o ;
+
+assign DAC_CS = \DAC_CS~output_o ;
+
+assign DAC_LD = \DAC_LD~output_o ;
+
+assign ADC_SDI = \ADC_SDI~output_o ;
+
+assign ADC_CS = \ADC_CS~output_o ;
+
+assign LEDG[0] = \LEDG[0]~output_o ;
+
+assign LEDG[1] = \LEDG[1]~output_o ;
+
+assign LEDG[2] = \LEDG[2]~output_o ;
+
+assign LEDG[3] = \LEDG[3]~output_o ;
+
+assign LEDG[4] = \LEDG[4]~output_o ;
+
+assign LEDG[5] = \LEDG[5]~output_o ;
+
+assign LEDG[6] = \LEDG[6]~output_o ;
+
+assign LEDG[7] = \LEDG[7]~output_o ;
+
+assign LEDG[8] = \LEDG[8]~output_o ;
+
+assign LEDG[9] = \LEDG[9]~output_o ;
+
+assign PWM_OUT = \PWM_OUT~output_o ;
+
+endmodule
diff --git a/part_4/ex16/simulation/modelsim/top_6_1200mv_85c_v_slow.sdo b/part_4/ex16/simulation/modelsim/top_6_1200mv_85c_v_slow.sdo
new file mode 100755
index 0000000..c5657c7
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_6_1200mv_85c_v_slow.sdo
@@ -0,0 +1,8658 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "top")
+  (DATE "02/18/2014 18:26:56")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (718:718:718) (698:698:698))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (675:675:675) (646:646:646))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (811:811:811) (794:794:794))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (765:765:765) (762:762:762))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (768:768:768) (752:752:752))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (786:786:786) (786:786:786))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (757:757:757) (771:771:771))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (480:480:480) (494:494:494))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (465:465:465) (452:452:452))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (472:472:472) (454:454:454))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (448:448:448) (461:461:461))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (440:440:440) (455:455:455))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (939:939:939) (958:958:958))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (728:728:728) (749:749:749))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (653:653:653) (634:634:634))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (483:483:483) (466:466:466))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (582:582:582) (584:584:584))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (481:481:481) (494:494:494))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (469:469:469) (450:450:450))
+        (IOPATH i o (2035:2035:2035) (1911:1911:1911))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (572:572:572) (577:577:577))
+        (IOPATH i o (2045:2045:2045) (1921:1921:1921))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (901:901:901) (866:866:866))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1146:1146:1146) (1175:1175:1175))
+        (IOPATH i o (1921:1921:1921) (2045:2045:2045))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1134:1134:1134) (1161:1161:1161))
+        (IOPATH i o (1921:1921:1921) (2045:2045:2045))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1362:1362:1362) (1406:1406:1406))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1362:1362:1362) (1406:1406:1406))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_SDI\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1885:1885:1885) (2030:2030:2030))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE SCK\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2059:2059:2059) (2156:2156:2156))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_CS\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1323:1323:1323) (1241:1241:1241))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_LD\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1455:1455:1455) (1543:1543:1543))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE ADC_SDI\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2718:2718:2718) (2899:2899:2899))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE ADC_CS\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2963:2963:2963) (2927:2927:2927))
+        (IOPATH i o (1891:1891:1891) (2015:2015:2015))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1429:1429:1429) (1488:1488:1488))
+        (IOPATH i o (2271:2271:2271) (2135:2135:2135))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1550:1550:1550) (1573:1573:1573))
+        (IOPATH i o (2271:2271:2271) (2135:2135:2135))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1626:1626:1626) (1651:1651:1651))
+        (IOPATH i o (4139:4139:4139) (3839:3839:3839))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1159:1159:1159) (1219:1219:1219))
+        (IOPATH i o (2281:2281:2281) (2145:2145:2145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1322:1322:1322) (1331:1331:1331))
+        (IOPATH i o (2291:2291:2291) (2155:2155:2155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1458:1458:1458) (1452:1452:1452))
+        (IOPATH i o (2291:2291:2291) (2155:2155:2155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1241:1241:1241) (1248:1248:1248))
+        (IOPATH i o (2301:2301:2301) (2165:2165:2165))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[7\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1084:1084:1084) (1095:1095:1095))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[8\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1126:1126:1126) (1144:1144:1144))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[9\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1266:1266:1266) (1263:1263:1263))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE PWM_OUT\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2758:2758:2758) (2894:2894:2894))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[8\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[7\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[6\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[5\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[4\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[10\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3092:3092:3092) (3394:3394:3394))
+        (PORT datab (3165:3165:3165) (3444:3444:3444))
+        (PORT datac (3090:3090:3090) (3378:3378:3378))
+        (PORT datad (3177:3177:3177) (3465:3465:3465))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[3\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[2\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[0\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[1\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[14\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3082:3082:3082) (3380:3380:3380))
+        (PORT datab (3128:3128:3128) (3400:3400:3400))
+        (PORT datac (3072:3072:3072) (3340:3340:3340))
+        (PORT datad (3151:3151:3151) (3447:3447:3447))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[13\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3083:3083:3083) (3378:3378:3378))
+        (PORT datab (3122:3122:3122) (3392:3392:3392))
+        (PORT datac (3077:3077:3077) (3345:3345:3345))
+        (PORT datad (3155:3155:3155) (3453:3453:3453))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[9\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3090:3090:3090) (3395:3395:3395))
+        (PORT datab (3164:3164:3164) (3447:3447:3447))
+        (PORT datac (3100:3100:3100) (3376:3376:3376))
+        (PORT datad (3188:3188:3188) (3463:3463:3463))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[12\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3083:3083:3083) (3377:3377:3377))
+        (PORT datab (3123:3123:3123) (3394:3394:3394))
+        (PORT datac (3074:3074:3074) (3342:3342:3342))
+        (PORT datad (3154:3154:3154) (3451:3451:3451))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[12\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3091:3091:3091) (3396:3396:3396))
+        (PORT datab (3164:3164:3164) (3448:3448:3448))
+        (PORT datac (3099:3099:3099) (3377:3377:3377))
+        (PORT datad (3187:3187:3187) (3464:3464:3464))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[11\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3086:3086:3086) (3393:3393:3393))
+        (PORT datab (3167:3167:3167) (3452:3452:3452))
+        (PORT datac (3098:3098:3098) (3386:3386:3386))
+        (PORT datad (3187:3187:3187) (3474:3474:3474))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[11\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3082:3082:3082) (3377:3377:3377))
+        (PORT datab (3123:3123:3123) (3395:3395:3395))
+        (PORT datac (3074:3074:3074) (3342:3342:3342))
+        (PORT datad (3154:3154:3154) (3451:3451:3451))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[10\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3084:3084:3084) (3378:3378:3378))
+        (PORT datab (3123:3123:3123) (3393:3393:3393))
+        (PORT datac (3077:3077:3077) (3346:3346:3346))
+        (PORT datad (3155:3155:3155) (3453:3453:3453))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[9\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3084:3084:3084) (3380:3380:3380))
+        (PORT datab (3128:3128:3128) (3400:3400:3400))
+        (PORT datac (3072:3072:3072) (3340:3340:3340))
+        (PORT datad (3151:3151:3151) (3447:3447:3447))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[4\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3087:3087:3087) (3393:3393:3393))
+        (PORT datab (3167:3167:3167) (3452:3452:3452))
+        (PORT datac (3100:3100:3100) (3386:3386:3386))
+        (PORT datad (3188:3188:3188) (3473:3473:3473))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[3\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3167:3167:3167) (3446:3446:3446))
+        (PORT datac (3105:3105:3105) (3390:3390:3390))
+        (PORT datad (3194:3194:3194) (3478:3478:3478))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[2\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (3105:3105:3105) (3389:3389:3389))
+        (PORT datad (3194:3194:3194) (3478:3478:3478))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[1\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (681:681:681) (726:726:726))
+        (PORT datab (3175:3175:3175) (3460:3460:3460))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[2\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (666:666:666) (701:701:701))
+        (PORT datab (649:649:649) (692:692:692))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[3\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (704:704:704) (742:742:742))
+        (PORT datab (650:650:650) (703:703:703))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[4\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (676:676:676) (724:724:724))
+        (PORT datab (662:662:662) (694:694:694))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[5\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (679:679:679) (728:728:728))
+        (PORT datab (711:711:711) (752:752:752))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[6\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (678:678:678) (720:720:720))
+        (PORT datab (650:650:650) (694:694:694))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[7\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (671:671:671) (724:724:724))
+        (PORT datab (651:651:651) (705:705:705))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[8\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (678:678:678) (726:726:726))
+        (PORT datab (712:712:712) (752:752:752))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[9\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (606:606:606) (660:660:660))
+        (PORT datab (710:710:710) (753:753:753))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[10\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (676:676:676) (718:718:718))
+        (PORT datab (829:829:829) (858:858:858))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (377:377:377) (396:396:396))
+        (PORT datab (3019:3019:3019) (3275:3275:3275))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3030:3030:3030) (3305:3305:3305))
+        (PORT datab (538:538:538) (554:554:554))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (376:376:376))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (338:338:338) (369:369:369))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3027:3027:3027) (3307:3307:3307))
+        (PORT datab (569:569:569) (589:589:589))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3027:3027:3027) (3308:3308:3308))
+        (PORT datab (338:338:338) (368:368:368))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[13\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3091:3091:3091) (3394:3394:3394))
+        (PORT datab (3165:3165:3165) (3446:3446:3446))
+        (PORT datac (3090:3090:3090) (3380:3380:3380))
+        (PORT datad (3176:3176:3176) (3467:3467:3467))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[11\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (672:672:672) (723:723:723))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[12\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (713:713:713) (752:752:752))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[13\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (625:625:625) (673:673:673))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (373:373:373) (394:394:394))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (378:378:378) (402:402:402))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3027:3027:3027) (3307:3307:3307))
+        (PORT datab (371:371:371) (393:393:393))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[14\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3090:3090:3090) (3394:3394:3394))
+        (PORT datab (3165:3165:3165) (3451:3451:3451))
+        (PORT datac (3101:3101:3101) (3383:3383:3383))
+        (PORT datad (3190:3190:3190) (3470:3470:3470))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[14\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (604:604:604) (640:640:640))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3026:3026:3026) (3304:3304:3304))
+        (PORT datab (333:333:333) (364:364:364))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~20)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1314:1314:1314) (1368:1368:1368))
+        (PORT datab (1113:1113:1113) (1135:1135:1135))
+        (PORT datac (1073:1073:1073) (1096:1096:1096))
+        (PORT datad (1254:1254:1254) (1291:1291:1291))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1322:1322:1322) (1373:1373:1373))
+        (PORT datab (1108:1108:1108) (1125:1125:1125))
+        (PORT datac (1072:1072:1072) (1089:1089:1089))
+        (PORT datad (1256:1256:1256) (1288:1288:1288))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1312:1312:1312) (1364:1364:1364))
+        (PORT datab (1116:1116:1116) (1131:1131:1131))
+        (PORT datac (1076:1076:1076) (1093:1093:1093))
+        (PORT datad (1252:1252:1252) (1287:1287:1287))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (440:440:440))
+        (PORT datab (400:400:400) (423:423:423))
+        (PORT datac (1040:1040:1040) (1038:1038:1038))
+        (PORT datad (338:338:338) (359:359:359))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (413:413:413) (439:439:439))
+        (PORT datab (400:400:400) (423:423:423))
+        (PORT datac (1040:1040:1040) (1038:1038:1038))
+        (PORT datad (338:338:338) (358:358:358))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (413:413:413) (439:439:439))
+        (PORT datab (400:400:400) (427:427:427))
+        (PORT datac (1039:1039:1039) (1035:1035:1035))
+        (PORT datad (338:338:338) (354:354:354))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1108:1108:1108) (1117:1117:1117))
+        (PORT datab (230:230:230) (280:280:280))
+        (PORT datac (201:201:201) (245:245:245))
+        (PORT datad (199:199:199) (235:235:235))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1113:1113:1113) (1124:1124:1124))
+        (PORT datab (226:226:226) (273:273:273))
+        (PORT datac (197:197:197) (239:239:239))
+        (PORT datad (196:196:196) (229:229:229))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1112:1112:1112) (1122:1122:1122))
+        (PORT datab (227:227:227) (277:277:277))
+        (PORT datac (198:198:198) (243:243:243))
+        (PORT datad (197:197:197) (233:233:233))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (411:411:411) (438:438:438))
+        (PORT datab (367:367:367) (403:403:403))
+        (PORT datac (342:342:342) (372:372:372))
+        (PORT datad (1000:1000:1000) (992:992:992))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (440:440:440))
+        (PORT datab (364:364:364) (396:396:396))
+        (PORT datac (343:343:343) (369:369:369))
+        (PORT datad (1003:1003:1003) (991:991:991))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (413:413:413) (439:439:439))
+        (PORT datab (368:368:368) (400:400:400))
+        (PORT datac (343:343:343) (371:371:371))
+        (PORT datad (999:999:999) (990:990:990))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (282:282:282))
+        (PORT datab (1132:1132:1132) (1139:1139:1139))
+        (PORT datac (201:201:201) (247:247:247))
+        (PORT datad (199:199:199) (235:235:235))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (284:284:284))
+        (PORT datab (1131:1131:1131) (1133:1133:1133))
+        (PORT datac (199:199:199) (242:242:242))
+        (PORT datad (197:197:197) (231:231:231))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (286:286:286))
+        (PORT datab (1130:1130:1130) (1134:1134:1134))
+        (PORT datac (198:198:198) (242:242:242))
+        (PORT datad (197:197:197) (232:232:232))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (411:411:411) (438:438:438))
+        (PORT datab (607:607:607) (624:624:624))
+        (PORT datac (1309:1309:1309) (1308:1308:1308))
+        (PORT datad (339:339:339) (358:358:358))
+        (IOPATH dataa combout (341:341:341) (319:319:319))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (441:441:441))
+        (PORT datab (611:611:611) (628:628:628))
+        (PORT datac (1309:1309:1309) (1303:1303:1303))
+        (PORT datad (340:340:340) (359:359:359))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (441:441:441))
+        (PORT datab (610:610:610) (624:624:624))
+        (PORT datac (1309:1309:1309) (1304:1304:1304))
+        (PORT datad (342:342:342) (356:356:356))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (319:319:319))
+        (PORT datab (1277:1277:1277) (1359:1359:1359))
+        (PORT datac (218:218:218) (269:269:269))
+        (PORT datad (216:216:216) (255:255:255))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (319:319:319))
+        (PORT datab (1282:1282:1282) (1365:1365:1365))
+        (PORT datac (225:225:225) (277:277:277))
+        (PORT datad (221:221:221) (262:262:262))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (322:322:322))
+        (PORT datab (1278:1278:1278) (1366:1366:1366))
+        (PORT datac (224:224:224) (275:275:275))
+        (PORT datad (220:220:220) (261:261:261))
+        (IOPATH dataa combout (341:341:341) (319:319:319))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (323:323:323))
+        (PORT datab (1278:1278:1278) (1359:1359:1359))
+        (PORT datac (217:217:217) (267:267:267))
+        (PORT datad (214:214:214) (254:254:254))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (319:319:319))
+        (PORT datab (1279:1279:1279) (1361:1361:1361))
+        (PORT datac (221:221:221) (274:274:274))
+        (PORT datad (218:218:218) (260:260:260))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (321:321:321))
+        (PORT datab (1277:1277:1277) (1362:1362:1362))
+        (PORT datac (221:221:221) (272:272:272))
+        (PORT datad (218:218:218) (258:258:258))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (318:318:318))
+        (PORT datab (1282:1282:1282) (1364:1364:1364))
+        (PORT datac (225:225:225) (276:276:276))
+        (PORT datad (221:221:221) (262:262:262))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1320:1320:1320) (1370:1370:1370))
+        (PORT datab (1113:1113:1113) (1133:1133:1133))
+        (PORT datac (1075:1075:1075) (1093:1093:1093))
+        (PORT datad (1258:1258:1258) (1292:1292:1292))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1318:1318:1318) (1368:1368:1368))
+        (PORT datab (1113:1113:1113) (1131:1131:1131))
+        (PORT datac (1075:1075:1075) (1095:1095:1095))
+        (PORT datad (1258:1258:1258) (1292:1292:1292))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (323:323:323) (346:346:346))
+        (PORT datad (326:326:326) (344:344:344))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1109:1109:1109) (1118:1118:1118))
+        (PORT datab (227:227:227) (276:276:276))
+        (PORT datac (198:198:198) (241:241:241))
+        (PORT datad (197:197:197) (231:231:231))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A7\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1322:1322:1322) (1373:1373:1373))
+        (PORT datab (1108:1108:1108) (1124:1124:1124))
+        (PORT datad (1256:1256:1256) (1288:1288:1288))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (438:438:438))
+        (PORT datab (401:401:401) (430:430:430))
+        (PORT datac (1037:1037:1037) (1035:1035:1035))
+        (PORT datad (334:334:334) (354:354:354))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (310:310:310))
+        (PORT datab (260:260:260) (312:312:312))
+        (PORT datac (381:381:381) (416:416:416))
+        (PORT datad (218:218:218) (261:261:261))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1023:1023:1023) (1046:1046:1046))
+        (PORT datab (1031:1031:1031) (1040:1040:1040))
+        (PORT datac (1076:1076:1076) (1093:1093:1093))
+        (PORT datad (1264:1264:1264) (1314:1314:1314))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1287:1287:1287) (1338:1338:1338))
+        (PORT datab (1107:1107:1107) (1129:1129:1129))
+        (PORT datad (176:176:176) (202:202:202))
+        (IOPATH dataa combout (325:325:325) (328:328:328))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (309:309:309))
+        (PORT datab (257:257:257) (308:308:308))
+        (PORT datac (379:379:379) (414:414:414))
+        (PORT datad (220:220:220) (256:256:256))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (382:382:382) (408:408:408))
+        (PORT datac (547:547:547) (551:551:551))
+        (PORT datad (330:330:330) (350:350:350))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A7\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1321:1321:1321) (1372:1372:1372))
+        (PORT datad (1255:1255:1255) (1292:1292:1292))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (309:309:309))
+        (PORT datab (372:372:372) (394:394:394))
+        (PORT datac (1021:1021:1021) (1006:1006:1006))
+        (PORT datad (217:217:217) (261:261:261))
+        (IOPATH dataa combout (341:341:341) (328:328:328))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (240:240:240) (306:306:306))
+        (PORT datab (258:258:258) (307:307:307))
+        (PORT datac (386:386:386) (421:421:421))
+        (PORT datad (214:214:214) (257:257:257))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (403:403:403))
+        (PORT datab (337:337:337) (366:366:366))
+        (PORT datac (345:345:345) (368:368:368))
+        (PORT datad (327:327:327) (346:346:346))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1307:1307:1307) (1357:1357:1357))
+        (PORT datab (1031:1031:1031) (1041:1041:1041))
+        (PORT datac (1077:1077:1077) (1096:1096:1096))
+        (PORT datad (1250:1250:1250) (1288:1288:1288))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (300:300:300) (310:310:310))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (309:309:309))
+        (PORT datab (258:258:258) (310:310:310))
+        (PORT datac (385:385:385) (419:419:419))
+        (PORT datad (218:218:218) (260:260:260))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (406:406:406))
+        (PORT datab (1324:1324:1324) (1320:1320:1320))
+        (PORT datac (583:583:583) (603:603:603))
+        (PORT datad (327:327:327) (344:344:344))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (410:410:410) (435:435:435))
+        (PORT datab (370:370:370) (401:401:401))
+        (PORT datac (342:342:342) (370:370:370))
+        (PORT datad (1000:1000:1000) (988:988:988))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (284:284:284))
+        (PORT datab (226:226:226) (274:274:274))
+        (PORT datac (196:196:196) (240:240:240))
+        (PORT datad (197:197:197) (231:231:231))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (283:283:283))
+        (PORT datab (230:230:230) (278:278:278))
+        (PORT datac (201:201:201) (245:245:245))
+        (PORT datad (196:196:196) (229:229:229))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (283:283:283))
+        (PORT datab (1131:1131:1131) (1133:1133:1133))
+        (PORT datac (198:198:198) (242:242:242))
+        (PORT datad (196:196:196) (231:231:231))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (289:289:289))
+        (PORT datab (227:227:227) (274:274:274))
+        (PORT datac (197:197:197) (239:239:239))
+        (PORT datad (199:199:199) (235:235:235))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (662:662:662))
+        (PORT datab (380:380:380) (418:418:418))
+        (PORT datac (558:558:558) (565:565:565))
+        (PORT datad (568:568:568) (587:587:587))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (647:647:647) (660:660:660))
+        (PORT datab (377:377:377) (415:415:415))
+        (PORT datac (561:561:561) (569:569:569))
+        (PORT datad (572:572:572) (586:586:586))
+        (IOPATH dataa combout (350:350:350) (367:367:367))
+        (IOPATH datab combout (350:350:350) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (664:664:664))
+        (PORT datab (380:380:380) (418:418:418))
+        (PORT datac (560:560:560) (568:568:568))
+        (PORT datad (569:569:569) (589:589:589))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (434:434:434))
+        (PORT datab (606:606:606) (622:622:622))
+        (PORT datac (1312:1312:1312) (1306:1306:1306))
+        (PORT datad (340:340:340) (355:355:355))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (318:318:318))
+        (PORT datab (249:249:249) (307:307:307))
+        (PORT datac (365:365:365) (404:404:404))
+        (PORT datad (553:553:553) (567:567:567))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (322:322:322))
+        (PORT datab (252:252:252) (311:311:311))
+        (PORT datac (367:367:367) (407:407:407))
+        (PORT datad (553:553:553) (570:570:570))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (319:319:319))
+        (PORT datab (256:256:256) (315:315:315))
+        (PORT datac (372:372:372) (411:411:411))
+        (PORT datad (549:549:549) (565:565:565))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (319:319:319))
+        (PORT datab (253:253:253) (312:312:312))
+        (PORT datac (372:372:372) (408:408:408))
+        (PORT datad (549:549:549) (565:565:565))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (319:319:319))
+        (PORT datab (253:253:253) (311:311:311))
+        (PORT datac (371:371:371) (407:407:407))
+        (PORT datad (550:550:550) (566:566:566))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (320:320:320))
+        (PORT datab (257:257:257) (316:316:316))
+        (PORT datac (373:373:373) (411:411:411))
+        (PORT datad (548:548:548) (564:564:564))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (323:323:323))
+        (PORT datab (255:255:255) (314:314:314))
+        (PORT datac (368:368:368) (411:411:411))
+        (PORT datad (551:551:551) (569:569:569))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (664:664:664))
+        (PORT datab (380:380:380) (418:418:418))
+        (PORT datac (560:560:560) (568:568:568))
+        (PORT datad (570:570:570) (590:590:590))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A14\|WideOr0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (385:385:385))
+        (PORT datab (588:588:588) (613:613:613))
+        (PORT datac (385:385:385) (419:419:419))
+        (PORT datad (217:217:217) (256:256:256))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (303:303:303))
+        (PORT datab (255:255:255) (306:306:306))
+        (PORT datac (385:385:385) (419:419:419))
+        (PORT datad (216:216:216) (256:256:256))
+        (IOPATH dataa combout (341:341:341) (319:319:319))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (389:389:389))
+        (PORT datab (381:381:381) (407:407:407))
+        (PORT datac (345:345:345) (367:367:367))
+        (PORT datad (328:328:328) (350:350:350))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1000:1000:1000) (1009:1009:1009))
+        (PORT datad (1105:1105:1105) (1100:1100:1100))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (288:288:288))
+        (PORT datab (228:228:228) (278:278:278))
+        (PORT datac (198:198:198) (243:243:243))
+        (PORT datad (199:199:199) (234:234:234))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (893:893:893) (946:946:946))
+        (PORT datab (1090:1090:1090) (1116:1116:1116))
+        (PORT datac (225:225:225) (281:281:281))
+        (PORT datad (1106:1106:1106) (1113:1113:1113))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (894:894:894) (942:942:942))
+        (PORT datab (1086:1086:1086) (1111:1111:1111))
+        (PORT datac (231:231:231) (285:285:285))
+        (PORT datad (1107:1107:1107) (1114:1114:1114))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (333:333:333) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (212:212:212) (260:260:260))
+        (PORT datad (195:195:195) (230:230:230))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (889:889:889) (940:940:940))
+        (PORT datab (1084:1084:1084) (1110:1110:1110))
+        (PORT datac (230:230:230) (286:286:286))
+        (PORT datad (1108:1108:1108) (1114:1114:1114))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1149:1149:1149) (1152:1152:1152))
+        (PORT datab (1087:1087:1087) (1110:1110:1110))
+        (PORT datac (1000:1000:1000) (1011:1011:1011))
+        (PORT datad (1108:1108:1108) (1113:1113:1113))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (304:304:304) (308:308:308))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (212:212:212) (256:256:256))
+        (PORT datac (858:858:858) (900:900:900))
+        (PORT datad (176:176:176) (202:202:202))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (897:897:897) (942:942:942))
+        (PORT datab (1091:1091:1091) (1113:1113:1113))
+        (PORT datac (225:225:225) (277:277:277))
+        (PORT datad (1104:1104:1104) (1107:1107:1107))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (894:894:894) (943:943:943))
+        (PORT datab (1087:1087:1087) (1115:1115:1115))
+        (PORT datac (228:228:228) (285:285:285))
+        (PORT datad (1109:1109:1109) (1116:1116:1116))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (311:311:311))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (890:890:890) (937:937:937))
+        (PORT datab (1083:1083:1083) (1108:1108:1108))
+        (PORT datac (231:231:231) (284:284:284))
+        (PORT datad (1109:1109:1109) (1112:1112:1112))
+        (IOPATH dataa combout (341:341:341) (319:319:319))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (210:210:210) (258:258:258))
+        (PORT datab (232:232:232) (274:274:274))
+        (PORT datac (175:175:175) (209:209:209))
+        (PORT datad (196:196:196) (231:231:231))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (893:893:893) (938:938:938))
+        (PORT datab (1081:1081:1081) (1109:1109:1109))
+        (PORT datac (232:232:232) (286:286:286))
+        (PORT datad (1111:1111:1111) (1113:1113:1113))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (213:213:213) (256:256:256))
+        (PORT datac (185:185:185) (224:224:224))
+        (PORT datad (319:319:319) (341:341:341))
+        (IOPATH datab combout (304:304:304) (311:311:311))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (268:268:268))
+        (PORT datab (234:234:234) (277:277:277))
+        (PORT datac (185:185:185) (224:224:224))
+        (PORT datad (199:199:199) (235:235:235))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (890:890:890) (938:938:938))
+        (PORT datab (1082:1082:1082) (1109:1109:1109))
+        (PORT datac (232:232:232) (285:285:285))
+        (PORT datad (1110:1110:1110) (1113:1113:1113))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (202:202:202) (242:242:242))
+        (PORT datac (366:366:366) (393:393:393))
+        (PORT datad (197:197:197) (232:232:232))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A23\|WideOr0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1027:1027:1027) (1048:1048:1048))
+        (PORT datab (1321:1321:1321) (1304:1304:1304))
+        (PORT datac (1072:1072:1072) (1089:1089:1089))
+        (PORT datad (1077:1077:1077) (1087:1087:1087))
+        (IOPATH dataa combout (301:301:301) (299:299:299))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A23\|WideOr0\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1316:1316:1316) (1367:1367:1367))
+        (PORT datab (1030:1030:1030) (1042:1042:1042))
+        (PORT datac (175:175:175) (209:209:209))
+        (PORT datad (1256:1256:1256) (1290:1290:1290))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE CLOCK_50\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (736:736:736) (991:991:991))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|clk_1MHz\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE CLOCK_50\~inputclkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (163:163:163) (145:145:145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (342:342:342))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (344:344:344))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (246:246:246) (317:317:317))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (201:201:201) (239:239:239))
+        (PORT datac (403:403:403) (467:467:467))
+        (PORT datad (195:195:195) (230:230:230))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (252:252:252) (338:338:338))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (200:200:200) (239:239:239))
+        (PORT datac (403:403:403) (467:467:467))
+        (PORT datad (194:194:194) (230:230:230))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (252:252:252) (337:337:337))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (199:199:199) (238:238:238))
+        (PORT datac (398:398:398) (464:464:464))
+        (PORT datad (200:200:200) (237:237:237))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (255:255:255) (347:347:347))
+        (PORT datab (254:254:254) (340:340:340))
+        (PORT datac (223:223:223) (302:302:302))
+        (PORT datad (225:225:225) (297:297:297))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (226:226:226) (274:274:274))
+        (PORT datad (246:246:246) (317:317:317))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|clk_1MHz)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2135:2135:2135) (2061:2061:2061))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (795:795:795) (793:793:793))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_DAC\|clk_1MHz\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (849:849:849) (897:897:897))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[0\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (261:261:261) (343:343:343))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (346:346:346))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (268:268:268) (320:320:320))
+        (PORT datab (676:676:676) (700:700:700))
+        (PORT datac (173:173:173) (207:207:207))
+        (PORT datad (920:920:920) (975:975:975))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (443:443:443) (508:508:508))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (710:710:710) (755:755:755))
+        (PORT datab (468:468:468) (511:511:511))
+        (PORT datac (310:310:310) (327:327:327))
+        (PORT datad (951:951:951) (1007:1007:1007))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (410:410:410) (487:487:487))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (333:333:333) (365:365:365))
+        (PORT datab (471:471:471) (511:511:511))
+        (PORT datac (677:677:677) (713:713:713))
+        (PORT datad (954:954:954) (1006:1006:1006))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (488:488:488))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (396:396:396))
+        (PORT datab (461:461:461) (503:503:503))
+        (PORT datac (668:668:668) (709:709:709))
+        (PORT datad (952:952:952) (1011:1011:1011))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (487:487:487))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (393:393:393))
+        (PORT datab (469:469:469) (512:512:512))
+        (PORT datac (675:675:675) (713:713:713))
+        (PORT datad (952:952:952) (1006:1006:1006))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (427:427:427) (497:497:497))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (370:370:370))
+        (PORT datab (463:463:463) (503:503:503))
+        (PORT datac (670:670:670) (709:709:709))
+        (PORT datad (952:952:952) (1011:1011:1011))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~36)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (440:440:440) (509:509:509))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (711:711:711) (756:756:756))
+        (PORT datab (470:470:470) (512:512:512))
+        (PORT datac (314:314:314) (333:333:333))
+        (PORT datad (953:953:953) (1005:1005:1005))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~38)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (344:344:344))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (950:950:950) (1019:1019:1019))
+        (PORT datab (199:199:199) (237:237:237))
+        (PORT datac (235:235:235) (277:277:277))
+        (PORT datad (639:639:639) (661:661:661))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~40)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (226:226:226) (299:299:299))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (951:951:951) (1019:1019:1019))
+        (PORT datab (198:198:198) (237:237:237))
+        (PORT datac (235:235:235) (278:278:278))
+        (PORT datad (638:638:638) (661:661:661))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (513:513:513))
+        (PORT datab (250:250:250) (334:334:334))
+        (PORT datac (223:223:223) (303:303:303))
+        (PORT datad (392:392:392) (456:456:456))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (729:729:729) (799:799:799))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (345:345:345))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (868:868:868) (918:918:918))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (709:709:709) (756:756:756))
+        (PORT datab (468:468:468) (510:510:510))
+        (PORT datac (617:617:617) (632:632:632))
+        (PORT datad (947:947:947) (1010:1010:1010))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (251:251:251) (336:336:336))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (276:276:276))
+        (PORT datab (688:688:688) (701:701:701))
+        (PORT datac (697:697:697) (764:764:764))
+        (PORT datad (175:175:175) (201:201:201))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (686:686:686) (754:754:754))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (708:708:708) (757:757:757))
+        (PORT datab (467:467:467) (509:509:509))
+        (PORT datac (594:594:594) (603:603:603))
+        (PORT datad (948:948:948) (1009:1009:1009))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (649:649:649) (721:721:721))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (707:707:707) (755:755:755))
+        (PORT datab (466:466:466) (507:507:507))
+        (PORT datac (603:603:603) (611:611:611))
+        (PORT datad (949:949:949) (1011:1011:1011))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (249:249:249) (334:334:334))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (339:339:339))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (248:248:248) (332:332:332))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (343:343:343))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (246:246:246))
+        (PORT datab (687:687:687) (700:700:700))
+        (PORT datac (697:697:697) (760:760:760))
+        (PORT datad (203:203:203) (232:232:232))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (354:354:354))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (949:949:949) (1018:1018:1018))
+        (PORT datab (201:201:201) (241:241:241))
+        (PORT datac (238:238:238) (282:282:282))
+        (PORT datad (639:639:639) (661:661:661))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (683:683:683) (751:751:751))
+        (PORT datab (726:726:726) (777:777:777))
+        (PORT datac (692:692:692) (743:743:743))
+        (PORT datad (224:224:224) (297:297:297))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (477:477:477))
+        (PORT datab (866:866:866) (915:915:915))
+        (PORT datac (659:659:659) (719:719:719))
+        (PORT datad (223:223:223) (295:295:295))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (646:646:646) (720:720:720))
+        (PORT datab (251:251:251) (336:336:336))
+        (PORT datac (223:223:223) (305:305:305))
+        (PORT datad (225:225:225) (298:298:298))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (352:352:352))
+        (PORT datab (264:264:264) (347:347:347))
+        (PORT datac (236:236:236) (313:313:313))
+        (PORT datad (238:238:238) (307:307:307))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (338:338:338) (375:375:375))
+        (PORT datab (199:199:199) (239:239:239))
+        (PORT datac (172:172:172) (206:206:206))
+        (PORT datad (601:601:601) (612:612:612))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|clkout\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (704:704:704) (748:748:748))
+        (PORT datab (454:454:454) (494:494:494))
+        (PORT datad (950:950:950) (1008:1008:1008))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|clkout)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PULSE\|state\.IDLE\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (224:224:224) (297:297:297))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PULSE\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PULSE\|pulse\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (219:219:219) (296:296:296))
+        (PORT datad (228:228:228) (301:301:301))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PULSE\|pulse)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (985:985:985) (1137:1137:1137))
+        (PORT datad (240:240:240) (317:317:317))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.WAIT_CSB_HIGH)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1485:1485:1485) (1501:1501:1501))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (984:984:984) (1136:1136:1136))
+        (PORT datab (712:712:712) (779:779:779))
+        (PORT datad (216:216:216) (285:285:285))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1485:1485:1485) (1501:1501:1501))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (983:983:983) (1139:1139:1139))
+        (PORT datab (707:707:707) (775:775:775))
+        (PORT datad (243:243:243) (322:322:322))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.WAIT_CSB_FALL)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1485:1485:1485) (1501:1501:1501))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|dac_start\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (983:983:983) (1131:1131:1131))
+        (PORT datab (264:264:264) (355:355:355))
+        (PORT datac (576:576:576) (622:622:622))
+        (PORT datad (302:302:302) (397:397:397))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (310:310:310))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|dac_start\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (709:709:709) (777:777:777))
+        (PORT datac (174:174:174) (208:208:208))
+        (PORT datad (243:243:243) (322:322:322))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_start)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1485:1485:1485) (1501:1501:1501))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (248:248:248) (333:333:333))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[3\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (343:343:343))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[4\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (269:269:269) (360:360:360))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (716:716:716) (808:808:808))
+        (PORT datab (217:217:217) (261:261:261))
+        (PORT datac (240:240:240) (327:327:327))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[1\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (250:250:250) (335:335:335))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[2\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (250:250:250) (335:335:335))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (345:345:345))
+        (PORT datab (252:252:252) (338:338:338))
+        (PORT datac (224:224:224) (305:305:305))
+        (PORT datad (226:226:226) (298:298:298))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (717:717:717) (812:812:812))
+        (PORT datab (218:218:218) (263:263:263))
+        (PORT datac (242:242:242) (329:329:329))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_cs)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|clk_1MHz\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|clk_1MHz)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2135:2135:2135) (2061:2061:2061))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (795:795:795) (793:793:793))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_ADC\|clk_1MHz\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (858:858:858) (929:929:929))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE ADC_SDO\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (649:649:649) (908:908:908))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (267:267:267) (354:354:354))
+        (PORT datac (876:876:876) (933:933:933))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.WAIT_CSB_HIGH)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (622:622:622) (680:680:680))
+        (PORT datab (904:904:904) (968:968:968))
+        (PORT datad (261:261:261) (332:332:332))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (742:742:742) (807:807:807))
+        (PORT datab (655:655:655) (726:726:726))
+        (PORT datad (855:855:855) (966:966:966))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.WAIT_CSB_FALL)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|adc_start\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (247:247:247) (335:335:335))
+        (PORT datab (878:878:878) (998:998:998))
+        (PORT datac (627:627:627) (695:695:695))
+        (PORT datad (240:240:240) (309:309:309))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (310:310:310))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|adc_start\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (203:203:203) (248:248:248))
+        (PORT datab (881:881:881) (1004:1004:1004))
+        (PORT datac (704:704:704) (767:767:767))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_start)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (275:275:275) (369:369:369))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (375:375:375))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (258:258:258) (340:340:340))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|state\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (239:239:239) (283:283:283))
+        (PORT datac (272:272:272) (374:374:374))
+        (PORT datad (177:177:177) (203:203:203))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (500:500:500) (581:581:581))
+        (PORT datad (253:253:253) (335:335:335))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (276:276:276) (374:374:374))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (246:246:246))
+        (PORT datab (239:239:239) (284:284:284))
+        (PORT datac (272:272:272) (374:374:374))
+        (PORT datad (176:176:176) (202:202:202))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (301:301:301) (409:409:409))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|state\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (279:279:279) (374:374:374))
+        (PORT datac (250:250:250) (340:340:340))
+        (PORT datad (247:247:247) (327:327:327))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector4\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (501:501:501) (578:578:578))
+        (PORT datab (238:238:238) (283:283:283))
+        (PORT datac (273:273:273) (375:375:375))
+        (PORT datad (251:251:251) (333:333:333))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_cs)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (973:973:973) (1063:1063:1063))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (414:414:414))
+        (PORT datab (278:278:278) (372:372:372))
+        (PORT datac (248:248:248) (339:339:339))
+        (PORT datad (247:247:247) (328:328:328))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (442:442:442) (476:476:476))
+        (PORT datab (201:201:201) (241:241:241))
+        (PORT datac (271:271:271) (373:373:373))
+        (PORT datad (254:254:254) (336:336:336))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_ena)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (628:628:628) (695:695:695))
+        (PORT datad (628:628:628) (698:698:698))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (3961:3961:3961) (4319:4319:4319))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (225:225:225) (296:296:296))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (567:567:567) (645:645:645))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (225:225:225) (296:296:296))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (567:567:567) (643:643:643))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (239:239:239) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (226:226:226) (297:297:297))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (582:582:582) (656:656:656))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (300:300:300) (410:410:410))
+        (PORT datab (279:279:279) (374:374:374))
+        (PORT datac (248:248:248) (340:340:340))
+        (PORT datad (248:248:248) (329:329:329))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Decoder0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (200:200:200) (240:240:240))
+        (PORT datad (251:251:251) (333:333:333))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_done)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT asdata (755:755:755) (817:817:817))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|PULSE2\|state\.IDLE\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1581:1581:1581) (1626:1626:1626))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|PULSE2\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|PULSE2\|pulse\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1607:1607:1607) (1663:1663:1663))
+        (PORT datad (217:217:217) (286:286:286))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|PULSE2\|pulse)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|rden_b_store)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT asdata (1210:1210:1210) (1273:1273:1273))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (894:894:894) (964:964:964))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (581:581:581) (656:656:656))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT asdata (754:754:754) (816:816:816))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (239:239:239) (309:309:309))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT asdata (706:706:706) (769:769:769))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_ADC\|adc_cs\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (1108:1108:1108) (1172:1172:1172))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[0\]\~36)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[1\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (264:264:264) (351:351:351))
+        (PORT datab (262:262:262) (344:344:344))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[2\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (345:345:345))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[3\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (353:353:353))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[4\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (353:353:353))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[4\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3107:3107:3107) (3383:3383:3383))
+        (PORT datab (1375:1375:1375) (1472:1472:1472))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[5\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[5\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1423:1423:1423) (1534:1534:1534))
+        (PORT datab (3192:3192:3192) (3495:3495:3495))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[6\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[6\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1468:1468:1468) (1548:1548:1548))
+        (PORT datab (3124:3124:3124) (3396:3396:3396))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[7\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[7\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1428:1428:1428) (1550:1550:1550))
+        (PORT datab (3099:3099:3099) (3370:3370:3370))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[8\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[8\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3183:3183:3183) (3497:3497:3497))
+        (PORT datab (1428:1428:1428) (1494:1494:1494))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[9\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (352:352:352))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[9\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1364:1364:1364) (1442:1442:1442))
+        (PORT datab (3373:3373:3373) (3642:3642:3642))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[10\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (283:283:283) (366:366:366))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[10\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1205:1205:1205) (1291:1291:1291))
+        (PORT datab (3405:3405:3405) (3686:3686:3686))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[11\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (351:351:351))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[11\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3115:3115:3115) (3398:3398:3398))
+        (PORT datab (1452:1452:1452) (1542:1542:1542))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[12\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (238:238:238) (306:306:306))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[12\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3101:3101:3101) (3380:3380:3380))
+        (PORT datad (1368:1368:1368) (1458:1458:1458))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (676:676:676) (689:689:689))
+        (PORT clk (1808:1808:1808) (1838:1838:1838))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1048:1048:1048) (1107:1107:1107))
+        (PORT d[1] (1016:1016:1016) (1089:1089:1089))
+        (PORT d[2] (1037:1037:1037) (1105:1105:1105))
+        (PORT d[3] (1572:1572:1572) (1657:1657:1657))
+        (PORT d[4] (1433:1433:1433) (1467:1467:1467))
+        (PORT d[5] (1422:1422:1422) (1450:1450:1450))
+        (PORT d[6] (1970:1970:1970) (1970:1970:1970))
+        (PORT d[7] (1446:1446:1446) (1480:1480:1480))
+        (PORT d[8] (1646:1646:1646) (1671:1671:1671))
+        (PORT d[9] (1417:1417:1417) (1420:1420:1420))
+        (PORT d[10] (1579:1579:1579) (1667:1667:1667))
+        (PORT d[11] (1649:1649:1649) (1676:1676:1676))
+        (PORT d[12] (1454:1454:1454) (1488:1488:1488))
+        (PORT clk (1805:1805:1805) (1834:1834:1834))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1241:1241:1241) (1230:1230:1230))
+        (PORT clk (1805:1805:1805) (1834:1834:1834))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1808:1808:1808) (1838:1838:1838))
+        (PORT d[0] (1766:1766:1766) (1767:1767:1767))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1809:1809:1809) (1839:1839:1839))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1809:1809:1809) (1839:1839:1839))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1809:1809:1809) (1839:1839:1839))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1809:1809:1809) (1839:1839:1839))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1005:1005:1005) (1058:1058:1058))
+        (PORT d[1] (1017:1017:1017) (1090:1090:1090))
+        (PORT d[2] (1060:1060:1060) (1124:1124:1124))
+        (PORT d[3] (1573:1573:1573) (1657:1657:1657))
+        (PORT d[4] (982:982:982) (1031:1031:1031))
+        (PORT d[5] (1284:1284:1284) (1388:1388:1388))
+        (PORT d[6] (998:998:998) (1062:1062:1062))
+        (PORT d[7] (1320:1320:1320) (1409:1409:1409))
+        (PORT d[8] (1050:1050:1050) (1112:1112:1112))
+        (PORT d[9] (1036:1036:1036) (1102:1102:1102))
+        (PORT d[10] (1411:1411:1411) (1474:1474:1474))
+        (PORT d[11] (1294:1294:1294) (1360:1360:1360))
+        (PORT d[12] (1005:1005:1005) (1063:1063:1063))
+        (PORT clk (1769:1769:1769) (1765:1765:1765))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1242:1242:1242) (1231:1231:1231))
+        (PORT clk (1769:1769:1769) (1765:1765:1765))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1769:1769:1769) (1765:1765:1765))
+        (PORT d[0] (2132:2132:2132) (2060:2060:2060))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1770:1770:1770) (1766:1766:1766))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1770:1770:1770) (1766:1766:1766))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1770:1770:1770) (1766:1766:1766))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1765:1765:1765) (1765:1765:1765))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT asdata (753:753:753) (813:813:813))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (225:225:225) (296:296:296))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (875:875:875) (900:900:900))
+        (PORT datab (243:243:243) (325:325:325))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1335:1335:1335) (1375:1375:1375))
+        (PORT clk (1802:1802:1802) (1832:1832:1832))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1966:1966:1966) (2061:2061:2061))
+        (PORT d[1] (2091:2091:2091) (2197:2197:2197))
+        (PORT d[2] (1184:1184:1184) (1276:1276:1276))
+        (PORT d[3] (2407:2407:2407) (2505:2505:2505))
+        (PORT d[4] (980:980:980) (1034:1034:1034))
+        (PORT d[5] (734:734:734) (784:784:784))
+        (PORT d[6] (1121:1121:1121) (1116:1116:1116))
+        (PORT d[7] (695:695:695) (736:736:736))
+        (PORT d[8] (1472:1472:1472) (1534:1534:1534))
+        (PORT d[9] (716:716:716) (752:752:752))
+        (PORT d[10] (1670:1670:1670) (1726:1726:1726))
+        (PORT d[11] (969:969:969) (1022:1022:1022))
+        (PORT d[12] (726:726:726) (777:777:777))
+        (PORT clk (1799:1799:1799) (1828:1828:1828))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1273:1273:1273) (1250:1250:1250))
+        (PORT clk (1799:1799:1799) (1828:1828:1828))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1802:1802:1802) (1832:1832:1832))
+        (PORT d[0] (1798:1798:1798) (1787:1787:1787))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1945:1945:1945) (2036:2036:2036))
+        (PORT d[1] (2092:2092:2092) (2191:2191:2191))
+        (PORT d[2] (1207:1207:1207) (1301:1301:1301))
+        (PORT d[3] (2408:2408:2408) (2505:2505:2505))
+        (PORT d[4] (1209:1209:1209) (1282:1282:1282))
+        (PORT d[5] (1778:1778:1778) (1894:1894:1894))
+        (PORT d[6] (2043:2043:2043) (2144:2144:2144))
+        (PORT d[7] (2249:2249:2249) (2337:2337:2337))
+        (PORT d[8] (1994:1994:1994) (2049:2049:2049))
+        (PORT d[9] (1211:1211:1211) (1275:1275:1275))
+        (PORT d[10] (1751:1751:1751) (1845:1845:1845))
+        (PORT d[11] (1734:1734:1734) (1820:1820:1820))
+        (PORT d[12] (1738:1738:1738) (1842:1842:1842))
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1274:1274:1274) (1251:1251:1251))
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+        (PORT d[0] (1471:1471:1471) (1437:1437:1437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1759:1759:1759) (1759:1759:1759))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (389:389:389) (453:453:453))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (597:597:597) (667:667:667))
+        (PORT datab (1119:1119:1119) (1124:1124:1124))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (934:934:934) (938:938:938))
+        (PORT clk (1812:1812:1812) (1841:1841:1841))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1007:1007:1007) (1060:1060:1060))
+        (PORT d[1] (1036:1036:1036) (1120:1120:1120))
+        (PORT d[2] (1009:1009:1009) (1061:1061:1061))
+        (PORT d[3] (1048:1048:1048) (1107:1107:1107))
+        (PORT d[4] (1423:1423:1423) (1440:1440:1440))
+        (PORT d[5] (1413:1413:1413) (1428:1428:1428))
+        (PORT d[6] (2545:2545:2545) (2565:2565:2565))
+        (PORT d[7] (1437:1437:1437) (1452:1452:1452))
+        (PORT d[8] (1615:1615:1615) (1620:1620:1620))
+        (PORT d[9] (1406:1406:1406) (1417:1417:1417))
+        (PORT d[10] (1786:1786:1786) (1898:1898:1898))
+        (PORT d[11] (1671:1671:1671) (1678:1678:1678))
+        (PORT d[12] (1947:1947:1947) (1965:1965:1965))
+        (PORT clk (1809:1809:1809) (1837:1837:1837))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1480:1480:1480) (1445:1445:1445))
+        (PORT clk (1809:1809:1809) (1837:1837:1837))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1812:1812:1812) (1841:1841:1841))
+        (PORT d[0] (2005:2005:2005) (1982:1982:1982))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1017:1017:1017) (1052:1052:1052))
+        (PORT d[1] (1037:1037:1037) (1120:1120:1120))
+        (PORT d[2] (1032:1032:1032) (1085:1085:1085))
+        (PORT d[3] (1049:1049:1049) (1107:1107:1107))
+        (PORT d[4] (1035:1035:1035) (1083:1083:1083))
+        (PORT d[5] (1303:1303:1303) (1406:1406:1406))
+        (PORT d[6] (1257:1257:1257) (1314:1314:1314))
+        (PORT d[7] (1028:1028:1028) (1121:1121:1121))
+        (PORT d[8] (1059:1059:1059) (1140:1140:1140))
+        (PORT d[9] (1300:1300:1300) (1398:1398:1398))
+        (PORT d[10] (1064:1064:1064) (1144:1144:1144))
+        (PORT d[11] (1014:1014:1014) (1082:1082:1082))
+        (PORT d[12] (1040:1040:1040) (1101:1101:1101))
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1481:1481:1481) (1446:1446:1446))
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+        (PORT d[0] (2170:2170:2170) (2105:2105:2105))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1769:1769:1769) (1768:1768:1768))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (463:463:463) (536:536:536))
+        (PORT datab (929:929:929) (946:946:946))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (937:937:937) (960:960:960))
+        (PORT clk (1798:1798:1798) (1829:1829:1829))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1195:1195:1195) (1251:1251:1251))
+        (PORT d[1] (2056:2056:2056) (2168:2168:2168))
+        (PORT d[2] (1529:1529:1529) (1613:1613:1613))
+        (PORT d[3] (2057:2057:2057) (2146:2146:2146))
+        (PORT d[4] (984:984:984) (1013:1013:1013))
+        (PORT d[5] (1332:1332:1332) (1395:1395:1395))
+        (PORT d[6] (1154:1154:1154) (1178:1178:1178))
+        (PORT d[7] (717:717:717) (745:745:745))
+        (PORT d[8] (1667:1667:1667) (1717:1717:1717))
+        (PORT d[9] (721:721:721) (746:746:746))
+        (PORT d[10] (1449:1449:1449) (1511:1511:1511))
+        (PORT d[11] (740:740:740) (763:763:763))
+        (PORT d[12] (700:700:700) (727:727:727))
+        (PORT clk (1795:1795:1795) (1825:1825:1825))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1698:1698:1698) (1698:1698:1698))
+        (PORT clk (1795:1795:1795) (1825:1825:1825))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1798:1798:1798) (1829:1829:1829))
+        (PORT d[0] (2223:2223:2223) (2235:2235:2235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1799:1799:1799) (1830:1830:1830))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1799:1799:1799) (1830:1830:1830))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1799:1799:1799) (1830:1830:1830))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1799:1799:1799) (1830:1830:1830))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1188:1188:1188) (1259:1259:1259))
+        (PORT d[1] (2079:2079:2079) (2192:2192:2192))
+        (PORT d[2] (1508:1508:1508) (1590:1590:1590))
+        (PORT d[3] (2058:2058:2058) (2146:2146:2146))
+        (PORT d[4] (1452:1452:1452) (1524:1524:1524))
+        (PORT d[5] (1746:1746:1746) (1880:1880:1880))
+        (PORT d[6] (2018:2018:2018) (2114:2114:2114))
+        (PORT d[7] (1983:1983:1983) (2077:2077:2077))
+        (PORT d[8] (1685:1685:1685) (1744:1744:1744))
+        (PORT d[9] (1388:1388:1388) (1451:1451:1451))
+        (PORT d[10] (2046:2046:2046) (2172:2172:2172))
+        (PORT d[11] (1993:1993:1993) (2071:2071:2071))
+        (PORT d[12] (1713:1713:1713) (1797:1797:1797))
+        (PORT clk (1759:1759:1759) (1756:1756:1756))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1699:1699:1699) (1699:1699:1699))
+        (PORT clk (1759:1759:1759) (1756:1756:1756))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1759:1759:1759) (1756:1756:1756))
+        (PORT d[0] (1741:1741:1741) (1708:1708:1708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1760:1760:1760) (1757:1757:1757))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1760:1760:1760) (1757:1757:1757))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1760:1760:1760) (1757:1757:1757))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1755:1755:1755) (1756:1756:1756))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT asdata (569:569:569) (646:646:646))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (225:225:225) (297:297:297))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (833:833:833) (852:852:852))
+        (PORT datab (608:608:608) (667:667:667))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1345:1345:1345) (1383:1383:1383))
+        (PORT clk (1802:1802:1802) (1832:1832:1832))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1504:1504:1504) (1561:1561:1561))
+        (PORT d[1] (2097:2097:2097) (2206:2206:2206))
+        (PORT d[2] (1532:1532:1532) (1622:1622:1622))
+        (PORT d[3] (2008:2008:2008) (2096:2096:2096))
+        (PORT d[4] (975:975:975) (1010:1010:1010))
+        (PORT d[5] (697:697:697) (726:726:726))
+        (PORT d[6] (1120:1120:1120) (1120:1120:1120))
+        (PORT d[7] (685:685:685) (707:707:707))
+        (PORT d[8] (1396:1396:1396) (1453:1453:1453))
+        (PORT d[9] (681:681:681) (708:708:708))
+        (PORT d[10] (1441:1441:1441) (1506:1506:1506))
+        (PORT d[11] (729:729:729) (760:760:760))
+        (PORT d[12] (963:963:963) (979:979:979))
+        (PORT clk (1799:1799:1799) (1828:1828:1828))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1719:1719:1719) (1713:1713:1713))
+        (PORT clk (1799:1799:1799) (1828:1828:1828))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1802:1802:1802) (1832:1832:1832))
+        (PORT d[0] (2244:2244:2244) (2250:2250:2250))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1498:1498:1498) (1564:1564:1564))
+        (PORT d[1] (2076:2076:2076) (2182:2182:2182))
+        (PORT d[2] (1511:1511:1511) (1598:1598:1598))
+        (PORT d[3] (2009:2009:2009) (2096:2096:2096))
+        (PORT d[4] (1439:1439:1439) (1507:1507:1507))
+        (PORT d[5] (1737:1737:1737) (1853:1853:1853))
+        (PORT d[6] (2031:2031:2031) (2091:2091:2091))
+        (PORT d[7] (1772:1772:1772) (1879:1879:1879))
+        (PORT d[8] (2240:2240:2240) (2337:2337:2337))
+        (PORT d[9] (1356:1356:1356) (1419:1419:1419))
+        (PORT d[10] (1733:1733:1733) (1830:1830:1830))
+        (PORT d[11] (1715:1715:1715) (1780:1780:1780))
+        (PORT d[12] (1443:1443:1443) (1509:1509:1509))
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1720:1720:1720) (1714:1714:1714))
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+        (PORT d[0] (1715:1715:1715) (1678:1678:1678))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1759:1759:1759) (1759:1759:1759))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT asdata (568:568:568) (645:645:645))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (427:427:427) (493:493:493))
+        (PORT datab (1320:1320:1320) (1348:1348:1348))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (909:909:909) (929:929:929))
+        (PORT clk (1812:1812:1812) (1841:1841:1841))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1319:1319:1319) (1388:1388:1388))
+        (PORT d[1] (752:752:752) (821:821:821))
+        (PORT d[2] (1320:1320:1320) (1388:1388:1388))
+        (PORT d[3] (1561:1561:1561) (1622:1622:1622))
+        (PORT d[4] (1445:1445:1445) (1465:1465:1465))
+        (PORT d[5] (1448:1448:1448) (1483:1483:1483))
+        (PORT d[6] (1972:1972:1972) (1964:1964:1964))
+        (PORT d[7] (1430:1430:1430) (1439:1439:1439))
+        (PORT d[8] (1663:1663:1663) (1670:1670:1670))
+        (PORT d[9] (1392:1392:1392) (1418:1418:1418))
+        (PORT d[10] (1581:1581:1581) (1672:1672:1672))
+        (PORT d[11] (1711:1711:1711) (1717:1717:1717))
+        (PORT d[12] (1439:1439:1439) (1448:1448:1448))
+        (PORT clk (1809:1809:1809) (1837:1837:1837))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1795:1795:1795) (1759:1759:1759))
+        (PORT clk (1809:1809:1809) (1837:1837:1837))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1812:1812:1812) (1841:1841:1841))
+        (PORT d[0] (2320:2320:2320) (2296:2296:2296))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1320:1320:1320) (1388:1388:1388))
+        (PORT d[1] (775:775:775) (845:845:845))
+        (PORT d[2] (1286:1286:1286) (1338:1338:1338))
+        (PORT d[3] (1562:1562:1562) (1622:1622:1622))
+        (PORT d[4] (755:755:755) (812:812:812))
+        (PORT d[5] (756:756:756) (820:820:820))
+        (PORT d[6] (733:733:733) (790:790:790))
+        (PORT d[7] (728:728:728) (782:782:782))
+        (PORT d[8] (745:745:745) (806:806:806))
+        (PORT d[9] (971:971:971) (1044:1044:1044))
+        (PORT d[10] (748:748:748) (812:812:812))
+        (PORT d[11] (1302:1302:1302) (1369:1369:1369))
+        (PORT d[12] (959:959:959) (1024:1024:1024))
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1796:1796:1796) (1760:1760:1760))
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+        (PORT d[0] (1893:1893:1893) (1841:1841:1841))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1769:1769:1769) (1768:1768:1768))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (387:387:387) (464:464:464))
+        (PORT datab (1162:1162:1162) (1173:1173:1173))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1393:1393:1393) (1409:1409:1409))
+        (PORT clk (1804:1804:1804) (1835:1835:1835))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1503:1503:1503) (1589:1589:1589))
+        (PORT d[1] (1532:1532:1532) (1630:1630:1630))
+        (PORT d[2] (1517:1517:1517) (1582:1582:1582))
+        (PORT d[3] (1489:1489:1489) (1574:1574:1574))
+        (PORT d[4] (700:700:700) (731:731:731))
+        (PORT d[5] (418:418:418) (445:445:445))
+        (PORT d[6] (409:409:409) (431:431:431))
+        (PORT d[7] (415:415:415) (441:441:441))
+        (PORT d[8] (409:409:409) (431:431:431))
+        (PORT d[9] (420:420:420) (448:448:448))
+        (PORT d[10] (408:408:408) (427:427:427))
+        (PORT d[11] (403:403:403) (430:430:430))
+        (PORT d[12] (420:420:420) (446:446:446))
+        (PORT clk (1801:1801:1801) (1831:1831:1831))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1687:1687:1687) (1701:1701:1701))
+        (PORT clk (1801:1801:1801) (1831:1831:1831))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1804:1804:1804) (1835:1835:1835))
+        (PORT d[0] (2212:2212:2212) (2238:2238:2238))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1805:1805:1805) (1836:1836:1836))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1805:1805:1805) (1836:1836:1836))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1805:1805:1805) (1836:1836:1836))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1805:1805:1805) (1836:1836:1836))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1526:1526:1526) (1608:1608:1608))
+        (PORT d[1] (1533:1533:1533) (1630:1630:1630))
+        (PORT d[2] (1531:1531:1531) (1608:1608:1608))
+        (PORT d[3] (1490:1490:1490) (1574:1574:1574))
+        (PORT d[4] (1466:1466:1466) (1559:1559:1559))
+        (PORT d[5] (1472:1472:1472) (1587:1587:1587))
+        (PORT d[6] (1507:1507:1507) (1587:1587:1587))
+        (PORT d[7] (1512:1512:1512) (1629:1629:1629))
+        (PORT d[8] (1533:1533:1533) (1604:1604:1604))
+        (PORT d[9] (1410:1410:1410) (1485:1485:1485))
+        (PORT d[10] (1474:1474:1474) (1570:1570:1570))
+        (PORT d[11] (1496:1496:1496) (1580:1580:1580))
+        (PORT d[12] (1470:1470:1470) (1560:1560:1560))
+        (PORT clk (1765:1765:1765) (1762:1762:1762))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1688:1688:1688) (1702:1702:1702))
+        (PORT clk (1765:1765:1765) (1762:1762:1762))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1765:1765:1765) (1762:1762:1762))
+        (PORT d[0] (1723:1723:1723) (1708:1708:1708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1766:1766:1766) (1763:1763:1763))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1766:1766:1766) (1763:1763:1763))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1766:1766:1766) (1763:1763:1763))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1761:1761:1761) (1762:1762:1762))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (227:227:227) (299:299:299))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1271:1271:1271) (1305:1305:1305))
+        (PORT datab (421:421:421) (485:485:485))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (386:386:386) (464:464:464))
+        (PORT datab (1216:1216:1216) (1221:1221:1221))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (425:425:425) (507:507:507))
+        (PORT datab (944:944:944) (960:960:960))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (501:501:501))
+        (PORT datad (907:907:907) (919:919:919))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (198:198:198) (236:236:236))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (198:198:198) (236:236:236))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (200:200:200) (243:243:243))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (970:970:970) (997:997:997))
+        (PORT clk (1814:1814:1814) (1844:1844:1844))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1066:1066:1066) (1141:1141:1141))
+        (PORT d[1] (1058:1058:1058) (1146:1146:1146))
+        (PORT d[2] (1070:1070:1070) (1157:1157:1157))
+        (PORT d[3] (1541:1541:1541) (1608:1608:1608))
+        (PORT d[4] (1149:1149:1149) (1157:1157:1157))
+        (PORT d[5] (1149:1149:1149) (1167:1167:1167))
+        (PORT d[6] (2548:2548:2548) (2536:2536:2536))
+        (PORT d[7] (1153:1153:1153) (1160:1160:1160))
+        (PORT d[8] (1158:1158:1158) (1169:1169:1169))
+        (PORT d[9] (1125:1125:1125) (1131:1131:1131))
+        (PORT d[10] (1213:1213:1213) (1289:1289:1289))
+        (PORT d[11] (1994:1994:1994) (1995:1995:1995))
+        (PORT d[12] (1105:1105:1105) (1127:1127:1127))
+        (PORT clk (1811:1811:1811) (1840:1840:1840))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1511:1511:1511) (1478:1478:1478))
+        (PORT clk (1811:1811:1811) (1840:1840:1840))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1814:1814:1814) (1844:1844:1844))
+        (PORT d[0] (2036:2036:2036) (2015:2015:2015))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1059:1059:1059) (1144:1144:1144))
+        (PORT d[1] (1059:1059:1059) (1146:1146:1146))
+        (PORT d[2] (1026:1026:1026) (1113:1113:1113))
+        (PORT d[3] (1542:1542:1542) (1608:1608:1608))
+        (PORT d[4] (1037:1037:1037) (1106:1106:1106))
+        (PORT d[5] (1026:1026:1026) (1123:1123:1123))
+        (PORT d[6] (1023:1023:1023) (1115:1115:1115))
+        (PORT d[7] (1003:1003:1003) (1079:1079:1079))
+        (PORT d[8] (1069:1069:1069) (1128:1128:1128))
+        (PORT d[9] (1257:1257:1257) (1348:1348:1348))
+        (PORT d[10] (1098:1098:1098) (1162:1162:1162))
+        (PORT d[11] (1234:1234:1234) (1319:1319:1319))
+        (PORT d[12] (1015:1015:1015) (1091:1091:1091))
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1512:1512:1512) (1479:1479:1479))
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+        (PORT d[0] (2144:2144:2144) (2105:2105:2105))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1771:1771:1771) (1771:1771:1771))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (959:959:959) (970:970:970))
+        (PORT clk (1814:1814:1814) (1844:1844:1844))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1309:1309:1309) (1353:1353:1353))
+        (PORT d[1] (1013:1013:1013) (1074:1074:1074))
+        (PORT d[2] (1303:1303:1303) (1370:1370:1370))
+        (PORT d[3] (1540:1540:1540) (1604:1604:1604))
+        (PORT d[4] (1719:1719:1719) (1719:1719:1719))
+        (PORT d[5] (1476:1476:1476) (1516:1516:1516))
+        (PORT d[6] (2799:2799:2799) (2826:2826:2826))
+        (PORT d[7] (1458:1458:1458) (1471:1471:1471))
+        (PORT d[8] (1664:1664:1664) (1671:1671:1671))
+        (PORT d[9] (1393:1393:1393) (1419:1419:1419))
+        (PORT d[10] (1513:1513:1513) (1613:1613:1613))
+        (PORT d[11] (1631:1631:1631) (1640:1640:1640))
+        (PORT d[12] (1439:1439:1439) (1449:1449:1449))
+        (PORT clk (1811:1811:1811) (1840:1840:1840))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1495:1495:1495) (1478:1478:1478))
+        (PORT clk (1811:1811:1811) (1840:1840:1840))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1814:1814:1814) (1844:1844:1844))
+        (PORT d[0] (2062:2062:2062) (2040:2040:2040))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1332:1332:1332) (1377:1377:1377))
+        (PORT d[1] (1000:1000:1000) (1042:1042:1042))
+        (PORT d[2] (1304:1304:1304) (1370:1370:1370))
+        (PORT d[3] (1541:1541:1541) (1604:1604:1604))
+        (PORT d[4] (1023:1023:1023) (1076:1076:1076))
+        (PORT d[5] (994:994:994) (1049:1049:1049))
+        (PORT d[6] (1311:1311:1311) (1383:1383:1383))
+        (PORT d[7] (1334:1334:1334) (1427:1427:1427))
+        (PORT d[8] (997:997:997) (1051:1051:1051))
+        (PORT d[9] (1242:1242:1242) (1310:1310:1310))
+        (PORT d[10] (1013:1013:1013) (1072:1072:1072))
+        (PORT d[11] (1331:1331:1331) (1420:1420:1420))
+        (PORT d[12] (1017:1017:1017) (1071:1071:1071))
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1538:1538:1538) (1504:1504:1504))
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+        (PORT d[0] (2394:2394:2394) (2348:2348:2348))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1771:1771:1771) (1771:1771:1771))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (964:964:964) (1067:1067:1067))
+        (PORT datac (1369:1369:1369) (1451:1451:1451))
+        (PORT datad (719:719:719) (779:779:779))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (964:964:964) (1067:1067:1067))
+        (PORT datab (243:243:243) (326:326:326))
+        (PORT datac (1150:1150:1150) (1198:1198:1198))
+        (PORT datad (719:719:719) (779:779:779))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1094:1094:1094) (1182:1182:1182))
+        (PORT datab (763:763:763) (827:827:827))
+        (PORT datac (218:218:218) (295:295:295))
+        (PORT datad (915:915:915) (1013:1013:1013))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (958:958:958) (1060:1060:1060))
+        (PORT datab (244:244:244) (326:326:326))
+        (PORT datac (1027:1027:1027) (1091:1091:1091))
+        (PORT datad (726:726:726) (787:787:787))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (957:957:957) (1059:1059:1059))
+        (PORT datab (244:244:244) (326:326:326))
+        (PORT datac (860:860:860) (904:904:904))
+        (PORT datad (727:727:727) (787:787:787))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (985:985:985) (1138:1138:1138))
+        (PORT datab (426:426:426) (507:507:507))
+        (PORT datac (1052:1052:1052) (1143:1143:1143))
+        (PORT datad (302:302:302) (396:396:396))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (982:982:982) (1136:1136:1136))
+        (PORT datab (246:246:246) (328:328:328))
+        (PORT datac (692:692:692) (750:750:750))
+        (PORT datad (306:306:306) (397:397:397))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (979:979:979) (1141:1141:1141))
+        (PORT datab (687:687:687) (755:755:755))
+        (PORT datac (218:218:218) (295:295:295))
+        (PORT datad (304:304:304) (399:399:399))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (977:977:977) (1142:1142:1142))
+        (PORT datab (245:245:245) (329:329:329))
+        (PORT datac (875:875:875) (961:961:961))
+        (PORT datad (305:305:305) (398:398:398))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|data_out\[9\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (193:193:193) (226:226:226))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (248:248:248) (336:336:336))
+        (PORT datab (328:328:328) (434:434:434))
+        (PORT datac (1271:1271:1271) (1339:1339:1339))
+        (PORT datad (957:957:957) (1084:1084:1084))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (982:982:982) (1138:1138:1138))
+        (PORT datac (217:217:217) (294:294:294))
+        (PORT datad (304:304:304) (394:394:394))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (991:991:991) (1136:1136:1136))
+        (PORT datac (217:217:217) (293:293:293))
+        (PORT datad (299:299:299) (392:392:392))
+        (IOPATH dataa combout (304:304:304) (307:307:307))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (975:975:975) (1139:1139:1139))
+        (PORT datac (219:219:219) (296:296:296))
+        (PORT datad (306:306:306) (399:399:399))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (984:984:984) (1141:1141:1141))
+        (PORT datab (335:335:335) (441:441:441))
+        (PORT datad (219:219:219) (288:288:288))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (310:310:310))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCK\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (410:410:410) (490:490:490))
+        (PORT datab (263:263:263) (345:345:345))
+        (PORT datac (623:623:623) (690:690:690))
+        (PORT datad (1279:1279:1279) (1430:1430:1430))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (336:336:336) (332:332:332))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (219:219:219) (265:265:265))
+        (PORT datac (243:243:243) (331:331:331))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_ld)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[9\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (736:736:736) (991:991:991))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (500:500:500) (577:577:577))
+        (PORT datab (3070:3070:3070) (3350:3350:3350))
+        (PORT datac (274:274:274) (374:374:374))
+        (PORT datad (246:246:246) (325:325:325))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (378:378:378))
+        (PORT datab (279:279:279) (371:371:371))
+        (PORT datac (175:175:175) (209:209:209))
+        (PORT datad (258:258:258) (340:340:340))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_din)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[1\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (508:508:508))
+        (PORT datab (262:262:262) (344:344:344))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[2\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (351:351:351))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[3\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (345:345:345))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[4\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (353:353:353))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[5\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (353:353:353))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[6\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[7\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[8\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[9\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (239:239:239) (309:309:309))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1209:1209:1209) (1257:1257:1257))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1823:1823:1823) (1907:1907:1907))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (997:997:997) (1053:1053:1053))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1188:1188:1188) (1234:1234:1234))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1822:1822:1822) (1912:1912:1912))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1205:1205:1205) (1246:1246:1246))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1369:1369:1369) (1432:1432:1432))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1397:1397:1397) (1484:1484:1484))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1496:1496:1496) (1540:1540:1540))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1711:1711:1711) (1788:1788:1788))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (329:329:329))
+        (PORT datab (911:911:911) (968:968:968))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (447:447:447) (513:513:513))
+        (PORT datab (242:242:242) (323:323:323))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (331:331:331))
+        (PORT datab (632:632:632) (701:701:701))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (331:331:331))
+        (PORT datab (440:440:440) (505:505:505))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (426:426:426) (506:506:506))
+        (PORT datab (405:405:405) (480:480:480))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (680:680:680) (741:741:741))
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (679:679:679) (742:742:742))
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (649:649:649) (716:716:716))
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (330:330:330))
+        (PORT datab (439:439:439) (505:505:505))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (486:486:486))
+        (PORT datab (242:242:242) (324:324:324))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|pwm_out\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (858:858:858) (864:864:864))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|pwm_out)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1478:1478:1478) (1494:1494:1494))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+)
diff --git a/part_4/ex16/simulation/modelsim/top_min_1200mv_0c_fast.vo b/part_4/ex16/simulation/modelsim/top_min_1200mv_0c_fast.vo
new file mode 100755
index 0000000..77234b3
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_min_1200mv_0c_fast.vo
@@ -0,0 +1,9959 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 32-bit"
+// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+// DATE "02/18/2014 18:26:56"
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module top (
+	CLOCK_50,
+	SW,
+	HEX0_D,
+	HEX1_D,
+	HEX2_D,
+	HEX3_D,
+	DAC_SDI,
+	SCK,
+	DAC_CS,
+	DAC_LD,
+	ADC_SDI,
+	ADC_CS,
+	ADC_SDO,
+	LEDG,
+	PWM_OUT);
+input 	CLOCK_50;
+input 	[9:0] SW;
+output 	[6:0] HEX0_D;
+output 	[6:0] HEX1_D;
+output 	[6:0] HEX2_D;
+output 	[6:0] HEX3_D;
+output 	DAC_SDI;
+output 	SCK;
+output 	DAC_CS;
+output 	DAC_LD;
+output 	ADC_SDI;
+output 	ADC_CS;
+input 	ADC_SDO;
+output 	[9:0] LEDG;
+output 	PWM_OUT;
+
+// Design Ports Information
+// HEX0_D[0]	=>  Location: PIN_E11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[1]	=>  Location: PIN_F11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[2]	=>  Location: PIN_H12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[3]	=>  Location: PIN_H13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[4]	=>  Location: PIN_G12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[5]	=>  Location: PIN_F12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX0_D[6]	=>  Location: PIN_F13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[0]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[1]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[2]	=>  Location: PIN_C13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[3]	=>  Location: PIN_A14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[4]	=>  Location: PIN_B14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[5]	=>  Location: PIN_E14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX1_D[6]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[0]	=>  Location: PIN_D15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[1]	=>  Location: PIN_A16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[2]	=>  Location: PIN_B16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[3]	=>  Location: PIN_E15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[4]	=>  Location: PIN_A17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[5]	=>  Location: PIN_B17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX2_D[6]	=>  Location: PIN_F14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[0]	=>  Location: PIN_B18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[1]	=>  Location: PIN_F15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[2]	=>  Location: PIN_A19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[3]	=>  Location: PIN_B19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[4]	=>  Location: PIN_C19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[5]	=>  Location: PIN_D19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// HEX3_D[6]	=>  Location: PIN_G15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_SDI	=>  Location: PIN_V5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SCK	=>  Location: PIN_W10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_CS	=>  Location: PIN_V12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// DAC_LD	=>  Location: PIN_W13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// ADC_SDI	=>  Location: PIN_V8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// ADC_CS	=>  Location: PIN_W6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[0]	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[1]	=>  Location: PIN_J2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[2]	=>  Location: PIN_J3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[3]	=>  Location: PIN_H1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[4]	=>  Location: PIN_F2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[5]	=>  Location: PIN_E1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[6]	=>  Location: PIN_C1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[7]	=>  Location: PIN_C2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[8]	=>  Location: PIN_B2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LEDG[9]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// PWM_OUT	=>  Location: PIN_U14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// SW[3]	=>  Location: PIN_G4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[2]	=>  Location: PIN_H6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[1]	=>  Location: PIN_H5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[0]	=>  Location: PIN_J6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[7]	=>  Location: PIN_E3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[6]	=>  Location: PIN_H7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[5]	=>  Location: PIN_J7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[4]	=>  Location: PIN_G5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[8]	=>  Location: PIN_E4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// CLOCK_50	=>  Location: PIN_G21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// SW[9]	=>  Location: PIN_D2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+// ADC_SDO	=>  Location: PIN_U7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("top_min_1200mv_0c_v_fast.sdo");
+// synopsys translate_on
+
+wire \HEX0_D[0]~output_o ;
+wire \HEX0_D[1]~output_o ;
+wire \HEX0_D[2]~output_o ;
+wire \HEX0_D[3]~output_o ;
+wire \HEX0_D[4]~output_o ;
+wire \HEX0_D[5]~output_o ;
+wire \HEX0_D[6]~output_o ;
+wire \HEX1_D[0]~output_o ;
+wire \HEX1_D[1]~output_o ;
+wire \HEX1_D[2]~output_o ;
+wire \HEX1_D[3]~output_o ;
+wire \HEX1_D[4]~output_o ;
+wire \HEX1_D[5]~output_o ;
+wire \HEX1_D[6]~output_o ;
+wire \HEX2_D[0]~output_o ;
+wire \HEX2_D[1]~output_o ;
+wire \HEX2_D[2]~output_o ;
+wire \HEX2_D[3]~output_o ;
+wire \HEX2_D[4]~output_o ;
+wire \HEX2_D[5]~output_o ;
+wire \HEX2_D[6]~output_o ;
+wire \HEX3_D[0]~output_o ;
+wire \HEX3_D[1]~output_o ;
+wire \HEX3_D[2]~output_o ;
+wire \HEX3_D[3]~output_o ;
+wire \HEX3_D[4]~output_o ;
+wire \HEX3_D[5]~output_o ;
+wire \HEX3_D[6]~output_o ;
+wire \DAC_SDI~output_o ;
+wire \SCK~output_o ;
+wire \DAC_CS~output_o ;
+wire \DAC_LD~output_o ;
+wire \ADC_SDI~output_o ;
+wire \ADC_CS~output_o ;
+wire \LEDG[0]~output_o ;
+wire \LEDG[1]~output_o ;
+wire \LEDG[2]~output_o ;
+wire \LEDG[3]~output_o ;
+wire \LEDG[4]~output_o ;
+wire \LEDG[5]~output_o ;
+wire \LEDG[6]~output_o ;
+wire \LEDG[7]~output_o ;
+wire \LEDG[8]~output_o ;
+wire \LEDG[9]~output_o ;
+wire \PWM_OUT~output_o ;
+wire \SW[8]~input_o ;
+wire \SW[7]~input_o ;
+wire \SW[6]~input_o ;
+wire \SW[5]~input_o ;
+wire \SW[4]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ;
+wire \SW[3]~input_o ;
+wire \SW[2]~input_o ;
+wire \SW[0]~input_o ;
+wire \SW[1]~input_o ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ;
+wire \SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ;
+wire \BCD_CONVERT|A9|WideOr2~0_combout ;
+wire \BCD_CONVERT|A9|WideOr1~combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ;
+wire \BCD_CONVERT|A9|WideOr3~0_combout ;
+wire \BCD_CONVERT|A12|WideOr1~0_combout ;
+wire \BCD_CONVERT|A12|WideOr2~0_combout ;
+wire \BCD_CONVERT|A12|WideOr3~0_combout ;
+wire \BCD_CONVERT|A15|WideOr1~0_combout ;
+wire \BCD_CONVERT|A15|WideOr3~0_combout ;
+wire \BCD_CONVERT|A15|WideOr2~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ;
+wire \BCD_CONVERT|A18|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ;
+wire \BCD_CONVERT|A18|WideOr2~0_combout ;
+wire \BCD_CONVERT|A18|WideOr3~0_combout ;
+wire \BCD_CONVERT|A21|WideOr1~0_combout ;
+wire \BCD_CONVERT|A21|WideOr2~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ;
+wire \BCD_CONVERT|A21|WideOr3~0_combout ;
+wire \BCD_CONVERT|A25|WideOr1~0_combout ;
+wire \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ;
+wire \BCD_CONVERT|A25|WideOr2~0_combout ;
+wire \BCD_CONVERT|A25|WideOr3~0_combout ;
+wire \SEG0|WideOr6~0_combout ;
+wire \SEG0|WideOr5~0_combout ;
+wire \SEG0|WideOr4~0_combout ;
+wire \SEG0|WideOr3~0_combout ;
+wire \SEG0|WideOr2~0_combout ;
+wire \SEG0|WideOr1~0_combout ;
+wire \SEG0|WideOr0~0_combout ;
+wire \BCD_CONVERT|A9|Decoder0~0_combout ;
+wire \BCD_CONVERT|A9|WideOr0~0_combout ;
+wire \BCD_CONVERT|A9|WideOr0~1_combout ;
+wire \BCD_CONVERT|A15|WideOr0~0_combout ;
+wire \BCD_CONVERT|A7|WideOr0~0_combout ;
+wire \BCD_CONVERT|A12|WideOr0~0_combout ;
+wire \BCD_CONVERT|A17|Decoder0~5_combout ;
+wire \BCD_CONVERT|A17|WideOr2~3_combout ;
+wire \BCD_CONVERT|A17|WideOr2~7_combout ;
+wire \BCD_CONVERT|A17|Decoder0~3_combout ;
+wire \BCD_CONVERT|A17|WideOr2~6_combout ;
+wire \BCD_CONVERT|A7|WideOr0~1_combout ;
+wire \BCD_CONVERT|A17|WideOr3~0_combout ;
+wire \BCD_CONVERT|A17|Decoder0~4_combout ;
+wire \BCD_CONVERT|A17|WideOr3~1_combout ;
+wire \BCD_CONVERT|A17|Decoder0~2_combout ;
+wire \BCD_CONVERT|A17|Decoder0~6_combout ;
+wire \BCD_CONVERT|A17|WideOr1~0_combout ;
+wire \BCD_CONVERT|A18|WideOr0~0_combout ;
+wire \BCD_CONVERT|A20|WideOr2~0_combout ;
+wire \BCD_CONVERT|A20|WideOr1~0_combout ;
+wire \BCD_CONVERT|A21|WideOr0~0_combout ;
+wire \BCD_CONVERT|A20|WideOr3~0_combout ;
+wire \BCD_CONVERT|A24|WideOr1~0_combout ;
+wire \BCD_CONVERT|A24|WideOr3~0_combout ;
+wire \BCD_CONVERT|A24|WideOr2~0_combout ;
+wire \BCD_CONVERT|A25|WideOr0~0_combout ;
+wire \SEG1|WideOr6~0_combout ;
+wire \SEG1|WideOr5~0_combout ;
+wire \SEG1|WideOr4~0_combout ;
+wire \SEG1|WideOr3~0_combout ;
+wire \SEG1|WideOr2~0_combout ;
+wire \SEG1|WideOr1~0_combout ;
+wire \SEG1|WideOr0~0_combout ;
+wire \BCD_CONVERT|A24|WideOr0~0_combout ;
+wire \BCD_CONVERT|A14|WideOr0~2_combout ;
+wire \BCD_CONVERT|A17|Decoder0~7_combout ;
+wire \BCD_CONVERT|A17|WideOr0~0_combout ;
+wire \BCD_CONVERT|A17|WideOr0~combout ;
+wire \BCD_CONVERT|A20|WideOr0~0_combout ;
+wire \SEG2|Decoder0~0_combout ;
+wire \SEG2|Decoder0~1_combout ;
+wire \SEG2|WideOr6~combout ;
+wire \SEG2|Decoder0~2_combout ;
+wire \SEG2|Decoder0~3_combout ;
+wire \SEG2|WideOr5~combout ;
+wire \SEG2|Decoder0~4_combout ;
+wire \SEG2|Decoder0~5_combout ;
+wire \SEG2|Decoder0~6_combout ;
+wire \SEG2|WideOr2~0_combout ;
+wire \SEG2|Decoder0~7_combout ;
+wire \SEG2|WideOr2~combout ;
+wire \SEG2|WideOr1~combout ;
+wire \SEG2|Decoder0~8_combout ;
+wire \SEG2|WideOr0~combout ;
+wire \BCD_CONVERT|A23|WideOr0~5_combout ;
+wire \BCD_CONVERT|A23|WideOr0~17_combout ;
+wire \CLOCK_50~input_o ;
+wire \SPI_DAC|clk_1MHz~0_combout ;
+wire \CLOCK_50~inputclkctrl_outclk ;
+wire \SPI_ADC|Add0~0_combout ;
+wire \SPI_ADC|Add0~7 ;
+wire \SPI_ADC|Add0~8_combout ;
+wire \SPI_ADC|ctr~0_combout ;
+wire \SPI_ADC|Add0~1 ;
+wire \SPI_ADC|Add0~2_combout ;
+wire \SPI_ADC|ctr~1_combout ;
+wire \SPI_ADC|Add0~3 ;
+wire \SPI_ADC|Add0~4_combout ;
+wire \SPI_ADC|ctr~2_combout ;
+wire \SPI_ADC|Add0~5 ;
+wire \SPI_ADC|Add0~6_combout ;
+wire \SPI_DAC|Equal0~0_combout ;
+wire \SPI_DAC|Equal0~1_combout ;
+wire \SPI_DAC|clk_1MHz~q ;
+wire \SPI_DAC|clk_1MHz~clkctrl_outclk ;
+wire \PWM_DC|count[0]~27_combout ;
+wire \GEN_10K|Add0~23 ;
+wire \GEN_10K|Add0~24_combout ;
+wire \GEN_10K|ctr~6_combout ;
+wire \GEN_10K|Add0~25 ;
+wire \GEN_10K|Add0~26_combout ;
+wire \GEN_10K|ctr~7_combout ;
+wire \GEN_10K|Add0~27 ;
+wire \GEN_10K|Add0~28_combout ;
+wire \GEN_10K|ctr~8_combout ;
+wire \GEN_10K|Add0~29 ;
+wire \GEN_10K|Add0~30_combout ;
+wire \GEN_10K|ctr~9_combout ;
+wire \GEN_10K|Add0~31 ;
+wire \GEN_10K|Add0~32_combout ;
+wire \GEN_10K|ctr~10_combout ;
+wire \GEN_10K|Add0~33 ;
+wire \GEN_10K|Add0~34_combout ;
+wire \GEN_10K|ctr~11_combout ;
+wire \GEN_10K|Add0~35 ;
+wire \GEN_10K|Add0~36_combout ;
+wire \GEN_10K|ctr~12_combout ;
+wire \GEN_10K|Add0~37 ;
+wire \GEN_10K|Add0~38_combout ;
+wire \GEN_10K|ctr~13_combout ;
+wire \GEN_10K|Add0~39 ;
+wire \GEN_10K|Add0~40_combout ;
+wire \GEN_10K|ctr~14_combout ;
+wire \GEN_10K|Equal0~5_combout ;
+wire \GEN_10K|Add0~1_cout ;
+wire \GEN_10K|Add0~2_combout ;
+wire \GEN_10K|Add0~3 ;
+wire \GEN_10K|Add0~4_combout ;
+wire \GEN_10K|ctr~0_combout ;
+wire \GEN_10K|Add0~5 ;
+wire \GEN_10K|Add0~6_combout ;
+wire \GEN_10K|ctr~1_combout ;
+wire \GEN_10K|Add0~7 ;
+wire \GEN_10K|Add0~8_combout ;
+wire \GEN_10K|ctr~2_combout ;
+wire \GEN_10K|Add0~9 ;
+wire \GEN_10K|Add0~10_combout ;
+wire \GEN_10K|ctr~3_combout ;
+wire \GEN_10K|Add0~11 ;
+wire \GEN_10K|Add0~12_combout ;
+wire \GEN_10K|Add0~13 ;
+wire \GEN_10K|Add0~14_combout ;
+wire \GEN_10K|Add0~15 ;
+wire \GEN_10K|Add0~16_combout ;
+wire \GEN_10K|Add0~17 ;
+wire \GEN_10K|Add0~18_combout ;
+wire \GEN_10K|ctr~4_combout ;
+wire \GEN_10K|Add0~19 ;
+wire \GEN_10K|Add0~20_combout ;
+wire \GEN_10K|ctr~5_combout ;
+wire \GEN_10K|Add0~21 ;
+wire \GEN_10K|Add0~22_combout ;
+wire \GEN_10K|Equal0~2_combout ;
+wire \GEN_10K|Equal0~0_combout ;
+wire \GEN_10K|Equal0~1_combout ;
+wire \GEN_10K|Equal0~3_combout ;
+wire \GEN_10K|Equal0~4_combout ;
+wire \GEN_10K|clkout~0_combout ;
+wire \GEN_10K|clkout~q ;
+wire \PULSE|state.IDLE~feeder_combout ;
+wire \PULSE|state.IDLE~q ;
+wire \PULSE|pulse~1_combout ;
+wire \PULSE|pulse~q ;
+wire \SPI_DAC|Selector2~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_DAC|Selector0~0_combout ;
+wire \SPI_DAC|sr_state.IDLE~q ;
+wire \SPI_DAC|Selector1~0_combout ;
+wire \SPI_DAC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_DAC|dac_start~0_combout ;
+wire \SPI_DAC|dac_start~1_combout ;
+wire \SPI_DAC|dac_start~q ;
+wire \SPI_DAC|state[0]~5_combout ;
+wire \SPI_DAC|state[3]~12 ;
+wire \SPI_DAC|state[4]~13_combout ;
+wire \SPI_DAC|Selector8~0_combout ;
+wire \SPI_DAC|state[0]~6 ;
+wire \SPI_DAC|state[1]~7_combout ;
+wire \SPI_DAC|state[1]~8 ;
+wire \SPI_DAC|state[2]~9_combout ;
+wire \SPI_DAC|state[2]~10 ;
+wire \SPI_DAC|state[3]~11_combout ;
+wire \SPI_DAC|Equal1~0_combout ;
+wire \SPI_DAC|Selector9~0_combout ;
+wire \SPI_DAC|dac_cs~q ;
+wire \SPI_ADC|clk_1MHz~0_combout ;
+wire \SPI_ADC|clk_1MHz~q ;
+wire \SPI_ADC|clk_1MHz~clkctrl_outclk ;
+wire \ADC_SDO~input_o ;
+wire \SPI_ADC|Selector2~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_HIGH~q ;
+wire \SPI_ADC|Selector0~0_combout ;
+wire \SPI_ADC|sr_state.IDLE~q ;
+wire \SPI_ADC|Selector1~0_combout ;
+wire \SPI_ADC|sr_state.WAIT_CSB_FALL~q ;
+wire \SPI_ADC|adc_start~0_combout ;
+wire \SPI_ADC|adc_start~1_combout ;
+wire \SPI_ADC|adc_start~q ;
+wire \SPI_ADC|Add1~5 ;
+wire \SPI_ADC|Add1~6_combout ;
+wire \SPI_ADC|Add1~7 ;
+wire \SPI_ADC|Add1~8_combout ;
+wire \SPI_ADC|state~1_combout ;
+wire \SPI_ADC|Selector4~2_combout ;
+wire \SPI_ADC|Add1~0_combout ;
+wire \SPI_ADC|Selector5~0_combout ;
+wire \SPI_ADC|Add1~1 ;
+wire \SPI_ADC|Add1~2_combout ;
+wire \SPI_ADC|Add1~3 ;
+wire \SPI_ADC|Add1~4_combout ;
+wire \SPI_ADC|state~0_combout ;
+wire \SPI_ADC|Selector4~3_combout ;
+wire \SPI_ADC|adc_cs~q ;
+wire \SPI_ADC|WideOr0~0_combout ;
+wire \SPI_ADC|WideOr0~1_combout ;
+wire \SPI_ADC|shift_ena~q ;
+wire \SPI_ADC|always3~0_combout ;
+wire \SPI_ADC|shift_reg[1]~feeder_combout ;
+wire \SPI_ADC|shift_reg[3]~feeder_combout ;
+wire \SPI_ADC|shift_reg[5]~feeder_combout ;
+wire \SPI_ADC|shift_reg[6]~feeder_combout ;
+wire \SPI_ADC|Decoder0~0_combout ;
+wire \SPI_ADC|Decoder0~1_combout ;
+wire \SPI_ADC|adc_done~q ;
+wire \DUMMY|PULSE2|state.IDLE~0_combout ;
+wire \DUMMY|PULSE2|state.IDLE~q ;
+wire \DUMMY|PULSE2|pulse~1_combout ;
+wire \DUMMY|PULSE2|pulse~q ;
+wire \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ;
+wire \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ;
+wire \SPI_ADC|shift_reg[9]~feeder_combout ;
+wire \SPI_ADC|adc_cs~clkctrl_outclk ;
+wire \DUMMY|ctr[0]~36_combout ;
+wire \DUMMY|ctr[1]~12_combout ;
+wire \DUMMY|ctr[1]~13 ;
+wire \DUMMY|ctr[2]~14_combout ;
+wire \DUMMY|ctr[2]~15 ;
+wire \DUMMY|ctr[3]~16_combout ;
+wire \DUMMY|ctr[3]~17 ;
+wire \DUMMY|ctr[4]~18_combout ;
+wire \DUMMY|wraddr[4]~0_combout ;
+wire \DUMMY|ctr[4]~19 ;
+wire \DUMMY|ctr[5]~20_combout ;
+wire \DUMMY|wraddr[4]~1 ;
+wire \DUMMY|wraddr[5]~2_combout ;
+wire \DUMMY|ctr[5]~21 ;
+wire \DUMMY|ctr[6]~22_combout ;
+wire \DUMMY|wraddr[5]~3 ;
+wire \DUMMY|wraddr[6]~4_combout ;
+wire \DUMMY|ctr[6]~23 ;
+wire \DUMMY|ctr[7]~24_combout ;
+wire \DUMMY|wraddr[6]~5 ;
+wire \DUMMY|wraddr[7]~6_combout ;
+wire \DUMMY|ctr[7]~25 ;
+wire \DUMMY|ctr[8]~26_combout ;
+wire \DUMMY|wraddr[7]~7 ;
+wire \DUMMY|wraddr[8]~8_combout ;
+wire \DUMMY|ctr[8]~27 ;
+wire \DUMMY|ctr[9]~28_combout ;
+wire \DUMMY|wraddr[8]~9 ;
+wire \DUMMY|wraddr[9]~10_combout ;
+wire \DUMMY|ctr[9]~29 ;
+wire \DUMMY|ctr[10]~30_combout ;
+wire \DUMMY|wraddr[9]~11 ;
+wire \DUMMY|wraddr[10]~12_combout ;
+wire \DUMMY|ctr[10]~31 ;
+wire \DUMMY|ctr[11]~32_combout ;
+wire \DUMMY|wraddr[10]~13 ;
+wire \DUMMY|wraddr[11]~14_combout ;
+wire \DUMMY|ctr[11]~33 ;
+wire \DUMMY|ctr[12]~34_combout ;
+wire \DUMMY|wraddr[11]~15 ;
+wire \DUMMY|wraddr[12]~16_combout ;
+wire \SPI_ADC|data_from_adc[5]~feeder_combout ;
+wire \DUMMY|Add0~12_combout ;
+wire \SPI_ADC|data_from_adc[4]~feeder_combout ;
+wire \DUMMY|Add0~10_combout ;
+wire \DUMMY|Add0~8_combout ;
+wire \SPI_ADC|data_from_adc[2]~feeder_combout ;
+wire \DUMMY|Add0~6_combout ;
+wire \DUMMY|Add0~4_combout ;
+wire \DUMMY|Add0~2_combout ;
+wire \SPI_ADC|data_from_adc[0]~feeder_combout ;
+wire \DUMMY|Add0~1 ;
+wire \DUMMY|Add0~3 ;
+wire \DUMMY|Add0~5 ;
+wire \DUMMY|Add0~7 ;
+wire \DUMMY|Add0~9 ;
+wire \DUMMY|Add0~11 ;
+wire \DUMMY|Add0~13 ;
+wire \DUMMY|Add0~15 ;
+wire \DUMMY|Add0~17 ;
+wire \DUMMY|Add0~18_combout ;
+wire \DUMMY|Add3~1 ;
+wire \DUMMY|Add3~3 ;
+wire \DUMMY|Add3~4_combout ;
+wire \DUMMY|Add0~16_combout ;
+wire \DUMMY|Add3~2_combout ;
+wire \DUMMY|Add0~14_combout ;
+wire \DUMMY|Add3~0_combout ;
+wire \DUMMY|Add0~0_combout ;
+wire \SPI_DAC|shift_reg~13_combout ;
+wire \SPI_DAC|shift_reg~12_combout ;
+wire \SPI_DAC|shift_reg~11_combout ;
+wire \SPI_DAC|shift_reg~10_combout ;
+wire \SPI_DAC|shift_reg~9_combout ;
+wire \SPI_DAC|shift_reg~8_combout ;
+wire \SPI_DAC|shift_reg~7_combout ;
+wire \SPI_DAC|shift_reg~6_combout ;
+wire \SPI_DAC|shift_reg~5_combout ;
+wire \DUMMY|data_out[9]~0_combout ;
+wire \SPI_DAC|shift_reg~4_combout ;
+wire \SPI_DAC|shift_reg~3_combout ;
+wire \SPI_DAC|shift_reg~2_combout ;
+wire \SPI_DAC|shift_reg~1_combout ;
+wire \SPI_DAC|shift_reg~0_combout ;
+wire \SCK~0_combout ;
+wire \SPI_DAC|Equal2~0_combout ;
+wire \SPI_DAC|dac_ld~q ;
+wire \SW[9]~input_o ;
+wire \SPI_ADC|Selector6~0_combout ;
+wire \SPI_ADC|Selector6~1_combout ;
+wire \SPI_ADC|adc_din~q ;
+wire \PWM_DC|count[1]~9_combout ;
+wire \PWM_DC|count[1]~10 ;
+wire \PWM_DC|count[2]~11_combout ;
+wire \PWM_DC|count[2]~12 ;
+wire \PWM_DC|count[3]~13_combout ;
+wire \PWM_DC|count[3]~14 ;
+wire \PWM_DC|count[4]~15_combout ;
+wire \PWM_DC|count[4]~16 ;
+wire \PWM_DC|count[5]~17_combout ;
+wire \PWM_DC|count[5]~18 ;
+wire \PWM_DC|count[6]~19_combout ;
+wire \PWM_DC|count[6]~20 ;
+wire \PWM_DC|count[7]~21_combout ;
+wire \PWM_DC|count[7]~22 ;
+wire \PWM_DC|count[8]~23_combout ;
+wire \PWM_DC|count[8]~24 ;
+wire \PWM_DC|count[9]~25_combout ;
+wire \PWM_DC|LessThan0~1_cout ;
+wire \PWM_DC|LessThan0~3_cout ;
+wire \PWM_DC|LessThan0~5_cout ;
+wire \PWM_DC|LessThan0~7_cout ;
+wire \PWM_DC|LessThan0~9_cout ;
+wire \PWM_DC|LessThan0~11_cout ;
+wire \PWM_DC|LessThan0~13_cout ;
+wire \PWM_DC|LessThan0~15_cout ;
+wire \PWM_DC|LessThan0~17_cout ;
+wire \PWM_DC|LessThan0~18_combout ;
+wire \PWM_DC|pwm_out~0_combout ;
+wire \PWM_DC|pwm_out~q ;
+wire [20:0] \GEN_10K|ctr ;
+wire [4:0] \SPI_DAC|state ;
+wire [15:0] \SPI_DAC|shift_reg ;
+wire [9:0] \PWM_DC|d ;
+wire [9:0] \PWM_DC|count ;
+wire [4:0] \SPI_ADC|state ;
+wire [9:0] \SPI_ADC|shift_reg ;
+wire [9:0] \SPI_ADC|data_from_adc ;
+wire [4:0] \SPI_ADC|ctr ;
+wire [9:0] \DUMMY|data_out ;
+wire [12:0] \DUMMY|ctr ;
+wire [8:0] \DUMMY|DELAY|altsyncram_component|auto_generated|q_b ;
+
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ;
+wire [0:0] \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0];
+
+assign \DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] = \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
+
+// Location: IOOBUF_X21_Y29_N23
+cycloneiii_io_obuf \HEX0_D[0]~output (
+	.i(\SEG0|WideOr6~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[0]~output .bus_hold = "false";
+defparam \HEX0_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N30
+cycloneiii_io_obuf \HEX0_D[1]~output (
+	.i(\SEG0|WideOr5~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[1]~output .bus_hold = "false";
+defparam \HEX0_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N2
+cycloneiii_io_obuf \HEX0_D[2]~output (
+	.i(\SEG0|WideOr4~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[2]~output .bus_hold = "false";
+defparam \HEX0_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N30
+cycloneiii_io_obuf \HEX0_D[3]~output (
+	.i(\SEG0|WideOr3~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[3]~output .bus_hold = "false";
+defparam \HEX0_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N9
+cycloneiii_io_obuf \HEX0_D[4]~output (
+	.i(\SEG0|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[4]~output .bus_hold = "false";
+defparam \HEX0_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N23
+cycloneiii_io_obuf \HEX0_D[5]~output (
+	.i(\SEG0|WideOr1~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[5]~output .bus_hold = "false";
+defparam \HEX0_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N16
+cycloneiii_io_obuf \HEX0_D[6]~output (
+	.i(!\SEG0|WideOr0~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX0_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX0_D[6]~output .bus_hold = "false";
+defparam \HEX0_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N2
+cycloneiii_io_obuf \HEX1_D[0]~output (
+	.i(!\SEG1|WideOr6~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[0]~output .bus_hold = "false";
+defparam \HEX1_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X21_Y29_N9
+cycloneiii_io_obuf \HEX1_D[1]~output (
+	.i(\SEG1|WideOr5~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[1]~output .bus_hold = "false";
+defparam \HEX1_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N2
+cycloneiii_io_obuf \HEX1_D[2]~output (
+	.i(\SEG1|WideOr4~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[2]~output .bus_hold = "false";
+defparam \HEX1_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N23
+cycloneiii_io_obuf \HEX1_D[3]~output (
+	.i(!\SEG1|WideOr3~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[3]~output .bus_hold = "false";
+defparam \HEX1_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y29_N30
+cycloneiii_io_obuf \HEX1_D[4]~output (
+	.i(!\SEG1|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[4]~output .bus_hold = "false";
+defparam \HEX1_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N16
+cycloneiii_io_obuf \HEX1_D[5]~output (
+	.i(!\SEG1|WideOr1~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[5]~output .bus_hold = "false";
+defparam \HEX1_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y29_N23
+cycloneiii_io_obuf \HEX1_D[6]~output (
+	.i(!\SEG1|WideOr0~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX1_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX1_D[6]~output .bus_hold = "false";
+defparam \HEX1_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N30
+cycloneiii_io_obuf \HEX2_D[0]~output (
+	.i(\SEG2|WideOr6~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[0]~output .bus_hold = "false";
+defparam \HEX2_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N30
+cycloneiii_io_obuf \HEX2_D[1]~output (
+	.i(\SEG2|WideOr5~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[1]~output .bus_hold = "false";
+defparam \HEX2_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X28_Y29_N2
+cycloneiii_io_obuf \HEX2_D[2]~output (
+	.i(\SEG2|Decoder0~4_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[2]~output .bus_hold = "false";
+defparam \HEX2_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N2
+cycloneiii_io_obuf \HEX2_D[3]~output (
+	.i(!\SEG2|WideOr2~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[3]~output .bus_hold = "false";
+defparam \HEX2_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N16
+cycloneiii_io_obuf \HEX2_D[4]~output (
+	.i(\SEG2|WideOr2~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[4]~output .bus_hold = "false";
+defparam \HEX2_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X30_Y29_N23
+cycloneiii_io_obuf \HEX2_D[5]~output (
+	.i(\SEG2|WideOr1~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[5]~output .bus_hold = "false";
+defparam \HEX2_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N2
+cycloneiii_io_obuf \HEX2_D[6]~output (
+	.i(\SEG2|WideOr0~combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX2_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX2_D[6]~output .bus_hold = "false";
+defparam \HEX2_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N23
+cycloneiii_io_obuf \HEX3_D[0]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[0]~output .bus_hold = "false";
+defparam \HEX3_D[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y29_N16
+cycloneiii_io_obuf \HEX3_D[1]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[1]~output .bus_hold = "false";
+defparam \HEX3_D[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N9
+cycloneiii_io_obuf \HEX3_D[2]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[2]~output .bus_hold = "false";
+defparam \HEX3_D[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X32_Y29_N2
+cycloneiii_io_obuf \HEX3_D[3]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[3]~output .bus_hold = "false";
+defparam \HEX3_D[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N23
+cycloneiii_io_obuf \HEX3_D[4]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[4]~output .bus_hold = "false";
+defparam \HEX3_D[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X37_Y29_N30
+cycloneiii_io_obuf \HEX3_D[5]~output (
+	.i(!\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[5]~output .bus_hold = "false";
+defparam \HEX3_D[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y29_N30
+cycloneiii_io_obuf \HEX3_D[6]~output (
+	.i(vcc),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\HEX3_D[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \HEX3_D[6]~output .bus_hold = "false";
+defparam \HEX3_D[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X3_Y0_N30
+cycloneiii_io_obuf \DAC_SDI~output (
+	.i(\SPI_DAC|shift_reg [15]),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_SDI~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_SDI~output .bus_hold = "false";
+defparam \DAC_SDI~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X19_Y0_N16
+cycloneiii_io_obuf \SCK~output (
+	.i(\SCK~0_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\SCK~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \SCK~output .bus_hold = "false";
+defparam \SCK~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X23_Y0_N2
+cycloneiii_io_obuf \DAC_CS~output (
+	.i(!\SPI_DAC|dac_cs~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_CS~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_CS~output .bus_hold = "false";
+defparam \DAC_CS~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X26_Y0_N30
+cycloneiii_io_obuf \DAC_LD~output (
+	.i(\SPI_DAC|dac_ld~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\DAC_LD~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \DAC_LD~output .bus_hold = "false";
+defparam \DAC_LD~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X11_Y0_N30
+cycloneiii_io_obuf \ADC_SDI~output (
+	.i(\SPI_ADC|adc_din~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\ADC_SDI~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \ADC_SDI~output .bus_hold = "false";
+defparam \ADC_SDI~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X7_Y0_N23
+cycloneiii_io_obuf \ADC_CS~output (
+	.i(!\SPI_ADC|adc_cs~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\ADC_CS~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \ADC_CS~output .bus_hold = "false";
+defparam \ADC_CS~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N9
+cycloneiii_io_obuf \LEDG[0]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[0]~output .bus_hold = "false";
+defparam \LEDG[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y20_N2
+cycloneiii_io_obuf \LEDG[1]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[1]~output .bus_hold = "false";
+defparam \LEDG[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N23
+cycloneiii_io_obuf \LEDG[2]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[2]~output .bus_hold = "false";
+defparam \LEDG[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y21_N16
+cycloneiii_io_obuf \LEDG[3]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[3]~output .bus_hold = "false";
+defparam \LEDG[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y24_N23
+cycloneiii_io_obuf \LEDG[4]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[4]~output .bus_hold = "false";
+defparam \LEDG[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y24_N16
+cycloneiii_io_obuf \LEDG[5]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[5]~output .bus_hold = "false";
+defparam \LEDG[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N23
+cycloneiii_io_obuf \LEDG[6]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[6]~output .bus_hold = "false";
+defparam \LEDG[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N16
+cycloneiii_io_obuf \LEDG[7]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[7]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[7]~output .bus_hold = "false";
+defparam \LEDG[7]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y27_N9
+cycloneiii_io_obuf \LEDG[8]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[8]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[8]~output .bus_hold = "false";
+defparam \LEDG[8]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y27_N16
+cycloneiii_io_obuf \LEDG[9]~output (
+	.i(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LEDG[9]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LEDG[9]~output .bus_hold = "false";
+defparam \LEDG[9]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X39_Y0_N23
+cycloneiii_io_obuf \PWM_OUT~output (
+	.i(\PWM_DC|pwm_out~q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\PWM_OUT~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \PWM_OUT~output .bus_hold = "false";
+defparam \PWM_OUT~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y26_N1
+cycloneiii_io_ibuf \SW[8]~input (
+	.i(SW[8]),
+	.ibar(gnd),
+	.o(\SW[8]~input_o ));
+// synopsys translate_off
+defparam \SW[8]~input .bus_hold = "false";
+defparam \SW[8]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y26_N8
+cycloneiii_io_ibuf \SW[7]~input (
+	.i(SW[7]),
+	.ibar(gnd),
+	.o(\SW[7]~input_o ));
+// synopsys translate_off
+defparam \SW[7]~input .bus_hold = "false";
+defparam \SW[7]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N15
+cycloneiii_io_ibuf \SW[6]~input (
+	.i(SW[6]),
+	.ibar(gnd),
+	.o(\SW[6]~input_o ));
+// synopsys translate_off
+defparam \SW[6]~input .bus_hold = "false";
+defparam \SW[6]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y22_N15
+cycloneiii_io_ibuf \SW[5]~input (
+	.i(SW[5]),
+	.ibar(gnd),
+	.o(\SW[5]~input_o ));
+// synopsys translate_off
+defparam \SW[5]~input .bus_hold = "false";
+defparam \SW[5]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y27_N22
+cycloneiii_io_ibuf \SW[4]~input (
+	.i(SW[4]),
+	.ibar(gnd),
+	.o(\SW[4]~input_o ));
+// synopsys translate_off
+defparam \SW[4]~input .bus_hold = "false";
+defparam \SW[4]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  = (\SW[7]~input_o  & (\SW[5]~input_o  $ (((\SW[6]~input_o  & !\SW[4]~input_o ))))) # (!\SW[7]~input_o  & ((\SW[5]~input_o  & ((\SW[6]~input_o ) # (!\SW[4]~input_o ))) # (!\SW[5]~input_o  & 
+// ((\SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 .lut_mask = 16'hE578;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][10]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y23_N8
+cycloneiii_io_ibuf \SW[3]~input (
+	.i(SW[3]),
+	.ibar(gnd),
+	.o(\SW[3]~input_o ));
+// synopsys translate_off
+defparam \SW[3]~input .bus_hold = "false";
+defparam \SW[3]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N22
+cycloneiii_io_ibuf \SW[2]~input (
+	.i(SW[2]),
+	.ibar(gnd),
+	.o(\SW[2]~input_o ));
+// synopsys translate_off
+defparam \SW[2]~input .bus_hold = "false";
+defparam \SW[2]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y24_N1
+cycloneiii_io_ibuf \SW[0]~input (
+	.i(SW[0]),
+	.ibar(gnd),
+	.o(\SW[0]~input_o ));
+// synopsys translate_off
+defparam \SW[0]~input .bus_hold = "false";
+defparam \SW[0]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y27_N1
+cycloneiii_io_ibuf \SW[1]~input (
+	.i(SW[1]),
+	.ibar(gnd),
+	.o(\SW[1]~input_o ));
+// synopsys translate_off
+defparam \SW[1]~input .bus_hold = "false";
+defparam \SW[1]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N28
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  = (\SW[3]~input_o  & ((\SW[2]~input_o ) # ((\SW[0]~input_o  & \SW[1]~input_o ))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 .lut_mask = 16'hA888;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][14]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N2
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  = (\SW[3]~input_o  & (!\SW[2]~input_o  & ((!\SW[1]~input_o ) # (!\SW[0]~input_o )))) # (!\SW[3]~input_o  & (\SW[2]~input_o  & ((\SW[1]~input_o ))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 .lut_mask = 16'h4622;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][13]~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  = (\SW[7]~input_o  & ((\SW[6]~input_o  & ((\SW[4]~input_o ))) # (!\SW[6]~input_o  & ((\SW[5]~input_o ) # (!\SW[4]~input_o ))))) # (!\SW[7]~input_o  & (\SW[4]~input_o  $ (((\SW[6]~input_o  & 
+// \SW[5]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 .lut_mask = 16'hBD62;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][9]~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  = (\SW[2]~input_o  & ((\SW[3]~input_o  & ((\SW[0]~input_o ) # (\SW[1]~input_o ))) # (!\SW[3]~input_o  & ((!\SW[1]~input_o ))))) # (!\SW[2]~input_o  & (\SW[3]~input_o  $ (((\SW[0]~input_o  & 
+// \SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 .lut_mask = 16'h9AE6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][12]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  = (\SW[6]~input_o  & ((\SW[7]~input_o  & ((\SW[5]~input_o ) # (\SW[4]~input_o ))) # (!\SW[7]~input_o  & (!\SW[5]~input_o )))) # (!\SW[6]~input_o  & (\SW[7]~input_o  $ (((\SW[5]~input_o  & 
+// \SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 .lut_mask = 16'h9EA6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][12]~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  = (\SW[5]~input_o  & ((\SW[6]~input_o  & ((\SW[7]~input_o ) # (\SW[4]~input_o ))) # (!\SW[6]~input_o  & ((!\SW[4]~input_o ))))) # (!\SW[5]~input_o  & (\SW[6]~input_o  $ (((\SW[7]~input_o  & 
+// \SW[4]~input_o )))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 .lut_mask = 16'hC6BC;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][11]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  = (\SW[0]~input_o  & (\SW[2]~input_o  $ (((\SW[3]~input_o  & !\SW[1]~input_o ))))) # (!\SW[0]~input_o  & ((\SW[2]~input_o  & ((\SW[3]~input_o ) # (!\SW[1]~input_o ))) # (!\SW[2]~input_o  & 
+// ((\SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 .lut_mask = 16'hCB6C;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][11]~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N0
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  = (\SW[3]~input_o  & (\SW[1]~input_o  $ (((\SW[2]~input_o  & !\SW[0]~input_o ))))) # (!\SW[3]~input_o  & ((\SW[0]~input_o  & ((\SW[2]~input_o ) # (!\SW[1]~input_o ))) # (!\SW[0]~input_o  & 
+// ((\SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .lut_mask = 16'hE758;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N26
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  = (\SW[3]~input_o  & ((\SW[2]~input_o  & (\SW[0]~input_o )) # (!\SW[2]~input_o  & ((\SW[1]~input_o ) # (!\SW[0]~input_o ))))) # (!\SW[3]~input_o  & (\SW[0]~input_o  $ (((\SW[2]~input_o  & 
+// \SW[1]~input_o )))))
+
+	.dataa(\SW[3]~input_o ),
+	.datab(\SW[2]~input_o ),
+	.datac(\SW[0]~input_o ),
+	.datad(\SW[1]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 .lut_mask = 16'hB6D2;
+defparam \SCALER|lpm_mult_component|mult_core|romout[0][9]~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout  = \SW[7]~input_o  $ (((\SW[6]~input_o  & (!\SW[5]~input_o )) # (!\SW[6]~input_o  & (\SW[5]~input_o  & \SW[4]~input_o ))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 .lut_mask = 16'h96A6;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][4]~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  = \SW[6]~input_o  $ (((\SW[5]~input_o  & !\SW[4]~input_o )))
+
+	.dataa(gnd),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 .lut_mask = 16'hCC3C;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][3]~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  = \SW[5]~input_o  $ (\SW[4]~input_o )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 .lut_mask = 16'h0FF0;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][2]~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & \SW[4]~input_o ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.datab(\SW[4]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 .lut_mask = 16'h0088;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][2]~8_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[1]~1_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 .lut_mask = 16'h0017;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ))) # (!\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout  & (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][3]~6_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[2]~3_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 .lut_mask = 16'h008E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout )) # (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][4]~4_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[3]~5_cout ),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 .lut_mask = 16'h0017;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ))) # (!\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout  & (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][9]~2_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[4]~7_cout ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N14
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][10]~0_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~9 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ))) # (!\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][11]~7_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~11 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  = (\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 )) # (!\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][12]~5_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~13 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  = ((\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  $ (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ))) # (!\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout  & (\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[0][13]~11_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][9]~3_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~15 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 )) # (!\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][10]~1_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[0][14]~12_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~17 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N4
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout  & \SW[8]~input_o ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[5]~8_combout ),
+	.datab(\SW[8]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .lut_mask = 16'h0088;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N6
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[6]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1_cout ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N8
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  $ (GND))) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[7]~12_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'hA50A;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N10
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[8]~14_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h3C3F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N12
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout  = ((\SW[8]~input_o  $ (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9  = CARRY((\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) # (!\SW[8]~input_o  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[9]~16_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N14
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~18_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  = (\SW[7]~input_o  & (!\SW[6]~input_o  & ((!\SW[4]~input_o ) # (!\SW[5]~input_o )))) # (!\SW[7]~input_o  & (\SW[6]~input_o  & (\SW[5]~input_o )))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 .lut_mask = 16'h4262;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][13]~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  $ (GND))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout  & !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|romout[1][11]~9_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[10]~19 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 .lut_mask = 16'hA50A;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N26
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 )) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ) # (!\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][12]~10_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~21 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 .lut_mask = 16'h3C3F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N28
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  = (\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  $ (GND))) # 
+// (!\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25  = CARRY((\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout  & !\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|romout[1][13]~13_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~23 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 .lut_mask = 16'hC30C;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  $ (GND))) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11  & VCC))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13  = CARRY((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ))
+
+	.dataa(gnd),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[11]~20_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hC30C;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N18
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  = (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ) # (GND)))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15  = CARRY((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[12]~22_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 .lut_mask = 16'h5A5F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N20
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  = ((\SW[8]~input_o  $ (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  $ 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 )))) # (GND)
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17  = CARRY((\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ))) # (!\SW[8]~input_o  & (\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 )))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~24_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~15 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 .lut_mask = 16'h698E;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X11_Y26_N16
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout  = (\SW[7]~input_o  & ((\SW[6]~input_o ) # ((\SW[5]~input_o  & \SW[4]~input_o ))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\SW[6]~input_o ),
+	.datac(\SW[5]~input_o ),
+	.datad(\SW[4]~input_o ),
+	.cin(gnd),
+	.combout(\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 .lut_mask = 16'hA888;
+defparam \SCALER|lpm_mult_component|mult_core|romout[1][14]~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y26_N30
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  = \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25  $ (\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|romout[1][14]~14_combout ),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[13]~25 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 .lut_mask = 16'h0FF0;
+defparam \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N22
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  = (\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17  & VCC)) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )))) # (!\SW[8]~input_o  & ((\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )) # (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ) # (GND)))))
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19  = CARRY((\SW[8]~input_o  & (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 )) # (!\SW[8]~input_o  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ))))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|result[14]~26_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ));
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 .lut_mask = 16'h9617;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X15_Y26_N24
+cycloneiii_lcell_comb \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 (
+// Equation(s):
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  = !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~19 ),
+	.combout(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 .lut_mask = 16'h0F0F;
+defparam \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr2~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr2~0 .lut_mask = 16'h6426;
+defparam \BCD_CONVERT|A9|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr1 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr1~combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  $ (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr1 .lut_mask = 16'h0940;
+defparam \BCD_CONVERT|A9|WideOr1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  $ 
+// (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr3~0 .lut_mask = 16'h42B4;
+defparam \BCD_CONVERT|A9|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr1~0_combout  = (\BCD_CONVERT|A9|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & !\BCD_CONVERT|A9|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A9|WideOr2~0_combout  & (\BCD_CONVERT|A9|WideOr1~combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (\BCD_CONVERT|A9|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr1~0 .lut_mask = 16'h444A;
+defparam \BCD_CONVERT|A12|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr2~0_combout  = (\BCD_CONVERT|A9|WideOr1~combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & (!\BCD_CONVERT|A9|WideOr2~0_combout  & \BCD_CONVERT|A9|WideOr3~0_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & ((!\BCD_CONVERT|A9|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A9|WideOr1~combout  & (\BCD_CONVERT|A9|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (!\BCD_CONVERT|A9|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr2~0 .lut_mask = 16'h710C;
+defparam \BCD_CONVERT|A12|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr3~0_combout  = (\BCD_CONVERT|A9|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & (\BCD_CONVERT|A9|WideOr1~combout  $ (\BCD_CONVERT|A9|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A9|WideOr2~0_combout  & (\BCD_CONVERT|A9|WideOr1~combout  $ ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr3~0 .lut_mask = 16'h161C;
+defparam \BCD_CONVERT|A12|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr1~0_combout  = (\BCD_CONVERT|A12|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & ((!\BCD_CONVERT|A12|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A12|WideOr2~0_combout  & (\BCD_CONVERT|A12|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ) # (\BCD_CONVERT|A12|WideOr3~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr1~0 .lut_mask = 16'h0C58;
+defparam \BCD_CONVERT|A15|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N30
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (!\BCD_CONVERT|A12|WideOr1~0_combout  & (!\BCD_CONVERT|A12|WideOr2~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (\BCD_CONVERT|A12|WideOr1~0_combout  $ (((\BCD_CONVERT|A12|WideOr2~0_combout  & \BCD_CONVERT|A12|WideOr3~0_combout )))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr3~0 .lut_mask = 16'h1646;
+defparam \BCD_CONVERT|A15|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr2~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & (\BCD_CONVERT|A12|WideOr3~0_combout  & ((!\BCD_CONVERT|A12|WideOr2~0_combout ) # (!\BCD_CONVERT|A12|WideOr1~0_combout 
+// )))) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & ((\BCD_CONVERT|A12|WideOr1~0_combout  & ((!\BCD_CONVERT|A12|WideOr3~0_combout ))) # (!\BCD_CONVERT|A12|WideOr1~0_combout  & 
+// (!\BCD_CONVERT|A12|WideOr2~0_combout  & \BCD_CONVERT|A12|WideOr3~0_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr2~0 .lut_mask = 16'h2B44;
+defparam \BCD_CONVERT|A15|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr1~0_combout  = (\BCD_CONVERT|A15|WideOr2~0_combout  & (((!\BCD_CONVERT|A15|WideOr3~0_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )))) # 
+// (!\BCD_CONVERT|A15|WideOr2~0_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr1~0 .lut_mask = 16'h0A38;
+defparam \BCD_CONVERT|A18|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr2~0_combout  = (\BCD_CONVERT|A15|WideOr1~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout  & (!\BCD_CONVERT|A15|WideOr2~0_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )) 
+// # (!\BCD_CONVERT|A15|WideOr3~0_combout  & ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ))))) # (!\BCD_CONVERT|A15|WideOr1~0_combout  & (\BCD_CONVERT|A15|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ) # (!\BCD_CONVERT|A15|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr2~0 .lut_mask = 16'h4C26;
+defparam \BCD_CONVERT|A18|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr3~0_combout  = (\BCD_CONVERT|A15|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  $ (\BCD_CONVERT|A15|WideOr3~0_combout 
+// )))) # (!\BCD_CONVERT|A15|WideOr2~0_combout  & (\BCD_CONVERT|A15|WideOr1~0_combout  $ (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr3~0 .lut_mask = 16'h056A;
+defparam \BCD_CONVERT|A18|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr1~0_combout  = (\BCD_CONVERT|A18|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & !\BCD_CONVERT|A18|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A18|WideOr2~0_combout  & (\BCD_CONVERT|A18|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (\BCD_CONVERT|A18|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr1~0 .lut_mask = 16'h0A38;
+defparam \BCD_CONVERT|A21|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr2~0_combout  = (\BCD_CONVERT|A18|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (!\BCD_CONVERT|A18|WideOr2~0_combout  & \BCD_CONVERT|A18|WideOr3~0_combout )) 
+// # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & ((!\BCD_CONVERT|A18|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A18|WideOr1~0_combout  & (\BCD_CONVERT|A18|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (!\BCD_CONVERT|A18|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr2~0 .lut_mask = 16'h4D22;
+defparam \BCD_CONVERT|A21|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (!\BCD_CONVERT|A18|WideOr1~0_combout  & (!\BCD_CONVERT|A18|WideOr2~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout  & (\BCD_CONVERT|A18|WideOr1~0_combout  $ (((\BCD_CONVERT|A18|WideOr2~0_combout  & \BCD_CONVERT|A18|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr3~0 .lut_mask = 16'h1626;
+defparam \BCD_CONVERT|A21|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr1~0_combout  = (\BCD_CONVERT|A21|WideOr2~0_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & !\BCD_CONVERT|A21|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A21|WideOr2~0_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (\BCD_CONVERT|A21|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr1~0 .lut_mask = 16'h222C;
+defparam \BCD_CONVERT|A25|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr2~0_combout  = (\BCD_CONVERT|A21|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & (!\BCD_CONVERT|A21|WideOr2~0_combout  & \BCD_CONVERT|A21|WideOr3~0_combout )) 
+// # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & ((!\BCD_CONVERT|A21|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A21|WideOr1~0_combout  & (\BCD_CONVERT|A21|WideOr3~0_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (!\BCD_CONVERT|A21|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr2~0 .lut_mask = 16'h710A;
+defparam \BCD_CONVERT|A25|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr3~0_combout  = (\BCD_CONVERT|A21|WideOr2~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  $ (\BCD_CONVERT|A21|WideOr3~0_combout 
+// )))) # (!\BCD_CONVERT|A21|WideOr2~0_combout  & (\BCD_CONVERT|A21|WideOr1~0_combout  $ ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr3~0 .lut_mask = 16'h161A;
+defparam \BCD_CONVERT|A25|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N22
+cycloneiii_lcell_comb \SEG0|WideOr6~0 (
+// Equation(s):
+// \SEG0|WideOr6~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr3~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  $ (\BCD_CONVERT|A25|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr6~0 .lut_mask = 16'h0894;
+defparam \SEG0|WideOr6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N0
+cycloneiii_lcell_comb \SEG0|WideOr5~0 (
+// Equation(s):
+// \SEG0|WideOr5~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr5~0 .lut_mask = 16'hB860;
+defparam \SEG0|WideOr5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N10
+cycloneiii_lcell_comb \SEG0|WideOr4~0 (
+// Equation(s):
+// \SEG0|WideOr4~0_combout  = (\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout )))) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr4~0 .lut_mask = 16'hA120;
+defparam \SEG0|WideOr4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N28
+cycloneiii_lcell_comb \SEG0|WideOr3~0 (
+// Equation(s):
+// \SEG0|WideOr3~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr2~0_combout  $ (!\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )) # 
+// (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\BCD_CONVERT|A25|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr3~0 .lut_mask = 16'hC21C;
+defparam \SEG0|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N6
+cycloneiii_lcell_comb \SEG0|WideOr2~0 (
+// Equation(s):
+// \SEG0|WideOr2~0_combout  = (\BCD_CONVERT|A25|WideOr3~0_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ))) # (!\BCD_CONVERT|A25|WideOr3~0_combout  & 
+// ((\BCD_CONVERT|A25|WideOr2~0_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout )) # (!\BCD_CONVERT|A25|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout )))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr2~0 .lut_mask = 16'h445C;
+defparam \SEG0|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N16
+cycloneiii_lcell_comb \SEG0|WideOr1~0 (
+// Equation(s):
+// \SEG0|WideOr1~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (\BCD_CONVERT|A25|WideOr1~0_combout  $ (((\BCD_CONVERT|A25|WideOr3~0_combout ) # (!\BCD_CONVERT|A25|WideOr2~0_combout ))))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & (!\BCD_CONVERT|A25|WideOr1~0_combout  & (!\BCD_CONVERT|A25|WideOr2~0_combout  & \BCD_CONVERT|A25|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr1~0 .lut_mask = 16'h4584;
+defparam \SEG0|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N2
+cycloneiii_lcell_comb \SEG0|WideOr0~0 (
+// Equation(s):
+// \SEG0|WideOr0~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr1~0_combout ) # (\BCD_CONVERT|A25|WideOr2~0_combout  $ (\BCD_CONVERT|A25|WideOr3~0_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout  & ((\BCD_CONVERT|A25|WideOr3~0_combout ) # (\BCD_CONVERT|A25|WideOr1~0_combout  $ (\BCD_CONVERT|A25|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A25|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ),
+	.datac(\BCD_CONVERT|A25|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\SEG0|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG0|WideOr0~0 .lut_mask = 16'hBFDA;
+defparam \SEG0|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N16
+cycloneiii_lcell_comb \BCD_CONVERT|A9|Decoder0~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|Decoder0~0_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ) # 
+// (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  $ (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|Decoder0~0 .lut_mask = 16'hFFF6;
+defparam \BCD_CONVERT|A9|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr0~0_combout  = \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  $ (((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr0~0 .lut_mask = 16'h4DB2;
+defparam \BCD_CONVERT|A9|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A9|WideOr0~1 (
+// Equation(s):
+// \BCD_CONVERT|A9|WideOr0~1_combout  = (\BCD_CONVERT|A9|WideOr0~0_combout ) # (!\BCD_CONVERT|A9|Decoder0~0_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A9|WideOr0~1 .lut_mask = 16'hFF0F;
+defparam \BCD_CONVERT|A9|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A15|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A15|WideOr0~0_combout  = \BCD_CONVERT|A12|WideOr1~0_combout  $ (((\BCD_CONVERT|A12|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ) # (\BCD_CONVERT|A12|WideOr3~0_combout 
+// )))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\BCD_CONVERT|A12|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A12|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A15|WideOr0~0 .lut_mask = 16'h3C6C;
+defparam \BCD_CONVERT|A15|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N26
+cycloneiii_lcell_comb \BCD_CONVERT|A7|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A7|WideOr0~0_combout  = ((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A7|WideOr0~0 .lut_mask = 16'h3377;
+defparam \BCD_CONVERT|A7|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A12|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A12|WideOr0~0_combout  = \BCD_CONVERT|A9|WideOr1~combout  $ (((\BCD_CONVERT|A9|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ) # (\BCD_CONVERT|A9|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A9|WideOr1~combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datad(\BCD_CONVERT|A9|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A12|WideOr0~0 .lut_mask = 16'h666C;
+defparam \BCD_CONVERT|A12|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~5 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~5_combout  = (!\BCD_CONVERT|A15|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  & \BCD_CONVERT|A12|WideOr0~0_combout )) # (!\BCD_CONVERT|A9|WideOr0~1_combout  & 
+// (!\BCD_CONVERT|A7|WideOr0~0_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~5 .lut_mask = 16'h2001;
+defparam \BCD_CONVERT|A17|Decoder0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~3 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~3_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & 
+// !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ) # 
+// ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~3 .lut_mask = 16'h1FF8;
+defparam \BCD_CONVERT|A17|WideOr2~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~7 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~7_combout  = (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & 
+// \BCD_CONVERT|A17|WideOr2~3_combout ))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(gnd),
+	.datad(\BCD_CONVERT|A17|WideOr2~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~7 .lut_mask = 16'h4400;
+defparam \BCD_CONVERT|A17|WideOr2~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~3 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~3_combout  = (\BCD_CONVERT|A15|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  & \BCD_CONVERT|A12|WideOr0~0_combout )) # (!\BCD_CONVERT|A9|WideOr0~1_combout  & 
+// (!\BCD_CONVERT|A7|WideOr0~0_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~3 .lut_mask = 16'h8004;
+defparam \BCD_CONVERT|A17|Decoder0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N10
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr2~6 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr2~6_combout  = (\BCD_CONVERT|A17|Decoder0~5_combout ) # ((\BCD_CONVERT|A17|WideOr2~7_combout ) # (\BCD_CONVERT|A17|Decoder0~3_combout ))
+
+	.dataa(gnd),
+	.datab(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr2~7_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr2~6 .lut_mask = 16'hFFFC;
+defparam \BCD_CONVERT|A17|WideOr2~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A7|WideOr0~1 (
+// Equation(s):
+// \BCD_CONVERT|A7|WideOr0~1_combout  = (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A7|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A7|WideOr0~1 .lut_mask = 16'h0055;
+defparam \BCD_CONVERT|A7|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr3~0_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A7|WideOr0~1_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & !\BCD_CONVERT|A12|WideOr0~0_combout ))) 
+// # (!\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A12|WideOr0~0_combout  & ((\BCD_CONVERT|A7|WideOr0~1_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A7|WideOr0~1_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr3~0 .lut_mask = 16'h4520;
+defparam \BCD_CONVERT|A17|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N0
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~4 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~4_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~4 .lut_mask = 16'h0880;
+defparam \BCD_CONVERT|A17|Decoder0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr3~1 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr3~1_combout  = (\BCD_CONVERT|A17|Decoder0~4_combout ) # ((\BCD_CONVERT|A17|Decoder0~3_combout ) # ((!\BCD_CONVERT|A15|WideOr0~0_combout  & \BCD_CONVERT|A17|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr3~1 .lut_mask = 16'hFFF4;
+defparam \BCD_CONVERT|A17|WideOr3~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N2
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~2 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~2_combout  = (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout  & (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout  & 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout  & \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )))
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~2 .lut_mask = 16'h01AA;
+defparam \BCD_CONVERT|A17|Decoder0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N14
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~6 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~6_combout  = (!\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~6 .lut_mask = 16'h0110;
+defparam \BCD_CONVERT|A17|Decoder0~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N30
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr1~0_combout  = (\BCD_CONVERT|A17|Decoder0~6_combout ) # ((\BCD_CONVERT|A15|WideOr0~0_combout  & (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout  & \BCD_CONVERT|A17|Decoder0~2_combout 
+// )))
+
+	.dataa(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~2_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr1~0 .lut_mask = 16'hFF80;
+defparam \BCD_CONVERT|A17|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A18|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A18|WideOr0~0_combout  = \BCD_CONVERT|A15|WideOr1~0_combout  $ (((\BCD_CONVERT|A15|WideOr2~0_combout  & ((\BCD_CONVERT|A15|WideOr3~0_combout ) # (\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A15|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A15|WideOr2~0_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A18|WideOr0~0 .lut_mask = 16'h5A6A;
+defparam \BCD_CONVERT|A18|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr2~0_combout  = (\BCD_CONVERT|A17|WideOr3~1_combout  & ((\BCD_CONVERT|A17|WideOr2~6_combout  & (!\BCD_CONVERT|A17|WideOr1~0_combout  & \BCD_CONVERT|A18|WideOr0~0_combout )) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & 
+// ((\BCD_CONVERT|A18|WideOr0~0_combout ) # (!\BCD_CONVERT|A17|WideOr1~0_combout ))))) # (!\BCD_CONVERT|A17|WideOr3~1_combout  & (((\BCD_CONVERT|A17|WideOr1~0_combout  & !\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr2~0 .lut_mask = 16'h4C34;
+defparam \BCD_CONVERT|A20|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N0
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr1~0_combout  = (\BCD_CONVERT|A17|WideOr2~6_combout  & (!\BCD_CONVERT|A17|WideOr3~1_combout  & ((!\BCD_CONVERT|A18|WideOr0~0_combout )))) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & (\BCD_CONVERT|A17|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A17|WideOr3~1_combout ) # (\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr1~0 .lut_mask = 16'h5062;
+defparam \BCD_CONVERT|A20|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A21|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A21|WideOr0~0_combout  = \BCD_CONVERT|A18|WideOr1~0_combout  $ (((\BCD_CONVERT|A18|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (\BCD_CONVERT|A18|WideOr3~0_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A18|WideOr1~0_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ),
+	.datac(\BCD_CONVERT|A18|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A21|WideOr0~0 .lut_mask = 16'h5A6A;
+defparam \BCD_CONVERT|A21|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N28
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr3~0_combout  = (\BCD_CONVERT|A17|WideOr2~6_combout  & ((\BCD_CONVERT|A18|WideOr0~0_combout ) # (\BCD_CONVERT|A17|WideOr3~1_combout  $ (!\BCD_CONVERT|A17|WideOr1~0_combout )))) # (!\BCD_CONVERT|A17|WideOr2~6_combout  & 
+// ((\BCD_CONVERT|A17|WideOr1~0_combout  $ (!\BCD_CONVERT|A18|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr3~0 .lut_mask = 16'hFA87;
+defparam \BCD_CONVERT|A20|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr1~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr1~0_combout  = (\BCD_CONVERT|A20|WideOr2~0_combout  & (((!\BCD_CONVERT|A21|WideOr0~0_combout  & \BCD_CONVERT|A20|WideOr3~0_combout )))) # (!\BCD_CONVERT|A20|WideOr2~0_combout  & (\BCD_CONVERT|A20|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr3~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr1~0 .lut_mask = 16'h4A44;
+defparam \BCD_CONVERT|A24|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N24
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr3~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr3~0_combout  = (\BCD_CONVERT|A20|WideOr2~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (\BCD_CONVERT|A20|WideOr1~0_combout  $ (\BCD_CONVERT|A20|WideOr3~0_combout )))) # (!\BCD_CONVERT|A20|WideOr2~0_combout  & 
+// (\BCD_CONVERT|A20|WideOr1~0_combout  $ ((!\BCD_CONVERT|A21|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr3~0 .lut_mask = 16'hE3E9;
+defparam \BCD_CONVERT|A24|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr2~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr2~0_combout  = (\BCD_CONVERT|A20|WideOr1~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout  & (!\BCD_CONVERT|A20|WideOr2~0_combout  & !\BCD_CONVERT|A20|WideOr3~0_combout )) # (!\BCD_CONVERT|A21|WideOr0~0_combout  & 
+// ((\BCD_CONVERT|A20|WideOr3~0_combout ))))) # (!\BCD_CONVERT|A20|WideOr1~0_combout  & (!\BCD_CONVERT|A20|WideOr3~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr2~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr2~0 .lut_mask = 16'h0C71;
+defparam \BCD_CONVERT|A24|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A25|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A25|WideOr0~0_combout  = \BCD_CONVERT|A21|WideOr1~0_combout  $ (((\BCD_CONVERT|A21|WideOr2~0_combout  & ((\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ) # (\BCD_CONVERT|A21|WideOr3~0_combout 
+// )))))
+
+	.dataa(\BCD_CONVERT|A21|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A21|WideOr2~0_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ),
+	.datad(\BCD_CONVERT|A21|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A25|WideOr0~0 .lut_mask = 16'h666A;
+defparam \BCD_CONVERT|A25|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N22
+cycloneiii_lcell_comb \SEG1|WideOr6~0 (
+// Equation(s):
+// \SEG1|WideOr6~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & ((\BCD_CONVERT|A24|WideOr3~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr2~0_combout  $ (!\BCD_CONVERT|A25|WideOr0~0_combout )) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr6~0 .lut_mask = 16'h79BF;
+defparam \SEG1|WideOr6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N16
+cycloneiii_lcell_comb \SEG1|WideOr5~0 (
+// Equation(s):
+// \SEG1|WideOr5~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & ((\BCD_CONVERT|A25|WideOr0~0_combout  & (!\BCD_CONVERT|A24|WideOr3~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr2~0_combout ))))) # 
+// (!\BCD_CONVERT|A24|WideOr1~0_combout  & (\BCD_CONVERT|A24|WideOr2~0_combout  & (\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr5~0 .lut_mask = 16'h62B0;
+defparam \SEG1|WideOr5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N2
+cycloneiii_lcell_comb \SEG1|WideOr4~0 (
+// Equation(s):
+// \SEG1|WideOr4~0_combout  = (\BCD_CONVERT|A24|WideOr1~0_combout  & (\BCD_CONVERT|A24|WideOr2~0_combout  & ((!\BCD_CONVERT|A25|WideOr0~0_combout ) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// (!\BCD_CONVERT|A24|WideOr3~0_combout  & (!\BCD_CONVERT|A24|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr4~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr4~0 .lut_mask = 16'h20A1;
+defparam \SEG1|WideOr4~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N4
+cycloneiii_lcell_comb \SEG1|WideOr3~0 (
+// Equation(s):
+// \SEG1|WideOr3~0_combout  = (\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A24|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr3~0_combout ) # (\BCD_CONVERT|A24|WideOr2~0_combout ))) # (!\BCD_CONVERT|A24|WideOr1~0_combout  & ((!\BCD_CONVERT|A24|WideOr2~0_combout ) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr3~0 .lut_mask = 16'hC3BD;
+defparam \SEG1|WideOr3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N6
+cycloneiii_lcell_comb \SEG1|WideOr2~0 (
+// Equation(s):
+// \SEG1|WideOr2~0_combout  = (\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr2~0_combout  & (\BCD_CONVERT|A24|WideOr1~0_combout )) # (!\BCD_CONVERT|A24|WideOr2~0_combout  & ((!\BCD_CONVERT|A25|WideOr0~0_combout ))))) # 
+// (!\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout ) # ((!\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr2~0 .lut_mask = 16'hA2BF;
+defparam \SEG1|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N0
+cycloneiii_lcell_comb \SEG1|WideOr1~0 (
+// Equation(s):
+// \SEG1|WideOr1~0_combout  = (\BCD_CONVERT|A24|WideOr3~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A25|WideOr0~0_combout ))) # (!\BCD_CONVERT|A24|WideOr3~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr1~0_combout ) # ((\BCD_CONVERT|A24|WideOr2~0_combout  & !\BCD_CONVERT|A25|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr1~0 .lut_mask = 16'h6AFE;
+defparam \SEG1|WideOr1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N10
+cycloneiii_lcell_comb \SEG1|WideOr0~0 (
+// Equation(s):
+// \SEG1|WideOr0~0_combout  = (\BCD_CONVERT|A25|WideOr0~0_combout  & ((\BCD_CONVERT|A24|WideOr1~0_combout ) # (\BCD_CONVERT|A24|WideOr3~0_combout  $ (!\BCD_CONVERT|A24|WideOr2~0_combout )))) # (!\BCD_CONVERT|A25|WideOr0~0_combout  & 
+// ((\BCD_CONVERT|A24|WideOr1~0_combout  $ (\BCD_CONVERT|A24|WideOr2~0_combout )) # (!\BCD_CONVERT|A24|WideOr3~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr1~0_combout ),
+	.datab(\BCD_CONVERT|A24|WideOr3~0_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr2~0_combout ),
+	.datad(\BCD_CONVERT|A25|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG1|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG1|WideOr0~0 .lut_mask = 16'hEB7B;
+defparam \SEG1|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y28_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A24|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A24|WideOr0~0_combout  = \BCD_CONVERT|A20|WideOr1~0_combout  $ (((\BCD_CONVERT|A20|WideOr2~0_combout  & ((\BCD_CONVERT|A21|WideOr0~0_combout ) # (!\BCD_CONVERT|A20|WideOr3~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A20|WideOr2~0_combout ),
+	.datab(\BCD_CONVERT|A20|WideOr1~0_combout ),
+	.datac(\BCD_CONVERT|A21|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr3~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A24|WideOr0~0 .lut_mask = 16'h6C66;
+defparam \BCD_CONVERT|A24|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N6
+cycloneiii_lcell_comb \BCD_CONVERT|A14|WideOr0~2 (
+// Equation(s):
+// \BCD_CONVERT|A14|WideOr0~2_combout  = (\BCD_CONVERT|A7|WideOr0~0_combout ) # ((!\BCD_CONVERT|A12|WideOr0~0_combout  & ((\BCD_CONVERT|A9|WideOr0~0_combout ) # (!\BCD_CONVERT|A9|Decoder0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A9|Decoder0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A14|WideOr0~2 .lut_mask = 16'hF0FB;
+defparam \BCD_CONVERT|A14|WideOr0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y27_N4
+cycloneiii_lcell_comb \BCD_CONVERT|A17|Decoder0~7 (
+// Equation(s):
+// \BCD_CONVERT|A17|Decoder0~7_combout  = (\BCD_CONVERT|A9|WideOr0~1_combout  & (!\BCD_CONVERT|A15|WideOr0~0_combout  & (\BCD_CONVERT|A7|WideOr0~0_combout  $ (\BCD_CONVERT|A12|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A9|WideOr0~1_combout ),
+	.datab(\BCD_CONVERT|A15|WideOr0~0_combout ),
+	.datac(\BCD_CONVERT|A7|WideOr0~0_combout ),
+	.datad(\BCD_CONVERT|A12|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|Decoder0~7 .lut_mask = 16'h0220;
+defparam \BCD_CONVERT|A17|Decoder0~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N20
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr0~0_combout  = (\BCD_CONVERT|A17|Decoder0~6_combout ) # ((\BCD_CONVERT|A17|Decoder0~5_combout ) # ((\BCD_CONVERT|A17|Decoder0~4_combout ) # (\BCD_CONVERT|A17|Decoder0~3_combout )))
+
+	.dataa(\BCD_CONVERT|A17|Decoder0~6_combout ),
+	.datab(\BCD_CONVERT|A17|Decoder0~5_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~4_combout ),
+	.datad(\BCD_CONVERT|A17|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr0~0 .lut_mask = 16'hFFFE;
+defparam \BCD_CONVERT|A17|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N8
+cycloneiii_lcell_comb \BCD_CONVERT|A17|WideOr0 (
+// Equation(s):
+// \BCD_CONVERT|A17|WideOr0~combout  = (\BCD_CONVERT|A17|Decoder0~7_combout ) # (\BCD_CONVERT|A17|WideOr0~0_combout )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.datad(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A17|WideOr0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A17|WideOr0 .lut_mask = 16'hFFF0;
+defparam \BCD_CONVERT|A17|WideOr0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y27_N18
+cycloneiii_lcell_comb \BCD_CONVERT|A20|WideOr0~0 (
+// Equation(s):
+// \BCD_CONVERT|A20|WideOr0~0_combout  = \BCD_CONVERT|A17|WideOr1~0_combout  $ (((\BCD_CONVERT|A17|WideOr2~6_combout  & ((\BCD_CONVERT|A17|WideOr3~1_combout ) # (\BCD_CONVERT|A18|WideOr0~0_combout )))))
+
+	.dataa(\BCD_CONVERT|A17|WideOr2~6_combout ),
+	.datab(\BCD_CONVERT|A17|WideOr3~1_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr1~0_combout ),
+	.datad(\BCD_CONVERT|A18|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A20|WideOr0~0 .lut_mask = 16'h5A78;
+defparam \BCD_CONVERT|A20|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N10
+cycloneiii_lcell_comb \SEG2|Decoder0~0 (
+// Equation(s):
+// \SEG2|Decoder0~0_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~0 .lut_mask = 16'h0104;
+defparam \SEG2|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N20
+cycloneiii_lcell_comb \SEG2|Decoder0~1 (
+// Equation(s):
+// \SEG2|Decoder0~1_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~1 .lut_mask = 16'h2080;
+defparam \SEG2|Decoder0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N22
+cycloneiii_lcell_comb \SEG2|WideOr6 (
+// Equation(s):
+// \SEG2|WideOr6~combout  = (\SEG2|Decoder0~0_combout ) # (\SEG2|Decoder0~1_combout )
+
+	.dataa(\SEG2|Decoder0~0_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr6~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr6 .lut_mask = 16'hFFAA;
+defparam \SEG2|WideOr6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N24
+cycloneiii_lcell_comb \SEG2|Decoder0~2 (
+// Equation(s):
+// \SEG2|Decoder0~2_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~2 .lut_mask = 16'h0208;
+defparam \SEG2|Decoder0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N18
+cycloneiii_lcell_comb \SEG2|Decoder0~3 (
+// Equation(s):
+// \SEG2|Decoder0~3_combout  = (!\BCD_CONVERT|A17|WideOr0~0_combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  & (!\BCD_CONVERT|A17|Decoder0~7_combout  & \BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A17|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|Decoder0~7_combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~3 .lut_mask = 16'h0400;
+defparam \SEG2|Decoder0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N12
+cycloneiii_lcell_comb \SEG2|WideOr5 (
+// Equation(s):
+// \SEG2|WideOr5~combout  = (\SEG2|Decoder0~2_combout ) # ((!\BCD_CONVERT|A24|WideOr0~0_combout  & \SEG2|Decoder0~3_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~2_combout ),
+	.datac(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datad(\SEG2|Decoder0~3_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr5~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr5 .lut_mask = 16'hCFCC;
+defparam \SEG2|WideOr5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N6
+cycloneiii_lcell_comb \SEG2|Decoder0~4 (
+// Equation(s):
+// \SEG2|Decoder0~4_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & ((\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )) # (!\BCD_CONVERT|A14|WideOr0~2_combout  & 
+// (!\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~4 .lut_mask = 16'h4001;
+defparam \SEG2|Decoder0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N16
+cycloneiii_lcell_comb \SEG2|Decoder0~5 (
+// Equation(s):
+// \SEG2|Decoder0~5_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  & (!\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~5 .lut_mask = 16'h0800;
+defparam \SEG2|Decoder0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N26
+cycloneiii_lcell_comb \SEG2|Decoder0~6 (
+// Equation(s):
+// \SEG2|Decoder0~6_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & (!\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout )))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~6 .lut_mask = 16'h0020;
+defparam \SEG2|Decoder0~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N4
+cycloneiii_lcell_comb \SEG2|WideOr2~0 (
+// Equation(s):
+// \SEG2|WideOr2~0_combout  = (!\SEG2|Decoder0~0_combout  & (!\SEG2|Decoder0~5_combout  & (!\SEG2|Decoder0~6_combout  & !\SEG2|Decoder0~1_combout )))
+
+	.dataa(\SEG2|Decoder0~0_combout ),
+	.datab(\SEG2|Decoder0~5_combout ),
+	.datac(\SEG2|Decoder0~6_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr2~0 .lut_mask = 16'h0001;
+defparam \SEG2|WideOr2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N30
+cycloneiii_lcell_comb \SEG2|Decoder0~7 (
+// Equation(s):
+// \SEG2|Decoder0~7_combout  = (\BCD_CONVERT|A24|WideOr0~0_combout  & ((\BCD_CONVERT|A14|WideOr0~2_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & \BCD_CONVERT|A20|WideOr0~0_combout )) # (!\BCD_CONVERT|A14|WideOr0~2_combout  & 
+// (!\BCD_CONVERT|A17|WideOr0~combout  & !\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~7 .lut_mask = 16'h8002;
+defparam \SEG2|Decoder0~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N0
+cycloneiii_lcell_comb \SEG2|WideOr2 (
+// Equation(s):
+// \SEG2|WideOr2~combout  = (\SEG2|Decoder0~2_combout ) # ((\SEG2|Decoder0~7_combout ) # (!\SEG2|WideOr2~0_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~2_combout ),
+	.datac(\SEG2|Decoder0~7_combout ),
+	.datad(\SEG2|WideOr2~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr2~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr2 .lut_mask = 16'hFCFF;
+defparam \SEG2|WideOr2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N2
+cycloneiii_lcell_comb \SEG2|WideOr1 (
+// Equation(s):
+// \SEG2|WideOr1~combout  = (\SEG2|Decoder0~4_combout ) # ((\SEG2|Decoder0~5_combout ) # ((\SEG2|Decoder0~7_combout ) # (\SEG2|Decoder0~1_combout )))
+
+	.dataa(\SEG2|Decoder0~4_combout ),
+	.datab(\SEG2|Decoder0~5_combout ),
+	.datac(\SEG2|Decoder0~7_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr1~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr1 .lut_mask = 16'hFFFE;
+defparam \SEG2|WideOr1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N28
+cycloneiii_lcell_comb \SEG2|Decoder0~8 (
+// Equation(s):
+// \SEG2|Decoder0~8_combout  = (!\BCD_CONVERT|A24|WideOr0~0_combout  & (\BCD_CONVERT|A17|WideOr0~combout  & (\BCD_CONVERT|A14|WideOr0~2_combout  $ (\BCD_CONVERT|A20|WideOr0~0_combout ))))
+
+	.dataa(\BCD_CONVERT|A24|WideOr0~0_combout ),
+	.datab(\BCD_CONVERT|A14|WideOr0~2_combout ),
+	.datac(\BCD_CONVERT|A17|WideOr0~combout ),
+	.datad(\BCD_CONVERT|A20|WideOr0~0_combout ),
+	.cin(gnd),
+	.combout(\SEG2|Decoder0~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|Decoder0~8 .lut_mask = 16'h1040;
+defparam \SEG2|Decoder0~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X30_Y28_N14
+cycloneiii_lcell_comb \SEG2|WideOr0 (
+// Equation(s):
+// \SEG2|WideOr0~combout  = (\SEG2|Decoder0~8_combout ) # ((\SEG2|Decoder0~5_combout ) # (\SEG2|Decoder0~1_combout ))
+
+	.dataa(gnd),
+	.datab(\SEG2|Decoder0~8_combout ),
+	.datac(\SEG2|Decoder0~5_combout ),
+	.datad(\SEG2|Decoder0~1_combout ),
+	.cin(gnd),
+	.combout(\SEG2|WideOr0~combout ),
+	.cout());
+// synopsys translate_off
+defparam \SEG2|WideOr0 .lut_mask = 16'hFFFC;
+defparam \SEG2|WideOr0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N22
+cycloneiii_lcell_comb \BCD_CONVERT|A23|WideOr0~5 (
+// Equation(s):
+// \BCD_CONVERT|A23|WideOr0~5_combout  = (((!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout  & !\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ),
+	.datac(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~14_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~20_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A23|WideOr0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A23|WideOr0~5 .lut_mask = 16'h1FFF;
+defparam \BCD_CONVERT|A23|WideOr0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y27_N12
+cycloneiii_lcell_comb \BCD_CONVERT|A23|WideOr0~17 (
+// Equation(s):
+// \BCD_CONVERT|A23|WideOr0~17_combout  = (((\BCD_CONVERT|A23|WideOr0~5_combout ) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout )) # 
+// (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout )
+
+	.dataa(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~16_combout ),
+	.datab(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ),
+	.datac(\BCD_CONVERT|A23|WideOr0~5_combout ),
+	.datad(\SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~18_combout ),
+	.cin(gnd),
+	.combout(\BCD_CONVERT|A23|WideOr0~17_combout ),
+	.cout());
+// synopsys translate_off
+defparam \BCD_CONVERT|A23|WideOr0~17 .lut_mask = 16'hF7FF;
+defparam \BCD_CONVERT|A23|WideOr0~17 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: IOIBUF_X41_Y15_N1
+cycloneiii_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N2
+cycloneiii_lcell_comb \SPI_DAC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_DAC|clk_1MHz~0_combout  = !\SPI_DAC|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_DAC|clk_1MHz~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|clk_1MHz~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~0 .lut_mask = 16'h0F0F;
+defparam \SPI_DAC|clk_1MHz~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: CLKCTRL_G9
+cycloneiii_clkctrl \CLOCK_50~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLOCK_50~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
+defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N16
+cycloneiii_lcell_comb \SPI_ADC|Add0~0 (
+// Equation(s):
+// \SPI_ADC|Add0~0_combout  = \SPI_ADC|ctr [0] $ (VCC)
+// \SPI_ADC|Add0~1  = CARRY(\SPI_ADC|ctr [0])
+
+	.dataa(\SPI_ADC|ctr [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_ADC|Add0~0_combout ),
+	.cout(\SPI_ADC|Add0~1 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~0 .lut_mask = 16'h55AA;
+defparam \SPI_ADC|Add0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N22
+cycloneiii_lcell_comb \SPI_ADC|Add0~6 (
+// Equation(s):
+// \SPI_ADC|Add0~6_combout  = (\SPI_ADC|ctr [3] & (\SPI_ADC|Add0~5  & VCC)) # (!\SPI_ADC|ctr [3] & (!\SPI_ADC|Add0~5 ))
+// \SPI_ADC|Add0~7  = CARRY((!\SPI_ADC|ctr [3] & !\SPI_ADC|Add0~5 ))
+
+	.dataa(\SPI_ADC|ctr [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~5 ),
+	.combout(\SPI_ADC|Add0~6_combout ),
+	.cout(\SPI_ADC|Add0~7 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~6 .lut_mask = 16'hA505;
+defparam \SPI_ADC|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N24
+cycloneiii_lcell_comb \SPI_ADC|Add0~8 (
+// Equation(s):
+// \SPI_ADC|Add0~8_combout  = \SPI_ADC|Add0~7  $ (\SPI_ADC|ctr [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|ctr [4]),
+	.cin(\SPI_ADC|Add0~7 ),
+	.combout(\SPI_ADC|Add0~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Add0~8 .lut_mask = 16'h0FF0;
+defparam \SPI_ADC|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N25
+dffeas \SPI_ADC|ctr[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Add0~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N6
+cycloneiii_lcell_comb \SPI_ADC|ctr~0 (
+// Equation(s):
+// \SPI_ADC|ctr~0_combout  = (\SPI_ADC|Add0~0_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~0_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~0 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N7
+dffeas \SPI_ADC|ctr[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N18
+cycloneiii_lcell_comb \SPI_ADC|Add0~2 (
+// Equation(s):
+// \SPI_ADC|Add0~2_combout  = (\SPI_ADC|ctr [1] & (\SPI_ADC|Add0~1  & VCC)) # (!\SPI_ADC|ctr [1] & (!\SPI_ADC|Add0~1 ))
+// \SPI_ADC|Add0~3  = CARRY((!\SPI_ADC|ctr [1] & !\SPI_ADC|Add0~1 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|ctr [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~1 ),
+	.combout(\SPI_ADC|Add0~2_combout ),
+	.cout(\SPI_ADC|Add0~3 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~2 .lut_mask = 16'hC303;
+defparam \SPI_ADC|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N4
+cycloneiii_lcell_comb \SPI_ADC|ctr~1 (
+// Equation(s):
+// \SPI_ADC|ctr~1_combout  = (\SPI_ADC|Add0~2_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~2_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~1 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N5
+dffeas \SPI_ADC|ctr[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N20
+cycloneiii_lcell_comb \SPI_ADC|Add0~4 (
+// Equation(s):
+// \SPI_ADC|Add0~4_combout  = (\SPI_ADC|ctr [2] & ((GND) # (!\SPI_ADC|Add0~3 ))) # (!\SPI_ADC|ctr [2] & (\SPI_ADC|Add0~3  $ (GND)))
+// \SPI_ADC|Add0~5  = CARRY((\SPI_ADC|ctr [2]) # (!\SPI_ADC|Add0~3 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add0~3 ),
+	.combout(\SPI_ADC|Add0~4_combout ),
+	.cout(\SPI_ADC|Add0~5 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add0~4 .lut_mask = 16'h3CCF;
+defparam \SPI_ADC|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N28
+cycloneiii_lcell_comb \SPI_ADC|ctr~2 (
+// Equation(s):
+// \SPI_ADC|ctr~2_combout  = (\SPI_ADC|Add0~4_combout  & ((\SPI_ADC|ctr [4]) # (!\SPI_DAC|Equal0~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Add0~4_combout ),
+	.datac(\SPI_ADC|ctr [4]),
+	.datad(\SPI_DAC|Equal0~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|ctr~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|ctr~2 .lut_mask = 16'hC0CC;
+defparam \SPI_ADC|ctr~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N29
+dffeas \SPI_ADC|ctr[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N23
+dffeas \SPI_ADC|ctr[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Add0~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|ctr[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N0
+cycloneiii_lcell_comb \SPI_DAC|Equal0~0 (
+// Equation(s):
+// \SPI_DAC|Equal0~0_combout  = (!\SPI_ADC|ctr [3] & (!\SPI_ADC|ctr [2] & (!\SPI_ADC|ctr [1] & !\SPI_ADC|ctr [0])))
+
+	.dataa(\SPI_ADC|ctr [3]),
+	.datab(\SPI_ADC|ctr [2]),
+	.datac(\SPI_ADC|ctr [1]),
+	.datad(\SPI_ADC|ctr [0]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal0~0 .lut_mask = 16'h0001;
+defparam \SPI_DAC|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N26
+cycloneiii_lcell_comb \SPI_DAC|Equal0~1 (
+// Equation(s):
+// \SPI_DAC|Equal0~1_combout  = (\SPI_DAC|Equal0~0_combout  & !\SPI_ADC|ctr [4])
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|Equal0~0_combout ),
+	.datac(gnd),
+	.datad(\SPI_ADC|ctr [4]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal0~1 .lut_mask = 16'h00CC;
+defparam \SPI_DAC|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N3
+dffeas \SPI_DAC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\SPI_DAC|clk_1MHz~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_DAC|Equal0~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_DAC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G11
+cycloneiii_clkctrl \SPI_DAC|clk_1MHz~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_DAC|clk_1MHz~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_DAC|clk_1MHz~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_DAC|clk_1MHz~clkctrl .clock_type = "global clock";
+defparam \SPI_DAC|clk_1MHz~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N0
+cycloneiii_lcell_comb \PWM_DC|count[0]~27 (
+// Equation(s):
+// \PWM_DC|count[0]~27_combout  = !\PWM_DC|count [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\PWM_DC|count [0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\PWM_DC|count[0]~27_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|count[0]~27 .lut_mask = 16'h0F0F;
+defparam \PWM_DC|count[0]~27 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N1
+dffeas \PWM_DC|count[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[0]~27_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[0] .is_wysiwyg = "true";
+defparam \PWM_DC|count[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N2
+cycloneiii_lcell_comb \GEN_10K|Add0~22 (
+// Equation(s):
+// \GEN_10K|Add0~22_combout  = (\GEN_10K|ctr [11] & (\GEN_10K|Add0~21  & VCC)) # (!\GEN_10K|ctr [11] & (!\GEN_10K|Add0~21 ))
+// \GEN_10K|Add0~23  = CARRY((!\GEN_10K|ctr [11] & !\GEN_10K|Add0~21 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~21 ),
+	.combout(\GEN_10K|Add0~22_combout ),
+	.cout(\GEN_10K|Add0~23 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~22 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N4
+cycloneiii_lcell_comb \GEN_10K|Add0~24 (
+// Equation(s):
+// \GEN_10K|Add0~24_combout  = (\GEN_10K|ctr [12] & ((GND) # (!\GEN_10K|Add0~23 ))) # (!\GEN_10K|ctr [12] & (\GEN_10K|Add0~23  $ (GND)))
+// \GEN_10K|Add0~25  = CARRY((\GEN_10K|ctr [12]) # (!\GEN_10K|Add0~23 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~23 ),
+	.combout(\GEN_10K|Add0~24_combout ),
+	.cout(\GEN_10K|Add0~25 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~24 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N24
+cycloneiii_lcell_comb \GEN_10K|ctr~6 (
+// Equation(s):
+// \GEN_10K|ctr~6_combout  = (\GEN_10K|Add0~24_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Equal0~5_combout ),
+	.datab(\GEN_10K|Equal0~4_combout ),
+	.datac(\GEN_10K|Add0~24_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~6 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N25
+dffeas \GEN_10K|ctr[12] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[12] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N6
+cycloneiii_lcell_comb \GEN_10K|Add0~26 (
+// Equation(s):
+// \GEN_10K|Add0~26_combout  = (\GEN_10K|ctr [13] & (\GEN_10K|Add0~25  & VCC)) # (!\GEN_10K|ctr [13] & (!\GEN_10K|Add0~25 ))
+// \GEN_10K|Add0~27  = CARRY((!\GEN_10K|ctr [13] & !\GEN_10K|Add0~25 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [13]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~25 ),
+	.combout(\GEN_10K|Add0~26_combout ),
+	.cout(\GEN_10K|Add0~27 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~26 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N8
+cycloneiii_lcell_comb \GEN_10K|ctr~7 (
+// Equation(s):
+// \GEN_10K|ctr~7_combout  = (\GEN_10K|Add0~26_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~26_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~7 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N9
+dffeas \GEN_10K|ctr[13] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[13] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N8
+cycloneiii_lcell_comb \GEN_10K|Add0~28 (
+// Equation(s):
+// \GEN_10K|Add0~28_combout  = (\GEN_10K|ctr [14] & ((GND) # (!\GEN_10K|Add0~27 ))) # (!\GEN_10K|ctr [14] & (\GEN_10K|Add0~27  $ (GND)))
+// \GEN_10K|Add0~29  = CARRY((\GEN_10K|ctr [14]) # (!\GEN_10K|Add0~27 ))
+
+	.dataa(\GEN_10K|ctr [14]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~27 ),
+	.combout(\GEN_10K|Add0~28_combout ),
+	.cout(\GEN_10K|Add0~29 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~28 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N2
+cycloneiii_lcell_comb \GEN_10K|ctr~8 (
+// Equation(s):
+// \GEN_10K|ctr~8_combout  = (\GEN_10K|Add0~28_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~28_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~8 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N3
+dffeas \GEN_10K|ctr[14] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[14] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N10
+cycloneiii_lcell_comb \GEN_10K|Add0~30 (
+// Equation(s):
+// \GEN_10K|Add0~30_combout  = (\GEN_10K|ctr [15] & (\GEN_10K|Add0~29  & VCC)) # (!\GEN_10K|ctr [15] & (!\GEN_10K|Add0~29 ))
+// \GEN_10K|Add0~31  = CARRY((!\GEN_10K|ctr [15] & !\GEN_10K|Add0~29 ))
+
+	.dataa(\GEN_10K|ctr [15]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~29 ),
+	.combout(\GEN_10K|Add0~30_combout ),
+	.cout(\GEN_10K|Add0~31 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~30 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N20
+cycloneiii_lcell_comb \GEN_10K|ctr~9 (
+// Equation(s):
+// \GEN_10K|ctr~9_combout  = (\GEN_10K|Add0~30_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~30_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~9 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N21
+dffeas \GEN_10K|ctr[15] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[15] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N12
+cycloneiii_lcell_comb \GEN_10K|Add0~32 (
+// Equation(s):
+// \GEN_10K|Add0~32_combout  = (\GEN_10K|ctr [16] & ((GND) # (!\GEN_10K|Add0~31 ))) # (!\GEN_10K|ctr [16] & (\GEN_10K|Add0~31  $ (GND)))
+// \GEN_10K|Add0~33  = CARRY((\GEN_10K|ctr [16]) # (!\GEN_10K|Add0~31 ))
+
+	.dataa(\GEN_10K|ctr [16]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~31 ),
+	.combout(\GEN_10K|Add0~32_combout ),
+	.cout(\GEN_10K|Add0~33 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~32 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N6
+cycloneiii_lcell_comb \GEN_10K|ctr~10 (
+// Equation(s):
+// \GEN_10K|ctr~10_combout  = (\GEN_10K|Add0~32_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~32_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~10 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N7
+dffeas \GEN_10K|ctr[16] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[16] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N14
+cycloneiii_lcell_comb \GEN_10K|Add0~34 (
+// Equation(s):
+// \GEN_10K|Add0~34_combout  = (\GEN_10K|ctr [17] & (\GEN_10K|Add0~33  & VCC)) # (!\GEN_10K|ctr [17] & (!\GEN_10K|Add0~33 ))
+// \GEN_10K|Add0~35  = CARRY((!\GEN_10K|ctr [17] & !\GEN_10K|Add0~33 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [17]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~33 ),
+	.combout(\GEN_10K|Add0~34_combout ),
+	.cout(\GEN_10K|Add0~35 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~34 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N18
+cycloneiii_lcell_comb \GEN_10K|ctr~11 (
+// Equation(s):
+// \GEN_10K|ctr~11_combout  = (\GEN_10K|Add0~34_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~34_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Equal0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~11 .lut_mask = 16'hAA2A;
+defparam \GEN_10K|ctr~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N19
+dffeas \GEN_10K|ctr[17] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[17] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N16
+cycloneiii_lcell_comb \GEN_10K|Add0~36 (
+// Equation(s):
+// \GEN_10K|Add0~36_combout  = (\GEN_10K|ctr [18] & ((GND) # (!\GEN_10K|Add0~35 ))) # (!\GEN_10K|ctr [18] & (\GEN_10K|Add0~35  $ (GND)))
+// \GEN_10K|Add0~37  = CARRY((\GEN_10K|ctr [18]) # (!\GEN_10K|Add0~35 ))
+
+	.dataa(\GEN_10K|ctr [18]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~35 ),
+	.combout(\GEN_10K|Add0~36_combout ),
+	.cout(\GEN_10K|Add0~37 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~36 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~36 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N4
+cycloneiii_lcell_comb \GEN_10K|ctr~12 (
+// Equation(s):
+// \GEN_10K|ctr~12_combout  = (\GEN_10K|Add0~36_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~36_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~12 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N5
+dffeas \GEN_10K|ctr[18] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[18] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N18
+cycloneiii_lcell_comb \GEN_10K|Add0~38 (
+// Equation(s):
+// \GEN_10K|Add0~38_combout  = (\GEN_10K|ctr [19] & (\GEN_10K|Add0~37  & VCC)) # (!\GEN_10K|ctr [19] & (!\GEN_10K|Add0~37 ))
+// \GEN_10K|Add0~39  = CARRY((!\GEN_10K|ctr [19] & !\GEN_10K|Add0~37 ))
+
+	.dataa(\GEN_10K|ctr [19]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~37 ),
+	.combout(\GEN_10K|Add0~38_combout ),
+	.cout(\GEN_10K|Add0~39 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~38 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~38 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N26
+cycloneiii_lcell_comb \GEN_10K|ctr~13 (
+// Equation(s):
+// \GEN_10K|ctr~13_combout  = (\GEN_10K|Add0~38_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~38_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~13 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N27
+dffeas \GEN_10K|ctr[19] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[19] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N20
+cycloneiii_lcell_comb \GEN_10K|Add0~40 (
+// Equation(s):
+// \GEN_10K|Add0~40_combout  = \GEN_10K|Add0~39  $ (\GEN_10K|ctr [20])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\GEN_10K|ctr [20]),
+	.cin(\GEN_10K|Add0~39 ),
+	.combout(\GEN_10K|Add0~40_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Add0~40 .lut_mask = 16'h0FF0;
+defparam \GEN_10K|Add0~40 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N28
+cycloneiii_lcell_comb \GEN_10K|ctr~14 (
+// Equation(s):
+// \GEN_10K|ctr~14_combout  = (\GEN_10K|Add0~40_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~40_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~14_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~14 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~14 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N29
+dffeas \GEN_10K|ctr[20] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[20] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N30
+cycloneiii_lcell_comb \GEN_10K|Equal0~5 (
+// Equation(s):
+// \GEN_10K|Equal0~5_combout  = (!\GEN_10K|ctr [18] & (!\GEN_10K|ctr [20] & (!\GEN_10K|ctr [19] & !\GEN_10K|ctr [17])))
+
+	.dataa(\GEN_10K|ctr [18]),
+	.datab(\GEN_10K|ctr [20]),
+	.datac(\GEN_10K|ctr [19]),
+	.datad(\GEN_10K|ctr [17]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~5 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N12
+cycloneiii_lcell_comb \GEN_10K|Add0~1 (
+// Equation(s):
+// \GEN_10K|Add0~1_cout  = CARRY(\PWM_DC|count [0])
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\GEN_10K|Add0~1_cout ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~1 .lut_mask = 16'h00AA;
+defparam \GEN_10K|Add0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N14
+cycloneiii_lcell_comb \GEN_10K|Add0~2 (
+// Equation(s):
+// \GEN_10K|Add0~2_combout  = (\GEN_10K|ctr [1] & (\GEN_10K|Add0~1_cout  & VCC)) # (!\GEN_10K|ctr [1] & (!\GEN_10K|Add0~1_cout ))
+// \GEN_10K|Add0~3  = CARRY((!\GEN_10K|ctr [1] & !\GEN_10K|Add0~1_cout ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~1_cout ),
+	.combout(\GEN_10K|Add0~2_combout ),
+	.cout(\GEN_10K|Add0~3 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~2 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N15
+dffeas \GEN_10K|ctr[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[1] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N16
+cycloneiii_lcell_comb \GEN_10K|Add0~4 (
+// Equation(s):
+// \GEN_10K|Add0~4_combout  = (\GEN_10K|ctr [2] & ((GND) # (!\GEN_10K|Add0~3 ))) # (!\GEN_10K|ctr [2] & (\GEN_10K|Add0~3  $ (GND)))
+// \GEN_10K|Add0~5  = CARRY((\GEN_10K|ctr [2]) # (!\GEN_10K|Add0~3 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~3 ),
+	.combout(\GEN_10K|Add0~4_combout ),
+	.cout(\GEN_10K|Add0~5 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~4 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N10
+cycloneiii_lcell_comb \GEN_10K|ctr~0 (
+// Equation(s):
+// \GEN_10K|ctr~0_combout  = (\GEN_10K|Add0~4_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~4_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~0 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N11
+dffeas \GEN_10K|ctr[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[2] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N18
+cycloneiii_lcell_comb \GEN_10K|Add0~6 (
+// Equation(s):
+// \GEN_10K|Add0~6_combout  = (\GEN_10K|ctr [3] & (\GEN_10K|Add0~5  & VCC)) # (!\GEN_10K|ctr [3] & (!\GEN_10K|Add0~5 ))
+// \GEN_10K|Add0~7  = CARRY((!\GEN_10K|ctr [3] & !\GEN_10K|Add0~5 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~5 ),
+	.combout(\GEN_10K|Add0~6_combout ),
+	.cout(\GEN_10K|Add0~7 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~6 .lut_mask = 16'hC303;
+defparam \GEN_10K|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N0
+cycloneiii_lcell_comb \GEN_10K|ctr~1 (
+// Equation(s):
+// \GEN_10K|ctr~1_combout  = (\GEN_10K|Add0~6_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\PWM_DC|count [0]),
+	.datad(\GEN_10K|Add0~6_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~1 .lut_mask = 16'hF700;
+defparam \GEN_10K|ctr~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N1
+dffeas \GEN_10K|ctr[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[3] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N20
+cycloneiii_lcell_comb \GEN_10K|Add0~8 (
+// Equation(s):
+// \GEN_10K|Add0~8_combout  = (\GEN_10K|ctr [4] & ((GND) # (!\GEN_10K|Add0~7 ))) # (!\GEN_10K|ctr [4] & (\GEN_10K|Add0~7  $ (GND)))
+// \GEN_10K|Add0~9  = CARRY((\GEN_10K|ctr [4]) # (!\GEN_10K|Add0~7 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~7 ),
+	.combout(\GEN_10K|Add0~8_combout ),
+	.cout(\GEN_10K|Add0~9 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~8 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N12
+cycloneiii_lcell_comb \GEN_10K|ctr~2 (
+// Equation(s):
+// \GEN_10K|ctr~2_combout  = (\GEN_10K|Add0~8_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~8_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~2 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N13
+dffeas \GEN_10K|ctr[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[4] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N22
+cycloneiii_lcell_comb \GEN_10K|Add0~10 (
+// Equation(s):
+// \GEN_10K|Add0~10_combout  = (\GEN_10K|ctr [5] & (\GEN_10K|Add0~9  & VCC)) # (!\GEN_10K|ctr [5] & (!\GEN_10K|Add0~9 ))
+// \GEN_10K|Add0~11  = CARRY((!\GEN_10K|ctr [5] & !\GEN_10K|Add0~9 ))
+
+	.dataa(\GEN_10K|ctr [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~9 ),
+	.combout(\GEN_10K|Add0~10_combout ),
+	.cout(\GEN_10K|Add0~11 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~10 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N14
+cycloneiii_lcell_comb \GEN_10K|ctr~3 (
+// Equation(s):
+// \GEN_10K|ctr~3_combout  = (\GEN_10K|Add0~10_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~5_combout )) # (!\GEN_10K|Equal0~4_combout )))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|Add0~10_combout ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~3 .lut_mask = 16'hF070;
+defparam \GEN_10K|ctr~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N15
+dffeas \GEN_10K|ctr[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[5] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N24
+cycloneiii_lcell_comb \GEN_10K|Add0~12 (
+// Equation(s):
+// \GEN_10K|Add0~12_combout  = (\GEN_10K|ctr [6] & ((GND) # (!\GEN_10K|Add0~11 ))) # (!\GEN_10K|ctr [6] & (\GEN_10K|Add0~11  $ (GND)))
+// \GEN_10K|Add0~13  = CARRY((\GEN_10K|ctr [6]) # (!\GEN_10K|Add0~11 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~11 ),
+	.combout(\GEN_10K|Add0~12_combout ),
+	.cout(\GEN_10K|Add0~13 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~12 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N25
+dffeas \GEN_10K|ctr[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[6] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N26
+cycloneiii_lcell_comb \GEN_10K|Add0~14 (
+// Equation(s):
+// \GEN_10K|Add0~14_combout  = (\GEN_10K|ctr [7] & (\GEN_10K|Add0~13  & VCC)) # (!\GEN_10K|ctr [7] & (!\GEN_10K|Add0~13 ))
+// \GEN_10K|Add0~15  = CARRY((!\GEN_10K|ctr [7] & !\GEN_10K|Add0~13 ))
+
+	.dataa(\GEN_10K|ctr [7]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~13 ),
+	.combout(\GEN_10K|Add0~14_combout ),
+	.cout(\GEN_10K|Add0~15 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~14 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N27
+dffeas \GEN_10K|ctr[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[7] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N28
+cycloneiii_lcell_comb \GEN_10K|Add0~16 (
+// Equation(s):
+// \GEN_10K|Add0~16_combout  = (\GEN_10K|ctr [8] & ((GND) # (!\GEN_10K|Add0~15 ))) # (!\GEN_10K|ctr [8] & (\GEN_10K|Add0~15  $ (GND)))
+// \GEN_10K|Add0~17  = CARRY((\GEN_10K|ctr [8]) # (!\GEN_10K|Add0~15 ))
+
+	.dataa(gnd),
+	.datab(\GEN_10K|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~15 ),
+	.combout(\GEN_10K|Add0~16_combout ),
+	.cout(\GEN_10K|Add0~17 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~16 .lut_mask = 16'h3CCF;
+defparam \GEN_10K|Add0~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N29
+dffeas \GEN_10K|ctr[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~16_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[8] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N30
+cycloneiii_lcell_comb \GEN_10K|Add0~18 (
+// Equation(s):
+// \GEN_10K|Add0~18_combout  = (\GEN_10K|ctr [9] & (\GEN_10K|Add0~17  & VCC)) # (!\GEN_10K|ctr [9] & (!\GEN_10K|Add0~17 ))
+// \GEN_10K|Add0~19  = CARRY((!\GEN_10K|ctr [9] & !\GEN_10K|Add0~17 ))
+
+	.dataa(\GEN_10K|ctr [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~17 ),
+	.combout(\GEN_10K|Add0~18_combout ),
+	.cout(\GEN_10K|Add0~19 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~18 .lut_mask = 16'hA505;
+defparam \GEN_10K|Add0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N6
+cycloneiii_lcell_comb \GEN_10K|ctr~4 (
+// Equation(s):
+// \GEN_10K|ctr~4_combout  = (\GEN_10K|Add0~18_combout  & (((\PWM_DC|count [0]) # (!\GEN_10K|Equal0~4_combout )) # (!\GEN_10K|Equal0~5_combout )))
+
+	.dataa(\GEN_10K|Add0~18_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\PWM_DC|count [0]),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~4 .lut_mask = 16'hA2AA;
+defparam \GEN_10K|ctr~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y23_N7
+dffeas \GEN_10K|ctr[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[9] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N0
+cycloneiii_lcell_comb \GEN_10K|Add0~20 (
+// Equation(s):
+// \GEN_10K|Add0~20_combout  = (\GEN_10K|ctr [10] & ((GND) # (!\GEN_10K|Add0~19 ))) # (!\GEN_10K|ctr [10] & (\GEN_10K|Add0~19  $ (GND)))
+// \GEN_10K|Add0~21  = CARRY((\GEN_10K|ctr [10]) # (!\GEN_10K|Add0~19 ))
+
+	.dataa(\GEN_10K|ctr [10]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\GEN_10K|Add0~19 ),
+	.combout(\GEN_10K|Add0~20_combout ),
+	.cout(\GEN_10K|Add0~21 ));
+// synopsys translate_off
+defparam \GEN_10K|Add0~20 .lut_mask = 16'h5AAF;
+defparam \GEN_10K|Add0~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y22_N22
+cycloneiii_lcell_comb \GEN_10K|ctr~5 (
+// Equation(s):
+// \GEN_10K|ctr~5_combout  = (\GEN_10K|Add0~20_combout  & ((\PWM_DC|count [0]) # ((!\GEN_10K|Equal0~4_combout ) # (!\GEN_10K|Equal0~5_combout ))))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\GEN_10K|Add0~20_combout ),
+	.datac(\GEN_10K|Equal0~5_combout ),
+	.datad(\GEN_10K|Equal0~4_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|ctr~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|ctr~5 .lut_mask = 16'h8CCC;
+defparam \GEN_10K|ctr~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N23
+dffeas \GEN_10K|ctr[10] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|ctr~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[10] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X19_Y22_N3
+dffeas \GEN_10K|ctr[11] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|Add0~22_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|ctr [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|ctr[11] .is_wysiwyg = "true";
+defparam \GEN_10K|ctr[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N8
+cycloneiii_lcell_comb \GEN_10K|Equal0~2 (
+// Equation(s):
+// \GEN_10K|Equal0~2_combout  = (!\GEN_10K|ctr [11] & (!\GEN_10K|ctr [10] & (!\GEN_10K|ctr [12] & !\GEN_10K|ctr [9])))
+
+	.dataa(\GEN_10K|ctr [11]),
+	.datab(\GEN_10K|ctr [10]),
+	.datac(\GEN_10K|ctr [12]),
+	.datad(\GEN_10K|ctr [9]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~2 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N2
+cycloneiii_lcell_comb \GEN_10K|Equal0~0 (
+// Equation(s):
+// \GEN_10K|Equal0~0_combout  = (!\GEN_10K|ctr [1] & (!\GEN_10K|ctr [2] & (!\GEN_10K|ctr [4] & !\GEN_10K|ctr [3])))
+
+	.dataa(\GEN_10K|ctr [1]),
+	.datab(\GEN_10K|ctr [2]),
+	.datac(\GEN_10K|ctr [4]),
+	.datad(\GEN_10K|ctr [3]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~0 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N4
+cycloneiii_lcell_comb \GEN_10K|Equal0~1 (
+// Equation(s):
+// \GEN_10K|Equal0~1_combout  = (!\GEN_10K|ctr [5] & (!\GEN_10K|ctr [6] & (!\GEN_10K|ctr [7] & !\GEN_10K|ctr [8])))
+
+	.dataa(\GEN_10K|ctr [5]),
+	.datab(\GEN_10K|ctr [6]),
+	.datac(\GEN_10K|ctr [7]),
+	.datad(\GEN_10K|ctr [8]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~1 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N16
+cycloneiii_lcell_comb \GEN_10K|Equal0~3 (
+// Equation(s):
+// \GEN_10K|Equal0~3_combout  = (!\GEN_10K|ctr [16] & (!\GEN_10K|ctr [14] & (!\GEN_10K|ctr [13] & !\GEN_10K|ctr [15])))
+
+	.dataa(\GEN_10K|ctr [16]),
+	.datab(\GEN_10K|ctr [14]),
+	.datac(\GEN_10K|ctr [13]),
+	.datad(\GEN_10K|ctr [15]),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~3 .lut_mask = 16'h0001;
+defparam \GEN_10K|Equal0~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y23_N10
+cycloneiii_lcell_comb \GEN_10K|Equal0~4 (
+// Equation(s):
+// \GEN_10K|Equal0~4_combout  = (\GEN_10K|Equal0~2_combout  & (\GEN_10K|Equal0~0_combout  & (\GEN_10K|Equal0~1_combout  & \GEN_10K|Equal0~3_combout )))
+
+	.dataa(\GEN_10K|Equal0~2_combout ),
+	.datab(\GEN_10K|Equal0~0_combout ),
+	.datac(\GEN_10K|Equal0~1_combout ),
+	.datad(\GEN_10K|Equal0~3_combout ),
+	.cin(gnd),
+	.combout(\GEN_10K|Equal0~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|Equal0~4 .lut_mask = 16'h8000;
+defparam \GEN_10K|Equal0~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N28
+cycloneiii_lcell_comb \GEN_10K|clkout~0 (
+// Equation(s):
+// \GEN_10K|clkout~0_combout  = \GEN_10K|clkout~q  $ (((\GEN_10K|Equal0~4_combout  & (\GEN_10K|Equal0~5_combout  & !\PWM_DC|count [0]))))
+
+	.dataa(\GEN_10K|Equal0~4_combout ),
+	.datab(\GEN_10K|Equal0~5_combout ),
+	.datac(\GEN_10K|clkout~q ),
+	.datad(\PWM_DC|count [0]),
+	.cin(gnd),
+	.combout(\GEN_10K|clkout~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \GEN_10K|clkout~0 .lut_mask = 16'hF078;
+defparam \GEN_10K|clkout~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N29
+dffeas \GEN_10K|clkout (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\GEN_10K|clkout~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\GEN_10K|clkout~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \GEN_10K|clkout .is_wysiwyg = "true";
+defparam \GEN_10K|clkout .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N22
+cycloneiii_lcell_comb \PULSE|state.IDLE~feeder (
+// Equation(s):
+// \PULSE|state.IDLE~feeder_combout  = \GEN_10K|clkout~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\GEN_10K|clkout~q ),
+	.cin(gnd),
+	.combout(\PULSE|state.IDLE~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PULSE|state.IDLE~feeder .lut_mask = 16'hFF00;
+defparam \PULSE|state.IDLE~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N23
+dffeas \PULSE|state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PULSE|state.IDLE~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PULSE|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PULSE|state.IDLE .is_wysiwyg = "true";
+defparam \PULSE|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N0
+cycloneiii_lcell_comb \PULSE|pulse~1 (
+// Equation(s):
+// \PULSE|pulse~1_combout  = (!\PULSE|state.IDLE~q  & \GEN_10K|clkout~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\PULSE|state.IDLE~q ),
+	.datad(\GEN_10K|clkout~q ),
+	.cin(gnd),
+	.combout(\PULSE|pulse~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PULSE|pulse~1 .lut_mask = 16'h0F00;
+defparam \PULSE|pulse~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N1
+dffeas \PULSE|pulse (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PULSE|pulse~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PULSE|pulse~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PULSE|pulse .is_wysiwyg = "true";
+defparam \PULSE|pulse .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N0
+cycloneiii_lcell_comb \SPI_DAC|Selector2~0 (
+// Equation(s):
+// \SPI_DAC|Selector2~0_combout  = (\SPI_DAC|dac_cs~q  & \SPI_DAC|sr_state.IDLE~q )
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector2~0 .lut_mask = 16'hAA00;
+defparam \SPI_DAC|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N1
+dffeas \SPI_DAC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N2
+cycloneiii_lcell_comb \SPI_DAC|Selector0~0 (
+// Equation(s):
+// \SPI_DAC|Selector0~0_combout  = (\SPI_DAC|dac_cs~q  & ((\PULSE|pulse~q ) # ((\SPI_DAC|sr_state.IDLE~q )))) # (!\SPI_DAC|dac_cs~q  & (!\SPI_DAC|sr_state.WAIT_CSB_HIGH~q  & ((\PULSE|pulse~q ) # (\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|sr_state.IDLE~q ),
+	.datad(\SPI_DAC|sr_state.WAIT_CSB_HIGH~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector0~0 .lut_mask = 16'hA8FC;
+defparam \SPI_DAC|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N3
+dffeas \SPI_DAC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N24
+cycloneiii_lcell_comb \SPI_DAC|Selector1~0 (
+// Equation(s):
+// \SPI_DAC|Selector1~0_combout  = (\SPI_DAC|dac_cs~q  & (\PULSE|pulse~q  & ((!\SPI_DAC|sr_state.IDLE~q )))) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|sr_state.WAIT_CSB_FALL~q ) # ((\PULSE|pulse~q  & !\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector1~0 .lut_mask = 16'h50DC;
+defparam \SPI_DAC|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N25
+dffeas \SPI_DAC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_DAC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N4
+cycloneiii_lcell_comb \SPI_DAC|dac_start~0 (
+// Equation(s):
+// \SPI_DAC|dac_start~0_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q ) # ((\SPI_DAC|sr_state.WAIT_CSB_FALL~q ) # (!\SPI_DAC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|sr_state.IDLE~q ),
+	.datac(\SPI_DAC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|dac_start~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_start~0 .lut_mask = 16'hFB00;
+defparam \SPI_DAC|dac_start~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N20
+cycloneiii_lcell_comb \SPI_DAC|dac_start~1 (
+// Equation(s):
+// \SPI_DAC|dac_start~1_combout  = (\SPI_DAC|dac_start~0_combout ) # ((\PULSE|pulse~q  & !\SPI_DAC|sr_state.IDLE~q ))
+
+	.dataa(gnd),
+	.datab(\PULSE|pulse~q ),
+	.datac(\SPI_DAC|dac_start~0_combout ),
+	.datad(\SPI_DAC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|dac_start~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|dac_start~1 .lut_mask = 16'hF0FC;
+defparam \SPI_DAC|dac_start~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N21
+dffeas \SPI_DAC|dac_start (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_DAC|dac_start~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_start .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N0
+cycloneiii_lcell_comb \SPI_DAC|state[0]~5 (
+// Equation(s):
+// \SPI_DAC|state[0]~5_combout  = \SPI_DAC|state [0] $ (VCC)
+// \SPI_DAC|state[0]~6  = CARRY(\SPI_DAC|state [0])
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_DAC|state[0]~5_combout ),
+	.cout(\SPI_DAC|state[0]~6 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[0]~5 .lut_mask = 16'h33CC;
+defparam \SPI_DAC|state[0]~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N6
+cycloneiii_lcell_comb \SPI_DAC|state[3]~11 (
+// Equation(s):
+// \SPI_DAC|state[3]~11_combout  = (\SPI_DAC|state [3] & (!\SPI_DAC|state[2]~10 )) # (!\SPI_DAC|state [3] & ((\SPI_DAC|state[2]~10 ) # (GND)))
+// \SPI_DAC|state[3]~12  = CARRY((!\SPI_DAC|state[2]~10 ) # (!\SPI_DAC|state [3]))
+
+	.dataa(\SPI_DAC|state [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[2]~10 ),
+	.combout(\SPI_DAC|state[3]~11_combout ),
+	.cout(\SPI_DAC|state[3]~12 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[3]~11 .lut_mask = 16'h5A5F;
+defparam \SPI_DAC|state[3]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N8
+cycloneiii_lcell_comb \SPI_DAC|state[4]~13 (
+// Equation(s):
+// \SPI_DAC|state[4]~13_combout  = \SPI_DAC|state [4] $ (!\SPI_DAC|state[3]~12 )
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [4]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\SPI_DAC|state[3]~12 ),
+	.combout(\SPI_DAC|state[4]~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|state[4]~13 .lut_mask = 16'hC3C3;
+defparam \SPI_DAC|state[4]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N9
+dffeas \SPI_DAC|state[4] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[4]~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N24
+cycloneiii_lcell_comb \SPI_DAC|Selector8~0 (
+// Equation(s):
+// \SPI_DAC|Selector8~0_combout  = (\SPI_DAC|Equal1~0_combout  & ((\SPI_DAC|state [4]) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_start~q ),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector8~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector8~0 .lut_mask = 16'hC4C4;
+defparam \SPI_DAC|Selector8~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N1
+dffeas \SPI_DAC|state[0] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[0]~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[0] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N2
+cycloneiii_lcell_comb \SPI_DAC|state[1]~7 (
+// Equation(s):
+// \SPI_DAC|state[1]~7_combout  = (\SPI_DAC|state [1] & (!\SPI_DAC|state[0]~6 )) # (!\SPI_DAC|state [1] & ((\SPI_DAC|state[0]~6 ) # (GND)))
+// \SPI_DAC|state[1]~8  = CARRY((!\SPI_DAC|state[0]~6 ) # (!\SPI_DAC|state [1]))
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[0]~6 ),
+	.combout(\SPI_DAC|state[1]~7_combout ),
+	.cout(\SPI_DAC|state[1]~8 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[1]~7 .lut_mask = 16'h3C3F;
+defparam \SPI_DAC|state[1]~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N3
+dffeas \SPI_DAC|state[1] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[1]~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[1] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N4
+cycloneiii_lcell_comb \SPI_DAC|state[2]~9 (
+// Equation(s):
+// \SPI_DAC|state[2]~9_combout  = (\SPI_DAC|state [2] & (\SPI_DAC|state[1]~8  $ (GND))) # (!\SPI_DAC|state [2] & (!\SPI_DAC|state[1]~8  & VCC))
+// \SPI_DAC|state[2]~10  = CARRY((\SPI_DAC|state [2] & !\SPI_DAC|state[1]~8 ))
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|state [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_DAC|state[1]~8 ),
+	.combout(\SPI_DAC|state[2]~9_combout ),
+	.cout(\SPI_DAC|state[2]~10 ));
+// synopsys translate_off
+defparam \SPI_DAC|state[2]~9 .lut_mask = 16'hC30C;
+defparam \SPI_DAC|state[2]~9 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N5
+dffeas \SPI_DAC|state[2] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[2]~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N7
+dffeas \SPI_DAC|state[3] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|state[3]~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(\SPI_DAC|Selector8~0_combout ),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|state[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N14
+cycloneiii_lcell_comb \SPI_DAC|Equal1~0 (
+// Equation(s):
+// \SPI_DAC|Equal1~0_combout  = (!\SPI_DAC|state [3] & (!\SPI_DAC|state [1] & (!\SPI_DAC|state [2] & !\SPI_DAC|state [0])))
+
+	.dataa(\SPI_DAC|state [3]),
+	.datab(\SPI_DAC|state [1]),
+	.datac(\SPI_DAC|state [2]),
+	.datad(\SPI_DAC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal1~0 .lut_mask = 16'h0001;
+defparam \SPI_DAC|Equal1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N10
+cycloneiii_lcell_comb \SPI_DAC|Selector9~0 (
+// Equation(s):
+// \SPI_DAC|Selector9~0_combout  = ((\SPI_DAC|dac_start~q  & !\SPI_DAC|state [4])) # (!\SPI_DAC|Equal1~0_combout )
+
+	.dataa(\SPI_DAC|dac_start~q ),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Selector9~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Selector9~0 .lut_mask = 16'h3B3B;
+defparam \SPI_DAC|Selector9~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N11
+dffeas \SPI_DAC|dac_cs (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|Selector9~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_cs .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N8
+cycloneiii_lcell_comb \SPI_ADC|clk_1MHz~0 (
+// Equation(s):
+// \SPI_ADC|clk_1MHz~0_combout  = !\SPI_ADC|clk_1MHz~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_ADC|clk_1MHz~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|clk_1MHz~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~0 .lut_mask = 16'h0F0F;
+defparam \SPI_ADC|clk_1MHz~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N9
+dffeas \SPI_ADC|clk_1MHz (
+	.clk(\CLOCK_50~input_o ),
+	.d(\SPI_ADC|clk_1MHz~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_DAC|Equal0~1_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|clk_1MHz~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz .is_wysiwyg = "true";
+defparam \SPI_ADC|clk_1MHz .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G12
+cycloneiii_clkctrl \SPI_ADC|clk_1MHz~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_ADC|clk_1MHz~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_ADC|clk_1MHz~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_ADC|clk_1MHz~clkctrl .clock_type = "global clock";
+defparam \SPI_ADC|clk_1MHz~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: IOIBUF_X3_Y0_N22
+cycloneiii_io_ibuf \ADC_SDO~input (
+	.i(ADC_SDO),
+	.ibar(gnd),
+	.o(\ADC_SDO~input_o ));
+// synopsys translate_off
+defparam \ADC_SDO~input .bus_hold = "false";
+defparam \ADC_SDO~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N24
+cycloneiii_lcell_comb \SPI_ADC|Selector2~0 (
+// Equation(s):
+// \SPI_ADC|Selector2~0_combout  = (\SPI_ADC|sr_state.IDLE~q  & \SPI_ADC|adc_cs~q )
+
+	.dataa(\SPI_ADC|sr_state.IDLE~q ),
+	.datab(gnd),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector2~0 .lut_mask = 16'hA0A0;
+defparam \SPI_ADC|Selector2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N25
+dffeas \SPI_ADC|sr_state.WAIT_CSB_HIGH (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_HIGH .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y22_N26
+cycloneiii_lcell_comb \SPI_ADC|Selector0~0 (
+// Equation(s):
+// \SPI_ADC|Selector0~0_combout  = (\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & (\SPI_ADC|adc_cs~q  & ((\SPI_ADC|sr_state.IDLE~q ) # (\PULSE|pulse~q )))) # (!\SPI_ADC|sr_state.WAIT_CSB_HIGH~q  & (((\SPI_ADC|sr_state.IDLE~q ) # (\PULSE|pulse~q ))))
+
+	.dataa(\SPI_ADC|sr_state.WAIT_CSB_HIGH~q ),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(\SPI_ADC|sr_state.IDLE~q ),
+	.datad(\PULSE|pulse~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector0~0 .lut_mask = 16'hDDD0;
+defparam \SPI_ADC|Selector0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y22_N27
+dffeas \SPI_ADC|sr_state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.IDLE .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N12
+cycloneiii_lcell_comb \SPI_ADC|Selector1~0 (
+// Equation(s):
+// \SPI_ADC|Selector1~0_combout  = (\PULSE|pulse~q  & (((!\SPI_ADC|adc_cs~q  & \SPI_ADC|sr_state.WAIT_CSB_FALL~q )) # (!\SPI_ADC|sr_state.IDLE~q ))) # (!\PULSE|pulse~q  & (!\SPI_ADC|adc_cs~q  & (\SPI_ADC|sr_state.WAIT_CSB_FALL~q )))
+
+	.dataa(\PULSE|pulse~q ),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datad(\SPI_ADC|sr_state.IDLE~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector1~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector1~0 .lut_mask = 16'h30BA;
+defparam \SPI_ADC|Selector1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N13
+dffeas \SPI_ADC|sr_state.WAIT_CSB_FALL (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|Selector1~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .is_wysiwyg = "true";
+defparam \SPI_ADC|sr_state.WAIT_CSB_FALL .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N30
+cycloneiii_lcell_comb \SPI_ADC|adc_start~0 (
+// Equation(s):
+// \SPI_ADC|adc_start~0_combout  = (\SPI_ADC|adc_start~q  & ((\SPI_ADC|sr_state.WAIT_CSB_FALL~q ) # ((\SPI_ADC|adc_cs~q ) # (!\SPI_ADC|sr_state.IDLE~q ))))
+
+	.dataa(\SPI_ADC|sr_state.WAIT_CSB_FALL~q ),
+	.datab(\SPI_ADC|sr_state.IDLE~q ),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_ADC|adc_start~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|adc_start~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~0 .lut_mask = 16'hFB00;
+defparam \SPI_ADC|adc_start~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N10
+cycloneiii_lcell_comb \SPI_ADC|adc_start~1 (
+// Equation(s):
+// \SPI_ADC|adc_start~1_combout  = (\SPI_ADC|adc_start~0_combout ) # ((!\SPI_ADC|sr_state.IDLE~q  & \PULSE|pulse~q ))
+
+	.dataa(\SPI_ADC|adc_start~0_combout ),
+	.datab(\SPI_ADC|sr_state.IDLE~q ),
+	.datac(\PULSE|pulse~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_ADC|adc_start~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|adc_start~1 .lut_mask = 16'hBABA;
+defparam \SPI_ADC|adc_start~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X20_Y25_N11
+dffeas \SPI_ADC|adc_start (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\SPI_ADC|adc_start~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_start~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_start .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_start .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N24
+cycloneiii_lcell_comb \SPI_ADC|Add1~4 (
+// Equation(s):
+// \SPI_ADC|Add1~4_combout  = (\SPI_ADC|state [2] & (\SPI_ADC|Add1~3  $ (GND))) # (!\SPI_ADC|state [2] & (!\SPI_ADC|Add1~3  & VCC))
+// \SPI_ADC|Add1~5  = CARRY((\SPI_ADC|state [2] & !\SPI_ADC|Add1~3 ))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~3 ),
+	.combout(\SPI_ADC|Add1~4_combout ),
+	.cout(\SPI_ADC|Add1~5 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~4 .lut_mask = 16'hC30C;
+defparam \SPI_ADC|Add1~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N26
+cycloneiii_lcell_comb \SPI_ADC|Add1~6 (
+// Equation(s):
+// \SPI_ADC|Add1~6_combout  = (\SPI_ADC|state [3] & (!\SPI_ADC|Add1~5 )) # (!\SPI_ADC|state [3] & ((\SPI_ADC|Add1~5 ) # (GND)))
+// \SPI_ADC|Add1~7  = CARRY((!\SPI_ADC|Add1~5 ) # (!\SPI_ADC|state [3]))
+
+	.dataa(\SPI_ADC|state [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~5 ),
+	.combout(\SPI_ADC|Add1~6_combout ),
+	.cout(\SPI_ADC|Add1~7 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~6 .lut_mask = 16'h5A5F;
+defparam \SPI_ADC|Add1~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N27
+dffeas \SPI_ADC|state[3] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N28
+cycloneiii_lcell_comb \SPI_ADC|Add1~8 (
+// Equation(s):
+// \SPI_ADC|Add1~8_combout  = \SPI_ADC|Add1~7  $ (!\SPI_ADC|state [4])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(\SPI_ADC|Add1~7 ),
+	.combout(\SPI_ADC|Add1~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Add1~8 .lut_mask = 16'hF00F;
+defparam \SPI_ADC|Add1~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N0
+cycloneiii_lcell_comb \SPI_ADC|state~1 (
+// Equation(s):
+// \SPI_ADC|state~1_combout  = (\SPI_ADC|Add1~8_combout  & ((\SPI_ADC|state [1]) # (!\SPI_ADC|state~0_combout )))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|Add1~8_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|state~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|state~1 .lut_mask = 16'hF300;
+defparam \SPI_ADC|state~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N1
+dffeas \SPI_ADC|state[4] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|state~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N10
+cycloneiii_lcell_comb \SPI_ADC|Selector4~2 (
+// Equation(s):
+// \SPI_ADC|Selector4~2_combout  = (\SPI_ADC|state [4]) # (!\SPI_ADC|adc_start~q )
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector4~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~2 .lut_mask = 16'hFF55;
+defparam \SPI_ADC|Selector4~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N20
+cycloneiii_lcell_comb \SPI_ADC|Add1~0 (
+// Equation(s):
+// \SPI_ADC|Add1~0_combout  = \SPI_ADC|state [0] $ (VCC)
+// \SPI_ADC|Add1~1  = CARRY(\SPI_ADC|state [0])
+
+	.dataa(\SPI_ADC|state [0]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\SPI_ADC|Add1~0_combout ),
+	.cout(\SPI_ADC|Add1~1 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~0 .lut_mask = 16'h55AA;
+defparam \SPI_ADC|Add1~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N12
+cycloneiii_lcell_comb \SPI_ADC|Selector5~0 (
+// Equation(s):
+// \SPI_ADC|Selector5~0_combout  = (\SPI_ADC|state~0_combout  & (((\SPI_ADC|state [1])) # (!\SPI_ADC|Selector4~2_combout ))) # (!\SPI_ADC|state~0_combout  & (((\SPI_ADC|Add1~0_combout ))))
+
+	.dataa(\SPI_ADC|Selector4~2_combout ),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|Add1~0_combout ),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector5~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector5~0 .lut_mask = 16'hF7C4;
+defparam \SPI_ADC|Selector5~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N13
+dffeas \SPI_ADC|state[0] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Selector5~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N22
+cycloneiii_lcell_comb \SPI_ADC|Add1~2 (
+// Equation(s):
+// \SPI_ADC|Add1~2_combout  = (\SPI_ADC|state [1] & (!\SPI_ADC|Add1~1 )) # (!\SPI_ADC|state [1] & ((\SPI_ADC|Add1~1 ) # (GND)))
+// \SPI_ADC|Add1~3  = CARRY((!\SPI_ADC|Add1~1 ) # (!\SPI_ADC|state [1]))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\SPI_ADC|Add1~1 ),
+	.combout(\SPI_ADC|Add1~2_combout ),
+	.cout(\SPI_ADC|Add1~3 ));
+// synopsys translate_off
+defparam \SPI_ADC|Add1~2 .lut_mask = 16'h5A5F;
+defparam \SPI_ADC|Add1~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N23
+dffeas \SPI_ADC|state[1] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N25
+dffeas \SPI_ADC|state[2] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Add1~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|state [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|state[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|state[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N2
+cycloneiii_lcell_comb \SPI_ADC|state~0 (
+// Equation(s):
+// \SPI_ADC|state~0_combout  = (!\SPI_ADC|state [2] & (!\SPI_ADC|state [3] & !\SPI_ADC|state [0]))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|state~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|state~0 .lut_mask = 16'h0003;
+defparam \SPI_ADC|state~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N6
+cycloneiii_lcell_comb \SPI_ADC|Selector4~3 (
+// Equation(s):
+// \SPI_ADC|Selector4~3_combout  = ((\SPI_ADC|state [1]) # ((\SPI_ADC|adc_start~q  & !\SPI_ADC|state [4]))) # (!\SPI_ADC|state~0_combout )
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(\SPI_ADC|state~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector4~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector4~3 .lut_mask = 16'hF3FB;
+defparam \SPI_ADC|Selector4~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N7
+dffeas \SPI_ADC|adc_cs (
+	.clk(\SPI_ADC|clk_1MHz~q ),
+	.d(\SPI_ADC|Selector4~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_cs~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_cs .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N16
+cycloneiii_lcell_comb \SPI_ADC|WideOr0~0 (
+// Equation(s):
+// \SPI_ADC|WideOr0~0_combout  = (\SPI_ADC|state [2] & (((!\SPI_ADC|state [0]) # (!\SPI_ADC|state [3])) # (!\SPI_ADC|state [1]))) # (!\SPI_ADC|state [2] & (((\SPI_ADC|state [3]))))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|WideOr0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~0 .lut_mask = 16'h7CFC;
+defparam \SPI_ADC|WideOr0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N14
+cycloneiii_lcell_comb \SPI_ADC|WideOr0~1 (
+// Equation(s):
+// \SPI_ADC|WideOr0~1_combout  = (\SPI_ADC|state [4] & (((\SPI_ADC|state [1])) # (!\SPI_ADC|state~0_combout ))) # (!\SPI_ADC|state [4] & (((\SPI_ADC|WideOr0~0_combout ))))
+
+	.dataa(\SPI_ADC|state~0_combout ),
+	.datab(\SPI_ADC|WideOr0~0_combout ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|WideOr0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|WideOr0~1 .lut_mask = 16'hF5CC;
+defparam \SPI_ADC|WideOr0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N15
+dffeas \SPI_ADC|shift_ena (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|WideOr0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_ena~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_ena .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_ena .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N14
+cycloneiii_lcell_comb \SPI_ADC|always3~0 (
+// Equation(s):
+// \SPI_ADC|always3~0_combout  = (\SPI_ADC|adc_cs~q  & \SPI_ADC|shift_ena~q )
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_ADC|shift_ena~q ),
+	.cin(gnd),
+	.combout(\SPI_ADC|always3~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|always3~0 .lut_mask = 16'hF000;
+defparam \SPI_ADC|always3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N21
+dffeas \SPI_ADC|shift_reg[0] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\ADC_SDO~input_o ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N26
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[1]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[1]~feeder_combout  = \SPI_ADC|shift_reg [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[1]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N27
+dffeas \SPI_ADC|shift_reg[1] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[1]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N17
+dffeas \SPI_ADC|shift_reg[2] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N22
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[3]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[3]~feeder_combout  = \SPI_ADC|shift_reg [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [2]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[3]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N23
+dffeas \SPI_ADC|shift_reg[3] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[3]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N29
+dffeas \SPI_ADC|shift_reg[4] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N18
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[5]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[5]~feeder_combout  = \SPI_ADC|shift_reg [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N19
+dffeas \SPI_ADC|shift_reg[5] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N8
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[6]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[6]~feeder_combout  = \SPI_ADC|shift_reg [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [5]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[6]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N9
+dffeas \SPI_ADC|shift_reg[6] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[6]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N31
+dffeas \SPI_ADC|shift_reg[7] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N18
+cycloneiii_lcell_comb \SPI_ADC|Decoder0~0 (
+// Equation(s):
+// \SPI_ADC|Decoder0~0_combout  = (\SPI_ADC|state [1] & (\SPI_ADC|state [2] & (\SPI_ADC|state [3] & \SPI_ADC|state [0])))
+
+	.dataa(\SPI_ADC|state [1]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|state [3]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Decoder0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~0 .lut_mask = 16'h8000;
+defparam \SPI_ADC|Decoder0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N4
+cycloneiii_lcell_comb \SPI_ADC|Decoder0~1 (
+// Equation(s):
+// \SPI_ADC|Decoder0~1_combout  = (\SPI_ADC|Decoder0~0_combout  & !\SPI_ADC|state [4])
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|Decoder0~0_combout ),
+	.datac(gnd),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Decoder0~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Decoder0~1 .lut_mask = 16'h00CC;
+defparam \SPI_ADC|Decoder0~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N5
+dffeas \SPI_ADC|adc_done (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Decoder0~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_done~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_done .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_done .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N19
+dffeas \SPI_ADC|data_from_adc[7] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[7] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y20_N2
+cycloneiii_lcell_comb \DUMMY|PULSE2|state.IDLE~0 (
+// Equation(s):
+// \DUMMY|PULSE2|state.IDLE~0_combout  = !\SPI_ADC|adc_cs~q 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|adc_cs~q ),
+	.cin(gnd),
+	.combout(\DUMMY|PULSE2|state.IDLE~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|PULSE2|state.IDLE~0 .lut_mask = 16'h00FF;
+defparam \DUMMY|PULSE2|state.IDLE~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y20_N3
+dffeas \DUMMY|PULSE2|state.IDLE (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|PULSE2|state.IDLE~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|PULSE2|state.IDLE~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|PULSE2|state.IDLE .is_wysiwyg = "true";
+defparam \DUMMY|PULSE2|state.IDLE .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X19_Y20_N0
+cycloneiii_lcell_comb \DUMMY|PULSE2|pulse~1 (
+// Equation(s):
+// \DUMMY|PULSE2|pulse~1_combout  = (!\SPI_ADC|adc_cs~q  & !\DUMMY|PULSE2|state.IDLE~q )
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|adc_cs~q ),
+	.datac(gnd),
+	.datad(\DUMMY|PULSE2|state.IDLE~q ),
+	.cin(gnd),
+	.combout(\DUMMY|PULSE2|pulse~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|PULSE2|pulse~1 .lut_mask = 16'h0033;
+defparam \DUMMY|PULSE2|pulse~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X19_Y20_N1
+dffeas \DUMMY|PULSE2|pulse (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|PULSE2|pulse~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|PULSE2|pulse~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|PULSE2|pulse .is_wysiwyg = "true";
+defparam \DUMMY|PULSE2|pulse .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X14_Y20_N25
+dffeas \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|PULSE2|pulse~q ),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store .is_wysiwyg = "true";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y20_N24
+cycloneiii_lcell_comb \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 (
+// Equation(s):
+// \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout  = (\DUMMY|PULSE2|pulse~q ) # (\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q )
+
+	.dataa(gnd),
+	.datab(\DUMMY|PULSE2|pulse~q ),
+	.datac(\DUMMY|DELAY|altsyncram_component|auto_generated|rden_b_store~q ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 .lut_mask = 16'hFCFC;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N13
+dffeas \SPI_ADC|shift_reg[8] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N21
+dffeas \SPI_ADC|data_from_adc[8] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[8] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N10
+cycloneiii_lcell_comb \SPI_ADC|shift_reg[9]~feeder (
+// Equation(s):
+// \SPI_ADC|shift_reg[9]~feeder_combout  = \SPI_ADC|shift_reg [8]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [8]),
+	.cin(gnd),
+	.combout(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|shift_reg[9]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N11
+dffeas \SPI_ADC|shift_reg[9] (
+	.clk(!\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|shift_reg[9]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|always3~0_combout ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N23
+dffeas \SPI_ADC|data_from_adc[9] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[9] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: CLKCTRL_G10
+cycloneiii_clkctrl \SPI_ADC|adc_cs~clkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\SPI_ADC|adc_cs~q }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\SPI_ADC|adc_cs~clkctrl_outclk ));
+// synopsys translate_off
+defparam \SPI_ADC|adc_cs~clkctrl .clock_type = "global clock";
+defparam \SPI_ADC|adc_cs~clkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N0
+cycloneiii_lcell_comb \DUMMY|ctr[0]~36 (
+// Equation(s):
+// \DUMMY|ctr[0]~36_combout  = !\DUMMY|ctr [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\DUMMY|ctr [0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|ctr[0]~36_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|ctr[0]~36 .lut_mask = 16'h0F0F;
+defparam \DUMMY|ctr[0]~36 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N1
+dffeas \DUMMY|ctr[0] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[0]~36_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[0] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N6
+cycloneiii_lcell_comb \DUMMY|ctr[1]~12 (
+// Equation(s):
+// \DUMMY|ctr[1]~12_combout  = (\DUMMY|ctr [1] & (\DUMMY|ctr [0] $ (VCC))) # (!\DUMMY|ctr [1] & (\DUMMY|ctr [0] & VCC))
+// \DUMMY|ctr[1]~13  = CARRY((\DUMMY|ctr [1] & \DUMMY|ctr [0]))
+
+	.dataa(\DUMMY|ctr [1]),
+	.datab(\DUMMY|ctr [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|ctr[1]~12_combout ),
+	.cout(\DUMMY|ctr[1]~13 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[1]~12 .lut_mask = 16'h6688;
+defparam \DUMMY|ctr[1]~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N7
+dffeas \DUMMY|ctr[1] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[1]~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[1] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N8
+cycloneiii_lcell_comb \DUMMY|ctr[2]~14 (
+// Equation(s):
+// \DUMMY|ctr[2]~14_combout  = (\DUMMY|ctr [2] & (!\DUMMY|ctr[1]~13 )) # (!\DUMMY|ctr [2] & ((\DUMMY|ctr[1]~13 ) # (GND)))
+// \DUMMY|ctr[2]~15  = CARRY((!\DUMMY|ctr[1]~13 ) # (!\DUMMY|ctr [2]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[1]~13 ),
+	.combout(\DUMMY|ctr[2]~14_combout ),
+	.cout(\DUMMY|ctr[2]~15 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[2]~14 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[2]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N9
+dffeas \DUMMY|ctr[2] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[2]~14_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[2] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N10
+cycloneiii_lcell_comb \DUMMY|ctr[3]~16 (
+// Equation(s):
+// \DUMMY|ctr[3]~16_combout  = (\DUMMY|ctr [3] & (\DUMMY|ctr[2]~15  $ (GND))) # (!\DUMMY|ctr [3] & (!\DUMMY|ctr[2]~15  & VCC))
+// \DUMMY|ctr[3]~17  = CARRY((\DUMMY|ctr [3] & !\DUMMY|ctr[2]~15 ))
+
+	.dataa(\DUMMY|ctr [3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[2]~15 ),
+	.combout(\DUMMY|ctr[3]~16_combout ),
+	.cout(\DUMMY|ctr[3]~17 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[3]~16 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[3]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N11
+dffeas \DUMMY|ctr[3] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[3]~16_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[3] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N12
+cycloneiii_lcell_comb \DUMMY|ctr[4]~18 (
+// Equation(s):
+// \DUMMY|ctr[4]~18_combout  = (\DUMMY|ctr [4] & (!\DUMMY|ctr[3]~17 )) # (!\DUMMY|ctr [4] & ((\DUMMY|ctr[3]~17 ) # (GND)))
+// \DUMMY|ctr[4]~19  = CARRY((!\DUMMY|ctr[3]~17 ) # (!\DUMMY|ctr [4]))
+
+	.dataa(\DUMMY|ctr [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[3]~17 ),
+	.combout(\DUMMY|ctr[4]~18_combout ),
+	.cout(\DUMMY|ctr[4]~19 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[4]~18 .lut_mask = 16'h5A5F;
+defparam \DUMMY|ctr[4]~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N13
+dffeas \DUMMY|ctr[4] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[4]~18_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[4] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N8
+cycloneiii_lcell_comb \DUMMY|wraddr[4]~0 (
+// Equation(s):
+// \DUMMY|wraddr[4]~0_combout  = (\SW[0]~input_o  & (\DUMMY|ctr [4] $ (VCC))) # (!\SW[0]~input_o  & (\DUMMY|ctr [4] & VCC))
+// \DUMMY|wraddr[4]~1  = CARRY((\SW[0]~input_o  & \DUMMY|ctr [4]))
+
+	.dataa(\SW[0]~input_o ),
+	.datab(\DUMMY|ctr [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|wraddr[4]~0_combout ),
+	.cout(\DUMMY|wraddr[4]~1 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[4]~0 .lut_mask = 16'h6688;
+defparam \DUMMY|wraddr[4]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N14
+cycloneiii_lcell_comb \DUMMY|ctr[5]~20 (
+// Equation(s):
+// \DUMMY|ctr[5]~20_combout  = (\DUMMY|ctr [5] & (\DUMMY|ctr[4]~19  $ (GND))) # (!\DUMMY|ctr [5] & (!\DUMMY|ctr[4]~19  & VCC))
+// \DUMMY|ctr[5]~21  = CARRY((\DUMMY|ctr [5] & !\DUMMY|ctr[4]~19 ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[4]~19 ),
+	.combout(\DUMMY|ctr[5]~20_combout ),
+	.cout(\DUMMY|ctr[5]~21 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[5]~20 .lut_mask = 16'hC30C;
+defparam \DUMMY|ctr[5]~20 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N15
+dffeas \DUMMY|ctr[5] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[5]~20_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[5] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N10
+cycloneiii_lcell_comb \DUMMY|wraddr[5]~2 (
+// Equation(s):
+// \DUMMY|wraddr[5]~2_combout  = (\DUMMY|ctr [5] & ((\SW[1]~input_o  & (\DUMMY|wraddr[4]~1  & VCC)) # (!\SW[1]~input_o  & (!\DUMMY|wraddr[4]~1 )))) # (!\DUMMY|ctr [5] & ((\SW[1]~input_o  & (!\DUMMY|wraddr[4]~1 )) # (!\SW[1]~input_o  & ((\DUMMY|wraddr[4]~1 ) 
+// # (GND)))))
+// \DUMMY|wraddr[5]~3  = CARRY((\DUMMY|ctr [5] & (!\SW[1]~input_o  & !\DUMMY|wraddr[4]~1 )) # (!\DUMMY|ctr [5] & ((!\DUMMY|wraddr[4]~1 ) # (!\SW[1]~input_o ))))
+
+	.dataa(\DUMMY|ctr [5]),
+	.datab(\SW[1]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[4]~1 ),
+	.combout(\DUMMY|wraddr[5]~2_combout ),
+	.cout(\DUMMY|wraddr[5]~3 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[5]~2 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[5]~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N16
+cycloneiii_lcell_comb \DUMMY|ctr[6]~22 (
+// Equation(s):
+// \DUMMY|ctr[6]~22_combout  = (\DUMMY|ctr [6] & (!\DUMMY|ctr[5]~21 )) # (!\DUMMY|ctr [6] & ((\DUMMY|ctr[5]~21 ) # (GND)))
+// \DUMMY|ctr[6]~23  = CARRY((!\DUMMY|ctr[5]~21 ) # (!\DUMMY|ctr [6]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[5]~21 ),
+	.combout(\DUMMY|ctr[6]~22_combout ),
+	.cout(\DUMMY|ctr[6]~23 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[6]~22 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[6]~22 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N17
+dffeas \DUMMY|ctr[6] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[6]~22_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[6] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N12
+cycloneiii_lcell_comb \DUMMY|wraddr[6]~4 (
+// Equation(s):
+// \DUMMY|wraddr[6]~4_combout  = ((\DUMMY|ctr [6] $ (\SW[2]~input_o  $ (!\DUMMY|wraddr[5]~3 )))) # (GND)
+// \DUMMY|wraddr[6]~5  = CARRY((\DUMMY|ctr [6] & ((\SW[2]~input_o ) # (!\DUMMY|wraddr[5]~3 ))) # (!\DUMMY|ctr [6] & (\SW[2]~input_o  & !\DUMMY|wraddr[5]~3 )))
+
+	.dataa(\DUMMY|ctr [6]),
+	.datab(\SW[2]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[5]~3 ),
+	.combout(\DUMMY|wraddr[6]~4_combout ),
+	.cout(\DUMMY|wraddr[6]~5 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[6]~4 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[6]~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N18
+cycloneiii_lcell_comb \DUMMY|ctr[7]~24 (
+// Equation(s):
+// \DUMMY|ctr[7]~24_combout  = (\DUMMY|ctr [7] & (\DUMMY|ctr[6]~23  $ (GND))) # (!\DUMMY|ctr [7] & (!\DUMMY|ctr[6]~23  & VCC))
+// \DUMMY|ctr[7]~25  = CARRY((\DUMMY|ctr [7] & !\DUMMY|ctr[6]~23 ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[6]~23 ),
+	.combout(\DUMMY|ctr[7]~24_combout ),
+	.cout(\DUMMY|ctr[7]~25 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[7]~24 .lut_mask = 16'hC30C;
+defparam \DUMMY|ctr[7]~24 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N19
+dffeas \DUMMY|ctr[7] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[7]~24_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[7] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N14
+cycloneiii_lcell_comb \DUMMY|wraddr[7]~6 (
+// Equation(s):
+// \DUMMY|wraddr[7]~6_combout  = (\DUMMY|ctr [7] & ((\SW[3]~input_o  & (\DUMMY|wraddr[6]~5  & VCC)) # (!\SW[3]~input_o  & (!\DUMMY|wraddr[6]~5 )))) # (!\DUMMY|ctr [7] & ((\SW[3]~input_o  & (!\DUMMY|wraddr[6]~5 )) # (!\SW[3]~input_o  & ((\DUMMY|wraddr[6]~5 ) 
+// # (GND)))))
+// \DUMMY|wraddr[7]~7  = CARRY((\DUMMY|ctr [7] & (!\SW[3]~input_o  & !\DUMMY|wraddr[6]~5 )) # (!\DUMMY|ctr [7] & ((!\DUMMY|wraddr[6]~5 ) # (!\SW[3]~input_o ))))
+
+	.dataa(\DUMMY|ctr [7]),
+	.datab(\SW[3]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[6]~5 ),
+	.combout(\DUMMY|wraddr[7]~6_combout ),
+	.cout(\DUMMY|wraddr[7]~7 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[7]~6 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[7]~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N20
+cycloneiii_lcell_comb \DUMMY|ctr[8]~26 (
+// Equation(s):
+// \DUMMY|ctr[8]~26_combout  = (\DUMMY|ctr [8] & (!\DUMMY|ctr[7]~25 )) # (!\DUMMY|ctr [8] & ((\DUMMY|ctr[7]~25 ) # (GND)))
+// \DUMMY|ctr[8]~27  = CARRY((!\DUMMY|ctr[7]~25 ) # (!\DUMMY|ctr [8]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[7]~25 ),
+	.combout(\DUMMY|ctr[8]~26_combout ),
+	.cout(\DUMMY|ctr[8]~27 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[8]~26 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[8]~26 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N21
+dffeas \DUMMY|ctr[8] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[8]~26_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[8] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N16
+cycloneiii_lcell_comb \DUMMY|wraddr[8]~8 (
+// Equation(s):
+// \DUMMY|wraddr[8]~8_combout  = ((\SW[4]~input_o  $ (\DUMMY|ctr [8] $ (!\DUMMY|wraddr[7]~7 )))) # (GND)
+// \DUMMY|wraddr[8]~9  = CARRY((\SW[4]~input_o  & ((\DUMMY|ctr [8]) # (!\DUMMY|wraddr[7]~7 ))) # (!\SW[4]~input_o  & (\DUMMY|ctr [8] & !\DUMMY|wraddr[7]~7 )))
+
+	.dataa(\SW[4]~input_o ),
+	.datab(\DUMMY|ctr [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[7]~7 ),
+	.combout(\DUMMY|wraddr[8]~8_combout ),
+	.cout(\DUMMY|wraddr[8]~9 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[8]~8 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[8]~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N22
+cycloneiii_lcell_comb \DUMMY|ctr[9]~28 (
+// Equation(s):
+// \DUMMY|ctr[9]~28_combout  = (\DUMMY|ctr [9] & (\DUMMY|ctr[8]~27  $ (GND))) # (!\DUMMY|ctr [9] & (!\DUMMY|ctr[8]~27  & VCC))
+// \DUMMY|ctr[9]~29  = CARRY((\DUMMY|ctr [9] & !\DUMMY|ctr[8]~27 ))
+
+	.dataa(\DUMMY|ctr [9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[8]~27 ),
+	.combout(\DUMMY|ctr[9]~28_combout ),
+	.cout(\DUMMY|ctr[9]~29 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[9]~28 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[9]~28 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N23
+dffeas \DUMMY|ctr[9] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[9]~28_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[9] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N18
+cycloneiii_lcell_comb \DUMMY|wraddr[9]~10 (
+// Equation(s):
+// \DUMMY|wraddr[9]~10_combout  = (\DUMMY|ctr [9] & ((\SW[5]~input_o  & (\DUMMY|wraddr[8]~9  & VCC)) # (!\SW[5]~input_o  & (!\DUMMY|wraddr[8]~9 )))) # (!\DUMMY|ctr [9] & ((\SW[5]~input_o  & (!\DUMMY|wraddr[8]~9 )) # (!\SW[5]~input_o  & ((\DUMMY|wraddr[8]~9 ) 
+// # (GND)))))
+// \DUMMY|wraddr[9]~11  = CARRY((\DUMMY|ctr [9] & (!\SW[5]~input_o  & !\DUMMY|wraddr[8]~9 )) # (!\DUMMY|ctr [9] & ((!\DUMMY|wraddr[8]~9 ) # (!\SW[5]~input_o ))))
+
+	.dataa(\DUMMY|ctr [9]),
+	.datab(\SW[5]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[8]~9 ),
+	.combout(\DUMMY|wraddr[9]~10_combout ),
+	.cout(\DUMMY|wraddr[9]~11 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[9]~10 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[9]~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N24
+cycloneiii_lcell_comb \DUMMY|ctr[10]~30 (
+// Equation(s):
+// \DUMMY|ctr[10]~30_combout  = (\DUMMY|ctr [10] & (!\DUMMY|ctr[9]~29 )) # (!\DUMMY|ctr [10] & ((\DUMMY|ctr[9]~29 ) # (GND)))
+// \DUMMY|ctr[10]~31  = CARRY((!\DUMMY|ctr[9]~29 ) # (!\DUMMY|ctr [10]))
+
+	.dataa(gnd),
+	.datab(\DUMMY|ctr [10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[9]~29 ),
+	.combout(\DUMMY|ctr[10]~30_combout ),
+	.cout(\DUMMY|ctr[10]~31 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[10]~30 .lut_mask = 16'h3C3F;
+defparam \DUMMY|ctr[10]~30 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N25
+dffeas \DUMMY|ctr[10] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[10]~30_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[10] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N20
+cycloneiii_lcell_comb \DUMMY|wraddr[10]~12 (
+// Equation(s):
+// \DUMMY|wraddr[10]~12_combout  = ((\DUMMY|ctr [10] $ (\SW[6]~input_o  $ (!\DUMMY|wraddr[9]~11 )))) # (GND)
+// \DUMMY|wraddr[10]~13  = CARRY((\DUMMY|ctr [10] & ((\SW[6]~input_o ) # (!\DUMMY|wraddr[9]~11 ))) # (!\DUMMY|ctr [10] & (\SW[6]~input_o  & !\DUMMY|wraddr[9]~11 )))
+
+	.dataa(\DUMMY|ctr [10]),
+	.datab(\SW[6]~input_o ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[9]~11 ),
+	.combout(\DUMMY|wraddr[10]~12_combout ),
+	.cout(\DUMMY|wraddr[10]~13 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[10]~12 .lut_mask = 16'h698E;
+defparam \DUMMY|wraddr[10]~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N26
+cycloneiii_lcell_comb \DUMMY|ctr[11]~32 (
+// Equation(s):
+// \DUMMY|ctr[11]~32_combout  = (\DUMMY|ctr [11] & (\DUMMY|ctr[10]~31  $ (GND))) # (!\DUMMY|ctr [11] & (!\DUMMY|ctr[10]~31  & VCC))
+// \DUMMY|ctr[11]~33  = CARRY((\DUMMY|ctr [11] & !\DUMMY|ctr[10]~31 ))
+
+	.dataa(\DUMMY|ctr [11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|ctr[10]~31 ),
+	.combout(\DUMMY|ctr[11]~32_combout ),
+	.cout(\DUMMY|ctr[11]~33 ));
+// synopsys translate_off
+defparam \DUMMY|ctr[11]~32 .lut_mask = 16'hA50A;
+defparam \DUMMY|ctr[11]~32 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N27
+dffeas \DUMMY|ctr[11] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[11]~32_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[11] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N22
+cycloneiii_lcell_comb \DUMMY|wraddr[11]~14 (
+// Equation(s):
+// \DUMMY|wraddr[11]~14_combout  = (\SW[7]~input_o  & ((\DUMMY|ctr [11] & (\DUMMY|wraddr[10]~13  & VCC)) # (!\DUMMY|ctr [11] & (!\DUMMY|wraddr[10]~13 )))) # (!\SW[7]~input_o  & ((\DUMMY|ctr [11] & (!\DUMMY|wraddr[10]~13 )) # (!\DUMMY|ctr [11] & 
+// ((\DUMMY|wraddr[10]~13 ) # (GND)))))
+// \DUMMY|wraddr[11]~15  = CARRY((\SW[7]~input_o  & (!\DUMMY|ctr [11] & !\DUMMY|wraddr[10]~13 )) # (!\SW[7]~input_o  & ((!\DUMMY|wraddr[10]~13 ) # (!\DUMMY|ctr [11]))))
+
+	.dataa(\SW[7]~input_o ),
+	.datab(\DUMMY|ctr [11]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|wraddr[10]~13 ),
+	.combout(\DUMMY|wraddr[11]~14_combout ),
+	.cout(\DUMMY|wraddr[11]~15 ));
+// synopsys translate_off
+defparam \DUMMY|wraddr[11]~14 .lut_mask = 16'h9617;
+defparam \DUMMY|wraddr[11]~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X23_Y20_N28
+cycloneiii_lcell_comb \DUMMY|ctr[12]~34 (
+// Equation(s):
+// \DUMMY|ctr[12]~34_combout  = \DUMMY|ctr[11]~33  $ (\DUMMY|ctr [12])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\DUMMY|ctr [12]),
+	.cin(\DUMMY|ctr[11]~33 ),
+	.combout(\DUMMY|ctr[12]~34_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|ctr[12]~34 .lut_mask = 16'h0FF0;
+defparam \DUMMY|ctr[12]~34 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X23_Y20_N29
+dffeas \DUMMY|ctr[12] (
+	.clk(\SPI_ADC|adc_cs~clkctrl_outclk ),
+	.d(\DUMMY|ctr[12]~34_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|ctr [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|ctr[12] .is_wysiwyg = "true";
+defparam \DUMMY|ctr[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X14_Y23_N24
+cycloneiii_lcell_comb \DUMMY|wraddr[12]~16 (
+// Equation(s):
+// \DUMMY|wraddr[12]~16_combout  = \SW[8]~input_o  $ (\DUMMY|wraddr[11]~15  $ (!\DUMMY|ctr [12]))
+
+	.dataa(\SW[8]~input_o ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\DUMMY|ctr [12]),
+	.cin(\DUMMY|wraddr[11]~15 ),
+	.combout(\DUMMY|wraddr[12]~16_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|wraddr[12]~16 .lut_mask = 16'h5AA5;
+defparam \DUMMY|wraddr[12]~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y21_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~0_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N3
+dffeas \SPI_ADC|data_from_adc[6] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[6] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N24
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[5]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[5]~feeder_combout  = \SPI_ADC|shift_reg [5]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [5]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[5]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[5]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N25
+dffeas \SPI_ADC|data_from_adc[5] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[5]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[5] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N16
+cycloneiii_lcell_comb \DUMMY|Add0~12 (
+// Equation(s):
+// \DUMMY|Add0~12_combout  = ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] $ (\SPI_ADC|data_from_adc [6] $ (\DUMMY|Add0~11 )))) # (GND)
+// \DUMMY|Add0~13  = CARRY((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] & (\SPI_ADC|data_from_adc [6] & !\DUMMY|Add0~11 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6] & ((\SPI_ADC|data_from_adc [6]) # (!\DUMMY|Add0~11 ))))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [6]),
+	.datab(\SPI_ADC|data_from_adc [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~11 ),
+	.combout(\DUMMY|Add0~12_combout ),
+	.cout(\DUMMY|Add0~13 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~12 .lut_mask = 16'h964D;
+defparam \DUMMY|Add0~12 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y20_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~12_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N0
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[4]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[4]~feeder_combout  = \SPI_ADC|shift_reg [4]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[4]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[4]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N1
+dffeas \SPI_ADC|data_from_adc[4] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[4]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[4] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N14
+cycloneiii_lcell_comb \DUMMY|Add0~10 (
+// Equation(s):
+// \DUMMY|Add0~10_combout  = (\SPI_ADC|data_from_adc [5] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (!\DUMMY|Add0~9 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (\DUMMY|Add0~9  & VCC)))) # (!\SPI_ADC|data_from_adc [5] 
+// & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & ((\DUMMY|Add0~9 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & (!\DUMMY|Add0~9 ))))
+// \DUMMY|Add0~11  = CARRY((\SPI_ADC|data_from_adc [5] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5] & !\DUMMY|Add0~9 )) # (!\SPI_ADC|data_from_adc [5] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5]) # (!\DUMMY|Add0~9 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [5]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~9 ),
+	.combout(\DUMMY|Add0~10_combout ),
+	.cout(\DUMMY|Add0~11 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~10 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~10 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y22_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~10_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N12
+cycloneiii_lcell_comb \DUMMY|Add0~8 (
+// Equation(s):
+// \DUMMY|Add0~8_combout  = ((\SPI_ADC|data_from_adc [4] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] $ (\DUMMY|Add0~7 )))) # (GND)
+// \DUMMY|Add0~9  = CARRY((\SPI_ADC|data_from_adc [4] & ((!\DUMMY|Add0~7 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4]))) # (!\SPI_ADC|data_from_adc [4] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4] & !\DUMMY|Add0~7 )))
+
+	.dataa(\SPI_ADC|data_from_adc [4]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~7 ),
+	.combout(\DUMMY|Add0~8_combout ),
+	.cout(\DUMMY|Add0~9 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~8 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~8 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y21_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~8_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N3
+dffeas \SPI_ADC|data_from_adc[3] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[3] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N4
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[2]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[2]~feeder_combout  = \SPI_ADC|shift_reg [2]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [2]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[2]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[2]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N5
+dffeas \SPI_ADC|data_from_adc[2] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[2]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[2] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N10
+cycloneiii_lcell_comb \DUMMY|Add0~6 (
+// Equation(s):
+// \DUMMY|Add0~6_combout  = (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & ((\SPI_ADC|data_from_adc [3] & (!\DUMMY|Add0~5 )) # (!\SPI_ADC|data_from_adc [3] & ((\DUMMY|Add0~5 ) # (GND))))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b 
+// [3] & ((\SPI_ADC|data_from_adc [3] & (\DUMMY|Add0~5  & VCC)) # (!\SPI_ADC|data_from_adc [3] & (!\DUMMY|Add0~5 ))))
+// \DUMMY|Add0~7  = CARRY((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & ((!\DUMMY|Add0~5 ) # (!\SPI_ADC|data_from_adc [3]))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3] & (!\SPI_ADC|data_from_adc [3] & !\DUMMY|Add0~5 )))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [3]),
+	.datab(\SPI_ADC|data_from_adc [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~5 ),
+	.combout(\DUMMY|Add0~6_combout ),
+	.cout(\DUMMY|Add0~7 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~6 .lut_mask = 16'h692B;
+defparam \DUMMY|Add0~6 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y22_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~6_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N7
+dffeas \SPI_ADC|data_from_adc[1] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(gnd),
+	.asdata(\SPI_ADC|shift_reg [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[1] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N8
+cycloneiii_lcell_comb \DUMMY|Add0~4 (
+// Equation(s):
+// \DUMMY|Add0~4_combout  = ((\SPI_ADC|data_from_adc [2] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] $ (\DUMMY|Add0~3 )))) # (GND)
+// \DUMMY|Add0~5  = CARRY((\SPI_ADC|data_from_adc [2] & ((!\DUMMY|Add0~3 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2]))) # (!\SPI_ADC|data_from_adc [2] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2] & !\DUMMY|Add0~3 )))
+
+	.dataa(\SPI_ADC|data_from_adc [2]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~3 ),
+	.combout(\DUMMY|Add0~4_combout ),
+	.cout(\DUMMY|Add0~5 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~4 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y20_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~4_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N6
+cycloneiii_lcell_comb \DUMMY|Add0~2 (
+// Equation(s):
+// \DUMMY|Add0~2_combout  = (\SPI_ADC|data_from_adc [1] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (!\DUMMY|Add0~1 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (\DUMMY|Add0~1  & VCC)))) # (!\SPI_ADC|data_from_adc [1] 
+// & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & ((\DUMMY|Add0~1 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & (!\DUMMY|Add0~1 ))))
+// \DUMMY|Add0~3  = CARRY((\SPI_ADC|data_from_adc [1] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1] & !\DUMMY|Add0~1 )) # (!\SPI_ADC|data_from_adc [1] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1]) # (!\DUMMY|Add0~1 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [1]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~1 ),
+	.combout(\DUMMY|Add0~2_combout ),
+	.cout(\DUMMY|Add0~3 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~2 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X13_Y23_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add0~2_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y21_N0
+cycloneiii_lcell_comb \SPI_ADC|data_from_adc[0]~feeder (
+// Equation(s):
+// \SPI_ADC|data_from_adc[0]~feeder_combout  = \SPI_ADC|shift_reg [0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\SPI_ADC|shift_reg [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|data_from_adc[0]~feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0]~feeder .lut_mask = 16'hFF00;
+defparam \SPI_ADC|data_from_adc[0]~feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y21_N1
+dffeas \SPI_ADC|data_from_adc[0] (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|data_from_adc[0]~feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(\SPI_ADC|adc_done~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|data_from_adc [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|data_from_adc[0] .is_wysiwyg = "true";
+defparam \SPI_ADC|data_from_adc[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N4
+cycloneiii_lcell_comb \DUMMY|Add0~0 (
+// Equation(s):
+// \DUMMY|Add0~0_combout  = (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & (\SPI_ADC|data_from_adc [0] & VCC)) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & (\SPI_ADC|data_from_adc [0] $ (VCC)))
+// \DUMMY|Add0~1  = CARRY((!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0] & \SPI_ADC|data_from_adc [0]))
+
+	.dataa(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [0]),
+	.datab(\SPI_ADC|data_from_adc [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|Add0~0_combout ),
+	.cout(\DUMMY|Add0~1 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~0 .lut_mask = 16'h9944;
+defparam \DUMMY|Add0~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N18
+cycloneiii_lcell_comb \DUMMY|Add0~14 (
+// Equation(s):
+// \DUMMY|Add0~14_combout  = (\SPI_ADC|data_from_adc [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (!\DUMMY|Add0~13 )) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (\DUMMY|Add0~13  & VCC)))) # (!\SPI_ADC|data_from_adc 
+// [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & ((\DUMMY|Add0~13 ) # (GND))) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & (!\DUMMY|Add0~13 ))))
+// \DUMMY|Add0~15  = CARRY((\SPI_ADC|data_from_adc [7] & (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7] & !\DUMMY|Add0~13 )) # (!\SPI_ADC|data_from_adc [7] & ((\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7]) # (!\DUMMY|Add0~13 ))))
+
+	.dataa(\SPI_ADC|data_from_adc [7]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~13 ),
+	.combout(\DUMMY|Add0~14_combout ),
+	.cout(\DUMMY|Add0~15 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~14 .lut_mask = 16'h694D;
+defparam \DUMMY|Add0~14 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N20
+cycloneiii_lcell_comb \DUMMY|Add0~16 (
+// Equation(s):
+// \DUMMY|Add0~16_combout  = ((\SPI_ADC|data_from_adc [8] $ (\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] $ (\DUMMY|Add0~15 )))) # (GND)
+// \DUMMY|Add0~17  = CARRY((\SPI_ADC|data_from_adc [8] & ((!\DUMMY|Add0~15 ) # (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]))) # (!\SPI_ADC|data_from_adc [8] & (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8] & !\DUMMY|Add0~15 )))
+
+	.dataa(\SPI_ADC|data_from_adc [8]),
+	.datab(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add0~15 ),
+	.combout(\DUMMY|Add0~16_combout ),
+	.cout(\DUMMY|Add0~17 ));
+// synopsys translate_off
+defparam \DUMMY|Add0~16 .lut_mask = 16'h962B;
+defparam \DUMMY|Add0~16 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N22
+cycloneiii_lcell_comb \DUMMY|Add0~18 (
+// Equation(s):
+// \DUMMY|Add0~18_combout  = \SPI_ADC|data_from_adc [9] $ (\DUMMY|Add0~17  $ (!\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]))
+
+	.dataa(gnd),
+	.datab(\SPI_ADC|data_from_adc [9]),
+	.datac(gnd),
+	.datad(\DUMMY|DELAY|altsyncram_component|auto_generated|q_b [8]),
+	.cin(\DUMMY|Add0~17 ),
+	.combout(\DUMMY|Add0~18_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|Add0~18 .lut_mask = 16'h3CC3;
+defparam \DUMMY|Add0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N26
+cycloneiii_lcell_comb \DUMMY|Add3~0 (
+// Equation(s):
+// \DUMMY|Add3~0_combout  = \DUMMY|Add0~14_combout  $ (VCC)
+// \DUMMY|Add3~1  = CARRY(\DUMMY|Add0~14_combout )
+
+	.dataa(gnd),
+	.datab(\DUMMY|Add0~14_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\DUMMY|Add3~0_combout ),
+	.cout(\DUMMY|Add3~1 ));
+// synopsys translate_off
+defparam \DUMMY|Add3~0 .lut_mask = 16'h33CC;
+defparam \DUMMY|Add3~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N28
+cycloneiii_lcell_comb \DUMMY|Add3~2 (
+// Equation(s):
+// \DUMMY|Add3~2_combout  = (\DUMMY|Add0~16_combout  & (!\DUMMY|Add3~1 )) # (!\DUMMY|Add0~16_combout  & ((\DUMMY|Add3~1 ) # (GND)))
+// \DUMMY|Add3~3  = CARRY((!\DUMMY|Add3~1 ) # (!\DUMMY|Add0~16_combout ))
+
+	.dataa(gnd),
+	.datab(\DUMMY|Add0~16_combout ),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\DUMMY|Add3~1 ),
+	.combout(\DUMMY|Add3~2_combout ),
+	.cout(\DUMMY|Add3~3 ));
+// synopsys translate_off
+defparam \DUMMY|Add3~2 .lut_mask = 16'h3C3F;
+defparam \DUMMY|Add3~2 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N30
+cycloneiii_lcell_comb \DUMMY|Add3~4 (
+// Equation(s):
+// \DUMMY|Add3~4_combout  = \DUMMY|Add0~18_combout  $ (\DUMMY|Add3~3 )
+
+	.dataa(\DUMMY|Add0~18_combout ),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\DUMMY|Add3~3 ),
+	.combout(\DUMMY|Add3~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|Add3~4 .lut_mask = 16'h5A5A;
+defparam \DUMMY|Add3~4 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: M9K_X25_Y23_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~4_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 8;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 8;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: M9K_X25_Y19_N0
+cycloneiii_ram_block \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 (
+	.portawe(\DUMMY|PULSE2|pulse~q ),
+	.portare(vcc),
+	.portaaddrstall(gnd),
+	.portbwe(gnd),
+	.portbre(\DUMMY|PULSE2|pulse~q ),
+	.portbaddrstall(gnd),
+	.clk0(\CLOCK_50~inputclkctrl_outclk ),
+	.clk1(\CLOCK_50~inputclkctrl_outclk ),
+	.ena0(\DUMMY|PULSE2|pulse~q ),
+	.ena1(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a0~0_combout ),
+	.ena2(vcc),
+	.ena3(vcc),
+	.clr0(gnd),
+	.clr1(gnd),
+	.portadatain({\DUMMY|Add3~2_combout }),
+	.portaaddr({\DUMMY|wraddr[12]~16_combout ,\DUMMY|wraddr[11]~14_combout ,\DUMMY|wraddr[10]~12_combout ,\DUMMY|wraddr[9]~10_combout ,\DUMMY|wraddr[8]~8_combout ,\DUMMY|wraddr[7]~6_combout ,\DUMMY|wraddr[6]~4_combout ,\DUMMY|wraddr[5]~2_combout ,\DUMMY|wraddr[4]~0_combout ,
+\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portabyteenamasks(1'b1),
+	.portbdatain(1'b0),
+	.portbaddr({\DUMMY|ctr [12],\DUMMY|ctr [11],\DUMMY|ctr [10],\DUMMY|ctr [9],\DUMMY|ctr [8],\DUMMY|ctr [7],\DUMMY|ctr [6],\DUMMY|ctr [5],\DUMMY|ctr [4],\DUMMY|ctr [3],\DUMMY|ctr [2],\DUMMY|ctr [1],\DUMMY|ctr [0]}),
+	.portbbyteenamasks(1'b1),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.portadataout(),
+	.portbdataout(\DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ));
+// synopsys translate_off
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .clk1_core_clock_enable = "ena1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "processor:DUMMY|delay_ram:DELAY|altsyncram:altsyncram_component|altsyncram_phq1:auto_generated|ALTSYNCRAM";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "dual_port";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 8192;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 9;
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1";
+defparam \DUMMY|DELAY|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N27
+dffeas \DUMMY|data_out[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add3~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[7] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N9
+dffeas \DUMMY|data_out[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[2] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N5
+dffeas \DUMMY|data_out[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[0] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N28
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~13 (
+// Equation(s):
+// \SPI_DAC|shift_reg~13_combout  = (!\SPI_DAC|dac_cs~q  & (\DUMMY|data_out [0] & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\DUMMY|data_out [0]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~13_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~13 .lut_mask = 16'h5000;
+defparam \SPI_DAC|shift_reg~13 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N29
+dffeas \SPI_DAC|shift_reg[2] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[2] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N7
+dffeas \DUMMY|data_out[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[1] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N26
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~12 (
+// Equation(s):
+// \SPI_DAC|shift_reg~12_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [2])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [1]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [2]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [2]),
+	.datac(\DUMMY|data_out [1]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~12_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~12 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~12 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N27
+dffeas \SPI_DAC|shift_reg[3] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[3] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N4
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~11 (
+// Equation(s):
+// \SPI_DAC|shift_reg~11_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q  & ((\SPI_DAC|shift_reg [3]))) # (!\SPI_DAC|dac_cs~q  & (\DUMMY|data_out [2])))) # (!\SPI_DAC|dac_start~q  & (((\SPI_DAC|shift_reg [3]))))
+
+	.dataa(\DUMMY|data_out [2]),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(\SPI_DAC|shift_reg [3]),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~11_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~11 .lut_mask = 16'hF0B8;
+defparam \SPI_DAC|shift_reg~11 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N5
+dffeas \SPI_DAC|shift_reg[4] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[4] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N11
+dffeas \DUMMY|data_out[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[3] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N2
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~10 (
+// Equation(s):
+// \SPI_DAC|shift_reg~10_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [4])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [3]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [4]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [4]),
+	.datac(\DUMMY|data_out [3]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~10_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~10 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~10 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N3
+dffeas \SPI_DAC|shift_reg[5] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[5] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N13
+dffeas \DUMMY|data_out[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[4] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N0
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~9 (
+// Equation(s):
+// \SPI_DAC|shift_reg~9_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [5])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [4]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [5]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [5]),
+	.datac(\DUMMY|data_out [4]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~9_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~9 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N1
+dffeas \SPI_DAC|shift_reg[6] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[6] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N15
+dffeas \DUMMY|data_out[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~10_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[5] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N18
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~8 (
+// Equation(s):
+// \SPI_DAC|shift_reg~8_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [6])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [5]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [6]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [6]),
+	.datac(\DUMMY|data_out [5]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~8_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~8 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~8 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N19
+dffeas \SPI_DAC|shift_reg[7] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~8_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[7] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N17
+dffeas \DUMMY|data_out[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add0~12_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[6] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N8
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~7 (
+// Equation(s):
+// \SPI_DAC|shift_reg~7_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [7])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [6]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [7]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [7]),
+	.datac(\DUMMY|data_out [6]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~7_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~7 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~7 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N9
+dffeas \SPI_DAC|shift_reg[8] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~7_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[8] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N14
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~6 (
+// Equation(s):
+// \SPI_DAC|shift_reg~6_combout  = (\SPI_DAC|dac_cs~q  & (((\SPI_DAC|shift_reg [8])))) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & (\DUMMY|data_out [7])) # (!\SPI_DAC|dac_start~q  & ((\SPI_DAC|shift_reg [8])))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\DUMMY|data_out [7]),
+	.datac(\SPI_DAC|shift_reg [8]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~6_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~6 .lut_mask = 16'hE4F0;
+defparam \SPI_DAC|shift_reg~6 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N15
+dffeas \SPI_DAC|shift_reg[9] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~6_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[9] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N29
+dffeas \DUMMY|data_out[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|Add3~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[8] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N12
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~5 (
+// Equation(s):
+// \SPI_DAC|shift_reg~5_combout  = (\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [9])) # (!\SPI_DAC|dac_cs~q  & ((\SPI_DAC|dac_start~q  & ((\DUMMY|data_out [8]))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [9]))))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|shift_reg [9]),
+	.datac(\DUMMY|data_out [8]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~5_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~5 .lut_mask = 16'hD8CC;
+defparam \SPI_DAC|shift_reg~5 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N13
+dffeas \SPI_DAC|shift_reg[10] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~5_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[10] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y21_N24
+cycloneiii_lcell_comb \DUMMY|data_out[9]~0 (
+// Equation(s):
+// \DUMMY|data_out[9]~0_combout  = !\DUMMY|Add3~4_combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(\DUMMY|Add3~4_combout ),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\DUMMY|data_out[9]~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \DUMMY|data_out[9]~0 .lut_mask = 16'h0F0F;
+defparam \DUMMY|data_out[9]~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y21_N25
+dffeas \DUMMY|data_out[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\DUMMY|data_out[9]~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\DUMMY|data_out [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \DUMMY|data_out[9] .is_wysiwyg = "true";
+defparam \DUMMY|data_out[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N26
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~4 (
+// Equation(s):
+// \SPI_DAC|shift_reg~4_combout  = (\SPI_DAC|dac_start~q  & ((\SPI_DAC|dac_cs~q  & (\SPI_DAC|shift_reg [10])) # (!\SPI_DAC|dac_cs~q  & ((\DUMMY|data_out [9]))))) # (!\SPI_DAC|dac_start~q  & (\SPI_DAC|shift_reg [10]))
+
+	.dataa(\SPI_DAC|shift_reg [10]),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(\DUMMY|data_out [9]),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~4_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~4 .lut_mask = 16'hAAE2;
+defparam \SPI_DAC|shift_reg~4 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N27
+dffeas \SPI_DAC|shift_reg[11] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~4_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[11] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N22
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~3 (
+// Equation(s):
+// \SPI_DAC|shift_reg~3_combout  = (\SPI_DAC|shift_reg [11]) # ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [11]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~3_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~3 .lut_mask = 16'hF5F0;
+defparam \SPI_DAC|shift_reg~3 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N23
+dffeas \SPI_DAC|shift_reg[12] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~3_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[12] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N30
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~2 (
+// Equation(s):
+// \SPI_DAC|shift_reg~2_combout  = (\SPI_DAC|shift_reg [12] & ((\SPI_DAC|dac_cs~q ) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [12]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~2_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~2 .lut_mask = 16'hA0F0;
+defparam \SPI_DAC|shift_reg~2 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N31
+dffeas \SPI_DAC|shift_reg[13] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~2_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[13] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N10
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~1 (
+// Equation(s):
+// \SPI_DAC|shift_reg~1_combout  = (\SPI_DAC|shift_reg [13]) # ((!\SPI_DAC|dac_cs~q  & \SPI_DAC|dac_start~q ))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(gnd),
+	.datac(\SPI_DAC|shift_reg [13]),
+	.datad(\SPI_DAC|dac_start~q ),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~1 .lut_mask = 16'hF5F0;
+defparam \SPI_DAC|shift_reg~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N11
+dffeas \SPI_DAC|shift_reg[14] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[14] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y23_N16
+cycloneiii_lcell_comb \SPI_DAC|shift_reg~0 (
+// Equation(s):
+// \SPI_DAC|shift_reg~0_combout  = (\SPI_DAC|shift_reg [14] & ((\SPI_DAC|dac_cs~q ) # (!\SPI_DAC|dac_start~q )))
+
+	.dataa(\SPI_DAC|dac_cs~q ),
+	.datab(\SPI_DAC|dac_start~q ),
+	.datac(gnd),
+	.datad(\SPI_DAC|shift_reg [14]),
+	.cin(gnd),
+	.combout(\SPI_DAC|shift_reg~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg~0 .lut_mask = 16'hBB00;
+defparam \SPI_DAC|shift_reg~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y23_N17
+dffeas \SPI_DAC|shift_reg[15] (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|shift_reg~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|shift_reg [15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|shift_reg[15] .is_wysiwyg = "true";
+defparam \SPI_DAC|shift_reg[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X20_Y25_N14
+cycloneiii_lcell_comb \SCK~0 (
+// Equation(s):
+// \SCK~0_combout  = (\SPI_ADC|clk_1MHz~q  & (!\SPI_DAC|clk_1MHz~q  & ((\SPI_DAC|dac_cs~q )))) # (!\SPI_ADC|clk_1MHz~q  & ((\SPI_ADC|adc_cs~q ) # ((!\SPI_DAC|clk_1MHz~q  & \SPI_DAC|dac_cs~q ))))
+
+	.dataa(\SPI_ADC|clk_1MHz~q ),
+	.datab(\SPI_DAC|clk_1MHz~q ),
+	.datac(\SPI_ADC|adc_cs~q ),
+	.datad(\SPI_DAC|dac_cs~q ),
+	.cin(gnd),
+	.combout(\SCK~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SCK~0 .lut_mask = 16'h7350;
+defparam \SCK~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y20_N28
+cycloneiii_lcell_comb \SPI_DAC|Equal2~0 (
+// Equation(s):
+// \SPI_DAC|Equal2~0_combout  = (!\SPI_DAC|state [4]) # (!\SPI_DAC|Equal1~0_combout )
+
+	.dataa(gnd),
+	.datab(\SPI_DAC|Equal1~0_combout ),
+	.datac(\SPI_DAC|state [4]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\SPI_DAC|Equal2~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_DAC|Equal2~0 .lut_mask = 16'h3F3F;
+defparam \SPI_DAC|Equal2~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y20_N29
+dffeas \SPI_DAC|dac_ld (
+	.clk(\SPI_DAC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_DAC|Equal2~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_DAC|dac_ld~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_DAC|dac_ld .is_wysiwyg = "true";
+defparam \SPI_DAC|dac_ld .power_up = "low";
+// synopsys translate_on
+
+// Location: IOIBUF_X0_Y25_N1
+cycloneiii_io_ibuf \SW[9]~input (
+	.i(SW[9]),
+	.ibar(gnd),
+	.o(\SW[9]~input_o ));
+// synopsys translate_off
+defparam \SW[9]~input .bus_hold = "false";
+defparam \SW[9]~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N8
+cycloneiii_lcell_comb \SPI_ADC|Selector6~0 (
+// Equation(s):
+// \SPI_ADC|Selector6~0_combout  = (\SPI_ADC|state [0]) # ((\SPI_ADC|state [1] & ((\SW[9]~input_o ))) # (!\SPI_ADC|state [1] & (\SPI_ADC|adc_start~q )))
+
+	.dataa(\SPI_ADC|adc_start~q ),
+	.datab(\SW[9]~input_o ),
+	.datac(\SPI_ADC|state [1]),
+	.datad(\SPI_ADC|state [0]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector6~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~0 .lut_mask = 16'hFFCA;
+defparam \SPI_ADC|Selector6~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y25_N30
+cycloneiii_lcell_comb \SPI_ADC|Selector6~1 (
+// Equation(s):
+// \SPI_ADC|Selector6~1_combout  = (!\SPI_ADC|state [3] & (!\SPI_ADC|state [2] & (\SPI_ADC|Selector6~0_combout  & !\SPI_ADC|state [4])))
+
+	.dataa(\SPI_ADC|state [3]),
+	.datab(\SPI_ADC|state [2]),
+	.datac(\SPI_ADC|Selector6~0_combout ),
+	.datad(\SPI_ADC|state [4]),
+	.cin(gnd),
+	.combout(\SPI_ADC|Selector6~1_combout ),
+	.cout());
+// synopsys translate_off
+defparam \SPI_ADC|Selector6~1 .lut_mask = 16'h0010;
+defparam \SPI_ADC|Selector6~1 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X21_Y25_N31
+dffeas \SPI_ADC|adc_din (
+	.clk(\SPI_ADC|clk_1MHz~clkctrl_outclk ),
+	.d(\SPI_ADC|Selector6~1_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\SPI_ADC|adc_din~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \SPI_ADC|adc_din .is_wysiwyg = "true";
+defparam \SPI_ADC|adc_din .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N4
+cycloneiii_lcell_comb \PWM_DC|count[1]~9 (
+// Equation(s):
+// \PWM_DC|count[1]~9_combout  = (\PWM_DC|count [0] & (\PWM_DC|count [1] $ (VCC))) # (!\PWM_DC|count [0] & (\PWM_DC|count [1] & VCC))
+// \PWM_DC|count[1]~10  = CARRY((\PWM_DC|count [0] & \PWM_DC|count [1]))
+
+	.dataa(\PWM_DC|count [0]),
+	.datab(\PWM_DC|count [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\PWM_DC|count[1]~9_combout ),
+	.cout(\PWM_DC|count[1]~10 ));
+// synopsys translate_off
+defparam \PWM_DC|count[1]~9 .lut_mask = 16'h6688;
+defparam \PWM_DC|count[1]~9 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N5
+dffeas \PWM_DC|count[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[1]~9_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[1] .is_wysiwyg = "true";
+defparam \PWM_DC|count[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N6
+cycloneiii_lcell_comb \PWM_DC|count[2]~11 (
+// Equation(s):
+// \PWM_DC|count[2]~11_combout  = (\PWM_DC|count [2] & (!\PWM_DC|count[1]~10 )) # (!\PWM_DC|count [2] & ((\PWM_DC|count[1]~10 ) # (GND)))
+// \PWM_DC|count[2]~12  = CARRY((!\PWM_DC|count[1]~10 ) # (!\PWM_DC|count [2]))
+
+	.dataa(\PWM_DC|count [2]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[1]~10 ),
+	.combout(\PWM_DC|count[2]~11_combout ),
+	.cout(\PWM_DC|count[2]~12 ));
+// synopsys translate_off
+defparam \PWM_DC|count[2]~11 .lut_mask = 16'h5A5F;
+defparam \PWM_DC|count[2]~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N7
+dffeas \PWM_DC|count[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[2]~11_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[2] .is_wysiwyg = "true";
+defparam \PWM_DC|count[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N8
+cycloneiii_lcell_comb \PWM_DC|count[3]~13 (
+// Equation(s):
+// \PWM_DC|count[3]~13_combout  = (\PWM_DC|count [3] & (\PWM_DC|count[2]~12  $ (GND))) # (!\PWM_DC|count [3] & (!\PWM_DC|count[2]~12  & VCC))
+// \PWM_DC|count[3]~14  = CARRY((\PWM_DC|count [3] & !\PWM_DC|count[2]~12 ))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[2]~12 ),
+	.combout(\PWM_DC|count[3]~13_combout ),
+	.cout(\PWM_DC|count[3]~14 ));
+// synopsys translate_off
+defparam \PWM_DC|count[3]~13 .lut_mask = 16'hC30C;
+defparam \PWM_DC|count[3]~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N9
+dffeas \PWM_DC|count[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[3]~13_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[3] .is_wysiwyg = "true";
+defparam \PWM_DC|count[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N10
+cycloneiii_lcell_comb \PWM_DC|count[4]~15 (
+// Equation(s):
+// \PWM_DC|count[4]~15_combout  = (\PWM_DC|count [4] & (!\PWM_DC|count[3]~14 )) # (!\PWM_DC|count [4] & ((\PWM_DC|count[3]~14 ) # (GND)))
+// \PWM_DC|count[4]~16  = CARRY((!\PWM_DC|count[3]~14 ) # (!\PWM_DC|count [4]))
+
+	.dataa(\PWM_DC|count [4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[3]~14 ),
+	.combout(\PWM_DC|count[4]~15_combout ),
+	.cout(\PWM_DC|count[4]~16 ));
+// synopsys translate_off
+defparam \PWM_DC|count[4]~15 .lut_mask = 16'h5A5F;
+defparam \PWM_DC|count[4]~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N11
+dffeas \PWM_DC|count[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[4]~15_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[4] .is_wysiwyg = "true";
+defparam \PWM_DC|count[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N12
+cycloneiii_lcell_comb \PWM_DC|count[5]~17 (
+// Equation(s):
+// \PWM_DC|count[5]~17_combout  = (\PWM_DC|count [5] & (\PWM_DC|count[4]~16  $ (GND))) # (!\PWM_DC|count [5] & (!\PWM_DC|count[4]~16  & VCC))
+// \PWM_DC|count[5]~18  = CARRY((\PWM_DC|count [5] & !\PWM_DC|count[4]~16 ))
+
+	.dataa(\PWM_DC|count [5]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[4]~16 ),
+	.combout(\PWM_DC|count[5]~17_combout ),
+	.cout(\PWM_DC|count[5]~18 ));
+// synopsys translate_off
+defparam \PWM_DC|count[5]~17 .lut_mask = 16'hA50A;
+defparam \PWM_DC|count[5]~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N13
+dffeas \PWM_DC|count[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[5]~17_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[5] .is_wysiwyg = "true";
+defparam \PWM_DC|count[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N14
+cycloneiii_lcell_comb \PWM_DC|count[6]~19 (
+// Equation(s):
+// \PWM_DC|count[6]~19_combout  = (\PWM_DC|count [6] & (!\PWM_DC|count[5]~18 )) # (!\PWM_DC|count [6] & ((\PWM_DC|count[5]~18 ) # (GND)))
+// \PWM_DC|count[6]~20  = CARRY((!\PWM_DC|count[5]~18 ) # (!\PWM_DC|count [6]))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[5]~18 ),
+	.combout(\PWM_DC|count[6]~19_combout ),
+	.cout(\PWM_DC|count[6]~20 ));
+// synopsys translate_off
+defparam \PWM_DC|count[6]~19 .lut_mask = 16'h3C3F;
+defparam \PWM_DC|count[6]~19 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N15
+dffeas \PWM_DC|count[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[6]~19_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[6] .is_wysiwyg = "true";
+defparam \PWM_DC|count[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N16
+cycloneiii_lcell_comb \PWM_DC|count[7]~21 (
+// Equation(s):
+// \PWM_DC|count[7]~21_combout  = (\PWM_DC|count [7] & (\PWM_DC|count[6]~20  $ (GND))) # (!\PWM_DC|count [7] & (!\PWM_DC|count[6]~20  & VCC))
+// \PWM_DC|count[7]~22  = CARRY((\PWM_DC|count [7] & !\PWM_DC|count[6]~20 ))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[6]~20 ),
+	.combout(\PWM_DC|count[7]~21_combout ),
+	.cout(\PWM_DC|count[7]~22 ));
+// synopsys translate_off
+defparam \PWM_DC|count[7]~21 .lut_mask = 16'hC30C;
+defparam \PWM_DC|count[7]~21 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N17
+dffeas \PWM_DC|count[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[7]~21_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[7] .is_wysiwyg = "true";
+defparam \PWM_DC|count[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N18
+cycloneiii_lcell_comb \PWM_DC|count[8]~23 (
+// Equation(s):
+// \PWM_DC|count[8]~23_combout  = (\PWM_DC|count [8] & (!\PWM_DC|count[7]~22 )) # (!\PWM_DC|count [8] & ((\PWM_DC|count[7]~22 ) # (GND)))
+// \PWM_DC|count[8]~24  = CARRY((!\PWM_DC|count[7]~22 ) # (!\PWM_DC|count [8]))
+
+	.dataa(gnd),
+	.datab(\PWM_DC|count [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|count[7]~22 ),
+	.combout(\PWM_DC|count[8]~23_combout ),
+	.cout(\PWM_DC|count[8]~24 ));
+// synopsys translate_off
+defparam \PWM_DC|count[8]~23 .lut_mask = 16'h3C3F;
+defparam \PWM_DC|count[8]~23 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N19
+dffeas \PWM_DC|count[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[8]~23_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[8] .is_wysiwyg = "true";
+defparam \PWM_DC|count[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X22_Y22_N20
+cycloneiii_lcell_comb \PWM_DC|count[9]~25 (
+// Equation(s):
+// \PWM_DC|count[9]~25_combout  = \PWM_DC|count[8]~24  $ (!\PWM_DC|count [9])
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\PWM_DC|count [9]),
+	.cin(\PWM_DC|count[8]~24 ),
+	.combout(\PWM_DC|count[9]~25_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|count[9]~25 .lut_mask = 16'hF00F;
+defparam \PWM_DC|count[9]~25 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X22_Y22_N21
+dffeas \PWM_DC|count[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|count[9]~25_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|count [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|count[9] .is_wysiwyg = "true";
+defparam \PWM_DC|count[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N25
+dffeas \PWM_DC|d[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [9]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[9] .is_wysiwyg = "true";
+defparam \PWM_DC|d[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N23
+dffeas \PWM_DC|d[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [8]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[8] .is_wysiwyg = "true";
+defparam \PWM_DC|d[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N21
+dffeas \PWM_DC|d[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [7]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[7] .is_wysiwyg = "true";
+defparam \PWM_DC|d[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N19
+dffeas \PWM_DC|d[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [6]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[6] .is_wysiwyg = "true";
+defparam \PWM_DC|d[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N17
+dffeas \PWM_DC|d[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [5]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[5] .is_wysiwyg = "true";
+defparam \PWM_DC|d[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N15
+dffeas \PWM_DC|d[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [4]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[4] .is_wysiwyg = "true";
+defparam \PWM_DC|d[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N13
+dffeas \PWM_DC|d[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [3]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[3] .is_wysiwyg = "true";
+defparam \PWM_DC|d[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N11
+dffeas \PWM_DC|d[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [2]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[2] .is_wysiwyg = "true";
+defparam \PWM_DC|d[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N9
+dffeas \PWM_DC|d[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [1]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[1] .is_wysiwyg = "true";
+defparam \PWM_DC|d[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: FF_X21_Y22_N7
+dffeas \PWM_DC|d[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(gnd),
+	.asdata(\DUMMY|data_out [0]),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(vcc),
+	.ena(\PULSE|pulse~q ),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|d [0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|d[0] .is_wysiwyg = "true";
+defparam \PWM_DC|d[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N6
+cycloneiii_lcell_comb \PWM_DC|LessThan0~1 (
+// Equation(s):
+// \PWM_DC|LessThan0~1_cout  = CARRY((!\PWM_DC|d [0] & \PWM_DC|count [0]))
+
+	.dataa(\PWM_DC|d [0]),
+	.datab(\PWM_DC|count [0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~1_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~1 .lut_mask = 16'h0044;
+defparam \PWM_DC|LessThan0~1 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N8
+cycloneiii_lcell_comb \PWM_DC|LessThan0~3 (
+// Equation(s):
+// \PWM_DC|LessThan0~3_cout  = CARRY((\PWM_DC|count [1] & (\PWM_DC|d [1] & !\PWM_DC|LessThan0~1_cout )) # (!\PWM_DC|count [1] & ((\PWM_DC|d [1]) # (!\PWM_DC|LessThan0~1_cout ))))
+
+	.dataa(\PWM_DC|count [1]),
+	.datab(\PWM_DC|d [1]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~1_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~3_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~3 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~3 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N10
+cycloneiii_lcell_comb \PWM_DC|LessThan0~5 (
+// Equation(s):
+// \PWM_DC|LessThan0~5_cout  = CARRY((\PWM_DC|d [2] & (\PWM_DC|count [2] & !\PWM_DC|LessThan0~3_cout )) # (!\PWM_DC|d [2] & ((\PWM_DC|count [2]) # (!\PWM_DC|LessThan0~3_cout ))))
+
+	.dataa(\PWM_DC|d [2]),
+	.datab(\PWM_DC|count [2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~3_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~5_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~5 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~5 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N12
+cycloneiii_lcell_comb \PWM_DC|LessThan0~7 (
+// Equation(s):
+// \PWM_DC|LessThan0~7_cout  = CARRY((\PWM_DC|d [3] & ((!\PWM_DC|LessThan0~5_cout ) # (!\PWM_DC|count [3]))) # (!\PWM_DC|d [3] & (!\PWM_DC|count [3] & !\PWM_DC|LessThan0~5_cout )))
+
+	.dataa(\PWM_DC|d [3]),
+	.datab(\PWM_DC|count [3]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~5_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~7_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~7 .lut_mask = 16'h002B;
+defparam \PWM_DC|LessThan0~7 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N14
+cycloneiii_lcell_comb \PWM_DC|LessThan0~9 (
+// Equation(s):
+// \PWM_DC|LessThan0~9_cout  = CARRY((\PWM_DC|d [4] & (\PWM_DC|count [4] & !\PWM_DC|LessThan0~7_cout )) # (!\PWM_DC|d [4] & ((\PWM_DC|count [4]) # (!\PWM_DC|LessThan0~7_cout ))))
+
+	.dataa(\PWM_DC|d [4]),
+	.datab(\PWM_DC|count [4]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~7_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~9_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~9 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~9 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N16
+cycloneiii_lcell_comb \PWM_DC|LessThan0~11 (
+// Equation(s):
+// \PWM_DC|LessThan0~11_cout  = CARRY((\PWM_DC|count [5] & (\PWM_DC|d [5] & !\PWM_DC|LessThan0~9_cout )) # (!\PWM_DC|count [5] & ((\PWM_DC|d [5]) # (!\PWM_DC|LessThan0~9_cout ))))
+
+	.dataa(\PWM_DC|count [5]),
+	.datab(\PWM_DC|d [5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~9_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~11_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~11 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~11 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N18
+cycloneiii_lcell_comb \PWM_DC|LessThan0~13 (
+// Equation(s):
+// \PWM_DC|LessThan0~13_cout  = CARRY((\PWM_DC|count [6] & ((!\PWM_DC|LessThan0~11_cout ) # (!\PWM_DC|d [6]))) # (!\PWM_DC|count [6] & (!\PWM_DC|d [6] & !\PWM_DC|LessThan0~11_cout )))
+
+	.dataa(\PWM_DC|count [6]),
+	.datab(\PWM_DC|d [6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~11_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~13_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~13 .lut_mask = 16'h002B;
+defparam \PWM_DC|LessThan0~13 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N20
+cycloneiii_lcell_comb \PWM_DC|LessThan0~15 (
+// Equation(s):
+// \PWM_DC|LessThan0~15_cout  = CARRY((\PWM_DC|count [7] & (\PWM_DC|d [7] & !\PWM_DC|LessThan0~13_cout )) # (!\PWM_DC|count [7] & ((\PWM_DC|d [7]) # (!\PWM_DC|LessThan0~13_cout ))))
+
+	.dataa(\PWM_DC|count [7]),
+	.datab(\PWM_DC|d [7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~13_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~15_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~15 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~15 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N22
+cycloneiii_lcell_comb \PWM_DC|LessThan0~17 (
+// Equation(s):
+// \PWM_DC|LessThan0~17_cout  = CARRY((\PWM_DC|d [8] & (\PWM_DC|count [8] & !\PWM_DC|LessThan0~15_cout )) # (!\PWM_DC|d [8] & ((\PWM_DC|count [8]) # (!\PWM_DC|LessThan0~15_cout ))))
+
+	.dataa(\PWM_DC|d [8]),
+	.datab(\PWM_DC|count [8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\PWM_DC|LessThan0~15_cout ),
+	.combout(),
+	.cout(\PWM_DC|LessThan0~17_cout ));
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~17 .lut_mask = 16'h004D;
+defparam \PWM_DC|LessThan0~17 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X21_Y22_N24
+cycloneiii_lcell_comb \PWM_DC|LessThan0~18 (
+// Equation(s):
+// \PWM_DC|LessThan0~18_combout  = (\PWM_DC|count [9] & ((\PWM_DC|LessThan0~17_cout ) # (!\PWM_DC|d [9]))) # (!\PWM_DC|count [9] & (!\PWM_DC|d [9] & \PWM_DC|LessThan0~17_cout ))
+
+	.dataa(\PWM_DC|count [9]),
+	.datab(\PWM_DC|d [9]),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\PWM_DC|LessThan0~17_cout ),
+	.combout(\PWM_DC|LessThan0~18_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|LessThan0~18 .lut_mask = 16'hB2B2;
+defparam \PWM_DC|LessThan0~18 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: LCCOMB_X24_Y21_N8
+cycloneiii_lcell_comb \PWM_DC|pwm_out~0 (
+// Equation(s):
+// \PWM_DC|pwm_out~0_combout  = !\PWM_DC|LessThan0~18_combout 
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(\PWM_DC|LessThan0~18_combout ),
+	.cin(gnd),
+	.combout(\PWM_DC|pwm_out~0_combout ),
+	.cout());
+// synopsys translate_off
+defparam \PWM_DC|pwm_out~0 .lut_mask = 16'h00FF;
+defparam \PWM_DC|pwm_out~0 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X24_Y21_N9
+dffeas \PWM_DC|pwm_out (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\PWM_DC|pwm_out~0_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\PWM_DC|pwm_out~q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \PWM_DC|pwm_out .is_wysiwyg = "true";
+defparam \PWM_DC|pwm_out .power_up = "low";
+// synopsys translate_on
+
+assign HEX0_D[0] = \HEX0_D[0]~output_o ;
+
+assign HEX0_D[1] = \HEX0_D[1]~output_o ;
+
+assign HEX0_D[2] = \HEX0_D[2]~output_o ;
+
+assign HEX0_D[3] = \HEX0_D[3]~output_o ;
+
+assign HEX0_D[4] = \HEX0_D[4]~output_o ;
+
+assign HEX0_D[5] = \HEX0_D[5]~output_o ;
+
+assign HEX0_D[6] = \HEX0_D[6]~output_o ;
+
+assign HEX1_D[0] = \HEX1_D[0]~output_o ;
+
+assign HEX1_D[1] = \HEX1_D[1]~output_o ;
+
+assign HEX1_D[2] = \HEX1_D[2]~output_o ;
+
+assign HEX1_D[3] = \HEX1_D[3]~output_o ;
+
+assign HEX1_D[4] = \HEX1_D[4]~output_o ;
+
+assign HEX1_D[5] = \HEX1_D[5]~output_o ;
+
+assign HEX1_D[6] = \HEX1_D[6]~output_o ;
+
+assign HEX2_D[0] = \HEX2_D[0]~output_o ;
+
+assign HEX2_D[1] = \HEX2_D[1]~output_o ;
+
+assign HEX2_D[2] = \HEX2_D[2]~output_o ;
+
+assign HEX2_D[3] = \HEX2_D[3]~output_o ;
+
+assign HEX2_D[4] = \HEX2_D[4]~output_o ;
+
+assign HEX2_D[5] = \HEX2_D[5]~output_o ;
+
+assign HEX2_D[6] = \HEX2_D[6]~output_o ;
+
+assign HEX3_D[0] = \HEX3_D[0]~output_o ;
+
+assign HEX3_D[1] = \HEX3_D[1]~output_o ;
+
+assign HEX3_D[2] = \HEX3_D[2]~output_o ;
+
+assign HEX3_D[3] = \HEX3_D[3]~output_o ;
+
+assign HEX3_D[4] = \HEX3_D[4]~output_o ;
+
+assign HEX3_D[5] = \HEX3_D[5]~output_o ;
+
+assign HEX3_D[6] = \HEX3_D[6]~output_o ;
+
+assign DAC_SDI = \DAC_SDI~output_o ;
+
+assign SCK = \SCK~output_o ;
+
+assign DAC_CS = \DAC_CS~output_o ;
+
+assign DAC_LD = \DAC_LD~output_o ;
+
+assign ADC_SDI = \ADC_SDI~output_o ;
+
+assign ADC_CS = \ADC_CS~output_o ;
+
+assign LEDG[0] = \LEDG[0]~output_o ;
+
+assign LEDG[1] = \LEDG[1]~output_o ;
+
+assign LEDG[2] = \LEDG[2]~output_o ;
+
+assign LEDG[3] = \LEDG[3]~output_o ;
+
+assign LEDG[4] = \LEDG[4]~output_o ;
+
+assign LEDG[5] = \LEDG[5]~output_o ;
+
+assign LEDG[6] = \LEDG[6]~output_o ;
+
+assign LEDG[7] = \LEDG[7]~output_o ;
+
+assign LEDG[8] = \LEDG[8]~output_o ;
+
+assign LEDG[9] = \LEDG[9]~output_o ;
+
+assign PWM_OUT = \PWM_OUT~output_o ;
+
+endmodule
diff --git a/part_4/ex16/simulation/modelsim/top_min_1200mv_0c_v_fast.sdo b/part_4/ex16/simulation/modelsim/top_min_1200mv_0c_v_fast.sdo
new file mode 100755
index 0000000..e557499
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_min_1200mv_0c_v_fast.sdo
@@ -0,0 +1,8658 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP3C16F484C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "top")
+  (DATE "02/18/2014 18:26:57")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (374:374:374) (415:415:415))
+        (IOPATH i o (1364:1364:1364) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (349:349:349) (381:381:381))
+        (IOPATH i o (1364:1364:1364) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (433:433:433) (469:469:469))
+        (IOPATH i o (1374:1374:1374) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (409:409:409) (451:451:451))
+        (IOPATH i o (1374:1374:1374) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (405:405:405) (446:446:446))
+        (IOPATH i o (1374:1374:1374) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (417:417:417) (463:463:463))
+        (IOPATH i o (1364:1364:1364) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (451:451:451) (411:411:411))
+        (IOPATH i o (1281:1281:1281) (1364:1364:1364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (273:273:273) (250:250:250))
+        (IOPATH i o (1301:1301:1301) (1384:1384:1384))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (235:235:235) (257:257:257))
+        (IOPATH i o (1384:1384:1384) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (237:237:237) (258:258:258))
+        (IOPATH i o (1374:1374:1374) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (255:255:255) (233:233:233))
+        (IOPATH i o (1301:1301:1301) (1384:1384:1384))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (252:252:252) (231:231:231))
+        (IOPATH i o (1301:1301:1301) (1384:1384:1384))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (554:554:554) (503:503:503))
+        (IOPATH i o (1281:1281:1281) (1364:1364:1364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (429:429:429) (396:396:396))
+        (IOPATH i o (1301:1301:1301) (1384:1384:1384))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (338:338:338) (363:363:363))
+        (IOPATH i o (1364:1364:1364) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (244:244:244) (266:266:266))
+        (IOPATH i o (1384:1384:1384) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (312:312:312) (343:343:343))
+        (IOPATH i o (1384:1384:1384) (1301:1301:1301))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (275:275:275) (250:250:250))
+        (IOPATH i o (1281:1281:1281) (1364:1364:1364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (235:235:235) (255:255:255))
+        (IOPATH i o (1394:1394:1394) (1311:1311:1311))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (305:305:305) (339:339:339))
+        (IOPATH i o (1404:1404:1404) (1321:1321:1321))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (470:470:470) (519:519:519))
+        (IOPATH i o (1374:1374:1374) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (700:700:700) (636:636:636))
+        (IOPATH i o (1321:1321:1321) (1404:1404:1404))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (692:692:692) (630:630:630))
+        (IOPATH i o (1321:1321:1321) (1404:1404:1404))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (838:838:838) (759:759:759))
+        (IOPATH i o (1301:1301:1301) (1384:1384:1384))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (838:838:838) (759:759:759))
+        (IOPATH i o (1301:1301:1301) (1384:1384:1384))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_SDI\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1079:1079:1079) (1264:1264:1264))
+        (IOPATH i o (1374:1374:1374) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE SCK\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1208:1208:1208) (1334:1334:1334))
+        (IOPATH i o (1364:1364:1364) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_CS\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (791:791:791) (697:697:697))
+        (IOPATH i o (1281:1281:1281) (1364:1364:1364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_LD\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (820:820:820) (934:934:934))
+        (IOPATH i o (1364:1364:1364) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE ADC_SDI\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1522:1522:1522) (1768:1768:1768))
+        (IOPATH i o (1374:1374:1374) (1291:1291:1291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE ADC_CS\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1877:1877:1877) (1629:1629:1629))
+        (IOPATH i o (1291:1291:1291) (1374:1374:1374))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (826:826:826) (931:931:931))
+        (IOPATH i o (1518:1518:1518) (1442:1442:1442))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (867:867:867) (972:972:972))
+        (IOPATH i o (1518:1518:1518) (1442:1442:1442))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (890:890:890) (1015:1015:1015))
+        (IOPATH i o (2979:2979:2979) (2713:2713:2713))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (655:655:655) (746:746:746))
+        (IOPATH i o (1528:1528:1528) (1452:1452:1452))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (733:733:733) (820:820:820))
+        (IOPATH i o (1538:1538:1538) (1462:1462:1462))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (816:816:816) (897:897:897))
+        (IOPATH i o (1538:1538:1538) (1462:1462:1462))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (671:671:671) (745:745:745))
+        (IOPATH i o (1548:1548:1548) (1472:1472:1472))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[7\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (583:583:583) (663:663:663))
+        (IOPATH i o (1558:1558:1558) (1482:1482:1482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[8\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (598:598:598) (680:680:680))
+        (IOPATH i o (1558:1558:1558) (1482:1482:1482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[9\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (688:688:688) (776:776:776))
+        (IOPATH i o (1558:1558:1558) (1482:1482:1482))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE PWM_OUT\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1547:1547:1547) (1792:1792:1792))
+        (IOPATH i o (1364:1364:1364) (1281:1281:1281))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[8\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (302:302:302) (861:861:861))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[7\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (302:302:302) (861:861:861))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[6\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (292:292:292) (851:851:851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[5\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (292:292:292) (851:851:851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[4\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (292:292:292) (851:851:851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[10\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1794:1794:1794) (2030:2030:2030))
+        (PORT datab (1829:1829:1829) (2051:2051:2051))
+        (PORT datac (1799:1799:1799) (2016:2016:2016))
+        (PORT datad (1845:1845:1845) (2076:2076:2076))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[3\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (302:302:302) (861:861:861))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[2\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (292:292:292) (851:851:851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[0\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (292:292:292) (851:851:851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[1\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (292:292:292) (851:851:851))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[14\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1802:1802:1802) (2019:2019:2019))
+        (PORT datab (1821:1821:1821) (2045:2045:2045))
+        (PORT datac (1788:1788:1788) (1998:1998:1998))
+        (PORT datad (1839:1839:1839) (2062:2062:2062))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[13\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1801:1801:1801) (2017:2017:2017))
+        (PORT datab (1816:1816:1816) (2037:2037:2037))
+        (PORT datac (1792:1792:1792) (2003:2003:2003))
+        (PORT datad (1844:1844:1844) (2068:2068:2068))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (167:167:167) (158:158:158))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[9\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1793:1793:1793) (2028:2028:2028))
+        (PORT datab (1830:1830:1830) (2051:2051:2051))
+        (PORT datac (1799:1799:1799) (2016:2016:2016))
+        (PORT datad (1845:1845:1845) (2077:2077:2077))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[12\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1799:1799:1799) (2016:2016:2016))
+        (PORT datab (1816:1816:1816) (2036:2036:2036))
+        (PORT datac (1790:1790:1790) (2001:2001:2001))
+        (PORT datad (1842:1842:1842) (2066:2066:2066))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[12\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1794:1794:1794) (2029:2029:2029))
+        (PORT datab (1830:1830:1830) (2052:2052:2052))
+        (PORT datac (1799:1799:1799) (2016:2016:2016))
+        (PORT datad (1846:1846:1846) (2078:2078:2078))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[11\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1790:1790:1790) (2025:2025:2025))
+        (PORT datab (1832:1832:1832) (2054:2054:2054))
+        (PORT datac (1807:1807:1807) (2024:2024:2024))
+        (PORT datad (1853:1853:1853) (2084:2084:2084))
+        (IOPATH dataa combout (181:181:181) (175:175:175))
+        (IOPATH datab combout (192:192:192) (188:188:188))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[11\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1799:1799:1799) (2016:2016:2016))
+        (PORT datab (1816:1816:1816) (2036:2036:2036))
+        (PORT datac (1790:1790:1790) (2000:2000:2000))
+        (PORT datad (1842:1842:1842) (2065:2065:2065))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[10\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1801:1801:1801) (2018:2018:2018))
+        (PORT datab (1816:1816:1816) (2037:2037:2037))
+        (PORT datac (1793:1793:1793) (2004:2004:2004))
+        (PORT datad (1844:1844:1844) (2069:2069:2069))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[9\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1802:1802:1802) (2019:2019:2019))
+        (PORT datab (1821:1821:1821) (2045:2045:2045))
+        (PORT datac (1788:1788:1788) (1998:1998:1998))
+        (PORT datad (1839:1839:1839) (2062:2062:2062))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (182:182:182) (193:193:193))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[4\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1790:1790:1790) (2025:2025:2025))
+        (PORT datab (1832:1832:1832) (2054:2054:2054))
+        (PORT datac (1807:1807:1807) (2023:2023:2023))
+        (PORT datad (1852:1852:1852) (2084:2084:2084))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[3\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1832:1832:1832) (2054:2054:2054))
+        (PORT datac (1807:1807:1807) (2021:2021:2021))
+        (PORT datad (1855:1855:1855) (2088:2088:2088))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[2\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1807:1807:1807) (2021:2021:2021))
+        (PORT datad (1855:1855:1855) (2088:2088:2088))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[1\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (433:433:433))
+        (PORT datab (1844:1844:1844) (2081:2081:2081))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[2\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (364:364:364) (417:417:417))
+        (PORT datab (353:353:353) (411:411:411))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[3\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (383:383:383) (444:444:444))
+        (PORT datab (354:354:354) (414:414:414))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[4\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (367:367:367) (428:428:428))
+        (PORT datab (360:360:360) (413:413:413))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[5\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (372:372:372) (434:434:434))
+        (PORT datab (385:385:385) (452:452:452))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[6\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (429:429:429))
+        (PORT datab (354:354:354) (413:413:413))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[7\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (367:367:367) (435:435:435))
+        (PORT datab (355:355:355) (414:414:414))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[8\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (369:369:369) (431:431:431))
+        (PORT datab (387:387:387) (451:451:451))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[9\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (334:334:334) (393:393:393))
+        (PORT datab (386:386:386) (454:454:454))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[10\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (369:369:369) (427:427:427))
+        (PORT datab (448:448:448) (508:508:508))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (189:189:189) (225:225:225))
+        (PORT datab (1743:1743:1743) (1944:1944:1944))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1754:1754:1754) (1963:1963:1963))
+        (PORT datab (278:278:278) (314:314:314))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (176:176:176) (214:214:214))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (172:172:172) (209:209:209))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1756:1756:1756) (1966:1966:1966))
+        (PORT datab (292:292:292) (333:333:333))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1753:1753:1753) (1965:1965:1965))
+        (PORT datab (171:171:171) (208:208:208))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[13\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1794:1794:1794) (2030:2030:2030))
+        (PORT datab (1831:1831:1831) (2053:2053:2053))
+        (PORT datac (1801:1801:1801) (2017:2017:2017))
+        (PORT datad (1847:1847:1847) (2078:2078:2078))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[11\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (369:369:369) (437:437:437))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[12\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (388:388:388) (452:452:452))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[13\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (347:347:347) (403:403:403))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (187:187:187) (224:224:224))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (189:189:189) (227:227:227))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1753:1753:1753) (1961:1961:1961))
+        (PORT datab (186:186:186) (222:222:222))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[14\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1792:1792:1792) (2028:2028:2028))
+        (PORT datab (1829:1829:1829) (2051:2051:2051))
+        (PORT datac (1803:1803:1803) (2021:2021:2021))
+        (PORT datad (1849:1849:1849) (2081:2081:2081))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[14\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (336:336:336) (380:380:380))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1752:1752:1752) (1962:1962:1962))
+        (PORT datab (170:170:170) (207:207:207))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~20)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (706:706:706) (828:828:828))
+        (PORT datab (606:606:606) (701:701:701))
+        (PORT datac (585:585:585) (668:668:668))
+        (PORT datad (688:688:688) (806:806:806))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (713:713:713) (834:834:834))
+        (PORT datab (599:599:599) (691:691:691))
+        (PORT datac (582:582:582) (661:661:661))
+        (PORT datad (692:692:692) (811:811:811))
+        (IOPATH dataa combout (158:158:158) (173:173:173))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (706:706:706) (829:829:829))
+        (PORT datab (605:605:605) (697:697:697))
+        (PORT datac (585:585:585) (666:666:666))
+        (PORT datad (688:688:688) (807:807:807))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (192:192:192) (188:188:188))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (207:207:207) (253:253:253))
+        (PORT datab (202:202:202) (245:245:245))
+        (PORT datac (558:558:558) (641:641:641))
+        (PORT datad (175:175:175) (204:204:204))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (207:207:207) (252:252:252))
+        (PORT datab (202:202:202) (245:245:245))
+        (PORT datac (558:558:558) (641:641:641))
+        (PORT datad (175:175:175) (204:204:204))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (205:205:205) (252:252:252))
+        (PORT datab (204:204:204) (245:245:245))
+        (PORT datac (557:557:557) (637:637:637))
+        (PORT datad (173:173:173) (201:201:201))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (192:192:192) (188:188:188))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (580:580:580) (677:677:677))
+        (PORT datab (123:123:123) (158:158:158))
+        (PORT datac (108:108:108) (137:137:137))
+        (PORT datad (106:106:106) (129:129:129))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (586:586:586) (684:684:684))
+        (PORT datab (117:117:117) (150:150:150))
+        (PORT datac (103:103:103) (129:129:129))
+        (PORT datad (102:102:102) (123:123:123))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (585:585:585) (683:683:683))
+        (PORT datab (120:120:120) (153:153:153))
+        (PORT datac (105:105:105) (131:131:131))
+        (PORT datad (104:104:104) (124:124:124))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (204:204:204) (251:251:251))
+        (PORT datab (191:191:191) (233:233:233))
+        (PORT datac (175:175:175) (213:213:213))
+        (PORT datad (541:541:541) (620:620:620))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (206:206:206) (254:254:254))
+        (PORT datab (186:186:186) (226:226:226))
+        (PORT datac (176:176:176) (210:210:210))
+        (PORT datad (544:544:544) (623:623:623))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (205:205:205) (253:253:253))
+        (PORT datab (189:189:189) (231:231:231))
+        (PORT datac (176:176:176) (210:210:210))
+        (PORT datad (540:540:540) (619:619:619))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (122:122:122) (158:158:158))
+        (PORT datab (605:605:605) (705:705:705))
+        (PORT datac (109:109:109) (138:138:138))
+        (PORT datad (106:106:106) (129:129:129))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (121:121:121) (157:157:157))
+        (PORT datab (602:602:602) (701:701:701))
+        (PORT datac (108:108:108) (134:134:134))
+        (PORT datad (102:102:102) (125:125:125))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (167:167:167) (176:176:176))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (121:121:121) (157:157:157))
+        (PORT datab (600:600:600) (698:698:698))
+        (PORT datac (108:108:108) (137:137:137))
+        (PORT datad (102:102:102) (123:123:123))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (204:204:204) (251:251:251))
+        (PORT datab (312:312:312) (362:362:362))
+        (PORT datac (697:697:697) (798:798:798))
+        (PORT datad (174:174:174) (203:203:203))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (206:206:206) (254:254:254))
+        (PORT datab (316:316:316) (365:365:365))
+        (PORT datac (693:693:693) (793:793:793))
+        (PORT datad (176:176:176) (204:204:204))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (206:206:206) (254:254:254))
+        (PORT datab (314:314:314) (362:362:362))
+        (PORT datac (693:693:693) (794:794:794))
+        (PORT datad (175:175:175) (201:201:201))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (138:138:138) (181:181:181))
+        (PORT datab (706:706:706) (844:844:844))
+        (PORT datac (116:116:116) (150:150:150))
+        (PORT datad (114:114:114) (139:139:139))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (191:191:191) (188:188:188))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (181:181:181))
+        (PORT datab (711:711:711) (849:849:849))
+        (PORT datac (123:123:123) (159:159:159))
+        (PORT datad (120:120:120) (147:147:147))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (180:180:180))
+        (PORT datab (709:709:709) (847:847:847))
+        (PORT datac (119:119:119) (157:157:157))
+        (PORT datad (116:116:116) (145:145:145))
+        (IOPATH dataa combout (170:170:170) (165:165:165))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (185:185:185))
+        (PORT datab (707:707:707) (844:844:844))
+        (PORT datac (114:114:114) (147:147:147))
+        (PORT datad (112:112:112) (138:138:138))
+        (IOPATH dataa combout (165:165:165) (159:159:159))
+        (IOPATH datab combout (192:192:192) (188:188:188))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (179:179:179))
+        (PORT datab (708:708:708) (846:846:846))
+        (PORT datac (122:122:122) (156:156:156))
+        (PORT datad (118:118:118) (145:145:145))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (179:179:179))
+        (PORT datab (706:706:706) (844:844:844))
+        (PORT datac (118:118:118) (152:152:152))
+        (PORT datad (115:115:115) (141:141:141))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (180:180:180))
+        (PORT datab (711:711:711) (849:849:849))
+        (PORT datac (123:123:123) (159:159:159))
+        (PORT datad (119:119:119) (147:147:147))
+        (IOPATH dataa combout (192:192:192) (184:184:184))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (711:711:711) (832:832:832))
+        (PORT datab (604:604:604) (698:698:698))
+        (PORT datac (583:583:583) (667:667:667))
+        (PORT datad (687:687:687) (805:805:805))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (709:709:709) (829:829:829))
+        (PORT datab (603:603:603) (695:695:695))
+        (PORT datac (584:584:584) (668:668:668))
+        (PORT datad (687:687:687) (806:806:806))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (167:167:167) (176:176:176))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (165:165:165) (196:196:196))
+        (PORT datad (168:168:168) (195:195:195))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (582:582:582) (679:679:679))
+        (PORT datab (122:122:122) (155:155:155))
+        (PORT datac (108:108:108) (133:133:133))
+        (PORT datad (106:106:106) (126:126:126))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A7\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (713:713:713) (834:834:834))
+        (PORT datab (599:599:599) (690:690:690))
+        (PORT datad (692:692:692) (811:811:811))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (248:248:248))
+        (PORT datab (207:207:207) (248:248:248))
+        (PORT datac (556:556:556) (637:637:637))
+        (PORT datad (171:171:171) (198:198:198))
+        (IOPATH dataa combout (188:188:188) (179:179:179))
+        (IOPATH datab combout (196:196:196) (205:205:205))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (131:131:131) (174:174:174))
+        (PORT datab (136:136:136) (176:176:176))
+        (PORT datac (199:199:199) (242:242:242))
+        (PORT datad (114:114:114) (143:143:143))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (548:548:548) (641:641:641))
+        (PORT datab (556:556:556) (645:645:645))
+        (PORT datac (587:587:587) (666:666:666))
+        (PORT datad (679:679:679) (796:796:796))
+        (IOPATH dataa combout (172:172:172) (163:163:163))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (704:704:704) (836:836:836))
+        (PORT datab (601:601:601) (695:695:695))
+        (PORT datad (93:93:93) (109:109:109))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (158:158:158))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (132:132:132) (176:176:176))
+        (PORT datab (139:139:139) (173:173:173))
+        (PORT datac (198:198:198) (242:242:242))
+        (PORT datad (118:118:118) (142:142:142))
+        (IOPATH dataa combout (159:159:159) (173:173:173))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (194:194:194) (233:233:233))
+        (PORT datac (283:283:283) (323:323:323))
+        (PORT datad (169:169:169) (198:198:198))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A7\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (712:712:712) (833:833:833))
+        (PORT datad (690:690:690) (810:810:810))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (131:131:131) (174:174:174))
+        (PORT datab (186:186:186) (223:223:223))
+        (PORT datac (553:553:553) (625:625:625))
+        (PORT datad (114:114:114) (143:143:143))
+        (IOPATH dataa combout (186:186:186) (179:179:179))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (172:172:172))
+        (PORT datab (136:136:136) (171:171:171))
+        (PORT datac (205:205:205) (250:250:250))
+        (PORT datad (116:116:116) (142:142:142))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (192:192:192) (231:231:231))
+        (PORT datab (171:171:171) (208:208:208))
+        (PORT datac (177:177:177) (212:212:212))
+        (PORT datad (167:167:167) (195:195:195))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (703:703:703) (825:825:825))
+        (PORT datab (557:557:557) (646:646:646))
+        (PORT datac (588:588:588) (668:668:668))
+        (PORT datad (689:689:689) (807:807:807))
+        (IOPATH dataa combout (170:170:170) (165:165:165))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (173:173:173))
+        (PORT datab (137:137:137) (172:172:172))
+        (PORT datac (201:201:201) (244:244:244))
+        (PORT datad (116:116:116) (141:141:141))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (193:193:193) (234:234:234))
+        (PORT datab (708:708:708) (813:813:813))
+        (PORT datac (319:319:319) (363:363:363))
+        (PORT datad (170:170:170) (196:196:196))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (248:248:248))
+        (PORT datab (190:190:190) (230:230:230))
+        (PORT datac (176:176:176) (210:210:210))
+        (PORT datad (541:541:541) (620:620:620))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (124:124:124) (159:159:159))
+        (PORT datab (118:118:118) (152:152:152))
+        (PORT datac (104:104:104) (132:132:132))
+        (PORT datad (106:106:106) (126:126:126))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (120:120:120) (158:158:158))
+        (PORT datab (122:122:122) (157:157:157))
+        (PORT datac (108:108:108) (137:137:137))
+        (PORT datad (102:102:102) (123:123:123))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (120:120:120) (158:158:158))
+        (PORT datab (603:603:603) (701:701:701))
+        (PORT datac (108:108:108) (134:134:134))
+        (PORT datad (103:103:103) (126:126:126))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (120:120:120) (164:164:164))
+        (PORT datab (118:118:118) (151:151:151))
+        (PORT datac (103:103:103) (129:129:129))
+        (PORT datad (107:107:107) (129:129:129))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (182:182:182) (193:193:193))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (326:326:326) (382:382:382))
+        (PORT datab (197:197:197) (241:241:241))
+        (PORT datac (285:285:285) (327:327:327))
+        (PORT datad (301:301:301) (343:343:343))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (384:384:384))
+        (PORT datab (194:194:194) (237:237:237))
+        (PORT datac (288:288:288) (330:330:330))
+        (PORT datad (303:303:303) (344:344:344))
+        (IOPATH dataa combout (188:188:188) (196:196:196))
+        (IOPATH datab combout (190:190:190) (197:197:197))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (328:328:328) (387:387:387))
+        (PORT datab (194:194:194) (237:237:237))
+        (PORT datac (288:288:288) (330:330:330))
+        (PORT datad (304:304:304) (347:347:347))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (201:201:201) (247:247:247))
+        (PORT datab (311:311:311) (359:359:359))
+        (PORT datac (695:695:695) (795:795:795))
+        (PORT datad (173:173:173) (200:200:200))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (180:180:180))
+        (PORT datab (131:131:131) (171:171:171))
+        (PORT datac (189:189:189) (232:232:232))
+        (PORT datad (288:288:288) (330:330:330))
+        (IOPATH dataa combout (181:181:181) (180:180:180))
+        (IOPATH datab combout (160:160:160) (176:176:176))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (134:134:134) (179:179:179))
+        (PORT datab (133:133:133) (173:173:173))
+        (PORT datac (190:190:190) (234:234:234))
+        (PORT datad (288:288:288) (331:331:331))
+        (IOPATH dataa combout (181:181:181) (180:180:180))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (181:181:181))
+        (PORT datab (138:138:138) (181:181:181))
+        (PORT datac (195:195:195) (240:240:240))
+        (PORT datad (284:284:284) (327:327:327))
+        (IOPATH dataa combout (188:188:188) (193:193:193))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (180:180:180))
+        (PORT datab (137:137:137) (178:178:178))
+        (PORT datac (193:193:193) (237:237:237))
+        (PORT datad (285:285:285) (328:328:328))
+        (IOPATH dataa combout (181:181:181) (193:193:193))
+        (IOPATH datab combout (190:190:190) (188:188:188))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (179:179:179))
+        (PORT datab (137:137:137) (177:177:177))
+        (PORT datac (193:193:193) (236:236:236))
+        (PORT datad (285:285:285) (328:328:328))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (182:182:182))
+        (PORT datab (139:139:139) (181:181:181))
+        (PORT datac (196:196:196) (240:240:240))
+        (PORT datad (284:284:284) (326:326:326))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (180:180:180))
+        (PORT datab (134:134:134) (178:178:178))
+        (PORT datac (193:193:193) (238:238:238))
+        (PORT datad (286:286:286) (327:327:327))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (329:329:329) (387:387:387))
+        (PORT datab (195:195:195) (237:237:237))
+        (PORT datac (288:288:288) (330:330:330))
+        (PORT datad (304:304:304) (347:347:347))
+        (IOPATH dataa combout (195:195:195) (193:193:193))
+        (IOPATH datab combout (196:196:196) (192:192:192))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A14\|WideOr0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (181:181:181) (219:219:219))
+        (PORT datab (302:302:302) (351:351:351))
+        (PORT datac (203:203:203) (247:247:247))
+        (PORT datad (114:114:114) (139:139:139))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (129:129:129) (170:170:170))
+        (PORT datab (135:135:135) (170:170:170))
+        (PORT datac (204:204:204) (248:248:248))
+        (PORT datad (114:114:114) (139:139:139))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (182:182:182) (221:221:221))
+        (PORT datab (192:192:192) (230:230:230))
+        (PORT datac (177:177:177) (211:211:211))
+        (PORT datad (168:168:168) (195:195:195))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (537:537:537) (605:605:605))
+        (PORT datad (584:584:584) (662:662:662))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (120:120:120) (161:161:161))
+        (PORT datab (118:118:118) (154:154:154))
+        (PORT datac (104:104:104) (133:133:133))
+        (PORT datad (103:103:103) (128:128:128))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (487:487:487) (571:571:571))
+        (PORT datab (590:590:590) (674:674:674))
+        (PORT datac (120:120:120) (158:158:158))
+        (PORT datad (585:585:585) (668:668:668))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (482:482:482) (564:564:564))
+        (PORT datab (588:588:588) (671:671:671))
+        (PORT datac (125:125:125) (161:161:161))
+        (PORT datad (588:588:588) (669:669:669))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (182:182:182) (181:181:181))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (112:112:112) (144:144:144))
+        (PORT datad (102:102:102) (122:122:122))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (481:481:481) (565:565:565))
+        (PORT datab (587:587:587) (672:672:672))
+        (PORT datac (125:125:125) (164:164:164))
+        (PORT datad (587:587:587) (670:670:670))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (177:177:177))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (608:608:608) (693:693:693))
+        (PORT datab (587:587:587) (670:670:670))
+        (PORT datac (536:536:536) (604:604:604))
+        (PORT datad (587:587:587) (668:668:668))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (166:166:166) (158:158:158))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (111:111:111) (140:140:140))
+        (PORT datac (470:470:470) (546:546:546))
+        (PORT datad (91:91:91) (108:108:108))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (485:485:485) (567:567:567))
+        (PORT datab (591:591:591) (674:674:674))
+        (PORT datac (119:119:119) (154:154:154))
+        (PORT datad (585:585:585) (664:664:664))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (167:167:167) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (484:484:484) (569:569:569))
+        (PORT datab (588:588:588) (672:672:672))
+        (PORT datac (123:123:123) (161:161:161))
+        (PORT datad (586:586:586) (670:670:670))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (160:160:160) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (480:480:480) (562:562:562))
+        (PORT datab (586:586:586) (669:669:669))
+        (PORT datac (126:126:126) (163:163:163))
+        (PORT datad (590:590:590) (668:668:668))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (109:109:109) (142:142:142))
+        (PORT datab (121:121:121) (153:153:153))
+        (PORT datac (93:93:93) (113:113:113))
+        (PORT datad (106:106:106) (126:126:126))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (481:481:481) (563:563:563))
+        (PORT datab (587:587:587) (670:670:670))
+        (PORT datac (127:127:127) (165:165:165))
+        (PORT datad (592:592:592) (669:669:669))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (161:161:161) (174:174:174))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (112:112:112) (144:144:144))
+        (PORT datac (99:99:99) (124:124:124))
+        (PORT datad (163:163:163) (192:192:192))
+        (IOPATH datab combout (166:166:166) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (117:117:117) (148:148:148))
+        (PORT datab (124:124:124) (155:155:155))
+        (PORT datac (98:98:98) (124:124:124))
+        (PORT datad (106:106:106) (129:129:129))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (481:481:481) (563:563:563))
+        (PORT datab (587:587:587) (669:669:669))
+        (PORT datac (127:127:127) (164:164:164))
+        (PORT datad (591:591:591) (668:668:668))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (105:105:105) (134:134:134))
+        (PORT datac (193:193:193) (224:224:224))
+        (PORT datad (102:102:102) (124:124:124))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A23\|WideOr0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (551:551:551) (643:643:643))
+        (PORT datab (696:696:696) (797:797:797))
+        (PORT datac (583:583:583) (662:662:662))
+        (PORT datad (586:586:586) (670:670:670))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A23\|WideOr0\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (708:708:708) (828:828:828))
+        (PORT datab (556:556:556) (646:646:646))
+        (PORT datac (91:91:91) (112:112:112))
+        (PORT datad (687:687:687) (805:805:805))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE CLOCK_50\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (342:342:342) (901:901:901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|clk_1MHz\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE CLOCK_50\~inputclkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (97:97:97) (82:82:82))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (135:135:135) (188:188:188))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (133:133:133) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (104:104:104) (133:133:133))
+        (PORT datac (211:211:211) (260:260:260))
+        (PORT datad (102:102:102) (125:125:125))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (137:137:137) (186:186:186))
+        (IOPATH datab combout (167:167:167) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (105:105:105) (133:133:133))
+        (PORT datac (211:211:211) (260:260:260))
+        (PORT datad (102:102:102) (125:125:125))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (188:188:188) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (209:209:209) (257:257:257))
+        (PORT datad (108:108:108) (131:131:131))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (139:139:139) (193:193:193))
+        (PORT datab (139:139:139) (190:190:190))
+        (PORT datac (121:121:121) (163:163:163))
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (121:121:121) (155:155:155))
+        (PORT datad (133:133:133) (171:171:171))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|clk_1MHz)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1293:1293:1293) (1159:1159:1159))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_DAC\|clk_1MHz\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (476:476:476) (531:531:531))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[0\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (140:140:140) (188:188:188))
+        (IOPATH datab combout (167:167:167) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (144:144:144) (191:191:191))
+        (IOPATH datab combout (188:188:188) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (145:145:145) (180:180:180))
+        (PORT datab (366:366:366) (425:425:425))
+        (PORT datac (92:92:92) (112:112:112))
+        (PORT datad (515:515:515) (594:594:594))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (229:229:229) (285:285:285))
+        (IOPATH datab combout (167:167:167) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (390:390:390) (459:459:459))
+        (PORT datab (250:250:250) (301:301:301))
+        (PORT datac (158:158:158) (185:185:185))
+        (PORT datad (530:530:530) (618:618:618))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (214:214:214) (273:273:273))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (170:170:170) (208:208:208))
+        (PORT datab (252:252:252) (302:302:302))
+        (PORT datac (374:374:374) (433:433:433))
+        (PORT datad (531:531:531) (620:620:620))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (214:214:214) (273:273:273))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (189:189:189) (225:225:225))
+        (PORT datab (241:241:241) (292:292:292))
+        (PORT datac (368:368:368) (427:427:427))
+        (PORT datad (530:530:530) (620:620:620))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (272:272:272))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (188:188:188) (223:223:223))
+        (PORT datab (251:251:251) (301:301:301))
+        (PORT datac (373:373:373) (433:433:433))
+        (PORT datad (529:529:529) (619:619:619))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (279:279:279))
+        (IOPATH datab combout (167:167:167) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (174:174:174) (211:211:211))
+        (PORT datab (241:241:241) (291:291:291))
+        (PORT datac (368:368:368) (427:427:427))
+        (PORT datad (530:530:530) (620:620:620))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~36)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (225:225:225) (286:286:286))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (391:391:391) (460:460:460))
+        (PORT datab (251:251:251) (302:302:302))
+        (PORT datac (161:161:161) (188:188:188))
+        (PORT datad (528:528:528) (620:620:620))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~38)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (190:190:190))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (529:529:529) (621:621:621))
+        (PORT datab (103:103:103) (131:131:131))
+        (PORT datac (127:127:127) (156:156:156))
+        (PORT datad (348:348:348) (401:401:401))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~40)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (161:161:161))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (529:529:529) (622:622:622))
+        (PORT datab (103:103:103) (131:131:131))
+        (PORT datac (128:128:128) (154:154:154))
+        (PORT datad (348:348:348) (401:401:401))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (291:291:291))
+        (PORT datab (134:134:134) (183:183:183))
+        (PORT datac (121:121:121) (164:164:164))
+        (PORT datad (203:203:203) (255:255:255))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (399:399:399) (480:480:480))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (141:141:141) (189:189:189))
+        (IOPATH datab combout (167:167:167) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (465:465:465) (540:540:540))
+        (IOPATH datab combout (188:188:188) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (389:389:389) (460:460:460))
+        (PORT datab (250:250:250) (300:300:300))
+        (PORT datac (325:325:325) (380:380:380))
+        (PORT datad (530:530:530) (619:619:619))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (136:136:136) (186:186:186))
+        (IOPATH datab combout (167:167:167) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (121:121:121) (154:154:154))
+        (PORT datab (368:368:368) (417:417:417))
+        (PORT datac (380:380:380) (460:460:460))
+        (PORT datad (92:92:92) (110:110:110))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (366:366:366) (449:449:449))
+        (IOPATH datab combout (188:188:188) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (388:388:388) (459:459:459))
+        (PORT datab (248:248:248) (298:298:298))
+        (PORT datac (315:315:315) (360:360:360))
+        (PORT datad (529:529:529) (618:618:618))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (350:350:350) (430:430:430))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (387:387:387) (459:459:459))
+        (PORT datab (248:248:248) (299:299:299))
+        (PORT datac (321:321:321) (365:365:365))
+        (PORT datad (527:527:527) (617:617:617))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (183:183:183))
+        (IOPATH datab combout (188:188:188) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (134:134:134) (186:186:186))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (132:132:132) (182:182:182))
+        (IOPATH datab combout (188:188:188) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (138:138:138) (191:191:191))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (106:106:106) (137:137:137))
+        (PORT datab (367:367:367) (415:415:415))
+        (PORT datac (378:378:378) (456:456:456))
+        (PORT datad (108:108:108) (126:126:126))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (145:145:145) (196:196:196))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (528:528:528) (620:620:620))
+        (PORT datab (106:106:106) (135:135:135))
+        (PORT datac (131:131:131) (158:158:158))
+        (PORT datad (348:348:348) (401:401:401))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (365:365:365) (443:443:443))
+        (PORT datab (384:384:384) (462:462:462))
+        (PORT datac (367:367:367) (441:441:441))
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (267:267:267))
+        (PORT datab (462:462:462) (537:537:537))
+        (PORT datac (351:351:351) (427:427:427))
+        (PORT datad (120:120:120) (159:159:159))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (428:428:428))
+        (PORT datab (137:137:137) (186:186:186))
+        (PORT datac (124:124:124) (166:166:166))
+        (PORT datad (125:125:125) (162:162:162))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (PORT datab (143:143:143) (192:192:192))
+        (PORT datac (128:128:128) (169:169:169))
+        (PORT datad (129:129:129) (165:165:165))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (172:172:172) (212:212:212))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (90:90:90) (111:111:111))
+        (PORT datad (319:319:319) (369:369:369))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|clkout\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (383:383:383) (445:445:445))
+        (PORT datab (235:235:235) (284:284:284))
+        (PORT datad (531:531:531) (621:621:621))
+        (IOPATH dataa combout (188:188:188) (203:203:203))
+        (IOPATH datab combout (190:190:190) (205:205:205))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|clkout)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PULSE\|state\.IDLE\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (121:121:121) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PULSE\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PULSE\|pulse\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (119:119:119) (161:161:161))
+        (PORT datad (125:125:125) (164:164:164))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PULSE\|pulse)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (586:586:586) (714:714:714))
+        (PORT datad (129:129:129) (170:170:170))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.WAIT_CSB_HIGH)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (586:586:586) (713:713:713))
+        (PORT datab (379:379:379) (453:453:453))
+        (PORT datad (116:116:116) (153:153:153))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (588:588:588) (716:716:716))
+        (PORT datab (375:375:375) (449:449:449))
+        (PORT datad (134:134:134) (176:176:176))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.WAIT_CSB_FALL)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|dac_start\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (584:584:584) (709:709:709))
+        (PORT datab (142:142:142) (195:195:195))
+        (PORT datac (299:299:299) (355:355:355))
+        (PORT datad (169:169:169) (222:222:222))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|dac_start\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (376:376:376) (449:449:449))
+        (PORT datac (92:92:92) (112:112:112))
+        (PORT datad (133:133:133) (176:176:176))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_start)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (883:883:883))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (133:133:133) (183:183:183))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[3\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (136:136:136) (188:188:188))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[4\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (145:145:145) (199:199:199))
+        (IOPATH datab combout (188:188:188) (193:193:193))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (318:318:318) (369:369:369))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (392:392:392) (475:475:475))
+        (PORT datab (116:116:116) (146:146:146))
+        (PORT datac (134:134:134) (179:179:179))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (318:318:318) (369:369:369))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[1\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (134:134:134) (184:184:184))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (318:318:318) (369:369:369))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[2\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (135:135:135) (185:185:185))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (318:318:318) (369:369:369))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT sclr (318:318:318) (369:369:369))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD sclr (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (137:137:137) (190:190:190))
+        (PORT datab (136:136:136) (186:186:186))
+        (PORT datac (122:122:122) (165:165:165))
+        (PORT datad (123:123:123) (162:162:162))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (394:394:394) (478:478:478))
+        (PORT datab (113:113:113) (145:145:145))
+        (PORT datac (130:130:130) (177:177:177))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_cs)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|clk_1MHz\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|clk_1MHz)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1293:1293:1293) (1159:1159:1159))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (409:409:409) (429:429:429))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_ADC\|clk_1MHz\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (486:486:486) (533:533:533))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE ADC_SDO\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (272:272:272) (833:833:833))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (PORT datac (476:476:476) (577:577:577))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.WAIT_CSB_HIGH)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (315:315:315) (385:385:385))
+        (PORT datab (492:492:492) (600:600:600))
+        (PORT datad (144:144:144) (182:182:182))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (492:492:492))
+        (PORT datab (347:347:347) (430:430:430))
+        (PORT datad (509:509:509) (608:608:608))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.WAIT_CSB_FALL)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|adc_start\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (132:132:132) (185:185:185))
+        (PORT datab (518:518:518) (627:627:627))
+        (PORT datac (336:336:336) (413:413:413))
+        (PORT datad (130:130:130) (169:169:169))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|adc_start\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (106:106:106) (139:139:139))
+        (PORT datab (523:523:523) (633:633:633))
+        (PORT datac (387:387:387) (468:468:468))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_start)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (878:878:878) (882:882:882))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (149:149:149) (204:204:204))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (151:151:151) (209:209:209))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (143:143:143) (189:189:189))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|state\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (126:126:126) (157:157:157))
+        (PORT datac (153:153:153) (211:211:211))
+        (PORT datad (94:94:94) (111:111:111))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (264:264:264) (332:332:332))
+        (PORT datad (139:139:139) (184:184:184))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (147:147:147) (206:206:206))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (104:104:104) (136:136:136))
+        (PORT datab (127:127:127) (160:160:160))
+        (PORT datac (151:151:151) (209:209:209))
+        (PORT datad (91:91:91) (108:108:108))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (165:165:165) (227:227:227))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|state\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (154:154:154) (210:210:210))
+        (PORT datac (140:140:140) (191:191:191))
+        (PORT datad (135:135:135) (178:178:178))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector4\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (264:264:264) (330:330:330))
+        (PORT datab (126:126:126) (158:158:158))
+        (PORT datac (152:152:152) (212:212:212))
+        (PORT datad (137:137:137) (182:182:182))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_cs)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (537:537:537) (592:592:592))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (164:164:164) (233:233:233))
+        (PORT datab (151:151:151) (206:206:206))
+        (PORT datac (137:137:137) (186:186:186))
+        (PORT datad (134:134:134) (177:177:177))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datac combout (119:119:119) (125:125:125))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (234:234:234) (276:276:276))
+        (PORT datab (103:103:103) (132:132:132))
+        (PORT datac (151:151:151) (208:208:208))
+        (PORT datad (140:140:140) (185:185:185))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_ena)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (340:340:340) (427:427:427))
+        (PORT datad (351:351:351) (409:409:409))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT asdata (2289:2289:2289) (2569:2569:2569))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (121:121:121) (159:159:159))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT asdata (299:299:299) (339:339:339))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (121:121:121) (159:159:159))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT asdata (298:298:298) (338:338:338))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (129:129:129) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT asdata (308:308:308) (348:348:348))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (163:163:163) (233:233:233))
+        (PORT datab (150:150:150) (208:208:208))
+        (PORT datac (136:136:136) (188:188:188))
+        (PORT datad (134:134:134) (180:180:180))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (161:161:161) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Decoder0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (105:105:105) (133:133:133))
+        (PORT datad (136:136:136) (182:182:182))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_done)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (390:390:390) (441:441:441))
+        (PORT ena (839:839:839) (940:940:940))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|PULSE2\|state\.IDLE\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (871:871:871) (1008:1008:1008))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|PULSE2\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|PULSE2\|pulse\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (884:884:884) (1032:1032:1032))
+        (PORT datad (116:116:116) (153:153:153))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|PULSE2\|pulse)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|rden_b_store)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (869:869:869) (874:874:874))
+        (PORT asdata (638:638:638) (715:715:715))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (475:475:475) (560:560:560))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT asdata (307:307:307) (347:347:347))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (390:390:390) (440:440:440))
+        (PORT ena (839:839:839) (940:940:940))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (130:130:130) (166:166:166))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (879:879:879) (867:867:867))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (421:421:421) (447:447:447))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (366:366:366) (414:414:414))
+        (PORT ena (839:839:839) (940:940:940))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_ADC\|adc_cs\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (625:625:625) (695:695:695))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[0\]\~36)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[1\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (142:142:142) (192:192:192))
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[2\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (189:189:189))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[3\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[4\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[4\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1806:1806:1806) (2025:2025:2025))
+        (PORT datab (763:763:763) (883:883:883))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[5\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[5\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (793:793:793) (925:925:925))
+        (PORT datab (1862:1862:1862) (2092:2092:2092))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[6\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[6\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (807:807:807) (943:943:943))
+        (PORT datab (1816:1816:1816) (2038:2038:2038))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[7\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (191:191:191))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[7\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (795:795:795) (922:922:922))
+        (PORT datab (1795:1795:1795) (2011:2011:2011))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[8\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (191:191:191))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[8\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1857:1857:1857) (2095:2095:2095))
+        (PORT datab (778:778:778) (926:926:926))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[9\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[9\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (751:751:751) (880:880:880))
+        (PORT datab (1951:1951:1951) (2186:2186:2186))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[10\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (154:154:154) (202:202:202))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[10\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (661:661:661) (779:779:779))
+        (PORT datab (1981:1981:1981) (2237:2237:2237))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (191:191:191) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[11\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (142:142:142) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[11\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1812:1812:1812) (2029:2029:2029))
+        (PORT datab (793:793:793) (935:935:935))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[12\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (128:128:128) (165:165:165))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[12\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1802:1802:1802) (2018:2018:2018))
+        (PORT datad (755:755:755) (877:877:877))
+        (IOPATH dataa combout (188:188:188) (193:193:193))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (370:370:370) (420:420:420))
+        (PORT clk (1057:1057:1057) (1075:1075:1075))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (576:576:576) (672:672:672))
+        (PORT d[1] (562:562:562) (659:659:659))
+        (PORT d[2] (567:567:567) (668:668:668))
+        (PORT d[3] (869:869:869) (1003:1003:1003))
+        (PORT d[4] (785:785:785) (897:897:897))
+        (PORT d[5] (792:792:792) (894:894:894))
+        (PORT d[6] (1084:1084:1084) (1203:1203:1203))
+        (PORT d[7] (814:814:814) (913:913:913))
+        (PORT d[8] (915:915:915) (1016:1016:1016))
+        (PORT d[9] (801:801:801) (895:895:895))
+        (PORT d[10] (880:880:880) (1005:1005:1005))
+        (PORT d[11] (908:908:908) (1026:1026:1026))
+        (PORT d[12] (819:819:819) (918:918:918))
+        (PORT clk (1055:1055:1055) (1073:1073:1073))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (686:686:686) (724:724:724))
+        (PORT clk (1055:1055:1055) (1073:1073:1073))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1057:1057:1057) (1075:1075:1075))
+        (PORT d[0] (970:970:970) (1017:1017:1017))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1058:1058:1058) (1076:1076:1076))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1058:1058:1058) (1076:1076:1076))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1058:1058:1058) (1076:1076:1076))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1058:1058:1058) (1076:1076:1076))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (553:553:553) (647:647:647))
+        (PORT d[1] (561:561:561) (661:661:661))
+        (PORT d[2] (580:580:580) (681:681:681))
+        (PORT d[3] (870:870:870) (1003:1003:1003))
+        (PORT d[4] (530:530:530) (616:616:616))
+        (PORT d[5] (750:750:750) (845:845:845))
+        (PORT d[6] (554:554:554) (647:647:647))
+        (PORT d[7] (741:741:741) (847:847:847))
+        (PORT d[8] (585:585:585) (667:667:667))
+        (PORT d[9] (571:571:571) (664:664:664))
+        (PORT d[10] (795:795:795) (913:913:913))
+        (PORT d[11] (730:730:730) (839:839:839))
+        (PORT d[12] (559:559:559) (643:643:643))
+        (PORT clk (1014:1014:1014) (1034:1034:1034))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (686:686:686) (724:724:724))
+        (PORT clk (1014:1014:1014) (1034:1034:1034))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1014:1014:1014) (1034:1034:1034))
+        (PORT d[0] (1144:1144:1144) (1218:1218:1218))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1015:1015:1015) (1035:1035:1035))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1015:1015:1015) (1035:1035:1035))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1015:1015:1015) (1035:1035:1035))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1013:1013:1013) (1033:1033:1033))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (389:389:389) (439:439:439))
+        (PORT ena (839:839:839) (940:940:940))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (121:121:121) (159:159:159))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (700:700:700) (767:767:767))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (469:469:469) (540:540:540))
+        (PORT datab (131:131:131) (179:179:179))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (750:750:750) (867:867:867))
+        (PORT clk (1054:1054:1054) (1071:1071:1071))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1105:1105:1105) (1306:1306:1306))
+        (PORT d[1] (1173:1173:1173) (1349:1349:1349))
+        (PORT d[2] (657:657:657) (772:772:772))
+        (PORT d[3] (1359:1359:1359) (1571:1571:1571))
+        (PORT d[4] (547:547:547) (638:638:638))
+        (PORT d[5] (417:417:417) (470:470:470))
+        (PORT d[6] (614:614:614) (689:689:689))
+        (PORT d[7] (391:391:391) (447:447:447))
+        (PORT d[8] (837:837:837) (976:976:976))
+        (PORT d[9] (401:401:401) (458:458:458))
+        (PORT d[10] (953:953:953) (1097:1097:1097))
+        (PORT d[11] (547:547:547) (633:633:633))
+        (PORT d[12] (406:406:406) (468:468:468))
+        (PORT clk (1052:1052:1052) (1069:1069:1069))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (691:691:691) (749:749:749))
+        (PORT clk (1052:1052:1052) (1069:1069:1069))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1054:1054:1054) (1071:1071:1071))
+        (PORT d[0] (975:975:975) (1042:1042:1042))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1055:1055:1055) (1072:1072:1072))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1055:1055:1055) (1072:1072:1072))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1055:1055:1055) (1072:1072:1072))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1055:1055:1055) (1072:1072:1072))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1095:1095:1095) (1292:1292:1292))
+        (PORT d[1] (1175:1175:1175) (1347:1347:1347))
+        (PORT d[2] (669:669:669) (786:786:786))
+        (PORT d[3] (1360:1360:1360) (1571:1571:1571))
+        (PORT d[4] (659:659:659) (769:769:769))
+        (PORT d[5] (1006:1006:1006) (1167:1167:1167))
+        (PORT d[6] (1148:1148:1148) (1325:1325:1325))
+        (PORT d[7] (1254:1254:1254) (1436:1436:1436))
+        (PORT d[8] (1113:1113:1113) (1276:1276:1276))
+        (PORT d[9] (665:665:665) (792:792:792))
+        (PORT d[10] (986:986:986) (1129:1129:1129))
+        (PORT d[11] (971:971:971) (1129:1129:1129))
+        (PORT d[12] (980:980:980) (1129:1129:1129))
+        (PORT clk (1011:1011:1011) (1030:1030:1030))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (691:691:691) (749:749:749))
+        (PORT clk (1011:1011:1011) (1030:1030:1030))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1011:1011:1011) (1030:1030:1030))
+        (PORT d[0] (774:774:774) (813:813:813))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1012:1012:1012) (1031:1031:1031))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1012:1012:1012) (1031:1031:1031))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1012:1012:1012) (1031:1031:1031))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1010:1010:1010) (1029:1029:1029))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (206:206:206) (252:252:252))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (839:839:839) (940:940:940))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (310:310:310) (378:378:378))
+        (PORT datab (612:612:612) (702:702:702))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (515:515:515) (577:577:577))
+        (PORT clk (1060:1060:1060) (1077:1077:1077))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (564:564:564) (658:658:658))
+        (PORT d[1] (580:580:580) (682:682:682))
+        (PORT d[2] (565:565:565) (658:658:658))
+        (PORT d[3] (587:587:587) (681:681:681))
+        (PORT d[4] (774:774:774) (881:881:881))
+        (PORT d[5] (781:781:781) (880:880:880))
+        (PORT d[6] (1401:1401:1401) (1552:1552:1552))
+        (PORT d[7] (803:803:803) (896:896:896))
+        (PORT d[8] (893:893:893) (984:984:984))
+        (PORT d[9] (790:790:790) (884:884:884))
+        (PORT d[10] (1022:1022:1022) (1151:1151:1151))
+        (PORT d[11] (914:914:914) (1030:1030:1030))
+        (PORT d[12] (1088:1088:1088) (1207:1207:1207))
+        (PORT clk (1058:1058:1058) (1075:1075:1075))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (808:808:808) (863:863:863))
+        (PORT clk (1058:1058:1058) (1075:1075:1075))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1060:1060:1060) (1077:1077:1077))
+        (PORT d[0] (1092:1092:1092) (1156:1156:1156))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1061:1061:1061) (1078:1078:1078))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1061:1061:1061) (1078:1078:1078))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1061:1061:1061) (1078:1078:1078))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1061:1061:1061) (1078:1078:1078))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (572:572:572) (656:656:656))
+        (PORT d[1] (582:582:582) (679:679:679))
+        (PORT d[2] (577:577:577) (672:672:672))
+        (PORT d[3] (588:588:588) (681:681:681))
+        (PORT d[4] (566:566:566) (655:655:655))
+        (PORT d[5] (750:750:750) (853:853:853))
+        (PORT d[6] (692:692:692) (802:802:802))
+        (PORT d[7] (574:574:574) (674:674:674))
+        (PORT d[8] (596:596:596) (684:684:684))
+        (PORT d[9] (726:726:726) (838:838:838))
+        (PORT d[10] (594:594:594) (689:689:689))
+        (PORT d[11] (562:562:562) (658:658:658))
+        (PORT d[12] (584:584:584) (669:669:669))
+        (PORT clk (1017:1017:1017) (1036:1036:1036))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (808:808:808) (863:863:863))
+        (PORT clk (1017:1017:1017) (1036:1036:1036))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1017:1017:1017) (1036:1036:1036))
+        (PORT d[0] (1173:1173:1173) (1248:1248:1248))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1018:1018:1018) (1037:1037:1037))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1018:1018:1018) (1037:1037:1037))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1018:1018:1018) (1037:1037:1037))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1016:1016:1016) (1035:1035:1035))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (308:308:308))
+        (PORT datab (511:511:511) (593:593:593))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (520:520:520) (589:589:589))
+        (PORT clk (1051:1051:1051) (1069:1069:1069))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (654:654:654) (772:772:772))
+        (PORT d[1] (1150:1150:1150) (1328:1328:1328))
+        (PORT d[2] (847:847:847) (980:980:980))
+        (PORT d[3] (1141:1141:1141) (1328:1328:1328))
+        (PORT d[4] (548:548:548) (637:637:637))
+        (PORT d[5] (751:751:751) (863:863:863))
+        (PORT d[6] (622:622:622) (708:708:708))
+        (PORT d[7] (400:400:400) (455:455:455))
+        (PORT d[8] (941:941:941) (1083:1083:1083))
+        (PORT d[9] (398:398:398) (460:460:460))
+        (PORT d[10] (826:826:826) (955:955:955))
+        (PORT d[11] (410:410:410) (477:477:477))
+        (PORT d[12] (392:392:392) (448:448:448))
+        (PORT clk (1049:1049:1049) (1067:1067:1067))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (939:939:939) (1043:1043:1043))
+        (PORT clk (1049:1049:1049) (1067:1067:1067))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1051:1051:1051) (1069:1069:1069))
+        (PORT d[0] (1223:1223:1223) (1336:1336:1336))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1052:1052:1052) (1070:1070:1070))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1052:1052:1052) (1070:1070:1070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1052:1052:1052) (1070:1070:1070))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1052:1052:1052) (1070:1070:1070))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (649:649:649) (774:774:774))
+        (PORT d[1] (1162:1162:1162) (1342:1342:1342))
+        (PORT d[2] (836:836:836) (968:968:968))
+        (PORT d[3] (1142:1142:1142) (1328:1328:1328))
+        (PORT d[4] (806:806:806) (922:922:922))
+        (PORT d[5] (988:988:988) (1148:1148:1148))
+        (PORT d[6] (1127:1127:1127) (1306:1306:1306))
+        (PORT d[7] (1115:1115:1115) (1269:1269:1269))
+        (PORT d[8] (942:942:942) (1090:1090:1090))
+        (PORT d[9] (768:768:768) (893:893:893))
+        (PORT d[10] (1149:1149:1149) (1323:1323:1323))
+        (PORT d[11] (1116:1116:1116) (1281:1281:1281))
+        (PORT d[12] (964:964:964) (1110:1110:1110))
+        (PORT clk (1008:1008:1008) (1028:1028:1028))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (939:939:939) (1043:1043:1043))
+        (PORT clk (1008:1008:1008) (1028:1028:1028))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1008:1008:1008) (1028:1028:1028))
+        (PORT d[0] (924:924:924) (988:988:988))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1009:1009:1009) (1029:1029:1029))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1009:1009:1009) (1029:1029:1029))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1009:1009:1009) (1029:1029:1029))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1007:1007:1007) (1027:1027:1027))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (301:301:301) (342:342:342))
+        (PORT ena (700:700:700) (767:767:767))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (122:122:122) (160:160:160))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (700:700:700) (767:767:767))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (455:455:455) (521:521:521))
+        (PORT datab (313:313:313) (389:389:389))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (167:167:167) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (752:752:752) (873:873:873))
+        (PORT clk (1054:1054:1054) (1071:1071:1071))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (825:825:825) (957:957:957))
+        (PORT d[1] (1174:1174:1174) (1340:1340:1340))
+        (PORT d[2] (842:842:842) (991:991:991))
+        (PORT d[3] (1116:1116:1116) (1294:1294:1294))
+        (PORT d[4] (535:535:535) (624:624:624))
+        (PORT d[5] (383:383:383) (437:437:437))
+        (PORT d[6] (608:608:608) (677:677:677))
+        (PORT d[7] (375:375:375) (430:430:430))
+        (PORT d[8] (786:786:786) (915:915:915))
+        (PORT d[9] (377:377:377) (431:431:431))
+        (PORT d[10] (810:810:810) (949:949:949))
+        (PORT d[11] (398:398:398) (466:466:466))
+        (PORT d[12] (542:542:542) (614:614:614))
+        (PORT clk (1052:1052:1052) (1069:1069:1069))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (960:960:960) (1058:1058:1058))
+        (PORT clk (1052:1052:1052) (1069:1069:1069))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1054:1054:1054) (1071:1071:1071))
+        (PORT d[0] (1244:1244:1244) (1351:1351:1351))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1055:1055:1055) (1072:1072:1072))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1055:1055:1055) (1072:1072:1072))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1055:1055:1055) (1072:1072:1072))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1055:1055:1055) (1072:1072:1072))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (822:822:822) (958:958:958))
+        (PORT d[1] (1162:1162:1162) (1327:1327:1327))
+        (PORT d[2] (832:832:832) (977:977:977))
+        (PORT d[3] (1117:1117:1117) (1294:1294:1294))
+        (PORT d[4] (809:809:809) (923:923:923))
+        (PORT d[5] (978:978:978) (1131:1131:1131))
+        (PORT d[6] (1128:1128:1128) (1289:1289:1289))
+        (PORT d[7] (1005:1005:1005) (1153:1153:1153))
+        (PORT d[8] (1250:1250:1250) (1486:1486:1486))
+        (PORT d[9] (761:761:761) (883:883:883))
+        (PORT d[10] (970:970:970) (1109:1109:1109))
+        (PORT d[11] (951:951:951) (1107:1107:1107))
+        (PORT d[12] (811:811:811) (937:937:937))
+        (PORT clk (1011:1011:1011) (1030:1030:1030))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (960:960:960) (1058:1058:1058))
+        (PORT clk (1011:1011:1011) (1030:1030:1030))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1011:1011:1011) (1030:1030:1030))
+        (PORT d[0] (920:920:920) (975:975:975))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1012:1012:1012) (1031:1031:1031))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1012:1012:1012) (1031:1031:1031))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1012:1012:1012) (1031:1031:1031))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1010:1010:1010) (1029:1029:1029))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT asdata (301:301:301) (341:341:341))
+        (PORT ena (700:700:700) (767:767:767))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (219:219:219) (277:277:277))
+        (PORT datab (729:729:729) (860:860:860))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (497:497:497) (561:561:561))
+        (PORT clk (1060:1060:1060) (1077:1077:1077))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (729:729:729) (846:846:846))
+        (PORT d[1] (408:408:408) (489:489:489))
+        (PORT d[2] (735:735:735) (848:848:848))
+        (PORT d[3] (866:866:866) (995:995:995))
+        (PORT d[4] (792:792:792) (905:905:905))
+        (PORT d[5] (815:815:815) (914:914:914))
+        (PORT d[6] (1081:1081:1081) (1194:1194:1194))
+        (PORT d[7] (809:809:809) (899:899:899))
+        (PORT d[8] (926:926:926) (1028:1028:1028))
+        (PORT d[9] (797:797:797) (882:882:882))
+        (PORT d[10] (891:891:891) (1010:1010:1010))
+        (PORT d[11] (937:937:937) (1067:1067:1067))
+        (PORT d[12] (814:814:814) (905:905:905))
+        (PORT clk (1058:1058:1058) (1075:1075:1075))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (982:982:982) (1053:1053:1053))
+        (PORT clk (1058:1058:1058) (1075:1075:1075))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1060:1060:1060) (1077:1077:1077))
+        (PORT d[0] (1266:1266:1266) (1346:1346:1346))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1061:1061:1061) (1078:1078:1078))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1061:1061:1061) (1078:1078:1078))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1061:1061:1061) (1078:1078:1078))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1061:1061:1061) (1078:1078:1078))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (732:732:732) (845:845:845))
+        (PORT d[1] (421:421:421) (500:500:500))
+        (PORT d[2] (720:720:720) (821:821:821))
+        (PORT d[3] (867:867:867) (995:995:995))
+        (PORT d[4] (412:412:412) (488:488:488))
+        (PORT d[5] (418:418:418) (494:494:494))
+        (PORT d[6] (404:404:404) (475:475:475))
+        (PORT d[7] (401:401:401) (470:470:470))
+        (PORT d[8] (409:409:409) (484:484:484))
+        (PORT d[9] (532:532:532) (614:614:614))
+        (PORT d[10] (413:413:413) (483:483:483))
+        (PORT d[11] (742:742:742) (851:851:851))
+        (PORT d[12] (523:523:523) (599:599:599))
+        (PORT clk (1017:1017:1017) (1036:1036:1036))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (982:982:982) (1053:1053:1053))
+        (PORT clk (1017:1017:1017) (1036:1036:1036))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1017:1017:1017) (1036:1036:1036))
+        (PORT d[0] (1008:1008:1008) (1059:1059:1059))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1018:1018:1018) (1037:1037:1037))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1018:1018:1018) (1037:1037:1037))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1018:1018:1018) (1037:1037:1037))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1016:1016:1016) (1035:1035:1035))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (200:200:200) (261:261:261))
+        (PORT datab (629:629:629) (725:725:725))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (772:772:772) (868:868:868))
+        (PORT clk (1056:1056:1056) (1073:1073:1073))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (826:826:826) (984:984:984))
+        (PORT d[1] (864:864:864) (1004:1004:1004))
+        (PORT d[2] (847:847:847) (979:979:979))
+        (PORT d[3] (830:830:830) (984:984:984))
+        (PORT d[4] (380:380:380) (445:445:445))
+        (PORT d[5] (223:223:223) (260:260:260))
+        (PORT d[6] (217:217:217) (252:252:252))
+        (PORT d[7] (221:221:221) (258:258:258))
+        (PORT d[8] (218:218:218) (252:252:252))
+        (PORT d[9] (225:225:225) (264:264:264))
+        (PORT d[10] (217:217:217) (250:250:250))
+        (PORT d[11] (214:214:214) (253:253:253))
+        (PORT d[12] (225:225:225) (262:262:262))
+        (PORT clk (1054:1054:1054) (1071:1071:1071))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (961:961:961) (1049:1049:1049))
+        (PORT clk (1054:1054:1054) (1071:1071:1071))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1056:1056:1056) (1073:1073:1073))
+        (PORT d[0] (1245:1245:1245) (1342:1342:1342))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1057:1057:1057) (1074:1074:1074))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1057:1057:1057) (1074:1074:1074))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1057:1057:1057) (1074:1074:1074))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1057:1057:1057) (1074:1074:1074))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (840:840:840) (995:995:995))
+        (PORT d[1] (866:866:866) (1001:1001:1001))
+        (PORT d[2] (852:852:852) (995:995:995))
+        (PORT d[3] (831:831:831) (984:984:984))
+        (PORT d[4] (825:825:825) (944:944:944))
+        (PORT d[5] (841:841:841) (982:982:982))
+        (PORT d[6] (837:837:837) (971:971:971))
+        (PORT d[7] (859:859:859) (998:998:998))
+        (PORT d[8] (846:846:846) (1005:1005:1005))
+        (PORT d[9] (785:785:785) (915:915:915))
+        (PORT d[10] (836:836:836) (962:962:962))
+        (PORT d[11] (822:822:822) (965:965:965))
+        (PORT d[12] (834:834:834) (970:970:970))
+        (PORT clk (1013:1013:1013) (1032:1032:1032))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (961:961:961) (1049:1049:1049))
+        (PORT clk (1013:1013:1013) (1032:1032:1032))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1013:1013:1013) (1032:1032:1032))
+        (PORT d[0] (928:928:928) (990:990:990))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1014:1014:1014) (1033:1033:1033))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1014:1014:1014) (1033:1033:1033))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1014:1014:1014) (1033:1033:1033))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1012:1012:1012) (1031:1031:1031))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (124:124:124) (162:162:162))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (871:871:871) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (PORT ena (700:700:700) (767:767:767))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (722:722:722) (834:834:834))
+        (PORT datab (215:215:215) (272:272:272))
+        (IOPATH dataa combout (159:159:159) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (169:169:169) (167:167:167))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (200:200:200) (261:261:261))
+        (PORT datab (663:663:663) (757:757:757))
+        (IOPATH dataa combout (166:166:166) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (289:289:289))
+        (PORT datab (529:529:529) (607:607:607))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (166:166:166) (174:174:174))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (225:225:225) (288:288:288))
+        (PORT datad (512:512:512) (583:583:583))
+        (IOPATH datab combout (188:188:188) (193:193:193))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (102:102:102) (130:130:130))
+        (IOPATH datab combout (192:192:192) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (102:102:102) (130:130:130))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (103:103:103) (134:134:134))
+        (IOPATH dataa combout (195:195:195) (203:203:203))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (524:524:524) (594:594:594))
+        (PORT clk (1062:1062:1062) (1080:1080:1080))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (596:596:596) (687:687:687))
+        (PORT d[1] (601:601:601) (694:694:694))
+        (PORT d[2] (595:595:595) (696:696:696))
+        (PORT d[3] (864:864:864) (993:993:993))
+        (PORT d[4] (627:627:627) (706:706:706))
+        (PORT d[5] (627:627:627) (711:711:711))
+        (PORT d[6] (1402:1402:1402) (1550:1550:1550))
+        (PORT d[7] (643:643:643) (714:714:714))
+        (PORT d[8] (641:641:641) (716:716:716))
+        (PORT d[9] (629:629:629) (694:694:694))
+        (PORT d[10] (669:669:669) (765:765:765))
+        (PORT d[11] (1110:1110:1110) (1249:1249:1249))
+        (PORT d[12] (619:619:619) (681:681:681))
+        (PORT clk (1060:1060:1060) (1078:1078:1078))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (833:833:833) (885:885:885))
+        (PORT clk (1060:1060:1060) (1078:1078:1078))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1062:1062:1062) (1080:1080:1080))
+        (PORT d[0] (1117:1117:1117) (1178:1178:1178))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1081:1081:1081))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1081:1081:1081))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1081:1081:1081))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1081:1081:1081))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (591:591:591) (692:692:692))
+        (PORT d[1] (602:602:602) (694:694:694))
+        (PORT d[2] (572:572:572) (671:671:671))
+        (PORT d[3] (865:865:865) (993:993:993))
+        (PORT d[4] (571:571:571) (660:660:660))
+        (PORT d[5] (582:582:582) (673:673:673))
+        (PORT d[6] (581:581:581) (667:667:667))
+        (PORT d[7] (573:573:573) (655:655:655))
+        (PORT d[8] (603:603:603) (689:689:689))
+        (PORT d[9] (712:712:712) (810:810:810))
+        (PORT d[10] (614:614:614) (710:710:710))
+        (PORT d[11] (688:688:688) (790:790:790))
+        (PORT d[12] (574:574:574) (661:661:661))
+        (PORT clk (1019:1019:1019) (1039:1039:1039))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (833:833:833) (885:885:885))
+        (PORT clk (1019:1019:1019) (1039:1039:1039))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1019:1019:1019) (1039:1039:1039))
+        (PORT d[0] (1160:1160:1160) (1230:1230:1230))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1020:1020:1020) (1040:1040:1040))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1020:1020:1020) (1040:1040:1040))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1020:1020:1020) (1040:1040:1040))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1018:1018:1018) (1038:1038:1038))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (529:529:529) (599:599:599))
+        (PORT clk (1062:1062:1062) (1080:1080:1080))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (727:727:727) (839:839:839))
+        (PORT d[1] (561:561:561) (653:653:653))
+        (PORT d[2] (734:734:734) (843:843:843))
+        (PORT d[3] (854:854:854) (984:984:984))
+        (PORT d[4] (951:951:951) (1065:1065:1065))
+        (PORT d[5] (829:829:829) (934:934:934))
+        (PORT d[6] (1557:1557:1557) (1722:1722:1722))
+        (PORT d[7] (823:823:823) (919:919:919))
+        (PORT d[8] (926:926:926) (1029:1029:1029))
+        (PORT d[9] (798:798:798) (883:883:883))
+        (PORT d[10] (858:858:858) (968:968:968))
+        (PORT d[11] (899:899:899) (1010:1010:1010))
+        (PORT d[12] (815:815:815) (905:905:905))
+        (PORT clk (1060:1060:1060) (1078:1078:1078))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (813:813:813) (882:882:882))
+        (PORT clk (1060:1060:1060) (1078:1078:1078))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1062:1062:1062) (1080:1080:1080))
+        (PORT d[0] (1121:1121:1121) (1191:1191:1191))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1081:1081:1081))
+        (IOPATH (posedge clk) pulse (0:0:0) (987:987:987))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1081:1081:1081))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1081:1081:1081))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1063:1063:1063) (1081:1081:1081))
+        (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (740:740:740) (852:852:852))
+        (PORT d[1] (557:557:557) (640:640:640))
+        (PORT d[2] (735:735:735) (843:843:843))
+        (PORT d[3] (855:855:855) (984:984:984))
+        (PORT d[4] (552:552:552) (639:639:639))
+        (PORT d[5] (552:552:552) (635:635:635))
+        (PORT d[6] (729:729:729) (842:842:842))
+        (PORT d[7] (753:753:753) (870:870:870))
+        (PORT d[8] (553:553:553) (636:636:636))
+        (PORT d[9] (688:688:688) (788:788:788))
+        (PORT d[10] (565:565:565) (650:650:650))
+        (PORT d[11] (759:759:759) (871:871:871))
+        (PORT d[12] (562:562:562) (638:638:638))
+        (PORT clk (1019:1019:1019) (1039:1039:1039))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (837:837:837) (898:898:898))
+        (PORT clk (1019:1019:1019) (1039:1039:1039))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (104:104:104))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1019:1019:1019) (1039:1039:1039))
+        (PORT d[0] (1306:1306:1306) (1404:1404:1404))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1020:1020:1020) (1040:1040:1040))
+        (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1020:1020:1020) (1040:1040:1040))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1020:1020:1020) (1040:1040:1040))
+        (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1018:1018:1018) (1038:1038:1038))
+        (IOPATH (posedge clk) q (164:164:164) (166:166:166))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (25:25:25))
+      (HOLD d (posedge clk) (90:90:90))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (543:543:543) (667:667:667))
+        (PORT datac (772:772:772) (908:908:908))
+        (PORT datad (384:384:384) (465:465:465))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (868:868:868) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (543:543:543) (667:667:667))
+        (PORT datab (129:129:129) (178:178:178))
+        (PORT datac (627:627:627) (714:714:714))
+        (PORT datad (384:384:384) (465:465:465))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (868:868:868) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (599:599:599) (726:726:726))
+        (PORT datab (410:410:410) (499:499:499))
+        (PORT datac (119:119:119) (160:160:160))
+        (PORT datad (515:515:515) (631:631:631))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (190:190:190) (188:188:188))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (868:868:868) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (538:538:538) (660:660:660))
+        (PORT datab (130:130:130) (178:178:178))
+        (PORT datac (566:566:566) (665:665:665))
+        (PORT datad (392:392:392) (473:473:473))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (868:868:868) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (537:537:537) (659:659:659))
+        (PORT datab (129:129:129) (178:178:178))
+        (PORT datac (458:458:458) (536:536:536))
+        (PORT datad (392:392:392) (473:473:473))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (868:868:868) (872:872:872))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (583:583:583) (709:709:709))
+        (PORT datab (227:227:227) (290:290:290))
+        (PORT datac (595:595:595) (712:712:712))
+        (PORT datad (165:165:165) (218:218:218))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (588:588:588) (714:714:714))
+        (PORT datab (131:131:131) (179:179:179))
+        (PORT datac (375:375:375) (452:452:452))
+        (PORT datad (168:168:168) (222:222:222))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (580:580:580) (716:716:716))
+        (PORT datab (378:378:378) (455:455:455))
+        (PORT datac (117:117:117) (158:158:158))
+        (PORT datad (167:167:167) (220:220:220))
+        (IOPATH dataa combout (166:166:166) (157:157:157))
+        (IOPATH datab combout (167:167:167) (158:158:158))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (584:584:584) (714:714:714))
+        (PORT datab (130:130:130) (179:179:179))
+        (PORT datac (499:499:499) (602:602:602))
+        (PORT datad (167:167:167) (220:220:220))
+        (IOPATH dataa combout (158:158:158) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|data_out\[9\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (101:101:101) (122:122:122))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (873:873:873) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (131:131:131) (184:184:184))
+        (PORT datab (178:178:178) (241:241:241))
+        (PORT datac (691:691:691) (832:832:832))
+        (PORT datad (571:571:571) (683:683:683))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (188:188:188) (177:177:177))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (588:588:588) (715:715:715))
+        (PORT datac (117:117:117) (157:157:157))
+        (PORT datad (167:167:167) (216:216:216))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (587:587:587) (714:714:714))
+        (PORT datac (117:117:117) (157:157:157))
+        (PORT datad (164:164:164) (216:216:216))
+        (IOPATH dataa combout (166:166:166) (163:163:163))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (585:585:585) (715:715:715))
+        (PORT datac (118:118:118) (161:161:161))
+        (PORT datad (168:168:168) (221:221:221))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (586:586:586) (714:714:714))
+        (PORT datab (179:179:179) (244:244:244))
+        (PORT datad (118:118:118) (155:155:155))
+        (IOPATH dataa combout (159:159:159) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (870:870:870) (875:875:875))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCK\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (215:215:215) (275:275:275))
+        (PORT datab (142:142:142) (189:189:189))
+        (PORT datac (332:332:332) (409:409:409))
+        (PORT datad (767:767:767) (907:907:907))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (113:113:113) (150:150:150))
+        (PORT datac (134:134:134) (183:183:183))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (120:120:120) (125:125:125))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_ld)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (878:878:878))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[9\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (342:342:342) (901:901:901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (264:264:264) (330:330:330))
+        (PORT datab (1782:1782:1782) (2000:2000:2000))
+        (PORT datac (152:152:152) (211:211:211))
+        (PORT datad (134:134:134) (176:176:176))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (168:168:168) (167:167:167))
+        (IOPATH datac combout (120:120:120) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (151:151:151) (209:209:209))
+        (PORT datab (150:150:150) (204:204:204))
+        (PORT datac (93:93:93) (114:114:114))
+        (PORT datad (143:143:143) (189:189:189))
+        (IOPATH dataa combout (158:158:158) (157:157:157))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_din)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (875:875:875) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[1\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (285:285:285))
+        (PORT datab (141:141:141) (189:189:189))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[2\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[3\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (189:189:189))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[4\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[5\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[6\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[7\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[8\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (191:191:191))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[9\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (130:130:130) (166:166:166))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (880:880:880))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (638:638:638) (717:717:717))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (1016:1016:1016) (1166:1166:1166))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (530:530:530) (598:598:598))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (626:626:626) (703:703:703))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (1012:1012:1012) (1174:1174:1174))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (637:637:637) (713:713:713))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (742:742:742) (842:842:842))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (754:754:754) (879:879:879))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (807:807:807) (891:891:891))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (876:876:876) (881:881:881))
+        (PORT asdata (946:946:946) (1080:1080:1080))
+        (PORT ena (563:563:563) (619:619:619))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (84:84:84))
+      (HOLD ena (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (180:180:180))
+        (PORT datab (485:485:485) (576:576:576))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (287:287:287))
+        (PORT datab (130:130:130) (176:176:176))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (181:181:181))
+        (PORT datab (327:327:327) (399:399:399))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (181:181:181))
+        (PORT datab (227:227:227) (282:282:282))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (290:290:290))
+        (PORT datab (212:212:212) (268:268:268))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (349:349:349) (422:422:422))
+        (PORT datab (129:129:129) (177:177:177))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (350:350:350) (422:422:422))
+        (PORT datab (129:129:129) (178:178:178))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (338:338:338) (403:403:403))
+        (PORT datab (130:130:130) (178:178:178))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (180:180:180))
+        (PORT datab (227:227:227) (283:283:283))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (213:213:213) (272:272:272))
+        (PORT datab (130:130:130) (177:177:177))
+        (IOPATH dataa combout (170:170:170) (163:163:163))
+        (IOPATH datab combout (160:160:160) (156:156:156))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|pwm_out\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (459:459:459) (523:523:523))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|pwm_out)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (872:872:872) (877:877:877))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+)
diff --git a/part_4/ex16/simulation/modelsim/top_modelsim.xrf b/part_4/ex16/simulation/modelsim/top_modelsim.xrf
new file mode 100755
index 0000000..df7749e
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_modelsim.xrf
@@ -0,0 +1,502 @@
+vendor_name = ModelSim
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Library/add3_ge5.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/echo_feedback.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/pwm.v
+source_file = 1, edge_detect.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/pulse_gen.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.v
+source_file = 1, ROM.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/multiply_k.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/clk_div.v
+source_file = 1, accumulator.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/spi2dac.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/spi2adc.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/delay_ram.v
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/altsyncram.tdf
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/stratix_ram_block.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mux.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_decode.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/aglobal160.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/a_rdenreg.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/altrom.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/altram.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/altdpram.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/altsyncram_ip02.tdf
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_mult.tdf
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_add_sub.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/multcore.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/bypassff.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/altshift.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/multcore.tdf
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/csa_add.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/muleabz.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/mul_lfrg.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/mul_boothc.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/alt_ded_mult.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/alt_ded_mult_y.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/dffpipe.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/mpar_add.tdf
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/addcore.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/look_add.inc
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/add_sub_a9h.tdf
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/db/add_sub_e9h.tdf
+source_file = 1, c:/altera_lite/16.0/quartus/libraries/megafunctions/altshift.tdf
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/bin2bcd.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/hex_to_7seg.v
+source_file = 1, Y:/_My Documents/EE2 Digital - New Experiment/VERI/Ex15/top.sdc
+design_name = top
+instance = comp, \HEX0[0]~output , HEX0[0]~output, top, 1
+instance = comp, \HEX0[1]~output , HEX0[1]~output, top, 1
+instance = comp, \HEX0[2]~output , HEX0[2]~output, top, 1
+instance = comp, \HEX0[3]~output , HEX0[3]~output, top, 1
+instance = comp, \HEX0[4]~output , HEX0[4]~output, top, 1
+instance = comp, \HEX0[5]~output , HEX0[5]~output, top, 1
+instance = comp, \HEX0[6]~output , HEX0[6]~output, top, 1
+instance = comp, \HEX1[0]~output , HEX1[0]~output, top, 1
+instance = comp, \HEX1[1]~output , HEX1[1]~output, top, 1
+instance = comp, \HEX1[2]~output , HEX1[2]~output, top, 1
+instance = comp, \HEX1[3]~output , HEX1[3]~output, top, 1
+instance = comp, \HEX1[4]~output , HEX1[4]~output, top, 1
+instance = comp, \HEX1[5]~output , HEX1[5]~output, top, 1
+instance = comp, \HEX1[6]~output , HEX1[6]~output, top, 1
+instance = comp, \HEX2[0]~output , HEX2[0]~output, top, 1
+instance = comp, \HEX2[1]~output , HEX2[1]~output, top, 1
+instance = comp, \HEX2[2]~output , HEX2[2]~output, top, 1
+instance = comp, \HEX2[3]~output , HEX2[3]~output, top, 1
+instance = comp, \HEX2[4]~output , HEX2[4]~output, top, 1
+instance = comp, \HEX2[5]~output , HEX2[5]~output, top, 1
+instance = comp, \HEX2[6]~output , HEX2[6]~output, top, 1
+instance = comp, \HEX3[0]~output , HEX3[0]~output, top, 1
+instance = comp, \HEX3[1]~output , HEX3[1]~output, top, 1
+instance = comp, \HEX3[2]~output , HEX3[2]~output, top, 1
+instance = comp, \HEX3[3]~output , HEX3[3]~output, top, 1
+instance = comp, \HEX3[4]~output , HEX3[4]~output, top, 1
+instance = comp, \HEX3[5]~output , HEX3[5]~output, top, 1
+instance = comp, \HEX3[6]~output , HEX3[6]~output, top, 1
+instance = comp, \DAC_SDI~output , DAC_SDI~output, top, 1
+instance = comp, \DAC_SCK~output , DAC_SCK~output, top, 1
+instance = comp, \DAC_CS~output , DAC_CS~output, top, 1
+instance = comp, \DAC_LD~output , DAC_LD~output, top, 1
+instance = comp, \ADC_SDI~output , ADC_SDI~output, top, 1
+instance = comp, \ADC_SCK~output , ADC_SCK~output, top, 1
+instance = comp, \ADC_CS~output , ADC_CS~output, top, 1
+instance = comp, \PWM_OUT~output , PWM_OUT~output, top, 1
+instance = comp, \SW[4]~input , SW[4]~input, top, 1
+instance = comp, \SW[5]~input , SW[5]~input, top, 1
+instance = comp, \SW[6]~input , SW[6]~input, top, 1
+instance = comp, \SW[1]~input , SW[1]~input, top, 1
+instance = comp, \SW[0]~input , SW[0]~input, top, 1
+instance = comp, \SW[2]~input , SW[2]~input, top, 1
+instance = comp, \SW[3]~input , SW[3]~input, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|romout[0][12]~2 , SCALER|lpm_mult_component|mult_core|romout[0][12]~2, top, 1
+instance = comp, \SW[7]~input , SW[7]~input, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|romout[0][11]~1 , SCALER|lpm_mult_component|mult_core|romout[0][11]~1, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|romout[0][10]~0 , SCALER|lpm_mult_component|mult_core|romout[0][10]~0, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|romout[1][9]~5 , SCALER|lpm_mult_component|mult_core|romout[1][9]~5, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|romout[1][4]~6 , SCALER|lpm_mult_component|mult_core|romout[1][4]~6, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~50, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~46, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~42, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~9, top, 1
+instance = comp, \SW[8]~input , SW[8]~input, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~42, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|romout[0][14]~4 , SCALER|lpm_mult_component|mult_core|romout[0][14]~4, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|romout[0][13]~3 , SCALER|lpm_mult_component|mult_core|romout[0][13]~3, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 , SCALER|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33, top, 1
+instance = comp, \SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 , SCALER|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37, top, 1
+instance = comp, \BCD_CONVERT|A9|WideOr2~0 , BCD_CONVERT|A9|WideOr2~0, top, 1
+instance = comp, \BCD_CONVERT|A9|WideOr1~0 , BCD_CONVERT|A9|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A9|WideOr3~0 , BCD_CONVERT|A9|WideOr3~0, top, 1
+instance = comp, \BCD_CONVERT|A12|WideOr1~0 , BCD_CONVERT|A12|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A12|WideOr2~0 , BCD_CONVERT|A12|WideOr2~0, top, 1
+instance = comp, \BCD_CONVERT|A12|WideOr3~0 , BCD_CONVERT|A12|WideOr3~0, top, 1
+instance = comp, \BCD_CONVERT|A15|WideOr1~0 , BCD_CONVERT|A15|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A15|WideOr2~0 , BCD_CONVERT|A15|WideOr2~0, top, 1
+instance = comp, \BCD_CONVERT|A15|WideOr3~0 , BCD_CONVERT|A15|WideOr3~0, top, 1
+instance = comp, \BCD_CONVERT|A18|WideOr2~0 , BCD_CONVERT|A18|WideOr2~0, top, 1
+instance = comp, \BCD_CONVERT|A18|WideOr1~0 , BCD_CONVERT|A18|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A18|WideOr3~0 , BCD_CONVERT|A18|WideOr3~0, top, 1
+instance = comp, \BCD_CONVERT|A21|WideOr1~0 , BCD_CONVERT|A21|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A21|WideOr3~0 , BCD_CONVERT|A21|WideOr3~0, top, 1
+instance = comp, \BCD_CONVERT|A21|WideOr2~0 , BCD_CONVERT|A21|WideOr2~0, top, 1
+instance = comp, \BCD_CONVERT|A25|WideOr2~0 , BCD_CONVERT|A25|WideOr2~0, top, 1
+instance = comp, \BCD_CONVERT|A25|WideOr1~0 , BCD_CONVERT|A25|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A25|WideOr3~0 , BCD_CONVERT|A25|WideOr3~0, top, 1
+instance = comp, \SEG0|WideOr6~0 , SEG0|WideOr6~0, top, 1
+instance = comp, \SEG0|WideOr5~0 , SEG0|WideOr5~0, top, 1
+instance = comp, \SEG0|WideOr4~0 , SEG0|WideOr4~0, top, 1
+instance = comp, \SEG0|WideOr3~0 , SEG0|WideOr3~0, top, 1
+instance = comp, \SEG0|WideOr2~0 , SEG0|WideOr2~0, top, 1
+instance = comp, \SEG0|WideOr1~0 , SEG0|WideOr1~0, top, 1
+instance = comp, \SEG0|WideOr0~0 , SEG0|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A25|WideOr0~0 , BCD_CONVERT|A25|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A17|WideOr1~0 , BCD_CONVERT|A17|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A17|WideOr3~0 , BCD_CONVERT|A17|WideOr3~0, top, 1
+instance = comp, \BCD_CONVERT|A17|WideOr2~0 , BCD_CONVERT|A17|WideOr2~0, top, 1
+instance = comp, \BCD_CONVERT|A18|WideOr0~0 , BCD_CONVERT|A18|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A20|WideOr2~0 , BCD_CONVERT|A20|WideOr2~0, top, 1
+instance = comp, \BCD_CONVERT|A20|WideOr3~0 , BCD_CONVERT|A20|WideOr3~0, top, 1
+instance = comp, \BCD_CONVERT|A20|WideOr1~0 , BCD_CONVERT|A20|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A21|WideOr0~0 , BCD_CONVERT|A21|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A24|WideOr3~0 , BCD_CONVERT|A24|WideOr3~0, top, 1
+instance = comp, \BCD_CONVERT|A24|WideOr1~0 , BCD_CONVERT|A24|WideOr1~0, top, 1
+instance = comp, \BCD_CONVERT|A24|WideOr2~0 , BCD_CONVERT|A24|WideOr2~0, top, 1
+instance = comp, \SEG1|WideOr6~0 , SEG1|WideOr6~0, top, 1
+instance = comp, \SEG1|WideOr5~0 , SEG1|WideOr5~0, top, 1
+instance = comp, \SEG1|WideOr4~0 , SEG1|WideOr4~0, top, 1
+instance = comp, \SEG1|WideOr3~0 , SEG1|WideOr3~0, top, 1
+instance = comp, \SEG1|WideOr2~0 , SEG1|WideOr2~0, top, 1
+instance = comp, \SEG1|WideOr1~0 , SEG1|WideOr1~0, top, 1
+instance = comp, \SEG1|WideOr0~0 , SEG1|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A24|WideOr0~0 , BCD_CONVERT|A24|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A20|WideOr0~0 , BCD_CONVERT|A20|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A17|WideOr0~0 , BCD_CONVERT|A17|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A7|WideOr0~0 , BCD_CONVERT|A7|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A9|WideOr0~0 , BCD_CONVERT|A9|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A12|WideOr0~0 , BCD_CONVERT|A12|WideOr0~0, top, 1
+instance = comp, \BCD_CONVERT|A14|WideOr0~0 , BCD_CONVERT|A14|WideOr0~0, top, 1
+instance = comp, \SEG2|Decoder0~1 , SEG2|Decoder0~1, top, 1
+instance = comp, \SEG2|Decoder0~0 , SEG2|Decoder0~0, top, 1
+instance = comp, \SEG2|WideOr6 , SEG2|WideOr6, top, 1
+instance = comp, \SEG2|Decoder0~2 , SEG2|Decoder0~2, top, 1
+instance = comp, \SEG2|WideOr5 , SEG2|WideOr5, top, 1
+instance = comp, \SEG2|Decoder0~3 , SEG2|Decoder0~3, top, 1
+instance = comp, \SEG2|Decoder0~4 , SEG2|Decoder0~4, top, 1
+instance = comp, \SEG2|Decoder0~5 , SEG2|Decoder0~5, top, 1
+instance = comp, \SEG2|WideOr2~0 , SEG2|WideOr2~0, top, 1
+instance = comp, \SEG2|Decoder0~6 , SEG2|Decoder0~6, top, 1
+instance = comp, \SEG2|WideOr2 , SEG2|WideOr2, top, 1
+instance = comp, \SEG2|WideOr1 , SEG2|WideOr1, top, 1
+instance = comp, \SEG2|WideOr0 , SEG2|WideOr0, top, 1
+instance = comp, \BCD_CONVERT|A23|WideOr0~0 , BCD_CONVERT|A23|WideOr0~0, top, 1
+instance = comp, \CLOCK_50~input , CLOCK_50~input, top, 1
+instance = comp, \SPI_DAC|clk_1MHz~0 , SPI_DAC|clk_1MHz~0, top, 1
+instance = comp, \CLOCK_50~inputCLKENA0 , CLOCK_50~inputCLKENA0, top, 1
+instance = comp, \SPI_ADC|ctr[4] , SPI_ADC|ctr[4], top, 1
+instance = comp, \SPI_ADC|ctr[0] , SPI_ADC|ctr[0], top, 1
+instance = comp, \SPI_ADC|Add0~0 , SPI_ADC|Add0~0, top, 1
+instance = comp, \SPI_ADC|ctr[4]~DUPLICATE , SPI_ADC|ctr[4]~DUPLICATE, top, 1
+instance = comp, \SPI_ADC|ctr[1] , SPI_ADC|ctr[1], top, 1
+instance = comp, \SPI_ADC|ctr[3] , SPI_ADC|ctr[3], top, 1
+instance = comp, \SPI_ADC|ctr~2 , SPI_ADC|ctr~2, top, 1
+instance = comp, \SPI_ADC|ctr[1]~DUPLICATE , SPI_ADC|ctr[1]~DUPLICATE, top, 1
+instance = comp, \SPI_ADC|ctr~1 , SPI_ADC|ctr~1, top, 1
+instance = comp, \SPI_ADC|ctr[0]~DUPLICATE , SPI_ADC|ctr[0]~DUPLICATE, top, 1
+instance = comp, \SPI_ADC|ctr[2] , SPI_ADC|ctr[2], top, 1
+instance = comp, \SPI_ADC|ctr~0 , SPI_ADC|ctr~0, top, 1
+instance = comp, \SPI_ADC|ctr[2]~DUPLICATE , SPI_ADC|ctr[2]~DUPLICATE, top, 1
+instance = comp, \SPI_ADC|Add0~1 , SPI_ADC|Add0~1, top, 1
+instance = comp, \SPI_ADC|ctr[3]~DUPLICATE , SPI_ADC|ctr[3]~DUPLICATE, top, 1
+instance = comp, \SPI_DAC|Equal0~0 , SPI_DAC|Equal0~0, top, 1
+instance = comp, \SPI_DAC|clk_1MHz , SPI_DAC|clk_1MHz, top, 1
+instance = comp, \SPI_DAC|Selector6~0 , SPI_DAC|Selector6~0, top, 1
+instance = comp, \SPI_DAC|state[2] , SPI_DAC|state[2], top, 1
+instance = comp, \SPI_DAC|Selector5~0 , SPI_DAC|Selector5~0, top, 1
+instance = comp, \SPI_DAC|state[3]~DUPLICATE , SPI_DAC|state[3]~DUPLICATE, top, 1
+instance = comp, \SPI_DAC|Selector4~0 , SPI_DAC|Selector4~0, top, 1
+instance = comp, \SPI_DAC|state[4]~feeder , SPI_DAC|state[4]~feeder, top, 1
+instance = comp, \SPI_DAC|state[4] , SPI_DAC|state[4], top, 1
+instance = comp, \SPI_DAC|state[3] , SPI_DAC|state[3], top, 1
+instance = comp, \SPI_DAC|Selector8~0 , SPI_DAC|Selector8~0, top, 1
+instance = comp, \SPI_DAC|state[0] , SPI_DAC|state[0], top, 1
+instance = comp, \SPI_DAC|Selector7~0 , SPI_DAC|Selector7~0, top, 1
+instance = comp, \SPI_DAC|state[1] , SPI_DAC|state[1], top, 1
+instance = comp, \SPI_DAC|Selector9~0 , SPI_DAC|Selector9~0, top, 1
+instance = comp, \SPI_DAC|dac_cs , SPI_DAC|dac_cs, top, 1
+instance = comp, \GEN_10K|Add0~41 , GEN_10K|Add0~41, top, 1
+instance = comp, \GEN_10K|ctr[0] , GEN_10K|ctr[0], top, 1
+instance = comp, \GEN_10K|Add0~45 , GEN_10K|Add0~45, top, 1
+instance = comp, \GEN_10K|ctr[1] , GEN_10K|ctr[1], top, 1
+instance = comp, \GEN_10K|Add0~77 , GEN_10K|Add0~77, top, 1
+instance = comp, \GEN_10K|Add0~53 , GEN_10K|Add0~53, top, 1
+instance = comp, \GEN_10K|Add0~57 , GEN_10K|Add0~57, top, 1
+instance = comp, \GEN_10K|ctr[8] , GEN_10K|ctr[8], top, 1
+instance = comp, \GEN_10K|Add0~21 , GEN_10K|Add0~21, top, 1
+instance = comp, \GEN_10K|ctr[9] , GEN_10K|ctr[9], top, 1
+instance = comp, \GEN_10K|Add0~25 , GEN_10K|Add0~25, top, 1
+instance = comp, \GEN_10K|ctr[10] , GEN_10K|ctr[10], top, 1
+instance = comp, \GEN_10K|Add0~61 , GEN_10K|Add0~61, top, 1
+instance = comp, \GEN_10K|ctr[11] , GEN_10K|ctr[11], top, 1
+instance = comp, \GEN_10K|Add0~29 , GEN_10K|Add0~29, top, 1
+instance = comp, \GEN_10K|ctr[12] , GEN_10K|ctr[12], top, 1
+instance = comp, \GEN_10K|Add0~33 , GEN_10K|Add0~33, top, 1
+instance = comp, \GEN_10K|ctr[13] , GEN_10K|ctr[13], top, 1
+instance = comp, \GEN_10K|Add0~37 , GEN_10K|Add0~37, top, 1
+instance = comp, \GEN_10K|ctr[14] , GEN_10K|ctr[14], top, 1
+instance = comp, \GEN_10K|Add0~5 , GEN_10K|Add0~5, top, 1
+instance = comp, \GEN_10K|ctr[15] , GEN_10K|ctr[15], top, 1
+instance = comp, \GEN_10K|Add0~9 , GEN_10K|Add0~9, top, 1
+instance = comp, \GEN_10K|ctr[16] , GEN_10K|ctr[16], top, 1
+instance = comp, \GEN_10K|Add0~13 , GEN_10K|Add0~13, top, 1
+instance = comp, \GEN_10K|ctr[17] , GEN_10K|ctr[17], top, 1
+instance = comp, \GEN_10K|Add0~65 , GEN_10K|Add0~65, top, 1
+instance = comp, \GEN_10K|ctr[18] , GEN_10K|ctr[18], top, 1
+instance = comp, \GEN_10K|Add0~69 , GEN_10K|Add0~69, top, 1
+instance = comp, \GEN_10K|ctr[19] , GEN_10K|ctr[19], top, 1
+instance = comp, \GEN_10K|Equal0~3 , GEN_10K|Equal0~3, top, 1
+instance = comp, \GEN_10K|Add0~1 , GEN_10K|Add0~1, top, 1
+instance = comp, \GEN_10K|ctr[20] , GEN_10K|ctr[20], top, 1
+instance = comp, \GEN_10K|Equal0~0 , GEN_10K|Equal0~0, top, 1
+instance = comp, \GEN_10K|Equal0~1 , GEN_10K|Equal0~1, top, 1
+instance = comp, \GEN_10K|Equal0~4 , GEN_10K|Equal0~4, top, 1
+instance = comp, \GEN_10K|ctr[2] , GEN_10K|ctr[2], top, 1
+instance = comp, \GEN_10K|Add0~81 , GEN_10K|Add0~81, top, 1
+instance = comp, \GEN_10K|ctr[3] , GEN_10K|ctr[3], top, 1
+instance = comp, \GEN_10K|Add0~73 , GEN_10K|Add0~73, top, 1
+instance = comp, \GEN_10K|ctr[4] , GEN_10K|ctr[4], top, 1
+instance = comp, \GEN_10K|Add0~17 , GEN_10K|Add0~17, top, 1
+instance = comp, \GEN_10K|ctr[5] , GEN_10K|ctr[5], top, 1
+instance = comp, \GEN_10K|Add0~49 , GEN_10K|Add0~49, top, 1
+instance = comp, \GEN_10K|ctr[6] , GEN_10K|ctr[6], top, 1
+instance = comp, \GEN_10K|ctr[7] , GEN_10K|ctr[7], top, 1
+instance = comp, \GEN_10K|Equal0~2 , GEN_10K|Equal0~2, top, 1
+instance = comp, \GEN_10K|clkout , GEN_10K|clkout, top, 1
+instance = comp, \GEN_10K|clkout~0 , GEN_10K|clkout~0, top, 1
+instance = comp, \GEN_10K|clkout~DUPLICATE , GEN_10K|clkout~DUPLICATE, top, 1
+instance = comp, \PULSE|state.IDLE , PULSE|state.IDLE, top, 1
+instance = comp, \PULSE|pulse~1 , PULSE|pulse~1, top, 1
+instance = comp, \PULSE|pulse , PULSE|pulse, top, 1
+instance = comp, \SPI_DAC|Selector2~0 , SPI_DAC|Selector2~0, top, 1
+instance = comp, \SPI_DAC|sr_state.WAIT_CSB_HIGH , SPI_DAC|sr_state.WAIT_CSB_HIGH, top, 1
+instance = comp, \SPI_DAC|Selector0~0 , SPI_DAC|Selector0~0, top, 1
+instance = comp, \SPI_DAC|sr_state.IDLE , SPI_DAC|sr_state.IDLE, top, 1
+instance = comp, \SPI_DAC|Selector1~0 , SPI_DAC|Selector1~0, top, 1
+instance = comp, \SPI_DAC|sr_state.WAIT_CSB_FALL , SPI_DAC|sr_state.WAIT_CSB_FALL, top, 1
+instance = comp, \SPI_DAC|dac_start~0 , SPI_DAC|dac_start~0, top, 1
+instance = comp, \SPI_DAC|dac_start , SPI_DAC|dac_start, top, 1
+instance = comp, \SPI_ADC|clk_1MHz~0 , SPI_ADC|clk_1MHz~0, top, 1
+instance = comp, \SPI_ADC|clk_1MHz , SPI_ADC|clk_1MHz, top, 1
+instance = comp, \SPI_ADC|state[1]~0 , SPI_ADC|state[1]~0, top, 1
+instance = comp, \SPI_ADC|state[1] , SPI_ADC|state[1], top, 1
+instance = comp, \SPI_ADC|state[2]~2 , SPI_ADC|state[2]~2, top, 1
+instance = comp, \SPI_ADC|state[2] , SPI_ADC|state[2], top, 1
+instance = comp, \SPI_ADC|Selector2~0 , SPI_ADC|Selector2~0, top, 1
+instance = comp, \SPI_ADC|sr_state.WAIT_CSB_HIGH , SPI_ADC|sr_state.WAIT_CSB_HIGH, top, 1
+instance = comp, \SPI_ADC|Selector0~0 , SPI_ADC|Selector0~0, top, 1
+instance = comp, \SPI_ADC|sr_state.IDLE , SPI_ADC|sr_state.IDLE, top, 1
+instance = comp, \SPI_ADC|Selector1~0 , SPI_ADC|Selector1~0, top, 1
+instance = comp, \SPI_ADC|sr_state.WAIT_CSB_FALL , SPI_ADC|sr_state.WAIT_CSB_FALL, top, 1
+instance = comp, \SPI_ADC|adc_start~0 , SPI_ADC|adc_start~0, top, 1
+instance = comp, \SPI_ADC|adc_start , SPI_ADC|adc_start, top, 1
+instance = comp, \SPI_ADC|Selector5~0 , SPI_ADC|Selector5~0, top, 1
+instance = comp, \SPI_ADC|state[0] , SPI_ADC|state[0], top, 1
+instance = comp, \SPI_ADC|state[3]~3 , SPI_ADC|state[3]~3, top, 1
+instance = comp, \SPI_ADC|state[3] , SPI_ADC|state[3], top, 1
+instance = comp, \SPI_ADC|state~1 , SPI_ADC|state~1, top, 1
+instance = comp, \SPI_ADC|state[4] , SPI_ADC|state[4], top, 1
+instance = comp, \SPI_ADC|adc_start~DUPLICATE , SPI_ADC|adc_start~DUPLICATE, top, 1
+instance = comp, \SPI_ADC|Selector4~0 , SPI_ADC|Selector4~0, top, 1
+instance = comp, \SPI_ADC|adc_cs , SPI_ADC|adc_cs, top, 1
+instance = comp, \ECHO|PULSE2|state.IDLE~0 , ECHO|PULSE2|state.IDLE~0, top, 1
+instance = comp, \ECHO|PULSE2|state.IDLE , ECHO|PULSE2|state.IDLE, top, 1
+instance = comp, \ECHO|PULSE2|pulse~1 , ECHO|PULSE2|pulse~1, top, 1
+instance = comp, \ECHO|PULSE2|pulse , ECHO|PULSE2|pulse, top, 1
+instance = comp, \ECHO|ctr[0]~0 , ECHO|ctr[0]~0, top, 1
+instance = comp, \ECHO|ctr[0] , ECHO|ctr[0], top, 1
+instance = comp, \ECHO|Add1~1 , ECHO|Add1~1, top, 1
+instance = comp, \ECHO|ctr[1] , ECHO|ctr[1], top, 1
+instance = comp, \ECHO|ctr[2] , ECHO|ctr[2], top, 1
+instance = comp, \ECHO|Add1~5 , ECHO|Add1~5, top, 1
+instance = comp, \ECHO|ctr[2]~DUPLICATE , ECHO|ctr[2]~DUPLICATE, top, 1
+instance = comp, \ECHO|Add1~9 , ECHO|Add1~9, top, 1
+instance = comp, \ECHO|ctr[3] , ECHO|ctr[3], top, 1
+instance = comp, \ECHO|ctr[4] , ECHO|ctr[4], top, 1
+instance = comp, \ECHO|Add1~13 , ECHO|Add1~13, top, 1
+instance = comp, \ECHO|ctr[4]~DUPLICATE , ECHO|ctr[4]~DUPLICATE, top, 1
+instance = comp, \ECHO|Add2~1 , ECHO|Add2~1, top, 1
+instance = comp, \ECHO|Add1~17 , ECHO|Add1~17, top, 1
+instance = comp, \ECHO|ctr[5] , ECHO|ctr[5], top, 1
+instance = comp, \ECHO|Add2~5 , ECHO|Add2~5, top, 1
+instance = comp, \ECHO|Add1~21 , ECHO|Add1~21, top, 1
+instance = comp, \ECHO|ctr[6] , ECHO|ctr[6], top, 1
+instance = comp, \ECHO|Add2~9 , ECHO|Add2~9, top, 1
+instance = comp, \ECHO|Add1~25 , ECHO|Add1~25, top, 1
+instance = comp, \ECHO|ctr[7] , ECHO|ctr[7], top, 1
+instance = comp, \ECHO|Add2~13 , ECHO|Add2~13, top, 1
+instance = comp, \ECHO|Add1~29 , ECHO|Add1~29, top, 1
+instance = comp, \ECHO|ctr[8] , ECHO|ctr[8], top, 1
+instance = comp, \ECHO|Add2~17 , ECHO|Add2~17, top, 1
+instance = comp, \ECHO|Add1~33 , ECHO|Add1~33, top, 1
+instance = comp, \ECHO|ctr[9] , ECHO|ctr[9], top, 1
+instance = comp, \ECHO|Add2~21 , ECHO|Add2~21, top, 1
+instance = comp, \ECHO|Add1~37 , ECHO|Add1~37, top, 1
+instance = comp, \ECHO|ctr[10] , ECHO|ctr[10], top, 1
+instance = comp, \ECHO|Add2~25 , ECHO|Add2~25, top, 1
+instance = comp, \ECHO|ctr[11] , ECHO|ctr[11], top, 1
+instance = comp, \ECHO|Add1~41 , ECHO|Add1~41, top, 1
+instance = comp, \ECHO|ctr[11]~DUPLICATE , ECHO|ctr[11]~DUPLICATE, top, 1
+instance = comp, \ECHO|Add2~29 , ECHO|Add2~29, top, 1
+instance = comp, \ECHO|Add1~45 , ECHO|Add1~45, top, 1
+instance = comp, \ECHO|ctr[12] , ECHO|ctr[12], top, 1
+instance = comp, \ECHO|Add2~33 , ECHO|Add2~33, top, 1
+instance = comp, \ECHO|ctr[6]~DUPLICATE , ECHO|ctr[6]~DUPLICATE, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a8, top, 1
+instance = comp, \ADC_SDO~input , ADC_SDO~input, top, 1
+instance = comp, \SPI_ADC|shift_reg[0]~feeder , SPI_ADC|shift_reg[0]~feeder, top, 1
+instance = comp, \SPI_ADC|WideOr0~0 , SPI_ADC|WideOr0~0, top, 1
+instance = comp, \SPI_ADC|shift_ena , SPI_ADC|shift_ena, top, 1
+instance = comp, \SPI_ADC|always3~0 , SPI_ADC|always3~0, top, 1
+instance = comp, \SPI_ADC|shift_reg[0] , SPI_ADC|shift_reg[0], top, 1
+instance = comp, \SPI_ADC|shift_reg[1]~feeder , SPI_ADC|shift_reg[1]~feeder, top, 1
+instance = comp, \SPI_ADC|shift_reg[1] , SPI_ADC|shift_reg[1], top, 1
+instance = comp, \SPI_ADC|shift_reg[2]~feeder , SPI_ADC|shift_reg[2]~feeder, top, 1
+instance = comp, \SPI_ADC|shift_reg[2] , SPI_ADC|shift_reg[2], top, 1
+instance = comp, \SPI_ADC|shift_reg[3]~feeder , SPI_ADC|shift_reg[3]~feeder, top, 1
+instance = comp, \SPI_ADC|shift_reg[3] , SPI_ADC|shift_reg[3], top, 1
+instance = comp, \SPI_ADC|shift_reg[4]~feeder , SPI_ADC|shift_reg[4]~feeder, top, 1
+instance = comp, \SPI_ADC|shift_reg[4] , SPI_ADC|shift_reg[4], top, 1
+instance = comp, \SPI_ADC|shift_reg[5] , SPI_ADC|shift_reg[5], top, 1
+instance = comp, \SPI_ADC|shift_reg[6] , SPI_ADC|shift_reg[6], top, 1
+instance = comp, \SPI_ADC|shift_reg[7] , SPI_ADC|shift_reg[7], top, 1
+instance = comp, \SPI_ADC|shift_reg[8] , SPI_ADC|shift_reg[8], top, 1
+instance = comp, \SPI_ADC|shift_reg[9]~feeder , SPI_ADC|shift_reg[9]~feeder, top, 1
+instance = comp, \SPI_ADC|shift_reg[9] , SPI_ADC|shift_reg[9], top, 1
+instance = comp, \SPI_ADC|Decoder0~0 , SPI_ADC|Decoder0~0, top, 1
+instance = comp, \SPI_ADC|adc_done , SPI_ADC|adc_done, top, 1
+instance = comp, \SPI_ADC|data_from_adc[9] , SPI_ADC|data_from_adc[9], top, 1
+instance = comp, \SPI_ADC|data_from_adc[8]~feeder , SPI_ADC|data_from_adc[8]~feeder, top, 1
+instance = comp, \SPI_ADC|data_from_adc[8] , SPI_ADC|data_from_adc[8], top, 1
+instance = comp, \ECHO|Add0~33 , ECHO|Add0~33, top, 1
+instance = comp, \SPI_ADC|data_from_adc[7] , SPI_ADC|data_from_adc[7], top, 1
+instance = comp, \ECHO|Add3~9 , ECHO|Add3~9, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a6, top, 1
+instance = comp, \SPI_ADC|shift_reg[6]~DUPLICATE , SPI_ADC|shift_reg[6]~DUPLICATE, top, 1
+instance = comp, \SPI_ADC|data_from_adc[6] , SPI_ADC|data_from_adc[6], top, 1
+instance = comp, \ECHO|Add0~1 , ECHO|Add0~1, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a5, top, 1
+instance = comp, \SPI_ADC|data_from_adc[5] , SPI_ADC|data_from_adc[5], top, 1
+instance = comp, \ECHO|Add0~5 , ECHO|Add0~5, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a4, top, 1
+instance = comp, \SPI_ADC|data_from_adc[4] , SPI_ADC|data_from_adc[4], top, 1
+instance = comp, \ECHO|Add0~9 , ECHO|Add0~9, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a3, top, 1
+instance = comp, \SPI_ADC|data_from_adc[3]~feeder , SPI_ADC|data_from_adc[3]~feeder, top, 1
+instance = comp, \SPI_ADC|data_from_adc[3] , SPI_ADC|data_from_adc[3], top, 1
+instance = comp, \SPI_ADC|data_from_adc[2]~feeder , SPI_ADC|data_from_adc[2]~feeder, top, 1
+instance = comp, \SPI_ADC|data_from_adc[2] , SPI_ADC|data_from_adc[2], top, 1
+instance = comp, \ECHO|Add0~13 , ECHO|Add0~13, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a2, top, 1
+instance = comp, \SPI_ADC|data_from_adc[1]~feeder , SPI_ADC|data_from_adc[1]~feeder, top, 1
+instance = comp, \SPI_ADC|data_from_adc[1] , SPI_ADC|data_from_adc[1], top, 1
+instance = comp, \ECHO|Add0~17 , ECHO|Add0~17, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a1, top, 1
+instance = comp, \ECHO|Add0~21 , ECHO|Add0~21, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a0, top, 1
+instance = comp, \SPI_ADC|data_from_adc[0]~feeder , SPI_ADC|data_from_adc[0]~feeder, top, 1
+instance = comp, \SPI_ADC|data_from_adc[0] , SPI_ADC|data_from_adc[0], top, 1
+instance = comp, \ECHO|Add0~25 , ECHO|Add0~25, top, 1
+instance = comp, \ECHO|Add0~37 , ECHO|Add0~37, top, 1
+instance = comp, \ECHO|Add3~5 , ECHO|Add3~5, top, 1
+instance = comp, \ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7 , ECHO|DELAY|altsyncram_component|auto_generated|ram_block1a7, top, 1
+instance = comp, \ECHO|Add0~29 , ECHO|Add0~29, top, 1
+instance = comp, \ECHO|Add3~1 , ECHO|Add3~1, top, 1
+instance = comp, \ECHO|data_out[9]~0 , ECHO|data_out[9]~0, top, 1
+instance = comp, \ECHO|data_out[9] , ECHO|data_out[9], top, 1
+instance = comp, \SPI_DAC|shift_reg[11]~feeder , SPI_DAC|shift_reg[11]~feeder, top, 1
+instance = comp, \ECHO|data_out[8] , ECHO|data_out[8], top, 1
+instance = comp, \SPI_DAC|shift_reg[10]~feeder , SPI_DAC|shift_reg[10]~feeder, top, 1
+instance = comp, \ECHO|data_out[7] , ECHO|data_out[7], top, 1
+instance = comp, \SPI_DAC|shift_reg[9]~feeder , SPI_DAC|shift_reg[9]~feeder, top, 1
+instance = comp, \ECHO|data_out[6] , ECHO|data_out[6], top, 1
+instance = comp, \SPI_DAC|shift_reg[8]~feeder , SPI_DAC|shift_reg[8]~feeder, top, 1
+instance = comp, \ECHO|data_out[5] , ECHO|data_out[5], top, 1
+instance = comp, \SPI_DAC|shift_reg[7]~feeder , SPI_DAC|shift_reg[7]~feeder, top, 1
+instance = comp, \ECHO|data_out[4] , ECHO|data_out[4], top, 1
+instance = comp, \SPI_DAC|shift_reg[6]~feeder , SPI_DAC|shift_reg[6]~feeder, top, 1
+instance = comp, \ECHO|data_out[3] , ECHO|data_out[3], top, 1
+instance = comp, \SPI_DAC|shift_reg[5]~feeder , SPI_DAC|shift_reg[5]~feeder, top, 1
+instance = comp, \ECHO|data_out[2] , ECHO|data_out[2], top, 1
+instance = comp, \SPI_DAC|shift_reg[4]~feeder , SPI_DAC|shift_reg[4]~feeder, top, 1
+instance = comp, \ECHO|data_out[1] , ECHO|data_out[1], top, 1
+instance = comp, \SPI_DAC|shift_reg[3]~feeder , SPI_DAC|shift_reg[3]~feeder, top, 1
+instance = comp, \ECHO|data_out[0] , ECHO|data_out[0], top, 1
+instance = comp, \SPI_DAC|shift_reg~4 , SPI_DAC|shift_reg~4, top, 1
+instance = comp, \SPI_DAC|shift_reg[2] , SPI_DAC|shift_reg[2], top, 1
+instance = comp, \SPI_DAC|always3~0 , SPI_DAC|always3~0, top, 1
+instance = comp, \SPI_DAC|shift_reg[3] , SPI_DAC|shift_reg[3], top, 1
+instance = comp, \SPI_DAC|shift_reg[4] , SPI_DAC|shift_reg[4], top, 1
+instance = comp, \SPI_DAC|shift_reg[5] , SPI_DAC|shift_reg[5], top, 1
+instance = comp, \SPI_DAC|shift_reg[6] , SPI_DAC|shift_reg[6], top, 1
+instance = comp, \SPI_DAC|shift_reg[7] , SPI_DAC|shift_reg[7], top, 1
+instance = comp, \SPI_DAC|shift_reg[8] , SPI_DAC|shift_reg[8], top, 1
+instance = comp, \SPI_DAC|shift_reg[9] , SPI_DAC|shift_reg[9], top, 1
+instance = comp, \SPI_DAC|shift_reg[10] , SPI_DAC|shift_reg[10], top, 1
+instance = comp, \SPI_DAC|shift_reg[11] , SPI_DAC|shift_reg[11], top, 1
+instance = comp, \SPI_DAC|shift_reg~3 , SPI_DAC|shift_reg~3, top, 1
+instance = comp, \SPI_DAC|shift_reg[12] , SPI_DAC|shift_reg[12], top, 1
+instance = comp, \SPI_DAC|shift_reg~2 , SPI_DAC|shift_reg~2, top, 1
+instance = comp, \SPI_DAC|shift_reg[13] , SPI_DAC|shift_reg[13], top, 1
+instance = comp, \SPI_DAC|shift_reg~1 , SPI_DAC|shift_reg~1, top, 1
+instance = comp, \SPI_DAC|shift_reg[14] , SPI_DAC|shift_reg[14], top, 1
+instance = comp, \SPI_DAC|shift_reg~0 , SPI_DAC|shift_reg~0, top, 1
+instance = comp, \SPI_DAC|shift_reg[15] , SPI_DAC|shift_reg[15], top, 1
+instance = comp, \SPI_DAC|dac_sck , SPI_DAC|dac_sck, top, 1
+instance = comp, \SPI_DAC|Equal2~0 , SPI_DAC|Equal2~0, top, 1
+instance = comp, \SPI_DAC|dac_ld , SPI_DAC|dac_ld, top, 1
+instance = comp, \SW[9]~input , SW[9]~input, top, 1
+instance = comp, \SPI_ADC|Selector6~0 , SPI_ADC|Selector6~0, top, 1
+instance = comp, \SPI_ADC|adc_din , SPI_ADC|adc_din, top, 1
+instance = comp, \SPI_ADC|adc_sck , SPI_ADC|adc_sck, top, 1
+instance = comp, \PWM_DC|count[0]~0 , PWM_DC|count[0]~0, top, 1
+instance = comp, \PWM_DC|count[0] , PWM_DC|count[0], top, 1
+instance = comp, \PWM_DC|Add0~33 , PWM_DC|Add0~33, top, 1
+instance = comp, \PWM_DC|count[1] , PWM_DC|count[1], top, 1
+instance = comp, \PWM_DC|Add0~29 , PWM_DC|Add0~29, top, 1
+instance = comp, \PWM_DC|count[2] , PWM_DC|count[2], top, 1
+instance = comp, \PWM_DC|Add0~25 , PWM_DC|Add0~25, top, 1
+instance = comp, \PWM_DC|count[3] , PWM_DC|count[3], top, 1
+instance = comp, \PWM_DC|Add0~21 , PWM_DC|Add0~21, top, 1
+instance = comp, \PWM_DC|count[4] , PWM_DC|count[4], top, 1
+instance = comp, \PWM_DC|Add0~17 , PWM_DC|Add0~17, top, 1
+instance = comp, \PWM_DC|count[5] , PWM_DC|count[5], top, 1
+instance = comp, \PWM_DC|Add0~13 , PWM_DC|Add0~13, top, 1
+instance = comp, \PWM_DC|count[6] , PWM_DC|count[6], top, 1
+instance = comp, \PWM_DC|Add0~9 , PWM_DC|Add0~9, top, 1
+instance = comp, \PWM_DC|count[7] , PWM_DC|count[7], top, 1
+instance = comp, \PWM_DC|Add0~5 , PWM_DC|Add0~5, top, 1
+instance = comp, \PWM_DC|count[8] , PWM_DC|count[8], top, 1
+instance = comp, \PWM_DC|Add0~1 , PWM_DC|Add0~1, top, 1
+instance = comp, \PWM_DC|count[9] , PWM_DC|count[9], top, 1
+instance = comp, \PWM_DC|d[7] , PWM_DC|d[7], top, 1
+instance = comp, \PWM_DC|LessThan0~0 , PWM_DC|LessThan0~0, top, 1
+instance = comp, \PWM_DC|LessThan0~1 , PWM_DC|LessThan0~1, top, 1
+instance = comp, \PWM_DC|d[0]~feeder , PWM_DC|d[0]~feeder, top, 1
+instance = comp, \PWM_DC|d[0] , PWM_DC|d[0], top, 1
+instance = comp, \PWM_DC|d[2] , PWM_DC|d[2], top, 1
+instance = comp, \PWM_DC|d[1] , PWM_DC|d[1], top, 1
+instance = comp, \PWM_DC|LessThan0~2 , PWM_DC|LessThan0~2, top, 1
+instance = comp, \PWM_DC|d[4] , PWM_DC|d[4], top, 1
+instance = comp, \PWM_DC|d[3] , PWM_DC|d[3], top, 1
+instance = comp, \PWM_DC|LessThan0~3 , PWM_DC|LessThan0~3, top, 1
+instance = comp, \PWM_DC|d[5] , PWM_DC|d[5], top, 1
+instance = comp, \PWM_DC|d[6]~feeder , PWM_DC|d[6]~feeder, top, 1
+instance = comp, \PWM_DC|d[6] , PWM_DC|d[6], top, 1
+instance = comp, \PWM_DC|LessThan0~4 , PWM_DC|LessThan0~4, top, 1
+instance = comp, \PWM_DC|d[8] , PWM_DC|d[8], top, 1
+instance = comp, \PWM_DC|d[9] , PWM_DC|d[9], top, 1
+instance = comp, \PWM_DC|LessThan0~5 , PWM_DC|LessThan0~5, top, 1
+instance = comp, \PWM_DC|pwm_out , PWM_DC|pwm_out, top, 1
+instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, top, 1
diff --git a/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do b/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do
new file mode 100755
index 0000000..377f3cd
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_run_msim_rtl_verilog.do
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+Z:/Dropbox/_My\ Documents/E2\ Digital/adc_dac {Z:/Dropbox/_My Documents/E2 Digital/adc_dac/spi2adc.v}
+
diff --git a/part_4/ex16/simulation/modelsim/top_v.sdo b/part_4/ex16/simulation/modelsim/top_v.sdo
new file mode 100755
index 0000000..4eadda6
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/top_v.sdo
@@ -0,0 +1,8658 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP3C16F484C6 Package FBGA484
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP3C16F484C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "top")
+  (DATE "02/18/2014 18:26:57")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (718:718:718) (698:698:698))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (675:675:675) (646:646:646))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (811:811:811) (794:794:794))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (765:765:765) (762:762:762))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (768:768:768) (752:752:752))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (786:786:786) (786:786:786))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX0_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (757:757:757) (771:771:771))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (480:480:480) (494:494:494))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (465:465:465) (452:452:452))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (472:472:472) (454:454:454))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (448:448:448) (461:461:461))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (440:440:440) (455:455:455))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (939:939:939) (958:958:958))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX1_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (728:728:728) (749:749:749))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (653:653:653) (634:634:634))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (483:483:483) (466:466:466))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (582:582:582) (584:584:584))
+        (IOPATH i o (2025:2025:2025) (1901:1901:1901))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (481:481:481) (494:494:494))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (469:469:469) (450:450:450))
+        (IOPATH i o (2035:2035:2035) (1911:1911:1911))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (572:572:572) (577:577:577))
+        (IOPATH i o (2045:2045:2045) (1921:1921:1921))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX2_D\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (901:901:901) (866:866:866))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1146:1146:1146) (1175:1175:1175))
+        (IOPATH i o (1921:1921:1921) (2045:2045:2045))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1134:1134:1134) (1161:1161:1161))
+        (IOPATH i o (1921:1921:1921) (2045:2045:2045))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1362:1362:1362) (1406:1406:1406))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE HEX3_D\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1362:1362:1362) (1406:1406:1406))
+        (IOPATH i o (1901:1901:1901) (2025:2025:2025))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_SDI\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1885:1885:1885) (2030:2030:2030))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE SCK\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2059:2059:2059) (2156:2156:2156))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_CS\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1323:1323:1323) (1241:1241:1241))
+        (IOPATH i o (1881:1881:1881) (2005:2005:2005))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE DAC_LD\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1455:1455:1455) (1543:1543:1543))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE ADC_SDI\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2718:2718:2718) (2899:2899:2899))
+        (IOPATH i o (2015:2015:2015) (1891:1891:1891))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE ADC_CS\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2963:2963:2963) (2927:2927:2927))
+        (IOPATH i o (1891:1891:1891) (2015:2015:2015))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1429:1429:1429) (1488:1488:1488))
+        (IOPATH i o (2271:2271:2271) (2135:2135:2135))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1550:1550:1550) (1573:1573:1573))
+        (IOPATH i o (2271:2271:2271) (2135:2135:2135))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1626:1626:1626) (1651:1651:1651))
+        (IOPATH i o (4139:4139:4139) (3839:3839:3839))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1159:1159:1159) (1219:1219:1219))
+        (IOPATH i o (2281:2281:2281) (2145:2145:2145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1322:1322:1322) (1331:1331:1331))
+        (IOPATH i o (2291:2291:2291) (2155:2155:2155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1458:1458:1458) (1452:1452:1452))
+        (IOPATH i o (2291:2291:2291) (2155:2155:2155))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1241:1241:1241) (1248:1248:1248))
+        (IOPATH i o (2301:2301:2301) (2165:2165:2165))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[7\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1084:1084:1084) (1095:1095:1095))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[8\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1126:1126:1126) (1144:1144:1144))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE LEDG\[9\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1266:1266:1266) (1263:1263:1263))
+        (IOPATH i o (2311:2311:2311) (2175:2175:2175))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_obuf")
+    (INSTANCE PWM_OUT\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2758:2758:2758) (2894:2894:2894))
+        (IOPATH i o (2005:2005:2005) (1881:1881:1881))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[8\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[7\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[6\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[5\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[4\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[10\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3092:3092:3092) (3394:3394:3394))
+        (PORT datab (3165:3165:3165) (3444:3444:3444))
+        (PORT datac (3090:3090:3090) (3378:3378:3378))
+        (PORT datad (3177:3177:3177) (3465:3465:3465))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[3\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (696:696:696) (951:951:951))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[2\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[0\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[1\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (686:686:686) (941:941:941))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[14\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3082:3082:3082) (3380:3380:3380))
+        (PORT datab (3128:3128:3128) (3400:3400:3400))
+        (PORT datac (3072:3072:3072) (3340:3340:3340))
+        (PORT datad (3151:3151:3151) (3447:3447:3447))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[13\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3083:3083:3083) (3378:3378:3378))
+        (PORT datab (3122:3122:3122) (3392:3392:3392))
+        (PORT datac (3077:3077:3077) (3345:3345:3345))
+        (PORT datad (3155:3155:3155) (3453:3453:3453))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[9\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3090:3090:3090) (3395:3395:3395))
+        (PORT datab (3164:3164:3164) (3447:3447:3447))
+        (PORT datac (3100:3100:3100) (3376:3376:3376))
+        (PORT datad (3188:3188:3188) (3463:3463:3463))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[12\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3083:3083:3083) (3377:3377:3377))
+        (PORT datab (3123:3123:3123) (3394:3394:3394))
+        (PORT datac (3074:3074:3074) (3342:3342:3342))
+        (PORT datad (3154:3154:3154) (3451:3451:3451))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[12\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3091:3091:3091) (3396:3396:3396))
+        (PORT datab (3164:3164:3164) (3448:3448:3448))
+        (PORT datac (3099:3099:3099) (3377:3377:3377))
+        (PORT datad (3187:3187:3187) (3464:3464:3464))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[11\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3086:3086:3086) (3393:3393:3393))
+        (PORT datab (3167:3167:3167) (3452:3452:3452))
+        (PORT datac (3098:3098:3098) (3386:3386:3386))
+        (PORT datad (3187:3187:3187) (3474:3474:3474))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[11\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3082:3082:3082) (3377:3377:3377))
+        (PORT datab (3123:3123:3123) (3395:3395:3395))
+        (PORT datac (3074:3074:3074) (3342:3342:3342))
+        (PORT datad (3154:3154:3154) (3451:3451:3451))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[10\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3084:3084:3084) (3378:3378:3378))
+        (PORT datab (3123:3123:3123) (3393:3393:3393))
+        (PORT datac (3077:3077:3077) (3346:3346:3346))
+        (PORT datad (3155:3155:3155) (3453:3453:3453))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[0\]\[9\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3084:3084:3084) (3380:3380:3380))
+        (PORT datab (3128:3128:3128) (3400:3400:3400))
+        (PORT datac (3072:3072:3072) (3340:3340:3340))
+        (PORT datad (3151:3151:3151) (3447:3447:3447))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[4\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3087:3087:3087) (3393:3393:3393))
+        (PORT datab (3167:3167:3167) (3452:3452:3452))
+        (PORT datac (3100:3100:3100) (3386:3386:3386))
+        (PORT datad (3188:3188:3188) (3473:3473:3473))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[3\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (3167:3167:3167) (3446:3446:3446))
+        (PORT datac (3105:3105:3105) (3390:3390:3390))
+        (PORT datad (3194:3194:3194) (3478:3478:3478))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[2\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (3105:3105:3105) (3389:3389:3389))
+        (PORT datad (3194:3194:3194) (3478:3478:3478))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[1\]\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (681:681:681) (726:726:726))
+        (PORT datab (3175:3175:3175) (3460:3460:3460))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[2\]\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (666:666:666) (701:701:701))
+        (PORT datab (649:649:649) (692:692:692))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[3\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (704:704:704) (742:742:742))
+        (PORT datab (650:650:650) (703:703:703))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[4\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (676:676:676) (724:724:724))
+        (PORT datab (662:662:662) (694:694:694))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[5\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (679:679:679) (728:728:728))
+        (PORT datab (711:711:711) (752:752:752))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[6\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (678:678:678) (720:720:720))
+        (PORT datab (650:650:650) (694:694:694))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[7\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (671:671:671) (724:724:724))
+        (PORT datab (651:651:651) (705:705:705))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[8\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (678:678:678) (726:726:726))
+        (PORT datab (712:712:712) (752:752:752))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[9\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (606:606:606) (660:660:660))
+        (PORT datab (710:710:710) (753:753:753))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[10\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (676:676:676) (718:718:718))
+        (PORT datab (829:829:829) (858:858:858))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (377:377:377) (396:396:396))
+        (PORT datab (3019:3019:3019) (3275:3275:3275))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3030:3030:3030) (3305:3305:3305))
+        (PORT datab (538:538:538) (554:554:554))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (347:347:347) (376:376:376))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (338:338:338) (369:369:369))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3027:3027:3027) (3307:3307:3307))
+        (PORT datab (569:569:569) (589:589:589))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3027:3027:3027) (3308:3308:3308))
+        (PORT datab (338:338:338) (368:368:368))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[13\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3091:3091:3091) (3394:3394:3394))
+        (PORT datab (3165:3165:3165) (3446:3446:3446))
+        (PORT datac (3090:3090:3090) (3380:3380:3380))
+        (PORT datad (3176:3176:3176) (3467:3467:3467))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[11\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (672:672:672) (723:723:723))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[12\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (713:713:713) (752:752:752))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[13\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (625:625:625) (673:673:673))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (373:373:373) (394:394:394))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (378:378:378) (402:402:402))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3027:3027:3027) (3307:3307:3307))
+        (PORT datab (371:371:371) (393:393:393))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|romout\[1\]\[14\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3090:3090:3090) (3394:3394:3394))
+        (PORT datab (3165:3165:3165) (3451:3451:3451))
+        (PORT datac (3101:3101:3101) (3383:3383:3383))
+        (PORT datad (3190:3190:3190) (3470:3470:3470))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|adder\[0\]\|auto_generated\|result\[14\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (604:604:604) (640:640:640))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3026:3026:3026) (3304:3304:3304))
+        (PORT datab (333:333:333) (364:364:364))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCALER\|lpm_mult_component\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~20)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1314:1314:1314) (1368:1368:1368))
+        (PORT datab (1113:1113:1113) (1135:1135:1135))
+        (PORT datac (1073:1073:1073) (1096:1096:1096))
+        (PORT datad (1254:1254:1254) (1291:1291:1291))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1322:1322:1322) (1373:1373:1373))
+        (PORT datab (1108:1108:1108) (1125:1125:1125))
+        (PORT datac (1072:1072:1072) (1089:1089:1089))
+        (PORT datad (1256:1256:1256) (1288:1288:1288))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1312:1312:1312) (1364:1364:1364))
+        (PORT datab (1116:1116:1116) (1131:1131:1131))
+        (PORT datac (1076:1076:1076) (1093:1093:1093))
+        (PORT datad (1252:1252:1252) (1287:1287:1287))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (440:440:440))
+        (PORT datab (400:400:400) (423:423:423))
+        (PORT datac (1040:1040:1040) (1038:1038:1038))
+        (PORT datad (338:338:338) (359:359:359))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (413:413:413) (439:439:439))
+        (PORT datab (400:400:400) (423:423:423))
+        (PORT datac (1040:1040:1040) (1038:1038:1038))
+        (PORT datad (338:338:338) (358:358:358))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (413:413:413) (439:439:439))
+        (PORT datab (400:400:400) (427:427:427))
+        (PORT datac (1039:1039:1039) (1035:1035:1035))
+        (PORT datad (338:338:338) (354:354:354))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1108:1108:1108) (1117:1117:1117))
+        (PORT datab (230:230:230) (280:280:280))
+        (PORT datac (201:201:201) (245:245:245))
+        (PORT datad (199:199:199) (235:235:235))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1113:1113:1113) (1124:1124:1124))
+        (PORT datab (226:226:226) (273:273:273))
+        (PORT datac (197:197:197) (239:239:239))
+        (PORT datad (196:196:196) (229:229:229))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1112:1112:1112) (1122:1122:1122))
+        (PORT datab (227:227:227) (277:277:277))
+        (PORT datac (198:198:198) (243:243:243))
+        (PORT datad (197:197:197) (233:233:233))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (411:411:411) (438:438:438))
+        (PORT datab (367:367:367) (403:403:403))
+        (PORT datac (342:342:342) (372:372:372))
+        (PORT datad (1000:1000:1000) (992:992:992))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (440:440:440))
+        (PORT datab (364:364:364) (396:396:396))
+        (PORT datac (343:343:343) (369:369:369))
+        (PORT datad (1003:1003:1003) (991:991:991))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (413:413:413) (439:439:439))
+        (PORT datab (368:368:368) (400:400:400))
+        (PORT datac (343:343:343) (371:371:371))
+        (PORT datad (999:999:999) (990:990:990))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (229:229:229) (282:282:282))
+        (PORT datab (1132:1132:1132) (1139:1139:1139))
+        (PORT datac (201:201:201) (247:247:247))
+        (PORT datad (199:199:199) (235:235:235))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (284:284:284))
+        (PORT datab (1131:1131:1131) (1133:1133:1133))
+        (PORT datac (199:199:199) (242:242:242))
+        (PORT datad (197:197:197) (231:231:231))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (286:286:286))
+        (PORT datab (1130:1130:1130) (1134:1134:1134))
+        (PORT datac (198:198:198) (242:242:242))
+        (PORT datad (197:197:197) (232:232:232))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (411:411:411) (438:438:438))
+        (PORT datab (607:607:607) (624:624:624))
+        (PORT datac (1309:1309:1309) (1308:1308:1308))
+        (PORT datad (339:339:339) (358:358:358))
+        (IOPATH dataa combout (341:341:341) (319:319:319))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (441:441:441))
+        (PORT datab (611:611:611) (628:628:628))
+        (PORT datac (1309:1309:1309) (1303:1303:1303))
+        (PORT datad (340:340:340) (359:359:359))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (333:333:333) (332:332:332))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (414:414:414) (441:441:441))
+        (PORT datab (610:610:610) (624:624:624))
+        (PORT datac (1309:1309:1309) (1304:1304:1304))
+        (PORT datad (342:342:342) (356:356:356))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (319:319:319))
+        (PORT datab (1277:1277:1277) (1359:1359:1359))
+        (PORT datac (218:218:218) (269:269:269))
+        (PORT datad (216:216:216) (255:255:255))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (319:319:319))
+        (PORT datab (1282:1282:1282) (1365:1365:1365))
+        (PORT datac (225:225:225) (277:277:277))
+        (PORT datad (221:221:221) (262:262:262))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (322:322:322))
+        (PORT datab (1278:1278:1278) (1366:1366:1366))
+        (PORT datac (224:224:224) (275:275:275))
+        (PORT datad (220:220:220) (261:261:261))
+        (IOPATH dataa combout (341:341:341) (319:319:319))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (323:323:323))
+        (PORT datab (1278:1278:1278) (1359:1359:1359))
+        (PORT datac (217:217:217) (267:267:267))
+        (PORT datad (214:214:214) (254:254:254))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (319:319:319))
+        (PORT datab (1279:1279:1279) (1361:1361:1361))
+        (PORT datac (221:221:221) (274:274:274))
+        (PORT datad (218:218:218) (260:260:260))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (321:321:321))
+        (PORT datab (1277:1277:1277) (1362:1362:1362))
+        (PORT datac (221:221:221) (272:272:272))
+        (PORT datad (218:218:218) (258:258:258))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG0\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (318:318:318))
+        (PORT datab (1282:1282:1282) (1364:1364:1364))
+        (PORT datac (225:225:225) (276:276:276))
+        (PORT datad (221:221:221) (262:262:262))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1320:1320:1320) (1370:1370:1370))
+        (PORT datab (1113:1113:1113) (1133:1133:1133))
+        (PORT datac (1075:1075:1075) (1093:1093:1093))
+        (PORT datad (1258:1258:1258) (1292:1292:1292))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1318:1318:1318) (1368:1368:1368))
+        (PORT datab (1113:1113:1113) (1131:1131:1131))
+        (PORT datac (1075:1075:1075) (1095:1095:1095))
+        (PORT datad (1258:1258:1258) (1292:1292:1292))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A9\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (323:323:323) (346:346:346))
+        (PORT datad (326:326:326) (344:344:344))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A15\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1109:1109:1109) (1118:1118:1118))
+        (PORT datab (227:227:227) (276:276:276))
+        (PORT datac (198:198:198) (241:241:241))
+        (PORT datad (197:197:197) (231:231:231))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A7\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1322:1322:1322) (1373:1373:1373))
+        (PORT datab (1108:1108:1108) (1124:1124:1124))
+        (PORT datad (1256:1256:1256) (1288:1288:1288))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A12\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (438:438:438))
+        (PORT datab (401:401:401) (430:430:430))
+        (PORT datac (1037:1037:1037) (1035:1035:1035))
+        (PORT datad (334:334:334) (354:354:354))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (310:310:310))
+        (PORT datab (260:260:260) (312:312:312))
+        (PORT datac (381:381:381) (416:416:416))
+        (PORT datad (218:218:218) (261:261:261))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1023:1023:1023) (1046:1046:1046))
+        (PORT datab (1031:1031:1031) (1040:1040:1040))
+        (PORT datac (1076:1076:1076) (1093:1093:1093))
+        (PORT datad (1264:1264:1264) (1314:1314:1314))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1287:1287:1287) (1338:1338:1338))
+        (PORT datab (1107:1107:1107) (1129:1129:1129))
+        (PORT datad (176:176:176) (202:202:202))
+        (IOPATH dataa combout (325:325:325) (328:328:328))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (309:309:309))
+        (PORT datab (257:257:257) (308:308:308))
+        (PORT datac (379:379:379) (414:414:414))
+        (PORT datad (220:220:220) (256:256:256))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr2\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (382:382:382) (408:408:408))
+        (PORT datac (547:547:547) (551:551:551))
+        (PORT datad (330:330:330) (350:350:350))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A7\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1321:1321:1321) (1372:1372:1372))
+        (PORT datad (1255:1255:1255) (1292:1292:1292))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (309:309:309))
+        (PORT datab (372:372:372) (394:394:394))
+        (PORT datac (1021:1021:1021) (1006:1006:1006))
+        (PORT datad (217:217:217) (261:261:261))
+        (IOPATH dataa combout (341:341:341) (328:328:328))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (240:240:240) (306:306:306))
+        (PORT datab (258:258:258) (307:307:307))
+        (PORT datac (386:386:386) (421:421:421))
+        (PORT datad (214:214:214) (257:257:257))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr3\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (370:370:370) (403:403:403))
+        (PORT datab (337:337:337) (366:366:366))
+        (PORT datac (345:345:345) (368:368:368))
+        (PORT datad (327:327:327) (346:346:346))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1307:1307:1307) (1357:1357:1357))
+        (PORT datab (1031:1031:1031) (1041:1041:1041))
+        (PORT datac (1077:1077:1077) (1096:1096:1096))
+        (PORT datad (1250:1250:1250) (1288:1288:1288))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (300:300:300) (310:310:310))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (309:309:309))
+        (PORT datab (258:258:258) (310:310:310))
+        (PORT datac (385:385:385) (419:419:419))
+        (PORT datad (218:218:218) (260:260:260))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (371:371:371) (406:406:406))
+        (PORT datab (1324:1324:1324) (1320:1320:1320))
+        (PORT datac (583:583:583) (603:603:603))
+        (PORT datad (327:327:327) (344:344:344))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A18\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (410:410:410) (435:435:435))
+        (PORT datab (370:370:370) (401:401:401))
+        (PORT datac (342:342:342) (370:370:370))
+        (PORT datad (1000:1000:1000) (988:988:988))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (284:284:284))
+        (PORT datab (226:226:226) (274:274:274))
+        (PORT datac (196:196:196) (240:240:240))
+        (PORT datad (197:197:197) (231:231:231))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (228:228:228) (283:283:283))
+        (PORT datab (230:230:230) (278:278:278))
+        (PORT datac (201:201:201) (245:245:245))
+        (PORT datad (196:196:196) (229:229:229))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A21\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (227:227:227) (283:283:283))
+        (PORT datab (1131:1131:1131) (1133:1133:1133))
+        (PORT datac (198:198:198) (242:242:242))
+        (PORT datad (196:196:196) (231:231:231))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (289:289:289))
+        (PORT datab (227:227:227) (274:274:274))
+        (PORT datac (197:197:197) (239:239:239))
+        (PORT datad (199:199:199) (235:235:235))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (662:662:662))
+        (PORT datab (380:380:380) (418:418:418))
+        (PORT datac (558:558:558) (565:565:565))
+        (PORT datad (568:568:568) (587:587:587))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (647:647:647) (660:660:660))
+        (PORT datab (377:377:377) (415:415:415))
+        (PORT datac (561:561:561) (569:569:569))
+        (PORT datad (572:572:572) (586:586:586))
+        (IOPATH dataa combout (350:350:350) (367:367:367))
+        (IOPATH datab combout (350:350:350) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (664:664:664))
+        (PORT datab (380:380:380) (418:418:418))
+        (PORT datac (560:560:560) (568:568:568))
+        (PORT datad (569:569:569) (589:589:589))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A25\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (434:434:434))
+        (PORT datab (606:606:606) (622:622:622))
+        (PORT datac (1312:1312:1312) (1306:1306:1306))
+        (PORT datad (340:340:340) (355:355:355))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (318:318:318))
+        (PORT datab (249:249:249) (307:307:307))
+        (PORT datac (365:365:365) (404:404:404))
+        (PORT datad (553:553:553) (567:567:567))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (322:322:322))
+        (PORT datab (252:252:252) (311:311:311))
+        (PORT datac (367:367:367) (407:407:407))
+        (PORT datad (553:553:553) (570:570:570))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr4\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (319:319:319))
+        (PORT datab (256:256:256) (315:315:315))
+        (PORT datac (372:372:372) (411:411:411))
+        (PORT datad (549:549:549) (565:565:565))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (319:319:319))
+        (PORT datab (253:253:253) (312:312:312))
+        (PORT datac (372:372:372) (408:408:408))
+        (PORT datad (549:549:549) (565:565:565))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (319:319:319))
+        (PORT datab (253:253:253) (311:311:311))
+        (PORT datac (371:371:371) (407:407:407))
+        (PORT datad (550:550:550) (566:566:566))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (320:320:320))
+        (PORT datab (257:257:257) (316:316:316))
+        (PORT datac (373:373:373) (411:411:411))
+        (PORT datad (548:548:548) (564:564:564))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG1\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (323:323:323))
+        (PORT datab (255:255:255) (314:314:314))
+        (PORT datac (368:368:368) (411:411:411))
+        (PORT datad (551:551:551) (569:569:569))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A24\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (645:645:645) (664:664:664))
+        (PORT datab (380:380:380) (418:418:418))
+        (PORT datac (560:560:560) (568:568:568))
+        (PORT datad (570:570:570) (590:590:590))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A14\|WideOr0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (356:356:356) (385:385:385))
+        (PORT datab (588:588:588) (613:613:613))
+        (PORT datac (385:385:385) (419:419:419))
+        (PORT datad (217:217:217) (256:256:256))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|Decoder0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (241:241:241) (303:303:303))
+        (PORT datab (255:255:255) (306:306:306))
+        (PORT datac (385:385:385) (419:419:419))
+        (PORT datad (216:216:216) (256:256:256))
+        (IOPATH dataa combout (341:341:341) (319:319:319))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (355:355:355) (389:389:389))
+        (PORT datab (381:381:381) (407:407:407))
+        (PORT datac (345:345:345) (367:367:367))
+        (PORT datad (328:328:328) (350:350:350))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A17\|WideOr0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1000:1000:1000) (1009:1009:1009))
+        (PORT datad (1105:1105:1105) (1100:1100:1100))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A20\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (230:230:230) (288:288:288))
+        (PORT datab (228:228:228) (278:278:278))
+        (PORT datac (198:198:198) (243:243:243))
+        (PORT datad (199:199:199) (234:234:234))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (893:893:893) (946:946:946))
+        (PORT datab (1090:1090:1090) (1116:1116:1116))
+        (PORT datac (225:225:225) (281:281:281))
+        (PORT datad (1106:1106:1106) (1113:1113:1113))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (894:894:894) (942:942:942))
+        (PORT datab (1086:1086:1086) (1111:1111:1111))
+        (PORT datac (231:231:231) (285:285:285))
+        (PORT datad (1107:1107:1107) (1114:1114:1114))
+        (IOPATH dataa combout (327:327:327) (347:347:347))
+        (IOPATH datab combout (333:333:333) (342:342:342))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (212:212:212) (260:260:260))
+        (PORT datad (195:195:195) (230:230:230))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (889:889:889) (940:940:940))
+        (PORT datab (1084:1084:1084) (1110:1110:1110))
+        (PORT datac (230:230:230) (286:286:286))
+        (PORT datad (1108:1108:1108) (1114:1114:1114))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1149:1149:1149) (1152:1152:1152))
+        (PORT datab (1087:1087:1087) (1110:1110:1110))
+        (PORT datac (1000:1000:1000) (1011:1011:1011))
+        (PORT datad (1108:1108:1108) (1113:1113:1113))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (304:304:304) (308:308:308))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (212:212:212) (256:256:256))
+        (PORT datac (858:858:858) (900:900:900))
+        (PORT datad (176:176:176) (202:202:202))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (897:897:897) (942:942:942))
+        (PORT datab (1091:1091:1091) (1113:1113:1113))
+        (PORT datac (225:225:225) (277:277:277))
+        (PORT datad (1104:1104:1104) (1107:1107:1107))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (894:894:894) (943:943:943))
+        (PORT datab (1087:1087:1087) (1115:1115:1115))
+        (PORT datac (228:228:228) (285:285:285))
+        (PORT datad (1109:1109:1109) (1116:1116:1116))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (311:311:311))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (890:890:890) (937:937:937))
+        (PORT datab (1083:1083:1083) (1108:1108:1108))
+        (PORT datac (231:231:231) (284:284:284))
+        (PORT datad (1109:1109:1109) (1112:1112:1112))
+        (IOPATH dataa combout (341:341:341) (319:319:319))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (210:210:210) (258:258:258))
+        (PORT datab (232:232:232) (274:274:274))
+        (PORT datac (175:175:175) (209:209:209))
+        (PORT datad (196:196:196) (231:231:231))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (893:893:893) (938:938:938))
+        (PORT datab (1081:1081:1081) (1109:1109:1109))
+        (PORT datac (232:232:232) (286:286:286))
+        (PORT datad (1111:1111:1111) (1113:1113:1113))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (213:213:213) (256:256:256))
+        (PORT datac (185:185:185) (224:224:224))
+        (PORT datad (319:319:319) (341:341:341))
+        (IOPATH datab combout (304:304:304) (311:311:311))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (224:224:224) (268:268:268))
+        (PORT datab (234:234:234) (277:277:277))
+        (PORT datac (185:185:185) (224:224:224))
+        (PORT datad (199:199:199) (235:235:235))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|Decoder0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (890:890:890) (938:938:938))
+        (PORT datab (1082:1082:1082) (1109:1109:1109))
+        (PORT datac (232:232:232) (285:285:285))
+        (PORT datad (1110:1110:1110) (1113:1113:1113))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (342:342:342) (318:318:318))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SEG2\|WideOr0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (202:202:202) (242:242:242))
+        (PORT datac (366:366:366) (393:393:393))
+        (PORT datad (197:197:197) (232:232:232))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A23\|WideOr0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1027:1027:1027) (1048:1048:1048))
+        (PORT datab (1321:1321:1321) (1304:1304:1304))
+        (PORT datac (1072:1072:1072) (1089:1089:1089))
+        (PORT datad (1077:1077:1077) (1087:1087:1087))
+        (IOPATH dataa combout (301:301:301) (299:299:299))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE BCD_CONVERT\|A23\|WideOr0\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1316:1316:1316) (1367:1367:1367))
+        (PORT datab (1030:1030:1030) (1042:1042:1042))
+        (PORT datac (175:175:175) (209:209:209))
+        (PORT datad (1256:1256:1256) (1290:1290:1290))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE CLOCK_50\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (736:736:736) (991:991:991))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|clk_1MHz\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE CLOCK_50\~inputclkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (163:163:163) (145:145:145))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (342:342:342))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (344:344:344))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (246:246:246) (317:317:317))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (201:201:201) (239:239:239))
+        (PORT datac (403:403:403) (467:467:467))
+        (PORT datad (195:195:195) (230:230:230))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (252:252:252) (338:338:338))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (200:200:200) (239:239:239))
+        (PORT datac (403:403:403) (467:467:467))
+        (PORT datad (194:194:194) (230:230:230))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (252:252:252) (337:337:337))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|ctr\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (199:199:199) (238:238:238))
+        (PORT datac (398:398:398) (464:464:464))
+        (PORT datad (200:200:200) (237:237:237))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (255:255:255) (347:347:347))
+        (PORT datab (254:254:254) (340:340:340))
+        (PORT datac (223:223:223) (302:302:302))
+        (PORT datad (225:225:225) (297:297:297))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (226:226:226) (274:274:274))
+        (PORT datad (246:246:246) (317:317:317))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|clk_1MHz)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2135:2135:2135) (2061:2061:2061))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (795:795:795) (793:793:793))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_DAC\|clk_1MHz\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (849:849:849) (897:897:897))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[0\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (261:261:261) (343:343:343))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (346:346:346))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (268:268:268) (320:320:320))
+        (PORT datab (676:676:676) (700:700:700))
+        (PORT datac (173:173:173) (207:207:207))
+        (PORT datad (920:920:920) (975:975:975))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (443:443:443) (508:508:508))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (710:710:710) (755:755:755))
+        (PORT datab (468:468:468) (511:511:511))
+        (PORT datac (310:310:310) (327:327:327))
+        (PORT datad (951:951:951) (1007:1007:1007))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (410:410:410) (487:487:487))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (333:333:333) (365:365:365))
+        (PORT datab (471:471:471) (511:511:511))
+        (PORT datac (677:677:677) (713:713:713))
+        (PORT datad (954:954:954) (1006:1006:1006))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (488:488:488))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (396:396:396))
+        (PORT datab (461:461:461) (503:503:503))
+        (PORT datac (668:668:668) (709:709:709))
+        (PORT datad (952:952:952) (1011:1011:1011))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (487:487:487))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (373:373:373) (393:393:393))
+        (PORT datab (469:469:469) (512:512:512))
+        (PORT datac (675:675:675) (713:713:713))
+        (PORT datad (952:952:952) (1006:1006:1006))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (427:427:427) (497:497:497))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (341:341:341) (370:370:370))
+        (PORT datab (463:463:463) (503:503:503))
+        (PORT datac (670:670:670) (709:709:709))
+        (PORT datad (952:952:952) (1011:1011:1011))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~36)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (440:440:440) (509:509:509))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (711:711:711) (756:756:756))
+        (PORT datab (470:470:470) (512:512:512))
+        (PORT datac (314:314:314) (333:333:333))
+        (PORT datad (953:953:953) (1005:1005:1005))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~38)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (253:253:253) (344:344:344))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (950:950:950) (1019:1019:1019))
+        (PORT datab (199:199:199) (237:237:237))
+        (PORT datac (235:235:235) (277:277:277))
+        (PORT datad (639:639:639) (661:661:661))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~40)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (226:226:226) (299:299:299))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (951:951:951) (1019:1019:1019))
+        (PORT datab (198:198:198) (237:237:237))
+        (PORT datac (235:235:235) (278:278:278))
+        (PORT datad (638:638:638) (661:661:661))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (513:513:513))
+        (PORT datab (250:250:250) (334:334:334))
+        (PORT datac (223:223:223) (303:303:303))
+        (PORT datad (392:392:392) (456:456:456))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (729:729:729) (799:799:799))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (345:345:345))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (868:868:868) (918:918:918))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (709:709:709) (756:756:756))
+        (PORT datab (468:468:468) (510:510:510))
+        (PORT datac (617:617:617) (632:632:632))
+        (PORT datad (947:947:947) (1010:1010:1010))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (251:251:251) (336:336:336))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (231:231:231) (276:276:276))
+        (PORT datab (688:688:688) (701:701:701))
+        (PORT datac (697:697:697) (764:764:764))
+        (PORT datad (175:175:175) (201:201:201))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (686:686:686) (754:754:754))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (708:708:708) (757:757:757))
+        (PORT datab (467:467:467) (509:509:509))
+        (PORT datac (594:594:594) (603:603:603))
+        (PORT datad (948:948:948) (1009:1009:1009))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (649:649:649) (721:721:721))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (707:707:707) (755:755:755))
+        (PORT datab (466:466:466) (507:507:507))
+        (PORT datac (603:603:603) (611:611:611))
+        (PORT datad (949:949:949) (1011:1011:1011))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (249:249:249) (334:334:334))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (251:251:251) (339:339:339))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (248:248:248) (332:332:332))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (343:343:343))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (246:246:246))
+        (PORT datab (687:687:687) (700:700:700))
+        (PORT datac (697:697:697) (760:760:760))
+        (PORT datad (203:203:203) (232:232:232))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1476:1476:1476) (1493:1493:1493))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Add0\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (354:354:354))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|ctr\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (949:949:949) (1018:1018:1018))
+        (PORT datab (201:201:201) (241:241:241))
+        (PORT datac (238:238:238) (282:282:282))
+        (PORT datad (639:639:639) (661:661:661))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|ctr\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (683:683:683) (751:751:751))
+        (PORT datab (726:726:726) (777:777:777))
+        (PORT datac (692:692:692) (743:743:743))
+        (PORT datad (224:224:224) (297:297:297))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (409:409:409) (477:477:477))
+        (PORT datab (866:866:866) (915:915:915))
+        (PORT datac (659:659:659) (719:719:719))
+        (PORT datad (223:223:223) (295:295:295))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (646:646:646) (720:720:720))
+        (PORT datab (251:251:251) (336:336:336))
+        (PORT datac (223:223:223) (305:305:305))
+        (PORT datad (225:225:225) (298:298:298))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (352:352:352))
+        (PORT datab (264:264:264) (347:347:347))
+        (PORT datac (236:236:236) (313:313:313))
+        (PORT datad (238:238:238) (307:307:307))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|Equal0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (338:338:338) (375:375:375))
+        (PORT datab (199:199:199) (239:239:239))
+        (PORT datac (172:172:172) (206:206:206))
+        (PORT datad (601:601:601) (612:612:612))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE GEN_10K\|clkout\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (704:704:704) (748:748:748))
+        (PORT datab (454:454:454) (494:494:494))
+        (PORT datad (950:950:950) (1008:1008:1008))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE GEN_10K\|clkout)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PULSE\|state\.IDLE\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (224:224:224) (297:297:297))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PULSE\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PULSE\|pulse\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (219:219:219) (296:296:296))
+        (PORT datad (228:228:228) (301:301:301))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PULSE\|pulse)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (985:985:985) (1137:1137:1137))
+        (PORT datad (240:240:240) (317:317:317))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.WAIT_CSB_HIGH)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1485:1485:1485) (1501:1501:1501))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (984:984:984) (1136:1136:1136))
+        (PORT datab (712:712:712) (779:779:779))
+        (PORT datad (216:216:216) (285:285:285))
+        (IOPATH dataa combout (304:304:304) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1485:1485:1485) (1501:1501:1501))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (983:983:983) (1139:1139:1139))
+        (PORT datab (707:707:707) (775:775:775))
+        (PORT datad (243:243:243) (322:322:322))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|sr_state\.WAIT_CSB_FALL)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1485:1485:1485) (1501:1501:1501))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|dac_start\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (983:983:983) (1131:1131:1131))
+        (PORT datab (264:264:264) (355:355:355))
+        (PORT datac (576:576:576) (622:622:622))
+        (PORT datad (302:302:302) (397:397:397))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (310:310:310))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|dac_start\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (709:709:709) (777:777:777))
+        (PORT datac (174:174:174) (208:208:208))
+        (PORT datad (243:243:243) (322:322:322))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_start)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1485:1485:1485) (1501:1501:1501))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[0\]\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (248:248:248) (333:333:333))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[3\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (252:252:252) (343:343:343))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[4\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (269:269:269) (360:360:360))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector8\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (716:716:716) (808:808:808))
+        (PORT datab (217:217:217) (261:261:261))
+        (PORT datac (240:240:240) (327:327:327))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[1\]\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (250:250:250) (335:335:335))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|state\[2\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (250:250:250) (335:335:335))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|state\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT sclr (668:668:668) (725:725:725))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD sclr (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (254:254:254) (345:345:345))
+        (PORT datab (252:252:252) (338:338:338))
+        (PORT datac (224:224:224) (305:305:305))
+        (PORT datad (226:226:226) (298:298:298))
+        (IOPATH dataa combout (350:350:350) (366:366:366))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Selector9\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (717:717:717) (812:812:812))
+        (PORT datab (218:218:218) (263:263:263))
+        (PORT datac (242:242:242) (329:329:329))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_cs)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|clk_1MHz\~0)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|clk_1MHz)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (2135:2135:2135) (2061:2061:2061))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (795:795:795) (793:793:793))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_ADC\|clk_1MHz\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (858:858:858) (929:929:929))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE ADC_SDO\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (649:649:649) (908:908:908))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (267:267:267) (354:354:354))
+        (PORT datac (876:876:876) (933:933:933))
+        (IOPATH dataa combout (341:341:341) (347:347:347))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.WAIT_CSB_HIGH)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (622:622:622) (680:680:680))
+        (PORT datab (904:904:904) (968:968:968))
+        (PORT datad (261:261:261) (332:332:332))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (331:331:331) (342:342:342))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1475:1475:1475) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (742:742:742) (807:807:807))
+        (PORT datab (655:655:655) (726:726:726))
+        (PORT datad (855:855:855) (966:966:966))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|sr_state\.WAIT_CSB_FALL)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|adc_start\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (247:247:247) (335:335:335))
+        (PORT datab (878:878:878) (998:998:998))
+        (PORT datac (627:627:627) (695:695:695))
+        (PORT datad (240:240:240) (309:309:309))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (310:310:310))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|adc_start\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (203:203:203) (248:248:248))
+        (PORT datab (881:881:881) (1004:1004:1004))
+        (PORT datac (704:704:704) (767:767:767))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_start)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1482:1482:1482) (1497:1497:1497))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (275:275:275) (369:369:369))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (279:279:279) (375:375:375))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (258:258:258) (340:340:340))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|state\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (239:239:239) (283:283:283))
+        (PORT datac (272:272:272) (374:374:374))
+        (PORT datad (177:177:177) (203:203:203))
+        (IOPATH datab combout (336:336:336) (325:325:325))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector4\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (500:500:500) (581:581:581))
+        (PORT datad (253:253:253) (335:335:335))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (276:276:276) (374:374:374))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector5\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (202:202:202) (246:246:246))
+        (PORT datab (239:239:239) (284:284:284))
+        (PORT datac (272:272:272) (374:374:374))
+        (PORT datad (176:176:176) (202:202:202))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Add1\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (301:301:301) (409:409:409))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|state\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|state\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (279:279:279) (374:374:374))
+        (PORT datac (250:250:250) (340:340:340))
+        (PORT datad (247:247:247) (327:327:327))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector4\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (501:501:501) (578:578:578))
+        (PORT datab (238:238:238) (283:283:283))
+        (PORT datac (273:273:273) (375:375:375))
+        (PORT datad (251:251:251) (333:333:333))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (350:350:350) (368:368:368))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_cs)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (973:973:973) (1063:1063:1063))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|WideOr0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (303:303:303) (414:414:414))
+        (PORT datab (278:278:278) (372:372:372))
+        (PORT datac (248:248:248) (339:339:339))
+        (PORT datad (247:247:247) (328:328:328))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|WideOr0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (442:442:442) (476:476:476))
+        (PORT datab (201:201:201) (241:241:241))
+        (PORT datac (271:271:271) (373:373:373))
+        (PORT datad (254:254:254) (336:336:336))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_ena)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|always3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (628:628:628) (695:695:695))
+        (PORT datad (628:628:628) (698:698:698))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (3961:3961:3961) (4319:4319:4319))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[1\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (225:225:225) (296:296:296))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (567:567:567) (645:645:645))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[3\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (225:225:225) (296:296:296))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (567:567:567) (643:643:643))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (239:239:239) (308:308:308))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[6\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (226:226:226) (297:297:297))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (582:582:582) (656:656:656))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Decoder0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (300:300:300) (410:410:410))
+        (PORT datab (279:279:279) (374:374:374))
+        (PORT datac (248:248:248) (340:340:340))
+        (PORT datad (248:248:248) (329:329:329))
+        (IOPATH dataa combout (300:300:300) (307:307:307))
+        (IOPATH datab combout (300:300:300) (308:308:308))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Decoder0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (200:200:200) (240:240:240))
+        (PORT datad (251:251:251) (333:333:333))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_done)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT asdata (755:755:755) (817:817:817))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|PULSE2\|state\.IDLE\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (1581:1581:1581) (1626:1626:1626))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|PULSE2\|state\.IDLE)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|PULSE2\|pulse\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1607:1607:1607) (1663:1663:1663))
+        (PORT datad (217:217:217) (286:286:286))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|PULSE2\|pulse)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|rden_b_store)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT asdata (1210:1210:1210) (1273:1273:1273))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (894:894:894) (964:964:964))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT asdata (581:581:581) (656:656:656))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT asdata (754:754:754) (816:816:816))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|shift_reg\[9\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (239:239:239) (309:309:309))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|shift_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1477:1477:1477) (1479:1479:1479))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (820:820:820) (826:826:826))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT asdata (706:706:706) (769:769:769))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_clkctrl")
+    (INSTANCE SPI_ADC\|adc_cs\~clkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (1108:1108:1108) (1172:1172:1172))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[0\]\~36)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[1\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (264:264:264) (351:351:351))
+        (PORT datab (262:262:262) (344:344:344))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[2\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (345:345:345))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[3\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (353:353:353))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[4\]\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (353:353:353))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[4\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3107:3107:3107) (3383:3383:3383))
+        (PORT datab (1375:1375:1375) (1472:1472:1472))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[5\]\~20)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[5\]\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1423:1423:1423) (1534:1534:1534))
+        (PORT datab (3192:3192:3192) (3495:3495:3495))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[6\]\~22)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[6\]\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1468:1468:1468) (1548:1548:1548))
+        (PORT datab (3124:3124:3124) (3396:3396:3396))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[7\]\~24)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[7\]\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1428:1428:1428) (1550:1550:1550))
+        (PORT datab (3099:3099:3099) (3370:3370:3370))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[8\]\~26)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[8\]\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3183:3183:3183) (3497:3497:3497))
+        (PORT datab (1428:1428:1428) (1494:1494:1494))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[9\]\~28)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (352:352:352))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[9\]\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1364:1364:1364) (1442:1442:1442))
+        (PORT datab (3373:3373:3373) (3642:3642:3642))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[10\]\~30)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (283:283:283) (366:366:366))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[10\]\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1205:1205:1205) (1291:1291:1291))
+        (PORT datab (3405:3405:3405) (3686:3686:3686))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[11\]\~32)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (351:351:351))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[11\]\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3115:3115:3115) (3398:3398:3398))
+        (PORT datab (1452:1452:1452) (1542:1542:1542))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|ctr\[12\]\~34)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (238:238:238) (306:306:306))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|ctr\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1472:1472:1472) (1487:1487:1487))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|wraddr\[12\]\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (3101:3101:3101) (3380:3380:3380))
+        (PORT datad (1368:1368:1368) (1458:1458:1458))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (676:676:676) (689:689:689))
+        (PORT clk (1808:1808:1808) (1838:1838:1838))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1048:1048:1048) (1107:1107:1107))
+        (PORT d[1] (1016:1016:1016) (1089:1089:1089))
+        (PORT d[2] (1037:1037:1037) (1105:1105:1105))
+        (PORT d[3] (1572:1572:1572) (1657:1657:1657))
+        (PORT d[4] (1433:1433:1433) (1467:1467:1467))
+        (PORT d[5] (1422:1422:1422) (1450:1450:1450))
+        (PORT d[6] (1970:1970:1970) (1970:1970:1970))
+        (PORT d[7] (1446:1446:1446) (1480:1480:1480))
+        (PORT d[8] (1646:1646:1646) (1671:1671:1671))
+        (PORT d[9] (1417:1417:1417) (1420:1420:1420))
+        (PORT d[10] (1579:1579:1579) (1667:1667:1667))
+        (PORT d[11] (1649:1649:1649) (1676:1676:1676))
+        (PORT d[12] (1454:1454:1454) (1488:1488:1488))
+        (PORT clk (1805:1805:1805) (1834:1834:1834))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1241:1241:1241) (1230:1230:1230))
+        (PORT clk (1805:1805:1805) (1834:1834:1834))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1808:1808:1808) (1838:1838:1838))
+        (PORT d[0] (1766:1766:1766) (1767:1767:1767))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1809:1809:1809) (1839:1839:1839))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1809:1809:1809) (1839:1839:1839))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1809:1809:1809) (1839:1839:1839))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1809:1809:1809) (1839:1839:1839))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1005:1005:1005) (1058:1058:1058))
+        (PORT d[1] (1017:1017:1017) (1090:1090:1090))
+        (PORT d[2] (1060:1060:1060) (1124:1124:1124))
+        (PORT d[3] (1573:1573:1573) (1657:1657:1657))
+        (PORT d[4] (982:982:982) (1031:1031:1031))
+        (PORT d[5] (1284:1284:1284) (1388:1388:1388))
+        (PORT d[6] (998:998:998) (1062:1062:1062))
+        (PORT d[7] (1320:1320:1320) (1409:1409:1409))
+        (PORT d[8] (1050:1050:1050) (1112:1112:1112))
+        (PORT d[9] (1036:1036:1036) (1102:1102:1102))
+        (PORT d[10] (1411:1411:1411) (1474:1474:1474))
+        (PORT d[11] (1294:1294:1294) (1360:1360:1360))
+        (PORT d[12] (1005:1005:1005) (1063:1063:1063))
+        (PORT clk (1769:1769:1769) (1765:1765:1765))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1242:1242:1242) (1231:1231:1231))
+        (PORT clk (1769:1769:1769) (1765:1765:1765))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1769:1769:1769) (1765:1765:1765))
+        (PORT d[0] (2132:2132:2132) (2060:2060:2060))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1770:1770:1770) (1766:1766:1766))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1770:1770:1770) (1766:1766:1766))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1770:1770:1770) (1766:1766:1766))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1765:1765:1765) (1765:1765:1765))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT asdata (753:753:753) (813:813:813))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[5\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (225:225:225) (296:296:296))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (875:875:875) (900:900:900))
+        (PORT datab (243:243:243) (325:325:325))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1335:1335:1335) (1375:1375:1375))
+        (PORT clk (1802:1802:1802) (1832:1832:1832))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1966:1966:1966) (2061:2061:2061))
+        (PORT d[1] (2091:2091:2091) (2197:2197:2197))
+        (PORT d[2] (1184:1184:1184) (1276:1276:1276))
+        (PORT d[3] (2407:2407:2407) (2505:2505:2505))
+        (PORT d[4] (980:980:980) (1034:1034:1034))
+        (PORT d[5] (734:734:734) (784:784:784))
+        (PORT d[6] (1121:1121:1121) (1116:1116:1116))
+        (PORT d[7] (695:695:695) (736:736:736))
+        (PORT d[8] (1472:1472:1472) (1534:1534:1534))
+        (PORT d[9] (716:716:716) (752:752:752))
+        (PORT d[10] (1670:1670:1670) (1726:1726:1726))
+        (PORT d[11] (969:969:969) (1022:1022:1022))
+        (PORT d[12] (726:726:726) (777:777:777))
+        (PORT clk (1799:1799:1799) (1828:1828:1828))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1273:1273:1273) (1250:1250:1250))
+        (PORT clk (1799:1799:1799) (1828:1828:1828))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1802:1802:1802) (1832:1832:1832))
+        (PORT d[0] (1798:1798:1798) (1787:1787:1787))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1945:1945:1945) (2036:2036:2036))
+        (PORT d[1] (2092:2092:2092) (2191:2191:2191))
+        (PORT d[2] (1207:1207:1207) (1301:1301:1301))
+        (PORT d[3] (2408:2408:2408) (2505:2505:2505))
+        (PORT d[4] (1209:1209:1209) (1282:1282:1282))
+        (PORT d[5] (1778:1778:1778) (1894:1894:1894))
+        (PORT d[6] (2043:2043:2043) (2144:2144:2144))
+        (PORT d[7] (2249:2249:2249) (2337:2337:2337))
+        (PORT d[8] (1994:1994:1994) (2049:2049:2049))
+        (PORT d[9] (1211:1211:1211) (1275:1275:1275))
+        (PORT d[10] (1751:1751:1751) (1845:1845:1845))
+        (PORT d[11] (1734:1734:1734) (1820:1820:1820))
+        (PORT d[12] (1738:1738:1738) (1842:1842:1842))
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1274:1274:1274) (1251:1251:1251))
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+        (PORT d[0] (1471:1471:1471) (1437:1437:1437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1759:1759:1759) (1759:1759:1759))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[4\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (389:389:389) (453:453:453))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1513:1513:1513) (1586:1586:1586))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (597:597:597) (667:667:667))
+        (PORT datab (1119:1119:1119) (1124:1124:1124))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (934:934:934) (938:938:938))
+        (PORT clk (1812:1812:1812) (1841:1841:1841))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1007:1007:1007) (1060:1060:1060))
+        (PORT d[1] (1036:1036:1036) (1120:1120:1120))
+        (PORT d[2] (1009:1009:1009) (1061:1061:1061))
+        (PORT d[3] (1048:1048:1048) (1107:1107:1107))
+        (PORT d[4] (1423:1423:1423) (1440:1440:1440))
+        (PORT d[5] (1413:1413:1413) (1428:1428:1428))
+        (PORT d[6] (2545:2545:2545) (2565:2565:2565))
+        (PORT d[7] (1437:1437:1437) (1452:1452:1452))
+        (PORT d[8] (1615:1615:1615) (1620:1620:1620))
+        (PORT d[9] (1406:1406:1406) (1417:1417:1417))
+        (PORT d[10] (1786:1786:1786) (1898:1898:1898))
+        (PORT d[11] (1671:1671:1671) (1678:1678:1678))
+        (PORT d[12] (1947:1947:1947) (1965:1965:1965))
+        (PORT clk (1809:1809:1809) (1837:1837:1837))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1480:1480:1480) (1445:1445:1445))
+        (PORT clk (1809:1809:1809) (1837:1837:1837))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1812:1812:1812) (1841:1841:1841))
+        (PORT d[0] (2005:2005:2005) (1982:1982:1982))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1017:1017:1017) (1052:1052:1052))
+        (PORT d[1] (1037:1037:1037) (1120:1120:1120))
+        (PORT d[2] (1032:1032:1032) (1085:1085:1085))
+        (PORT d[3] (1049:1049:1049) (1107:1107:1107))
+        (PORT d[4] (1035:1035:1035) (1083:1083:1083))
+        (PORT d[5] (1303:1303:1303) (1406:1406:1406))
+        (PORT d[6] (1257:1257:1257) (1314:1314:1314))
+        (PORT d[7] (1028:1028:1028) (1121:1121:1121))
+        (PORT d[8] (1059:1059:1059) (1140:1140:1140))
+        (PORT d[9] (1300:1300:1300) (1398:1398:1398))
+        (PORT d[10] (1064:1064:1064) (1144:1144:1144))
+        (PORT d[11] (1014:1014:1014) (1082:1082:1082))
+        (PORT d[12] (1040:1040:1040) (1101:1101:1101))
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1481:1481:1481) (1446:1446:1446))
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+        (PORT d[0] (2170:2170:2170) (2105:2105:2105))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1769:1769:1769) (1768:1768:1768))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (463:463:463) (536:536:536))
+        (PORT datab (929:929:929) (946:946:946))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (937:937:937) (960:960:960))
+        (PORT clk (1798:1798:1798) (1829:1829:1829))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1195:1195:1195) (1251:1251:1251))
+        (PORT d[1] (2056:2056:2056) (2168:2168:2168))
+        (PORT d[2] (1529:1529:1529) (1613:1613:1613))
+        (PORT d[3] (2057:2057:2057) (2146:2146:2146))
+        (PORT d[4] (984:984:984) (1013:1013:1013))
+        (PORT d[5] (1332:1332:1332) (1395:1395:1395))
+        (PORT d[6] (1154:1154:1154) (1178:1178:1178))
+        (PORT d[7] (717:717:717) (745:745:745))
+        (PORT d[8] (1667:1667:1667) (1717:1717:1717))
+        (PORT d[9] (721:721:721) (746:746:746))
+        (PORT d[10] (1449:1449:1449) (1511:1511:1511))
+        (PORT d[11] (740:740:740) (763:763:763))
+        (PORT d[12] (700:700:700) (727:727:727))
+        (PORT clk (1795:1795:1795) (1825:1825:1825))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1698:1698:1698) (1698:1698:1698))
+        (PORT clk (1795:1795:1795) (1825:1825:1825))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1798:1798:1798) (1829:1829:1829))
+        (PORT d[0] (2223:2223:2223) (2235:2235:2235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1799:1799:1799) (1830:1830:1830))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1799:1799:1799) (1830:1830:1830))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1799:1799:1799) (1830:1830:1830))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1799:1799:1799) (1830:1830:1830))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1188:1188:1188) (1259:1259:1259))
+        (PORT d[1] (2079:2079:2079) (2192:2192:2192))
+        (PORT d[2] (1508:1508:1508) (1590:1590:1590))
+        (PORT d[3] (2058:2058:2058) (2146:2146:2146))
+        (PORT d[4] (1452:1452:1452) (1524:1524:1524))
+        (PORT d[5] (1746:1746:1746) (1880:1880:1880))
+        (PORT d[6] (2018:2018:2018) (2114:2114:2114))
+        (PORT d[7] (1983:1983:1983) (2077:2077:2077))
+        (PORT d[8] (1685:1685:1685) (1744:1744:1744))
+        (PORT d[9] (1388:1388:1388) (1451:1451:1451))
+        (PORT d[10] (2046:2046:2046) (2172:2172:2172))
+        (PORT d[11] (1993:1993:1993) (2071:2071:2071))
+        (PORT d[12] (1713:1713:1713) (1797:1797:1797))
+        (PORT clk (1759:1759:1759) (1756:1756:1756))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1699:1699:1699) (1699:1699:1699))
+        (PORT clk (1759:1759:1759) (1756:1756:1756))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1759:1759:1759) (1756:1756:1756))
+        (PORT d[0] (1741:1741:1741) (1708:1708:1708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1760:1760:1760) (1757:1757:1757))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1760:1760:1760) (1757:1757:1757))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1760:1760:1760) (1757:1757:1757))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1755:1755:1755) (1756:1756:1756))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT asdata (569:569:569) (646:646:646))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[2\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (225:225:225) (297:297:297))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (833:833:833) (852:852:852))
+        (PORT datab (608:608:608) (667:667:667))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1345:1345:1345) (1383:1383:1383))
+        (PORT clk (1802:1802:1802) (1832:1832:1832))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1504:1504:1504) (1561:1561:1561))
+        (PORT d[1] (2097:2097:2097) (2206:2206:2206))
+        (PORT d[2] (1532:1532:1532) (1622:1622:1622))
+        (PORT d[3] (2008:2008:2008) (2096:2096:2096))
+        (PORT d[4] (975:975:975) (1010:1010:1010))
+        (PORT d[5] (697:697:697) (726:726:726))
+        (PORT d[6] (1120:1120:1120) (1120:1120:1120))
+        (PORT d[7] (685:685:685) (707:707:707))
+        (PORT d[8] (1396:1396:1396) (1453:1453:1453))
+        (PORT d[9] (681:681:681) (708:708:708))
+        (PORT d[10] (1441:1441:1441) (1506:1506:1506))
+        (PORT d[11] (729:729:729) (760:760:760))
+        (PORT d[12] (963:963:963) (979:979:979))
+        (PORT clk (1799:1799:1799) (1828:1828:1828))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1719:1719:1719) (1713:1713:1713))
+        (PORT clk (1799:1799:1799) (1828:1828:1828))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1802:1802:1802) (1832:1832:1832))
+        (PORT d[0] (2244:2244:2244) (2250:2250:2250))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1803:1803:1803) (1833:1833:1833))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1498:1498:1498) (1564:1564:1564))
+        (PORT d[1] (2076:2076:2076) (2182:2182:2182))
+        (PORT d[2] (1511:1511:1511) (1598:1598:1598))
+        (PORT d[3] (2009:2009:2009) (2096:2096:2096))
+        (PORT d[4] (1439:1439:1439) (1507:1507:1507))
+        (PORT d[5] (1737:1737:1737) (1853:1853:1853))
+        (PORT d[6] (2031:2031:2031) (2091:2091:2091))
+        (PORT d[7] (1772:1772:1772) (1879:1879:1879))
+        (PORT d[8] (2240:2240:2240) (2337:2337:2337))
+        (PORT d[9] (1356:1356:1356) (1419:1419:1419))
+        (PORT d[10] (1733:1733:1733) (1830:1830:1830))
+        (PORT d[11] (1715:1715:1715) (1780:1780:1780))
+        (PORT d[12] (1443:1443:1443) (1509:1509:1509))
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1720:1720:1720) (1714:1714:1714))
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1763:1763:1763) (1759:1759:1759))
+        (PORT d[0] (1715:1715:1715) (1678:1678:1678))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1764:1764:1764) (1760:1760:1760))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1759:1759:1759) (1759:1759:1759))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT asdata (568:568:568) (645:645:645))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (427:427:427) (493:493:493))
+        (PORT datab (1320:1320:1320) (1348:1348:1348))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (909:909:909) (929:929:929))
+        (PORT clk (1812:1812:1812) (1841:1841:1841))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1319:1319:1319) (1388:1388:1388))
+        (PORT d[1] (752:752:752) (821:821:821))
+        (PORT d[2] (1320:1320:1320) (1388:1388:1388))
+        (PORT d[3] (1561:1561:1561) (1622:1622:1622))
+        (PORT d[4] (1445:1445:1445) (1465:1465:1465))
+        (PORT d[5] (1448:1448:1448) (1483:1483:1483))
+        (PORT d[6] (1972:1972:1972) (1964:1964:1964))
+        (PORT d[7] (1430:1430:1430) (1439:1439:1439))
+        (PORT d[8] (1663:1663:1663) (1670:1670:1670))
+        (PORT d[9] (1392:1392:1392) (1418:1418:1418))
+        (PORT d[10] (1581:1581:1581) (1672:1672:1672))
+        (PORT d[11] (1711:1711:1711) (1717:1717:1717))
+        (PORT d[12] (1439:1439:1439) (1448:1448:1448))
+        (PORT clk (1809:1809:1809) (1837:1837:1837))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1795:1795:1795) (1759:1759:1759))
+        (PORT clk (1809:1809:1809) (1837:1837:1837))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1812:1812:1812) (1841:1841:1841))
+        (PORT d[0] (2320:2320:2320) (2296:2296:2296))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1813:1813:1813) (1842:1842:1842))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1320:1320:1320) (1388:1388:1388))
+        (PORT d[1] (775:775:775) (845:845:845))
+        (PORT d[2] (1286:1286:1286) (1338:1338:1338))
+        (PORT d[3] (1562:1562:1562) (1622:1622:1622))
+        (PORT d[4] (755:755:755) (812:812:812))
+        (PORT d[5] (756:756:756) (820:820:820))
+        (PORT d[6] (733:733:733) (790:790:790))
+        (PORT d[7] (728:728:728) (782:782:782))
+        (PORT d[8] (745:745:745) (806:806:806))
+        (PORT d[9] (971:971:971) (1044:1044:1044))
+        (PORT d[10] (748:748:748) (812:812:812))
+        (PORT d[11] (1302:1302:1302) (1369:1369:1369))
+        (PORT d[12] (959:959:959) (1024:1024:1024))
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1796:1796:1796) (1760:1760:1760))
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1773:1773:1773) (1768:1768:1768))
+        (PORT d[0] (1893:1893:1893) (1841:1841:1841))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1774:1774:1774) (1769:1769:1769))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1769:1769:1769) (1768:1768:1768))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (387:387:387) (464:464:464))
+        (PORT datab (1162:1162:1162) (1173:1173:1173))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1393:1393:1393) (1409:1409:1409))
+        (PORT clk (1804:1804:1804) (1835:1835:1835))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1503:1503:1503) (1589:1589:1589))
+        (PORT d[1] (1532:1532:1532) (1630:1630:1630))
+        (PORT d[2] (1517:1517:1517) (1582:1582:1582))
+        (PORT d[3] (1489:1489:1489) (1574:1574:1574))
+        (PORT d[4] (700:700:700) (731:731:731))
+        (PORT d[5] (418:418:418) (445:445:445))
+        (PORT d[6] (409:409:409) (431:431:431))
+        (PORT d[7] (415:415:415) (441:441:441))
+        (PORT d[8] (409:409:409) (431:431:431))
+        (PORT d[9] (420:420:420) (448:448:448))
+        (PORT d[10] (408:408:408) (427:427:427))
+        (PORT d[11] (403:403:403) (430:430:430))
+        (PORT d[12] (420:420:420) (446:446:446))
+        (PORT clk (1801:1801:1801) (1831:1831:1831))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1687:1687:1687) (1701:1701:1701))
+        (PORT clk (1801:1801:1801) (1831:1831:1831))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1804:1804:1804) (1835:1835:1835))
+        (PORT d[0] (2212:2212:2212) (2238:2238:2238))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1805:1805:1805) (1836:1836:1836))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1805:1805:1805) (1836:1836:1836))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1805:1805:1805) (1836:1836:1836))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1805:1805:1805) (1836:1836:1836))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1526:1526:1526) (1608:1608:1608))
+        (PORT d[1] (1533:1533:1533) (1630:1630:1630))
+        (PORT d[2] (1531:1531:1531) (1608:1608:1608))
+        (PORT d[3] (1490:1490:1490) (1574:1574:1574))
+        (PORT d[4] (1466:1466:1466) (1559:1559:1559))
+        (PORT d[5] (1472:1472:1472) (1587:1587:1587))
+        (PORT d[6] (1507:1507:1507) (1587:1587:1587))
+        (PORT d[7] (1512:1512:1512) (1629:1629:1629))
+        (PORT d[8] (1533:1533:1533) (1604:1604:1604))
+        (PORT d[9] (1410:1410:1410) (1485:1485:1485))
+        (PORT d[10] (1474:1474:1474) (1570:1570:1570))
+        (PORT d[11] (1496:1496:1496) (1580:1580:1580))
+        (PORT d[12] (1470:1470:1470) (1560:1560:1560))
+        (PORT clk (1765:1765:1765) (1762:1762:1762))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1688:1688:1688) (1702:1702:1702))
+        (PORT clk (1765:1765:1765) (1762:1762:1762))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1765:1765:1765) (1762:1762:1762))
+        (PORT d[0] (1723:1723:1723) (1708:1708:1708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1766:1766:1766) (1763:1763:1763))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1766:1766:1766) (1763:1763:1763))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1766:1766:1766) (1763:1763:1763))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1761:1761:1761) (1762:1762:1762))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|data_from_adc\[0\]\~feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (227:227:227) (299:299:299))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|data_from_adc\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1470:1470:1470) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (PORT ena (1313:1313:1313) (1361:1361:1361))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1271:1271:1271) (1305:1305:1305))
+        (PORT datab (421:421:421) (485:485:485))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (355:355:355) (349:349:349))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~14)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (386:386:386) (464:464:464))
+        (PORT datab (1216:1216:1216) (1221:1221:1221))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~16)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (425:425:425) (507:507:507))
+        (PORT datab (944:944:944) (960:960:960))
+        (IOPATH dataa combout (341:341:341) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (501:501:501))
+        (PORT datad (907:907:907) (919:919:919))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (198:198:198) (236:236:236))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (198:198:198) (236:236:236))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|Add3\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (200:200:200) (243:243:243))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (970:970:970) (997:997:997))
+        (PORT clk (1814:1814:1814) (1844:1844:1844))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1066:1066:1066) (1141:1141:1141))
+        (PORT d[1] (1058:1058:1058) (1146:1146:1146))
+        (PORT d[2] (1070:1070:1070) (1157:1157:1157))
+        (PORT d[3] (1541:1541:1541) (1608:1608:1608))
+        (PORT d[4] (1149:1149:1149) (1157:1157:1157))
+        (PORT d[5] (1149:1149:1149) (1167:1167:1167))
+        (PORT d[6] (2548:2548:2548) (2536:2536:2536))
+        (PORT d[7] (1153:1153:1153) (1160:1160:1160))
+        (PORT d[8] (1158:1158:1158) (1169:1169:1169))
+        (PORT d[9] (1125:1125:1125) (1131:1131:1131))
+        (PORT d[10] (1213:1213:1213) (1289:1289:1289))
+        (PORT d[11] (1994:1994:1994) (1995:1995:1995))
+        (PORT d[12] (1105:1105:1105) (1127:1127:1127))
+        (PORT clk (1811:1811:1811) (1840:1840:1840))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1511:1511:1511) (1478:1478:1478))
+        (PORT clk (1811:1811:1811) (1840:1840:1840))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1814:1814:1814) (1844:1844:1844))
+        (PORT d[0] (2036:2036:2036) (2015:2015:2015))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1059:1059:1059) (1144:1144:1144))
+        (PORT d[1] (1059:1059:1059) (1146:1146:1146))
+        (PORT d[2] (1026:1026:1026) (1113:1113:1113))
+        (PORT d[3] (1542:1542:1542) (1608:1608:1608))
+        (PORT d[4] (1037:1037:1037) (1106:1106:1106))
+        (PORT d[5] (1026:1026:1026) (1123:1123:1123))
+        (PORT d[6] (1023:1023:1023) (1115:1115:1115))
+        (PORT d[7] (1003:1003:1003) (1079:1079:1079))
+        (PORT d[8] (1069:1069:1069) (1128:1128:1128))
+        (PORT d[9] (1257:1257:1257) (1348:1348:1348))
+        (PORT d[10] (1098:1098:1098) (1162:1162:1162))
+        (PORT d[11] (1234:1234:1234) (1319:1319:1319))
+        (PORT d[12] (1015:1015:1015) (1091:1091:1091))
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1512:1512:1512) (1479:1479:1479))
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+        (PORT d[0] (2144:2144:2144) (2105:2105:2105))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1771:1771:1771) (1771:1771:1771))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.datain_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (959:959:959) (970:970:970))
+        (PORT clk (1814:1814:1814) (1844:1844:1844))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1309:1309:1309) (1353:1353:1353))
+        (PORT d[1] (1013:1013:1013) (1074:1074:1074))
+        (PORT d[2] (1303:1303:1303) (1370:1370:1370))
+        (PORT d[3] (1540:1540:1540) (1604:1604:1604))
+        (PORT d[4] (1719:1719:1719) (1719:1719:1719))
+        (PORT d[5] (1476:1476:1476) (1516:1516:1516))
+        (PORT d[6] (2799:2799:2799) (2826:2826:2826))
+        (PORT d[7] (1458:1458:1458) (1471:1471:1471))
+        (PORT d[8] (1664:1664:1664) (1671:1671:1671))
+        (PORT d[9] (1393:1393:1393) (1419:1419:1419))
+        (PORT d[10] (1513:1513:1513) (1613:1613:1613))
+        (PORT d[11] (1631:1631:1631) (1640:1640:1640))
+        (PORT d[12] (1439:1439:1439) (1449:1449:1449))
+        (PORT clk (1811:1811:1811) (1840:1840:1840))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.we_a_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1495:1495:1495) (1478:1478:1478))
+        (PORT clk (1811:1811:1811) (1840:1840:1840))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1814:1814:1814) (1844:1844:1844))
+        (PORT d[0] (2062:2062:2062) (2040:2040:2040))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.wpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2070:2070:2070))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_a)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1815:1815:1815) (1845:1845:1845))
+        (IOPATH (posedge clk) pulse (0:0:0) (2618:2618:2618))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.addr_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1332:1332:1332) (1377:1377:1377))
+        (PORT d[1] (1000:1000:1000) (1042:1042:1042))
+        (PORT d[2] (1304:1304:1304) (1370:1370:1370))
+        (PORT d[3] (1541:1541:1541) (1604:1604:1604))
+        (PORT d[4] (1023:1023:1023) (1076:1076:1076))
+        (PORT d[5] (994:994:994) (1049:1049:1049))
+        (PORT d[6] (1311:1311:1311) (1383:1383:1383))
+        (PORT d[7] (1334:1334:1334) (1427:1427:1427))
+        (PORT d[8] (997:997:997) (1051:1051:1051))
+        (PORT d[9] (1242:1242:1242) (1310:1310:1310))
+        (PORT d[10] (1013:1013:1013) (1072:1072:1072))
+        (PORT d[11] (1331:1331:1331) (1420:1420:1420))
+        (PORT d[12] (1017:1017:1017) (1071:1071:1071))
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.re_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT d[0] (1538:1538:1538) (1504:1504:1504))
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (187:187:187))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1775:1775:1775) (1771:1771:1771))
+        (PORT d[0] (2394:2394:2394) (2348:2348:2348))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2424:2424:2424))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_pulse_generator")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1776:1776:1776) (1772:1772:1772))
+        (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_ram_register")
+    (INSTANCE DUMMY\|DELAY\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_b_register)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1771:1771:1771) (1771:1771:1771))
+        (IOPATH (posedge clk) q (301:301:301) (301:301:301))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP d (posedge clk) (51:51:51))
+      (HOLD d (posedge clk) (159:159:159))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (964:964:964) (1067:1067:1067))
+        (PORT datac (1369:1369:1369) (1451:1451:1451))
+        (PORT datad (719:719:719) (779:779:779))
+        (IOPATH dataa combout (324:324:324) (328:328:328))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~12)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (964:964:964) (1067:1067:1067))
+        (PORT datab (243:243:243) (326:326:326))
+        (PORT datac (1150:1150:1150) (1198:1198:1198))
+        (PORT datad (719:719:719) (779:779:779))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1094:1094:1094) (1182:1182:1182))
+        (PORT datab (763:763:763) (827:827:827))
+        (PORT datac (218:218:218) (295:295:295))
+        (PORT datad (915:915:915) (1013:1013:1013))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~10)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (958:958:958) (1060:1060:1060))
+        (PORT datab (244:244:244) (326:326:326))
+        (PORT datac (1027:1027:1027) (1091:1091:1091))
+        (PORT datad (726:726:726) (787:787:787))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (957:957:957) (1059:1059:1059))
+        (PORT datab (244:244:244) (326:326:326))
+        (PORT datac (860:860:860) (904:904:904))
+        (PORT datad (727:727:727) (787:787:787))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1467:1467:1467) (1484:1484:1484))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~8)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (985:985:985) (1138:1138:1138))
+        (PORT datab (426:426:426) (507:507:507))
+        (PORT datac (1052:1052:1052) (1143:1143:1143))
+        (PORT datad (302:302:302) (396:396:396))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (982:982:982) (1136:1136:1136))
+        (PORT datab (246:246:246) (328:328:328))
+        (PORT datac (692:692:692) (750:750:750))
+        (PORT datad (306:306:306) (397:397:397))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~6)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (979:979:979) (1141:1141:1141))
+        (PORT datab (687:687:687) (755:755:755))
+        (PORT datac (218:218:218) (295:295:295))
+        (PORT datad (304:304:304) (399:399:399))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datab combout (306:306:306) (308:308:308))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (977:977:977) (1142:1142:1142))
+        (PORT datab (245:245:245) (329:329:329))
+        (PORT datac (875:875:875) (961:961:961))
+        (PORT datad (305:305:305) (398:398:398))
+        (IOPATH dataa combout (301:301:301) (308:308:308))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datac combout (241:241:241) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE DUMMY\|data_out\[9\]\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (193:193:193) (226:226:226))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE DUMMY\|data_out\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1479:1479:1479) (1495:1495:1495))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~4)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (248:248:248) (336:336:336))
+        (PORT datab (328:328:328) (434:434:434))
+        (PORT datac (1271:1271:1271) (1339:1339:1339))
+        (PORT datad (957:957:957) (1084:1084:1084))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (982:982:982) (1138:1138:1138))
+        (PORT datac (217:217:217) (294:294:294))
+        (PORT datad (304:304:304) (394:394:394))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~2)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (991:991:991) (1136:1136:1136))
+        (PORT datac (217:217:217) (293:293:293))
+        (PORT datad (299:299:299) (392:392:392))
+        (IOPATH dataa combout (304:304:304) (307:307:307))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (975:975:975) (1139:1139:1139))
+        (PORT datac (219:219:219) (296:296:296))
+        (PORT datad (306:306:306) (399:399:399))
+        (IOPATH dataa combout (325:325:325) (320:320:320))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|shift_reg\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (984:984:984) (1141:1141:1141))
+        (PORT datab (335:335:335) (441:441:441))
+        (PORT datad (219:219:219) (288:288:288))
+        (IOPATH dataa combout (300:300:300) (308:308:308))
+        (IOPATH datab combout (300:300:300) (310:310:310))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|shift_reg\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1471:1471:1471) (1486:1486:1486))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SCK\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (410:410:410) (490:490:490))
+        (PORT datab (263:263:263) (345:345:345))
+        (PORT datac (623:623:623) (690:690:690))
+        (PORT datad (1279:1279:1279) (1430:1430:1430))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH datab combout (336:336:336) (332:332:332))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_DAC\|Equal2\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (219:219:219) (265:265:265))
+        (PORT datac (243:243:243) (331:331:331))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datac combout (241:241:241) (241:241:241))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_DAC\|dac_ld)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1473:1473:1473) (1488:1488:1488))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_io_ibuf")
+    (INSTANCE SW\[9\]\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (736:736:736) (991:991:991))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector6\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (500:500:500) (577:577:577))
+        (PORT datab (3070:3070:3070) (3350:3350:3350))
+        (PORT datac (274:274:274) (374:374:374))
+        (PORT datad (246:246:246) (325:325:325))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH datab combout (342:342:342) (342:342:342))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE SPI_ADC\|Selector6\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (281:281:281) (378:378:378))
+        (PORT datab (279:279:279) (371:371:371))
+        (PORT datac (175:175:175) (209:209:209))
+        (PORT datad (258:258:258) (340:340:340))
+        (IOPATH dataa combout (337:337:337) (338:338:338))
+        (IOPATH datab combout (337:337:337) (348:348:348))
+        (IOPATH datac combout (243:243:243) (241:241:241))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE SPI_ADC\|adc_din)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1474:1474:1474) (1490:1490:1490))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[1\]\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (508:508:508))
+        (PORT datab (262:262:262) (344:344:344))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[2\]\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (265:265:265) (351:351:351))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[3\]\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (345:345:345))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[4\]\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (353:353:353))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[5\]\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (353:353:353))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[6\]\~19)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[7\]\~21)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[8\]\~23)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|count\[9\]\~25)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (239:239:239) (309:309:309))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|count\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1209:1209:1209) (1257:1257:1257))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1823:1823:1823) (1907:1907:1907))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (997:997:997) (1053:1053:1053))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1188:1188:1188) (1234:1234:1234))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1822:1822:1822) (1912:1912:1912))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1205:1205:1205) (1246:1246:1246))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1369:1369:1369) (1432:1432:1432))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1397:1397:1397) (1484:1484:1484))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1496:1496:1496) (1540:1540:1540))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|d\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1483:1483:1483) (1498:1498:1498))
+        (PORT asdata (1711:1711:1711) (1788:1788:1788))
+        (PORT ena (1075:1075:1075) (1115:1115:1115))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD asdata (posedge clk) (157:157:157))
+      (HOLD ena (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~1)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (329:329:329))
+        (PORT datab (911:911:911) (968:968:968))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~3)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (447:447:447) (513:513:513))
+        (PORT datab (242:242:242) (323:323:323))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~5)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (331:331:331))
+        (PORT datab (632:632:632) (701:701:701))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~7)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (331:331:331))
+        (PORT datab (440:440:440) (505:505:505))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~9)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (426:426:426) (506:506:506))
+        (PORT datab (405:405:405) (480:480:480))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~11)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (680:680:680) (741:741:741))
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~13)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (679:679:679) (742:742:742))
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~15)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (649:649:649) (716:716:716))
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~17)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (330:330:330))
+        (PORT datab (439:439:439) (505:505:505))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|LessThan0\~18)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (407:407:407) (486:486:486))
+        (PORT datab (242:242:242) (324:324:324))
+        (IOPATH dataa combout (354:354:354) (349:349:349))
+        (IOPATH datab combout (381:381:381) (380:380:380))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneiii_lcell_comb")
+    (INSTANCE PWM_DC\|pwm_out\~0)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (858:858:858) (864:864:864))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE PWM_DC\|pwm_out)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1478:1478:1478) (1494:1494:1494))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+)
diff --git a/part_4/ex16/simulation/modelsim/vsim.wlf b/part_4/ex16/simulation/modelsim/vsim.wlf
new file mode 100755
index 0000000..762c078
--- /dev/null
+++ b/part_4/ex16/simulation/modelsim/vsim.wlf
diff --git a/part_4/ex16/spi2adc.v b/part_4/ex16/spi2adc.v
new file mode 100755
index 0000000..3878f71
--- /dev/null
+++ b/part_4/ex16/spi2adc.v
@@ -0,0 +1,150 @@
+//------------------------------
+// Module name: spi2adc
+// Function: SPI interface for MCP3002 ADC
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     24 Jan 2014
+//------------------------------
+
+module spi2adc (sysclk, start, channel, data_from_adc, data_valid, 
+						sdata_to_adc, adc_cs, adc_sck, sdata_from_adc);
+
+	input	sysclk;			// 50MHz system clock of DE0
+	input	start;			// Pulse to start ADC, minimum wide = clock period
+	input	channel;			// channel 0 or 1 to be converted
+	output [9:0] data_from_adc;	// 10-bit ADC result
+	output data_valid;	// High indicates that converted data valid
+	output sdata_to_adc;	// Serial commands send to adc chip
+	output adc_cs;			// chip select - low when converting
+	output adc_sck;		// SPI clock - active during conversion
+	input sdata_from_adc;	// Converted serial data from ADC, MSB first
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire	sysclk, start, sdata_from_adc;
+
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg [9:0]	data_from_adc;
+	reg			adc_cs;
+	wire			sdata_to_adc, adc_sck, data_valid;
+	
+//-------------Configuration parameters for ADC --------
+	parameter	SGL=1'b1;	// 0:diff i/p, 1:single-ended
+	parameter	MSBF=1'b1;	// 0:LSB first, 1:MSB first
+			
+// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... to start.  Initialise to make simulation easier
+	end
+		
+	always @ (posedge sysclk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+// ---- end internal clock generator ----------
+
+// ---- Detect start is asserted with a small state machine
+	// .... FF set on positive edge of start
+	// .... reset when adc_cs goes high again
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			adc_start;
+	
+	initial begin
+		sr_state = IDLE;
+		adc_start = 1'b0;	// set while sending data to ADC
+		end
+	
+	always @ (posedge sysclk)
+		case (sr_state)
+			IDLE:	if (start==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						adc_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (adc_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (adc_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						adc_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+//------- End circuit to detect start and end of conversion	
+
+	
+// spi controller designed as a state machine
+// .... with 16 states (idle, and S1-S15 indicated by state value
+
+	reg [4:0] 	state;
+	reg  	adc_done, adc_din, shift_ena;
+	
+	initial	begin	
+		state = 5'b0; adc_cs = 1'b1; adc_done = 1'b0; 
+		adc_din = 1'b0; shift_ena <= 1'b0;
+		end
+		
+	always @(posedge clk_1MHz)  begin
+	
+	// default outputs and state transition
+		adc_cs <= 1'b0;  adc_done <= 1'b0;  adc_din <= 1'b0; shift_ena <= 1'b0;
+		state <= state + 1'b1;
+		case (state)
+			5'd0:	begin
+						if (adc_start==1'b0) begin
+							state <= 5'd0;			// still idle
+							adc_cs <= 1'b1;		// chip select not active
+							end
+						else begin
+							state <= 5'd1;			// start converting
+							adc_din <= 1'b1;		// start bit is 1
+							end
+					end
+			5'd1:	adc_din <= SGL;				// SGL bit
+			5'd2:	adc_din <= channel;			// CH bit
+			5'd3:	adc_din <= MSBF;				// MSB first bit
+			5'd4: shift_ena <= 1'b1;  			// start shifting data from adc
+			5'd15: begin
+						shift_ena <= 1'b0;
+						adc_done <= 1'b1;
+					 end
+			5'd16: begin  
+						adc_cs <= 1'b1;		// last state - disable chip select
+						state <= 5'd0;  		// go back to idle state
+					 end
+			default: 				
+						shift_ena <= 1'b1;	// unspecified states are covered by default above
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [9:0] shift_reg;
+	initial	begin
+			shift_reg = 10'b0;
+			data_from_adc = 10'b0;
+			end
+	
+	always @(negedge clk_1MHz)
+		if((adc_cs==1'b0)&&(shift_ena==1'b1))		// start shifting data_in
+				shift_reg <= {shift_reg[8:0],sdata_from_adc};
+	
+	// Latch converted output data
+	always @(posedge clk_1MHz)
+		if(adc_done) 					
+				data_from_adc = shift_reg;
+
+	// Assign outputs to drive SPI interface to DAC
+		assign adc_sck = !clk_1MHz & !adc_cs;
+		assign sdata_to_adc = adc_din;
+		assign data_valid = adc_cs;
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex16/spi2dac.v b/part_4/ex16/spi2dac.v
new file mode 100755
index 0000000..ccfb4e8
--- /dev/null
+++ b/part_4/ex16/spi2dac.v
@@ -0,0 +1,128 @@
+//------------------------------
+// Module name: spi2dac
+// Function: SPI interface for MPC4911 DAC
+// Creator:  Peter Cheung
+// Version:  1.3
+// Date:     8 Nov 2016
+//------------------------------
+
+module spi2dac (clk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld);
+
+	input	clk;				// 50MHz system clock of DE0
+	input	[9:0]	data_in;	// input data to DAC
+	input	load;				// Pulse to load data to dac
+	output dac_sdi;		// SPI serial data out
+	output dac_cs;			// chip select - low when sending data to dac
+	output dac_sck;		// SPI clock, 16 cycles at half clk freq
+	output dac_ld;
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire			clk, load;
+	wire [9:0]	data_in;
+	
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg			dac_cs, dac_ld;
+	wire			dac_sck, dac_sdi;
+	
+	parameter	BUF=1'b1;		// 0:no buffer, 1:Vref buffered
+	parameter	GA_N=1'b1;		// 0:gain = 2x, 1:gain = 1x
+	parameter	SHDN_N=1'b1;	// 0:power down, 1:dac active
+	
+	wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N};  // wire to VDD or GND
+	
+	// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... Initialise when FPGA is configured
+	end
+		
+	always @ (posedge clk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+	// ---- end internal clock generator ----------
+
+	// ---- Detect posedge of load with a small state machine
+	// .... FF set on posedge of load
+	// .... reset when dac_cs goes high at the end of DAC output cycle
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			dac_start;		 // set if a DAC write is detected
+	
+	initial begin
+		sr_state = IDLE;
+		dac_start = 1'b0;	// set while sending data to DAC
+		end
+	
+	always @ (posedge clk)
+		case (sr_state)
+			IDLE:	if (load==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						dac_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (dac_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						dac_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+	//------- End circuit to detect start and end of conversion	
+
+	//------- spi controller designed as a state machine
+	// .... with 17 states (idle, and S1-S16 
+	// .... for the 16 cycles each sending 1-bit to dac)
+	reg [4:0] 	state;
+	
+	initial	begin	
+		state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; 
+		end
+		
+	always @(posedge clk_1MHz)  begin
+		// default outputs and state transition
+		dac_cs <= 1'b0; dac_ld <= 1'b1; 
+		state <= state + 1'b1;	// move to next state by default
+		case (state)
+			5'd0:	if (dac_start == 1'b0)  begin  
+						state <= 5'd0; 				// still waiting
+						dac_cs <= 1'b1; 
+						end
+			5'd16: begin  
+						dac_cs <= 1'b1; dac_ld <= 1'b0; 
+						state <= 5'd0;  // go back to idle state
+					end
+			default:   begin					// all other states
+					dac_cs <= 1'b0; dac_ld <= 1'b1; 
+					state <= state + 1'b1;	// default state transition
+					end
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [15:0] shift_reg;
+	initial	begin	
+		shift_reg = 16'b0; 
+		end
+
+	always @(posedge clk_1MHz)
+		if((dac_start==1'b1)&&(dac_cs==1'b1))		// parallel load data to shift reg
+			shift_reg <= {cmd,data_in,2'b00};
+		else 													// .. else start shifting
+			shift_reg <= {shift_reg[14:0],1'b0};
+	
+	// Assign outputs to drive SPI interface to DAC
+			assign dac_sck = !clk_1MHz&!dac_cs;
+			assign dac_sdi = shift_reg[15];
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex17/c5_pin_model_dump.txt b/part_4/ex17/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_4/ex17/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_4/ex17/db/.cmp.kpt b/part_4/ex17/db/.cmp.kpt
new file mode 100755
index 0000000..2386445
--- /dev/null
+++ b/part_4/ex17/db/.cmp.kpt
diff --git a/part_4/ex17/db/a_dpfifo_br81.tdf b/part_4/ex17/db/a_dpfifo_br81.tdf
new file mode 100755
index 0000000..e8ece42
--- /dev/null
+++ b/part_4/ex17/db/a_dpfifo_br81.tdf
@@ -0,0 +1,77 @@
+--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone V" LPM_NUMWORDS=8192 LPM_SHOWAHEAD="OFF" lpm_width=10 lpm_widthu=13 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data full q rreq sclr wreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO"
+--VERSION_BEGIN 16.0 cbx_altdpram 2016:04:27:18:05:34:SJ cbx_altera_syncram 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_scfifo 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION a_fefifo_4be (aclr, clock, rreq, sclr, wreq)
+RETURNS ( empty, full);
+FUNCTION altsyncram_44t1 (address_a[12..0], address_b[12..0], clock0, clock1, clocken1, data_a[9..0], wren_a)
+RETURNS ( q_b[9..0]);
+FUNCTION cntr_1ib (aclr, clock, cnt_en, sclr)
+RETURNS ( q[12..0]);
+
+--synthesis_resources = lut 39 M10K 10 reg 41 
+SUBDESIGN a_dpfifo_br81
+( 
+	clock	:	input;
+	data[9..0]	:	input;
+	full	:	output;
+	q[9..0]	:	output;
+	rreq	:	input;
+	sclr	:	input;
+	wreq	:	input;
+) 
+VARIABLE 
+	fifo_state : a_fefifo_4be;
+	FIFOram : altsyncram_44t1;
+	rd_ptr_count : cntr_1ib;
+	wr_ptr : cntr_1ib;
+	aclr	: NODE;
+	rd_ptr[12..0]	: WIRE;
+	valid_rreq	: WIRE;
+	valid_wreq	: WIRE;
+
+BEGIN 
+	fifo_state.aclr = aclr;
+	fifo_state.clock = clock;
+	fifo_state.rreq = rreq;
+	fifo_state.sclr = sclr;
+	fifo_state.wreq = wreq;
+	FIFOram.address_a[] = wr_ptr.q[];
+	FIFOram.address_b[] = ((! sclr) & rd_ptr[]);
+	FIFOram.clock0 = clock;
+	FIFOram.clock1 = clock;
+	FIFOram.clocken1 = (valid_rreq # sclr);
+	FIFOram.data_a[] = data[];
+	FIFOram.wren_a = valid_wreq;
+	rd_ptr_count.aclr = aclr;
+	rd_ptr_count.clock = clock;
+	rd_ptr_count.cnt_en = valid_rreq;
+	rd_ptr_count.sclr = sclr;
+	wr_ptr.aclr = aclr;
+	wr_ptr.clock = clock;
+	wr_ptr.cnt_en = valid_wreq;
+	wr_ptr.sclr = sclr;
+	aclr = GND;
+	full = fifo_state.full;
+	q[] = FIFOram.q_b[];
+	rd_ptr[] = rd_ptr_count.q[];
+	valid_rreq = (rreq & (! fifo_state.empty));
+	valid_wreq = (wreq & (! fifo_state.full));
+END;
+--VALID FILE
diff --git a/part_4/ex17/db/a_fefifo_4be.tdf b/part_4/ex17/db/a_fefifo_4be.tdf
new file mode 100755
index 0000000..c1151ed
--- /dev/null
+++ b/part_4/ex17/db/a_fefifo_4be.tdf
@@ -0,0 +1,117 @@
+--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=8192 lpm_widthad=13 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" aclr clock empty full rreq sclr wreq
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cntr_di7 (aclr, clock, cnt_en, sclr, updown)
+RETURNS ( q[12..0]);
+
+--synthesis_resources = lut 13 reg 15 
+SUBDESIGN a_fefifo_4be
+( 
+	aclr	:	input;
+	clock	:	input;
+	empty	:	output;
+	full	:	output;
+	rreq	:	input;
+	sclr	:	input;
+	wreq	:	input;
+) 
+VARIABLE 
+	b_full : dffe;
+	b_non_empty : dffe;
+	count_usedw : cntr_di7;
+	equal_af1w[12..0]	: WIRE;
+	equal_one[12..0]	: WIRE;
+	is_almost_empty0	: WIRE;
+	is_almost_empty1	: WIRE;
+	is_almost_empty10	: WIRE;
+	is_almost_empty11	: WIRE;
+	is_almost_empty12	: WIRE;
+	is_almost_empty2	: WIRE;
+	is_almost_empty3	: WIRE;
+	is_almost_empty4	: WIRE;
+	is_almost_empty5	: WIRE;
+	is_almost_empty6	: WIRE;
+	is_almost_empty7	: WIRE;
+	is_almost_empty8	: WIRE;
+	is_almost_empty9	: WIRE;
+	is_almost_full0	: WIRE;
+	is_almost_full1	: WIRE;
+	is_almost_full10	: WIRE;
+	is_almost_full11	: WIRE;
+	is_almost_full12	: WIRE;
+	is_almost_full2	: WIRE;
+	is_almost_full3	: WIRE;
+	is_almost_full4	: WIRE;
+	is_almost_full5	: WIRE;
+	is_almost_full6	: WIRE;
+	is_almost_full7	: WIRE;
+	is_almost_full8	: WIRE;
+	is_almost_full9	: WIRE;
+	usedw[12..0]	: WIRE;
+	valid_rreq	: WIRE;
+	valid_wreq	: WIRE;
+
+BEGIN 
+	b_full.clk = clock;
+	b_full.clrn = (! aclr);
+	b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full12 & wreq) & (! rreq)))));
+	b_non_empty.clk = clock;
+	b_non_empty.clrn = (! aclr);
+	b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty12 & rreq) & (! wreq))))));
+	count_usedw.aclr = aclr;
+	count_usedw.clock = clock;
+	count_usedw.cnt_en = (valid_wreq $ valid_rreq);
+	count_usedw.sclr = sclr;
+	count_usedw.updown = valid_wreq;
+	empty = (! b_non_empty.q);
+	equal_af1w[] = ( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0");
+	equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"0");
+	full = b_full.q;
+	is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]);
+	is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0);
+	is_almost_empty10 = ((usedw[10..10] $ equal_one[10..10]) & is_almost_empty9);
+	is_almost_empty11 = ((usedw[11..11] $ equal_one[11..11]) & is_almost_empty10);
+	is_almost_empty12 = ((usedw[12..12] $ equal_one[12..12]) & is_almost_empty11);
+	is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1);
+	is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2);
+	is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3);
+	is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4);
+	is_almost_empty6 = ((usedw[6..6] $ equal_one[6..6]) & is_almost_empty5);
+	is_almost_empty7 = ((usedw[7..7] $ equal_one[7..7]) & is_almost_empty6);
+	is_almost_empty8 = ((usedw[8..8] $ equal_one[8..8]) & is_almost_empty7);
+	is_almost_empty9 = ((usedw[9..9] $ equal_one[9..9]) & is_almost_empty8);
+	is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]);
+	is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0);
+	is_almost_full10 = ((usedw[10..10] $ equal_af1w[10..10]) & is_almost_full9);
+	is_almost_full11 = ((usedw[11..11] $ equal_af1w[11..11]) & is_almost_full10);
+	is_almost_full12 = ((usedw[12..12] $ equal_af1w[12..12]) & is_almost_full11);
+	is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1);
+	is_almost_full3 = ((usedw[3..3] $ equal_af1w[3..3]) & is_almost_full2);
+	is_almost_full4 = ((usedw[4..4] $ equal_af1w[4..4]) & is_almost_full3);
+	is_almost_full5 = ((usedw[5..5] $ equal_af1w[5..5]) & is_almost_full4);
+	is_almost_full6 = ((usedw[6..6] $ equal_af1w[6..6]) & is_almost_full5);
+	is_almost_full7 = ((usedw[7..7] $ equal_af1w[7..7]) & is_almost_full6);
+	is_almost_full8 = ((usedw[8..8] $ equal_af1w[8..8]) & is_almost_full7);
+	is_almost_full9 = ((usedw[9..9] $ equal_af1w[9..9]) & is_almost_full8);
+	usedw[] = count_usedw.q[];
+	valid_rreq = (rreq & b_non_empty.q);
+	valid_wreq = (wreq & (! b_full.q));
+END;
+--VALID FILE
diff --git a/part_4/ex17/db/altsyncram_44t1.tdf b/part_4/ex17/db/altsyncram_44t1.tdf
new file mode 100755
index 0000000..58aacc2
--- /dev/null
+++ b/part_4/ex17/db/altsyncram_44t1.tdf
@@ -0,0 +1,366 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" ENABLE_ECC="FALSE" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=8192 NUMWORDS_B=8192 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=10 WIDTH_B=10 WIDTH_ECCSTATUS=2 WIDTHAD_A=13 WIDTHAD_B=13 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 10 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_44t1
+( 
+	address_a[12..0]	:	input;
+	address_b[12..0]	:	input;
+	clock0	:	input;
+	clock1	:	input;
+	clocken1	:	input;
+	data_a[9..0]	:	input;
+	q_b[9..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[12..0]	: WIRE;
+	address_b_wire[12..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[9..0].clk0 = clock0;
+	ram_block1a[9..0].clk1 = clock1;
+	ram_block1a[9..0].ena0 = wren_a;
+	ram_block1a[9..0].ena1 = clocken1;
+	ram_block1a[9..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[8].portadatain[] = ( data_a[8..8]);
+	ram_block1a[9].portadatain[] = ( data_a[9..9]);
+	ram_block1a[9..0].portawe = wren_a;
+	ram_block1a[9..0].portbaddr[] = ( address_b_wire[12..0]);
+	ram_block1a[9..0].portbre = B"1111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block1a[9..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_4/ex17/db/cntr_1ib.tdf b/part_4/ex17/db/cntr_1ib.tdf
new file mode 100755
index 0000000..4580e79
--- /dev/null
+++ b/part_4/ex17/db/cntr_1ib.tdf
@@ -0,0 +1,152 @@
+--lpm_counter DEVICE_FAMILY="Cyclone V" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=13 aclr clock cnt_en q sclr
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein)
+WITH ( DONT_TOUCH, EXTENDED_LUT, LUT_MASK, SHARED_ARITH)
+RETURNS ( combout, cout, shareout, sumout);
+
+--synthesis_resources = lut 13 reg 13 
+SUBDESIGN cntr_1ib
+( 
+	aclr	:	input;
+	clock	:	input;
+	cnt_en	:	input;
+	q[12..0]	:	output;
+	sclr	:	input;
+) 
+VARIABLE 
+	counter_reg_bit[12..0] : dffeas;
+	counter_comb_bita0 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "000000000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita1 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita2 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita3 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita4 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita5 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita6 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita7 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita8 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita9 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita10 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita11 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita12 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	aclr_actual	: WIRE;
+	clk_en	: NODE;
+	data[12..0]	: NODE;
+	external_cin	: WIRE;
+	lsb_cin	: WIRE;
+	s_val[12..0]	: WIRE;
+	safe_q[12..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	updown_dir	: WIRE;
+	updown_lsb	: WIRE;
+	updown_other_bits	: WIRE;
+
+BEGIN 
+	counter_reg_bit[].asdata = ((sset & s_val[]) # ((! sset) & data[]));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[12..0].sumout);
+	counter_reg_bit[].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
+	counter_reg_bit[].sclr = sclr;
+	counter_reg_bit[].sload = (sset # sload);
+	counter_comb_bita[12..0].cin = ( counter_comb_bita[11..0].cout, lsb_cin);
+	counter_comb_bita[12..0].datad = ( counter_reg_bit[12..0].q);
+	counter_comb_bita[12..0].dataf = ( updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_lsb);
+	aclr_actual = aclr;
+	clk_en = VCC;
+	data[] = GND;
+	external_cin = B"1";
+	lsb_cin = B"0";
+	q[] = safe_q[];
+	s_val[] = B"1111111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sload = GND;
+	sset = GND;
+	updown_dir = B"1";
+	updown_lsb = updown_dir;
+	updown_other_bits = ((! external_cin) # updown_dir);
+END;
+--VALID FILE
diff --git a/part_4/ex17/db/cntr_di7.tdf b/part_4/ex17/db/cntr_di7.tdf
new file mode 100755
index 0000000..ca8be54
--- /dev/null
+++ b/part_4/ex17/db/cntr_di7.tdf
@@ -0,0 +1,153 @@
+--lpm_counter DEVICE_FAMILY="Cyclone V" lpm_width=13 aclr clock cnt_en q sclr updown
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein)
+WITH ( DONT_TOUCH, EXTENDED_LUT, LUT_MASK, SHARED_ARITH)
+RETURNS ( combout, cout, shareout, sumout);
+
+--synthesis_resources = lut 13 reg 13 
+SUBDESIGN cntr_di7
+( 
+	aclr	:	input;
+	clock	:	input;
+	cnt_en	:	input;
+	q[12..0]	:	output;
+	sclr	:	input;
+	updown	:	input;
+) 
+VARIABLE 
+	counter_reg_bit[12..0] : dffeas;
+	counter_comb_bita0 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "000000000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita1 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita2 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita3 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita4 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita5 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita6 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita7 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita8 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita9 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita10 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita11 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita12 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	aclr_actual	: WIRE;
+	clk_en	: NODE;
+	data[12..0]	: NODE;
+	external_cin	: WIRE;
+	lsb_cin	: WIRE;
+	s_val[12..0]	: WIRE;
+	safe_q[12..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	updown_dir	: WIRE;
+	updown_lsb	: WIRE;
+	updown_other_bits	: WIRE;
+
+BEGIN 
+	counter_reg_bit[].asdata = ((sset & s_val[]) # ((! sset) & data[]));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[12..0].sumout);
+	counter_reg_bit[].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
+	counter_reg_bit[].sclr = sclr;
+	counter_reg_bit[].sload = (sset # sload);
+	counter_comb_bita[12..0].cin = ( counter_comb_bita[11..0].cout, lsb_cin);
+	counter_comb_bita[12..0].datad = ( counter_reg_bit[12..0].q);
+	counter_comb_bita[12..0].dataf = ( updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_lsb);
+	aclr_actual = aclr;
+	clk_en = VCC;
+	data[] = GND;
+	external_cin = B"1";
+	lsb_cin = B"0";
+	q[] = safe_q[];
+	s_val[] = B"1111111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sload = GND;
+	sset = GND;
+	updown_dir = updown;
+	updown_lsb = updown_dir;
+	updown_other_bits = ((! external_cin) # updown_dir);
+END;
+--VALID FILE
diff --git a/part_4/ex17/db/ex17.(0).cnf.cdb b/part_4/ex17/db/ex17.(0).cnf.cdb
new file mode 100755
index 0000000..0bfaa76
--- /dev/null
+++ b/part_4/ex17/db/ex17.(0).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(0).cnf.hdb b/part_4/ex17/db/ex17.(0).cnf.hdb
new file mode 100755
index 0000000..617eb1a
--- /dev/null
+++ b/part_4/ex17/db/ex17.(0).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(1).cnf.cdb b/part_4/ex17/db/ex17.(1).cnf.cdb
new file mode 100755
index 0000000..bafd7f8
--- /dev/null
+++ b/part_4/ex17/db/ex17.(1).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(1).cnf.hdb b/part_4/ex17/db/ex17.(1).cnf.hdb
new file mode 100755
index 0000000..6ca1381
--- /dev/null
+++ b/part_4/ex17/db/ex17.(1).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(10).cnf.cdb b/part_4/ex17/db/ex17.(10).cnf.cdb
new file mode 100755
index 0000000..d950715
--- /dev/null
+++ b/part_4/ex17/db/ex17.(10).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(10).cnf.hdb b/part_4/ex17/db/ex17.(10).cnf.hdb
new file mode 100755
index 0000000..2ee8073
--- /dev/null
+++ b/part_4/ex17/db/ex17.(10).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(11).cnf.cdb b/part_4/ex17/db/ex17.(11).cnf.cdb
new file mode 100755
index 0000000..64e7f0b
--- /dev/null
+++ b/part_4/ex17/db/ex17.(11).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(11).cnf.hdb b/part_4/ex17/db/ex17.(11).cnf.hdb
new file mode 100755
index 0000000..4b7230c
--- /dev/null
+++ b/part_4/ex17/db/ex17.(11).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(12).cnf.cdb b/part_4/ex17/db/ex17.(12).cnf.cdb
new file mode 100755
index 0000000..6e72f4e
--- /dev/null
+++ b/part_4/ex17/db/ex17.(12).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(12).cnf.hdb b/part_4/ex17/db/ex17.(12).cnf.hdb
new file mode 100755
index 0000000..87916a2
--- /dev/null
+++ b/part_4/ex17/db/ex17.(12).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(13).cnf.cdb b/part_4/ex17/db/ex17.(13).cnf.cdb
new file mode 100755
index 0000000..eb4a3c4
--- /dev/null
+++ b/part_4/ex17/db/ex17.(13).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(13).cnf.hdb b/part_4/ex17/db/ex17.(13).cnf.hdb
new file mode 100755
index 0000000..59be03a
--- /dev/null
+++ b/part_4/ex17/db/ex17.(13).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(14).cnf.cdb b/part_4/ex17/db/ex17.(14).cnf.cdb
new file mode 100755
index 0000000..7f08008
--- /dev/null
+++ b/part_4/ex17/db/ex17.(14).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(14).cnf.hdb b/part_4/ex17/db/ex17.(14).cnf.hdb
new file mode 100755
index 0000000..6ba3316
--- /dev/null
+++ b/part_4/ex17/db/ex17.(14).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(15).cnf.cdb b/part_4/ex17/db/ex17.(15).cnf.cdb
new file mode 100755
index 0000000..0dd93ae
--- /dev/null
+++ b/part_4/ex17/db/ex17.(15).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(15).cnf.hdb b/part_4/ex17/db/ex17.(15).cnf.hdb
new file mode 100755
index 0000000..5c16533
--- /dev/null
+++ b/part_4/ex17/db/ex17.(15).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(16).cnf.cdb b/part_4/ex17/db/ex17.(16).cnf.cdb
new file mode 100755
index 0000000..3221fee
--- /dev/null
+++ b/part_4/ex17/db/ex17.(16).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(16).cnf.hdb b/part_4/ex17/db/ex17.(16).cnf.hdb
new file mode 100755
index 0000000..123882e
--- /dev/null
+++ b/part_4/ex17/db/ex17.(16).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(2).cnf.cdb b/part_4/ex17/db/ex17.(2).cnf.cdb
new file mode 100755
index 0000000..1562ac6
--- /dev/null
+++ b/part_4/ex17/db/ex17.(2).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(2).cnf.hdb b/part_4/ex17/db/ex17.(2).cnf.hdb
new file mode 100755
index 0000000..19c0e6a
--- /dev/null
+++ b/part_4/ex17/db/ex17.(2).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(3).cnf.cdb b/part_4/ex17/db/ex17.(3).cnf.cdb
new file mode 100755
index 0000000..d4817e6
--- /dev/null
+++ b/part_4/ex17/db/ex17.(3).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(3).cnf.hdb b/part_4/ex17/db/ex17.(3).cnf.hdb
new file mode 100755
index 0000000..a38cc1e
--- /dev/null
+++ b/part_4/ex17/db/ex17.(3).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(4).cnf.cdb b/part_4/ex17/db/ex17.(4).cnf.cdb
new file mode 100755
index 0000000..2eecdb0
--- /dev/null
+++ b/part_4/ex17/db/ex17.(4).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(4).cnf.hdb b/part_4/ex17/db/ex17.(4).cnf.hdb
new file mode 100755
index 0000000..a2a248c
--- /dev/null
+++ b/part_4/ex17/db/ex17.(4).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(5).cnf.cdb b/part_4/ex17/db/ex17.(5).cnf.cdb
new file mode 100755
index 0000000..81cf669
--- /dev/null
+++ b/part_4/ex17/db/ex17.(5).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(5).cnf.hdb b/part_4/ex17/db/ex17.(5).cnf.hdb
new file mode 100755
index 0000000..21b93dd
--- /dev/null
+++ b/part_4/ex17/db/ex17.(5).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(6).cnf.cdb b/part_4/ex17/db/ex17.(6).cnf.cdb
new file mode 100755
index 0000000..74baf8a
--- /dev/null
+++ b/part_4/ex17/db/ex17.(6).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(6).cnf.hdb b/part_4/ex17/db/ex17.(6).cnf.hdb
new file mode 100755
index 0000000..b7f263f
--- /dev/null
+++ b/part_4/ex17/db/ex17.(6).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(7).cnf.cdb b/part_4/ex17/db/ex17.(7).cnf.cdb
new file mode 100755
index 0000000..d96aaf6
--- /dev/null
+++ b/part_4/ex17/db/ex17.(7).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(7).cnf.hdb b/part_4/ex17/db/ex17.(7).cnf.hdb
new file mode 100755
index 0000000..42287e3
--- /dev/null
+++ b/part_4/ex17/db/ex17.(7).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(8).cnf.cdb b/part_4/ex17/db/ex17.(8).cnf.cdb
new file mode 100755
index 0000000..8016e59
--- /dev/null
+++ b/part_4/ex17/db/ex17.(8).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(8).cnf.hdb b/part_4/ex17/db/ex17.(8).cnf.hdb
new file mode 100755
index 0000000..0943ac7
--- /dev/null
+++ b/part_4/ex17/db/ex17.(8).cnf.hdb
diff --git a/part_4/ex17/db/ex17.(9).cnf.cdb b/part_4/ex17/db/ex17.(9).cnf.cdb
new file mode 100755
index 0000000..50e40c6
--- /dev/null
+++ b/part_4/ex17/db/ex17.(9).cnf.cdb
diff --git a/part_4/ex17/db/ex17.(9).cnf.hdb b/part_4/ex17/db/ex17.(9).cnf.hdb
new file mode 100755
index 0000000..bca6fbd
--- /dev/null
+++ b/part_4/ex17/db/ex17.(9).cnf.hdb
diff --git a/part_2/ex9_final/db/ex9.asm.qmsg b/part_4/ex17/db/ex17.asm.qmsg
index 7acd89c..3ecd030 100755
--- a/part_2/ex9_final/db/ex9.asm.qmsg
+++ b/part_4/ex17/db/ex17.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480075862814 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480075862816 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 25 12:11:02 2016 " "Processing started: Fri Nov 25 12:11:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480075862816 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480075862816 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480075862816 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480075863791 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480075868447 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "895 " "Peak virtual memory: 895 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480075868793 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 25 12:11:08 2016 " "Processing ended: Fri Nov 25 12:11:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480075868793 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480075868793 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480075868793 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480075868793 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480677450146 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480677450148 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:17:29 2016 " "Processing started: Fri Dec 02 11:17:29 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480677450148 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480677450148 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex17 -c ex17 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex17 -c ex17" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480677450149 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480677450965 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480677455590 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "894 " "Peak virtual memory: 894 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480677455934 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:17:35 2016 " "Processing ended: Fri Dec 02 11:17:35 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480677455934 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480677455934 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480677455934 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480677455934 ""}
diff --git a/part_4/ex17/db/ex17.asm.rdb b/part_4/ex17/db/ex17.asm.rdb
new file mode 100755
index 0000000..2f5202f
--- /dev/null
+++ b/part_4/ex17/db/ex17.asm.rdb
diff --git a/part_2/ex9_partially_working/db/ex9.cbx.xml b/part_4/ex17/db/ex17.cbx.xml
index 9156ad4..26aa7a0 100755
--- a/part_2/ex9_partially_working/db/ex9.cbx.xml
+++ b/part_4/ex17/db/ex17.cbx.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" ?>
 <LOG_ROOT>
-	<PROJECT NAME="ex9">
+	<PROJECT NAME="ex17">
 	</PROJECT>
 </LOG_ROOT>
diff --git a/part_4/ex17/db/ex17.cmp.ammdb b/part_4/ex17/db/ex17.cmp.ammdb
new file mode 100755
index 0000000..f3a91d0
--- /dev/null
+++ b/part_4/ex17/db/ex17.cmp.ammdb
diff --git a/part_4/ex17/db/ex17.cmp.bpm b/part_4/ex17/db/ex17.cmp.bpm
new file mode 100755
index 0000000..e66155d
--- /dev/null
+++ b/part_4/ex17/db/ex17.cmp.bpm
diff --git a/part_4/ex17/db/ex17.cmp.cdb b/part_4/ex17/db/ex17.cmp.cdb
new file mode 100755
index 0000000..79b78ea
--- /dev/null
+++ b/part_4/ex17/db/ex17.cmp.cdb
diff --git a/part_4/ex17/db/ex17.cmp.hdb b/part_4/ex17/db/ex17.cmp.hdb
new file mode 100755
index 0000000..4f96ed4
--- /dev/null
+++ b/part_4/ex17/db/ex17.cmp.hdb
diff --git a/part_4/ex17/db/ex17.cmp.idb b/part_4/ex17/db/ex17.cmp.idb
new file mode 100755
index 0000000..e879e66
--- /dev/null
+++ b/part_4/ex17/db/ex17.cmp.idb
diff --git a/part_4/ex17/db/ex17.cmp.logdb b/part_4/ex17/db/ex17.cmp.logdb
new file mode 100755
index 0000000..e044ed7
--- /dev/null
+++ b/part_4/ex17/db/ex17.cmp.logdb
@@ -0,0 +1,80 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,41;0;41;0;0;41;41;0;41;41;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;41;0;41;41;0;0;41;0;0;41;41;41;41;41;41;41;41;41;41;41;41;41;41;41;41;41;41,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_LD,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PWM_OUT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDO,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_4/ex17/db/ex17.cmp.rdb b/part_4/ex17/db/ex17.cmp.rdb
new file mode 100755
index 0000000..4a17648
--- /dev/null
+++ b/part_4/ex17/db/ex17.cmp.rdb
diff --git a/part_4/ex17/db/ex17.cmp_merge.kpt b/part_4/ex17/db/ex17.cmp_merge.kpt
new file mode 100755
index 0000000..9e3663b
--- /dev/null
+++ b/part_4/ex17/db/ex17.cmp_merge.kpt
diff --git a/part_4/ex17/db/ex17.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_4/ex17/db/ex17.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..da61997
--- /dev/null
+++ b/part_4/ex17/db/ex17.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_4/ex17/db/ex17.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_4/ex17/db/ex17.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_4/ex17/db/ex17.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_4/ex17/db/ex17.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_4/ex17/db/ex17.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_4/ex17/db/ex17.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_4/ex17/db/ex17.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_4/ex17/db/ex17.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..acc52a8
--- /dev/null
+++ b/part_4/ex17/db/ex17.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_4/ex17/db/ex17.db_info b/part_4/ex17/db/ex17.db_info
new file mode 100755
index 0000000..25e33b3
--- /dev/null
+++ b/part_4/ex17/db/ex17.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Dec 02 09:42:26 2016
diff --git a/part_4/ex17/db/ex17.fit.qmsg b/part_4/ex17/db/ex17.fit.qmsg
new file mode 100755
index 0000000..814a618
--- /dev/null
+++ b/part_4/ex17/db/ex17.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480677412879 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480677412879 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex17 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex17\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480677413126 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480677413175 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480677413175 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480677413567 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480677413710 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480677413717 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480677423809 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 118 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 118 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480677423898 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480677423898 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677423899 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480677423903 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480677423904 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480677423905 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480677423906 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480677423906 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480677423907 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex17.sdc " "Synopsys Design Constraints File file not found: 'ex17.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480677424732 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480677424732 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480677424737 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480677424738 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480677424738 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480677424760 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480677424761 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480677424761 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1480677424803 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1480677424803 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677424805 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480677429746 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480677429963 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677430887 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480677431999 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480677433470 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677433470 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480677434749 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "7 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex17/" { { 1 { 0 "Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480677439524 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480677439524 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480677443151 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480677443151 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677443155 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.83 " "Total time spent on timing analysis during the Fitter is 0.83 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480677444551 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480677444591 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480677445047 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480677445047 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480677445489 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677447996 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1480677448242 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex17/output_files/ex17.fit.smsg " "Generated suppressed messages file C:/New folder/ex17/output_files/ex17.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480677448304 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 45 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 45 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2765 " "Peak virtual memory: 2765 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480677448776 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:17:28 2016 " "Processing ended: Fri Dec 02 11:17:28 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480677448776 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Elapsed time: 00:00:37" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480677448776 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:06 " "Total CPU time (on all processors): 00:01:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480677448776 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480677448776 ""}
diff --git a/part_4/ex17/db/ex17.hier_info b/part_4/ex17/db/ex17.hier_info
new file mode 100755
index 0000000..f5a83a9
--- /dev/null
+++ b/part_4/ex17/db/ex17.hier_info
@@ -0,0 +1,932 @@
+|ex17
+CLOCK_50 => CLOCK_50.IN5
+SW[0] => ~NO_FANOUT~
+SW[1] => ~NO_FANOUT~
+SW[2] => ~NO_FANOUT~
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => ~NO_FANOUT~
+SW[8] => ~NO_FANOUT~
+SW[9] => ~NO_FANOUT~
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+DAC_SDI << spi2dac:SPI_DAC.port3
+DAC_SCK << spi2dac:SPI_DAC.port5
+DAC_CS << spi2dac:SPI_DAC.port4
+DAC_LD << spi2dac:SPI_DAC.port6
+ADC_SDI << spi2adc:SPI_ADC.sdata_to_adc
+ADC_SCK << spi2adc:SPI_ADC.adc_sck
+ADC_CS << spi2adc:SPI_ADC.adc_cs
+ADC_SDO => ADC_SDO.IN1
+PWM_OUT << pwm:PWM_DC.port3
+
+
+|ex17|clktick_16:GEN_10K
+clkin => count[0].CLK
+clkin => count[1].CLK
+clkin => count[2].CLK
+clkin => count[3].CLK
+clkin => count[4].CLK
+clkin => count[5].CLK
+clkin => count[6].CLK
+clkin => count[7].CLK
+clkin => count[8].CLK
+clkin => count[9].CLK
+clkin => count[10].CLK
+clkin => count[11].CLK
+clkin => count[12].CLK
+clkin => count[13].CLK
+clkin => count[14].CLK
+clkin => count[15].CLK
+clkin => tick~reg0.CLK
+enable => count[0].ENA
+enable => count[1].ENA
+enable => count[2].ENA
+enable => count[3].ENA
+enable => count[4].ENA
+enable => count[5].ENA
+enable => count[6].ENA
+enable => count[7].ENA
+enable => count[8].ENA
+enable => count[9].ENA
+enable => count[10].ENA
+enable => count[11].ENA
+enable => count[12].ENA
+enable => count[13].ENA
+enable => count[14].ENA
+enable => count[15].ENA
+enable => tick~reg0.ENA
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => count.DATAB
+N[8] => count.DATAB
+N[9] => count.DATAB
+N[10] => count.DATAB
+N[11] => count.DATAB
+N[12] => count.DATAB
+N[13] => count.DATAB
+N[14] => count.DATAB
+N[15] => count.DATAB
+tick <= tick~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex17|spi2dac:SPI_DAC
+clk => dac_start.CLK
+clk => clk_1MHz.CLK
+clk => ctr[0].CLK
+clk => ctr[1].CLK
+clk => ctr[2].CLK
+clk => ctr[3].CLK
+clk => ctr[4].CLK
+clk => sr_state~1.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => Selector1.IN1
+load => dac_start.OUTPUTSELECT
+load => Selector0.IN1
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= dac_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= dac_ld~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex17|pwm:PWM_DC
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex17|spi2adc:SPI_ADC
+sysclk => adc_start.CLK
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~1.DATAIN
+start => Selector1.IN1
+start => adc_start.OUTPUTSELECT
+start => Selector0.IN1
+channel => Selector6.IN6
+data_from_adc[0] <= data_from_adc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[1] <= data_from_adc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[2] <= data_from_adc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[3] <= data_from_adc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[4] <= data_from_adc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[5] <= data_from_adc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[6] <= data_from_adc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[7] <= data_from_adc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[8] <= data_from_adc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[9] <= data_from_adc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+sdata_to_adc <= adc_din.DB_MAX_OUTPUT_PORT_TYPE
+adc_cs <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+adc_sck <= adc_sck.DB_MAX_OUTPUT_PORT_TYPE
+sdata_from_adc => shift_reg[0].DATAIN
+
+
+|ex17|processor:ALLPASS
+sysclk => sysclk.IN1
+tick => tick.IN2
+data_in[0] => Add0.IN20
+data_in[1] => Add0.IN19
+data_in[2] => Add0.IN18
+data_in[3] => Add0.IN17
+data_in[4] => Add0.IN16
+data_in[5] => Add0.IN15
+data_in[6] => Add0.IN14
+data_in[7] => Add0.IN13
+data_in[8] => Add0.IN12
+data_in[9] => Add0.IN11
+data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex17|processor:ALLPASS|FIFO:fifo
+clock => clock.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+rdreq => rdreq.IN1
+wrreq => wrreq.IN1
+full <= scfifo:scfifo_component.full
+q[0] <= scfifo:scfifo_component.q
+q[1] <= scfifo:scfifo_component.q
+q[2] <= scfifo:scfifo_component.q
+q[3] <= scfifo:scfifo_component.q
+q[4] <= scfifo:scfifo_component.q
+q[5] <= scfifo:scfifo_component.q
+q[6] <= scfifo:scfifo_component.q
+q[7] <= scfifo:scfifo_component.q
+q[8] <= scfifo:scfifo_component.q
+q[9] <= scfifo:scfifo_component.q
+
+
+|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component
+data[0] => scfifo_4l81:auto_generated.data[0]
+data[1] => scfifo_4l81:auto_generated.data[1]
+data[2] => scfifo_4l81:auto_generated.data[2]
+data[3] => scfifo_4l81:auto_generated.data[3]
+data[4] => scfifo_4l81:auto_generated.data[4]
+data[5] => scfifo_4l81:auto_generated.data[5]
+data[6] => scfifo_4l81:auto_generated.data[6]
+data[7] => scfifo_4l81:auto_generated.data[7]
+data[8] => scfifo_4l81:auto_generated.data[8]
+data[9] => scfifo_4l81:auto_generated.data[9]
+q[0] <= scfifo_4l81:auto_generated.q[0]
+q[1] <= scfifo_4l81:auto_generated.q[1]
+q[2] <= scfifo_4l81:auto_generated.q[2]
+q[3] <= scfifo_4l81:auto_generated.q[3]
+q[4] <= scfifo_4l81:auto_generated.q[4]
+q[5] <= scfifo_4l81:auto_generated.q[5]
+q[6] <= scfifo_4l81:auto_generated.q[6]
+q[7] <= scfifo_4l81:auto_generated.q[7]
+q[8] <= scfifo_4l81:auto_generated.q[8]
+q[9] <= scfifo_4l81:auto_generated.q[9]
+wrreq => scfifo_4l81:auto_generated.wrreq
+rdreq => scfifo_4l81:auto_generated.rdreq
+clock => scfifo_4l81:auto_generated.clock
+aclr => ~NO_FANOUT~
+sclr => ~NO_FANOUT~
+eccstatus[0] <= <UNC>
+eccstatus[1] <= <UNC>
+empty <= <GND>
+full <= scfifo_4l81:auto_generated.full
+almost_full <= <GND>
+almost_empty <= <GND>
+usedw[0] <= <GND>
+usedw[1] <= <GND>
+usedw[2] <= <GND>
+usedw[3] <= <GND>
+usedw[4] <= <GND>
+usedw[5] <= <GND>
+usedw[6] <= <GND>
+usedw[7] <= <GND>
+usedw[8] <= <GND>
+usedw[9] <= <GND>
+usedw[10] <= <GND>
+usedw[11] <= <GND>
+usedw[12] <= <GND>
+
+
+|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated
+clock => a_dpfifo_br81:dpfifo.clock
+data[0] => a_dpfifo_br81:dpfifo.data[0]
+data[1] => a_dpfifo_br81:dpfifo.data[1]
+data[2] => a_dpfifo_br81:dpfifo.data[2]
+data[3] => a_dpfifo_br81:dpfifo.data[3]
+data[4] => a_dpfifo_br81:dpfifo.data[4]
+data[5] => a_dpfifo_br81:dpfifo.data[5]
+data[6] => a_dpfifo_br81:dpfifo.data[6]
+data[7] => a_dpfifo_br81:dpfifo.data[7]
+data[8] => a_dpfifo_br81:dpfifo.data[8]
+data[9] => a_dpfifo_br81:dpfifo.data[9]
+full <= a_dpfifo_br81:dpfifo.full
+q[0] <= a_dpfifo_br81:dpfifo.q[0]
+q[1] <= a_dpfifo_br81:dpfifo.q[1]
+q[2] <= a_dpfifo_br81:dpfifo.q[2]
+q[3] <= a_dpfifo_br81:dpfifo.q[3]
+q[4] <= a_dpfifo_br81:dpfifo.q[4]
+q[5] <= a_dpfifo_br81:dpfifo.q[5]
+q[6] <= a_dpfifo_br81:dpfifo.q[6]
+q[7] <= a_dpfifo_br81:dpfifo.q[7]
+q[8] <= a_dpfifo_br81:dpfifo.q[8]
+q[9] <= a_dpfifo_br81:dpfifo.q[9]
+rdreq => a_dpfifo_br81:dpfifo.rreq
+wrreq => a_dpfifo_br81:dpfifo.wreq
+
+
+|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo
+clock => a_fefifo_4be:fifo_state.clock
+clock => altsyncram_44t1:FIFOram.clock0
+clock => altsyncram_44t1:FIFOram.clock1
+clock => cntr_1ib:rd_ptr_count.clock
+clock => cntr_1ib:wr_ptr.clock
+data[0] => altsyncram_44t1:FIFOram.data_a[0]
+data[1] => altsyncram_44t1:FIFOram.data_a[1]
+data[2] => altsyncram_44t1:FIFOram.data_a[2]
+data[3] => altsyncram_44t1:FIFOram.data_a[3]
+data[4] => altsyncram_44t1:FIFOram.data_a[4]
+data[5] => altsyncram_44t1:FIFOram.data_a[5]
+data[6] => altsyncram_44t1:FIFOram.data_a[6]
+data[7] => altsyncram_44t1:FIFOram.data_a[7]
+data[8] => altsyncram_44t1:FIFOram.data_a[8]
+data[9] => altsyncram_44t1:FIFOram.data_a[9]
+full <= a_fefifo_4be:fifo_state.full
+q[0] <= altsyncram_44t1:FIFOram.q_b[0]
+q[1] <= altsyncram_44t1:FIFOram.q_b[1]
+q[2] <= altsyncram_44t1:FIFOram.q_b[2]
+q[3] <= altsyncram_44t1:FIFOram.q_b[3]
+q[4] <= altsyncram_44t1:FIFOram.q_b[4]
+q[5] <= altsyncram_44t1:FIFOram.q_b[5]
+q[6] <= altsyncram_44t1:FIFOram.q_b[6]
+q[7] <= altsyncram_44t1:FIFOram.q_b[7]
+q[8] <= altsyncram_44t1:FIFOram.q_b[8]
+q[9] <= altsyncram_44t1:FIFOram.q_b[9]
+rreq => a_fefifo_4be:fifo_state.rreq
+rreq => valid_rreq.IN0
+sclr => a_fefifo_4be:fifo_state.sclr
+sclr => _.IN0
+sclr => _.IN1
+sclr => cntr_1ib:rd_ptr_count.sclr
+sclr => cntr_1ib:wr_ptr.sclr
+wreq => a_fefifo_4be:fifo_state.wreq
+wreq => valid_wreq.IN0
+
+
+|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state
+aclr => b_full.IN0
+aclr => b_non_empty.IN0
+aclr => cntr_di7:count_usedw.aclr
+clock => cntr_di7:count_usedw.clock
+clock => b_full.CLK
+clock => b_non_empty.CLK
+empty <= empty.DB_MAX_OUTPUT_PORT_TYPE
+full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
+rreq => _.IN1
+rreq => _.IN0
+rreq => _.IN1
+rreq => valid_rreq.IN0
+sclr => _.IN0
+sclr => _.IN0
+sclr => _.IN1
+sclr => _.IN0
+sclr => _.IN0
+sclr => cntr_di7:count_usedw.sclr
+wreq => _.IN1
+wreq => _.IN1
+wreq => _.IN0
+wreq => valid_wreq.IN0
+
+
+|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw
+aclr => counter_reg_bit[12].IN0
+clock => counter_reg_bit[12].CLK
+clock => counter_reg_bit[11].CLK
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+cnt_en => _.IN0
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+q[11] <= counter_reg_bit[11].DB_MAX_OUTPUT_PORT_TYPE
+q[12] <= counter_reg_bit[12].DB_MAX_OUTPUT_PORT_TYPE
+sclr => _.IN1
+sclr => counter_reg_bit[12].SCLR
+sclr => counter_reg_bit[11].SCLR
+sclr => counter_reg_bit[10].SCLR
+sclr => counter_reg_bit[9].SCLR
+sclr => counter_reg_bit[8].SCLR
+sclr => counter_reg_bit[7].SCLR
+sclr => counter_reg_bit[6].SCLR
+sclr => counter_reg_bit[5].SCLR
+sclr => counter_reg_bit[4].SCLR
+sclr => counter_reg_bit[3].SCLR
+sclr => counter_reg_bit[2].SCLR
+sclr => counter_reg_bit[1].SCLR
+sclr => counter_reg_bit[0].SCLR
+updown => updown_other_bits.IN1
+updown => counter_comb_bita0.DATAF
+
+
+|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram
+address_a[0] => ram_block1a0.PORTAADDR
+address_a[0] => ram_block1a1.PORTAADDR
+address_a[0] => ram_block1a2.PORTAADDR
+address_a[0] => ram_block1a3.PORTAADDR
+address_a[0] => ram_block1a4.PORTAADDR
+address_a[0] => ram_block1a5.PORTAADDR
+address_a[0] => ram_block1a6.PORTAADDR
+address_a[0] => ram_block1a7.PORTAADDR
+address_a[0] => ram_block1a8.PORTAADDR
+address_a[0] => ram_block1a9.PORTAADDR
+address_a[1] => ram_block1a0.PORTAADDR1
+address_a[1] => ram_block1a1.PORTAADDR1
+address_a[1] => ram_block1a2.PORTAADDR1
+address_a[1] => ram_block1a3.PORTAADDR1
+address_a[1] => ram_block1a4.PORTAADDR1
+address_a[1] => ram_block1a5.PORTAADDR1
+address_a[1] => ram_block1a6.PORTAADDR1
+address_a[1] => ram_block1a7.PORTAADDR1
+address_a[1] => ram_block1a8.PORTAADDR1
+address_a[1] => ram_block1a9.PORTAADDR1
+address_a[2] => ram_block1a0.PORTAADDR2
+address_a[2] => ram_block1a1.PORTAADDR2
+address_a[2] => ram_block1a2.PORTAADDR2
+address_a[2] => ram_block1a3.PORTAADDR2
+address_a[2] => ram_block1a4.PORTAADDR2
+address_a[2] => ram_block1a5.PORTAADDR2
+address_a[2] => ram_block1a6.PORTAADDR2
+address_a[2] => ram_block1a7.PORTAADDR2
+address_a[2] => ram_block1a8.PORTAADDR2
+address_a[2] => ram_block1a9.PORTAADDR2
+address_a[3] => ram_block1a0.PORTAADDR3
+address_a[3] => ram_block1a1.PORTAADDR3
+address_a[3] => ram_block1a2.PORTAADDR3
+address_a[3] => ram_block1a3.PORTAADDR3
+address_a[3] => ram_block1a4.PORTAADDR3
+address_a[3] => ram_block1a5.PORTAADDR3
+address_a[3] => ram_block1a6.PORTAADDR3
+address_a[3] => ram_block1a7.PORTAADDR3
+address_a[3] => ram_block1a8.PORTAADDR3
+address_a[3] => ram_block1a9.PORTAADDR3
+address_a[4] => ram_block1a0.PORTAADDR4
+address_a[4] => ram_block1a1.PORTAADDR4
+address_a[4] => ram_block1a2.PORTAADDR4
+address_a[4] => ram_block1a3.PORTAADDR4
+address_a[4] => ram_block1a4.PORTAADDR4
+address_a[4] => ram_block1a5.PORTAADDR4
+address_a[4] => ram_block1a6.PORTAADDR4
+address_a[4] => ram_block1a7.PORTAADDR4
+address_a[4] => ram_block1a8.PORTAADDR4
+address_a[4] => ram_block1a9.PORTAADDR4
+address_a[5] => ram_block1a0.PORTAADDR5
+address_a[5] => ram_block1a1.PORTAADDR5
+address_a[5] => ram_block1a2.PORTAADDR5
+address_a[5] => ram_block1a3.PORTAADDR5
+address_a[5] => ram_block1a4.PORTAADDR5
+address_a[5] => ram_block1a5.PORTAADDR5
+address_a[5] => ram_block1a6.PORTAADDR5
+address_a[5] => ram_block1a7.PORTAADDR5
+address_a[5] => ram_block1a8.PORTAADDR5
+address_a[5] => ram_block1a9.PORTAADDR5
+address_a[6] => ram_block1a0.PORTAADDR6
+address_a[6] => ram_block1a1.PORTAADDR6
+address_a[6] => ram_block1a2.PORTAADDR6
+address_a[6] => ram_block1a3.PORTAADDR6
+address_a[6] => ram_block1a4.PORTAADDR6
+address_a[6] => ram_block1a5.PORTAADDR6
+address_a[6] => ram_block1a6.PORTAADDR6
+address_a[6] => ram_block1a7.PORTAADDR6
+address_a[6] => ram_block1a8.PORTAADDR6
+address_a[6] => ram_block1a9.PORTAADDR6
+address_a[7] => ram_block1a0.PORTAADDR7
+address_a[7] => ram_block1a1.PORTAADDR7
+address_a[7] => ram_block1a2.PORTAADDR7
+address_a[7] => ram_block1a3.PORTAADDR7
+address_a[7] => ram_block1a4.PORTAADDR7
+address_a[7] => ram_block1a5.PORTAADDR7
+address_a[7] => ram_block1a6.PORTAADDR7
+address_a[7] => ram_block1a7.PORTAADDR7
+address_a[7] => ram_block1a8.PORTAADDR7
+address_a[7] => ram_block1a9.PORTAADDR7
+address_a[8] => ram_block1a0.PORTAADDR8
+address_a[8] => ram_block1a1.PORTAADDR8
+address_a[8] => ram_block1a2.PORTAADDR8
+address_a[8] => ram_block1a3.PORTAADDR8
+address_a[8] => ram_block1a4.PORTAADDR8
+address_a[8] => ram_block1a5.PORTAADDR8
+address_a[8] => ram_block1a6.PORTAADDR8
+address_a[8] => ram_block1a7.PORTAADDR8
+address_a[8] => ram_block1a8.PORTAADDR8
+address_a[8] => ram_block1a9.PORTAADDR8
+address_a[9] => ram_block1a0.PORTAADDR9
+address_a[9] => ram_block1a1.PORTAADDR9
+address_a[9] => ram_block1a2.PORTAADDR9
+address_a[9] => ram_block1a3.PORTAADDR9
+address_a[9] => ram_block1a4.PORTAADDR9
+address_a[9] => ram_block1a5.PORTAADDR9
+address_a[9] => ram_block1a6.PORTAADDR9
+address_a[9] => ram_block1a7.PORTAADDR9
+address_a[9] => ram_block1a8.PORTAADDR9
+address_a[9] => ram_block1a9.PORTAADDR9
+address_a[10] => ram_block1a0.PORTAADDR10
+address_a[10] => ram_block1a1.PORTAADDR10
+address_a[10] => ram_block1a2.PORTAADDR10
+address_a[10] => ram_block1a3.PORTAADDR10
+address_a[10] => ram_block1a4.PORTAADDR10
+address_a[10] => ram_block1a5.PORTAADDR10
+address_a[10] => ram_block1a6.PORTAADDR10
+address_a[10] => ram_block1a7.PORTAADDR10
+address_a[10] => ram_block1a8.PORTAADDR10
+address_a[10] => ram_block1a9.PORTAADDR10
+address_a[11] => ram_block1a0.PORTAADDR11
+address_a[11] => ram_block1a1.PORTAADDR11
+address_a[11] => ram_block1a2.PORTAADDR11
+address_a[11] => ram_block1a3.PORTAADDR11
+address_a[11] => ram_block1a4.PORTAADDR11
+address_a[11] => ram_block1a5.PORTAADDR11
+address_a[11] => ram_block1a6.PORTAADDR11
+address_a[11] => ram_block1a7.PORTAADDR11
+address_a[11] => ram_block1a8.PORTAADDR11
+address_a[11] => ram_block1a9.PORTAADDR11
+address_a[12] => ram_block1a0.PORTAADDR12
+address_a[12] => ram_block1a1.PORTAADDR12
+address_a[12] => ram_block1a2.PORTAADDR12
+address_a[12] => ram_block1a3.PORTAADDR12
+address_a[12] => ram_block1a4.PORTAADDR12
+address_a[12] => ram_block1a5.PORTAADDR12
+address_a[12] => ram_block1a6.PORTAADDR12
+address_a[12] => ram_block1a7.PORTAADDR12
+address_a[12] => ram_block1a8.PORTAADDR12
+address_a[12] => ram_block1a9.PORTAADDR12
+address_b[0] => ram_block1a0.PORTBADDR
+address_b[0] => ram_block1a1.PORTBADDR
+address_b[0] => ram_block1a2.PORTBADDR
+address_b[0] => ram_block1a3.PORTBADDR
+address_b[0] => ram_block1a4.PORTBADDR
+address_b[0] => ram_block1a5.PORTBADDR
+address_b[0] => ram_block1a6.PORTBADDR
+address_b[0] => ram_block1a7.PORTBADDR
+address_b[0] => ram_block1a8.PORTBADDR
+address_b[0] => ram_block1a9.PORTBADDR
+address_b[1] => ram_block1a0.PORTBADDR1
+address_b[1] => ram_block1a1.PORTBADDR1
+address_b[1] => ram_block1a2.PORTBADDR1
+address_b[1] => ram_block1a3.PORTBADDR1
+address_b[1] => ram_block1a4.PORTBADDR1
+address_b[1] => ram_block1a5.PORTBADDR1
+address_b[1] => ram_block1a6.PORTBADDR1
+address_b[1] => ram_block1a7.PORTBADDR1
+address_b[1] => ram_block1a8.PORTBADDR1
+address_b[1] => ram_block1a9.PORTBADDR1
+address_b[2] => ram_block1a0.PORTBADDR2
+address_b[2] => ram_block1a1.PORTBADDR2
+address_b[2] => ram_block1a2.PORTBADDR2
+address_b[2] => ram_block1a3.PORTBADDR2
+address_b[2] => ram_block1a4.PORTBADDR2
+address_b[2] => ram_block1a5.PORTBADDR2
+address_b[2] => ram_block1a6.PORTBADDR2
+address_b[2] => ram_block1a7.PORTBADDR2
+address_b[2] => ram_block1a8.PORTBADDR2
+address_b[2] => ram_block1a9.PORTBADDR2
+address_b[3] => ram_block1a0.PORTBADDR3
+address_b[3] => ram_block1a1.PORTBADDR3
+address_b[3] => ram_block1a2.PORTBADDR3
+address_b[3] => ram_block1a3.PORTBADDR3
+address_b[3] => ram_block1a4.PORTBADDR3
+address_b[3] => ram_block1a5.PORTBADDR3
+address_b[3] => ram_block1a6.PORTBADDR3
+address_b[3] => ram_block1a7.PORTBADDR3
+address_b[3] => ram_block1a8.PORTBADDR3
+address_b[3] => ram_block1a9.PORTBADDR3
+address_b[4] => ram_block1a0.PORTBADDR4
+address_b[4] => ram_block1a1.PORTBADDR4
+address_b[4] => ram_block1a2.PORTBADDR4
+address_b[4] => ram_block1a3.PORTBADDR4
+address_b[4] => ram_block1a4.PORTBADDR4
+address_b[4] => ram_block1a5.PORTBADDR4
+address_b[4] => ram_block1a6.PORTBADDR4
+address_b[4] => ram_block1a7.PORTBADDR4
+address_b[4] => ram_block1a8.PORTBADDR4
+address_b[4] => ram_block1a9.PORTBADDR4
+address_b[5] => ram_block1a0.PORTBADDR5
+address_b[5] => ram_block1a1.PORTBADDR5
+address_b[5] => ram_block1a2.PORTBADDR5
+address_b[5] => ram_block1a3.PORTBADDR5
+address_b[5] => ram_block1a4.PORTBADDR5
+address_b[5] => ram_block1a5.PORTBADDR5
+address_b[5] => ram_block1a6.PORTBADDR5
+address_b[5] => ram_block1a7.PORTBADDR5
+address_b[5] => ram_block1a8.PORTBADDR5
+address_b[5] => ram_block1a9.PORTBADDR5
+address_b[6] => ram_block1a0.PORTBADDR6
+address_b[6] => ram_block1a1.PORTBADDR6
+address_b[6] => ram_block1a2.PORTBADDR6
+address_b[6] => ram_block1a3.PORTBADDR6
+address_b[6] => ram_block1a4.PORTBADDR6
+address_b[6] => ram_block1a5.PORTBADDR6
+address_b[6] => ram_block1a6.PORTBADDR6
+address_b[6] => ram_block1a7.PORTBADDR6
+address_b[6] => ram_block1a8.PORTBADDR6
+address_b[6] => ram_block1a9.PORTBADDR6
+address_b[7] => ram_block1a0.PORTBADDR7
+address_b[7] => ram_block1a1.PORTBADDR7
+address_b[7] => ram_block1a2.PORTBADDR7
+address_b[7] => ram_block1a3.PORTBADDR7
+address_b[7] => ram_block1a4.PORTBADDR7
+address_b[7] => ram_block1a5.PORTBADDR7
+address_b[7] => ram_block1a6.PORTBADDR7
+address_b[7] => ram_block1a7.PORTBADDR7
+address_b[7] => ram_block1a8.PORTBADDR7
+address_b[7] => ram_block1a9.PORTBADDR7
+address_b[8] => ram_block1a0.PORTBADDR8
+address_b[8] => ram_block1a1.PORTBADDR8
+address_b[8] => ram_block1a2.PORTBADDR8
+address_b[8] => ram_block1a3.PORTBADDR8
+address_b[8] => ram_block1a4.PORTBADDR8
+address_b[8] => ram_block1a5.PORTBADDR8
+address_b[8] => ram_block1a6.PORTBADDR8
+address_b[8] => ram_block1a7.PORTBADDR8
+address_b[8] => ram_block1a8.PORTBADDR8
+address_b[8] => ram_block1a9.PORTBADDR8
+address_b[9] => ram_block1a0.PORTBADDR9
+address_b[9] => ram_block1a1.PORTBADDR9
+address_b[9] => ram_block1a2.PORTBADDR9
+address_b[9] => ram_block1a3.PORTBADDR9
+address_b[9] => ram_block1a4.PORTBADDR9
+address_b[9] => ram_block1a5.PORTBADDR9
+address_b[9] => ram_block1a6.PORTBADDR9
+address_b[9] => ram_block1a7.PORTBADDR9
+address_b[9] => ram_block1a8.PORTBADDR9
+address_b[9] => ram_block1a9.PORTBADDR9
+address_b[10] => ram_block1a0.PORTBADDR10
+address_b[10] => ram_block1a1.PORTBADDR10
+address_b[10] => ram_block1a2.PORTBADDR10
+address_b[10] => ram_block1a3.PORTBADDR10
+address_b[10] => ram_block1a4.PORTBADDR10
+address_b[10] => ram_block1a5.PORTBADDR10
+address_b[10] => ram_block1a6.PORTBADDR10
+address_b[10] => ram_block1a7.PORTBADDR10
+address_b[10] => ram_block1a8.PORTBADDR10
+address_b[10] => ram_block1a9.PORTBADDR10
+address_b[11] => ram_block1a0.PORTBADDR11
+address_b[11] => ram_block1a1.PORTBADDR11
+address_b[11] => ram_block1a2.PORTBADDR11
+address_b[11] => ram_block1a3.PORTBADDR11
+address_b[11] => ram_block1a4.PORTBADDR11
+address_b[11] => ram_block1a5.PORTBADDR11
+address_b[11] => ram_block1a6.PORTBADDR11
+address_b[11] => ram_block1a7.PORTBADDR11
+address_b[11] => ram_block1a8.PORTBADDR11
+address_b[11] => ram_block1a9.PORTBADDR11
+address_b[12] => ram_block1a0.PORTBADDR12
+address_b[12] => ram_block1a1.PORTBADDR12
+address_b[12] => ram_block1a2.PORTBADDR12
+address_b[12] => ram_block1a3.PORTBADDR12
+address_b[12] => ram_block1a4.PORTBADDR12
+address_b[12] => ram_block1a5.PORTBADDR12
+address_b[12] => ram_block1a6.PORTBADDR12
+address_b[12] => ram_block1a7.PORTBADDR12
+address_b[12] => ram_block1a8.PORTBADDR12
+address_b[12] => ram_block1a9.PORTBADDR12
+clock0 => ram_block1a0.CLK0
+clock0 => ram_block1a1.CLK0
+clock0 => ram_block1a2.CLK0
+clock0 => ram_block1a3.CLK0
+clock0 => ram_block1a4.CLK0
+clock0 => ram_block1a5.CLK0
+clock0 => ram_block1a6.CLK0
+clock0 => ram_block1a7.CLK0
+clock0 => ram_block1a8.CLK0
+clock0 => ram_block1a9.CLK0
+clock1 => ram_block1a0.CLK1
+clock1 => ram_block1a1.CLK1
+clock1 => ram_block1a2.CLK1
+clock1 => ram_block1a3.CLK1
+clock1 => ram_block1a4.CLK1
+clock1 => ram_block1a5.CLK1
+clock1 => ram_block1a6.CLK1
+clock1 => ram_block1a7.CLK1
+clock1 => ram_block1a8.CLK1
+clock1 => ram_block1a9.CLK1
+clocken1 => ram_block1a0.ENA1
+clocken1 => ram_block1a1.ENA1
+clocken1 => ram_block1a2.ENA1
+clocken1 => ram_block1a3.ENA1
+clocken1 => ram_block1a4.ENA1
+clocken1 => ram_block1a5.ENA1
+clocken1 => ram_block1a6.ENA1
+clocken1 => ram_block1a7.ENA1
+clocken1 => ram_block1a8.ENA1
+clocken1 => ram_block1a9.ENA1
+data_a[0] => ram_block1a0.PORTADATAIN
+data_a[1] => ram_block1a1.PORTADATAIN
+data_a[2] => ram_block1a2.PORTADATAIN
+data_a[3] => ram_block1a3.PORTADATAIN
+data_a[4] => ram_block1a4.PORTADATAIN
+data_a[5] => ram_block1a5.PORTADATAIN
+data_a[6] => ram_block1a6.PORTADATAIN
+data_a[7] => ram_block1a7.PORTADATAIN
+data_a[8] => ram_block1a8.PORTADATAIN
+data_a[9] => ram_block1a9.PORTADATAIN
+q_b[0] <= ram_block1a0.PORTBDATAOUT
+q_b[1] <= ram_block1a1.PORTBDATAOUT
+q_b[2] <= ram_block1a2.PORTBDATAOUT
+q_b[3] <= ram_block1a3.PORTBDATAOUT
+q_b[4] <= ram_block1a4.PORTBDATAOUT
+q_b[5] <= ram_block1a5.PORTBDATAOUT
+q_b[6] <= ram_block1a6.PORTBDATAOUT
+q_b[7] <= ram_block1a7.PORTBDATAOUT
+q_b[8] <= ram_block1a8.PORTBDATAOUT
+q_b[9] <= ram_block1a9.PORTBDATAOUT
+wren_a => ram_block1a0.PORTAWE
+wren_a => ram_block1a0.ENA0
+wren_a => ram_block1a1.PORTAWE
+wren_a => ram_block1a1.ENA0
+wren_a => ram_block1a2.PORTAWE
+wren_a => ram_block1a2.ENA0
+wren_a => ram_block1a3.PORTAWE
+wren_a => ram_block1a3.ENA0
+wren_a => ram_block1a4.PORTAWE
+wren_a => ram_block1a4.ENA0
+wren_a => ram_block1a5.PORTAWE
+wren_a => ram_block1a5.ENA0
+wren_a => ram_block1a6.PORTAWE
+wren_a => ram_block1a6.ENA0
+wren_a => ram_block1a7.PORTAWE
+wren_a => ram_block1a7.ENA0
+wren_a => ram_block1a8.PORTAWE
+wren_a => ram_block1a8.ENA0
+wren_a => ram_block1a9.PORTAWE
+wren_a => ram_block1a9.ENA0
+
+
+|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:rd_ptr_count
+aclr => counter_reg_bit[12].IN0
+clock => counter_reg_bit[12].CLK
+clock => counter_reg_bit[11].CLK
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+cnt_en => _.IN0
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+q[11] <= counter_reg_bit[11].DB_MAX_OUTPUT_PORT_TYPE
+q[12] <= counter_reg_bit[12].DB_MAX_OUTPUT_PORT_TYPE
+sclr => _.IN1
+sclr => counter_reg_bit[12].SCLR
+sclr => counter_reg_bit[11].SCLR
+sclr => counter_reg_bit[10].SCLR
+sclr => counter_reg_bit[9].SCLR
+sclr => counter_reg_bit[8].SCLR
+sclr => counter_reg_bit[7].SCLR
+sclr => counter_reg_bit[6].SCLR
+sclr => counter_reg_bit[5].SCLR
+sclr => counter_reg_bit[4].SCLR
+sclr => counter_reg_bit[3].SCLR
+sclr => counter_reg_bit[2].SCLR
+sclr => counter_reg_bit[1].SCLR
+sclr => counter_reg_bit[0].SCLR
+
+
+|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:wr_ptr
+aclr => counter_reg_bit[12].IN0
+clock => counter_reg_bit[12].CLK
+clock => counter_reg_bit[11].CLK
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+cnt_en => _.IN0
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+q[11] <= counter_reg_bit[11].DB_MAX_OUTPUT_PORT_TYPE
+q[12] <= counter_reg_bit[12].DB_MAX_OUTPUT_PORT_TYPE
+sclr => _.IN1
+sclr => counter_reg_bit[12].SCLR
+sclr => counter_reg_bit[11].SCLR
+sclr => counter_reg_bit[10].SCLR
+sclr => counter_reg_bit[9].SCLR
+sclr => counter_reg_bit[8].SCLR
+sclr => counter_reg_bit[7].SCLR
+sclr => counter_reg_bit[6].SCLR
+sclr => counter_reg_bit[5].SCLR
+sclr => counter_reg_bit[4].SCLR
+sclr => counter_reg_bit[3].SCLR
+sclr => counter_reg_bit[2].SCLR
+sclr => counter_reg_bit[1].SCLR
+sclr => counter_reg_bit[0].SCLR
+
+
+|ex17|processor:ALLPASS|d_ff:d
+clk => out~reg0.CLK
+in => out~reg0.DATAIN
+out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex17|processor:ALLPASS|div_by_2:comb_5
+in[0] => ~NO_FANOUT~
+in[1] => out[0].DATAIN
+in[2] => out[1].DATAIN
+in[3] => out[2].DATAIN
+in[4] => out[3].DATAIN
+in[5] => out[4].DATAIN
+in[6] => out[5].DATAIN
+in[7] => out[6].DATAIN
+in[8] => out[7].DATAIN
+in[9] => out[8].DATAIN
+in[9] => out[9].DATAIN
+out[0] <= in[1].DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= in[2].DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= in[3].DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= in[4].DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= in[5].DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= in[6].DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= in[7].DB_MAX_OUTPUT_PORT_TYPE
+out[7] <= in[8].DB_MAX_OUTPUT_PORT_TYPE
+out[8] <= in[9].DB_MAX_OUTPUT_PORT_TYPE
+out[9] <= in[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex17|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex17|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex17|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_4/ex17/db/ex17.hif b/part_4/ex17/db/ex17.hif
new file mode 100755
index 0000000..32d6b5b
--- /dev/null
+++ b/part_4/ex17/db/ex17.hif
diff --git a/part_4/ex17/db/ex17.lpc.html b/part_4/ex17/db/ex17.lpc.html
new file mode 100755
index 0000000..e085ae4
--- /dev/null
+++ b/part_4/ex17/db/ex17.lpc.html
@@ -0,0 +1,306 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >7</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|comb_5</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|d</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|wr_ptr</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|FIFOram</TD>
+<TD >40</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|fifo_state</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_ADC</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >14</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >PWM_DC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_DAC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >GEN_10K</TD>
+<TD >18</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >17</TD>
+<TD >1</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_4/ex17/db/ex17.lpc.rdb b/part_4/ex17/db/ex17.lpc.rdb
new file mode 100755
index 0000000..7b6cd1a
--- /dev/null
+++ b/part_4/ex17/db/ex17.lpc.rdb
diff --git a/part_4/ex17/db/ex17.lpc.txt b/part_4/ex17/db/ex17.lpc.txt
new file mode 100755
index 0000000..c8da36d
--- /dev/null
+++ b/part_4/ex17/db/ex17.lpc.txt
@@ -0,0 +1,24 @@
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                                                  ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG2                                                                       ; 4     ; 2              ; 0            ; 2              ; 7      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG1                                                                       ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG0                                                                       ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|comb_5                                                             ; 10    ; 0              ; 1            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|d                                                                  ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|wr_ptr                 ; 4     ; 0              ; 0            ; 0              ; 13     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count           ; 4     ; 0              ; 0            ; 0              ; 13     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|FIFOram                ; 40    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw ; 5     ; 0              ; 0            ; 0              ; 13     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|fifo_state             ; 5     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo                        ; 14    ; 0              ; 0            ; 0              ; 11     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated                               ; 13    ; 0              ; 0            ; 0              ; 11     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo                                                               ; 13    ; 0              ; 0            ; 0              ; 11     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS                                                                    ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_ADC                                                                    ; 4     ; 1              ; 0            ; 1              ; 14     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; PWM_DC                                                                     ; 12    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_DAC                                                                    ; 12    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; GEN_10K                                                                    ; 18    ; 17             ; 0            ; 17             ; 1      ; 17              ; 17            ; 17              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_4/ex17/db/ex17.map.ammdb b/part_4/ex17/db/ex17.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_4/ex17/db/ex17.map.ammdb
diff --git a/part_4/ex17/db/ex17.map.bpm b/part_4/ex17/db/ex17.map.bpm
new file mode 100755
index 0000000..e4ab20f
--- /dev/null
+++ b/part_4/ex17/db/ex17.map.bpm
diff --git a/part_4/ex17/db/ex17.map.cdb b/part_4/ex17/db/ex17.map.cdb
new file mode 100755
index 0000000..6f6d817
--- /dev/null
+++ b/part_4/ex17/db/ex17.map.cdb
diff --git a/part_4/ex17/db/ex17.map.hdb b/part_4/ex17/db/ex17.map.hdb
new file mode 100755
index 0000000..e1efb31
--- /dev/null
+++ b/part_4/ex17/db/ex17.map.hdb
diff --git a/part_4/ex17/db/ex17.map.kpt b/part_4/ex17/db/ex17.map.kpt
new file mode 100755
index 0000000..60f1363
--- /dev/null
+++ b/part_4/ex17/db/ex17.map.kpt
diff --git a/part_4/ex17/db/ex17.map.logdb b/part_4/ex17/db/ex17.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex17/db/ex17.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex17/db/ex17.map.qmsg b/part_4/ex17/db/ex17.map.qmsg
new file mode 100755
index 0000000..304779f
--- /dev/null
+++ b/part_4/ex17/db/ex17.map.qmsg
@@ -0,0 +1,89 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480677400559 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480677400561 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:16:40 2016 " "Processing started: Fri Dec 02 11:16:40 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480677400561 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677400561 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677400561 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480677401048 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480677401048 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/div_by_2.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_by_2 " "Found entity 1: div_by_2" {  } { { "verilog_files/div_by_2.v" "" { Text "C:/New folder/ex17/verilog_files/div_by_2.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409545 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409545 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex17/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409547 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409547 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "verilog_files/spi2adc.v" "" { Text "C:/New folder/ex17/verilog_files/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409549 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409549 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex17/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409550 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409550 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" {  } { { "verilog_files/pulse_gen.v" "" { Text "C:/New folder/ex17/verilog_files/pulse_gen.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409552 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409552 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" {  } { { "verilog_files/multiply_k.v" "" { Text "C:/New folder/ex17/verilog_files/multiply_k.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409553 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409553 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex17/verilog_files/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409555 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409555 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "verilog_files/delay_ram.v" "" { Text "C:/New folder/ex17/verilog_files/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409557 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409557 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" {  } { { "verilog_files/clktick_16.v" "" { Text "C:/New folder/ex17/verilog_files/clktick_16.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409558 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409558 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409560 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409561 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409561 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex17/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409562 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409562 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO " "Found entity 1: FIFO" {  } { { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex17/verilog_files/FIFO.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409564 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409564 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/echo_synth.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/echo_synth.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "verilog_files/echo_synth.v" "" { Text "C:/New folder/ex17/verilog_files/echo_synth.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409565 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409565 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex17.v 1 1 " "Found 1 design units, including 1 entities, in source file ex17.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex17 " "Found entity 1: ex17" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409567 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409567 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" {  } { { "verilog_files/d_ff.v" "" { Text "C:/New folder/ex17/verilog_files/d_ff.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409569 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409569 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "echo_synth.v(25) " "Verilog HDL Instantiation warning at echo_synth.v(25): instance has no name" {  } { { "verilog_files/echo_synth.v" "" { Text "C:/New folder/ex17/verilog_files/echo_synth.v" 25 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480677409570 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex17 " "Elaborating entity \"ex17\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480677409613 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clktick_16 clktick_16:GEN_10K " "Elaborating entity \"clktick_16\" for hierarchy \"clktick_16:GEN_10K\"" {  } { { "ex17.v" "GEN_10K" { Text "C:/New folder/ex17/ex17.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409614 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" {  } { { "ex17.v" "SPI_DAC" { Text "C:/New folder/ex17/ex17.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409615 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" {  } { { "ex17.v" "PWM_DC" { Text "C:/New folder/ex17/ex17.v" 27 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409616 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "ex17.v" "SPI_ADC" { Text "C:/New folder/ex17/ex17.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409617 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:ALLPASS " "Elaborating entity \"processor\" for hierarchy \"processor:ALLPASS\"" {  } { { "ex17.v" "ALLPASS" { Text "C:/New folder/ex17/ex17.v" 40 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409618 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FIFO processor:ALLPASS\|FIFO:fifo " "Elaborating entity \"FIFO\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\"" {  } { { "verilog_files/echo_synth.v" "fifo" { Text "C:/New folder/ex17/verilog_files/echo_synth.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409630 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component " "Elaborating entity \"scfifo\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\"" {  } { { "verilog_files/FIFO.v" "scfifo_component" { Text "C:/New folder/ex17/verilog_files/FIFO.v" 73 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409802 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component " "Elaborated megafunction instantiation \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\"" {  } { { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex17/verilog_files/FIFO.v" 73 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409803 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component " "Instantiated megafunction \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 8192 " "Parameter \"lpm_numwords\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 10 " "Parameter \"lpm_width\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 13 " "Parameter \"lpm_widthu\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677409803 ""}  } { { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex17/verilog_files/FIFO.v" 73 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480677409803 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_4l81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_4l81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_4l81 " "Found entity 1: scfifo_4l81" {  } { { "db/scfifo_4l81.tdf" "" { Text "C:/New folder/ex17/db/scfifo_4l81.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409845 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409845 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_4l81 processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated " "Elaborating entity \"scfifo_4l81\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/scfifo.tdf" 300 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409846 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_br81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_br81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_br81 " "Found entity 1: a_dpfifo_br81" {  } { { "db/a_dpfifo_br81.tdf" "" { Text "C:/New folder/ex17/db/a_dpfifo_br81.tdf" 29 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409859 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409859 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_br81 processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo " "Elaborating entity \"a_dpfifo_br81\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\"" {  } { { "db/scfifo_4l81.tdf" "dpfifo" { Text "C:/New folder/ex17/db/scfifo_4l81.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409859 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_4be.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_4be.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_4be " "Found entity 1: a_fefifo_4be" {  } { { "db/a_fefifo_4be.tdf" "" { Text "C:/New folder/ex17/db/a_fefifo_4be.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409872 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409872 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_4be processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|a_fefifo_4be:fifo_state " "Elaborating entity \"a_fefifo_4be\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|a_fefifo_4be:fifo_state\"" {  } { { "db/a_dpfifo_br81.tdf" "fifo_state" { Text "C:/New folder/ex17/db/a_dpfifo_br81.tdf" 40 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409872 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_di7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_di7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_di7 " "Found entity 1: cntr_di7" {  } { { "db/cntr_di7.tdf" "" { Text "C:/New folder/ex17/db/cntr_di7.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409914 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409914 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_di7 processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|a_fefifo_4be:fifo_state\|cntr_di7:count_usedw " "Elaborating entity \"cntr_di7\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|a_fefifo_4be:fifo_state\|cntr_di7:count_usedw\"" {  } { { "db/a_fefifo_4be.tdf" "count_usedw" { Text "C:/New folder/ex17/db/a_fefifo_4be.tdf" 38 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409915 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_44t1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_44t1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_44t1 " "Found entity 1: altsyncram_44t1" {  } { { "db/altsyncram_44t1.tdf" "" { Text "C:/New folder/ex17/db/altsyncram_44t1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677409958 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677409958 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_44t1 processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|altsyncram_44t1:FIFOram " "Elaborating entity \"altsyncram_44t1\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|altsyncram_44t1:FIFOram\"" {  } { { "db/a_dpfifo_br81.tdf" "FIFOram" { Text "C:/New folder/ex17/db/a_dpfifo_br81.tdf" 41 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677409958 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ib.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ib.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ib " "Found entity 1: cntr_1ib" {  } { { "db/cntr_1ib.tdf" "" { Text "C:/New folder/ex17/db/cntr_1ib.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677410000 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677410000 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ib processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|cntr_1ib:rd_ptr_count " "Elaborating entity \"cntr_1ib\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|cntr_1ib:rd_ptr_count\"" {  } { { "db/a_dpfifo_br81.tdf" "rd_ptr_count" { Text "C:/New folder/ex17/db/a_dpfifo_br81.tdf" 42 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677410000 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_ff processor:ALLPASS\|d_ff:d " "Elaborating entity \"d_ff\" for hierarchy \"processor:ALLPASS\|d_ff:d\"" {  } { { "verilog_files/echo_synth.v" "d" { Text "C:/New folder/ex17/verilog_files/echo_synth.v" 21 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677410003 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_by_2 processor:ALLPASS\|div_by_2:comb_5 " "Elaborating entity \"div_by_2\" for hierarchy \"processor:ALLPASS\|div_by_2:comb_5\"" {  } { { "verilog_files/echo_synth.v" "comb_5" { Text "C:/New folder/ex17/verilog_files/echo_synth.v" 25 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677410003 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex17.v" "SEG0" { Text "C:/New folder/ex17/ex17.v" 42 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677410007 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|altsyncram_44t1:FIFOram\|q_b\[0\] " "Synthesized away node \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|altsyncram_44t1:FIFOram\|q_b\[0\]\"" {  } { { "db/altsyncram_44t1.tdf" "" { Text "C:/New folder/ex17/db/altsyncram_44t1.tdf" 40 2 0 } } { "db/a_dpfifo_br81.tdf" "" { Text "C:/New folder/ex17/db/a_dpfifo_br81.tdf" 41 2 0 } } { "db/scfifo_4l81.tdf" "" { Text "C:/New folder/ex17/db/scfifo_4l81.tdf" 35 2 0 } } { "scfifo.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/scfifo.tdf" 300 3 0 } } { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex17/verilog_files/FIFO.v" 73 0 0 } } { "verilog_files/echo_synth.v" "" { Text "C:/New folder/ex17/verilog_files/echo_synth.v" 19 0 0 } } { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677410086 "|ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a0"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1480677410086 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1480677410086 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480677410622 "|ex17|HEX2[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480677410622 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480677410702 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex17/output_files/ex17.map.smsg " "Generated suppressed messages file C:/New folder/ex17/output_files/ex17.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677410935 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480677411028 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677411028 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "10 " "Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "No output dependent on input pin \"SW\[5\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "No output dependent on input pin \"SW\[6\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "No output dependent on input pin \"SW\[7\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[8]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677411078 "|ex17|SW[9]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480677411078 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "255 " "Implemented 255 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480677411079 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480677411079 ""} { "Info" "ICUT_CUT_TM_LCELLS" "205 " "Implemented 205 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480677411079 ""} { "Info" "ICUT_CUT_TM_RAMS" "9 " "Implemented 9 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1480677411079 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480677411079 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "903 " "Peak virtual memory: 903 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480677411094 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:16:51 2016 " "Processing ended: Fri Dec 02 11:16:51 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480677411094 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480677411094 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480677411094 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677411094 ""}
diff --git a/part_4/ex17/db/ex17.map.rdb b/part_4/ex17/db/ex17.map.rdb
new file mode 100755
index 0000000..ed64312
--- /dev/null
+++ b/part_4/ex17/db/ex17.map.rdb
diff --git a/part_4/ex17/db/ex17.map_bb.cdb b/part_4/ex17/db/ex17.map_bb.cdb
new file mode 100755
index 0000000..b446a8b
--- /dev/null
+++ b/part_4/ex17/db/ex17.map_bb.cdb
diff --git a/part_4/ex17/db/ex17.map_bb.hdb b/part_4/ex17/db/ex17.map_bb.hdb
new file mode 100755
index 0000000..0790dc9
--- /dev/null
+++ b/part_4/ex17/db/ex17.map_bb.hdb
diff --git a/part_4/ex17/db/ex17.map_bb.logdb b/part_4/ex17/db/ex17.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex17/db/ex17.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex17/db/ex17.npp.qmsg b/part_4/ex17/db/ex17.npp.qmsg
new file mode 100755
index 0000000..570808c
--- /dev/null
+++ b/part_4/ex17/db/ex17.npp.qmsg
@@ -0,0 +1,5 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480676749815 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480676749818 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:05:49 2016 " "Processing started: Fri Dec 02 11:05:49 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480676749818 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1480676749818 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp ex17 -c ex17 --netlist_type=sgate " "Command: quartus_npp ex17 -c ex17 --netlist_type=sgate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1480676749818 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1480676750040 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1  Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "391 " "Peak virtual memory: 391 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480676750079 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:05:50 2016 " "Processing ended: Fri Dec 02 11:05:50 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480676750079 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480676750079 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480676750079 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1480676750079 ""}
diff --git a/part_4/ex17/db/ex17.pre_map.hdb b/part_4/ex17/db/ex17.pre_map.hdb
new file mode 100755
index 0000000..574ccbe
--- /dev/null
+++ b/part_4/ex17/db/ex17.pre_map.hdb
diff --git a/part_4/ex17/db/ex17.root_partition.map.reg_db.cdb b/part_4/ex17/db/ex17.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..5213f9e
--- /dev/null
+++ b/part_4/ex17/db/ex17.root_partition.map.reg_db.cdb
diff --git a/part_4/ex17/db/ex17.routing.rdb b/part_4/ex17/db/ex17.routing.rdb
new file mode 100755
index 0000000..582e327
--- /dev/null
+++ b/part_4/ex17/db/ex17.routing.rdb
diff --git a/part_4/ex17/db/ex17.rtlv.hdb b/part_4/ex17/db/ex17.rtlv.hdb
new file mode 100755
index 0000000..3ea6c94
--- /dev/null
+++ b/part_4/ex17/db/ex17.rtlv.hdb
diff --git a/part_4/ex17/db/ex17.rtlv_sg.cdb b/part_4/ex17/db/ex17.rtlv_sg.cdb
new file mode 100755
index 0000000..81d15ab
--- /dev/null
+++ b/part_4/ex17/db/ex17.rtlv_sg.cdb
diff --git a/part_4/ex17/db/ex17.rtlv_sg_swap.cdb b/part_4/ex17/db/ex17.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..7cc2512
--- /dev/null
+++ b/part_4/ex17/db/ex17.rtlv_sg_swap.cdb
diff --git a/part_4/ex17/db/ex17.sgate.nvd b/part_4/ex17/db/ex17.sgate.nvd
new file mode 100755
index 0000000..4bf00e1
--- /dev/null
+++ b/part_4/ex17/db/ex17.sgate.nvd
diff --git a/part_4/ex17/db/ex17.sgate_sm.nvd b/part_4/ex17/db/ex17.sgate_sm.nvd
new file mode 100755
index 0000000..abc4b05
--- /dev/null
+++ b/part_4/ex17/db/ex17.sgate_sm.nvd
diff --git a/part_4/ex17/db/ex17.sld_design_entry.sci b/part_4/ex17/db/ex17.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_4/ex17/db/ex17.sld_design_entry.sci
diff --git a/part_4/ex17/db/ex17.sld_design_entry_dsc.sci b/part_4/ex17/db/ex17.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_4/ex17/db/ex17.sld_design_entry_dsc.sci
diff --git a/part_4/ex17/db/ex17.smart_action.txt b/part_4/ex17/db/ex17.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_4/ex17/db/ex17.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/part_4/ex17/db/ex17.smp_dump.txt b/part_4/ex17/db/ex17.smp_dump.txt
new file mode 100755
index 0000000..f965caa
--- /dev/null
+++ b/part_4/ex17/db/ex17.smp_dump.txt
@@ -0,0 +1,12 @@
+
+State Machine - |ex17|spi2adc:SPI_ADC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
+
+State Machine - |ex17|spi2dac:SPI_DAC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
diff --git a/part_4/ex17/db/ex17.sta.qmsg b/part_4/ex17/db/ex17.sta.qmsg
new file mode 100755
index 0000000..396f26c
--- /dev/null
+++ b/part_4/ex17/db/ex17.sta.qmsg
@@ -0,0 +1,52 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480677457372 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480677457373 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:17:36 2016 " "Processing started: Fri Dec 02 11:17:36 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480677457373 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677457373 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex17 -c ex17 " "Command: quartus_sta ex17 -c ex17" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677457373 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480677457496 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458058 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458059 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458106 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458106 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex17.sdc " "Synopsys Design Constraints File file not found: 'ex17.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458635 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458635 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480677458637 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clktick_16:GEN_10K\|tick clktick_16:GEN_10K\|tick " "create_clock -period 1.000 -name clktick_16:GEN_10K\|tick clktick_16:GEN_10K\|tick" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480677458637 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz " "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480677458637 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2dac:SPI_DAC\|clk_1MHz spi2dac:SPI_DAC\|clk_1MHz " "create_clock -period 1.000 -name spi2dac:SPI_DAC\|clk_1MHz spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480677458637 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458637 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458640 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458647 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480677458648 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480677458655 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480677458687 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458687 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.994 " "Worst-case setup slack is -4.994" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.994           -1215.299 CLOCK_50  " "   -4.994           -1215.299 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.053             -66.004 spi2dac:SPI_DAC\|clk_1MHz  " "   -4.053             -66.004 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.114             -53.900 spi2adc:SPI_ADC\|clk_1MHz  " "   -3.114             -53.900 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.678              -2.678 clktick_16:GEN_10K\|tick  " "   -2.678              -2.678 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458689 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458689 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.216 " "Worst-case hold slack is 0.216" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.216               0.000 CLOCK_50  " "    0.216               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.562               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.562               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.714               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.714               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458693 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.976               0.000 clktick_16:GEN_10K\|tick  " "    1.976               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458693 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458693 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458695 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458696 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1383.263 CLOCK_50  " "   -2.174           -1383.263 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -17.619 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.394             -17.619 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -11.427 spi2dac:SPI_DAC\|clk_1MHz  " "   -0.394             -11.427 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -0.606 clktick_16:GEN_10K\|tick  " "   -0.394              -0.606 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677458698 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458698 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480677458714 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677458750 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677459902 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677459970 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480677459979 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677459979 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.050 " "Worst-case setup slack is -5.050" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459981 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459981 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.050           -1121.685 CLOCK_50  " "   -5.050           -1121.685 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459981 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.187             -67.782 spi2dac:SPI_DAC\|clk_1MHz  " "   -4.187             -67.782 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459981 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.261             -52.098 spi2adc:SPI_ADC\|clk_1MHz  " "   -3.261             -52.098 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459981 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.847              -2.847 clktick_16:GEN_10K\|tick  " "   -2.847              -2.847 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459981 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677459981 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.151 " "Worst-case hold slack is 0.151" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.151               0.000 CLOCK_50  " "    0.151               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.589               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.589               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.708               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.708               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459985 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.149               0.000 clktick_16:GEN_10K\|tick  " "    2.149               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459985 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677459985 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677459987 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677459989 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1374.432 CLOCK_50  " "   -2.174           -1374.432 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -17.072 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.394             -17.072 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -11.267 spi2dac:SPI_DAC\|clk_1MHz  " "   -0.394             -11.267 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -0.616 clktick_16:GEN_10K\|tick  " "   -0.394              -0.616 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677459990 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677459990 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480677460006 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677460160 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461153 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461219 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480677461222 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461222 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.284 " "Worst-case setup slack is -3.284" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.284            -731.582 CLOCK_50  " "   -3.284            -731.582 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.019             -29.840 spi2dac:SPI_DAC\|clk_1MHz  " "   -2.019             -29.840 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.371             -26.126 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.371             -26.126 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.141              -1.141 clktick_16:GEN_10K\|tick  " "   -1.141              -1.141 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461223 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461223 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.129 " "Worst-case hold slack is 0.129" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.129               0.000 CLOCK_50  " "    0.129               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.300               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.300               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.330               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.330               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.863               0.000 clktick_16:GEN_10K\|tick  " "    0.863               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461227 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461227 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461229 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461230 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1382.020 CLOCK_50  " "   -2.174           -1382.020 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.019               0.000 clktick_16:GEN_10K\|tick  " "    0.019               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.104               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.104               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461232 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.152               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.152               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461232 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461232 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480677461248 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461413 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480677461416 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461416 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.747 " "Worst-case setup slack is -2.747" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.747            -575.387 CLOCK_50  " "   -2.747            -575.387 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.914             -28.398 spi2dac:SPI_DAC\|clk_1MHz  " "   -1.914             -28.398 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.344             -23.465 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.344             -23.465 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.139              -1.139 clktick_16:GEN_10K\|tick  " "   -1.139              -1.139 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461418 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461418 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.088 " "Worst-case hold slack is 0.088" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.088               0.000 CLOCK_50  " "    0.088               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.274               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.274               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.296               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.296               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461421 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.878               0.000 clktick_16:GEN_10K\|tick  " "    0.878               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461421 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461421 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461423 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461425 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1412.607 CLOCK_50  " "   -2.174           -1412.607 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.039               0.000 clktick_16:GEN_10K\|tick  " "    0.039               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.119               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.119               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461426 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.150               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.150               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480677461426 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677461426 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677462772 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677462773 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1237 " "Peak virtual memory: 1237 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480677462817 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:17:42 2016 " "Processing ended: Fri Dec 02 11:17:42 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480677462817 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480677462817 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480677462817 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480677462817 ""}
diff --git a/part_4/ex17/db/ex17.sta.rdb b/part_4/ex17/db/ex17.sta.rdb
new file mode 100755
index 0000000..505cc91
--- /dev/null
+++ b/part_4/ex17/db/ex17.sta.rdb
diff --git a/part_4/ex17/db/ex17.sta_cmp.6_slow_1100mv_85c.tdb b/part_4/ex17/db/ex17.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..52da888
--- /dev/null
+++ b/part_4/ex17/db/ex17.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_4/ex17/db/ex17.tis_db_list.ddb b/part_4/ex17/db/ex17.tis_db_list.ddb
new file mode 100755
index 0000000..88225e8
--- /dev/null
+++ b/part_4/ex17/db/ex17.tis_db_list.ddb
diff --git a/part_4/ex17/db/ex17.tiscmp.fast_1100mv_0c.ddb b/part_4/ex17/db/ex17.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..6b389b6
--- /dev/null
+++ b/part_4/ex17/db/ex17.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_4/ex17/db/ex17.tiscmp.fast_1100mv_85c.ddb b/part_4/ex17/db/ex17.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..9e397a8
--- /dev/null
+++ b/part_4/ex17/db/ex17.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_4/ex17/db/ex17.tiscmp.slow_1100mv_0c.ddb b/part_4/ex17/db/ex17.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..b238d4d
--- /dev/null
+++ b/part_4/ex17/db/ex17.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_4/ex17/db/ex17.tiscmp.slow_1100mv_85c.ddb b/part_4/ex17/db/ex17.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..55ea1c1
--- /dev/null
+++ b/part_4/ex17/db/ex17.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_2/ex9_final/db/ex9.tmw_info b/part_4/ex17/db/ex17.tmw_info
index 436c9e2..724425d 100755
--- a/part_2/ex9_final/db/ex9.tmw_info
+++ b/part_4/ex17/db/ex17.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:01:01
+start_full_compilation:s:00:01:04
 start_analysis_synthesis:s:00:00:12-start_full_compilation
 start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:35-start_full_compilation
+start_fitter:s:00:00:38-start_full_compilation
 start_assembler:s:00:00:07-start_full_compilation
 start_timing_analyzer:s:00:00:07-start_full_compilation
diff --git a/part_4/ex17/db/ex17.vpr.ammdb b/part_4/ex17/db/ex17.vpr.ammdb
new file mode 100755
index 0000000..46bf2ae
--- /dev/null
+++ b/part_4/ex17/db/ex17.vpr.ammdb
diff --git a/part_4/ex17/db/ex17_partition_pins.json b/part_4/ex17/db/ex17_partition_pins.json
new file mode 100755
index 0000000..884712b
--- /dev/null
+++ b/part_4/ex17/db/ex17_partition_pins.json
@@ -0,0 +1,129 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_LD",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "PWM_OUT",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDO",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
+\ No newline at end of file
diff --git a/part_4/ex17/db/prev_cmp_ex17.qmsg b/part_4/ex17/db/prev_cmp_ex17.qmsg
new file mode 100755
index 0000000..28d6bc7
--- /dev/null
+++ b/part_4/ex17/db/prev_cmp_ex17.qmsg
@@ -0,0 +1,61 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480677339607 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480677339609 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:15:39 2016 " "Processing started: Fri Dec 02 11:15:39 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480677339609 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677339609 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677339609 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480677340067 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480677340068 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/div_by_2.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_by_2 " "Found entity 1: div_by_2" {  } { { "verilog_files/div_by_2.v" "" { Text "C:/New folder/ex17/verilog_files/div_by_2.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348359 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348359 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/allpass.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/allpass.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "verilog_files/allpass.v" "" { Text "C:/New folder/ex17/verilog_files/allpass.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348360 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348360 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex17/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348362 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348362 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "verilog_files/spi2adc.v" "" { Text "C:/New folder/ex17/verilog_files/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348364 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348364 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex17/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348365 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348365 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" {  } { { "verilog_files/pulse_gen.v" "" { Text "C:/New folder/ex17/verilog_files/pulse_gen.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348367 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348367 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" {  } { { "verilog_files/multiply_k.v" "" { Text "C:/New folder/ex17/verilog_files/multiply_k.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348368 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348368 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex17/verilog_files/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348370 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348370 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "verilog_files/delay_ram.v" "" { Text "C:/New folder/ex17/verilog_files/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348371 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348371 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" {  } { { "verilog_files/clktick_16.v" "" { Text "C:/New folder/ex17/verilog_files/clktick_16.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348373 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348373 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex17/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348376 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348376 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex17/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348378 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348378 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO " "Found entity 1: FIFO" {  } { { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex17/verilog_files/FIFO.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348379 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348379 ""}
+{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "processor echo_synth.v(1) " "Verilog HDL error at echo_synth.v(1): module \"processor\" cannot be declared more than once" {  } { { "verilog_files/echo_synth.v" "" { Text "C:/New folder/ex17/verilog_files/echo_synth.v" 1 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "Analysis & Synthesis" 0 -1 1480677348381 ""}
+{ "Info" "IVRFX_HDL_SEE_DECLARATION" "processor allpass.v(9) " "HDL info at allpass.v(9): see declaration for object \"processor\"" {  } { { "verilog_files/allpass.v" "" { Text "C:/New folder/ex17/verilog_files/allpass.v" 9 0 0 } }  } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677348381 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/echo_synth.v 0 0 " "Found 0 design units, including 0 entities, in source file verilog_files/echo_synth.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348381 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex17.v 1 1 " "Found 1 design units, including 1 entities, in source file ex17.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex17 " "Found entity 1: ex17" {  } { { "ex17.v" "" { Text "C:/New folder/ex17/ex17.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348382 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348382 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" {  } { { "verilog_files/d_ff.v" "" { Text "C:/New folder/ex17/verilog_files/d_ff.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677348384 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348384 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex17/output_files/ex17.map.smsg " "Generated suppressed messages file C:/New folder/ex17/output_files/ex17.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348404 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "834 " "Peak virtual memory: 834 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480677348438 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Dec 02 11:15:48 2016 " "Processing ended: Fri Dec 02 11:15:48 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480677348438 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480677348438 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480677348438 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677348438 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1  " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677349023 ""}
diff --git a/part_4/ex17/db/scfifo_4l81.tdf b/part_4/ex17/db/scfifo_4l81.tdf
new file mode 100755
index 0000000..64b9640
--- /dev/null
+++ b/part_4/ex17/db/scfifo_4l81.tdf
@@ -0,0 +1,48 @@
+--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Cyclone V" LPM_NUMWORDS=8192 LPM_SHOWAHEAD="OFF" LPM_WIDTH=10 LPM_WIDTHU=13 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data full q rdreq wrreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO"
+--VERSION_BEGIN 16.0 cbx_altdpram 2016:04:27:18:05:34:SJ cbx_altera_syncram 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_scfifo 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION a_dpfifo_br81 (clock, data[9..0], rreq, sclr, wreq)
+RETURNS ( full, q[9..0]);
+
+--synthesis_resources = lut 39 M10K 10 reg 41 
+SUBDESIGN scfifo_4l81
+( 
+	clock	:	input;
+	data[9..0]	:	input;
+	full	:	output;
+	q[9..0]	:	output;
+	rdreq	:	input;
+	wrreq	:	input;
+) 
+VARIABLE 
+	dpfifo : a_dpfifo_br81;
+	sclr	: NODE;
+
+BEGIN 
+	dpfifo.clock = clock;
+	dpfifo.data[] = data[];
+	dpfifo.rreq = rdreq;
+	dpfifo.sclr = sclr;
+	dpfifo.wreq = wrreq;
+	full = dpfifo.full;
+	q[] = dpfifo.q[];
+	sclr = GND;
+END;
+--VALID FILE
diff --git a/part_4/ex17/ex17.qpf b/part_4/ex17/ex17.qpf
new file mode 100755
index 0000000..0b0cf68
--- /dev/null
+++ b/part_4/ex17/ex17.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 09:42:26  December 02, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "09:42:26  December 02, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex17"
diff --git a/part_2/ex9_final/ex9.qsf b/part_4/ex17/ex17.qsf
index af789d5..abe86da 100755
--- a/part_2/ex9_final/ex9.qsf
+++ b/part_4/ex17/ex17.qsf
@@ -1,3 +1,60 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 09:42:26  December 02, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ex17_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex17
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:42:26  DECEMBER 02, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+
+
 #============================================================
 # CLOCK
 #============================================================
@@ -208,67 +265,20 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
 
 #============================================================
 # End of pin and io_standard assignments
-#============================================================# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, the Altera Quartus Prime License Agreement,
-# the Altera MegaCore Function License Agreement, or other 
-# applicable license agreement, including, without limitation, 
-# that your use is for the sole purpose of programming logic 
-# devices manufactured by Altera and sold by Altera or its 
-# authorized distributors.  Please refer to the applicable 
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		ex9_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus Prime software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name DEVICE 5CSEMA5F31C6
-set_global_assignment -name TOP_LEVEL_ENTITY ex9
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
-set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v
-set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v
+#============================================================
+set_global_assignment -name VERILOG_FILE verilog_files/div_by_2.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2dac.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2adc.v
+set_global_assignment -name VERILOG_FILE verilog_files/pwm.v
+set_global_assignment -name VERILOG_FILE verilog_files/pulse_gen.v
+set_global_assignment -name VERILOG_FILE verilog_files/multiply_k.v
 set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
-set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v
-set_global_assignment -name VERILOG_FILE verilog_files/delay.v
-set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/delay_ram.v
+set_global_assignment -name VERILOG_FILE verilog_files/clktick_16.v
 set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
 set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
-set_global_assignment -name VERILOG_FILE verilog_files/ex9.v
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name QIP_FILE verilog_files/FIFO.qip
+set_global_assignment -name VERILOG_FILE verilog_files/echo_synth.v
+set_global_assignment -name VERILOG_FILE ex17.v
+set_global_assignment -name VERILOG_FILE verilog_files/d_ff.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 \ No newline at end of file
diff --git a/part_2/ex9_partially_working/ex9.qsf.bak b/part_4/ex17/ex17.qsf.bak
index d4eef07..dbd4bac 100755
--- a/part_2/ex9_partially_working/ex9.qsf.bak
+++ b/part_4/ex17/ex17.qsf.bak
@@ -19,14 +19,14 @@
 #
 # Quartus Prime
 # Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
+# Date created = 09:42:26  December 02, 2016
 #
 # -------------------------------------------------------------------------- #
 #
 # Notes:
 #
 # 1) The default values for assignments are stored in the file:
-#		ex9_assignment_defaults.qdf
+#		ex17_assignment_defaults.qdf
 #    If this file doesn't exist, see file:
 #		assignment_defaults.qdf
 #
@@ -39,26 +39,30 @@
 
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name DEVICE 5CSEMA5F31C6
-set_global_assignment -name TOP_LEVEL_ENTITY ex9
+set_global_assignment -name TOP_LEVEL_ENTITY ex17
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:42:26  DECEMBER 02, 2016"
 set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v
-set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v
-set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2dac.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2adc.v
+set_global_assignment -name VERILOG_FILE verilog_files/pwm.v
+set_global_assignment -name VERILOG_FILE verilog_files/pulse_gen.v
+set_global_assignment -name VERILOG_FILE verilog_files/multiply_k.v
 set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
-set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v
-set_global_assignment -name VERILOG_FILE verilog_files/delay.v
-set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/delay_ram.v
+set_global_assignment -name VERILOG_FILE verilog_files/clktick_16.v
 set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
 set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
-set_global_assignment -name VERILOG_FILE verilog_files/ex9.v
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name QIP_FILE verilog_files/FIFO.qip
+set_global_assignment -name VERILOG_FILE verilog_files/echo_synth.v
+set_global_assignment -name VERILOG_FILE verilog_files/div_by_4.v
+set_global_assignment -name VERILOG_FILE ex17.v
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
diff --git a/part_4/ex17/ex17.qws b/part_4/ex17/ex17.qws
new file mode 100755
index 0000000..899f330
--- /dev/null
+++ b/part_4/ex17/ex17.qws
diff --git a/part_4/ex17/ex17.v b/part_4/ex17/ex17.v
new file mode 100755
index 0000000..f1c114a
--- /dev/null
+++ b/part_4/ex17/ex17.v
@@ -0,0 +1,46 @@
+module ex17 (CLOCK_50, SW, HEX0, HEX1, HEX2, 
+					DAC_SDI, DAC_SCK, DAC_CS, DAC_LD,
+					ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT);
+
+	input			CLOCK_50;		// DE0 50MHz system clock
+	input [9:0]	SW;				// 10 slide switches to specify address to ROM
+	output [6:0] HEX0, HEX1, HEX2;
+	output 		DAC_SDI;			//Serial data out to SDI of the DAC
+	output 		DAC_SCK;				//Serial clock signal to both DAC and ADC
+	output		DAC_CS;			//Chip select to the DAC, low active
+	output 		DAC_LD;			//Load new data to DAC, low active	
+	output 		ADC_SDI;			//Serial data out to SDI of the ADC
+	output 		ADC_SCK;		// ADC Clock signal
+	output		ADC_CS;			//Chip select to the ADC, low active
+	input 		ADC_SDO;			//Converted serial data from ADC	
+	output		PWM_OUT;			// PWM output to R channel
+		
+	wire			tick_10k;		// internal clock at 10kHz
+	wire [9:0] 	data_in;		// converted data from ADC
+	wire [9:0] 	data_out;	// processed data to DAC
+	wire			data_valid;
+	wire			DAC_SCK, ADC_SCK;
+	
+	clktick_16  GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k);  	// generate 10KHz sampling clock ticks
+	spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, 		// send processed sample to DAC
+					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);		// order of signals matter
+	pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT);		// output via PWM - R-channel
+					
+	spi2adc SPI_ADC (												// perform a A-to-D conversion
+		.sysclk (CLOCK_50), 										// order of parameters do not matter
+		.channel (1'b1), 											// use only CH1
+		.start (tick_10k),
+		.data_from_adc (data_in),
+		.data_valid (data_valid),
+		.sdata_to_adc (ADC_SDI),
+		.adc_cs (ADC_CS),
+		.adc_sck (ADC_SCK),
+		.sdata_from_adc (ADC_SDO));		
+					
+	processor	ALLPASS (CLOCK_50, tick_10k, data_in, data_out);	// do some processing on the data
+	
+	hex_to_7seg		SEG0 (HEX0, data_in[3:0]);			
+	hex_to_7seg		SEG1 (HEX1, data_in[7:4]);			
+	hex_to_7seg		SEG2 (HEX2, {2'b0,data_in[9:8]});			
+		
+endmodule
diff --git a/part_4/ex17/ex17.v.bak b/part_4/ex17/ex17.v.bak
new file mode 100755
index 0000000..852036e
--- /dev/null
+++ b/part_4/ex17/ex17.v.bak
@@ -0,0 +1,54 @@
+//------------------------------
+// Module name: ex16_top
+// Function: top level module - pass audio input to output directly
+// Creator:  Peter Cheung
+// Version:  2.0
+// Date:     10 Nov 2016
+//------------------------------
+
+module ex16_top (CLOCK_50, SW, HEX0, HEX1, HEX2, 
+					DAC_SDI, DAC_SCK, DAC_CS, DAC_LD,
+					ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT);
+
+	input			CLOCK_50;		// DE0 50MHz system clock
+	input [9:0]	SW;				// 10 slide switches to specify address to ROM
+	output [6:0] HEX0, HEX1, HEX2;
+	output 		DAC_SDI;			//Serial data out to SDI of the DAC
+	output 		DAC_SCK;				//Serial clock signal to both DAC and ADC
+	output		DAC_CS;			//Chip select to the DAC, low active
+	output 		DAC_LD;			//Load new data to DAC, low active	
+	output 		ADC_SDI;			//Serial data out to SDI of the ADC
+	output 		ADC_SCK;		// ADC Clock signal
+	output		ADC_CS;			//Chip select to the ADC, low active
+	input 		ADC_SDO;			//Converted serial data from ADC	
+	output		PWM_OUT;			// PWM output to R channel
+		
+	wire			tick_10k;		// internal clock at 10kHz
+	wire [9:0] 	data_in;		// converted data from ADC
+	wire [9:0] 	data_out;	// processed data to DAC
+	wire			data_valid;
+	wire			DAC_SCK, ADC_SCK;
+	
+	clktick_16  GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k);  	// generate 10KHz sampling clock ticks
+	spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, 		// send processed sample to DAC
+					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);		// order of signals matter
+	pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT);		// output via PWM - R-channel
+					
+	spi2adc SPI_ADC (												// perform a A-to-D conversion
+		.sysclk (CLOCK_50), 										// order of parameters do not matter
+		.channel (1'b1), 											// use only CH1
+		.start (tick_10k),
+		.data_from_adc (data_in),
+		.data_valid (data_valid),
+		.sdata_to_adc (ADC_SDI),
+		.adc_cs (ADC_CS),
+		.adc_sck (ADC_SCK),
+		.sdata_from_adc (ADC_SDO));		
+					
+	processor	ALLPASS (CLOCK_50, data_in, data_out);	// do some processing on the data
+	
+	hex_to_7seg		SEG0 (HEX0, data_in[3:0]);			
+	hex_to_7seg		SEG1 (HEX1, data_in[7:4]);			
+	hex_to_7seg		SEG2 (HEX2, {2'b0,data_in[9:8]});			
+		
+endmodule
diff --git a/part_4/ex17/greybox_tmp/cbx_args.txt b/part_4/ex17/greybox_tmp/cbx_args.txt
new file mode 100755
index 0000000..d8e0c62
--- /dev/null
+++ b/part_4/ex17/greybox_tmp/cbx_args.txt
@@ -0,0 +1,17 @@
+ADD_RAM_OUTPUT_REGISTER=OFF
+INTENDED_DEVICE_FAMILY="Cyclone V"
+LPM_NUMWORDS=8192
+LPM_SHOWAHEAD=OFF
+LPM_TYPE=scfifo
+LPM_WIDTH=10
+LPM_WIDTHU=13
+OVERFLOW_CHECKING=ON
+UNDERFLOW_CHECKING=ON
+USE_EAB=ON
+DEVICE_FAMILY="Cyclone V"
+clock
+data
+rdreq
+wrreq
+full
+q
diff --git a/part_4/ex17/incremental_db/README b/part_4/ex17/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_4/ex17/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.db_info b/part_4/ex17/incremental_db/compiled_partitions/ex17.db_info
new file mode 100755
index 0000000..4843a0e
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Dec 02 10:04:00 2016
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.ammdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.ammdb
new file mode 100755
index 0000000..2fbd710
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.ammdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.cdb
new file mode 100755
index 0000000..0156fa1
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.dfp b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.dfp
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..6242f54
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.hdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..0a0a18f
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.hdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.sig b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hdb
new file mode 100755
index 0000000..fe9b1c7
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.hdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.logdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.rcfdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..6674dc4
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.cmp.rcfdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.cdb
new file mode 100755
index 0000000..46eb5e0
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.dpi b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.dpi
new file mode 100755
index 0000000..65713de
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.dpi
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..85a405a
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.hb_info b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.hb_info
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.hdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..a0bf316
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.hdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.sig b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hdb
new file mode 100755
index 0000000..4ae34ea
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.hdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.kpt b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.kpt
new file mode 100755
index 0000000..d47422e
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.kpt
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.olf.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.olf.cdb
new file mode 100755
index 0000000..8dd6e81
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.olf.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.olm.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.olm.cdb
new file mode 100755
index 0000000..92f7059
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.olm.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.oln.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.oln.cdb
new file mode 100755
index 0000000..11ac05e
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.oln.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.opi b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.opi
@@ -0,0 +1 @@
+1
+\ No newline at end of file
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orf.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orf.cdb
new file mode 100755
index 0000000..3b57ac3
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orf.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orm.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orm.cdb
new file mode 100755
index 0000000..8dbd549
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orm.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orn.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orn.cdb
new file mode 100755
index 0000000..4999258
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.map.orn.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.cdb
new file mode 100755
index 0000000..46eb5e0
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hbdb.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..85a405a
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hbdb.cdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hbdb.hdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..a0bf316
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hbdb.hdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hdb
new file mode 100755
index 0000000..4ae34ea
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.hdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.kpt b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.kpt
new file mode 100755
index 0000000..d47422e
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.root_partition.rrp.kpt
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.rrp.hdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.rrp.hdb
new file mode 100755
index 0000000..70828cc
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.rrp.hdb
diff --git a/part_4/ex17/incremental_db/compiled_partitions/ex17.rrs.cdb b/part_4/ex17/incremental_db/compiled_partitions/ex17.rrs.cdb
new file mode 100755
index 0000000..c00f99d
--- /dev/null
+++ b/part_4/ex17/incremental_db/compiled_partitions/ex17.rrs.cdb
diff --git a/part_2/ex9_final/output_files/ex9.asm.rpt b/part_4/ex17/output_files/ex17.asm.rpt
index 3fcae64..f5907e9 100755
--- a/part_2/ex9_final/output_files/ex9.asm.rpt
+++ b/part_4/ex17/output_files/ex17.asm.rpt
@@ -1,5 +1,5 @@
-Assembler report for ex9
-Fri Nov 25 12:11:08 2016
+Assembler report for ex17
+Fri Dec 02 11:17:35 2016
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 
 
@@ -10,7 +10,7 @@ Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: C:/New folder/ex9/output_files/ex9.sof
+  5. Assembler Device Options: C:/New folder/ex17/output_files/ex17.sof
   6. Assembler Messages
 
 
@@ -38,9 +38,9 @@ agreement for further details.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Fri Nov 25 12:11:08 2016 ;
-; Revision Name         ; ex9                                   ;
-; Top-level Entity Name ; ex9                                   ;
+; Assembler Status      ; Successful - Fri Dec 02 11:17:35 2016 ;
+; Revision Name         ; ex17                                  ;
+; Top-level Entity Name ; ex17                                  ;
 ; Family                ; Cyclone V                             ;
 ; Device                ; 5CSEMA5F31C6                          ;
 +-----------------------+---------------------------------------+
@@ -53,24 +53,24 @@ agreement for further details.
 +--------+---------+---------------+
 
 
-+----------------------------------------+
-; Assembler Generated Files              ;
-+----------------------------------------+
-; File Name                              ;
-+----------------------------------------+
-; C:/New folder/ex9/output_files/ex9.sof ;
-+----------------------------------------+
++------------------------------------------+
+; Assembler Generated Files                ;
++------------------------------------------+
+; File Name                                ;
++------------------------------------------+
+; C:/New folder/ex17/output_files/ex17.sof ;
++------------------------------------------+
 
 
-+------------------------------------------------------------------+
-; Assembler Device Options: C:/New folder/ex9/output_files/ex9.sof ;
-+----------------+-------------------------------------------------+
-; Option         ; Setting                                         ;
-+----------------+-------------------------------------------------+
-; Device         ; 5CSEMA5F31C6                                    ;
-; JTAG usercode  ; 0x00B4D80C                                      ;
-; Checksum       ; 0x00B4D80C                                      ;
-+----------------+-------------------------------------------------+
++--------------------------------------------------------------------+
+; Assembler Device Options: C:/New folder/ex17/output_files/ex17.sof ;
++----------------+---------------------------------------------------+
+; Option         ; Setting                                           ;
++----------------+---------------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                      ;
+; JTAG usercode  ; 0x00E0A368                                        ;
+; Checksum       ; 0x00E0A368                                        ;
++----------------+---------------------------------------------------+
 
 
 +--------------------+
@@ -79,13 +79,13 @@ agreement for further details.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Fri Nov 25 12:11:02 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+    Info: Processing started: Fri Dec 02 11:17:29 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex17 -c ex17
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 895 megabytes
-    Info: Processing ended: Fri Nov 25 12:11:08 2016
+    Info: Peak virtual memory: 894 megabytes
+    Info: Processing ended: Fri Dec 02 11:17:35 2016
     Info: Elapsed time: 00:00:06
     Info: Total CPU time (on all processors): 00:00:06
 
diff --git a/part_4/ex17/output_files/ex17.done b/part_4/ex17/output_files/ex17.done
new file mode 100755
index 0000000..a1728fb
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.done
@@ -0,0 +1 @@
+Fri Dec 02 11:17:43 2016
diff --git a/part_4/ex17/output_files/ex17.fit.rpt b/part_4/ex17/output_files/ex17.fit.rpt
new file mode 100755
index 0000000..7b9fc89
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.fit.rpt
@@ -0,0 +1,2116 @@
+Fitter report for ex17
+Fri Dec 02 11:17:28 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Fitter RAM Summary
+ 24. Routing Usage Summary
+ 25. I/O Rules Summary
+ 26. I/O Rules Details
+ 27. I/O Rules Matrix
+ 28. Fitter Device Options
+ 29. Operating Settings and Conditions
+ 30. Estimated Delay Added for Hold Timing Summary
+ 31. Estimated Delay Added for Hold Timing Details
+ 32. Fitter Messages
+ 33. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Fri Dec 02 11:17:28 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex17                                            ;
+; Top-level Entity Name           ; ex17                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 92 / 32,070 ( < 1 % )                           ;
+; Total registers                 ; 165                                             ;
+; Total pins                      ; 41 / 457 ( 9 % )                                ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 73,728 / 4,065,280 ( 2 % )                      ;
+; Total RAM Blocks                ; 9 / 397 ( 2 % )                                 ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.03        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   1.2%      ;
+;     Processor 3            ;   1.0%      ;
+;     Processor 4            ;   1.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; HEX0[0]  ; Missing drive strength and slew rate ;
+; HEX0[1]  ; Missing drive strength and slew rate ;
+; HEX0[2]  ; Missing drive strength and slew rate ;
+; HEX0[3]  ; Missing drive strength and slew rate ;
+; HEX0[4]  ; Missing drive strength and slew rate ;
+; HEX0[5]  ; Missing drive strength and slew rate ;
+; HEX0[6]  ; Missing drive strength and slew rate ;
+; HEX1[0]  ; Missing drive strength and slew rate ;
+; HEX1[1]  ; Missing drive strength and slew rate ;
+; HEX1[2]  ; Missing drive strength and slew rate ;
+; HEX1[3]  ; Missing drive strength and slew rate ;
+; HEX1[4]  ; Missing drive strength and slew rate ;
+; HEX1[5]  ; Missing drive strength and slew rate ;
+; HEX1[6]  ; Missing drive strength and slew rate ;
+; HEX2[0]  ; Missing drive strength and slew rate ;
+; HEX2[1]  ; Missing drive strength and slew rate ;
+; HEX2[2]  ; Missing drive strength and slew rate ;
+; HEX2[3]  ; Missing drive strength and slew rate ;
+; HEX2[4]  ; Missing drive strength and slew rate ;
+; HEX2[5]  ; Missing drive strength and slew rate ;
+; HEX2[6]  ; Missing drive strength and slew rate ;
+; DAC_SDI  ; Missing drive strength and slew rate ;
+; DAC_SCK  ; Missing drive strength and slew rate ;
+; DAC_CS   ; Missing drive strength and slew rate ;
+; DAC_LD   ; Missing drive strength and slew rate ;
+; ADC_SDI  ; Missing drive strength and slew rate ;
+; ADC_SCK  ; Missing drive strength and slew rate ;
+; ADC_CS   ; Missing drive strength and slew rate ;
+; PWM_OUT  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                                        ;
++----------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------+------------------+-----------------------+
+; Node                             ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                           ; Destination Port ; Destination Port Name ;
++----------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0            ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                            ;                  ;                       ;
+; clktick_16:GEN_10K|count[0]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[0]~DUPLICATE      ;                  ;                       ;
+; clktick_16:GEN_10K|count[1]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[1]~DUPLICATE      ;                  ;                       ;
+; clktick_16:GEN_10K|count[6]      ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[6]~DUPLICATE      ;                  ;                       ;
+; clktick_16:GEN_10K|count[12]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[12]~DUPLICATE     ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[1]           ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[1]~DUPLICATE           ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[4]           ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[4]~DUPLICATE           ;                  ;                       ;
+; spi2adc:SPI_ADC|data_from_adc[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|data_from_adc[0]~DUPLICATE ;                  ;                       ;
+; spi2adc:SPI_ADC|state[2]         ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[2]~DUPLICATE         ;                  ;                       ;
+; spi2adc:SPI_ADC|state[3]         ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[3]~DUPLICATE         ;                  ;                       ;
+; spi2adc:SPI_ADC|state[4]         ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[4]~DUPLICATE         ;                  ;                       ;
+; spi2dac:SPI_DAC|state[4]         ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:SPI_DAC|state[4]~DUPLICATE         ;                  ;                       ;
++----------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                        ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location     ;                ;              ; HEX3[0]    ; PIN_AD26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[1]    ; PIN_AC27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[2]    ; PIN_AD25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[3]    ; PIN_AC25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[4]    ; PIN_AB28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[5]    ; PIN_AB25      ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[6]    ; PIN_AB22      ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[0]    ; PIN_AA24      ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[1]    ; PIN_Y23       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[2]    ; PIN_Y24       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[3]    ; PIN_W22       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[4]    ; PIN_W24       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[5]    ; PIN_V23       ; QSF Assignment ;
+; Location     ;                ;              ; HEX4[6]    ; PIN_W25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[0]     ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]     ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX3[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX3[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX3[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX3[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX3[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX3[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX3[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX4[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX4[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX4[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX4[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX4[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX4[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX4[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; KEY[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; KEY[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex17           ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 411 ) ; 0.00 % ( 0 / 411 )         ; 0.00 % ( 0 / 411 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 411 ) ; 0.00 % ( 0 / 411 )         ; 0.00 % ( 0 / 411 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 411 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/New folder/ex17/output_files/ex17.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 92 / 32,070        ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 92                 ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 101 / 32,070       ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 63                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 23                 ;       ;
+;         [c] ALMs used for registers                         ; 15                 ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 9 / 32,070         ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 18 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 18                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 165                ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 8                  ;       ;
+;     -- 5 input functions                                    ; 19                 ;       ;
+;     -- 4 input functions                                    ; 27                 ;       ;
+;     -- <=3 input functions                                  ; 111                ;       ;
+; Combinational ALUT usage for route-throughs                 ; 10                 ;       ;
+; Dedicated logic registers                                   ; 165                ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 154 / 64,140       ; < 1 % ;
+;         -- Secondary logic registers                        ; 11 / 64,140        ; < 1 % ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 154                ;       ;
+;         -- Routing optimization registers                   ; 11                 ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 41 / 457           ; 9 %   ;
+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 9 / 397            ; 2 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 73,728 / 4,065,280 ; 2 %   ;
+; Total block memory implementation bits                      ; 92,160 / 4,065,280 ; 2 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.3% / 0.3% / 0.2% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 7.9% / 8.6% / 6.0% ;       ;
+; Maximum fan-out                                             ; 124                ;       ;
+; Highest non-global fan-out                                  ; 43                 ;       ;
+; Total fan-out                                               ; 1272               ;       ;
+; Average fan-out                                             ; 2.94               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                          ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 92 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 92                    ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 101 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 63                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 23                    ; 0                              ;
+;         [c] ALMs used for registers                         ; 15                    ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 9 / 32070 ( < 1 % )   ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Difficulty packing design                                   ; Low                   ; Low                            ;
+;                                                             ;                       ;                                ;
+; Total LABs:  partially or completely used                   ; 18 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 18                    ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Combinational ALUT usage for logic                          ; 165                   ; 0                              ;
+;     -- 7 input functions                                    ; 0                     ; 0                              ;
+;     -- 6 input functions                                    ; 8                     ; 0                              ;
+;     -- 5 input functions                                    ; 19                    ; 0                              ;
+;     -- 4 input functions                                    ; 27                    ; 0                              ;
+;     -- <=3 input functions                                  ; 111                   ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 10                    ; 0                              ;
+; Memory ALUT usage                                           ; 0                     ; 0                              ;
+;     -- 64-address deep                                      ; 0                     ; 0                              ;
+;     -- 32-address deep                                      ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Dedicated logic registers                                   ; 0                     ; 0                              ;
+;     -- By type:                                             ;                       ;                                ;
+;         -- Primary logic registers                          ; 154 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 11 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                       ;                                ;
+;         -- Design implementation registers                  ; 154                   ; 0                              ;
+;         -- Routing optimization registers                   ; 11                    ; 0                              ;
+;                                                             ;                       ;                                ;
+;                                                             ;                       ;                                ;
+; Virtual pins                                                ; 0                     ; 0                              ;
+; I/O pins                                                    ; 41                    ; 0                              ;
+; I/O registers                                               ; 0                     ; 0                              ;
+; Total block memory bits                                     ; 73728                 ; 0                              ;
+; Total block memory implementation bits                      ; 92160                 ; 0                              ;
+; M10K block                                                  ; 9 / 397 ( 2 % )       ; 0 / 397 ( 0 % )                ;
+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
+;                                                             ;                       ;                                ;
+; Connections                                                 ;                       ;                                ;
+;     -- Input Connections                                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections                         ; 0                     ; 0                              ;
+;     -- Output Connections                                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections                        ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Internal Connections                                        ;                       ;                                ;
+;     -- Total Connections                                    ; 1425                  ; 0                              ;
+;     -- Registered Connections                               ; 734                   ; 0                              ;
+;                                                             ;                       ;                                ;
+; External Connections                                        ;                       ;                                ;
+;     -- Top                                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Partition Interface                                         ;                       ;                                ;
+;     -- Input Ports                                          ; 12                    ; 0                              ;
+;     -- Output Ports                                         ; 29                    ; 0                              ;
+;     -- Bidir Ports                                          ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Registered Ports                                            ;                       ;                                ;
+;     -- Registered Input Ports                               ; 0                     ; 0                              ;
+;     -- Registered Output Ports                              ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Port Connectivity                                           ;                       ;                                ;
+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; ADC_SDO  ; AJ21  ; 4A       ; 62           ; 0            ; 51           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 127                   ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[0]    ; AB12  ; 3A       ; 12           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[1]    ; AC12  ; 3A       ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[2]    ; AF9   ; 3A       ; 8            ; 0            ; 34           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[3]    ; AF10  ; 3A       ; 4            ; 0            ; 51           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[4]    ; AD11  ; 3A       ; 2            ; 0            ; 40           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[5]    ; AD12  ; 3A       ; 16           ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[6]    ; AE11  ; 3A       ; 4            ; 0            ; 34           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[7]    ; AC9   ; 3A       ; 4            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[8]    ; AD10  ; 3A       ; 4            ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[9]    ; AE12  ; 3A       ; 2            ; 0            ; 57           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; ADC_CS  ; AG20  ; 4A       ; 62           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; ADC_SCK ; AF21  ; 4A       ; 70           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; ADC_SDI ; AG21  ; 4A       ; 54           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_CS  ; AD20  ; 4A       ; 82           ; 0            ; 40           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_LD  ; AK21  ; 4A       ; 68           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SCK ; AF20  ; 4A       ; 70           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SDI ; AG18  ; 4A       ; 58           ; 0            ; 74           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; PWM_OUT ; AJ20  ; 4A       ; 62           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 10 / 32 ( 31 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 3B       ; 1 / 48 ( 2 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 9 / 80 ( 11 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 15 / 32 ( 47 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 6 / 16 ( 38 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; SW[0]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; SW[7]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; SW[1]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; SW[8]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD11     ; 54         ; 3A             ; SW[4]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD12     ; 80         ; 3A             ; SW[5]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; DAC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD26     ; 240        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; SW[6]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE12     ; 52         ; 3A             ; SW[9]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; SW[2]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF10     ; 57         ; 3A             ; SW[3]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; DAC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF21     ; 173        ; 4A             ; ADC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; DAC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; ADC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG21     ; 143        ; 4A             ; ADC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; PWM_OUT                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AJ21     ; 156        ; 4A             ; ADC_SDO                         ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; DAC_LD                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W22      ; 223        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W25      ; 244        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y24      ; 234        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                  ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                    ; Entity Name     ; Library Name ;
++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex17                                       ; 91.5 (0.5)           ; 100.0 (0.5)                      ; 8.5 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 165 (1)             ; 165 (0)                   ; 0 (0)         ; 73728             ; 9     ; 0          ; 41   ; 0            ; |ex17                                                                                                                                                  ; ex17            ; work         ;
+;    |clktick_16:GEN_10K|                     ; 11.0 (11.0)          ; 11.5 (11.5)                      ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 20 (20)             ; 21 (21)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|clktick_16:GEN_10K                                                                                                                               ; clktick_16      ; work         ;
+;    |hex_to_7seg:SEG0|                       ; 2.4 (2.4)            ; 2.4 (2.4)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|hex_to_7seg:SEG0                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:SEG1|                       ; 2.5 (2.5)            ; 2.5 (2.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|hex_to_7seg:SEG1                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:SEG2|                       ; 1.0 (1.0)            ; 1.5 (1.5)                        ; 0.5 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|hex_to_7seg:SEG2                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |processor:ALLPASS|                      ; 33.6 (10.1)          ; 33.6 (10.1)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 67 (22)             ; 51 (10)                   ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS                                                                                                                                ; processor       ; work         ;
+;       |FIFO:fifo|                           ; 22.8 (0.0)           ; 23.2 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (0)              ; 40 (0)                    ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo                                                                                                                      ; FIFO            ; work         ;
+;          |scfifo:scfifo_component|          ; 22.8 (0.0)           ; 23.2 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (0)              ; 40 (0)                    ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component                                                                                              ; scfifo          ; work         ;
+;             |scfifo_4l81:auto_generated|    ; 22.8 (0.0)           ; 23.2 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (0)              ; 40 (0)                    ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated                                                                   ; scfifo_4l81     ; work         ;
+;                |a_dpfifo_br81:dpfifo|       ; 22.8 (0.0)           ; 23.2 (0.5)                       ; 0.3 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (1)              ; 40 (0)                    ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo                                              ; a_dpfifo_br81   ; work         ;
+;                   |a_fefifo_4be:fifo_state| ; 9.7 (3.2)            ; 9.7 (3.2)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (5)              ; 14 (1)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state                      ; a_fefifo_4be    ; work         ;
+;                      |cntr_di7:count_usedw| ; 6.5 (6.5)            ; 6.5 (6.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7        ; work         ;
+;                   |altsyncram_44t1:FIFOram| ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram                      ; altsyncram_44t1 ; work         ;
+;                   |cntr_1ib:rd_ptr_count|   ; 6.5 (6.5)            ; 6.5 (6.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:rd_ptr_count                        ; cntr_1ib        ; work         ;
+;                   |cntr_1ib:wr_ptr|         ; 6.5 (6.5)            ; 6.5 (6.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:wr_ptr                              ; cntr_1ib        ; work         ;
+;       |d_ff:d|                              ; 0.3 (0.3)            ; 0.3 (0.3)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 1 (1)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|d_ff:d                                                                                                                         ; d_ff            ; work         ;
+;    |pwm:PWM_DC|                             ; 10.7 (10.7)          ; 11.3 (11.3)                      ; 0.6 (0.6)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 19 (19)             ; 21 (21)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|pwm:PWM_DC                                                                                                                                       ; pwm             ; work         ;
+;    |spi2adc:SPI_ADC|                        ; 14.5 (14.5)          ; 20.8 (20.8)                      ; 6.3 (6.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 21 (21)             ; 45 (45)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|spi2adc:SPI_ADC                                                                                                                                  ; spi2adc         ; work         ;
+;    |spi2dac:SPI_DAC|                        ; 14.7 (14.7)          ; 15.9 (15.9)                      ; 1.3 (1.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 20 (20)             ; 27 (27)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex17|spi2dac:SPI_DAC                                                                                                                                  ; spi2dac         ; work         ;
++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; SW[0]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[1]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[2]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[3]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[4]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[5]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[6]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[7]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[8]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[9]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_LD   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; PWM_OUT  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; ADC_SDO  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                    ;
++-------------------------------------+-------------------+---------+
+; Source Pin / Fanout                 ; Pad To Core Index ; Setting ;
++-------------------------------------+-------------------+---------+
+; SW[0]                               ;                   ;         ;
+; SW[1]                               ;                   ;         ;
+; SW[2]                               ;                   ;         ;
+; SW[3]                               ;                   ;         ;
+; SW[4]                               ;                   ;         ;
+; SW[5]                               ;                   ;         ;
+; SW[6]                               ;                   ;         ;
+; SW[7]                               ;                   ;         ;
+; SW[8]                               ;                   ;         ;
+; SW[9]                               ;                   ;         ;
+; CLOCK_50                            ;                   ;         ;
+;      - spi2dac:SPI_DAC|clk_1MHz     ; 0                 ; 0       ;
+;      - spi2adc:SPI_ADC|clk_1MHz     ; 0                 ; 0       ;
+;      - clktick_16:GEN_10K|tick      ; 0                 ; 0       ;
+; ADC_SDO                             ;                   ;         ;
+;      - spi2adc:SPI_ADC|shift_reg[0] ; 1                 ; 0       ;
++-------------------------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                             ;
++---------------------------------------------------------------------------------------------------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                            ; Location            ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                                                                        ; PIN_AF14            ; 4       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                                        ; PIN_AF14            ; 115     ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; clktick_16:GEN_10K|Equal0~3                                                                                                     ; LABCELL_X51_Y4_N48  ; 11      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; clktick_16:GEN_10K|tick                                                                                                         ; FF_X51_Y4_N53       ; 21      ; Clock, Clock enable        ; no     ; --                   ; --               ; --                        ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|_~0 ; LABCELL_X51_Y4_N57  ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|valid_wreq                  ; MLABCELL_X52_Y4_N42 ; 34      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; processor:ALLPASS|and_if                                                                                                        ; MLABCELL_X52_Y4_N45 ; 23      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|adc_done                                                                                                        ; FF_X62_Y3_N31       ; 11      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|always3~0                                                                                                       ; LABCELL_X62_Y3_N15  ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|clk_1MHz                                                                                                        ; FF_X62_Y4_N11       ; 35      ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|Equal0~0                                                                                                        ; LABCELL_X62_Y4_N6   ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|always3~0                                                                                                       ; LABCELL_X63_Y4_N57  ; 9       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|clk_1MHz                                                                                                        ; FF_X62_Y4_N8        ; 24      ; Clock                      ; no     ; --                   ; --               ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------------+---------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 115     ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; Name                                                                                                                                   ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF  ; Location                                                                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs         ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 8192         ; 10           ; 8192         ; 10           ; yes                    ; no                      ; yes                    ; no                      ; 81920 ; 8192                        ; 9                           ; 8192                        ; 9                           ; 73728               ; 9           ; 0          ; None ; M10K_X58_Y6_N0, M10K_X69_Y3_N0, M10K_X69_Y5_N0, M10K_X58_Y4_N0, M10K_X69_Y2_N0, M10K_X58_Y3_N0, M10K_X69_Y4_N0, M10K_X58_Y2_N0, M10K_X58_Y5_N0 ; Don't care           ; New data        ; New data        ; Off      ; No                     ; No - Address Too Wide ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 538 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 21 / 13,420 ( < 1 % )   ;
+; C2 interconnects                            ; 243 / 119,108 ( < 1 % ) ;
+; C4 interconnects                            ; 137 / 56,300 ( < 1 % )  ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 22 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 1 / 16 ( 6 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 101 / 84,580 ( < 1 % )  ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 111 / 12,676 ( < 1 % )  ;
+; R14/C12 interconnect drivers                ; 117 / 20,720 ( < 1 % )  ;
+; R3 interconnects                            ; 371 / 130,992 ( < 1 % ) ;
+; R6 interconnects                            ; 490 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 2 / 360 ( < 1 % )       ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                  ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 41        ; 0            ; 41        ; 0            ; 0            ; 41        ; 41        ; 0            ; 41        ; 41        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 41           ; 0         ; 41           ; 41           ; 0         ; 0         ; 41           ; 0         ; 0         ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; SW[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_LD             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; PWM_OUT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDO            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++---------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                   ;
++----------------------------------+--------------------------+-------------------+
+; Source Clock(s)                  ; Destination Clock(s)     ; Delay Added in ns ;
++----------------------------------+--------------------------+-------------------+
+; spi2adc:SPI_ADC|clk_1MHz         ; CLOCK_50                 ; 282.5             ;
+; CLOCK_50                         ; CLOCK_50                 ; 161.1             ;
+; spi2adc:SPI_ADC|clk_1MHz         ; spi2adc:SPI_ADC|clk_1MHz ; 31.7              ;
+; CLOCK_50,clktick_16:GEN_10K|tick ; CLOCK_50                 ; 27.1              ;
+; spi2dac:SPI_DAC|clk_1MHz         ; spi2dac:SPI_DAC|clk_1MHz ; 21.4              ;
+; spi2dac:SPI_DAC|clk_1MHz         ; CLOCK_50                 ; 16.1              ;
++----------------------------------+--------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                                   ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                                                                      ; Destination Register                                                                                                                                                 ; Delay Added in ns ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 5.344             ;
+; spi2dac:SPI_DAC|clk_1MHz                                                                                                                                             ; spi2dac:SPI_DAC|clk_1MHz                                                                                                                                             ; 4.991             ;
+; clktick_16:GEN_10K|tick                                                                                                                                              ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[12] ; 4.831             ;
+; spi2dac:SPI_DAC|dac_cs                                                                                                                                               ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL                                                                                                                               ; 4.205             ;
+; spi2adc:SPI_ADC|adc_cs                                                                                                                                               ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL                                                                                                                               ; 4.157             ;
+; spi2adc:SPI_ADC|data_from_adc[4]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.983             ;
+; spi2adc:SPI_ADC|data_from_adc[2]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.979             ;
+; spi2adc:SPI_ADC|data_from_adc[6]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.973             ;
+; spi2adc:SPI_ADC|data_from_adc[5]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.966             ;
+; spi2adc:SPI_ADC|data_from_adc[8]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.965             ;
+; spi2adc:SPI_ADC|data_from_adc[1]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.965             ;
+; spi2adc:SPI_ADC|data_from_adc[3]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.958             ;
+; spi2adc:SPI_ADC|data_from_adc[7]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.937             ;
+; spi2adc:SPI_ADC|data_from_adc[0]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.918             ;
+; processor:ALLPASS|d_ff:d|out                                                                                                                                         ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 3.551             ;
+; spi2adc:SPI_ADC|data_from_adc[9]                                                                                                                                     ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~porta_datain_reg0           ; 3.274             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[12] ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 2.652             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[11] ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 2.652             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[10] ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 2.652             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[9]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 2.652             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[12] ; 2.542             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[8]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[7]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[6]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[5]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[3]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[2]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[1]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[0]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[4]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.324             ;
+; spi2adc:SPI_ADC|ctr[3]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 1.167             ;
+; clktick_16:GEN_10K|count[11]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 1.165             ;
+; clktick_16:GEN_10K|count[2]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 1.140             ;
+; clktick_16:GEN_10K|count[9]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 1.090             ;
+; clktick_16:GEN_10K|count[8]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 1.082             ;
+; spi2adc:SPI_ADC|state[1]                                                                                                                                             ; spi2adc:SPI_ADC|adc_din                                                                                                                                              ; 1.002             ;
+; spi2adc:SPI_ADC|state[0]                                                                                                                                             ; spi2adc:SPI_ADC|adc_din                                                                                                                                              ; 0.998             ;
+; spi2adc:SPI_ADC|state[4]                                                                                                                                             ; spi2adc:SPI_ADC|adc_din                                                                                                                                              ; 0.985             ;
+; clktick_16:GEN_10K|count[6]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.981             ;
+; clktick_16:GEN_10K|count[7]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.965             ;
+; spi2adc:SPI_ADC|shift_reg[0]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[1]                                                                                                                                         ; 0.947             ;
+; spi2adc:SPI_ADC|shift_reg[8]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[9]                                                                                                                                         ; 0.941             ;
+; spi2adc:SPI_ADC|shift_reg[6]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[7]                                                                                                                                         ; 0.941             ;
+; spi2adc:SPI_ADC|shift_reg[4]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[5]                                                                                                                                         ; 0.941             ;
+; spi2adc:SPI_ADC|state[2]                                                                                                                                             ; spi2adc:SPI_ADC|shift_ena                                                                                                                                            ; 0.933             ;
+; spi2adc:SPI_ADC|shift_reg[7]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[8]                                                                                                                                         ; 0.929             ;
+; spi2adc:SPI_ADC|shift_reg[5]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[6]                                                                                                                                         ; 0.929             ;
+; spi2adc:SPI_ADC|shift_reg[3]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[4]                                                                                                                                         ; 0.929             ;
+; spi2adc:SPI_ADC|ctr[0]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.927             ;
+; spi2dac:SPI_DAC|shift_reg[14]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[15]                                                                                                                                        ; 0.924             ;
+; spi2adc:SPI_ADC|ctr[2]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.924             ;
+; clktick_16:GEN_10K|count[1]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.918             ;
+; clktick_16:GEN_10K|count[0]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.915             ;
+; spi2adc:SPI_ADC|ctr[4]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.911             ;
+; spi2dac:SPI_DAC|shift_reg[12]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[13]                                                                                                                                        ; 0.909             ;
+; spi2dac:SPI_DAC|shift_reg[13]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[14]                                                                                                                                        ; 0.909             ;
+; spi2dac:SPI_DAC|shift_reg[11]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[12]                                                                                                                                        ; 0.909             ;
+; spi2adc:SPI_ADC|state[3]                                                                                                                                             ; spi2adc:SPI_ADC|shift_ena                                                                                                                                            ; 0.897             ;
+; clktick_16:GEN_10K|count[4]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.890             ;
+; clktick_16:GEN_10K|count[13]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.886             ;
+; clktick_16:GEN_10K|count[15]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.872             ;
+; clktick_16:GEN_10K|count[10]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.867             ;
+; spi2dac:SPI_DAC|state[4]                                                                                                                                             ; spi2dac:SPI_DAC|dac_cs                                                                                                                                               ; 0.865             ;
+; spi2adc:SPI_ADC|ctr[1]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.820             ;
+; clktick_16:GEN_10K|count[12]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.785             ;
+; spi2adc:SPI_ADC|shift_reg[2]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[3]                                                                                                                                         ; 0.780             ;
+; spi2adc:SPI_ADC|shift_reg[1]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[2]                                                                                                                                         ; 0.775             ;
+; clktick_16:GEN_10K|count[5]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.763             ;
+; spi2dac:SPI_DAC|state[1]                                                                                                                                             ; spi2dac:SPI_DAC|dac_cs                                                                                                                                               ; 0.747             ;
+; spi2dac:SPI_DAC|state[0]                                                                                                                                             ; spi2dac:SPI_DAC|dac_cs                                                                                                                                               ; 0.745             ;
+; clktick_16:GEN_10K|count[3]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.738             ;
+; clktick_16:GEN_10K|count[14]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.670             ;
+; spi2dac:SPI_DAC|state[2]                                                                                                                                             ; spi2dac:SPI_DAC|dac_cs                                                                                                                                               ; 0.649             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a7~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a4~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a3~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a2~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a1~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 0.647             ;
+; pwm:PWM_DC|d[3]                                                                                                                                                      ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.636             ;
+; pwm:PWM_DC|d[2]                                                                                                                                                      ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.636             ;
+; pwm:PWM_DC|d[1]                                                                                                                                                      ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.636             ;
+; pwm:PWM_DC|d[0]                                                                                                                                                      ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.636             ;
+; pwm:PWM_DC|count[3]                                                                                                                                                  ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.636             ;
+; pwm:PWM_DC|count[2]                                                                                                                                                  ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.636             ;
+; pwm:PWM_DC|count[1]                                                                                                                                                  ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.636             ;
+; pwm:PWM_DC|count[0]                                                                                                                                                  ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.636             ;
+; spi2dac:SPI_DAC|shift_reg[2]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[3]                                                                                                                                         ; 0.604             ;
+; spi2dac:SPI_DAC|shift_reg[10]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[11]                                                                                                                                        ; 0.604             ;
+; spi2dac:SPI_DAC|shift_reg[9]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[10]                                                                                                                                        ; 0.597             ;
+; spi2dac:SPI_DAC|state[3]                                                                                                                                             ; spi2dac:SPI_DAC|dac_cs                                                                                                                                               ; 0.592             ;
+; spi2dac:SPI_DAC|shift_reg[4]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[5]                                                                                                                                         ; 0.572             ;
+; spi2dac:SPI_DAC|shift_reg[7]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[8]                                                                                                                                         ; 0.572             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[0]                               ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a4~porta_address_reg0          ; 0.547             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:wr_ptr|counter_reg_bit[1]                               ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a4~porta_address_reg0          ; 0.540             ;
+; spi2dac:SPI_DAC|shift_reg[3]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[4]                                                                                                                                         ; 0.527             ;
+; spi2dac:SPI_DAC|shift_reg[6]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[7]                                                                                                                                         ; 0.527             ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex17"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 118 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex17.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:03
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:04
+Info (11888): Total time spent on timing analysis during the Fitter is 0.83 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:03
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file C:/New folder/ex17/output_files/ex17.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 45 warnings
+    Info: Peak virtual memory: 2765 megabytes
+    Info: Processing ended: Fri Dec 02 11:17:28 2016
+    Info: Elapsed time: 00:00:37
+    Info: Total CPU time (on all processors): 00:01:06
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/New folder/ex17/output_files/ex17.fit.smsg.
+
+
diff --git a/part_4/ex17/output_files/ex17.fit.smsg b/part_4/ex17/output_files/ex17.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_2/ex9_partially_working/output_files/ex9.fit.summary b/part_4/ex17/output_files/ex17.fit.summary
index 976377e..931f66e 100755
--- a/part_2/ex9_partially_working/output_files/ex9.fit.summary
+++ b/part_4/ex17/output_files/ex17.fit.summary
@@ -1,16 +1,16 @@
-Fitter Status : Successful - Fri Nov 25 11:27:54 2016
+Fitter Status : Successful - Fri Dec 02 11:17:28 2016
 Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-Revision Name : ex9
-Top-level Entity Name : ex9
+Revision Name : ex17
+Top-level Entity Name : ex17
 Family : Cyclone V
 Device : 5CSEMA5F31C6
 Timing Models : Final
-Logic utilization (in ALMs) : 154 / 32,070 ( < 1 % )
-Total registers : 95
-Total pins : 57 / 457 ( 12 % )
+Logic utilization (in ALMs) : 92 / 32,070 ( < 1 % )
+Total registers : 165
+Total pins : 41 / 457 ( 9 % )
 Total virtual pins : 0
-Total block memory bits : 0 / 4,065,280 ( 0 % )
-Total RAM Blocks : 0 / 397 ( 0 % )
+Total block memory bits : 73,728 / 4,065,280 ( 2 % )
+Total RAM Blocks : 9 / 397 ( 2 % )
 Total DSP Blocks : 0 / 87 ( 0 % )
 Total HSSI RX PCSs : 0
 Total HSSI PMA RX Deserializers : 0
diff --git a/part_2/ex9_final/output_files/ex9.flow.rpt b/part_4/ex17/output_files/ex17.flow.rpt
index f4ca16c..e96fbd8 100755
--- a/part_2/ex9_final/output_files/ex9.flow.rpt
+++ b/part_4/ex17/output_files/ex17.flow.rpt
@@ -1,5 +1,5 @@
-Flow report for ex9
-Fri Nov 25 12:11:15 2016
+Flow report for ex17
+Fri Dec 02 11:17:42 2016
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 
 
@@ -41,18 +41,18 @@ agreement for further details.
 +-----------------------------------------------------------------------------------+
 ; Flow Summary                                                                      ;
 +---------------------------------+-------------------------------------------------+
-; Flow Status                     ; Successful - Fri Nov 25 12:11:08 2016           ;
+; Flow Status                     ; Successful - Fri Dec 02 11:17:35 2016           ;
 ; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
-; Revision Name                   ; ex9                                             ;
-; Top-level Entity Name           ; ex9                                             ;
+; Revision Name                   ; ex17                                            ;
+; Top-level Entity Name           ; ex17                                            ;
 ; Family                          ; Cyclone V                                       ;
 ; Device                          ; 5CSEMA5F31C6                                    ;
 ; Timing Models                   ; Final                                           ;
-; Logic utilization (in ALMs)     ; 159 / 32,070 ( < 1 % )                          ;
-; Total registers                 ; 95                                              ;
-; Total pins                      ; 57 / 457 ( 12 % )                               ;
+; Logic utilization (in ALMs)     ; 92 / 32,070 ( < 1 % )                           ;
+; Total registers                 ; 165                                             ;
+; Total pins                      ; 41 / 457 ( 9 % )                                ;
 ; Total virtual pins              ; 0                                               ;
-; Total block memory bits         ; 0 / 4,065,280 ( 0 % )                           ;
+; Total block memory bits         ; 73,728 / 4,065,280 ( 2 % )                      ;
 ; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
 ; Total HSSI RX PCSs              ; 0                                               ;
 ; Total HSSI PMA RX Deserializers ; 0                                               ;
@@ -68,9 +68,9 @@ agreement for further details.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 11/25/2016 12:10:16 ;
+; Start date & time ; 12/02/2016 11:16:40 ;
 ; Main task         ; Compilation         ;
-; Revision Name     ; ex9                 ;
+; Revision Name     ; ex17                ;
 +-------------------+---------------------+
 
 
@@ -79,9 +79,10 @@ agreement for further details.
 +-------------------------------------+---------------------------------------+---------------+-------------+------------+
 ; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
 +-------------------------------------+---------------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID               ; 260248564297095.148007581608608       ; --            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID               ; 260248564297095.148067740003008       ; --            ; --          ; --         ;
 ; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
 ; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; MISC_FILE                           ; verilog_files/FIFO_bb.v               ; --            ; --          ; --         ;
 ; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
 ; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
 ; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
@@ -96,11 +97,11 @@ agreement for further details.
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 898 MB              ; 00:00:22                           ;
-; Fitter                    ; 00:00:34     ; 1.0                     ; 2592 MB             ; 00:01:01                           ;
-; Assembler                 ; 00:00:06     ; 1.0                     ; 894 MB              ; 00:00:06                           ;
-; TimeQuest Timing Analyzer ; 00:00:06     ; 1.1                     ; 1213 MB             ; 00:00:06                           ;
-; Total                     ; 00:00:56     ; --                      ; --                  ; 00:01:35                           ;
+; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 903 MB              ; 00:00:23                           ;
+; Fitter                    ; 00:00:37     ; 1.0                     ; 2765 MB             ; 00:01:06                           ;
+; Assembler                 ; 00:00:06     ; 1.0                     ; 893 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:06     ; 1.2                     ; 1237 MB             ; 00:00:07                           ;
+; Total                     ; 00:00:59     ; --                      ; --                  ; 00:01:42                           ;
 +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
@@ -119,10 +120,10 @@ agreement for further details.
 ------------
 ; Flow Log ;
 ------------
-quartus_map --read_settings_files=on --write_settings_files=off ex9 -c ex9
-quartus_fit --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
-quartus_sta ex9 -c ex9
+quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17
+quartus_fit --read_settings_files=off --write_settings_files=off ex17 -c ex17
+quartus_asm --read_settings_files=off --write_settings_files=off ex17 -c ex17
+quartus_sta ex17 -c ex17
 
 
 
diff --git a/part_4/ex17/output_files/ex17.jdi b/part_4/ex17/output_files/ex17.jdi
new file mode 100755
index 0000000..dad57e2
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="6d9f5a2f9f704aef6789"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex17.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_4/ex17/output_files/ex17.map.rpt b/part_4/ex17/output_files/ex17.map.rpt
new file mode 100755
index 0000000..a332be8
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.map.rpt
@@ -0,0 +1,668 @@
+Analysis & Synthesis report for ex17
+Fri Dec 02 11:16:51 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |ex17|spi2adc:SPI_ADC|sr_state
+ 11. State Machine - |ex17|spi2dac:SPI_DAC|sr_state
+ 12. Registers Removed During Synthesis
+ 13. Removed Registers Triggering Further Register Optimizations
+ 14. General Register Statistics
+ 15. Inverted Register Statistics
+ 16. Source assignments for processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram
+ 17. Parameter Settings for User Entity Instance: clktick_16:GEN_10K
+ 18. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC
+ 19. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC
+ 20. Parameter Settings for User Entity Instance: processor:ALLPASS
+ 21. Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component
+ 22. scfifo Parameter Settings by Entity Instance
+ 23. Port Connectivity Checks: "hex_to_7seg:SEG2"
+ 24. Port Connectivity Checks: "spi2adc:SPI_ADC"
+ 25. Port Connectivity Checks: "clktick_16:GEN_10K"
+ 26. Post-Synthesis Netlist Statistics for Top Partition
+ 27. Elapsed Time Per Partition
+ 28. Analysis & Synthesis Messages
+ 29. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Fri Dec 02 11:16:51 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex17                                            ;
+; Top-level Entity Name           ; ex17                                            ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 154                                             ;
+; Total pins                      ; 41                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 73,728                                          ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex17               ; ex17               ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                      ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                  ; Library ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------+---------+
+; verilog_files/div_by_2.v         ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/verilog_files/div_by_2.v                   ;         ;
+; verilog_files/spi2dac.v          ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/verilog_files/spi2dac.v                    ;         ;
+; verilog_files/spi2adc.v          ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/verilog_files/spi2adc.v                    ;         ;
+; verilog_files/pwm.v              ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/verilog_files/pwm.v                        ;         ;
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/verilog_files/hex_to_7seg.v                ;         ;
+; verilog_files/clktick_16.v       ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/verilog_files/clktick_16.v                 ;         ;
+; verilog_files/FIFO.v             ; yes             ; User Wizard-Generated File   ; C:/New folder/ex17/verilog_files/FIFO.v                       ;         ;
+; verilog_files/echo_synth.v       ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/verilog_files/echo_synth.v                 ;         ;
+; ex17.v                           ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/ex17.v                                     ;         ;
+; verilog_files/d_ff.v             ; yes             ; User Verilog HDL File        ; C:/New folder/ex17/verilog_files/d_ff.v                       ;         ;
+; scfifo.tdf                       ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/scfifo.tdf     ;         ;
+; a_regfifo.inc                    ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_regfifo.inc  ;         ;
+; a_dpfifo.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_dpfifo.inc   ;         ;
+; a_i2fifo.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_i2fifo.inc   ;         ;
+; a_fffifo.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_fffifo.inc   ;         ;
+; a_f2fifo.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_f2fifo.inc   ;         ;
+; aglobal160.inc                   ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc ;         ;
+; db/scfifo_4l81.tdf               ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex17/db/scfifo_4l81.tdf                         ;         ;
+; db/a_dpfifo_br81.tdf             ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex17/db/a_dpfifo_br81.tdf                       ;         ;
+; db/a_fefifo_4be.tdf              ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex17/db/a_fefifo_4be.tdf                        ;         ;
+; db/cntr_di7.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex17/db/cntr_di7.tdf                            ;         ;
+; db/altsyncram_44t1.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex17/db/altsyncram_44t1.tdf                     ;         ;
+; db/cntr_1ib.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex17/db/cntr_1ib.tdf                            ;         ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimate of Logic utilization (ALMs needed) ; 95             ;
+;                                             ;                ;
+; Combinational ALUT usage for logic          ; 164            ;
+;     -- 7 input functions                    ; 0              ;
+;     -- 6 input functions                    ; 8              ;
+;     -- 5 input functions                    ; 19             ;
+;     -- 4 input functions                    ; 27             ;
+;     -- <=3 input functions                  ; 110            ;
+;                                             ;                ;
+; Dedicated logic registers                   ; 154            ;
+;                                             ;                ;
+; I/O pins                                    ; 41             ;
+; Total MLAB memory bits                      ; 0              ;
+; Total block memory bits                     ; 73728          ;
+;                                             ;                ;
+; Total DSP Blocks                            ; 0              ;
+;                                             ;                ;
+; Maximum fan-out node                        ; CLOCK_50~input ;
+; Maximum fan-out                             ; 112            ;
+; Total fan-out                               ; 1237           ;
+; Average fan-out                             ; 3.02           ;
++---------------------------------------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                             ;
++---------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                  ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                    ; Entity Name     ; Library Name ;
++---------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex17                                       ; 164 (0)           ; 154 (0)      ; 73728             ; 0          ; 41   ; 0            ; |ex17                                                                                                                                                  ; ex17            ; work         ;
+;    |clktick_16:GEN_10K|                     ; 20 (20)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex17|clktick_16:GEN_10K                                                                                                                               ; clktick_16      ; work         ;
+;    |hex_to_7seg:SEG0|                       ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex17|hex_to_7seg:SEG0                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:SEG1|                       ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex17|hex_to_7seg:SEG1                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:SEG2|                       ; 3 (3)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex17|hex_to_7seg:SEG2                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |processor:ALLPASS|                      ; 67 (22)           ; 51 (10)      ; 73728             ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS                                                                                                                                ; processor       ; work         ;
+;       |FIFO:fifo|                           ; 45 (0)            ; 40 (0)       ; 73728             ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo                                                                                                                      ; FIFO            ; work         ;
+;          |scfifo:scfifo_component|          ; 45 (0)            ; 40 (0)       ; 73728             ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component                                                                                              ; scfifo          ; work         ;
+;             |scfifo_4l81:auto_generated|    ; 45 (0)            ; 40 (0)       ; 73728             ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated                                                                   ; scfifo_4l81     ; work         ;
+;                |a_dpfifo_br81:dpfifo|       ; 45 (1)            ; 40 (0)       ; 73728             ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo                                              ; a_dpfifo_br81   ; work         ;
+;                   |a_fefifo_4be:fifo_state| ; 18 (5)            ; 14 (1)       ; 0                 ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state                      ; a_fefifo_4be    ; work         ;
+;                      |cntr_di7:count_usedw| ; 13 (13)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7        ; work         ;
+;                   |altsyncram_44t1:FIFOram| ; 0 (0)             ; 0 (0)        ; 73728             ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram                      ; altsyncram_44t1 ; work         ;
+;                   |cntr_1ib:rd_ptr_count|   ; 13 (13)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:rd_ptr_count                        ; cntr_1ib        ; work         ;
+;                   |cntr_1ib:wr_ptr|         ; 13 (13)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:wr_ptr                              ; cntr_1ib        ; work         ;
+;       |d_ff:d|                              ; 0 (0)             ; 1 (1)        ; 0                 ; 0          ; 0    ; 0            ; |ex17|processor:ALLPASS|d_ff:d                                                                                                                         ; d_ff            ; work         ;
+;    |pwm:PWM_DC|                             ; 19 (19)           ; 21 (21)      ; 0                 ; 0          ; 0    ; 0            ; |ex17|pwm:PWM_DC                                                                                                                                       ; pwm             ; work         ;
+;    |spi2adc:SPI_ADC|                        ; 21 (21)           ; 39 (39)      ; 0                 ; 0          ; 0    ; 0            ; |ex17|spi2adc:SPI_ADC                                                                                                                                  ; spi2adc         ; work         ;
+;    |spi2dac:SPI_DAC|                        ; 20 (20)           ; 26 (26)      ; 0                 ; 0          ; 0    ; 0            ; |ex17|spi2dac:SPI_DAC                                                                                                                                  ; spi2dac         ; work         ;
++---------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                            ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; Name                                                                                                                                   ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8192         ; 10           ; 8192         ; 10           ; 81920 ; None ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                    ;
++--------+--------------+---------+--------------+--------------+-----------------------------------+----------------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                   ; IP Include File      ;
++--------+--------------+---------+--------------+--------------+-----------------------------------+----------------------+
+; Altera ; FIFO         ; 16.0    ; N/A          ; N/A          ; |ex17|processor:ALLPASS|FIFO:fifo ; verilog_files/FIFO.v ;
++--------+--------------+---------+--------------+--------------+-----------------------------------+----------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex17|spi2adc:SPI_ADC|sr_state                                           ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex17|spi2dac:SPI_DAC|sr_state                                           ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                               ;
++-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+; Register name                                                                                                                           ; Reason for Removal                     ;
++-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+; spi2dac:SPI_DAC|shift_reg[0,1]                                                                                                          ; Stuck at GND due to stuck port data_in ;
+; spi2dac:SPI_DAC|ctr[4]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[4]     ;
+; spi2dac:SPI_DAC|ctr[3]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[3]     ;
+; spi2dac:SPI_DAC|ctr[2]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[2]     ;
+; spi2dac:SPI_DAC|ctr[1]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[1]     ;
+; spi2dac:SPI_DAC|ctr[0]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[0]     ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_non_empty ; Stuck at VCC due to stuck port data_in ;
+; Total Number of Removed Registers = 8                                                                                                   ;                                        ;
++-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                       ;
++------------------------------+---------------------------+----------------------------------------+
+; Register name                ; Reason for Removal        ; Registers Removed due to This Register ;
++------------------------------+---------------------------+----------------------------------------+
+; spi2dac:SPI_DAC|shift_reg[0] ; Stuck at GND              ; spi2dac:SPI_DAC|shift_reg[1]           ;
+;                              ; due to stuck port data_in ;                                        ;
++------------------------------+---------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 154   ;
+; Number of registers using Synchronous Clear  ; 9     ;
+; Number of registers using Synchronous Load   ; 9     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 71    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; spi2dac:SPI_DAC|dac_cs                 ; 12      ;
+; spi2adc:SPI_ADC|adc_cs                 ; 7       ;
+; Total number of inverted registers = 2 ;         ;
++----------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                   ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                    ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ;
++----------------+-------+----------------------------------------+
+; Parameter Name ; Value ; Type                                   ;
++----------------+-------+----------------------------------------+
+; N_BIT          ; 16    ; Signed Integer                         ;
++----------------+-------+----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; BUF            ; 1     ; Unsigned Binary                     ;
+; GA_N           ; 1     ; Unsigned Binary                     ;
+; SHDN_N         ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; SGL            ; 1     ; Unsigned Binary                     ;
+; MSBF           ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:ALLPASS ;
++----------------+------------+----------------------------------+
+; Parameter Name ; Value      ; Type                             ;
++----------------+------------+----------------------------------+
+; ADC_OFFSET     ; 0110000001 ; Unsigned Binary                  ;
+; DAC_OFFSET     ; 1000000000 ; Unsigned Binary                  ;
++----------------+------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component ;
++-------------------------+-------------+----------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                     ;
++-------------------------+-------------+----------------------------------------------------------+
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                               ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                             ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                             ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                           ;
+; lpm_width               ; 10          ; Signed Integer                                           ;
+; LPM_NUMWORDS            ; 8192        ; Signed Integer                                           ;
+; LPM_WIDTHU              ; 13          ; Signed Integer                                           ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                  ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                  ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                  ;
+; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                  ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                  ;
+; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                  ;
+; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                  ;
+; ENABLE_ECC              ; FALSE       ; Untyped                                                  ;
+; USE_EAB                 ; ON          ; Untyped                                                  ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                  ;
+; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                  ;
+; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                  ;
+; CBXI_PARAMETER          ; scfifo_4l81 ; Untyped                                                  ;
++-------------------------+-------------+----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------+
+; scfifo Parameter Settings by Entity Instance                                     ;
++----------------------------+-----------------------------------------------------+
+; Name                       ; Value                                               ;
++----------------------------+-----------------------------------------------------+
+; Number of entity instances ; 1                                                   ;
+; Entity Instance            ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component ;
+;     -- FIFO Type           ; Single Clock                                        ;
+;     -- lpm_width           ; 10                                                  ;
+;     -- LPM_NUMWORDS        ; 8192                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                 ;
+;     -- USE_EAB             ; ON                                                  ;
++----------------------------+-----------------------------------------------------+
+
+
++----------------------------------------------+
+; Port Connectivity Checks: "hex_to_7seg:SEG2" ;
++----------+-------+----------+----------------+
+; Port     ; Type  ; Severity ; Details        ;
++----------+-------+----------+----------------+
+; in[3..2] ; Input ; Info     ; Stuck at GND   ;
++----------+-------+----------+----------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "spi2adc:SPI_ADC"                                                                          ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port       ; Type   ; Severity ; Details                                                                             ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+; channel    ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; data_valid ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------+
+; Port Connectivity Checks: "clktick_16:GEN_10K" ;
++-----------+-------+----------+-----------------+
+; Port      ; Type  ; Severity ; Details         ;
++-----------+-------+----------+-----------------+
+; enable    ; Input ; Info     ; Stuck at VCC    ;
+; N[9..7]   ; Input ; Info     ; Stuck at VCC    ;
+; N[2..0]   ; Input ; Info     ; Stuck at VCC    ;
+; N[15..13] ; Input ; Info     ; Stuck at GND    ;
+; N[11..10] ; Input ; Info     ; Stuck at GND    ;
+; N[6..3]   ; Input ; Info     ; Stuck at GND    ;
+; N[12]     ; Input ; Info     ; Stuck at VCC    ;
++-----------+-------+----------+-----------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 154                         ;
+;     ENA               ; 71                          ;
+;     SCLR              ; 9                           ;
+;     SLD               ; 9                           ;
+;     plain             ; 65                          ;
+; arriav_lcell_comb     ; 172                         ;
+;     arith             ; 84                          ;
+;         1 data inputs ; 61                          ;
+;         2 data inputs ; 23                          ;
+;     normal            ; 88                          ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 11                          ;
+;         2 data inputs ; 13                          ;
+;         3 data inputs ; 9                           ;
+;         4 data inputs ; 27                          ;
+;         5 data inputs ; 19                          ;
+;         6 data inputs ; 8                           ;
+; boundary_port         ; 41                          ;
+; stratixv_ram_block    ; 9                           ;
+;                       ;                             ;
+; Max LUT depth         ; 3.90                        ;
+; Average LUT depth     ; 1.85                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 11:16:40 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex17 -c ex17
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v
+    Info (12023): Found entity 1: div_by_2 File: C:/New folder/ex17/verilog_files/div_by_2.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v
+    Info (12023): Found entity 1: spi2dac File: C:/New folder/ex17/verilog_files/spi2dac.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v
+    Info (12023): Found entity 1: spi2adc File: C:/New folder/ex17/verilog_files/spi2adc.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/pwm.v
+    Info (12023): Found entity 1: pwm File: C:/New folder/ex17/verilog_files/pwm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v
+    Info (12023): Found entity 1: pulse_gen File: C:/New folder/ex17/verilog_files/pulse_gen.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v
+    Info (12023): Found entity 1: multiply_k File: C:/New folder/ex17/verilog_files/multiply_k.v Line: 39
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex17/verilog_files/hex_to_7seg.v Line: 10
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v
+    Info (12023): Found entity 1: delay_ram File: C:/New folder/ex17/verilog_files/delay_ram.v Line: 39
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v
+    Info (12023): Found entity 1: clktick_16 File: C:/New folder/ex17/verilog_files/clktick_16.v Line: 6
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex17/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/fifo.v
+    Info (12023): Found entity 1: FIFO File: C:/New folder/ex17/verilog_files/FIFO.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/echo_synth.v
+    Info (12023): Found entity 1: processor File: C:/New folder/ex17/verilog_files/echo_synth.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file ex17.v
+    Info (12023): Found entity 1: ex17 File: C:/New folder/ex17/ex17.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v
+    Info (12023): Found entity 1: d_ff File: C:/New folder/ex17/verilog_files/d_ff.v Line: 1
+Critical Warning (10846): Verilog HDL Instantiation warning at echo_synth.v(25): instance has no name File: C:/New folder/ex17/verilog_files/echo_synth.v Line: 25
+Info (12127): Elaborating entity "ex17" for the top level hierarchy
+Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: C:/New folder/ex17/ex17.v Line: 24
+Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: C:/New folder/ex17/ex17.v Line: 26
+Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: C:/New folder/ex17/ex17.v Line: 27
+Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: C:/New folder/ex17/ex17.v Line: 38
+Info (12128): Elaborating entity "processor" for hierarchy "processor:ALLPASS" File: C:/New folder/ex17/ex17.v Line: 40
+Info (12128): Elaborating entity "FIFO" for hierarchy "processor:ALLPASS|FIFO:fifo" File: C:/New folder/ex17/verilog_files/echo_synth.v Line: 19
+Info (12128): Elaborating entity "scfifo" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component" File: C:/New folder/ex17/verilog_files/FIFO.v Line: 73
+Info (12130): Elaborated megafunction instantiation "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component" File: C:/New folder/ex17/verilog_files/FIFO.v Line: 73
+Info (12133): Instantiated megafunction "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component" with the following parameter: File: C:/New folder/ex17/verilog_files/FIFO.v Line: 73
+    Info (12134): Parameter "add_ram_output_register" = "OFF"
+    Info (12134): Parameter "intended_device_family" = "Cyclone V"
+    Info (12134): Parameter "lpm_numwords" = "8192"
+    Info (12134): Parameter "lpm_showahead" = "OFF"
+    Info (12134): Parameter "lpm_type" = "scfifo"
+    Info (12134): Parameter "lpm_width" = "10"
+    Info (12134): Parameter "lpm_widthu" = "13"
+    Info (12134): Parameter "overflow_checking" = "ON"
+    Info (12134): Parameter "underflow_checking" = "ON"
+    Info (12134): Parameter "use_eab" = "ON"
+Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_4l81.tdf
+    Info (12023): Found entity 1: scfifo_4l81 File: C:/New folder/ex17/db/scfifo_4l81.tdf Line: 25
+Info (12128): Elaborating entity "scfifo_4l81" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/scfifo.tdf Line: 300
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_br81.tdf
+    Info (12023): Found entity 1: a_dpfifo_br81 File: C:/New folder/ex17/db/a_dpfifo_br81.tdf Line: 29
+Info (12128): Elaborating entity "a_dpfifo_br81" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo" File: C:/New folder/ex17/db/scfifo_4l81.tdf Line: 35
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_4be.tdf
+    Info (12023): Found entity 1: a_fefifo_4be File: C:/New folder/ex17/db/a_fefifo_4be.tdf Line: 25
+Info (12128): Elaborating entity "a_fefifo_4be" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state" File: C:/New folder/ex17/db/a_dpfifo_br81.tdf Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_di7.tdf
+    Info (12023): Found entity 1: cntr_di7 File: C:/New folder/ex17/db/cntr_di7.tdf Line: 26
+Info (12128): Elaborating entity "cntr_di7" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw" File: C:/New folder/ex17/db/a_fefifo_4be.tdf Line: 38
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_44t1.tdf
+    Info (12023): Found entity 1: altsyncram_44t1 File: C:/New folder/ex17/db/altsyncram_44t1.tdf Line: 28
+Info (12128): Elaborating entity "altsyncram_44t1" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram" File: C:/New folder/ex17/db/a_dpfifo_br81.tdf Line: 41
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ib.tdf
+    Info (12023): Found entity 1: cntr_1ib File: C:/New folder/ex17/db/cntr_1ib.tdf Line: 26
+Info (12128): Elaborating entity "cntr_1ib" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:rd_ptr_count" File: C:/New folder/ex17/db/a_dpfifo_br81.tdf Line: 42
+Info (12128): Elaborating entity "d_ff" for hierarchy "processor:ALLPASS|d_ff:d" File: C:/New folder/ex17/verilog_files/echo_synth.v Line: 21
+Info (12128): Elaborating entity "div_by_2" for hierarchy "processor:ALLPASS|div_by_2:comb_5" File: C:/New folder/ex17/verilog_files/echo_synth.v Line: 25
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex17/ex17.v Line: 42
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|q_b[0]" File: C:/New folder/ex17/db/altsyncram_44t1.tdf Line: 40
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX2[1]" is stuck at GND File: C:/New folder/ex17/ex17.v Line: 7
+Info (286030): Timing-Driven Synthesis is running
+Info (144001): Generated suppressed messages file C:/New folder/ex17/output_files/ex17.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 10 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "SW[0]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[1]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[2]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[3]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[4]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[5]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[6]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[7]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[8]" File: C:/New folder/ex17/ex17.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[9]" File: C:/New folder/ex17/ex17.v Line: 6
+Info (21057): Implemented 255 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 12 input pins
+    Info (21059): Implemented 29 output pins
+    Info (21061): Implemented 205 logic cells
+    Info (21064): Implemented 9 RAM segments
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings
+    Info: Peak virtual memory: 903 megabytes
+    Info: Processing ended: Fri Dec 02 11:16:51 2016
+    Info: Elapsed time: 00:00:11
+    Info: Total CPU time (on all processors): 00:00:23
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in C:/New folder/ex17/output_files/ex17.map.smsg.
+
+
diff --git a/part_2/ex9_final/output_files/ex9.map.smsg b/part_4/ex17/output_files/ex17.map.smsg
index e17538c..c810b0d 100755
--- a/part_2/ex9_final/output_files/ex9.map.smsg
+++ b/part_4/ex17/output_files/ex17.map.smsg
@@ -1,38 +1,35 @@
-Warning (10268): Verilog HDL information at formula_fsm.v(38): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 38
-Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: C:/New folder/ex9/verilog_files/delay.v Line: 7
-Warning (10268): Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex9/verilog_files/counter_16.v Line: 16
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex17/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_4/ex17/output_files/ex17.map.summary b/part_4/ex17/output_files/ex17.map.summary
new file mode 100755
index 0000000..13a8c00
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Fri Dec 02 11:16:51 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex17
+Top-level Entity Name : ex17
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 154
+Total pins : 41
+Total virtual pins : 0
+Total block memory bits : 73,728
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_4/ex17/output_files/ex17.pin b/part_4/ex17/output_files/ex17.pin
new file mode 100755
index 0000000..cce47ba
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       3.3V
+ --                  Bank 3B:       3.3V
+ --                  Bank 4A:       3.3V
+ --                  Bank 5A:       3.3V
+ --                  Bank 5B:       3.3V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex17"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 3.3V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+SW[0]                        : AB12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 5A        :                
+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB28      :        :                   :         : 5B        :                
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+SW[7]                        : AC9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3A                      : AC10      : power  :                   : 3.3V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 3.3V    : 3A        :                
+SW[1]                        : AC12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC25      :        :                   :         : 5A        :                
+GND                          : AC26      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC27      :        :                   :         : 5A        :                
+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+SW[8]                        : AD10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[4]                        : AD11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[5]                        : AD12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+DAC_CS                       : AD20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD26      :        :                   :         : 5A        :                
+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+SW[6]                        : AE11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[9]                        : AE12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+SW[2]                        : AF9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[3]                        : AF10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+DAC_SCK                      : AF20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SCK                      : AF21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+DAC_SDI                      : AG18      : output : 3.3-V LVTTL       :         : 4A        : Y              
+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
+ADC_CS                       : AG20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SDI                      : AG21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+PWM_OUT                      : AJ20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SDO                      : AJ21      : input  : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
+DAC_LD                       : AK21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23       :        :                   :         : 5A        :                
+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
+GND                          : W18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5A        :                
+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W24       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24       :        :                   :         : 5A        :                
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_4/ex17/output_files/ex17.sld b/part_4/ex17/output_files/ex17.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/part_4/ex17/output_files/ex17.sof b/part_4/ex17/output_files/ex17.sof
new file mode 100755
index 0000000..a2f4d3f
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.sof
diff --git a/part_4/ex17/output_files/ex17.sta.rpt b/part_4/ex17/output_files/ex17.sta.rpt
new file mode 100755
index 0000000..266a932
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.sta.rpt
@@ -0,0 +1,901 @@
+TimeQuest Timing Analyzer report for ex17
+Fri Dec 02 11:17:42 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex17                                                    ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CSEMA5F31C6                                            ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.19        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   6.5%      ;
+;     Processor 3            ;   6.4%      ;
+;     Processor 4            ;   6.3%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                             ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+; Clock Name               ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                      ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+; clktick_16:GEN_10K|tick  ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clktick_16:GEN_10K|tick }  ;
+; CLOCK_50                 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                 ;
+; spi2adc:SPI_ADC|clk_1MHz ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2adc:SPI_ADC|clk_1MHz } ;
+; spi2dac:SPI_DAC|clk_1MHz ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2dac:SPI_DAC|clk_1MHz } ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary                             ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 166.83 MHz ; 166.83 MHz      ; CLOCK_50                 ;      ;
+; 223.71 MHz ; 223.71 MHz      ; spi2adc:SPI_ADC|clk_1MHz ;      ;
+; 406.83 MHz ; 406.83 MHz      ; spi2dac:SPI_DAC|clk_1MHz ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary               ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -4.994 ; -1215.299     ;
+; spi2dac:SPI_DAC|clk_1MHz ; -4.053 ; -66.004       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -3.114 ; -53.900       ;
+; clktick_16:GEN_10K|tick  ; -2.678 ; -2.678        ;
++--------------------------+--------+---------------+
+
+
++--------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary               ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; CLOCK_50                 ; 0.216 ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.562 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.714 ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 1.976 ; 0.000         ;
++--------------------------+-------+---------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1383.263     ;
+; spi2adc:SPI_ADC|clk_1MHz ; -0.394 ; -17.619       ;
+; spi2dac:SPI_DAC|clk_1MHz ; -0.394 ; -11.427       ;
+; clktick_16:GEN_10K|tick  ; -0.394 ; -0.606        ;
++--------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                              ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 165.29 MHz ; 165.29 MHz      ; CLOCK_50                 ;      ;
+; 245.7 MHz  ; 245.7 MHz       ; spi2adc:SPI_ADC|clk_1MHz ;      ;
+; 423.37 MHz ; 423.37 MHz      ; spi2dac:SPI_DAC|clk_1MHz ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -5.050 ; -1121.685     ;
+; spi2dac:SPI_DAC|clk_1MHz ; -4.187 ; -67.782       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -3.261 ; -52.098       ;
+; clktick_16:GEN_10K|tick  ; -2.847 ; -2.847        ;
++--------------------------+--------+---------------+
+
+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary                ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; CLOCK_50                 ; 0.151 ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.589 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.708 ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 2.149 ; 0.000         ;
++--------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary  ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1374.432     ;
+; spi2adc:SPI_ADC|clk_1MHz ; -0.394 ; -17.072       ;
+; spi2dac:SPI_DAC|clk_1MHz ; -0.394 ; -11.267       ;
+; clktick_16:GEN_10K|tick  ; -0.394 ; -0.616        ;
++--------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary               ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -3.284 ; -731.582      ;
+; spi2dac:SPI_DAC|clk_1MHz ; -2.019 ; -29.840       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -1.371 ; -26.126       ;
+; clktick_16:GEN_10K|tick  ; -1.141 ; -1.141        ;
++--------------------------+--------+---------------+
+
+
++--------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary               ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; CLOCK_50                 ; 0.129 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.300 ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.330 ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 0.863 ; 0.000         ;
++--------------------------+-------+---------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1382.020     ;
+; clktick_16:GEN_10K|tick  ; 0.019  ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.104  ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.152  ; 0.000         ;
++--------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.747 ; -575.387      ;
+; spi2dac:SPI_DAC|clk_1MHz ; -1.914 ; -28.398       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -1.344 ; -23.465       ;
+; clktick_16:GEN_10K|tick  ; -1.139 ; -1.139        ;
++--------------------------+--------+---------------+
+
+
++--------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary                ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; CLOCK_50                 ; 0.088 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.274 ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.296 ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 0.878 ; 0.000         ;
++--------------------------+-------+---------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary  ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1412.607     ;
+; clktick_16:GEN_10K|tick  ; 0.039  ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.119  ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.150  ; 0.000         ;
++--------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                      ;
++---------------------------+-----------+-------+----------+---------+---------------------+
+; Clock                     ; Setup     ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++---------------------------+-----------+-------+----------+---------+---------------------+
+; Worst-case Slack          ; -5.050    ; 0.088 ; N/A      ; N/A     ; -2.174              ;
+;  CLOCK_50                 ; -5.050    ; 0.088 ; N/A      ; N/A     ; -2.174              ;
+;  clktick_16:GEN_10K|tick  ; -2.847    ; 0.863 ; N/A      ; N/A     ; -0.394              ;
+;  spi2adc:SPI_ADC|clk_1MHz ; -3.261    ; 0.296 ; N/A      ; N/A     ; -0.394              ;
+;  spi2dac:SPI_DAC|clk_1MHz ; -4.187    ; 0.274 ; N/A      ; N/A     ; -0.394              ;
+; Design-wide TNS           ; -1337.881 ; 0.0   ; 0.0      ; 0.0     ; -1412.915           ;
+;  CLOCK_50                 ; -1215.299 ; 0.000 ; N/A      ; N/A     ; -1412.607           ;
+;  clktick_16:GEN_10K|tick  ; -2.847    ; 0.000 ; N/A      ; N/A     ; -0.616              ;
+;  spi2adc:SPI_ADC|clk_1MHz ; -53.900   ; 0.000 ; N/A      ; N/A     ; -17.619             ;
+;  spi2dac:SPI_DAC|clk_1MHz ; -67.782   ; 0.000 ; N/A      ; N/A     ; -11.427             ;
++---------------------------+-----------+-------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; SW[0]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ADC_SDO  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX0[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX1[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; HEX2[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; HEX2[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                 ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; From Clock               ; To Clock                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; CLOCK_50                 ; clktick_16:GEN_10K|tick  ; 1        ; 0        ; 0        ; 0        ;
+; clktick_16:GEN_10K|tick  ; CLOCK_50                 ; 199      ; 162      ; 0        ; 0        ;
+; CLOCK_50                 ; CLOCK_50                 ; 1194     ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 1089     ; 1        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; CLOCK_50                 ; 5        ; 1        ; 0        ; 0        ;
+; CLOCK_50                 ; spi2adc:SPI_ADC|clk_1MHz ; 3        ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; 62       ; 11       ; 20       ; 9        ;
+; CLOCK_50                 ; spi2dac:SPI_DAC|clk_1MHz ; 26       ; 0        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; 61       ; 0        ; 0        ; 0        ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                  ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; From Clock               ; To Clock                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; CLOCK_50                 ; clktick_16:GEN_10K|tick  ; 1        ; 0        ; 0        ; 0        ;
+; clktick_16:GEN_10K|tick  ; CLOCK_50                 ; 199      ; 162      ; 0        ; 0        ;
+; CLOCK_50                 ; CLOCK_50                 ; 1194     ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 1089     ; 1        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; CLOCK_50                 ; 5        ; 1        ; 0        ; 0        ;
+; CLOCK_50                 ; spi2adc:SPI_ADC|clk_1MHz ; 3        ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; 62       ; 11       ; 20       ; 9        ;
+; CLOCK_50                 ; spi2dac:SPI_DAC|clk_1MHz ; 26       ; 0        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; 61       ; 0        ; 0        ; 0        ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 1     ; 1    ;
+; Unconstrained Input Port Paths  ; 1     ; 1    ;
+; Unconstrained Output Ports      ; 28    ; 28   ;
+; Unconstrained Output Port Paths ; 76    ; 76   ;
++---------------------------------+-------+------+
+
+
++--------------------------------------------------------------------------+
+; Clock Status Summary                                                     ;
++--------------------------+--------------------------+------+-------------+
+; Target                   ; Clock                    ; Type ; Status      ;
++--------------------------+--------------------------+------+-------------+
+; CLOCK_50                 ; CLOCK_50                 ; Base ; Constrained ;
+; clktick_16:GEN_10K|tick  ; clktick_16:GEN_10K|tick  ; Base ; Constrained ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; Base ; Constrained ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; Base ; Constrained ;
++--------------------------+--------------------------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 11:17:36 2016
+Info: Command: quartus_sta ex17 -c ex17
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex17.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+    Info (332105): create_clock -period 1.000 -name clktick_16:GEN_10K|tick clktick_16:GEN_10K|tick
+    Info (332105): create_clock -period 1.000 -name spi2adc:SPI_ADC|clk_1MHz spi2adc:SPI_ADC|clk_1MHz
+    Info (332105): create_clock -period 1.000 -name spi2dac:SPI_DAC|clk_1MHz spi2dac:SPI_DAC|clk_1MHz
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -4.994
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -4.994           -1215.299 CLOCK_50 
+    Info (332119):    -4.053             -66.004 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -3.114             -53.900 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -2.678              -2.678 clktick_16:GEN_10K|tick 
+Info (332146): Worst-case hold slack is 0.216
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.216               0.000 CLOCK_50 
+    Info (332119):     0.562               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.714               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     1.976               0.000 clktick_16:GEN_10K|tick 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174           -1383.263 CLOCK_50 
+    Info (332119):    -0.394             -17.619 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.394             -11.427 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -0.394              -0.606 clktick_16:GEN_10K|tick 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -5.050
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -5.050           -1121.685 CLOCK_50 
+    Info (332119):    -4.187             -67.782 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -3.261             -52.098 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -2.847              -2.847 clktick_16:GEN_10K|tick 
+Info (332146): Worst-case hold slack is 0.151
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.151               0.000 CLOCK_50 
+    Info (332119):     0.589               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.708               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     2.149               0.000 clktick_16:GEN_10K|tick 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174           -1374.432 CLOCK_50 
+    Info (332119):    -0.394             -17.072 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.394             -11.267 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -0.394              -0.616 clktick_16:GEN_10K|tick 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.284
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.284            -731.582 CLOCK_50 
+    Info (332119):    -2.019             -29.840 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -1.371             -26.126 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -1.141              -1.141 clktick_16:GEN_10K|tick 
+Info (332146): Worst-case hold slack is 0.129
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.129               0.000 CLOCK_50 
+    Info (332119):     0.300               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     0.330               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.863               0.000 clktick_16:GEN_10K|tick 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174           -1382.020 CLOCK_50 
+    Info (332119):     0.019               0.000 clktick_16:GEN_10K|tick 
+    Info (332119):     0.104               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.152               0.000 spi2dac:SPI_DAC|clk_1MHz 
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.747
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.747            -575.387 CLOCK_50 
+    Info (332119):    -1.914             -28.398 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -1.344             -23.465 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -1.139              -1.139 clktick_16:GEN_10K|tick 
+Info (332146): Worst-case hold slack is 0.088
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.088               0.000 CLOCK_50 
+    Info (332119):     0.274               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     0.296               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.878               0.000 clktick_16:GEN_10K|tick 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174           -1412.607 CLOCK_50 
+    Info (332119):     0.039               0.000 clktick_16:GEN_10K|tick 
+    Info (332119):     0.119               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.150               0.000 spi2dac:SPI_DAC|clk_1MHz 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 1237 megabytes
+    Info: Processing ended: Fri Dec 02 11:17:42 2016
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:07
+
+
diff --git a/part_4/ex17/output_files/ex17.sta.summary b/part_4/ex17/output_files/ex17.sta.summary
new file mode 100755
index 0000000..4804e39
--- /dev/null
+++ b/part_4/ex17/output_files/ex17.sta.summary
@@ -0,0 +1,197 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -4.994
+TNS   : -1215.299
+
+Type  : Slow 1100mV 85C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -4.053
+TNS   : -66.004
+
+Type  : Slow 1100mV 85C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -3.114
+TNS   : -53.900
+
+Type  : Slow 1100mV 85C Model Setup 'clktick_16:GEN_10K|tick'
+Slack : -2.678
+TNS   : -2.678
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.216
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.562
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.714
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'clktick_16:GEN_10K|tick'
+Slack : 1.976
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1383.263
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -0.394
+TNS   : -17.619
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -0.394
+TNS   : -11.427
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'clktick_16:GEN_10K|tick'
+Slack : -0.394
+TNS   : -0.606
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -5.050
+TNS   : -1121.685
+
+Type  : Slow 1100mV 0C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -4.187
+TNS   : -67.782
+
+Type  : Slow 1100mV 0C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -3.261
+TNS   : -52.098
+
+Type  : Slow 1100mV 0C Model Setup 'clktick_16:GEN_10K|tick'
+Slack : -2.847
+TNS   : -2.847
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.151
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.589
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.708
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'clktick_16:GEN_10K|tick'
+Slack : 2.149
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1374.432
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -0.394
+TNS   : -17.072
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -0.394
+TNS   : -11.267
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'clktick_16:GEN_10K|tick'
+Slack : -0.394
+TNS   : -0.616
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -3.284
+TNS   : -731.582
+
+Type  : Fast 1100mV 85C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -2.019
+TNS   : -29.840
+
+Type  : Fast 1100mV 85C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -1.371
+TNS   : -26.126
+
+Type  : Fast 1100mV 85C Model Setup 'clktick_16:GEN_10K|tick'
+Slack : -1.141
+TNS   : -1.141
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.129
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.300
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.330
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'clktick_16:GEN_10K|tick'
+Slack : 0.863
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1382.020
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'clktick_16:GEN_10K|tick'
+Slack : 0.019
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.104
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.152
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -2.747
+TNS   : -575.387
+
+Type  : Fast 1100mV 0C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -1.914
+TNS   : -28.398
+
+Type  : Fast 1100mV 0C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -1.344
+TNS   : -23.465
+
+Type  : Fast 1100mV 0C Model Setup 'clktick_16:GEN_10K|tick'
+Slack : -1.139
+TNS   : -1.139
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.088
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.274
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.296
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'clktick_16:GEN_10K|tick'
+Slack : 0.878
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1412.607
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'clktick_16:GEN_10K|tick'
+Slack : 0.039
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.119
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.150
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_4/ex17/verilog_files/FIFO.qip b/part_4/ex17/verilog_files/FIFO.qip
new file mode 100755
index 0000000..5559867
--- /dev/null
+++ b/part_4/ex17/verilog_files/FIFO.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "FIFO.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FIFO_bb.v"]
diff --git a/part_4/ex17/verilog_files/FIFO.v b/part_4/ex17/verilog_files/FIFO.v
new file mode 100755
index 0000000..07ece20
--- /dev/null
+++ b/part_4/ex17/verilog_files/FIFO.v
@@ -0,0 +1,153 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: FIFO.v
+// Megafunction Name(s):
+// 			scfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module FIFO (
+	clock,
+	data,
+	rdreq,
+	wrreq,
+	full,
+	q);
+
+	input	  clock;
+	input	[9:0]  data;
+	input	  rdreq;
+	input	  wrreq;
+	output	  full;
+	output	[9:0]  q;
+
+	wire  sub_wire0;
+	wire [9:0] sub_wire1;
+	wire  full = sub_wire0;
+	wire [9:0] q = sub_wire1[9:0];
+
+	scfifo	scfifo_component (
+				.clock (clock),
+				.data (data),
+				.rdreq (rdreq),
+				.wrreq (wrreq),
+				.full (sub_wire0),
+				.q (sub_wire1),
+				.aclr (),
+				.almost_empty (),
+				.almost_full (),
+				.eccstatus (),
+				.empty (),
+				.sclr (),
+				.usedw ());
+	defparam
+		scfifo_component.add_ram_output_register = "OFF",
+		scfifo_component.intended_device_family = "Cyclone V",
+		scfifo_component.lpm_numwords = 8192,
+		scfifo_component.lpm_showahead = "OFF",
+		scfifo_component.lpm_type = "scfifo",
+		scfifo_component.lpm_width = 10,
+		scfifo_component.lpm_widthu = 13,
+		scfifo_component.overflow_checking = "ON",
+		scfifo_component.underflow_checking = "ON",
+		scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "8192"
+// Retrieval info: PRIVATE: Empty NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "10"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "10"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex17/verilog_files/FIFO_bb.v b/part_4/ex17/verilog_files/FIFO_bb.v
new file mode 100755
index 0000000..7e480c2
--- /dev/null
+++ b/part_4/ex17/verilog_files/FIFO_bb.v
@@ -0,0 +1,116 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: FIFO.v
+// Megafunction Name(s):
+// 			scfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module FIFO (
+	clock,
+	data,
+	rdreq,
+	wrreq,
+	full,
+	q);
+
+	input	  clock;
+	input	[9:0]  data;
+	input	  rdreq;
+	input	  wrreq;
+	output	  full;
+	output	[9:0]  q;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "8192"
+// Retrieval info: PRIVATE: Empty NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "10"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "10"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex17/verilog_files/add3_ge5.v b/part_4/ex17/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..0daf78a
--- /dev/null
+++ b/part_4/ex17/verilog_files/add3_ge5.v
@@ -0,0 +1,31 @@
+//------------------------------
+// Module name: add3_ge5
+// Function: Add 3 to input if it is 5 or above
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     21 Jan 2014
+//------------------------------
+
+module add3_ge5(w,a); 
+	input [3:0] w; 
+	output [3:0] a; 
+	reg [3:0] a; 
+ 
+	always @ (w) 
+		case (w) 
+			4'b0000: a <= 4'b0000; 
+			4'b0001: a <= 4'b0001; 
+			4'b0010: a <= 4'b0010; 
+			4'b0011: a <= 4'b0011; 
+			4'b0100: a <= 4'b0100; 
+			4'b0101: a <= 4'b1000; 
+			4'b0110: a <= 4'b1001; 
+			4'b0111: a <= 4'b1010; 
+			4'b1000: a <= 4'b1011; 
+			4'b1001: a <= 4'b1100;
+			4'b1010: a <= 4'b1101;	
+			4'b1011: a <= 4'b1110;	
+			4'b1100: a <= 4'b1111;	
+			default: a <= 4'b0000; // a cannot be 13 or larger, else overflow
+		endcase 
+endmodule 
+\ No newline at end of file
diff --git a/part_2/ex9_partially_working/verilog_files/bin2bcd_16.v b/part_4/ex17/verilog_files/bin2bcd_16.v
index b25d0bd..b25d0bd 100755
--- a/part_2/ex9_partially_working/verilog_files/bin2bcd_16.v
+++ b/part_4/ex17/verilog_files/bin2bcd_16.v
diff --git a/part_4/ex17/verilog_files/clktick_16.v b/part_4/ex17/verilog_files/clktick_16.v
new file mode 100755
index 0000000..e6b99eb
--- /dev/null
+++ b/part_4/ex17/verilog_files/clktick_16.v
@@ -0,0 +1,42 @@
+// Design Name : clktick_16
+// File Name : clktick.v
+// Function : divide an input clock signal by n+1
+//-----------------------------------------------------
+
+module clktick_16 (
+  clkin, 	// Clock input to the design
+  enable,	// enable clk divider
+  N,			// Clock division factor is N+1
+  tick		// pulse_out goes high for one cycle (n+1) clock cycles
+); 			// 	End of port list
+
+parameter	N_BIT = 16;
+//-------------Input Ports-----------------------------
+input clkin;
+input enable;
+input [N_BIT-1:0] N;
+
+//-------------Output Ports----------------------------
+output 	tick;
+
+//-------------Output Ports Data Type------------------
+// Output port can be a storage element (reg) or a wire
+reg [N_BIT-1:0] count;
+reg			tick;
+
+initial		tick = 1'b0;
+
+//------------ Main Body of the module ------------------------
+
+	always @ (posedge clkin)  
+		if (enable == 1'b1)
+			if (count == 0)	begin
+				tick <= 1'b1;
+				count <= N;
+				end
+			else	begin
+				tick <= 1'b0;
+				count <= count - 1'b1;
+				end
+		
+endmodule // End of Module clktick
+\ No newline at end of file
diff --git a/part_4/ex17/verilog_files/d_ff.v b/part_4/ex17/verilog_files/d_ff.v
new file mode 100755
index 0000000..65aec4d
--- /dev/null
+++ b/part_4/ex17/verilog_files/d_ff.v
@@ -0,0 +1,11 @@
+module d_ff(clk, in, out);
+
+	input clk, in;
+	output out;
+	wire in;
+	reg out;
+
+	always @ (posedge clk)
+		out <= in;
+
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex17/verilog_files/d_ff.v.bak b/part_4/ex17/verilog_files/d_ff.v.bak
new file mode 100755
index 0000000..1463387
--- /dev/null
+++ b/part_4/ex17/verilog_files/d_ff.v.bak
@@ -0,0 +1,6 @@
+module d_ff(clk, in, out);
+
+	always @ (posedge clk)
+		in <= out;
+
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex17/verilog_files/delay_ram.v b/part_4/ex17/verilog_files/delay_ram.v
new file mode 100755
index 0000000..23d49af
--- /dev/null
+++ b/part_4/ex17/verilog_files/delay_ram.v
@@ -0,0 +1,220 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: delay_ram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module delay_ram (
+	clock,
+	data,
+	rdaddress,
+	rden,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[8:0]  data;
+	input	[12:0]  rdaddress;
+	input	  rden;
+	input	[12:0]  wraddress;
+	input	  wren;
+	output	[8:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [8:0] sub_wire0;
+	wire [8:0] q = sub_wire0[8:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.rden_b (rden),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({9{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 8192,
+		altsyncram_component.numwords_b = 8192,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "CLOCK0",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.rdcontrol_reg_b = "CLOCK0",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 13,
+		altsyncram_component.widthad_b = 13,
+		altsyncram_component.width_a = 9,
+		altsyncram_component.width_b = 9,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
+// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
+// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex17/verilog_files/div_by_2.v b/part_4/ex17/verilog_files/div_by_2.v
new file mode 100755
index 0000000..11b8e75
--- /dev/null
+++ b/part_4/ex17/verilog_files/div_by_2.v
@@ -0,0 +1,8 @@
+module div_by_2(in, out);
+
+	input signed [9:0] in;
+	output signed [9:0] out;
+	
+	assign out = in >>> 1;
+	
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex17/verilog_files/div_by_4.v.bak b/part_4/ex17/verilog_files/div_by_4.v.bak
new file mode 100755
index 0000000..8ceab41
--- /dev/null
+++ b/part_4/ex17/verilog_files/div_by_4.v.bak
@@ -0,0 +1,8 @@
+module div_by_4(in, out);
+
+	input in;
+	output out;
+	
+	assign out = in >> 2;
+	
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex17/verilog_files/echo_synth.v b/part_4/ex17/verilog_files/echo_synth.v
new file mode 100755
index 0000000..d5507b5
--- /dev/null
+++ b/part_4/ex17/verilog_files/echo_synth.v
@@ -0,0 +1,34 @@
+module processor (sysclk, tick, data_in, data_out);
+
+	input				sysclk, tick;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+	wire [9:0]		tmp_data, echoed_data;
+	wire is_full, and_if, from_dff;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	FIFO fifo(sysclk, x, and_if, tick, is_full, tmp_data);
+	
+	d_ff d(tick, is_full, from_dff);
+	
+	assign and_if = tick & from_dff;
+	
+	div_by_2(tmp_data, echoed_data);
+		
+	assign y = x + echoed_data;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex17/verilog_files/echo_synth.v.bak b/part_4/ex17/verilog_files/echo_synth.v.bak
new file mode 100755
index 0000000..91d95dc
--- /dev/null
+++ b/part_4/ex17/verilog_files/echo_synth.v.bak
@@ -0,0 +1,27 @@
+module processor (sysclk, data_in, data_out);
+
+	input				sysclk;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	// This part should include your own processing hardware 
+	// ... that takes x to produce y
+	// ... In this case, it is ALL PASS.
+	assign y = x;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex17/verilog_files/hex_to_7seg.v b/part_4/ex17/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..1c39f02
--- /dev/null
+++ b/part_4/ex17/verilog_files/hex_to_7seg.v
@@ -0,0 +1,38 @@
+//------------------------------
+// Module name: hex_to_7seg
+// Function: convert 4-bit hex value to drive 7 segment display
+//           output is low active - using case statement
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     23 Oct 2011
+//------------------------------
+
+module hex_to_7seg	(out,in);
+
+	output	[6:0]	out;    // low-active output to drive 7 segment display
+	input	[3:0]	in;		// 4-bit binary input of a hexademical number
+	
+	reg		[6:0]	out;	// make out a variable for use in procedural assignment
+	
+	always @ (in)
+	  case (in)
+		4'h0: out = 7'b1000000;
+		4'h1: out = 7'b1111001;		// -- 0 ---
+		4'h2: out = 7'b0100100; 	// |	  |
+		4'h3: out = 7'b0110000; 	// 5      1
+		4'h4: out = 7'b0011001; 	// |	  |
+		4'h5: out = 7'b0010010; 	// -- 6 ---
+		4'h6: out = 7'b0000010; 	// |	  |
+		4'h7: out = 7'b1111000; 	// 4      2
+		4'h8: out = 7'b0000000; 	// |	  |
+		4'h9: out = 7'b0011000; 	// -- 3 ---
+		4'ha: out = 7'b0001000;
+		4'hb: out = 7'b0000011;
+		4'hc: out = 7'b1000110;
+		4'hd: out = 7'b0100001;
+		4'he: out = 7'b0000110;
+		4'hf: out = 7'b0001110;
+	  endcase
+endmodule
+
+
diff --git a/part_4/ex17/verilog_files/multiply_k.v b/part_4/ex17/verilog_files/multiply_k.v
new file mode 100755
index 0000000..8292b58
--- /dev/null
+++ b/part_4/ex17/verilog_files/multiply_k.v
@@ -0,0 +1,107 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: multiply_k.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module multiply_k (
+	dataa,
+	result);
+
+	input	[8:0]  dataa;
+	output	[19:0]  result;
+
+	wire [19:0] sub_wire0;
+	wire [10:0] sub_wire1 = 11'h666;
+	wire [19:0] result = sub_wire0[19:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (sub_wire1),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 9,
+		lpm_mult_component.lpm_widthb = 11,
+		lpm_mult_component.lpm_widthp = 20;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "1638"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "9"
+// Retrieval info: PRIVATE: WidthB NUMERIC "11"
+// Retrieval info: PRIVATE: WidthP NUMERIC "20"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20"
+// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
+// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]"
+// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
+// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0
+// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_4/ex17/verilog_files/pulse_gen.v b/part_4/ex17/verilog_files/pulse_gen.v
new file mode 100755
index 0000000..d82fe49
--- /dev/null
+++ b/part_4/ex17/verilog_files/pulse_gen.v
@@ -0,0 +1,43 @@
+//------------------------------
+// Module name: pulse_gen (Moore)
+// Function: Generate one clock pulse on +ve edge of input
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     29 Jan 2014
+//------------------------------
+
+module pulse_gen(pulse, in, clk);
+
+	output 			pulse;	// output pulse lasting one clk cycle
+	input 			in;		// input, +ve edge to be detected
+	input 			clk;		// clock signal
+
+	reg [1:0]	state;
+	reg	pulse;
+	
+	parameter	IDLE = 2'b0;	// state coding for IDLE state
+	parameter	IN_HIGH = 2'b01;
+	parameter	WAIT_LOW = 2'b10;  
+	
+	initial state = IDLE;
+	
+	always @ (posedge clk) 
+		begin	
+			pulse <= 0;		 // default output
+			case (state)
+			IDLE: 	if (in == 1'b1) begin
+							state <= IN_HIGH;	pulse <= 1'b1; end
+						else 
+							state <= IDLE; 
+			IN_HIGH: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						else 
+							state <= IDLE; 
+			WAIT_LOW: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						 else  
+							state <= IDLE;
+			default: ;
+			endcase
+		end			//... always
+endmodule
diff --git a/part_4/ex17/verilog_files/pwm.v b/part_4/ex17/verilog_files/pwm.v
new file mode 100755
index 0000000..c3b34d9
--- /dev/null
+++ b/part_4/ex17/verilog_files/pwm.v
@@ -0,0 +1,25 @@
+module pwm (clk, data_in, load, pwm_out);
+
+	input				clk;			// system clock
+	input [9:0] 	data_in;		// input data for conversion
+	input 			load;			// high pulse to load new data
+	output			pwm_out;		// PWM output
+
+	reg [9:0]		d;				// internal register
+	reg [9:0]		count;		// internal 10-bit counter
+	reg				pwm_out;
+
+	always @ (posedge clk)
+		if (load == 1'b1) d <= data_in;
+	
+	initial count = 10'b0;	
+	
+	always @ (posedge clk) begin
+		count <= count + 1'b1;
+		if (count > d)
+			pwm_out <= 1'b0;
+		else	
+			pwm_out <= 1'b1;
+		end
+
+endmodule
diff --git a/part_4/ex17/verilog_files/spi2adc.v b/part_4/ex17/verilog_files/spi2adc.v
new file mode 100755
index 0000000..3878f71
--- /dev/null
+++ b/part_4/ex17/verilog_files/spi2adc.v
@@ -0,0 +1,150 @@
+//------------------------------
+// Module name: spi2adc
+// Function: SPI interface for MCP3002 ADC
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     24 Jan 2014
+//------------------------------
+
+module spi2adc (sysclk, start, channel, data_from_adc, data_valid, 
+						sdata_to_adc, adc_cs, adc_sck, sdata_from_adc);
+
+	input	sysclk;			// 50MHz system clock of DE0
+	input	start;			// Pulse to start ADC, minimum wide = clock period
+	input	channel;			// channel 0 or 1 to be converted
+	output [9:0] data_from_adc;	// 10-bit ADC result
+	output data_valid;	// High indicates that converted data valid
+	output sdata_to_adc;	// Serial commands send to adc chip
+	output adc_cs;			// chip select - low when converting
+	output adc_sck;		// SPI clock - active during conversion
+	input sdata_from_adc;	// Converted serial data from ADC, MSB first
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire	sysclk, start, sdata_from_adc;
+
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg [9:0]	data_from_adc;
+	reg			adc_cs;
+	wire			sdata_to_adc, adc_sck, data_valid;
+	
+//-------------Configuration parameters for ADC --------
+	parameter	SGL=1'b1;	// 0:diff i/p, 1:single-ended
+	parameter	MSBF=1'b1;	// 0:LSB first, 1:MSB first
+			
+// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... to start.  Initialise to make simulation easier
+	end
+		
+	always @ (posedge sysclk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+// ---- end internal clock generator ----------
+
+// ---- Detect start is asserted with a small state machine
+	// .... FF set on positive edge of start
+	// .... reset when adc_cs goes high again
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			adc_start;
+	
+	initial begin
+		sr_state = IDLE;
+		adc_start = 1'b0;	// set while sending data to ADC
+		end
+	
+	always @ (posedge sysclk)
+		case (sr_state)
+			IDLE:	if (start==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						adc_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (adc_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (adc_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						adc_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+//------- End circuit to detect start and end of conversion	
+
+	
+// spi controller designed as a state machine
+// .... with 16 states (idle, and S1-S15 indicated by state value
+
+	reg [4:0] 	state;
+	reg  	adc_done, adc_din, shift_ena;
+	
+	initial	begin	
+		state = 5'b0; adc_cs = 1'b1; adc_done = 1'b0; 
+		adc_din = 1'b0; shift_ena <= 1'b0;
+		end
+		
+	always @(posedge clk_1MHz)  begin
+	
+	// default outputs and state transition
+		adc_cs <= 1'b0;  adc_done <= 1'b0;  adc_din <= 1'b0; shift_ena <= 1'b0;
+		state <= state + 1'b1;
+		case (state)
+			5'd0:	begin
+						if (adc_start==1'b0) begin
+							state <= 5'd0;			// still idle
+							adc_cs <= 1'b1;		// chip select not active
+							end
+						else begin
+							state <= 5'd1;			// start converting
+							adc_din <= 1'b1;		// start bit is 1
+							end
+					end
+			5'd1:	adc_din <= SGL;				// SGL bit
+			5'd2:	adc_din <= channel;			// CH bit
+			5'd3:	adc_din <= MSBF;				// MSB first bit
+			5'd4: shift_ena <= 1'b1;  			// start shifting data from adc
+			5'd15: begin
+						shift_ena <= 1'b0;
+						adc_done <= 1'b1;
+					 end
+			5'd16: begin  
+						adc_cs <= 1'b1;		// last state - disable chip select
+						state <= 5'd0;  		// go back to idle state
+					 end
+			default: 				
+						shift_ena <= 1'b1;	// unspecified states are covered by default above
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [9:0] shift_reg;
+	initial	begin
+			shift_reg = 10'b0;
+			data_from_adc = 10'b0;
+			end
+	
+	always @(negedge clk_1MHz)
+		if((adc_cs==1'b0)&&(shift_ena==1'b1))		// start shifting data_in
+				shift_reg <= {shift_reg[8:0],sdata_from_adc};
+	
+	// Latch converted output data
+	always @(posedge clk_1MHz)
+		if(adc_done) 					
+				data_from_adc = shift_reg;
+
+	// Assign outputs to drive SPI interface to DAC
+		assign adc_sck = !clk_1MHz & !adc_cs;
+		assign sdata_to_adc = adc_din;
+		assign data_valid = adc_cs;
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex17/verilog_files/spi2dac.v b/part_4/ex17/verilog_files/spi2dac.v
new file mode 100755
index 0000000..ccfb4e8
--- /dev/null
+++ b/part_4/ex17/verilog_files/spi2dac.v
@@ -0,0 +1,128 @@
+//------------------------------
+// Module name: spi2dac
+// Function: SPI interface for MPC4911 DAC
+// Creator:  Peter Cheung
+// Version:  1.3
+// Date:     8 Nov 2016
+//------------------------------
+
+module spi2dac (clk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld);
+
+	input	clk;				// 50MHz system clock of DE0
+	input	[9:0]	data_in;	// input data to DAC
+	input	load;				// Pulse to load data to dac
+	output dac_sdi;		// SPI serial data out
+	output dac_cs;			// chip select - low when sending data to dac
+	output dac_sck;		// SPI clock, 16 cycles at half clk freq
+	output dac_ld;
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire			clk, load;
+	wire [9:0]	data_in;
+	
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg			dac_cs, dac_ld;
+	wire			dac_sck, dac_sdi;
+	
+	parameter	BUF=1'b1;		// 0:no buffer, 1:Vref buffered
+	parameter	GA_N=1'b1;		// 0:gain = 2x, 1:gain = 1x
+	parameter	SHDN_N=1'b1;	// 0:power down, 1:dac active
+	
+	wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N};  // wire to VDD or GND
+	
+	// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... Initialise when FPGA is configured
+	end
+		
+	always @ (posedge clk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+	// ---- end internal clock generator ----------
+
+	// ---- Detect posedge of load with a small state machine
+	// .... FF set on posedge of load
+	// .... reset when dac_cs goes high at the end of DAC output cycle
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			dac_start;		 // set if a DAC write is detected
+	
+	initial begin
+		sr_state = IDLE;
+		dac_start = 1'b0;	// set while sending data to DAC
+		end
+	
+	always @ (posedge clk)
+		case (sr_state)
+			IDLE:	if (load==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						dac_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (dac_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						dac_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+	//------- End circuit to detect start and end of conversion	
+
+	//------- spi controller designed as a state machine
+	// .... with 17 states (idle, and S1-S16 
+	// .... for the 16 cycles each sending 1-bit to dac)
+	reg [4:0] 	state;
+	
+	initial	begin	
+		state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; 
+		end
+		
+	always @(posedge clk_1MHz)  begin
+		// default outputs and state transition
+		dac_cs <= 1'b0; dac_ld <= 1'b1; 
+		state <= state + 1'b1;	// move to next state by default
+		case (state)
+			5'd0:	if (dac_start == 1'b0)  begin  
+						state <= 5'd0; 				// still waiting
+						dac_cs <= 1'b1; 
+						end
+			5'd16: begin  
+						dac_cs <= 1'b1; dac_ld <= 1'b0; 
+						state <= 5'd0;  // go back to idle state
+					end
+			default:   begin					// all other states
+					dac_cs <= 1'b0; dac_ld <= 1'b1; 
+					state <= state + 1'b1;	// default state transition
+					end
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [15:0] shift_reg;
+	initial	begin	
+		shift_reg = 16'b0; 
+		end
+
+	always @(posedge clk_1MHz)
+		if((dac_start==1'b1)&&(dac_cs==1'b1))		// parallel load data to shift reg
+			shift_reg <= {cmd,data_in,2'b00};
+		else 													// .. else start shifting
+			shift_reg <= {shift_reg[14:0],1'b0};
+	
+	// Assign outputs to drive SPI interface to DAC
+			assign dac_sck = !clk_1MHz&!dac_cs;
+			assign dac_sdi = shift_reg[15];
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex18/c5_pin_model_dump.txt b/part_4/ex18/c5_pin_model_dump.txt
new file mode 100755
index 0000000..d8a635e
--- /dev/null
+++ b/part_4/ex18/c5_pin_model_dump.txt
@@ -0,0 +1,120 @@
+io_4iomodule_c5_index: 77gpio_index: 2
+io_4iomodule_c5_index: 60gpio_index: 476
+io_4iomodule_c5_index: 62gpio_index: 6
+io_4iomodule_c5_index: 26gpio_index: 472
+io_4iomodule_c5_index: 20gpio_index: 10
+io_4iomodule_c5_index: 12gpio_index: 468
+io_4iomodule_c5_index: 27gpio_index: 14
+io_4iomodule_c5_index: 71gpio_index: 464
+io_4iomodule_c5_index: 56gpio_index: 19
+io_4iomodule_c5_index: 14gpio_index: 460
+io_4iomodule_c5_index: 22gpio_index: 22
+io_4iomodule_c5_index: 10gpio_index: 456
+io_4iomodule_c5_index: 11gpio_index: 27
+io_4iomodule_c5_index: 73gpio_index: 452
+io_4iomodule_c5_index: 74gpio_index: 30
+io_4iomodule_c5_index: 76gpio_index: 448
+io_4iomodule_c5_index: 2gpio_index: 35
+io_4iomodule_c5_index: 78gpio_index: 444
+io_4iomodule_c5_index: 9gpio_index: 38
+io_4iomodule_c5_index: 36gpio_index: 440
+io_4iomodule_c5_index: 51gpio_index: 43
+io_4iomodule_c5_index: 23gpio_index: 436
+io_4iomodule_c5_index: 53gpio_index: 46
+io_4iomodule_c5_index: 50gpio_index: 432
+io_4iomodule_c5_index: 0gpio_index: 51
+io_4iomodule_c5_index: 43gpio_index: 428
+io_4iomodule_c5_index: 67gpio_index: 54
+io_4iomodule_c5_index: 16gpio_index: 424
+io_4iomodule_c5_index: 44gpio_index: 59
+io_4iomodule_c5_index: 29gpio_index: 420
+io_4iomodule_c5_index: 1gpio_index: 62
+io_4iomodule_c5_index: 8gpio_index: 416
+io_4iomodule_c5_index: 65gpio_index: 67
+io_4iomodule_c5_index: 25gpio_index: 412
+io_4iomodule_c5_index: 40gpio_index: 70
+io_4iomodule_c5_index: 55gpio_index: 408
+io_4iomodule_c5_index: 66gpio_index: 75
+io_4iomodule_c5_index: 5gpio_index: 404
+io_4iomodule_c5_index: 61gpio_index: 78
+io_4iomodule_c5_index: 17gpio_index: 400
+io_4iomodule_c5_index: 42gpio_index: 83
+io_4iomodule_c5_index: 59gpio_index: 396
+io_4iomodule_c5_index: 54gpio_index: 86
+io_4iomodule_c5_index: 58gpio_index: 392
+io_4iomodule_c5_index: 33gpio_index: 91
+io_4iomodule_c5_index: 41gpio_index: 388
+io_4iomodule_c5_index: 69gpio_index: 94
+io_4iomodule_c5_index: 3gpio_index: 384
+io_4iomodule_c5_index: 18gpio_index: 99
+io_4iomodule_c5_index: 15gpio_index: 380
+io_4iomodule_c5_index: 6gpio_index: 102
+io_4iomodule_c5_index: 7gpio_index: 376
+io_4iomodule_c5_index: 47gpio_index: 107
+io_4iomodule_c5_index: 39gpio_index: 372
+io_4iomodule_c5_index: 32gpio_index: 110
+io_4iomodule_c5_index: 24gpio_index: 368
+io_4iomodule_c5_index: 48gpio_index: 115
+io_4iomodule_c5_index: 57gpio_index: 364
+io_4iomodule_c5_index: 64gpio_index: 118
+io_4iomodule_c5_index: 31gpio_index: 360
+io_4iomodule_c5_index: 46gpio_index: 123
+io_4iomodule_c5_index: 21gpio_index: 356
+io_4iomodule_c5_index: 72gpio_index: 126
+io_4iomodule_c5_index: 70gpio_index: 352
+io_4iomodule_c5_index: 49gpio_index: 131
+io_4iomodule_c5_index: 63gpio_index: 348
+io_4iomodule_c5_index: 79gpio_index: 134
+io_4iomodule_c5_index: 28gpio_index: 344
+io_4iomodule_c5_index: 34gpio_index: 139
+io_4iomodule_c5_index: 4gpio_index: 340
+io_4iomodule_c5_index: 68gpio_index: 142
+io_4iomodule_c5_index: 37gpio_index: 336
+io_4iomodule_c5_index: 45gpio_index: 147
+io_4iomodule_c5_index: 35gpio_index: 332
+io_4iomodule_c5_index: 38gpio_index: 150
+io_4iomodule_c5_index: 19gpio_index: 328
+io_4iomodule_c5_index: 52gpio_index: 155
+io_4iomodule_c5_index: 30gpio_index: 324
+io_4iomodule_c5_index: 75gpio_index: 158
+io_4iomodule_c5_index: 13gpio_index: 320
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 15gpio_index: 165
+io_4iomodule_h_c5_index: 27gpio_index: 169
+io_4iomodule_h_c5_index: 30gpio_index: 173
+io_4iomodule_h_c5_index: 36gpio_index: 176
+io_4iomodule_h_c5_index: 37gpio_index: 180
+io_4iomodule_h_c5_index: 26gpio_index: 184
+io_4iomodule_h_c5_index: 24gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 21gpio_index: 196
+io_4iomodule_h_c5_index: 18gpio_index: 200
+io_4iomodule_h_c5_index: 6gpio_index: 204
+io_4iomodule_h_c5_index: 31gpio_index: 208
+io_4iomodule_h_c5_index: 3gpio_index: 212
+io_4iomodule_h_c5_index: 20gpio_index: 216
+io_4iomodule_h_c5_index: 4gpio_index: 220
+io_4iomodule_h_c5_index: 29gpio_index: 224
+io_4iomodule_h_c5_index: 22gpio_index: 228
+io_4iomodule_h_c5_index: 16gpio_index: 232
+io_4iomodule_h_c5_index: 9gpio_index: 236
+io_4iomodule_h_c5_index: 25gpio_index: 240
+io_4iomodule_h_c5_index: 11gpio_index: 244
+io_4iomodule_h_c5_index: 19gpio_index: 248
+io_4iomodule_h_c5_index: 23gpio_index: 252
+io_4iomodule_h_c5_index: 17gpio_index: 256
+io_4iomodule_h_c5_index: 8gpio_index: 260
+io_4iomodule_h_c5_index: 38gpio_index: 264
+io_4iomodule_h_c5_index: 2gpio_index: 268
+io_4iomodule_h_c5_index: 12gpio_index: 272
+io_4iomodule_h_c5_index: 35gpio_index: 276
+io_4iomodule_h_c5_index: 13gpio_index: 280
+io_4iomodule_h_c5_index: 5gpio_index: 284
+io_4iomodule_h_c5_index: 28gpio_index: 288
+io_4iomodule_h_c5_index: 7gpio_index: 292
+io_4iomodule_h_c5_index: 34gpio_index: 296
+io_4iomodule_h_c5_index: 14gpio_index: 300
+io_4iomodule_h_c5_index: 33gpio_index: 304
+io_4iomodule_h_c5_index: 39gpio_index: 308
+io_4iomodule_h_c5_index: 32gpio_index: 312
+io_4iomodule_h_c5_index: 10gpio_index: 316
diff --git a/part_4/ex18/db/.cmp.kpt b/part_4/ex18/db/.cmp.kpt
new file mode 100755
index 0000000..b589bc6
--- /dev/null
+++ b/part_4/ex18/db/.cmp.kpt
diff --git a/part_4/ex18/db/a_dpfifo_br81.tdf b/part_4/ex18/db/a_dpfifo_br81.tdf
new file mode 100755
index 0000000..e8ece42
--- /dev/null
+++ b/part_4/ex18/db/a_dpfifo_br81.tdf
@@ -0,0 +1,77 @@
+--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone V" LPM_NUMWORDS=8192 LPM_SHOWAHEAD="OFF" lpm_width=10 lpm_widthu=13 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data full q rreq sclr wreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO"
+--VERSION_BEGIN 16.0 cbx_altdpram 2016:04:27:18:05:34:SJ cbx_altera_syncram 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_scfifo 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION a_fefifo_4be (aclr, clock, rreq, sclr, wreq)
+RETURNS ( empty, full);
+FUNCTION altsyncram_44t1 (address_a[12..0], address_b[12..0], clock0, clock1, clocken1, data_a[9..0], wren_a)
+RETURNS ( q_b[9..0]);
+FUNCTION cntr_1ib (aclr, clock, cnt_en, sclr)
+RETURNS ( q[12..0]);
+
+--synthesis_resources = lut 39 M10K 10 reg 41 
+SUBDESIGN a_dpfifo_br81
+( 
+	clock	:	input;
+	data[9..0]	:	input;
+	full	:	output;
+	q[9..0]	:	output;
+	rreq	:	input;
+	sclr	:	input;
+	wreq	:	input;
+) 
+VARIABLE 
+	fifo_state : a_fefifo_4be;
+	FIFOram : altsyncram_44t1;
+	rd_ptr_count : cntr_1ib;
+	wr_ptr : cntr_1ib;
+	aclr	: NODE;
+	rd_ptr[12..0]	: WIRE;
+	valid_rreq	: WIRE;
+	valid_wreq	: WIRE;
+
+BEGIN 
+	fifo_state.aclr = aclr;
+	fifo_state.clock = clock;
+	fifo_state.rreq = rreq;
+	fifo_state.sclr = sclr;
+	fifo_state.wreq = wreq;
+	FIFOram.address_a[] = wr_ptr.q[];
+	FIFOram.address_b[] = ((! sclr) & rd_ptr[]);
+	FIFOram.clock0 = clock;
+	FIFOram.clock1 = clock;
+	FIFOram.clocken1 = (valid_rreq # sclr);
+	FIFOram.data_a[] = data[];
+	FIFOram.wren_a = valid_wreq;
+	rd_ptr_count.aclr = aclr;
+	rd_ptr_count.clock = clock;
+	rd_ptr_count.cnt_en = valid_rreq;
+	rd_ptr_count.sclr = sclr;
+	wr_ptr.aclr = aclr;
+	wr_ptr.clock = clock;
+	wr_ptr.cnt_en = valid_wreq;
+	wr_ptr.sclr = sclr;
+	aclr = GND;
+	full = fifo_state.full;
+	q[] = FIFOram.q_b[];
+	rd_ptr[] = rd_ptr_count.q[];
+	valid_rreq = (rreq & (! fifo_state.empty));
+	valid_wreq = (wreq & (! fifo_state.full));
+END;
+--VALID FILE
diff --git a/part_4/ex18/db/a_fefifo_4be.tdf b/part_4/ex18/db/a_fefifo_4be.tdf
new file mode 100755
index 0000000..c1151ed
--- /dev/null
+++ b/part_4/ex18/db/a_fefifo_4be.tdf
@@ -0,0 +1,117 @@
+--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=8192 lpm_widthad=13 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" aclr clock empty full rreq sclr wreq
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cntr_di7 (aclr, clock, cnt_en, sclr, updown)
+RETURNS ( q[12..0]);
+
+--synthesis_resources = lut 13 reg 15 
+SUBDESIGN a_fefifo_4be
+( 
+	aclr	:	input;
+	clock	:	input;
+	empty	:	output;
+	full	:	output;
+	rreq	:	input;
+	sclr	:	input;
+	wreq	:	input;
+) 
+VARIABLE 
+	b_full : dffe;
+	b_non_empty : dffe;
+	count_usedw : cntr_di7;
+	equal_af1w[12..0]	: WIRE;
+	equal_one[12..0]	: WIRE;
+	is_almost_empty0	: WIRE;
+	is_almost_empty1	: WIRE;
+	is_almost_empty10	: WIRE;
+	is_almost_empty11	: WIRE;
+	is_almost_empty12	: WIRE;
+	is_almost_empty2	: WIRE;
+	is_almost_empty3	: WIRE;
+	is_almost_empty4	: WIRE;
+	is_almost_empty5	: WIRE;
+	is_almost_empty6	: WIRE;
+	is_almost_empty7	: WIRE;
+	is_almost_empty8	: WIRE;
+	is_almost_empty9	: WIRE;
+	is_almost_full0	: WIRE;
+	is_almost_full1	: WIRE;
+	is_almost_full10	: WIRE;
+	is_almost_full11	: WIRE;
+	is_almost_full12	: WIRE;
+	is_almost_full2	: WIRE;
+	is_almost_full3	: WIRE;
+	is_almost_full4	: WIRE;
+	is_almost_full5	: WIRE;
+	is_almost_full6	: WIRE;
+	is_almost_full7	: WIRE;
+	is_almost_full8	: WIRE;
+	is_almost_full9	: WIRE;
+	usedw[12..0]	: WIRE;
+	valid_rreq	: WIRE;
+	valid_wreq	: WIRE;
+
+BEGIN 
+	b_full.clk = clock;
+	b_full.clrn = (! aclr);
+	b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full12 & wreq) & (! rreq)))));
+	b_non_empty.clk = clock;
+	b_non_empty.clrn = (! aclr);
+	b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty12 & rreq) & (! wreq))))));
+	count_usedw.aclr = aclr;
+	count_usedw.clock = clock;
+	count_usedw.cnt_en = (valid_wreq $ valid_rreq);
+	count_usedw.sclr = sclr;
+	count_usedw.updown = valid_wreq;
+	empty = (! b_non_empty.q);
+	equal_af1w[] = ( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0");
+	equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"0");
+	full = b_full.q;
+	is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]);
+	is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0);
+	is_almost_empty10 = ((usedw[10..10] $ equal_one[10..10]) & is_almost_empty9);
+	is_almost_empty11 = ((usedw[11..11] $ equal_one[11..11]) & is_almost_empty10);
+	is_almost_empty12 = ((usedw[12..12] $ equal_one[12..12]) & is_almost_empty11);
+	is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1);
+	is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2);
+	is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3);
+	is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4);
+	is_almost_empty6 = ((usedw[6..6] $ equal_one[6..6]) & is_almost_empty5);
+	is_almost_empty7 = ((usedw[7..7] $ equal_one[7..7]) & is_almost_empty6);
+	is_almost_empty8 = ((usedw[8..8] $ equal_one[8..8]) & is_almost_empty7);
+	is_almost_empty9 = ((usedw[9..9] $ equal_one[9..9]) & is_almost_empty8);
+	is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]);
+	is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0);
+	is_almost_full10 = ((usedw[10..10] $ equal_af1w[10..10]) & is_almost_full9);
+	is_almost_full11 = ((usedw[11..11] $ equal_af1w[11..11]) & is_almost_full10);
+	is_almost_full12 = ((usedw[12..12] $ equal_af1w[12..12]) & is_almost_full11);
+	is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1);
+	is_almost_full3 = ((usedw[3..3] $ equal_af1w[3..3]) & is_almost_full2);
+	is_almost_full4 = ((usedw[4..4] $ equal_af1w[4..4]) & is_almost_full3);
+	is_almost_full5 = ((usedw[5..5] $ equal_af1w[5..5]) & is_almost_full4);
+	is_almost_full6 = ((usedw[6..6] $ equal_af1w[6..6]) & is_almost_full5);
+	is_almost_full7 = ((usedw[7..7] $ equal_af1w[7..7]) & is_almost_full6);
+	is_almost_full8 = ((usedw[8..8] $ equal_af1w[8..8]) & is_almost_full7);
+	is_almost_full9 = ((usedw[9..9] $ equal_af1w[9..9]) & is_almost_full8);
+	usedw[] = count_usedw.q[];
+	valid_rreq = (rreq & b_non_empty.q);
+	valid_wreq = (wreq & (! b_full.q));
+END;
+--VALID FILE
diff --git a/part_4/ex18/db/altsyncram_44t1.tdf b/part_4/ex18/db/altsyncram_44t1.tdf
new file mode 100755
index 0000000..58aacc2
--- /dev/null
+++ b/part_4/ex18/db/altsyncram_44t1.tdf
@@ -0,0 +1,366 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" ENABLE_ECC="FALSE" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=8192 NUMWORDS_B=8192 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=10 WIDTH_B=10 WIDTH_ECCSTATUS=2 WIDTHAD_A=13 WIDTHAD_B=13 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 10 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_44t1
+( 
+	address_a[12..0]	:	input;
+	address_b[12..0]	:	input;
+	clock0	:	input;
+	clock1	:	input;
+	clocken1	:	input;
+	data_a[9..0]	:	input;
+	q_b[9..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a9 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 10,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[12..0]	: WIRE;
+	address_b_wire[12..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[9..0].clk0 = clock0;
+	ram_block1a[9..0].clk1 = clock1;
+	ram_block1a[9..0].ena0 = wren_a;
+	ram_block1a[9..0].ena1 = clocken1;
+	ram_block1a[9..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[8].portadatain[] = ( data_a[8..8]);
+	ram_block1a[9].portadatain[] = ( data_a[9..9]);
+	ram_block1a[9..0].portawe = wren_a;
+	ram_block1a[9..0].portbaddr[] = ( address_b_wire[12..0]);
+	ram_block1a[9..0].portbre = B"1111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block1a[9..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_4/ex18/db/cntr_1ib.tdf b/part_4/ex18/db/cntr_1ib.tdf
new file mode 100755
index 0000000..4580e79
--- /dev/null
+++ b/part_4/ex18/db/cntr_1ib.tdf
@@ -0,0 +1,152 @@
+--lpm_counter DEVICE_FAMILY="Cyclone V" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=13 aclr clock cnt_en q sclr
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein)
+WITH ( DONT_TOUCH, EXTENDED_LUT, LUT_MASK, SHARED_ARITH)
+RETURNS ( combout, cout, shareout, sumout);
+
+--synthesis_resources = lut 13 reg 13 
+SUBDESIGN cntr_1ib
+( 
+	aclr	:	input;
+	clock	:	input;
+	cnt_en	:	input;
+	q[12..0]	:	output;
+	sclr	:	input;
+) 
+VARIABLE 
+	counter_reg_bit[12..0] : dffeas;
+	counter_comb_bita0 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "000000000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita1 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita2 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita3 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita4 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita5 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita6 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita7 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita8 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita9 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita10 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita11 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita12 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	aclr_actual	: WIRE;
+	clk_en	: NODE;
+	data[12..0]	: NODE;
+	external_cin	: WIRE;
+	lsb_cin	: WIRE;
+	s_val[12..0]	: WIRE;
+	safe_q[12..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	updown_dir	: WIRE;
+	updown_lsb	: WIRE;
+	updown_other_bits	: WIRE;
+
+BEGIN 
+	counter_reg_bit[].asdata = ((sset & s_val[]) # ((! sset) & data[]));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[12..0].sumout);
+	counter_reg_bit[].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
+	counter_reg_bit[].sclr = sclr;
+	counter_reg_bit[].sload = (sset # sload);
+	counter_comb_bita[12..0].cin = ( counter_comb_bita[11..0].cout, lsb_cin);
+	counter_comb_bita[12..0].datad = ( counter_reg_bit[12..0].q);
+	counter_comb_bita[12..0].dataf = ( updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_lsb);
+	aclr_actual = aclr;
+	clk_en = VCC;
+	data[] = GND;
+	external_cin = B"1";
+	lsb_cin = B"0";
+	q[] = safe_q[];
+	s_val[] = B"1111111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sload = GND;
+	sset = GND;
+	updown_dir = B"1";
+	updown_lsb = updown_dir;
+	updown_other_bits = ((! external_cin) # updown_dir);
+END;
+--VALID FILE
diff --git a/part_4/ex18/db/cntr_di7.tdf b/part_4/ex18/db/cntr_di7.tdf
new file mode 100755
index 0000000..ca8be54
--- /dev/null
+++ b/part_4/ex18/db/cntr_di7.tdf
@@ -0,0 +1,153 @@
+--lpm_counter DEVICE_FAMILY="Cyclone V" lpm_width=13 aclr clock cnt_en q sclr updown
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein)
+WITH ( DONT_TOUCH, EXTENDED_LUT, LUT_MASK, SHARED_ARITH)
+RETURNS ( combout, cout, shareout, sumout);
+
+--synthesis_resources = lut 13 reg 13 
+SUBDESIGN cntr_di7
+( 
+	aclr	:	input;
+	clock	:	input;
+	cnt_en	:	input;
+	q[12..0]	:	output;
+	sclr	:	input;
+	updown	:	input;
+) 
+VARIABLE 
+	counter_reg_bit[12..0] : dffeas;
+	counter_comb_bita0 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "000000000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita1 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita2 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita3 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita4 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita5 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita6 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita7 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita8 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita9 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita10 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita11 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita12 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	aclr_actual	: WIRE;
+	clk_en	: NODE;
+	data[12..0]	: NODE;
+	external_cin	: WIRE;
+	lsb_cin	: WIRE;
+	s_val[12..0]	: WIRE;
+	safe_q[12..0]	: WIRE;
+	sload	: NODE;
+	sset	: NODE;
+	updown_dir	: WIRE;
+	updown_lsb	: WIRE;
+	updown_other_bits	: WIRE;
+
+BEGIN 
+	counter_reg_bit[].asdata = ((sset & s_val[]) # ((! sset) & data[]));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[12..0].sumout);
+	counter_reg_bit[].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
+	counter_reg_bit[].sclr = sclr;
+	counter_reg_bit[].sload = (sset # sload);
+	counter_comb_bita[12..0].cin = ( counter_comb_bita[11..0].cout, lsb_cin);
+	counter_comb_bita[12..0].datad = ( counter_reg_bit[12..0].q);
+	counter_comb_bita[12..0].dataf = ( updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_lsb);
+	aclr_actual = aclr;
+	clk_en = VCC;
+	data[] = GND;
+	external_cin = B"1";
+	lsb_cin = B"0";
+	q[] = safe_q[];
+	s_val[] = B"1111111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sload = GND;
+	sset = GND;
+	updown_dir = updown;
+	updown_lsb = updown_dir;
+	updown_other_bits = ((! external_cin) # updown_dir);
+END;
+--VALID FILE
diff --git a/part_4/ex18/db/ex18.(0).cnf.cdb b/part_4/ex18/db/ex18.(0).cnf.cdb
new file mode 100755
index 0000000..0bfaa76
--- /dev/null
+++ b/part_4/ex18/db/ex18.(0).cnf.cdb
diff --git a/part_4/ex18/db/ex18.(0).cnf.hdb b/part_4/ex18/db/ex18.(0).cnf.hdb
new file mode 100755
index 0000000..76f80ba
--- /dev/null
+++ b/part_4/ex18/db/ex18.(0).cnf.hdb
diff --git a/part_4/ex18/db/ex18.(1).cnf.cdb b/part_4/ex18/db/ex18.(1).cnf.cdb
new file mode 100755
index 0000000..bafd7f8
--- /dev/null
+++ b/part_4/ex18/db/ex18.(1).cnf.cdb
diff --git a/part_4/ex18/db/ex18.(1).cnf.hdb b/part_4/ex18/db/ex18.(1).cnf.hdb
new file mode 100755
index 0000000..8c65e74
--- /dev/null
+++ b/part_4/ex18/db/ex18.(1).cnf.hdb
diff --git a/part_4/ex18/db/ex18.(10).cnf.cdb b/part_4/ex18/db/ex18.(10).cnf.cdb
new file mode 100755
index 0000000..e35acea
--- /dev/null
+++ b/part_4/ex18/db/ex18.(10).cnf.cdb
diff --git a/part_4/ex18/db/ex18.(10).cnf.hdb b/part_4/ex18/db/ex18.(10).cnf.hdb
new file mode 100755
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--- /dev/null
+++ b/part_4/ex18/db/ex18.(10).cnf.hdb
diff --git a/part_4/ex18/db/ex18.(11).cnf.cdb b/part_4/ex18/db/ex18.(11).cnf.cdb
new file mode 100755
index 0000000..edb8dd4
--- /dev/null
+++ b/part_4/ex18/db/ex18.(11).cnf.cdb
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new file mode 100755
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+++ b/part_4/ex18/db/ex18.(11).cnf.hdb
diff --git a/part_4/ex18/db/ex18.(12).cnf.cdb b/part_4/ex18/db/ex18.(12).cnf.cdb
new file mode 100755
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diff --git a/part_4/ex18/db/ex18.(14).cnf.cdb b/part_4/ex18/db/ex18.(14).cnf.cdb
new file mode 100755
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diff --git a/part_4/ex18/db/ex18.(15).cnf.cdb b/part_4/ex18/db/ex18.(15).cnf.cdb
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new file mode 100755
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diff --git a/part_4/ex18/db/ex18.(2).cnf.cdb b/part_4/ex18/db/ex18.(2).cnf.cdb
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diff --git a/part_4/ex18/db/ex18.(3).cnf.cdb b/part_4/ex18/db/ex18.(3).cnf.cdb
new file mode 100755
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diff --git a/part_4/ex18/db/ex18.(4).cnf.cdb b/part_4/ex18/db/ex18.(4).cnf.cdb
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diff --git a/part_4/ex18/db/ex18.(5).cnf.cdb b/part_4/ex18/db/ex18.(5).cnf.cdb
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diff --git a/part_4/ex18/db/ex18.(6).cnf.cdb b/part_4/ex18/db/ex18.(6).cnf.cdb
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diff --git a/part_4/ex18/db/ex18.(7).cnf.cdb b/part_4/ex18/db/ex18.(7).cnf.cdb
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diff --git a/part_4/ex18/db/ex18.(7).cnf.hdb b/part_4/ex18/db/ex18.(7).cnf.hdb
new file mode 100755
index 0000000..3286f74
--- /dev/null
+++ b/part_4/ex18/db/ex18.(7).cnf.hdb
diff --git a/part_4/ex18/db/ex18.(8).cnf.cdb b/part_4/ex18/db/ex18.(8).cnf.cdb
new file mode 100755
index 0000000..3b37e63
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diff --git a/part_4/ex18/db/ex18.(8).cnf.hdb b/part_4/ex18/db/ex18.(8).cnf.hdb
new file mode 100755
index 0000000..8c9a399
--- /dev/null
+++ b/part_4/ex18/db/ex18.(8).cnf.hdb
diff --git a/part_4/ex18/db/ex18.(9).cnf.cdb b/part_4/ex18/db/ex18.(9).cnf.cdb
new file mode 100755
index 0000000..8b8d645
--- /dev/null
+++ b/part_4/ex18/db/ex18.(9).cnf.cdb
diff --git a/part_4/ex18/db/ex18.(9).cnf.hdb b/part_4/ex18/db/ex18.(9).cnf.hdb
new file mode 100755
index 0000000..82160f2
--- /dev/null
+++ b/part_4/ex18/db/ex18.(9).cnf.hdb
diff --git a/part_4/ex18/db/ex18.asm.qmsg b/part_4/ex18/db/ex18.asm.qmsg
new file mode 100755
index 0000000..d4eb95e
--- /dev/null
+++ b/part_4/ex18/db/ex18.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480678020892 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480678020894 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:27:00 2016 " "Processing started: Fri Dec 02 11:27:00 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480678020894 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1480678020894 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex18 -c ex18 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex18 -c ex18" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1480678020894 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1480678021711 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1480678027444 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "884 " "Peak virtual memory: 884 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480678027799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:27:07 2016 " "Processing ended: Fri Dec 02 11:27:07 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480678027799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480678027799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480678027799 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1480678027799 ""}
diff --git a/part_4/ex18/db/ex18.asm.rdb b/part_4/ex18/db/ex18.asm.rdb
new file mode 100755
index 0000000..ec27b9b
--- /dev/null
+++ b/part_4/ex18/db/ex18.asm.rdb
diff --git a/part_4/ex18/db/ex18.cmp.ammdb b/part_4/ex18/db/ex18.cmp.ammdb
new file mode 100755
index 0000000..a2fdcb8
--- /dev/null
+++ b/part_4/ex18/db/ex18.cmp.ammdb
diff --git a/part_4/ex18/db/ex18.cmp.bpm b/part_4/ex18/db/ex18.cmp.bpm
new file mode 100755
index 0000000..5d279bd
--- /dev/null
+++ b/part_4/ex18/db/ex18.cmp.bpm
diff --git a/part_4/ex18/db/ex18.cmp.cdb b/part_4/ex18/db/ex18.cmp.cdb
new file mode 100755
index 0000000..e0c8985
--- /dev/null
+++ b/part_4/ex18/db/ex18.cmp.cdb
diff --git a/part_4/ex18/db/ex18.cmp.hdb b/part_4/ex18/db/ex18.cmp.hdb
new file mode 100755
index 0000000..4b8f51a
--- /dev/null
+++ b/part_4/ex18/db/ex18.cmp.hdb
diff --git a/part_4/ex18/db/ex18.cmp.idb b/part_4/ex18/db/ex18.cmp.idb
new file mode 100755
index 0000000..cd292c6
--- /dev/null
+++ b/part_4/ex18/db/ex18.cmp.idb
diff --git a/part_4/ex18/db/ex18.cmp.logdb b/part_4/ex18/db/ex18.cmp.logdb
new file mode 100755
index 0000000..d3039fb
--- /dev/null
+++ b/part_4/ex18/db/ex18.cmp.logdb
@@ -0,0 +1,81 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;41;0;0;41;41;0;29;0;0;0;0;29;0;0;0;0;29;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,41;41;41;41;41;0;41;41;0;0;41;12;41;41;41;41;12;41;41;41;41;12;41;41;41;41;41;41,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,SW[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SDI,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SCK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_CS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_LD,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDI,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SCK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_CS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PWM_OUT,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDO,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,28,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/part_4/ex18/db/ex18.cmp.rdb b/part_4/ex18/db/ex18.cmp.rdb
new file mode 100755
index 0000000..3c40100
--- /dev/null
+++ b/part_4/ex18/db/ex18.cmp.rdb
diff --git a/part_4/ex18/db/ex18.cmp_merge.kpt b/part_4/ex18/db/ex18.cmp_merge.kpt
new file mode 100755
index 0000000..aa606a2
--- /dev/null
+++ b/part_4/ex18/db/ex18.cmp_merge.kpt
diff --git a/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..5b115d6
--- /dev/null
+++ b/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ss_0c_slow.hsd b/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ss_0c_slow.hsd
new file mode 100755
index 0000000..3f61b64
--- /dev/null
+++ b/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ss_0c_slow.hsd
diff --git a/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ss_85c_slow.hsd b/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ss_85c_slow.hsd
new file mode 100755
index 0000000..6aaa577
--- /dev/null
+++ b/part_4/ex18/db/ex18.cyclonev_io_sim_cache.ss_85c_slow.hsd
diff --git a/part_4/ex18/db/ex18.db_info b/part_4/ex18/db/ex18.db_info
new file mode 100755
index 0000000..3defa9e
--- /dev/null
+++ b/part_4/ex18/db/ex18.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Dec 02 11:20:34 2016
diff --git a/part_4/ex18/db/ex18.fit.qmsg b/part_4/ex18/db/ex18.fit.qmsg
new file mode 100755
index 0000000..9ae908d
--- /dev/null
+++ b/part_4/ex18/db/ex18.fit.qmsg
@@ -0,0 +1,44 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1480677980653 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1480677980653 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex18 5CGXFC7C7F23C8 " "Selected device 5CGXFC7C7F23C8 for design \"ex18\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1480677980914 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480677980980 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1480677980980 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1480677981419 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1480677981552 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1480677981558 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "41 41 " "No exact pin location assignment(s) for 41 pins of 41 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1480677981750 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1480677989203 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 118 global CLKCTRL_G10 " "CLOCK_50~inputCLKENA0 with 118 fanout uses global clock CLKCTRL_G10" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1480677989406 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1480677989406 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677989407 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1480677989411 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480677989412 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1480677989413 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1480677989414 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1480677989414 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1480677989415 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex18.sdc " "Synopsys Design Constraints File file not found: 'ex18.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1480677990328 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1480677990329 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1480677990333 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1480677990334 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1480677990334 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1480677990354 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1480677990355 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1480677990355 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:09 " "Fitter preparation operations ending: elapsed time is 00:00:09" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677990387 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1480677995291 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1480677995512 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480677996813 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1480677998045 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1480678000428 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480678000428 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1480678001905 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X67_Y35 X77_Y45 " "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X67_Y35 to location X77_Y45" {  } { { "loc" "" { Generic "C:/New folder/ex18/" { { 1 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X67_Y35 to location X77_Y45"} { { 12 { 0 ""} 67 35 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1480678007622 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1480678007622 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1480678012001 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1480678012001 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:05 " "Fitter routing operations ending: elapsed time is 00:00:05" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480678012005 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.90 " "Total time spent on timing analysis during the Fitter is 0.90 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1480678013509 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480678013549 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480678014008 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1480678014008 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1480678015257 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:05 " "Fitter post-fit operations ending: elapsed time is 00:00:05" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1480678018622 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex18/output_files/ex18.fit.smsg " "Generated suppressed messages file C:/New folder/ex18/output_files/ex18.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1480678018903 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2906 " "Peak virtual memory: 2906 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480678019511 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:26:59 2016 " "Processing ended: Fri Dec 02 11:26:59 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480678019511 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480678019511 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:14 " "Total CPU time (on all processors): 00:01:14" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480678019511 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1480678019511 ""}
diff --git a/part_4/ex18/db/ex18.hier_info b/part_4/ex18/db/ex18.hier_info
new file mode 100755
index 0000000..db80fa0
--- /dev/null
+++ b/part_4/ex18/db/ex18.hier_info
@@ -0,0 +1,932 @@
+|ex18
+CLOCK_50 => CLOCK_50.IN5
+SW[0] => ~NO_FANOUT~
+SW[1] => ~NO_FANOUT~
+SW[2] => ~NO_FANOUT~
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => ~NO_FANOUT~
+SW[8] => ~NO_FANOUT~
+SW[9] => ~NO_FANOUT~
+HEX0[0] <= hex_to_7seg:SEG0.port0
+HEX0[1] <= hex_to_7seg:SEG0.port0
+HEX0[2] <= hex_to_7seg:SEG0.port0
+HEX0[3] <= hex_to_7seg:SEG0.port0
+HEX0[4] <= hex_to_7seg:SEG0.port0
+HEX0[5] <= hex_to_7seg:SEG0.port0
+HEX0[6] <= hex_to_7seg:SEG0.port0
+HEX1[0] <= hex_to_7seg:SEG1.port0
+HEX1[1] <= hex_to_7seg:SEG1.port0
+HEX1[2] <= hex_to_7seg:SEG1.port0
+HEX1[3] <= hex_to_7seg:SEG1.port0
+HEX1[4] <= hex_to_7seg:SEG1.port0
+HEX1[5] <= hex_to_7seg:SEG1.port0
+HEX1[6] <= hex_to_7seg:SEG1.port0
+HEX2[0] <= hex_to_7seg:SEG2.port0
+HEX2[1] <= hex_to_7seg:SEG2.port0
+HEX2[2] <= hex_to_7seg:SEG2.port0
+HEX2[3] <= hex_to_7seg:SEG2.port0
+HEX2[4] <= hex_to_7seg:SEG2.port0
+HEX2[5] <= hex_to_7seg:SEG2.port0
+HEX2[6] <= hex_to_7seg:SEG2.port0
+DAC_SDI <= spi2dac:SPI_DAC.port3
+DAC_SCK <= spi2dac:SPI_DAC.port5
+DAC_CS <= spi2dac:SPI_DAC.port4
+DAC_LD <= spi2dac:SPI_DAC.port6
+ADC_SDI <= spi2adc:SPI_ADC.sdata_to_adc
+ADC_SCK <= spi2adc:SPI_ADC.adc_sck
+ADC_CS <= spi2adc:SPI_ADC.adc_cs
+ADC_SDO => ADC_SDO.IN1
+PWM_OUT <= pwm:PWM_DC.port3
+
+
+|ex18|clktick_16:GEN_10K
+clkin => count[0].CLK
+clkin => count[1].CLK
+clkin => count[2].CLK
+clkin => count[3].CLK
+clkin => count[4].CLK
+clkin => count[5].CLK
+clkin => count[6].CLK
+clkin => count[7].CLK
+clkin => count[8].CLK
+clkin => count[9].CLK
+clkin => count[10].CLK
+clkin => count[11].CLK
+clkin => count[12].CLK
+clkin => count[13].CLK
+clkin => count[14].CLK
+clkin => count[15].CLK
+clkin => tick~reg0.CLK
+enable => count[0].ENA
+enable => count[1].ENA
+enable => count[2].ENA
+enable => count[3].ENA
+enable => count[4].ENA
+enable => count[5].ENA
+enable => count[6].ENA
+enable => count[7].ENA
+enable => count[8].ENA
+enable => count[9].ENA
+enable => count[10].ENA
+enable => count[11].ENA
+enable => count[12].ENA
+enable => count[13].ENA
+enable => count[14].ENA
+enable => count[15].ENA
+enable => tick~reg0.ENA
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => count.DATAB
+N[8] => count.DATAB
+N[9] => count.DATAB
+N[10] => count.DATAB
+N[11] => count.DATAB
+N[12] => count.DATAB
+N[13] => count.DATAB
+N[14] => count.DATAB
+N[15] => count.DATAB
+tick <= tick~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex18|spi2dac:SPI_DAC
+clk => dac_start.CLK
+clk => clk_1MHz.CLK
+clk => ctr[0].CLK
+clk => ctr[1].CLK
+clk => ctr[2].CLK
+clk => ctr[3].CLK
+clk => ctr[4].CLK
+clk => sr_state~1.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => Selector1.IN1
+load => dac_start.OUTPUTSELECT
+load => Selector0.IN1
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= dac_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= dac_ld~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex18|pwm:PWM_DC
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex18|spi2adc:SPI_ADC
+sysclk => adc_start.CLK
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~1.DATAIN
+start => Selector1.IN1
+start => adc_start.OUTPUTSELECT
+start => Selector0.IN1
+channel => Selector6.IN6
+data_from_adc[0] <= data_from_adc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[1] <= data_from_adc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[2] <= data_from_adc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[3] <= data_from_adc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[4] <= data_from_adc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[5] <= data_from_adc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[6] <= data_from_adc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[7] <= data_from_adc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[8] <= data_from_adc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[9] <= data_from_adc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+sdata_to_adc <= adc_din.DB_MAX_OUTPUT_PORT_TYPE
+adc_cs <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+adc_sck <= adc_sck.DB_MAX_OUTPUT_PORT_TYPE
+sdata_from_adc => shift_reg[0].DATAIN
+
+
+|ex18|processor:ALLPASS
+sysclk => sysclk.IN1
+tick => tick.IN2
+data_in[0] => Add0.IN20
+data_in[1] => Add0.IN19
+data_in[2] => Add0.IN18
+data_in[3] => Add0.IN17
+data_in[4] => Add0.IN16
+data_in[5] => Add0.IN15
+data_in[6] => Add0.IN14
+data_in[7] => Add0.IN13
+data_in[8] => Add0.IN12
+data_in[9] => Add0.IN11
+data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex18|processor:ALLPASS|FIFO:fifo
+clock => clock.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+rdreq => rdreq.IN1
+wrreq => wrreq.IN1
+full <= scfifo:scfifo_component.full
+q[0] <= scfifo:scfifo_component.q
+q[1] <= scfifo:scfifo_component.q
+q[2] <= scfifo:scfifo_component.q
+q[3] <= scfifo:scfifo_component.q
+q[4] <= scfifo:scfifo_component.q
+q[5] <= scfifo:scfifo_component.q
+q[6] <= scfifo:scfifo_component.q
+q[7] <= scfifo:scfifo_component.q
+q[8] <= scfifo:scfifo_component.q
+q[9] <= scfifo:scfifo_component.q
+
+
+|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component
+data[0] => scfifo_4l81:auto_generated.data[0]
+data[1] => scfifo_4l81:auto_generated.data[1]
+data[2] => scfifo_4l81:auto_generated.data[2]
+data[3] => scfifo_4l81:auto_generated.data[3]
+data[4] => scfifo_4l81:auto_generated.data[4]
+data[5] => scfifo_4l81:auto_generated.data[5]
+data[6] => scfifo_4l81:auto_generated.data[6]
+data[7] => scfifo_4l81:auto_generated.data[7]
+data[8] => scfifo_4l81:auto_generated.data[8]
+data[9] => scfifo_4l81:auto_generated.data[9]
+q[0] <= scfifo_4l81:auto_generated.q[0]
+q[1] <= scfifo_4l81:auto_generated.q[1]
+q[2] <= scfifo_4l81:auto_generated.q[2]
+q[3] <= scfifo_4l81:auto_generated.q[3]
+q[4] <= scfifo_4l81:auto_generated.q[4]
+q[5] <= scfifo_4l81:auto_generated.q[5]
+q[6] <= scfifo_4l81:auto_generated.q[6]
+q[7] <= scfifo_4l81:auto_generated.q[7]
+q[8] <= scfifo_4l81:auto_generated.q[8]
+q[9] <= scfifo_4l81:auto_generated.q[9]
+wrreq => scfifo_4l81:auto_generated.wrreq
+rdreq => scfifo_4l81:auto_generated.rdreq
+clock => scfifo_4l81:auto_generated.clock
+aclr => ~NO_FANOUT~
+sclr => ~NO_FANOUT~
+eccstatus[0] <= <UNC>
+eccstatus[1] <= <UNC>
+empty <= <GND>
+full <= scfifo_4l81:auto_generated.full
+almost_full <= <GND>
+almost_empty <= <GND>
+usedw[0] <= <GND>
+usedw[1] <= <GND>
+usedw[2] <= <GND>
+usedw[3] <= <GND>
+usedw[4] <= <GND>
+usedw[5] <= <GND>
+usedw[6] <= <GND>
+usedw[7] <= <GND>
+usedw[8] <= <GND>
+usedw[9] <= <GND>
+usedw[10] <= <GND>
+usedw[11] <= <GND>
+usedw[12] <= <GND>
+
+
+|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated
+clock => a_dpfifo_br81:dpfifo.clock
+data[0] => a_dpfifo_br81:dpfifo.data[0]
+data[1] => a_dpfifo_br81:dpfifo.data[1]
+data[2] => a_dpfifo_br81:dpfifo.data[2]
+data[3] => a_dpfifo_br81:dpfifo.data[3]
+data[4] => a_dpfifo_br81:dpfifo.data[4]
+data[5] => a_dpfifo_br81:dpfifo.data[5]
+data[6] => a_dpfifo_br81:dpfifo.data[6]
+data[7] => a_dpfifo_br81:dpfifo.data[7]
+data[8] => a_dpfifo_br81:dpfifo.data[8]
+data[9] => a_dpfifo_br81:dpfifo.data[9]
+full <= a_dpfifo_br81:dpfifo.full
+q[0] <= a_dpfifo_br81:dpfifo.q[0]
+q[1] <= a_dpfifo_br81:dpfifo.q[1]
+q[2] <= a_dpfifo_br81:dpfifo.q[2]
+q[3] <= a_dpfifo_br81:dpfifo.q[3]
+q[4] <= a_dpfifo_br81:dpfifo.q[4]
+q[5] <= a_dpfifo_br81:dpfifo.q[5]
+q[6] <= a_dpfifo_br81:dpfifo.q[6]
+q[7] <= a_dpfifo_br81:dpfifo.q[7]
+q[8] <= a_dpfifo_br81:dpfifo.q[8]
+q[9] <= a_dpfifo_br81:dpfifo.q[9]
+rdreq => a_dpfifo_br81:dpfifo.rreq
+wrreq => a_dpfifo_br81:dpfifo.wreq
+
+
+|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo
+clock => a_fefifo_4be:fifo_state.clock
+clock => altsyncram_44t1:FIFOram.clock0
+clock => altsyncram_44t1:FIFOram.clock1
+clock => cntr_1ib:rd_ptr_count.clock
+clock => cntr_1ib:wr_ptr.clock
+data[0] => altsyncram_44t1:FIFOram.data_a[0]
+data[1] => altsyncram_44t1:FIFOram.data_a[1]
+data[2] => altsyncram_44t1:FIFOram.data_a[2]
+data[3] => altsyncram_44t1:FIFOram.data_a[3]
+data[4] => altsyncram_44t1:FIFOram.data_a[4]
+data[5] => altsyncram_44t1:FIFOram.data_a[5]
+data[6] => altsyncram_44t1:FIFOram.data_a[6]
+data[7] => altsyncram_44t1:FIFOram.data_a[7]
+data[8] => altsyncram_44t1:FIFOram.data_a[8]
+data[9] => altsyncram_44t1:FIFOram.data_a[9]
+full <= a_fefifo_4be:fifo_state.full
+q[0] <= altsyncram_44t1:FIFOram.q_b[0]
+q[1] <= altsyncram_44t1:FIFOram.q_b[1]
+q[2] <= altsyncram_44t1:FIFOram.q_b[2]
+q[3] <= altsyncram_44t1:FIFOram.q_b[3]
+q[4] <= altsyncram_44t1:FIFOram.q_b[4]
+q[5] <= altsyncram_44t1:FIFOram.q_b[5]
+q[6] <= altsyncram_44t1:FIFOram.q_b[6]
+q[7] <= altsyncram_44t1:FIFOram.q_b[7]
+q[8] <= altsyncram_44t1:FIFOram.q_b[8]
+q[9] <= altsyncram_44t1:FIFOram.q_b[9]
+rreq => a_fefifo_4be:fifo_state.rreq
+rreq => valid_rreq.IN0
+sclr => a_fefifo_4be:fifo_state.sclr
+sclr => _.IN0
+sclr => _.IN1
+sclr => cntr_1ib:rd_ptr_count.sclr
+sclr => cntr_1ib:wr_ptr.sclr
+wreq => a_fefifo_4be:fifo_state.wreq
+wreq => valid_wreq.IN0
+
+
+|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state
+aclr => b_full.IN0
+aclr => b_non_empty.IN0
+aclr => cntr_di7:count_usedw.aclr
+clock => cntr_di7:count_usedw.clock
+clock => b_full.CLK
+clock => b_non_empty.CLK
+empty <= empty.DB_MAX_OUTPUT_PORT_TYPE
+full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
+rreq => _.IN1
+rreq => _.IN0
+rreq => _.IN1
+rreq => valid_rreq.IN0
+sclr => _.IN0
+sclr => _.IN0
+sclr => _.IN1
+sclr => _.IN0
+sclr => _.IN0
+sclr => cntr_di7:count_usedw.sclr
+wreq => _.IN1
+wreq => _.IN1
+wreq => _.IN0
+wreq => valid_wreq.IN0
+
+
+|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw
+aclr => counter_reg_bit[12].IN0
+clock => counter_reg_bit[12].CLK
+clock => counter_reg_bit[11].CLK
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+cnt_en => _.IN0
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+q[11] <= counter_reg_bit[11].DB_MAX_OUTPUT_PORT_TYPE
+q[12] <= counter_reg_bit[12].DB_MAX_OUTPUT_PORT_TYPE
+sclr => _.IN1
+sclr => counter_reg_bit[12].SCLR
+sclr => counter_reg_bit[11].SCLR
+sclr => counter_reg_bit[10].SCLR
+sclr => counter_reg_bit[9].SCLR
+sclr => counter_reg_bit[8].SCLR
+sclr => counter_reg_bit[7].SCLR
+sclr => counter_reg_bit[6].SCLR
+sclr => counter_reg_bit[5].SCLR
+sclr => counter_reg_bit[4].SCLR
+sclr => counter_reg_bit[3].SCLR
+sclr => counter_reg_bit[2].SCLR
+sclr => counter_reg_bit[1].SCLR
+sclr => counter_reg_bit[0].SCLR
+updown => updown_other_bits.IN1
+updown => counter_comb_bita0.DATAF
+
+
+|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram
+address_a[0] => ram_block1a0.PORTAADDR
+address_a[0] => ram_block1a1.PORTAADDR
+address_a[0] => ram_block1a2.PORTAADDR
+address_a[0] => ram_block1a3.PORTAADDR
+address_a[0] => ram_block1a4.PORTAADDR
+address_a[0] => ram_block1a5.PORTAADDR
+address_a[0] => ram_block1a6.PORTAADDR
+address_a[0] => ram_block1a7.PORTAADDR
+address_a[0] => ram_block1a8.PORTAADDR
+address_a[0] => ram_block1a9.PORTAADDR
+address_a[1] => ram_block1a0.PORTAADDR1
+address_a[1] => ram_block1a1.PORTAADDR1
+address_a[1] => ram_block1a2.PORTAADDR1
+address_a[1] => ram_block1a3.PORTAADDR1
+address_a[1] => ram_block1a4.PORTAADDR1
+address_a[1] => ram_block1a5.PORTAADDR1
+address_a[1] => ram_block1a6.PORTAADDR1
+address_a[1] => ram_block1a7.PORTAADDR1
+address_a[1] => ram_block1a8.PORTAADDR1
+address_a[1] => ram_block1a9.PORTAADDR1
+address_a[2] => ram_block1a0.PORTAADDR2
+address_a[2] => ram_block1a1.PORTAADDR2
+address_a[2] => ram_block1a2.PORTAADDR2
+address_a[2] => ram_block1a3.PORTAADDR2
+address_a[2] => ram_block1a4.PORTAADDR2
+address_a[2] => ram_block1a5.PORTAADDR2
+address_a[2] => ram_block1a6.PORTAADDR2
+address_a[2] => ram_block1a7.PORTAADDR2
+address_a[2] => ram_block1a8.PORTAADDR2
+address_a[2] => ram_block1a9.PORTAADDR2
+address_a[3] => ram_block1a0.PORTAADDR3
+address_a[3] => ram_block1a1.PORTAADDR3
+address_a[3] => ram_block1a2.PORTAADDR3
+address_a[3] => ram_block1a3.PORTAADDR3
+address_a[3] => ram_block1a4.PORTAADDR3
+address_a[3] => ram_block1a5.PORTAADDR3
+address_a[3] => ram_block1a6.PORTAADDR3
+address_a[3] => ram_block1a7.PORTAADDR3
+address_a[3] => ram_block1a8.PORTAADDR3
+address_a[3] => ram_block1a9.PORTAADDR3
+address_a[4] => ram_block1a0.PORTAADDR4
+address_a[4] => ram_block1a1.PORTAADDR4
+address_a[4] => ram_block1a2.PORTAADDR4
+address_a[4] => ram_block1a3.PORTAADDR4
+address_a[4] => ram_block1a4.PORTAADDR4
+address_a[4] => ram_block1a5.PORTAADDR4
+address_a[4] => ram_block1a6.PORTAADDR4
+address_a[4] => ram_block1a7.PORTAADDR4
+address_a[4] => ram_block1a8.PORTAADDR4
+address_a[4] => ram_block1a9.PORTAADDR4
+address_a[5] => ram_block1a0.PORTAADDR5
+address_a[5] => ram_block1a1.PORTAADDR5
+address_a[5] => ram_block1a2.PORTAADDR5
+address_a[5] => ram_block1a3.PORTAADDR5
+address_a[5] => ram_block1a4.PORTAADDR5
+address_a[5] => ram_block1a5.PORTAADDR5
+address_a[5] => ram_block1a6.PORTAADDR5
+address_a[5] => ram_block1a7.PORTAADDR5
+address_a[5] => ram_block1a8.PORTAADDR5
+address_a[5] => ram_block1a9.PORTAADDR5
+address_a[6] => ram_block1a0.PORTAADDR6
+address_a[6] => ram_block1a1.PORTAADDR6
+address_a[6] => ram_block1a2.PORTAADDR6
+address_a[6] => ram_block1a3.PORTAADDR6
+address_a[6] => ram_block1a4.PORTAADDR6
+address_a[6] => ram_block1a5.PORTAADDR6
+address_a[6] => ram_block1a6.PORTAADDR6
+address_a[6] => ram_block1a7.PORTAADDR6
+address_a[6] => ram_block1a8.PORTAADDR6
+address_a[6] => ram_block1a9.PORTAADDR6
+address_a[7] => ram_block1a0.PORTAADDR7
+address_a[7] => ram_block1a1.PORTAADDR7
+address_a[7] => ram_block1a2.PORTAADDR7
+address_a[7] => ram_block1a3.PORTAADDR7
+address_a[7] => ram_block1a4.PORTAADDR7
+address_a[7] => ram_block1a5.PORTAADDR7
+address_a[7] => ram_block1a6.PORTAADDR7
+address_a[7] => ram_block1a7.PORTAADDR7
+address_a[7] => ram_block1a8.PORTAADDR7
+address_a[7] => ram_block1a9.PORTAADDR7
+address_a[8] => ram_block1a0.PORTAADDR8
+address_a[8] => ram_block1a1.PORTAADDR8
+address_a[8] => ram_block1a2.PORTAADDR8
+address_a[8] => ram_block1a3.PORTAADDR8
+address_a[8] => ram_block1a4.PORTAADDR8
+address_a[8] => ram_block1a5.PORTAADDR8
+address_a[8] => ram_block1a6.PORTAADDR8
+address_a[8] => ram_block1a7.PORTAADDR8
+address_a[8] => ram_block1a8.PORTAADDR8
+address_a[8] => ram_block1a9.PORTAADDR8
+address_a[9] => ram_block1a0.PORTAADDR9
+address_a[9] => ram_block1a1.PORTAADDR9
+address_a[9] => ram_block1a2.PORTAADDR9
+address_a[9] => ram_block1a3.PORTAADDR9
+address_a[9] => ram_block1a4.PORTAADDR9
+address_a[9] => ram_block1a5.PORTAADDR9
+address_a[9] => ram_block1a6.PORTAADDR9
+address_a[9] => ram_block1a7.PORTAADDR9
+address_a[9] => ram_block1a8.PORTAADDR9
+address_a[9] => ram_block1a9.PORTAADDR9
+address_a[10] => ram_block1a0.PORTAADDR10
+address_a[10] => ram_block1a1.PORTAADDR10
+address_a[10] => ram_block1a2.PORTAADDR10
+address_a[10] => ram_block1a3.PORTAADDR10
+address_a[10] => ram_block1a4.PORTAADDR10
+address_a[10] => ram_block1a5.PORTAADDR10
+address_a[10] => ram_block1a6.PORTAADDR10
+address_a[10] => ram_block1a7.PORTAADDR10
+address_a[10] => ram_block1a8.PORTAADDR10
+address_a[10] => ram_block1a9.PORTAADDR10
+address_a[11] => ram_block1a0.PORTAADDR11
+address_a[11] => ram_block1a1.PORTAADDR11
+address_a[11] => ram_block1a2.PORTAADDR11
+address_a[11] => ram_block1a3.PORTAADDR11
+address_a[11] => ram_block1a4.PORTAADDR11
+address_a[11] => ram_block1a5.PORTAADDR11
+address_a[11] => ram_block1a6.PORTAADDR11
+address_a[11] => ram_block1a7.PORTAADDR11
+address_a[11] => ram_block1a8.PORTAADDR11
+address_a[11] => ram_block1a9.PORTAADDR11
+address_a[12] => ram_block1a0.PORTAADDR12
+address_a[12] => ram_block1a1.PORTAADDR12
+address_a[12] => ram_block1a2.PORTAADDR12
+address_a[12] => ram_block1a3.PORTAADDR12
+address_a[12] => ram_block1a4.PORTAADDR12
+address_a[12] => ram_block1a5.PORTAADDR12
+address_a[12] => ram_block1a6.PORTAADDR12
+address_a[12] => ram_block1a7.PORTAADDR12
+address_a[12] => ram_block1a8.PORTAADDR12
+address_a[12] => ram_block1a9.PORTAADDR12
+address_b[0] => ram_block1a0.PORTBADDR
+address_b[0] => ram_block1a1.PORTBADDR
+address_b[0] => ram_block1a2.PORTBADDR
+address_b[0] => ram_block1a3.PORTBADDR
+address_b[0] => ram_block1a4.PORTBADDR
+address_b[0] => ram_block1a5.PORTBADDR
+address_b[0] => ram_block1a6.PORTBADDR
+address_b[0] => ram_block1a7.PORTBADDR
+address_b[0] => ram_block1a8.PORTBADDR
+address_b[0] => ram_block1a9.PORTBADDR
+address_b[1] => ram_block1a0.PORTBADDR1
+address_b[1] => ram_block1a1.PORTBADDR1
+address_b[1] => ram_block1a2.PORTBADDR1
+address_b[1] => ram_block1a3.PORTBADDR1
+address_b[1] => ram_block1a4.PORTBADDR1
+address_b[1] => ram_block1a5.PORTBADDR1
+address_b[1] => ram_block1a6.PORTBADDR1
+address_b[1] => ram_block1a7.PORTBADDR1
+address_b[1] => ram_block1a8.PORTBADDR1
+address_b[1] => ram_block1a9.PORTBADDR1
+address_b[2] => ram_block1a0.PORTBADDR2
+address_b[2] => ram_block1a1.PORTBADDR2
+address_b[2] => ram_block1a2.PORTBADDR2
+address_b[2] => ram_block1a3.PORTBADDR2
+address_b[2] => ram_block1a4.PORTBADDR2
+address_b[2] => ram_block1a5.PORTBADDR2
+address_b[2] => ram_block1a6.PORTBADDR2
+address_b[2] => ram_block1a7.PORTBADDR2
+address_b[2] => ram_block1a8.PORTBADDR2
+address_b[2] => ram_block1a9.PORTBADDR2
+address_b[3] => ram_block1a0.PORTBADDR3
+address_b[3] => ram_block1a1.PORTBADDR3
+address_b[3] => ram_block1a2.PORTBADDR3
+address_b[3] => ram_block1a3.PORTBADDR3
+address_b[3] => ram_block1a4.PORTBADDR3
+address_b[3] => ram_block1a5.PORTBADDR3
+address_b[3] => ram_block1a6.PORTBADDR3
+address_b[3] => ram_block1a7.PORTBADDR3
+address_b[3] => ram_block1a8.PORTBADDR3
+address_b[3] => ram_block1a9.PORTBADDR3
+address_b[4] => ram_block1a0.PORTBADDR4
+address_b[4] => ram_block1a1.PORTBADDR4
+address_b[4] => ram_block1a2.PORTBADDR4
+address_b[4] => ram_block1a3.PORTBADDR4
+address_b[4] => ram_block1a4.PORTBADDR4
+address_b[4] => ram_block1a5.PORTBADDR4
+address_b[4] => ram_block1a6.PORTBADDR4
+address_b[4] => ram_block1a7.PORTBADDR4
+address_b[4] => ram_block1a8.PORTBADDR4
+address_b[4] => ram_block1a9.PORTBADDR4
+address_b[5] => ram_block1a0.PORTBADDR5
+address_b[5] => ram_block1a1.PORTBADDR5
+address_b[5] => ram_block1a2.PORTBADDR5
+address_b[5] => ram_block1a3.PORTBADDR5
+address_b[5] => ram_block1a4.PORTBADDR5
+address_b[5] => ram_block1a5.PORTBADDR5
+address_b[5] => ram_block1a6.PORTBADDR5
+address_b[5] => ram_block1a7.PORTBADDR5
+address_b[5] => ram_block1a8.PORTBADDR5
+address_b[5] => ram_block1a9.PORTBADDR5
+address_b[6] => ram_block1a0.PORTBADDR6
+address_b[6] => ram_block1a1.PORTBADDR6
+address_b[6] => ram_block1a2.PORTBADDR6
+address_b[6] => ram_block1a3.PORTBADDR6
+address_b[6] => ram_block1a4.PORTBADDR6
+address_b[6] => ram_block1a5.PORTBADDR6
+address_b[6] => ram_block1a6.PORTBADDR6
+address_b[6] => ram_block1a7.PORTBADDR6
+address_b[6] => ram_block1a8.PORTBADDR6
+address_b[6] => ram_block1a9.PORTBADDR6
+address_b[7] => ram_block1a0.PORTBADDR7
+address_b[7] => ram_block1a1.PORTBADDR7
+address_b[7] => ram_block1a2.PORTBADDR7
+address_b[7] => ram_block1a3.PORTBADDR7
+address_b[7] => ram_block1a4.PORTBADDR7
+address_b[7] => ram_block1a5.PORTBADDR7
+address_b[7] => ram_block1a6.PORTBADDR7
+address_b[7] => ram_block1a7.PORTBADDR7
+address_b[7] => ram_block1a8.PORTBADDR7
+address_b[7] => ram_block1a9.PORTBADDR7
+address_b[8] => ram_block1a0.PORTBADDR8
+address_b[8] => ram_block1a1.PORTBADDR8
+address_b[8] => ram_block1a2.PORTBADDR8
+address_b[8] => ram_block1a3.PORTBADDR8
+address_b[8] => ram_block1a4.PORTBADDR8
+address_b[8] => ram_block1a5.PORTBADDR8
+address_b[8] => ram_block1a6.PORTBADDR8
+address_b[8] => ram_block1a7.PORTBADDR8
+address_b[8] => ram_block1a8.PORTBADDR8
+address_b[8] => ram_block1a9.PORTBADDR8
+address_b[9] => ram_block1a0.PORTBADDR9
+address_b[9] => ram_block1a1.PORTBADDR9
+address_b[9] => ram_block1a2.PORTBADDR9
+address_b[9] => ram_block1a3.PORTBADDR9
+address_b[9] => ram_block1a4.PORTBADDR9
+address_b[9] => ram_block1a5.PORTBADDR9
+address_b[9] => ram_block1a6.PORTBADDR9
+address_b[9] => ram_block1a7.PORTBADDR9
+address_b[9] => ram_block1a8.PORTBADDR9
+address_b[9] => ram_block1a9.PORTBADDR9
+address_b[10] => ram_block1a0.PORTBADDR10
+address_b[10] => ram_block1a1.PORTBADDR10
+address_b[10] => ram_block1a2.PORTBADDR10
+address_b[10] => ram_block1a3.PORTBADDR10
+address_b[10] => ram_block1a4.PORTBADDR10
+address_b[10] => ram_block1a5.PORTBADDR10
+address_b[10] => ram_block1a6.PORTBADDR10
+address_b[10] => ram_block1a7.PORTBADDR10
+address_b[10] => ram_block1a8.PORTBADDR10
+address_b[10] => ram_block1a9.PORTBADDR10
+address_b[11] => ram_block1a0.PORTBADDR11
+address_b[11] => ram_block1a1.PORTBADDR11
+address_b[11] => ram_block1a2.PORTBADDR11
+address_b[11] => ram_block1a3.PORTBADDR11
+address_b[11] => ram_block1a4.PORTBADDR11
+address_b[11] => ram_block1a5.PORTBADDR11
+address_b[11] => ram_block1a6.PORTBADDR11
+address_b[11] => ram_block1a7.PORTBADDR11
+address_b[11] => ram_block1a8.PORTBADDR11
+address_b[11] => ram_block1a9.PORTBADDR11
+address_b[12] => ram_block1a0.PORTBADDR12
+address_b[12] => ram_block1a1.PORTBADDR12
+address_b[12] => ram_block1a2.PORTBADDR12
+address_b[12] => ram_block1a3.PORTBADDR12
+address_b[12] => ram_block1a4.PORTBADDR12
+address_b[12] => ram_block1a5.PORTBADDR12
+address_b[12] => ram_block1a6.PORTBADDR12
+address_b[12] => ram_block1a7.PORTBADDR12
+address_b[12] => ram_block1a8.PORTBADDR12
+address_b[12] => ram_block1a9.PORTBADDR12
+clock0 => ram_block1a0.CLK0
+clock0 => ram_block1a1.CLK0
+clock0 => ram_block1a2.CLK0
+clock0 => ram_block1a3.CLK0
+clock0 => ram_block1a4.CLK0
+clock0 => ram_block1a5.CLK0
+clock0 => ram_block1a6.CLK0
+clock0 => ram_block1a7.CLK0
+clock0 => ram_block1a8.CLK0
+clock0 => ram_block1a9.CLK0
+clock1 => ram_block1a0.CLK1
+clock1 => ram_block1a1.CLK1
+clock1 => ram_block1a2.CLK1
+clock1 => ram_block1a3.CLK1
+clock1 => ram_block1a4.CLK1
+clock1 => ram_block1a5.CLK1
+clock1 => ram_block1a6.CLK1
+clock1 => ram_block1a7.CLK1
+clock1 => ram_block1a8.CLK1
+clock1 => ram_block1a9.CLK1
+clocken1 => ram_block1a0.ENA1
+clocken1 => ram_block1a1.ENA1
+clocken1 => ram_block1a2.ENA1
+clocken1 => ram_block1a3.ENA1
+clocken1 => ram_block1a4.ENA1
+clocken1 => ram_block1a5.ENA1
+clocken1 => ram_block1a6.ENA1
+clocken1 => ram_block1a7.ENA1
+clocken1 => ram_block1a8.ENA1
+clocken1 => ram_block1a9.ENA1
+data_a[0] => ram_block1a0.PORTADATAIN
+data_a[1] => ram_block1a1.PORTADATAIN
+data_a[2] => ram_block1a2.PORTADATAIN
+data_a[3] => ram_block1a3.PORTADATAIN
+data_a[4] => ram_block1a4.PORTADATAIN
+data_a[5] => ram_block1a5.PORTADATAIN
+data_a[6] => ram_block1a6.PORTADATAIN
+data_a[7] => ram_block1a7.PORTADATAIN
+data_a[8] => ram_block1a8.PORTADATAIN
+data_a[9] => ram_block1a9.PORTADATAIN
+q_b[0] <= ram_block1a0.PORTBDATAOUT
+q_b[1] <= ram_block1a1.PORTBDATAOUT
+q_b[2] <= ram_block1a2.PORTBDATAOUT
+q_b[3] <= ram_block1a3.PORTBDATAOUT
+q_b[4] <= ram_block1a4.PORTBDATAOUT
+q_b[5] <= ram_block1a5.PORTBDATAOUT
+q_b[6] <= ram_block1a6.PORTBDATAOUT
+q_b[7] <= ram_block1a7.PORTBDATAOUT
+q_b[8] <= ram_block1a8.PORTBDATAOUT
+q_b[9] <= ram_block1a9.PORTBDATAOUT
+wren_a => ram_block1a0.PORTAWE
+wren_a => ram_block1a0.ENA0
+wren_a => ram_block1a1.PORTAWE
+wren_a => ram_block1a1.ENA0
+wren_a => ram_block1a2.PORTAWE
+wren_a => ram_block1a2.ENA0
+wren_a => ram_block1a3.PORTAWE
+wren_a => ram_block1a3.ENA0
+wren_a => ram_block1a4.PORTAWE
+wren_a => ram_block1a4.ENA0
+wren_a => ram_block1a5.PORTAWE
+wren_a => ram_block1a5.ENA0
+wren_a => ram_block1a6.PORTAWE
+wren_a => ram_block1a6.ENA0
+wren_a => ram_block1a7.PORTAWE
+wren_a => ram_block1a7.ENA0
+wren_a => ram_block1a8.PORTAWE
+wren_a => ram_block1a8.ENA0
+wren_a => ram_block1a9.PORTAWE
+wren_a => ram_block1a9.ENA0
+
+
+|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:rd_ptr_count
+aclr => counter_reg_bit[12].IN0
+clock => counter_reg_bit[12].CLK
+clock => counter_reg_bit[11].CLK
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+cnt_en => _.IN0
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+q[11] <= counter_reg_bit[11].DB_MAX_OUTPUT_PORT_TYPE
+q[12] <= counter_reg_bit[12].DB_MAX_OUTPUT_PORT_TYPE
+sclr => _.IN1
+sclr => counter_reg_bit[12].SCLR
+sclr => counter_reg_bit[11].SCLR
+sclr => counter_reg_bit[10].SCLR
+sclr => counter_reg_bit[9].SCLR
+sclr => counter_reg_bit[8].SCLR
+sclr => counter_reg_bit[7].SCLR
+sclr => counter_reg_bit[6].SCLR
+sclr => counter_reg_bit[5].SCLR
+sclr => counter_reg_bit[4].SCLR
+sclr => counter_reg_bit[3].SCLR
+sclr => counter_reg_bit[2].SCLR
+sclr => counter_reg_bit[1].SCLR
+sclr => counter_reg_bit[0].SCLR
+
+
+|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:wr_ptr
+aclr => counter_reg_bit[12].IN0
+clock => counter_reg_bit[12].CLK
+clock => counter_reg_bit[11].CLK
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+cnt_en => _.IN0
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+q[11] <= counter_reg_bit[11].DB_MAX_OUTPUT_PORT_TYPE
+q[12] <= counter_reg_bit[12].DB_MAX_OUTPUT_PORT_TYPE
+sclr => _.IN1
+sclr => counter_reg_bit[12].SCLR
+sclr => counter_reg_bit[11].SCLR
+sclr => counter_reg_bit[10].SCLR
+sclr => counter_reg_bit[9].SCLR
+sclr => counter_reg_bit[8].SCLR
+sclr => counter_reg_bit[7].SCLR
+sclr => counter_reg_bit[6].SCLR
+sclr => counter_reg_bit[5].SCLR
+sclr => counter_reg_bit[4].SCLR
+sclr => counter_reg_bit[3].SCLR
+sclr => counter_reg_bit[2].SCLR
+sclr => counter_reg_bit[1].SCLR
+sclr => counter_reg_bit[0].SCLR
+
+
+|ex18|processor:ALLPASS|d_ff:d
+clk => out~reg0.CLK
+in => out~reg0.DATAIN
+out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex18|processor:ALLPASS|div_by_2:comb_5
+in[0] => ~NO_FANOUT~
+in[1] => out[0].DATAIN
+in[2] => out[1].DATAIN
+in[3] => out[2].DATAIN
+in[4] => out[3].DATAIN
+in[5] => out[4].DATAIN
+in[6] => out[5].DATAIN
+in[7] => out[6].DATAIN
+in[8] => out[7].DATAIN
+in[9] => out[8].DATAIN
+in[9] => out[9].DATAIN
+out[0] <= in[1].DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= in[2].DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= in[3].DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= in[4].DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= in[5].DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= in[6].DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= in[7].DB_MAX_OUTPUT_PORT_TYPE
+out[7] <= in[8].DB_MAX_OUTPUT_PORT_TYPE
+out[8] <= in[9].DB_MAX_OUTPUT_PORT_TYPE
+out[9] <= in[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex18|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex18|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex18|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_4/ex18/db/ex18.hif b/part_4/ex18/db/ex18.hif
new file mode 100755
index 0000000..e79ac16
--- /dev/null
+++ b/part_4/ex18/db/ex18.hif
diff --git a/part_4/ex18/db/ex18.lpc.html b/part_4/ex18/db/ex18.lpc.html
new file mode 100755
index 0000000..e085ae4
--- /dev/null
+++ b/part_4/ex18/db/ex18.lpc.html
@@ -0,0 +1,306 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >SEG2</TD>
+<TD >4</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >7</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SEG0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|comb_5</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|d</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|wr_ptr</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|FIFOram</TD>
+<TD >40</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|fifo_state</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated|dpfifo</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo|scfifo_component|auto_generated</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS|fifo</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >ALLPASS</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_ADC</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >14</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >PWM_DC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_DAC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >GEN_10K</TD>
+<TD >18</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >17</TD>
+<TD >1</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >17</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_4/ex18/db/ex18.lpc.rdb b/part_4/ex18/db/ex18.lpc.rdb
new file mode 100755
index 0000000..7b6cd1a
--- /dev/null
+++ b/part_4/ex18/db/ex18.lpc.rdb
diff --git a/part_4/ex18/db/ex18.lpc.txt b/part_4/ex18/db/ex18.lpc.txt
new file mode 100755
index 0000000..c8da36d
--- /dev/null
+++ b/part_4/ex18/db/ex18.lpc.txt
@@ -0,0 +1,24 @@
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                                                  ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; SEG2                                                                       ; 4     ; 2              ; 0            ; 2              ; 7      ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG1                                                                       ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SEG0                                                                       ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|comb_5                                                             ; 10    ; 0              ; 1            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|d                                                                  ; 2     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|wr_ptr                 ; 4     ; 0              ; 0            ; 0              ; 13     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count           ; 4     ; 0              ; 0            ; 0              ; 13     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|FIFOram                ; 40    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw ; 5     ; 0              ; 0            ; 0              ; 13     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo|fifo_state             ; 5     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated|dpfifo                        ; 14    ; 0              ; 0            ; 0              ; 11     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo|scfifo_component|auto_generated                               ; 13    ; 0              ; 0            ; 0              ; 11     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS|fifo                                                               ; 13    ; 0              ; 0            ; 0              ; 11     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; ALLPASS                                                                    ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_ADC                                                                    ; 4     ; 1              ; 0            ; 1              ; 14     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; PWM_DC                                                                     ; 12    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_DAC                                                                    ; 12    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; GEN_10K                                                                    ; 18    ; 17             ; 0            ; 17             ; 1      ; 17              ; 17            ; 17              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++----------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_4/ex18/db/ex18.map.ammdb b/part_4/ex18/db/ex18.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_4/ex18/db/ex18.map.ammdb
diff --git a/part_4/ex18/db/ex18.map.bpm b/part_4/ex18/db/ex18.map.bpm
new file mode 100755
index 0000000..bb05e4b
--- /dev/null
+++ b/part_4/ex18/db/ex18.map.bpm
diff --git a/part_4/ex18/db/ex18.map.cdb b/part_4/ex18/db/ex18.map.cdb
new file mode 100755
index 0000000..6d1122d
--- /dev/null
+++ b/part_4/ex18/db/ex18.map.cdb
diff --git a/part_4/ex18/db/ex18.map.hdb b/part_4/ex18/db/ex18.map.hdb
new file mode 100755
index 0000000..b772c5d
--- /dev/null
+++ b/part_4/ex18/db/ex18.map.hdb
diff --git a/part_4/ex18/db/ex18.map.kpt b/part_4/ex18/db/ex18.map.kpt
new file mode 100755
index 0000000..83bd6db
--- /dev/null
+++ b/part_4/ex18/db/ex18.map.kpt
diff --git a/part_4/ex18/db/ex18.map.logdb b/part_4/ex18/db/ex18.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex18/db/ex18.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex18/db/ex18.map.qmsg b/part_4/ex18/db/ex18.map.qmsg
new file mode 100755
index 0000000..7c4c2bd
--- /dev/null
+++ b/part_4/ex18/db/ex18.map.qmsg
@@ -0,0 +1,89 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480677968478 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480677968480 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:26:08 2016 " "Processing started: Fri Dec 02 11:26:08 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480677968480 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677968480 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex18 -c ex18 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex18 -c ex18" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677968480 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480677968931 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480677968931 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/mult_echo_synth.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/mult_echo_synth.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "verilog_files/mult_echo_synth.v" "" { Text "C:/New folder/ex18/verilog_files/mult_echo_synth.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977207 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977207 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex18/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977209 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977209 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "verilog_files/spi2adc.v" "" { Text "C:/New folder/ex18/verilog_files/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977210 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977210 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex18/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977212 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977212 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" {  } { { "verilog_files/pulse_gen.v" "" { Text "C:/New folder/ex18/verilog_files/pulse_gen.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977214 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977214 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" {  } { { "verilog_files/multiply_k.v" "" { Text "C:/New folder/ex18/verilog_files/multiply_k.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977215 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977215 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex18/verilog_files/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977217 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977217 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO " "Found entity 1: FIFO" {  } { { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex18/verilog_files/FIFO.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977218 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977218 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/div_by_2.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_by_2 " "Found entity 1: div_by_2" {  } { { "verilog_files/div_by_2.v" "" { Text "C:/New folder/ex18/verilog_files/div_by_2.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977220 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977220 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "verilog_files/delay_ram.v" "" { Text "C:/New folder/ex18/verilog_files/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977222 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977222 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" {  } { { "verilog_files/d_ff.v" "" { Text "C:/New folder/ex18/verilog_files/d_ff.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977223 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977223 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" {  } { { "verilog_files/clktick_16.v" "" { Text "C:/New folder/ex18/verilog_files/clktick_16.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977225 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977225 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977226 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677977227 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977228 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977228 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex18/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977229 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977229 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex18.v 1 1 " "Found 1 design units, including 1 entities, in source file ex18.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex18 " "Found entity 1: ex18" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977231 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977231 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "mult_echo_synth.v(25) " "Verilog HDL Instantiation warning at mult_echo_synth.v(25): instance has no name" {  } { { "verilog_files/mult_echo_synth.v" "" { Text "C:/New folder/ex18/verilog_files/mult_echo_synth.v" 25 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1480677977231 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex18 " "Elaborating entity \"ex18\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1480677977255 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clktick_16 clktick_16:GEN_10K " "Elaborating entity \"clktick_16\" for hierarchy \"clktick_16:GEN_10K\"" {  } { { "ex18.v" "GEN_10K" { Text "C:/New folder/ex18/ex18.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977262 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" {  } { { "ex18.v" "SPI_DAC" { Text "C:/New folder/ex18/ex18.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977274 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" {  } { { "ex18.v" "PWM_DC" { Text "C:/New folder/ex18/ex18.v" 27 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977281 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "ex18.v" "SPI_ADC" { Text "C:/New folder/ex18/ex18.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977286 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:ALLPASS " "Elaborating entity \"processor\" for hierarchy \"processor:ALLPASS\"" {  } { { "ex18.v" "ALLPASS" { Text "C:/New folder/ex18/ex18.v" 40 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977295 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FIFO processor:ALLPASS\|FIFO:fifo " "Elaborating entity \"FIFO\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\"" {  } { { "verilog_files/mult_echo_synth.v" "fifo" { Text "C:/New folder/ex18/verilog_files/mult_echo_synth.v" 19 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977306 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component " "Elaborating entity \"scfifo\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\"" {  } { { "verilog_files/FIFO.v" "scfifo_component" { Text "C:/New folder/ex18/verilog_files/FIFO.v" 73 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977552 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component " "Elaborated megafunction instantiation \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\"" {  } { { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex18/verilog_files/FIFO.v" 73 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977558 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component " "Instantiated megafunction \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 8192 " "Parameter \"lpm_numwords\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 10 " "Parameter \"lpm_width\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 13 " "Parameter \"lpm_widthu\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1480677977559 ""}  } { { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex18/verilog_files/FIFO.v" 73 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1480677977559 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_4l81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_4l81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_4l81 " "Found entity 1: scfifo_4l81" {  } { { "db/scfifo_4l81.tdf" "" { Text "C:/New folder/ex18/db/scfifo_4l81.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977599 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977599 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_4l81 processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated " "Elaborating entity \"scfifo_4l81\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/scfifo.tdf" 300 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977599 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_br81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_br81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_br81 " "Found entity 1: a_dpfifo_br81" {  } { { "db/a_dpfifo_br81.tdf" "" { Text "C:/New folder/ex18/db/a_dpfifo_br81.tdf" 29 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977616 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977616 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_br81 processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo " "Elaborating entity \"a_dpfifo_br81\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\"" {  } { { "db/scfifo_4l81.tdf" "dpfifo" { Text "C:/New folder/ex18/db/scfifo_4l81.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977616 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_4be.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_4be.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_4be " "Found entity 1: a_fefifo_4be" {  } { { "db/a_fefifo_4be.tdf" "" { Text "C:/New folder/ex18/db/a_fefifo_4be.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977631 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977631 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_4be processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|a_fefifo_4be:fifo_state " "Elaborating entity \"a_fefifo_4be\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|a_fefifo_4be:fifo_state\"" {  } { { "db/a_dpfifo_br81.tdf" "fifo_state" { Text "C:/New folder/ex18/db/a_dpfifo_br81.tdf" 40 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977631 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_di7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_di7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_di7 " "Found entity 1: cntr_di7" {  } { { "db/cntr_di7.tdf" "" { Text "C:/New folder/ex18/db/cntr_di7.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977675 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977675 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_di7 processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|a_fefifo_4be:fifo_state\|cntr_di7:count_usedw " "Elaborating entity \"cntr_di7\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|a_fefifo_4be:fifo_state\|cntr_di7:count_usedw\"" {  } { { "db/a_fefifo_4be.tdf" "count_usedw" { Text "C:/New folder/ex18/db/a_fefifo_4be.tdf" 38 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977675 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_44t1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_44t1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_44t1 " "Found entity 1: altsyncram_44t1" {  } { { "db/altsyncram_44t1.tdf" "" { Text "C:/New folder/ex18/db/altsyncram_44t1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977722 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977722 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_44t1 processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|altsyncram_44t1:FIFOram " "Elaborating entity \"altsyncram_44t1\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|altsyncram_44t1:FIFOram\"" {  } { { "db/a_dpfifo_br81.tdf" "FIFOram" { Text "C:/New folder/ex18/db/a_dpfifo_br81.tdf" 41 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977723 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ib.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ib.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ib " "Found entity 1: cntr_1ib" {  } { { "db/cntr_1ib.tdf" "" { Text "C:/New folder/ex18/db/cntr_1ib.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677977778 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677977778 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ib processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|cntr_1ib:rd_ptr_count " "Elaborating entity \"cntr_1ib\" for hierarchy \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|cntr_1ib:rd_ptr_count\"" {  } { { "db/a_dpfifo_br81.tdf" "rd_ptr_count" { Text "C:/New folder/ex18/db/a_dpfifo_br81.tdf" 42 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977778 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d_ff processor:ALLPASS\|d_ff:d " "Elaborating entity \"d_ff\" for hierarchy \"processor:ALLPASS\|d_ff:d\"" {  } { { "verilog_files/mult_echo_synth.v" "d" { Text "C:/New folder/ex18/verilog_files/mult_echo_synth.v" 21 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977784 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_by_2 processor:ALLPASS\|div_by_2:comb_5 " "Elaborating entity \"div_by_2\" for hierarchy \"processor:ALLPASS\|div_by_2:comb_5\"" {  } { { "verilog_files/mult_echo_synth.v" "comb_5" { Text "C:/New folder/ex18/verilog_files/mult_echo_synth.v" 25 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977788 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg hex_to_7seg:SEG0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"hex_to_7seg:SEG0\"" {  } { { "ex18.v" "SEG0" { Text "C:/New folder/ex18/ex18.v" 42 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677977792 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|altsyncram_44t1:FIFOram\|q_b\[0\] " "Synthesized away node \"processor:ALLPASS\|FIFO:fifo\|scfifo:scfifo_component\|scfifo_4l81:auto_generated\|a_dpfifo_br81:dpfifo\|altsyncram_44t1:FIFOram\|q_b\[0\]\"" {  } { { "db/altsyncram_44t1.tdf" "" { Text "C:/New folder/ex18/db/altsyncram_44t1.tdf" 40 2 0 } } { "db/a_dpfifo_br81.tdf" "" { Text "C:/New folder/ex18/db/a_dpfifo_br81.tdf" 41 2 0 } } { "db/scfifo_4l81.tdf" "" { Text "C:/New folder/ex18/db/scfifo_4l81.tdf" 35 2 0 } } { "scfifo.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/scfifo.tdf" 300 3 0 } } { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex18/verilog_files/FIFO.v" 73 0 0 } } { "verilog_files/mult_echo_synth.v" "" { Text "C:/New folder/ex18/verilog_files/mult_echo_synth.v" 19 0 0 } } { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677977879 "|ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a0"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1480677977879 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1480677977879 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] GND " "Pin \"HEX2\[1\]\" is stuck at GND" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1480677978432 "|ex18|HEX2[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1480677978432 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1480677978509 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex18/output_files/ex18.map.smsg " "Generated suppressed messages file C:/New folder/ex18/output_files/ex18.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677978738 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1480677978825 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677978825 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "10 " "Design contains 10 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "No output dependent on input pin \"SW\[5\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "No output dependent on input pin \"SW\[6\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "No output dependent on input pin \"SW\[7\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[8]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1480677978883 "|ex18|SW[9]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1480677978883 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "256 " "Implemented 256 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1480677978884 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1480677978884 ""} { "Info" "ICUT_CUT_TM_LCELLS" "206 " "Implemented 206 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1480677978884 ""} { "Info" "ICUT_CUT_TM_RAMS" "9 " "Implemented 9 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1480677978884 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1480677978884 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "911 " "Peak virtual memory: 911 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480677978899 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:26:18 2016 " "Processing ended: Fri Dec 02 11:26:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480677978899 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480677978899 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480677978899 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677978899 ""}
diff --git a/part_4/ex18/db/ex18.map.rdb b/part_4/ex18/db/ex18.map.rdb
new file mode 100755
index 0000000..5cfd1af
--- /dev/null
+++ b/part_4/ex18/db/ex18.map.rdb
diff --git a/part_4/ex18/db/ex18.map_bb.cdb b/part_4/ex18/db/ex18.map_bb.cdb
new file mode 100755
index 0000000..e549176
--- /dev/null
+++ b/part_4/ex18/db/ex18.map_bb.cdb
diff --git a/part_4/ex18/db/ex18.map_bb.hdb b/part_4/ex18/db/ex18.map_bb.hdb
new file mode 100755
index 0000000..1c44fa2
--- /dev/null
+++ b/part_4/ex18/db/ex18.map_bb.hdb
diff --git a/part_4/ex18/db/ex18.map_bb.logdb b/part_4/ex18/db/ex18.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex18/db/ex18.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex18/db/ex18.pre_map.hdb b/part_4/ex18/db/ex18.pre_map.hdb
new file mode 100755
index 0000000..a721be5
--- /dev/null
+++ b/part_4/ex18/db/ex18.pre_map.hdb
diff --git a/part_4/ex18/db/ex18.root_partition.map.reg_db.cdb b/part_4/ex18/db/ex18.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..7d5e7cc
--- /dev/null
+++ b/part_4/ex18/db/ex18.root_partition.map.reg_db.cdb
diff --git a/part_4/ex18/db/ex18.routing.rdb b/part_4/ex18/db/ex18.routing.rdb
new file mode 100755
index 0000000..ebff4eb
--- /dev/null
+++ b/part_4/ex18/db/ex18.routing.rdb
diff --git a/part_4/ex18/db/ex18.rtlv.hdb b/part_4/ex18/db/ex18.rtlv.hdb
new file mode 100755
index 0000000..4cf170d
--- /dev/null
+++ b/part_4/ex18/db/ex18.rtlv.hdb
diff --git a/part_4/ex18/db/ex18.rtlv_sg.cdb b/part_4/ex18/db/ex18.rtlv_sg.cdb
new file mode 100755
index 0000000..530afd6
--- /dev/null
+++ b/part_4/ex18/db/ex18.rtlv_sg.cdb
diff --git a/part_4/ex18/db/ex18.rtlv_sg_swap.cdb b/part_4/ex18/db/ex18.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..e002f71
--- /dev/null
+++ b/part_4/ex18/db/ex18.rtlv_sg_swap.cdb
diff --git a/part_4/ex18/db/ex18.sld_design_entry.sci b/part_4/ex18/db/ex18.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_4/ex18/db/ex18.sld_design_entry.sci
diff --git a/part_4/ex18/db/ex18.sld_design_entry_dsc.sci b/part_4/ex18/db/ex18.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_4/ex18/db/ex18.sld_design_entry_dsc.sci
diff --git a/part_4/ex18/db/ex18.smart_action.txt b/part_4/ex18/db/ex18.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_4/ex18/db/ex18.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/part_4/ex18/db/ex18.smp_dump.txt b/part_4/ex18/db/ex18.smp_dump.txt
new file mode 100755
index 0000000..d1c5b41
--- /dev/null
+++ b/part_4/ex18/db/ex18.smp_dump.txt
@@ -0,0 +1,12 @@
+
+State Machine - |ex18|spi2adc:SPI_ADC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
+
+State Machine - |ex18|spi2dac:SPI_DAC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
diff --git a/part_4/ex18/db/ex18.sta.qmsg b/part_4/ex18/db/ex18.sta.qmsg
new file mode 100755
index 0000000..dff2c0c
--- /dev/null
+++ b/part_4/ex18/db/ex18.sta.qmsg
@@ -0,0 +1,52 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480678029260 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480678029261 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:27:08 2016 " "Processing started: Fri Dec 02 11:27:08 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480678029261 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678029261 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex18 -c ex18 " "Command: quartus_sta ex18 -c ex18" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678029261 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1480678029385 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678029949 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678029949 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678029994 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678029994 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex18.sdc " "Synopsys Design Constraints File file not found: 'ex18.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030580 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030580 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480678030583 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz " "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480678030583 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clktick_16:GEN_10K\|tick clktick_16:GEN_10K\|tick " "create_clock -period 1.000 -name clktick_16:GEN_10K\|tick clktick_16:GEN_10K\|tick" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480678030583 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2dac:SPI_DAC\|clk_1MHz spi2dac:SPI_DAC\|clk_1MHz " "create_clock -period 1.000 -name spi2dac:SPI_DAC\|clk_1MHz spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1480678030583 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030583 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030586 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030592 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1480678030593 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480678030599 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480678030642 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030642 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.396 " "Worst-case setup slack is -10.396" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -10.396           -1930.765 CLOCK_50  " "  -10.396           -1930.765 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.481             -76.352 spi2adc:SPI_ADC\|clk_1MHz  " "   -4.481             -76.352 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.340             -79.060 spi2dac:SPI_DAC\|clk_1MHz  " "   -4.340             -79.060 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030644 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.446              -3.446 clktick_16:GEN_10K\|tick  " "   -3.446              -3.446 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030644 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030644 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.177 " "Worst-case hold slack is 0.177" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.177               0.000 CLOCK_50  " "    0.177               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.433               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.433               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.752               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.752               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030649 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.922               0.000 clktick_16:GEN_10K\|tick  " "    2.922               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030649 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030649 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030651 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030652 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.166 " "Worst-case minimum pulse width slack is -3.166" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.166           -2106.846 CLOCK_50  " "   -3.166           -2106.846 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724             -35.901 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.724             -35.901 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724             -26.588 spi2dac:SPI_DAC\|clk_1MHz  " "   -0.724             -26.588 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724              -1.136 clktick_16:GEN_10K\|tick  " "   -0.724              -1.136 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678030654 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030654 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480678030671 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678030717 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678032731 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678032849 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480678032858 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678032858 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -10.556 " "Worst-case setup slack is -10.556" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032860 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032860 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  -10.556           -1900.830 CLOCK_50  " "  -10.556           -1900.830 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032860 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.649             -73.671 spi2adc:SPI_ADC\|clk_1MHz  " "   -4.649             -73.671 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032860 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.477             -81.791 spi2dac:SPI_DAC\|clk_1MHz  " "   -4.477             -81.791 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032860 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.689              -3.689 clktick_16:GEN_10K\|tick  " "   -3.689              -3.689 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032860 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678032860 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.251 " "Worst-case hold slack is -0.251" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032865 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032865 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.251              -2.476 CLOCK_50  " "   -0.251              -2.476 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032865 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.516               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.516               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032865 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.750               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.750               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032865 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.173               0.000 clktick_16:GEN_10K\|tick  " "    3.173               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032865 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678032865 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678032867 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678032868 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.166 " "Worst-case minimum pulse width slack is -3.166" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.166           -2105.141 CLOCK_50  " "   -3.166           -2105.141 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724             -35.136 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.724             -35.136 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724             -26.303 spi2dac:SPI_DAC\|clk_1MHz  " "   -0.724             -26.303 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.724              -1.131 clktick_16:GEN_10K\|tick  " "   -0.724              -1.131 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678032870 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678032870 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480678032886 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678033147 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034155 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034228 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480678034231 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034231 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.377 " "Worst-case setup slack is -4.377" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034233 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034233 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -4.377            -721.833 CLOCK_50  " "   -4.377            -721.833 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034233 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.710             -26.172 spi2dac:SPI_DAC\|clk_1MHz  " "   -1.710             -26.172 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034233 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.537             -25.590 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.537             -25.590 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034233 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.128              -1.128 clktick_16:GEN_10K\|tick  " "   -1.128              -1.128 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034233 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034233 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.177 " "Worst-case hold slack is -0.177" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034237 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034237 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.177              -0.991 CLOCK_50  " "   -0.177              -0.991 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034237 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.172               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.172               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034237 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.240               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.240               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034237 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.116               0.000 clktick_16:GEN_10K\|tick  " "    1.116               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034237 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034237 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034239 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034240 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1313.734 CLOCK_50  " "   -2.174           -1313.734 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.082               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.082               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.104               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.104               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034242 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.126               0.000 clktick_16:GEN_10K\|tick  " "    0.126               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034242 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034242 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1480678034258 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034426 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1480678034429 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034429 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.956 " "Worst-case setup slack is -3.956" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034431 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034431 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.956            -615.142 CLOCK_50  " "   -3.956            -615.142 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034431 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.593             -24.610 spi2dac:SPI_DAC\|clk_1MHz  " "   -1.593             -24.610 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034431 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.474             -23.182 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.474             -23.182 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034431 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.111              -1.111 clktick_16:GEN_10K\|tick  " "   -1.111              -1.111 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034431 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034431 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.307 " "Worst-case hold slack is -0.307" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034435 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034435 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.307             -14.229 CLOCK_50  " "   -0.307             -14.229 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034435 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.157               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.157               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034435 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.212               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.212               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034435 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.109               0.000 clktick_16:GEN_10K\|tick  " "    1.109               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034435 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034435 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034437 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034439 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1314.254 CLOCK_50  " "   -2.174           -1314.254 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.104               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.104               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.122               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.122               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.131               0.000 clktick_16:GEN_10K\|tick  " "    0.131               0.000 clktick_16:GEN_10K\|tick " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1480678034441 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678034441 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678035775 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678035775 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1312 " "Peak virtual memory: 1312 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480678035827 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 11:27:15 2016 " "Processing ended: Fri Dec 02 11:27:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480678035827 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480678035827 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480678035827 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1480678035827 ""}
diff --git a/part_4/ex18/db/ex18.sta.rdb b/part_4/ex18/db/ex18.sta.rdb
new file mode 100755
index 0000000..6b59e93
--- /dev/null
+++ b/part_4/ex18/db/ex18.sta.rdb
diff --git a/part_4/ex18/db/ex18.sta_cmp.8_H7_slow_1100mv_85c.tdb b/part_4/ex18/db/ex18.sta_cmp.8_H7_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..44ee8f6
--- /dev/null
+++ b/part_4/ex18/db/ex18.sta_cmp.8_H7_slow_1100mv_85c.tdb
diff --git a/part_4/ex18/db/ex18.tis_db_list.ddb b/part_4/ex18/db/ex18.tis_db_list.ddb
new file mode 100755
index 0000000..29334c3
--- /dev/null
+++ b/part_4/ex18/db/ex18.tis_db_list.ddb
diff --git a/part_4/ex18/db/ex18.tiscmp.fast_1100mv_0c.ddb b/part_4/ex18/db/ex18.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..371f422
--- /dev/null
+++ b/part_4/ex18/db/ex18.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_4/ex18/db/ex18.tiscmp.fast_1100mv_85c.ddb b/part_4/ex18/db/ex18.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..ed887a9
--- /dev/null
+++ b/part_4/ex18/db/ex18.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_4/ex18/db/ex18.tiscmp.fastest_slow_1100mv_0c.ddb b/part_4/ex18/db/ex18.tiscmp.fastest_slow_1100mv_0c.ddb
new file mode 100755
index 0000000..75e243a
--- /dev/null
+++ b/part_4/ex18/db/ex18.tiscmp.fastest_slow_1100mv_0c.ddb
diff --git a/part_4/ex18/db/ex18.tiscmp.fastest_slow_1100mv_85c.ddb b/part_4/ex18/db/ex18.tiscmp.fastest_slow_1100mv_85c.ddb
new file mode 100755
index 0000000..5e54f41
--- /dev/null
+++ b/part_4/ex18/db/ex18.tiscmp.fastest_slow_1100mv_85c.ddb
diff --git a/part_4/ex18/db/ex18.tiscmp.slow_1100mv_0c.ddb b/part_4/ex18/db/ex18.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..ef070da
--- /dev/null
+++ b/part_4/ex18/db/ex18.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_4/ex18/db/ex18.tiscmp.slow_1100mv_85c.ddb b/part_4/ex18/db/ex18.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..0d833c7
--- /dev/null
+++ b/part_4/ex18/db/ex18.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_4/ex18/db/ex18.tmw_info b/part_4/ex18/db/ex18.tmw_info
new file mode 100755
index 0000000..78b56b0
--- /dev/null
+++ b/part_4/ex18/db/ex18.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:01:09
+start_analysis_synthesis:s:00:00:12-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:41-start_full_compilation
+start_assembler:s:00:00:08-start_full_compilation
+start_timing_analyzer:s:00:00:08-start_full_compilation
diff --git a/part_4/ex18/db/ex18.vpr.ammdb b/part_4/ex18/db/ex18.vpr.ammdb
new file mode 100755
index 0000000..3efff7f
--- /dev/null
+++ b/part_4/ex18/db/ex18.vpr.ammdb
diff --git a/part_4/ex18/db/ex18_partition_pins.json b/part_4/ex18/db/ex18_partition_pins.json
new file mode 100755
index 0000000..884712b
--- /dev/null
+++ b/part_4/ex18/db/ex18_partition_pins.json
@@ -0,0 +1,129 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_LD",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "PWM_OUT",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDO",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
+\ No newline at end of file
diff --git a/part_4/ex18/db/prev_cmp_ex18.qmsg b/part_4/ex18/db/prev_cmp_ex18.qmsg
new file mode 100755
index 0000000..215af30
--- /dev/null
+++ b/part_4/ex18/db/prev_cmp_ex18.qmsg
@@ -0,0 +1,61 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480677907866 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480677907868 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 11:25:07 2016 " "Processing started: Fri Dec 02 11:25:07 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480677907868 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677907868 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex18 -c ex18 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex18 -c ex18" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677907868 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1480677908290 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1480677908290 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/mult_echo_synth.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/mult_echo_synth.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "verilog_files/mult_echo_synth.v" "" { Text "C:/New folder/ex18/verilog_files/mult_echo_synth.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916577 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916577 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex18/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916581 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916581 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "verilog_files/spi2adc.v" "" { Text "C:/New folder/ex18/verilog_files/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916584 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916584 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex18/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916586 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916586 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" {  } { { "verilog_files/pulse_gen.v" "" { Text "C:/New folder/ex18/verilog_files/pulse_gen.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916588 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916588 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" {  } { { "verilog_files/multiply_k.v" "" { Text "C:/New folder/ex18/verilog_files/multiply_k.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916590 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916590 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex18/verilog_files/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916591 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916591 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/fifo_bb.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/fifo_bb.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO " "Found entity 1: FIFO" {  } { { "verilog_files/FIFO_bb.v" "" { Text "C:/New folder/ex18/verilog_files/FIFO_bb.v" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916593 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916593 ""}
+{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "FIFO FIFO.v(40) " "Verilog HDL error at FIFO.v(40): module \"FIFO\" cannot be declared more than once" {  } { { "verilog_files/FIFO.v" "" { Text "C:/New folder/ex18/verilog_files/FIFO.v" 40 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "Analysis & Synthesis" 0 -1 1480677916595 ""}
+{ "Info" "IVRFX_HDL_SEE_DECLARATION" "FIFO FIFO_bb.v(35) " "HDL info at FIFO_bb.v(35): see declaration for object \"FIFO\"" {  } { { "verilog_files/FIFO_bb.v" "" { Text "C:/New folder/ex18/verilog_files/FIFO_bb.v" 35 0 0 } }  } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1480677916595 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/fifo.v 0 0 " "Found 0 design units, including 0 entities, in source file verilog_files/fifo.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916595 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/div_by_2.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_by_2 " "Found entity 1: div_by_2" {  } { { "verilog_files/div_by_2.v" "" { Text "C:/New folder/ex18/verilog_files/div_by_2.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916597 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916597 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "verilog_files/delay_ram.v" "" { Text "C:/New folder/ex18/verilog_files/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916599 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916599 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" {  } { { "verilog_files/d_ff.v" "" { Text "C:/New folder/ex18/verilog_files/d_ff.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916600 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916600 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" {  } { { "verilog_files/clktick_16.v" "" { Text "C:/New folder/ex18/verilog_files/clktick_16.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916602 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916602 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916604 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex18/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916605 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916605 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex18/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916607 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916607 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex18.v 1 1 " "Found 1 design units, including 1 entities, in source file ex18.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex18 " "Found entity 1: ex18" {  } { { "ex18.v" "" { Text "C:/New folder/ex18/ex18.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1480677916608 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916608 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex18/output_files/ex18.map.smsg " "Generated suppressed messages file C:/New folder/ex18/output_files/ex18.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916627 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "833 " "Peak virtual memory: 833 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480677916663 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Dec 02 11:25:16 2016 " "Processing ended: Fri Dec 02 11:25:16 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480677916663 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480677916663 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480677916663 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677916663 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1  " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" {  } {  } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1480677917271 ""}
diff --git a/part_4/ex18/db/scfifo_4l81.tdf b/part_4/ex18/db/scfifo_4l81.tdf
new file mode 100755
index 0000000..64b9640
--- /dev/null
+++ b/part_4/ex18/db/scfifo_4l81.tdf
@@ -0,0 +1,48 @@
+--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Cyclone V" LPM_NUMWORDS=8192 LPM_SHOWAHEAD="OFF" LPM_WIDTH=10 LPM_WIDTHU=13 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data full q rdreq wrreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO"
+--VERSION_BEGIN 16.0 cbx_altdpram 2016:04:27:18:05:34:SJ cbx_altera_syncram 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_scfifo 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION a_dpfifo_br81 (clock, data[9..0], rreq, sclr, wreq)
+RETURNS ( full, q[9..0]);
+
+--synthesis_resources = lut 39 M10K 10 reg 41 
+SUBDESIGN scfifo_4l81
+( 
+	clock	:	input;
+	data[9..0]	:	input;
+	full	:	output;
+	q[9..0]	:	output;
+	rdreq	:	input;
+	wrreq	:	input;
+) 
+VARIABLE 
+	dpfifo : a_dpfifo_br81;
+	sclr	: NODE;
+
+BEGIN 
+	dpfifo.clock = clock;
+	dpfifo.data[] = data[];
+	dpfifo.rreq = rdreq;
+	dpfifo.sclr = sclr;
+	dpfifo.wreq = wrreq;
+	full = dpfifo.full;
+	q[] = dpfifo.q[];
+	sclr = GND;
+END;
+--VALID FILE
diff --git a/part_4/ex18/ex18.qpf b/part_4/ex18/ex18.qpf
new file mode 100755
index 0000000..edf884b
--- /dev/null
+++ b/part_4/ex18/ex18.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:20:34  December 02, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "11:20:34  December 02, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex18"
diff --git a/part_2/ex9_final/ex9.qsf.bak b/part_4/ex18/ex18.qsf
index d4eef07..5f156c3 100755
--- a/part_2/ex9_final/ex9.qsf.bak
+++ b/part_4/ex18/ex18.qsf
@@ -19,14 +19,14 @@
 #
 # Quartus Prime
 # Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
+# Date created = 11:20:34  December 02, 2016
 #
 # -------------------------------------------------------------------------- #
 #
 # Notes:
 #
 # 1) The default values for assignments are stored in the file:
-#		ex9_assignment_defaults.qdf
+#		ex18_assignment_defaults.qdf
 #    If this file doesn't exist, see file:
 #		assignment_defaults.qdf
 #
@@ -38,27 +38,33 @@
 
 
 set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name DEVICE 5CSEMA5F31C6
-set_global_assignment -name TOP_LEVEL_ENTITY ex9
+set_global_assignment -name DEVICE 5CGXFC7C7F23C8
+set_global_assignment -name TOP_LEVEL_ENTITY ex18
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:20:34  DECEMBER 02, 2016"
 set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v
-set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v
-set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v
+set_global_assignment -name VERILOG_FILE verilog_files/mult_echo_synth.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2dac.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2adc.v
+set_global_assignment -name VERILOG_FILE verilog_files/pwm.v
+set_global_assignment -name VERILOG_FILE verilog_files/pulse_gen.v
+set_global_assignment -name VERILOG_FILE verilog_files/multiply_k.v
 set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
-set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v
-set_global_assignment -name VERILOG_FILE verilog_files/delay.v
-set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/FIFO.v
+set_global_assignment -name QIP_FILE verilog_files/FIFO.qip
+set_global_assignment -name VERILOG_FILE verilog_files/div_by_2.v
+set_global_assignment -name VERILOG_FILE verilog_files/delay_ram.v
+set_global_assignment -name VERILOG_FILE verilog_files/d_ff.v
+set_global_assignment -name VERILOG_FILE verilog_files/clktick_16.v
 set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
 set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
-set_global_assignment -name VERILOG_FILE verilog_files/ex9.v
+set_global_assignment -name VERILOG_FILE ex18.v
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
diff --git a/part_4/ex18/ex18.qws b/part_4/ex18/ex18.qws
new file mode 100755
index 0000000..6dab36e
--- /dev/null
+++ b/part_4/ex18/ex18.qws
diff --git a/part_4/ex18/ex18.v b/part_4/ex18/ex18.v
new file mode 100755
index 0000000..0e33a83
--- /dev/null
+++ b/part_4/ex18/ex18.v
@@ -0,0 +1,46 @@
+module ex18 (CLOCK_50, SW, HEX0, HEX1, HEX2, 
+					DAC_SDI, DAC_SCK, DAC_CS, DAC_LD,
+					ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT);
+
+	input			CLOCK_50;		// DE0 50MHz system clock
+	input [9:0]	SW;				// 10 slide switches to specify address to ROM
+	output [6:0] HEX0, HEX1, HEX2;
+	output 		DAC_SDI;			//Serial data out to SDI of the DAC
+	output 		DAC_SCK;				//Serial clock signal to both DAC and ADC
+	output		DAC_CS;			//Chip select to the DAC, low active
+	output 		DAC_LD;			//Load new data to DAC, low active	
+	output 		ADC_SDI;			//Serial data out to SDI of the ADC
+	output 		ADC_SCK;		// ADC Clock signal
+	output		ADC_CS;			//Chip select to the ADC, low active
+	input 		ADC_SDO;			//Converted serial data from ADC	
+	output		PWM_OUT;			// PWM output to R channel
+		
+	wire			tick_10k;		// internal clock at 10kHz
+	wire [9:0] 	data_in;		// converted data from ADC
+	wire [9:0] 	data_out;	// processed data to DAC
+	wire			data_valid;
+	wire			DAC_SCK, ADC_SCK;
+	
+	clktick_16  GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k);  	// generate 10KHz sampling clock ticks
+	spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, 		// send processed sample to DAC
+					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);		// order of signals matter
+	pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT);		// output via PWM - R-channel
+					
+	spi2adc SPI_ADC (												// perform a A-to-D conversion
+		.sysclk (CLOCK_50), 										// order of parameters do not matter
+		.channel (1'b1), 											// use only CH1
+		.start (tick_10k),
+		.data_from_adc (data_in),
+		.data_valid (data_valid),
+		.sdata_to_adc (ADC_SDI),
+		.adc_cs (ADC_CS),
+		.adc_sck (ADC_SCK),
+		.sdata_from_adc (ADC_SDO));		
+					
+	processor	ALLPASS (CLOCK_50, tick_10k, data_in, data_out);	// do some processing on the data
+	
+	hex_to_7seg		SEG0 (HEX0, data_in[3:0]);			
+	hex_to_7seg		SEG1 (HEX1, data_in[7:4]);			
+	hex_to_7seg		SEG2 (HEX2, {2'b0,data_in[9:8]});			
+		
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex18/ex18.v.bak b/part_4/ex18/ex18.v.bak
new file mode 100755
index 0000000..70dcc7a
--- /dev/null
+++ b/part_4/ex18/ex18.v.bak
@@ -0,0 +1,46 @@
+module ex17 (CLOCK_50, SW, HEX0, HEX1, HEX2, 
+					DAC_SDI, DAC_SCK, DAC_CS, DAC_LD,
+					ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT);
+
+	input			CLOCK_50;		// DE0 50MHz system clock
+	input [9:0]	SW;				// 10 slide switches to specify address to ROM
+	output [6:0] HEX0, HEX1, HEX2;
+	output 		DAC_SDI;			//Serial data out to SDI of the DAC
+	output 		DAC_SCK;				//Serial clock signal to both DAC and ADC
+	output		DAC_CS;			//Chip select to the DAC, low active
+	output 		DAC_LD;			//Load new data to DAC, low active	
+	output 		ADC_SDI;			//Serial data out to SDI of the ADC
+	output 		ADC_SCK;		// ADC Clock signal
+	output		ADC_CS;			//Chip select to the ADC, low active
+	input 		ADC_SDO;			//Converted serial data from ADC	
+	output		PWM_OUT;			// PWM output to R channel
+		
+	wire			tick_10k;		// internal clock at 10kHz
+	wire [9:0] 	data_in;		// converted data from ADC
+	wire [9:0] 	data_out;	// processed data to DAC
+	wire			data_valid;
+	wire			DAC_SCK, ADC_SCK;
+	
+	clktick_16  GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k);  	// generate 10KHz sampling clock ticks
+	spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, 		// send processed sample to DAC
+					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);		// order of signals matter
+	pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT);		// output via PWM - R-channel
+					
+	spi2adc SPI_ADC (												// perform a A-to-D conversion
+		.sysclk (CLOCK_50), 										// order of parameters do not matter
+		.channel (1'b1), 											// use only CH1
+		.start (tick_10k),
+		.data_from_adc (data_in),
+		.data_valid (data_valid),
+		.sdata_to_adc (ADC_SDI),
+		.adc_cs (ADC_CS),
+		.adc_sck (ADC_SCK),
+		.sdata_from_adc (ADC_SDO));		
+					
+	processor	ALLPASS (CLOCK_50, tick_10k, data_in, data_out);	// do some processing on the data
+	
+	hex_to_7seg		SEG0 (HEX0, data_in[3:0]);			
+	hex_to_7seg		SEG1 (HEX1, data_in[7:4]);			
+	hex_to_7seg		SEG2 (HEX2, {2'b0,data_in[9:8]});			
+		
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex18/incremental_db/README b/part_4/ex18/incremental_db/README
new file mode 100755
index 0000000..6191fbe
--- /dev/null
+++ b/part_4/ex18/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.db_info b/part_4/ex18/incremental_db/compiled_partitions/ex18.db_info
new file mode 100755
index 0000000..5741279
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Dec 02 11:26:17 2016
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.ammdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.ammdb
new file mode 100755
index 0000000..ce40bd3
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.ammdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.cdb
new file mode 100755
index 0000000..46568a5
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.dfp b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.dfp
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..932ac81
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.hdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..70fd6ae
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.hdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.sig b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hdb
new file mode 100755
index 0000000..20b2f88
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.hdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.logdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.rcfdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..ae2837e
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.cmp.rcfdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.cdb
new file mode 100755
index 0000000..e4858e2
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.dpi b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.dpi
new file mode 100755
index 0000000..32750a7
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.dpi
diff --git a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.cdb
index 50abb6e..b4e2fdd 100755
--- a/part_2/ex9_final/incremental_db/compiled_partitions/ex9.root_partition.map.hbdb.cdb
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.hb_info b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.hb_info
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.hdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..4ca719f
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.hdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.sig b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hdb
new file mode 100755
index 0000000..79c0e44
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.hdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.kpt b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.kpt
new file mode 100755
index 0000000..c7110fc
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.kpt
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.olf.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.olf.cdb
new file mode 100755
index 0000000..8dd6e81
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.olf.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.olm.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.olm.cdb
new file mode 100755
index 0000000..84b3bbc
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.olm.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.oln.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.oln.cdb
new file mode 100755
index 0000000..a3b0a24
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.oln.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.opi b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.opi
@@ -0,0 +1 @@
+1
+\ No newline at end of file
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orf.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orf.cdb
new file mode 100755
index 0000000..3b57ac3
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orf.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orm.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orm.cdb
new file mode 100755
index 0000000..5ff6456
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orm.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orn.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orn.cdb
new file mode 100755
index 0000000..8b6fcb3
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.map.orn.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.cdb
new file mode 100755
index 0000000..e4858e2
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hbdb.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..b4e2fdd
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hbdb.cdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hbdb.hdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..4ca719f
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hbdb.hdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hdb
new file mode 100755
index 0000000..79c0e44
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.hdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.kpt b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.kpt
new file mode 100755
index 0000000..c7110fc
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.root_partition.rrp.kpt
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.rrp.hdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.rrp.hdb
new file mode 100755
index 0000000..eeed7c5
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.rrp.hdb
diff --git a/part_4/ex18/incremental_db/compiled_partitions/ex18.rrs.cdb b/part_4/ex18/incremental_db/compiled_partitions/ex18.rrs.cdb
new file mode 100755
index 0000000..af42266
--- /dev/null
+++ b/part_4/ex18/incremental_db/compiled_partitions/ex18.rrs.cdb
diff --git a/part_4/ex18/output_files/ex18.asm.rpt b/part_4/ex18/output_files/ex18.asm.rpt
new file mode 100755
index 0000000..e776a74
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for ex18
+Fri Dec 02 11:27:07 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/New folder/ex18/output_files/ex18.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Fri Dec 02 11:27:07 2016 ;
+; Revision Name         ; ex18                                  ;
+; Top-level Entity Name ; ex18                                  ;
+; Family                ; Cyclone V                             ;
+; Device                ; 5CGXFC7C7F23C8                        ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings               ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++------------------------------------------+
+; Assembler Generated Files                ;
++------------------------------------------+
+; File Name                                ;
++------------------------------------------+
+; C:/New folder/ex18/output_files/ex18.sof ;
++------------------------------------------+
+
+
++--------------------------------------------------------------------+
+; Assembler Device Options: C:/New folder/ex18/output_files/ex18.sof ;
++----------------+---------------------------------------------------+
+; Option         ; Setting                                           ;
++----------------+---------------------------------------------------+
+; Device         ; 5CGXFC7C7F23C8                                    ;
+; JTAG usercode  ; 0x011D4942                                        ;
+; Checksum       ; 0x011D4942                                        ;
++----------------+---------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 11:27:00 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex18 -c ex18
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+    Info: Peak virtual memory: 884 megabytes
+    Info: Processing ended: Fri Dec 02 11:27:07 2016
+    Info: Elapsed time: 00:00:07
+    Info: Total CPU time (on all processors): 00:00:07
+
+
diff --git a/part_4/ex18/output_files/ex18.done b/part_4/ex18/output_files/ex18.done
new file mode 100755
index 0000000..446336c
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.done
@@ -0,0 +1 @@
+Fri Dec 02 11:27:16 2016
diff --git a/part_4/ex18/output_files/ex18.fit.rpt b/part_4/ex18/output_files/ex18.fit.rpt
new file mode 100755
index 0000000..d9b2cd4
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.fit.rpt
@@ -0,0 +1,1555 @@
+Fitter report for ex18
+Fri Dec 02 11:26:58 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. Fitter Resource Utilization by Entity
+ 18. Delay Chain Summary
+ 19. Pad To Core Delay Chain Fanout
+ 20. Control Signals
+ 21. Global & Other Fast Signals
+ 22. Fitter RAM Summary
+ 23. Routing Usage Summary
+ 24. I/O Rules Summary
+ 25. I/O Rules Details
+ 26. I/O Rules Matrix
+ 27. Fitter Device Options
+ 28. Operating Settings and Conditions
+ 29. Estimated Delay Added for Hold Timing Summary
+ 30. Estimated Delay Added for Hold Timing Details
+ 31. Fitter Messages
+ 32. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Fri Dec 02 11:26:58 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex18                                            ;
+; Top-level Entity Name           ; ex18                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CGXFC7C7F23C8                                  ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 90 / 56,480 ( < 1 % )                           ;
+; Total registers                 ; 169                                             ;
+; Total pins                      ; 41 / 268 ( 15 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 73,728 / 7,024,640 ( 1 % )                      ;
+; Total RAM Blocks                ; 9 / 686 ( 1 % )                                 ;
+; Total DSP Blocks                ; 0 / 156 ( 0 % )                                 ;
+; Total HSSI RX PCSs              ; 0 / 6 ( 0 % )                                   ;
+; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % )                                   ;
+; Total HSSI TX PCSs              ; 0 / 6 ( 0 % )                                   ;
+; Total HSSI PMA TX Serializers   ; 0 / 6 ( 0 % )                                   ;
+; Total PLLs                      ; 0 / 13 ( 0 % )                                  ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CGXFC7C7F23C8                        ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.03        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   1.0%      ;
+;     Processor 3            ;   0.9%      ;
+;     Processor 4            ;   0.8%      ;
++----------------------------+-------------+
+
+
++------------------------------------------+
+; I/O Assignment Warnings                  ;
++----------+-------------------------------+
+; Pin Name ; Reason                        ;
++----------+-------------------------------+
+; SW[0]    ; Incomplete set of assignments ;
+; SW[1]    ; Incomplete set of assignments ;
+; SW[2]    ; Incomplete set of assignments ;
+; SW[3]    ; Incomplete set of assignments ;
+; SW[4]    ; Incomplete set of assignments ;
+; SW[5]    ; Incomplete set of assignments ;
+; SW[6]    ; Incomplete set of assignments ;
+; SW[7]    ; Incomplete set of assignments ;
+; SW[8]    ; Incomplete set of assignments ;
+; SW[9]    ; Incomplete set of assignments ;
+; HEX0[0]  ; Incomplete set of assignments ;
+; HEX0[1]  ; Incomplete set of assignments ;
+; HEX0[2]  ; Incomplete set of assignments ;
+; HEX0[3]  ; Incomplete set of assignments ;
+; HEX0[4]  ; Incomplete set of assignments ;
+; HEX0[5]  ; Incomplete set of assignments ;
+; HEX0[6]  ; Incomplete set of assignments ;
+; HEX1[0]  ; Incomplete set of assignments ;
+; HEX1[1]  ; Incomplete set of assignments ;
+; HEX1[2]  ; Incomplete set of assignments ;
+; HEX1[3]  ; Incomplete set of assignments ;
+; HEX1[4]  ; Incomplete set of assignments ;
+; HEX1[5]  ; Incomplete set of assignments ;
+; HEX1[6]  ; Incomplete set of assignments ;
+; HEX2[0]  ; Incomplete set of assignments ;
+; HEX2[1]  ; Incomplete set of assignments ;
+; HEX2[2]  ; Incomplete set of assignments ;
+; HEX2[3]  ; Incomplete set of assignments ;
+; HEX2[4]  ; Incomplete set of assignments ;
+; HEX2[5]  ; Incomplete set of assignments ;
+; HEX2[6]  ; Incomplete set of assignments ;
+; DAC_SDI  ; Incomplete set of assignments ;
+; DAC_SCK  ; Incomplete set of assignments ;
+; DAC_CS   ; Incomplete set of assignments ;
+; DAC_LD   ; Incomplete set of assignments ;
+; ADC_SDI  ; Incomplete set of assignments ;
+; ADC_SCK  ; Incomplete set of assignments ;
+; ADC_CS   ; Incomplete set of assignments ;
+; PWM_OUT  ; Incomplete set of assignments ;
+; CLOCK_50 ; Incomplete set of assignments ;
+; ADC_SDO  ; Incomplete set of assignments ;
+; SW[0]    ; Missing location assignment   ;
+; SW[1]    ; Missing location assignment   ;
+; SW[2]    ; Missing location assignment   ;
+; SW[3]    ; Missing location assignment   ;
+; SW[4]    ; Missing location assignment   ;
+; SW[5]    ; Missing location assignment   ;
+; SW[6]    ; Missing location assignment   ;
+; SW[7]    ; Missing location assignment   ;
+; SW[8]    ; Missing location assignment   ;
+; SW[9]    ; Missing location assignment   ;
+; HEX0[0]  ; Missing location assignment   ;
+; HEX0[1]  ; Missing location assignment   ;
+; HEX0[2]  ; Missing location assignment   ;
+; HEX0[3]  ; Missing location assignment   ;
+; HEX0[4]  ; Missing location assignment   ;
+; HEX0[5]  ; Missing location assignment   ;
+; HEX0[6]  ; Missing location assignment   ;
+; HEX1[0]  ; Missing location assignment   ;
+; HEX1[1]  ; Missing location assignment   ;
+; HEX1[2]  ; Missing location assignment   ;
+; HEX1[3]  ; Missing location assignment   ;
+; HEX1[4]  ; Missing location assignment   ;
+; HEX1[5]  ; Missing location assignment   ;
+; HEX1[6]  ; Missing location assignment   ;
+; HEX2[0]  ; Missing location assignment   ;
+; HEX2[1]  ; Missing location assignment   ;
+; HEX2[2]  ; Missing location assignment   ;
+; HEX2[3]  ; Missing location assignment   ;
+; HEX2[4]  ; Missing location assignment   ;
+; HEX2[5]  ; Missing location assignment   ;
+; HEX2[6]  ; Missing location assignment   ;
+; DAC_SDI  ; Missing location assignment   ;
+; DAC_SCK  ; Missing location assignment   ;
+; DAC_CS   ; Missing location assignment   ;
+; DAC_LD   ; Missing location assignment   ;
+; ADC_SDI  ; Missing location assignment   ;
+; ADC_SCK  ; Missing location assignment   ;
+; ADC_CS   ; Missing location assignment   ;
+; PWM_OUT  ; Missing location assignment   ;
+; CLOCK_50 ; Missing location assignment   ;
+; ADC_SDO  ; Missing location assignment   ;
++----------+-------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                                ;
++------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------+------------------+-----------------------+
+; Node                         ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                       ; Destination Port ; Destination Port Name ;
++------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0        ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                        ;                  ;                       ;
+; clktick_16:GEN_10K|count[3]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[3]~DUPLICATE  ;                  ;                       ;
+; clktick_16:GEN_10K|count[5]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[5]~DUPLICATE  ;                  ;                       ;
+; clktick_16:GEN_10K|count[9]  ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[9]~DUPLICATE  ;                  ;                       ;
+; clktick_16:GEN_10K|count[10] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[10]~DUPLICATE ;                  ;                       ;
+; clktick_16:GEN_10K|count[11] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[11]~DUPLICATE ;                  ;                       ;
+; clktick_16:GEN_10K|count[13] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[13]~DUPLICATE ;                  ;                       ;
+; clktick_16:GEN_10K|count[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; clktick_16:GEN_10K|count[14]~DUPLICATE ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[0]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[0]~DUPLICATE       ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[2]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[2]~DUPLICATE       ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[3]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[3]~DUPLICATE       ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[4]       ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[4]~DUPLICATE       ;                  ;                       ;
+; spi2adc:SPI_ADC|state[2]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[2]~DUPLICATE     ;                  ;                       ;
+; spi2adc:SPI_ADC|state[3]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[3]~DUPLICATE     ;                  ;                       ;
+; spi2dac:SPI_DAC|state[3]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:SPI_DAC|state[3]~DUPLICATE     ;                  ;                       ;
+; spi2dac:SPI_DAC|state[4]     ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:SPI_DAC|state[4]~DUPLICATE     ;                  ;                       ;
++------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 404 ) ; 0.00 % ( 0 / 404 )         ; 0.00 % ( 0 / 404 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 404 ) ; 0.00 % ( 0 / 404 )         ; 0.00 % ( 0 / 404 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 404 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/New folder/ex18/output_files/ex18.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 90 / 56,480        ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 90                 ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 98 / 56,480        ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 63                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 20                 ;       ;
+;         [c] ALMs used for registers                         ; 15                 ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 8 / 56,480         ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 56,480         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 14 / 5,648         ; < 1 % ;
+;     -- Logic LABs                                           ; 14                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 158                ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 8                  ;       ;
+;     -- 5 input functions                                    ; 19                 ;       ;
+;     -- 4 input functions                                    ; 27                 ;       ;
+;     -- <=3 input functions                                  ; 104                ;       ;
+; Combinational ALUT usage for route-throughs                 ; 12                 ;       ;
+; Dedicated logic registers                                   ; 169                ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 154 / 112,960      ; < 1 % ;
+;         -- Secondary logic registers                        ; 15 / 112,960       ; < 1 % ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 154                ;       ;
+;         -- Routing optimization registers                   ; 15                 ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 41 / 268           ; 15 %  ;
+;     -- Clock pins                                           ; 1 / 11             ; 9 %   ;
+;     -- Dedicated input pins                                 ; 0 / 23             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 9 / 686            ; 1 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 73,728 / 7,024,640 ; 1 %   ;
+; Total block memory implementation bits                      ; 92,160 / 7,024,640 ; 1 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 156            ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 7              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 88             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 120            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 120            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Hard IPs                                                    ; 0 / 1              ; 0 %   ;
+; Standard RX PCSs                                            ; 0 / 6              ; 0 %   ;
+; HSSI PMA RX Deserializers                                   ; 0 / 6              ; 0 %   ;
+; Standard TX PCSs                                            ; 0 / 6              ; 0 %   ;
+; HSSI PMA TX Serializers                                     ; 0 / 6              ; 0 %   ;
+; Channel PLLs                                                ; 0 / 6              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 3              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.2% / 0.2% / 0.2% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 4.6% / 4.9% / 3.7% ;       ;
+; Maximum fan-out                                             ; 129                ;       ;
+; Highest non-global fan-out                                  ; 43                 ;       ;
+; Total fan-out                                               ; 1272               ;       ;
+; Average fan-out                                             ; 2.95               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                           ;
++-------------------------------------------------------------+------------------------+--------------------------------+
+; Statistic                                                   ; Top                    ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+------------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 90 / 56480 ( < 1 % )   ; 0 / 56480 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 90                     ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 98 / 56480 ( < 1 % )   ; 0 / 56480 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 63                     ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 20                     ; 0                              ;
+;         [c] ALMs used for registers                         ; 15                     ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                      ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 8 / 56480 ( < 1 % )    ; 0 / 56480 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 56480 ( 0 % )      ; 0 / 56480 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                      ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                      ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                      ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                      ; 0                              ;
+;                                                             ;                        ;                                ;
+; Difficulty packing design                                   ; Low                    ; Low                            ;
+;                                                             ;                        ;                                ;
+; Total LABs:  partially or completely used                   ; 14 / 5648 ( < 1 % )    ; 0 / 5648 ( 0 % )               ;
+;     -- Logic LABs                                           ; 14                     ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                      ; 0                              ;
+;                                                             ;                        ;                                ;
+; Combinational ALUT usage for logic                          ; 158                    ; 0                              ;
+;     -- 7 input functions                                    ; 0                      ; 0                              ;
+;     -- 6 input functions                                    ; 8                      ; 0                              ;
+;     -- 5 input functions                                    ; 19                     ; 0                              ;
+;     -- 4 input functions                                    ; 27                     ; 0                              ;
+;     -- <=3 input functions                                  ; 104                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 12                     ; 0                              ;
+; Memory ALUT usage                                           ; 0                      ; 0                              ;
+;     -- 64-address deep                                      ; 0                      ; 0                              ;
+;     -- 32-address deep                                      ; 0                      ; 0                              ;
+;                                                             ;                        ;                                ;
+; Dedicated logic registers                                   ; 0                      ; 0                              ;
+;     -- By type:                                             ;                        ;                                ;
+;         -- Primary logic registers                          ; 154 / 112960 ( < 1 % ) ; 0 / 112960 ( 0 % )             ;
+;         -- Secondary logic registers                        ; 15 / 112960 ( < 1 % )  ; 0 / 112960 ( 0 % )             ;
+;     -- By function:                                         ;                        ;                                ;
+;         -- Design implementation registers                  ; 154                    ; 0                              ;
+;         -- Routing optimization registers                   ; 15                     ; 0                              ;
+;                                                             ;                        ;                                ;
+;                                                             ;                        ;                                ;
+; Virtual pins                                                ; 0                      ; 0                              ;
+; I/O pins                                                    ; 41                     ; 0                              ;
+; I/O registers                                               ; 0                      ; 0                              ;
+; Total block memory bits                                     ; 73728                  ; 0                              ;
+; Total block memory implementation bits                      ; 92160                  ; 0                              ;
+; M10K block                                                  ; 9 / 686 ( 1 % )        ; 0 / 686 ( 0 % )                ;
+; Clock enable block                                          ; 1 / 122 ( < 1 % )      ; 0 / 122 ( 0 % )                ;
+;                                                             ;                        ;                                ;
+; Connections                                                 ;                        ;                                ;
+;     -- Input Connections                                    ; 0                      ; 0                              ;
+;     -- Registered Input Connections                         ; 0                      ; 0                              ;
+;     -- Output Connections                                   ; 0                      ; 0                              ;
+;     -- Registered Output Connections                        ; 0                      ; 0                              ;
+;                                                             ;                        ;                                ;
+; Internal Connections                                        ;                        ;                                ;
+;     -- Total Connections                                    ; 1425                   ; 0                              ;
+;     -- Registered Connections                               ; 731                    ; 0                              ;
+;                                                             ;                        ;                                ;
+; External Connections                                        ;                        ;                                ;
+;     -- Top                                                  ; 0                      ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                      ; 0                              ;
+;                                                             ;                        ;                                ;
+; Partition Interface                                         ;                        ;                                ;
+;     -- Input Ports                                          ; 12                     ; 0                              ;
+;     -- Output Ports                                         ; 29                     ; 0                              ;
+;     -- Bidir Ports                                          ; 0                      ; 0                              ;
+;                                                             ;                        ;                                ;
+; Registered Ports                                            ;                        ;                                ;
+;     -- Registered Input Ports                               ; 0                      ; 0                              ;
+;     -- Registered Output Ports                              ; 0                      ; 0                              ;
+;                                                             ;                        ;                                ;
+; Port Connectivity                                           ;                        ;                                ;
+;     -- Input Ports driven by GND                            ; 0                      ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                      ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                      ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                      ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                      ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                      ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                      ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                      ; 0                              ;
++-------------------------------------------------------------+------------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; ADC_SDO  ; M22   ; 5B       ; 89           ; 36           ; 37           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; CLOCK_50 ; M16   ; 5B       ; 89           ; 35           ; 60           ; 132                   ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[0]    ; C16   ; 7A       ; 72           ; 81           ; 51           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[1]    ; E19   ; 7A       ; 86           ; 81           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[2]    ; D9    ; 8A       ; 28           ; 81           ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[3]    ; AB13  ; 4A       ; 50           ; 0            ; 91           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[4]    ; M6    ; 3A       ; 8            ; 0            ; 17           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[5]    ; H8    ; 8A       ; 38           ; 81           ; 34           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[6]    ; T18   ; 5A       ; 89           ; 4            ; 43           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[7]    ; AB21  ; 4A       ; 58           ; 0            ; 74           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[8]    ; K9    ; 7A       ; 52           ; 81           ; 51           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
+; SW[9]    ; R7    ; 3A       ; 8            ; 0            ; 51           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 2.5 V        ; Off         ; --                        ; Fitter               ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; ADC_CS  ; N19   ; 5B       ; 89           ; 36           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; ADC_SCK ; L22   ; 5B       ; 89           ; 36           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; ADC_SDI ; U20   ; 4A       ; 72           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; DAC_CS  ; M18   ; 5B       ; 89           ; 36           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; DAC_LD  ; N20   ; 5B       ; 89           ; 35           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; DAC_SCK ; G20   ; 7A       ; 80           ; 81           ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; DAC_SDI ; M20   ; 5B       ; 89           ; 37           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX0[0] ; A17   ; 7A       ; 74           ; 81           ; 57           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX0[1] ; A20   ; 7A       ; 74           ; 81           ; 74           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX0[2] ; A18   ; 7A       ; 74           ; 81           ; 40           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX0[3] ; P18   ; 5A       ; 89           ; 9            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX0[4] ; E20   ; 7A       ; 76           ; 81           ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX0[5] ; A19   ; 7A       ; 74           ; 81           ; 91           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX0[6] ; R21   ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX1[0] ; L19   ; 5B       ; 89           ; 38           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX1[1] ; N16   ; 5B       ; 89           ; 35           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX1[2] ; K22   ; 5B       ; 89           ; 38           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX1[3] ; N21   ; 5B       ; 89           ; 35           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX1[4] ; L17   ; 5B       ; 89           ; 37           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX1[5] ; K17   ; 5B       ; 89           ; 37           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX1[6] ; L18   ; 5B       ; 89           ; 38           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX2[0] ; P17   ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX2[1] ; E22   ; 7A       ; 80           ; 81           ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX2[2] ; P16   ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX2[3] ; P19   ; 5A       ; 89           ; 9            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX2[4] ; F20   ; 7A       ; 76           ; 81           ; 51           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX2[5] ; F19   ; 7A       ; 76           ; 81           ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; HEX2[6] ; M21   ; 5B       ; 89           ; 37           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
+; PWM_OUT ; K21   ; 5B       ; 89           ; 38           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; 0                   ; Off                         ; Fitter               ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------+
+; I/O Bank Usage                                                              ;
++----------+-------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+-------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )      ; --            ; --           ; --            ;
+; B1L      ; 0 / 14 ( 0 % )    ; --            ; --           ; --            ;
+; B0L      ; 0 / 14 ( 0 % )    ; --            ; --           ; --            ;
+; 3A       ; 2 / 16 ( 13 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 3B       ; 0 / 32 ( 0 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 4A       ; 3 / 48 ( 6 % )    ; 2.5V          ; --           ; 2.5V          ;
+; 5A       ; 6 / 16 ( 38 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 5B       ; 16 / 16 ( 100 % ) ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 12 / 80 ( 15 % )  ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 2 / 32 ( 6 % )    ; 2.5V          ; --           ; 2.5V          ;
++----------+-------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                            ;
++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A1       ;            ;          ; RREF                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A2       ; 538        ; 9A       ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ;            ; --       ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; A4       ; 540        ; 9A       ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A5       ; 466        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A7       ; 475        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A8       ; 473        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 464        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 462        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A12      ; 444        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A13      ; 432        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 420        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 418        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A17      ; 403        ; 7A       ; HEX0[0]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; A18      ; 401        ; 7A       ; HEX0[2]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; A19      ; 404        ; 7A       ; HEX0[5]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; A20      ; 402        ; 7A       ; HEX0[1]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; A21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A22      ; 396        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA1      ; 39         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ; 38         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ; 47         ; 3A       ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AA6      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ; 105        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA8      ; 108        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA9      ; 115        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA10     ; 113        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA11     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 131        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 139        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 137        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 142        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA16     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA17     ; 153        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA18     ; 155        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 156        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 158        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA22     ; 163        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ; 49         ; 3A       ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB4      ; 51         ; 3A       ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB5      ; 102        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB6      ; 100        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB7      ; 107        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB8      ; 110        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB9      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ; 124        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB11     ; 126        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB12     ; 134        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB13     ; 132        ; 4A       ; SW[3]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AB14     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB15     ; 140        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; 4A       ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB17     ; 145        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ; 147        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB19     ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ; 148        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB21     ; 150        ; 4A       ; SW[7]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; AB22     ; 161        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B3       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B4       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B5       ; 468        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 470        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 472        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ;            ; 8A       ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ; 465        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B11      ; 452        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 442        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 430        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 427        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 406        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 384        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 382        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B20      ; 380        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 387        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 394        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C1       ; 19         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 18         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C5       ; 542        ; 9A       ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C6       ; 474        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C7       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C8       ; 480        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 467        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C11      ; 450        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C12      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C13      ; 443        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ;            ; 7A       ; VREFB7AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; C15      ; 425        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ; 408        ; 7A       ; SW[0]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; C17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C18      ; 395        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 393        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 378        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ; 385        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C22      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D3       ; 16         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 17         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D6       ; 476        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 478        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 479        ; 8A       ; SW[2]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; D10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D11      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D12      ; 449        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ; 441        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D14      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D15      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D16      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D17      ; 409        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 379        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D21      ; 376        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 392        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E1       ; 20         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E2       ; 21         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E5       ; 539        ; 9A       ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E6       ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E7       ; 484        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E9       ; 477        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ; 469        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E11      ;            ; 7A, 8A   ; VCCPD7A8A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E12      ; 451        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E14      ; 433        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ; 417        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E16      ; 411        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E18      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E19      ; 377        ; 7A       ; SW[1]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; E20      ; 398        ; 7A       ; HEX0[4]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; E21      ; 374        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ; 390        ; 7A       ; HEX2[1]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; F1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 541        ; 9A       ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F5       ; 14         ; B1L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; F6       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F7       ; 482        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F8       ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; F9       ; 471        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 455        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F12      ; 440        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F13      ; 435        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 428        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 419        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F17      ; 372        ; 7A       ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 399        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 397        ; 7A       ; HEX2[5]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; F20      ; 400        ; 7A       ; HEX2[4]                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; F21      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F22      ; 388        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G1       ; 23         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ; 22         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ; 15         ; B1L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G5       ; 537        ; 9A       ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 481        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G7       ;            ; 8A       ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G8       ; 460        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G10      ; 453        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 438        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 447        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 439        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 426        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 412        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 410        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 413        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G20      ; 389        ; 7A       ; DAC_SCK                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; G21      ; 375        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 386        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ; 536        ; 9A       ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ; 483        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H8       ; 458        ; 8A       ; SW[5]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; H9       ; 463        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H10      ; 436        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H11      ; 445        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H13      ; 437        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 429        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 423        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ; 421        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H17      ;            ; 7A       ; VCCIO7A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H18      ; 415        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H20      ; 391        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ; 373        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J1       ; 24         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ; 25         ; B1L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; J5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 535        ; 9A       ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 457        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ; 459        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J9       ; 461        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; J11      ; 434        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; J13      ; 431        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; J15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; J17      ; 422        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J18      ; 416        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J19      ; 414        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J21      ; 381        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J22      ; 383        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ; --       ; VCCL_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; K4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; K6       ; 534        ; 9A       ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 456        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K9       ; 448        ; 7A       ; SW[8]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; K10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; K14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; K16      ; 424        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K17      ; 284        ; 5B       ; HEX1[5]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; K18      ;            ; 5B       ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ; 407        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K20      ; 405        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K21      ; 289        ; 5B       ; PWM_OUT                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; K22      ; 291        ; 5B       ; HEX1[2]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; L1       ; 27         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ; 26         ; B1L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L6       ; 533        ; 9A       ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 454        ; 8A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; L8       ; 446        ; 7A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; L9       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ; 286        ; 5B       ; HEX1[4]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; L18      ; 290        ; 5B       ; HEX1[6]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; L19      ; 288        ; 5B       ; HEX1[0]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; L20      ;            ; 5B       ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; L21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L22      ; 283        ; 5B       ; ADC_SCK                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; M1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ; --       ; VCCH_GXBL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ; 42         ; 3A       ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ; 64         ; 3A       ; SW[4]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; M7       ; 66         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M8       ; 112        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M9       ; 114        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ; 278        ; 5B       ; CLOCK_50                        ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; M17      ;            ; 5B       ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M18      ; 282        ; 5B       ; DAC_CS                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; M19      ;            ; 5B       ; VCCIO5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M20      ; 285        ; 5B       ; DAC_SDI                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; M21      ; 287        ; 5B       ; HEX2[6]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; M22      ; 281        ; 5B       ; ADC_SDO                         ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; N1       ; 28         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ; 29         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ; --       ; VCCE_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N6       ; 58         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N8       ; 106        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N9       ; 130        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N10      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 276        ; 5B       ; HEX1[1]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; N17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ;            ; 5B       ; VCCPD5B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N19      ; 280        ; 5B       ; ADC_CS                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; N20      ; 277        ; 5B       ; DAC_LD                          ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; N21      ; 279        ; 5B       ; HEX1[3]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; N22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ; --       ; VCCL_GXBL                       ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ; 44         ; 3A       ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ; 56         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; P7       ; 67         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; P8       ; 104        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; P9       ; 128        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; P10      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ; 123        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; P13      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ; 168        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; P15      ;            ; --       ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ; 225        ; 5A       ; HEX2[2]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; P17      ; 227        ; 5A       ; HEX2[0]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; P18      ; 226        ; 5A       ; HEX0[3]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; P19      ; 224        ; 5A       ; HEX2[3]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; P20      ;            ; 5A       ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 5A       ; VCCPD5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 222        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ; 31         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ; 30         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ; 43         ; 3A       ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; R5       ; 54         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; R6       ; 52         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; R7       ; 65         ; 3A       ; SW[9]                           ; input  ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; R8       ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R9       ; 119        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; R10      ; 125        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; R11      ; 127        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; R12      ; 121        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; R13      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ; 170        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; R15      ; 219        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R16      ; 221        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R17      ; 223        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R18      ;            ; 5A       ; VCCIO5A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R19      ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; R20      ;            ; 5A       ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; R21      ; 220        ; 5A       ; HEX0[6]                         ; output ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; R22      ; 218        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ; --       ; VCCH_GXBL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T4       ; 45         ; 3A       ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; T5       ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T6       ;            ; 3A       ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T7       ; 60         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; T8       ; 62         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; T9       ; 109        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; T10      ; 117        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; T11      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T12      ; 136        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; T13      ; 138        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; T14      ; 152        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; T15      ; 217        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T16      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ; 215        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T18      ; 213        ; 5A       ; SW[6]                           ; input  ; 2.5 V        ;                     ; Row I/O      ; N               ; no       ; Off          ;
+; T19      ; 212        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T20      ; 214        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T21      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T22      ; 216        ; 5A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ; 32         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ; 33         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ; 41         ; B0L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; U5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U6       ; 61         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U7       ; 53         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U8       ; 55         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U9       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ; 111        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U11      ; 120        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U12      ; 122        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U13      ; 135        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U14      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U15      ; 154        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U16      ; 176        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U17      ; 178        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U18      ;            ; --       ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 179        ; 4A       ; ADC_SDI                         ; output ; 2.5 V        ;                     ; Column I/O   ; N               ; no       ; Off          ;
+; U21      ; 177        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; U22      ; 172        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ; 50         ; 3A       ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; V4       ; 40         ; B0L      ; GND                             ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V5       ; 46         ; 3A       ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ; 63         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V7       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --       ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; V9       ; 101        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V10      ; 103        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V11      ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V12      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ; 133        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V14      ; 144        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V15      ; 146        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V16      ; 160        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V18      ; 175        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ; 173        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V20      ; 157        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V21      ; 174        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V22      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W1       ; 35         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ; 34         ; B0L      ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ; 48         ; 3A       ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; W6       ;            ; 3A       ; VCCPD3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W7       ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W8       ; 57         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W9       ; 59         ; 3A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W10      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W12      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W14      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W15      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W16      ; 162        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ;            ; 3B, 4A   ; VCCPD3B4A                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W18      ;            ; --       ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W19      ; 159        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ;            ; 4A       ; VCCIO4A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; W21      ; 171        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W22      ; 166        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y1       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ; 36         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ; 37         ; B0L      ; GXB_NC                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ;          ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y7       ;            ; 3A       ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ; 3A       ; VCCIO3A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y9       ; 118        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y10      ; 116        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y11      ; 129        ; 3B       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y12      ;            ; 3B       ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; 3B       ; VCCIO3B                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y14      ; 141        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y15      ; 143        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y16      ; 149        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y17      ; 151        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y19      ; 167        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ; 165        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y21      ; 169        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y22      ; 164        ; 4A       ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
++----------+------------+----------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                  ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                    ; Entity Name     ; Library Name ;
++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex18                                       ; 89.5 (0.5)           ; 96.5 (0.5)                       ; 7.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 158 (1)             ; 169 (0)                   ; 0 (0)         ; 73728             ; 9     ; 0          ; 41   ; 0            ; |ex18                                                                                                                                                  ; ex18            ; work         ;
+;    |clktick_16:GEN_10K|                     ; 11.0 (11.0)          ; 12.0 (12.0)                      ; 1.0 (1.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 20 (20)             ; 24 (24)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|clktick_16:GEN_10K                                                                                                                               ; clktick_16      ; work         ;
+;    |hex_to_7seg:SEG0|                       ; 2.3 (2.3)            ; 3.0 (3.0)                        ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|hex_to_7seg:SEG0                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:SEG1|                       ; 2.4 (2.4)            ; 2.4 (2.4)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|hex_to_7seg:SEG1                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:SEG2|                       ; 0.8 (0.8)            ; 0.8 (0.8)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 3 (3)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|hex_to_7seg:SEG2                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |processor:ALLPASS|                      ; 30.1 (6.6)           ; 30.1 (6.6)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 60 (15)             ; 51 (10)                   ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS                                                                                                                                ; processor       ; work         ;
+;       |FIFO:fifo|                           ; 22.8 (0.0)           ; 23.2 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (0)              ; 40 (0)                    ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo                                                                                                                      ; FIFO            ; work         ;
+;          |scfifo:scfifo_component|          ; 22.8 (0.0)           ; 23.2 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (0)              ; 40 (0)                    ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component                                                                                              ; scfifo          ; work         ;
+;             |scfifo_4l81:auto_generated|    ; 22.8 (0.0)           ; 23.2 (0.0)                       ; 0.3 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (0)              ; 40 (0)                    ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated                                                                   ; scfifo_4l81     ; work         ;
+;                |a_dpfifo_br81:dpfifo|       ; 22.8 (0.0)           ; 23.2 (0.5)                       ; 0.3 (0.5)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 45 (1)              ; 40 (0)                    ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo                                              ; a_dpfifo_br81   ; work         ;
+;                   |a_fefifo_4be:fifo_state| ; 9.7 (3.2)            ; 9.7 (3.2)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 18 (5)              ; 14 (1)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state                      ; a_fefifo_4be    ; work         ;
+;                      |cntr_di7:count_usedw| ; 6.5 (6.5)            ; 6.5 (6.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7        ; work         ;
+;                   |altsyncram_44t1:FIFOram| ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 73728             ; 9     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram                      ; altsyncram_44t1 ; work         ;
+;                   |cntr_1ib:rd_ptr_count|   ; 6.5 (6.5)            ; 6.5 (6.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:rd_ptr_count                        ; cntr_1ib        ; work         ;
+;                   |cntr_1ib:wr_ptr|         ; 6.5 (6.5)            ; 6.5 (6.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 13 (13)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:wr_ptr                              ; cntr_1ib        ; work         ;
+;       |d_ff:d|                              ; 0.3 (0.3)            ; 0.3 (0.3)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 1 (1)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|d_ff:d                                                                                                                         ; d_ff            ; work         ;
+;    |pwm:PWM_DC|                             ; 10.7 (10.7)          ; 11.5 (11.5)                      ; 0.8 (0.8)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 19 (19)             ; 21 (21)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|pwm:PWM_DC                                                                                                                                       ; pwm             ; work         ;
+;    |spi2adc:SPI_ADC|                        ; 16.2 (16.2)          ; 18.9 (18.9)                      ; 2.7 (2.7)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 21 (21)             ; 45 (45)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|spi2adc:SPI_ADC                                                                                                                                  ; spi2adc         ; work         ;
+;    |spi2dac:SPI_DAC|                        ; 14.7 (14.7)          ; 17.3 (17.3)                      ; 2.7 (2.7)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 20 (20)             ; 28 (28)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex18|spi2dac:SPI_DAC                                                                                                                                  ; spi2dac         ; work         ;
++---------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; SW[0]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[1]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[2]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[3]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[4]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[5]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[6]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[7]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[8]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[9]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_LD   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; PWM_OUT  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; ADC_SDO  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++-------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                    ;
++-------------------------------------+-------------------+---------+
+; Source Pin / Fanout                 ; Pad To Core Index ; Setting ;
++-------------------------------------+-------------------+---------+
+; SW[0]                               ;                   ;         ;
+; SW[1]                               ;                   ;         ;
+; SW[2]                               ;                   ;         ;
+; SW[3]                               ;                   ;         ;
+; SW[4]                               ;                   ;         ;
+; SW[5]                               ;                   ;         ;
+; SW[6]                               ;                   ;         ;
+; SW[7]                               ;                   ;         ;
+; SW[8]                               ;                   ;         ;
+; SW[9]                               ;                   ;         ;
+; CLOCK_50                            ;                   ;         ;
+;      - spi2dac:SPI_DAC|clk_1MHz     ; 1                 ; 0       ;
+;      - spi2adc:SPI_ADC|clk_1MHz     ; 1                 ; 0       ;
+;      - clktick_16:GEN_10K|tick      ; 1                 ; 0       ;
+; ADC_SDO                             ;                   ;         ;
+;      - spi2adc:SPI_ADC|shift_reg[0] ; 1                 ; 0       ;
++-------------------------------------+-------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                              ;
++---------------------------------------------------------------------------------------------------------------------------------+----------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                            ; Location             ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------------+----------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                                                                        ; PIN_M16              ; 4       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                                        ; PIN_M16              ; 120     ; Clock                      ; yes    ; Global Clock         ; GCLK10           ; --                        ;
+; clktick_16:GEN_10K|Equal0~3                                                                                                     ; LABCELL_X73_Y35_N36  ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; clktick_16:GEN_10K|tick                                                                                                         ; FF_X73_Y35_N17       ; 21      ; Clock, Clock enable        ; no     ; --                   ; --               ; --                        ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|_~0 ; LABCELL_X73_Y35_N27  ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|valid_wreq                  ; LABCELL_X73_Y35_N51  ; 34      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; processor:ALLPASS|and_if                                                                                                        ; LABCELL_X74_Y35_N57  ; 23      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|adc_done                                                                                                        ; FF_X77_Y36_N37       ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|always3~0                                                                                                       ; LABCELL_X77_Y36_N39  ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|clk_1MHz                                                                                                        ; FF_X78_Y36_N44       ; 33      ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|Equal0~0                                                                                                        ; MLABCELL_X78_Y36_N57 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|always3~0                                                                                                       ; LABCELL_X79_Y36_N27  ; 9       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|clk_1MHz                                                                                                        ; FF_X78_Y36_N35       ; 25      ; Clock                      ; no     ; --                   ; --               ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------------+----------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_M16  ; 120     ; Global Clock         ; GCLK10           ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; Name                                                                                                                                   ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF  ; Location                                                                                                                                                ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs         ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 8192         ; 10           ; 8192         ; 10           ; yes                    ; no                      ; yes                    ; no                      ; 81920 ; 8192                        ; 9                           ; 8192                        ; 9                           ; 73728               ; 9           ; 0          ; None ; M10K_X76_Y34_N0, M10K_X76_Y39_N0, M10K_X69_Y36_N0, M10K_X69_Y35_N0, M10K_X76_Y33_N0, M10K_X76_Y37_N0, M10K_X76_Y38_N0, M10K_X76_Y36_N0, M10K_X76_Y35_N0 ; Don't care           ; New data        ; New data        ; Off      ; No                     ; No - Address Too Wide ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++--------------------------------------------------------+
+; Routing Usage Summary                                  ;
++------------------------------+-------------------------+
+; Routing Resource Type        ; Usage                   ;
++------------------------------+-------------------------+
+; Block interconnects          ; 507 / 374,484 ( < 1 % ) ;
+; C12 interconnects            ; 25 / 16,664 ( < 1 % )   ;
+; C2 interconnects             ; 186 / 155,012 ( < 1 % ) ;
+; C4 interconnects             ; 183 / 72,600 ( < 1 % )  ;
+; DQS bus muxes                ; 0 / 30 ( 0 % )          ;
+; DQS-18 I/O buses             ; 0 / 30 ( 0 % )          ;
+; DQS-9 I/O buses              ; 0 / 30 ( 0 % )          ;
+; Direct links                 ; 31 / 374,484 ( < 1 % )  ;
+; Global clocks                ; 1 / 16 ( 6 % )          ;
+; Horizontal periphery clocks  ; 0 / 72 ( 0 % )          ;
+; Local interconnects          ; 97 / 112,960 ( < 1 % )  ;
+; Quadrant clocks              ; 0 / 88 ( 0 % )          ;
+; R14 interconnects            ; 76 / 15,868 ( < 1 % )   ;
+; R14/C12 interconnect drivers ; 95 / 27,256 ( < 1 % )   ;
+; R3 interconnects             ; 307 / 169,296 ( < 1 % ) ;
+; R6 interconnects             ; 366 / 330,800 ( < 1 % ) ;
+; Spine clocks                 ; 2 / 480 ( < 1 % )       ;
+; Wire stub REs                ; 0 / 20,834 ( 0 % )      ;
++------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                 ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Inapplicable ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; No Location assignments found.                                           ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                            ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                              ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 0            ; 0            ; 0            ; 0            ; 0            ; 41        ; 0            ; 0            ; 41        ; 41        ; 0            ; 29           ; 0            ; 0            ; 0            ; 0            ; 29           ; 0            ; 0            ; 0            ; 0            ; 29           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 41           ; 41           ; 41           ; 41           ; 41           ; 0         ; 41           ; 41           ; 0         ; 0         ; 41           ; 12           ; 41           ; 41           ; 41           ; 41           ; 12           ; 41           ; 41           ; 41           ; 41           ; 12           ; 41           ; 41           ; 41           ; 41           ; 41           ; 41           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; SW[0]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SDI            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SCK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_CS             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_LD             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDI            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SCK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_CS             ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; PWM_OUT            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDO            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++----------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                    ;
++-----------------------------------+--------------------------+-------------------+
+; Source Clock(s)                   ; Destination Clock(s)     ; Delay Added in ns ;
++-----------------------------------+--------------------------+-------------------+
+; CLOCK_50                          ; CLOCK_50                 ; 154.5             ;
+; CLOCK_50,spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 55.6              ;
+; spi2adc:SPI_ADC|clk_1MHz          ; CLOCK_50                 ; 48.8              ;
+; spi2adc:SPI_ADC|clk_1MHz          ; spi2adc:SPI_ADC|clk_1MHz ; 43.8              ;
+; spi2dac:SPI_DAC|clk_1MHz          ; spi2dac:SPI_DAC|clk_1MHz ; 30.8              ;
+; CLOCK_50,clktick_16:GEN_10K|tick  ; CLOCK_50                 ; 26.3              ;
+; spi2dac:SPI_DAC|clk_1MHz          ; CLOCK_50                 ; 16.6              ;
++-----------------------------------+--------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                                   ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                                                                      ; Destination Register                                                                                                                                                 ; Delay Added in ns ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; spi2adc:SPI_ADC|data_from_adc[1]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 7.166             ;
+; spi2adc:SPI_ADC|data_from_adc[5]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 7.165             ;
+; spi2adc:SPI_ADC|data_from_adc[4]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 7.165             ;
+; spi2adc:SPI_ADC|data_from_adc[0]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 7.165             ;
+; spi2adc:SPI_ADC|data_from_adc[3]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 6.799             ;
+; spi2adc:SPI_ADC|data_from_adc[2]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 6.139             ;
+; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 5.736             ;
+; spi2dac:SPI_DAC|clk_1MHz                                                                                                                                             ; spi2dac:SPI_DAC|clk_1MHz                                                                                                                                             ; 5.729             ;
+; clktick_16:GEN_10K|tick                                                                                                                                              ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[12] ; 5.490             ;
+; spi2adc:SPI_ADC|data_from_adc[8]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 4.947             ;
+; spi2adc:SPI_ADC|data_from_adc[7]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 4.757             ;
+; spi2adc:SPI_ADC|data_from_adc[6]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 4.210             ;
+; spi2dac:SPI_DAC|dac_cs                                                                                                                                               ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL                                                                                                                               ; 4.197             ;
+; spi2adc:SPI_ADC|adc_cs                                                                                                                                               ; spi2adc:SPI_ADC|sr_state.WAIT_CSB_HIGH                                                                                                                               ; 3.871             ;
+; processor:ALLPASS|d_ff:d|out                                                                                                                                         ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~portb_address_reg0          ; 3.760             ;
+; spi2adc:SPI_ADC|data_from_adc[9]                                                                                                                                     ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 3.362             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[12] ; 2.761             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a9~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a8~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a7~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a6~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a5~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a4~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a3~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a2~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ram_block1a1~portb_address_reg0          ; processor:ALLPASS|data_out[9]                                                                                                                                        ; 2.655             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[12] ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 2.443             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[11] ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 2.443             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[10] ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 2.443             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[9]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 2.443             ;
+; spi2adc:SPI_ADC|shift_reg[7]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[8]                                                                                                                                         ; 1.270             ;
+; spi2adc:SPI_ADC|shift_reg[5]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[6]                                                                                                                                         ; 1.270             ;
+; spi2adc:SPI_ADC|state[4]                                                                                                                                             ; spi2adc:SPI_ADC|adc_din                                                                                                                                              ; 1.250             ;
+; spi2adc:SPI_ADC|state[1]                                                                                                                                             ; spi2adc:SPI_ADC|adc_din                                                                                                                                              ; 1.249             ;
+; spi2adc:SPI_ADC|shift_reg[8]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[9]                                                                                                                                         ; 1.246             ;
+; spi2adc:SPI_ADC|shift_reg[6]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[7]                                                                                                                                         ; 1.246             ;
+; spi2adc:SPI_ADC|state[0]                                                                                                                                             ; spi2adc:SPI_ADC|adc_din                                                                                                                                              ; 1.245             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[8]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[7]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[6]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[5]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[3]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[2]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[1]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[0]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw|counter_reg_bit[4]  ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_full                                   ; 1.225             ;
+; spi2adc:SPI_ADC|state[2]                                                                                                                                             ; spi2adc:SPI_ADC|shift_ena                                                                                                                                            ; 1.209             ;
+; spi2dac:SPI_DAC|state[4]                                                                                                                                             ; spi2dac:SPI_DAC|dac_ld                                                                                                                                               ; 1.167             ;
+; spi2adc:SPI_ADC|state[3]                                                                                                                                             ; spi2adc:SPI_ADC|shift_ena                                                                                                                                            ; 1.143             ;
+; spi2dac:SPI_DAC|state[2]                                                                                                                                             ; spi2dac:SPI_DAC|dac_ld                                                                                                                                               ; 1.118             ;
+; spi2dac:SPI_DAC|state[0]                                                                                                                                             ; spi2dac:SPI_DAC|dac_ld                                                                                                                                               ; 1.109             ;
+; spi2dac:SPI_DAC|shift_reg[14]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[15]                                                                                                                                        ; 1.104             ;
+; spi2dac:SPI_DAC|shift_reg[11]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[12]                                                                                                                                        ; 1.104             ;
+; spi2dac:SPI_DAC|shift_reg[13]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[14]                                                                                                                                        ; 1.102             ;
+; spi2dac:SPI_DAC|state[1]                                                                                                                                             ; spi2dac:SPI_DAC|dac_ld                                                                                                                                               ; 1.095             ;
+; spi2dac:SPI_DAC|shift_reg[12]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[13]                                                                                                                                        ; 1.085             ;
+; spi2dac:SPI_DAC|state[3]                                                                                                                                             ; spi2dac:SPI_DAC|dac_ld                                                                                                                                               ; 1.049             ;
+; spi2adc:SPI_ADC|shift_reg[4]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[5]                                                                                                                                         ; 1.048             ;
+; spi2adc:SPI_ADC|shift_reg[2]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[3]                                                                                                                                         ; 1.048             ;
+; spi2adc:SPI_ADC|shift_reg[0]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[1]                                                                                                                                         ; 1.048             ;
+; spi2adc:SPI_ADC|shift_reg[3]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[4]                                                                                                                                         ; 1.034             ;
+; spi2adc:SPI_ADC|shift_reg[1]                                                                                                                                         ; spi2adc:SPI_ADC|shift_reg[2]                                                                                                                                         ; 1.034             ;
+; clktick_16:GEN_10K|count[3]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 1.026             ;
+; clktick_16:GEN_10K|count[6]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 1.023             ;
+; clktick_16:GEN_10K|count[2]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 1.015             ;
+; clktick_16:GEN_10K|count[5]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 1.011             ;
+; clktick_16:GEN_10K|count[13]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.915             ;
+; clktick_16:GEN_10K|count[4]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.907             ;
+; clktick_16:GEN_10K|count[8]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.900             ;
+; clktick_16:GEN_10K|count[15]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.893             ;
+; clktick_16:GEN_10K|count[10]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.880             ;
+; clktick_16:GEN_10K|count[12]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.838             ;
+; clktick_16:GEN_10K|count[7]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.817             ;
+; clktick_16:GEN_10K|count[1]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.817             ;
+; clktick_16:GEN_10K|count[0]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.817             ;
+; spi2adc:SPI_ADC|ctr[2]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.791             ;
+; spi2adc:SPI_ADC|ctr[4]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.789             ;
+; spi2adc:SPI_ADC|ctr[3]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.786             ;
+; clktick_16:GEN_10K|count[11]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.786             ;
+; clktick_16:GEN_10K|count[14]                                                                                                                                         ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.774             ;
+; spi2adc:SPI_ADC|ctr[0]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.748             ;
+; clktick_16:GEN_10K|count[9]                                                                                                                                          ; clktick_16:GEN_10K|tick                                                                                                                                              ; 0.719             ;
+; spi2adc:SPI_ADC|ctr[1]                                                                                                                                               ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                                             ; 0.684             ;
+; spi2dac:SPI_DAC|shift_reg[2]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[3]                                                                                                                                         ; 0.609             ;
+; spi2dac:SPI_DAC|shift_reg[4]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[5]                                                                                                                                         ; 0.609             ;
+; spi2dac:SPI_DAC|shift_reg[6]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[7]                                                                                                                                         ; 0.609             ;
+; spi2dac:SPI_DAC|shift_reg[8]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[9]                                                                                                                                         ; 0.609             ;
+; spi2dac:SPI_DAC|shift_reg[9]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[10]                                                                                                                                        ; 0.609             ;
+; spi2dac:SPI_DAC|shift_reg[3]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[4]                                                                                                                                         ; 0.604             ;
+; spi2dac:SPI_DAC|shift_reg[5]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[6]                                                                                                                                         ; 0.604             ;
+; spi2dac:SPI_DAC|shift_reg[7]                                                                                                                                         ; spi2dac:SPI_DAC|shift_reg[8]                                                                                                                                         ; 0.604             ;
+; spi2dac:SPI_DAC|shift_reg[10]                                                                                                                                        ; spi2dac:SPI_DAC|shift_reg[11]                                                                                                                                        ; 0.604             ;
+; pwm:PWM_DC|count[0]                                                                                                                                                  ; pwm:PWM_DC|count[9]                                                                                                                                                  ; 0.572             ;
+; spi2adc:SPI_ADC|adc_done                                                                                                                                             ; spi2adc:SPI_ADC|data_from_adc[0]                                                                                                                                     ; 0.490             ;
+; pwm:PWM_DC|d[3]                                                                                                                                                      ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.464             ;
+; pwm:PWM_DC|d[2]                                                                                                                                                      ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.464             ;
+; pwm:PWM_DC|d[1]                                                                                                                                                      ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.464             ;
+; pwm:PWM_DC|d[0]                                                                                                                                                      ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.464             ;
+; pwm:PWM_DC|count[3]                                                                                                                                                  ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.464             ;
+; pwm:PWM_DC|count[2]                                                                                                                                                  ; pwm:PWM_DC|pwm_out                                                                                                                                                   ; 0.464             ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CGXFC7C7F23C8 for design "ex18"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 41 pins of 41 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 118 fanout uses global clock CLKCTRL_G10
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex18.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:09
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:04
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X67_Y35 to location X77_Y45
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:05
+Info (11888): Total time spent on timing analysis during the Fitter is 0.90 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05
+Info (144001): Generated suppressed messages file C:/New folder/ex18/output_files/ex18.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 2906 megabytes
+    Info: Processing ended: Fri Dec 02 11:26:59 2016
+    Info: Elapsed time: 00:00:40
+    Info: Total CPU time (on all processors): 00:01:14
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/New folder/ex18/output_files/ex18.fit.smsg.
+
+
diff --git a/part_4/ex18/output_files/ex18.fit.smsg b/part_4/ex18/output_files/ex18.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_4/ex18/output_files/ex18.fit.summary b/part_4/ex18/output_files/ex18.fit.summary
new file mode 100755
index 0000000..bd92131
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Fri Dec 02 11:26:58 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex18
+Top-level Entity Name : ex18
+Family : Cyclone V
+Device : 5CGXFC7C7F23C8
+Timing Models : Final
+Logic utilization (in ALMs) : 90 / 56,480 ( < 1 % )
+Total registers : 169
+Total pins : 41 / 268 ( 15 % )
+Total virtual pins : 0
+Total block memory bits : 73,728 / 7,024,640 ( 1 % )
+Total RAM Blocks : 9 / 686 ( 1 % )
+Total DSP Blocks : 0 / 156 ( 0 % )
+Total HSSI RX PCSs : 0 / 6 ( 0 % )
+Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % )
+Total HSSI TX PCSs : 0 / 6 ( 0 % )
+Total HSSI PMA TX Serializers : 0 / 6 ( 0 % )
+Total PLLs : 0 / 13 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_4/ex18/output_files/ex18.flow.rpt b/part_4/ex18/output_files/ex18.flow.rpt
new file mode 100755
index 0000000..8d78e98
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.flow.rpt
@@ -0,0 +1,129 @@
+Flow report for ex18
+Fri Dec 02 11:27:15 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Fri Dec 02 11:27:07 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex18                                            ;
+; Top-level Entity Name           ; ex18                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CGXFC7C7F23C8                                  ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 90 / 56,480 ( < 1 % )                           ;
+; Total registers                 ; 169                                             ;
+; Total pins                      ; 41 / 268 ( 15 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 73,728 / 7,024,640 ( 1 % )                      ;
+; Total DSP Blocks                ; 0 / 156 ( 0 % )                                 ;
+; Total HSSI RX PCSs              ; 0 / 6 ( 0 % )                                   ;
+; Total HSSI PMA RX Deserializers ; 0 / 6 ( 0 % )                                   ;
+; Total HSSI TX PCSs              ; 0 / 6 ( 0 % )                                   ;
+; Total HSSI PMA TX Serializers   ; 0 / 6 ( 0 % )                                   ;
+; Total PLLs                      ; 0 / 13 ( 0 % )                                  ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 12/02/2016 11:26:08 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex18                ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564297095.148067796808056       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; MISC_FILE                           ; verilog_files/FIFO_bb.v               ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:10     ; 1.0                     ; 911 MB              ; 00:00:22                           ;
+; Fitter                    ; 00:00:39     ; 1.0                     ; 2906 MB             ; 00:01:13                           ;
+; Assembler                 ; 00:00:07     ; 1.0                     ; 883 MB              ; 00:00:07                           ;
+; TimeQuest Timing Analyzer ; 00:00:07     ; 1.1                     ; 1312 MB             ; 00:00:08                           ;
+; Total                     ; 00:01:03     ; --                      ; --                  ; 00:01:50                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-024     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex18 -c ex18
+quartus_fit --read_settings_files=off --write_settings_files=off ex18 -c ex18
+quartus_asm --read_settings_files=off --write_settings_files=off ex18 -c ex18
+quartus_sta ex18 -c ex18
+
+
+
diff --git a/part_4/ex18/output_files/ex18.jdi b/part_4/ex18/output_files/ex18.jdi
new file mode 100755
index 0000000..ab6d6e4
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="bc86cef921a8ce220b91"/>
+  </project>
+  <file_info>
+    <file device="5CGXFC7C7F23C8" path="ex18.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_4/ex18/output_files/ex18.map.rpt b/part_4/ex18/output_files/ex18.map.rpt
new file mode 100755
index 0000000..59ed584
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.map.rpt
@@ -0,0 +1,668 @@
+Analysis & Synthesis report for ex18
+Fri Dec 02 11:26:18 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |ex18|spi2adc:SPI_ADC|sr_state
+ 11. State Machine - |ex18|spi2dac:SPI_DAC|sr_state
+ 12. Registers Removed During Synthesis
+ 13. Removed Registers Triggering Further Register Optimizations
+ 14. General Register Statistics
+ 15. Inverted Register Statistics
+ 16. Source assignments for processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram
+ 17. Parameter Settings for User Entity Instance: clktick_16:GEN_10K
+ 18. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC
+ 19. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC
+ 20. Parameter Settings for User Entity Instance: processor:ALLPASS
+ 21. Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component
+ 22. scfifo Parameter Settings by Entity Instance
+ 23. Port Connectivity Checks: "hex_to_7seg:SEG2"
+ 24. Port Connectivity Checks: "spi2adc:SPI_ADC"
+ 25. Port Connectivity Checks: "clktick_16:GEN_10K"
+ 26. Post-Synthesis Netlist Statistics for Top Partition
+ 27. Elapsed Time Per Partition
+ 28. Analysis & Synthesis Messages
+ 29. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Fri Dec 02 11:26:18 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex18                                            ;
+; Top-level Entity Name           ; ex18                                            ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 154                                             ;
+; Total pins                      ; 41                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 73,728                                          ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CGXFC7C7F23C8     ;                    ;
+; Top-level entity name                                                           ; ex18               ; ex18               ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                      ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                  ; Library ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------+---------+
+; verilog_files/mult_echo_synth.v  ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/verilog_files/mult_echo_synth.v            ;         ;
+; verilog_files/spi2dac.v          ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/verilog_files/spi2dac.v                    ;         ;
+; verilog_files/spi2adc.v          ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/verilog_files/spi2adc.v                    ;         ;
+; verilog_files/pwm.v              ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/verilog_files/pwm.v                        ;         ;
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/verilog_files/hex_to_7seg.v                ;         ;
+; verilog_files/FIFO.v             ; yes             ; User Wizard-Generated File   ; C:/New folder/ex18/verilog_files/FIFO.v                       ;         ;
+; verilog_files/div_by_2.v         ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/verilog_files/div_by_2.v                   ;         ;
+; verilog_files/d_ff.v             ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/verilog_files/d_ff.v                       ;         ;
+; verilog_files/clktick_16.v       ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/verilog_files/clktick_16.v                 ;         ;
+; ex18.v                           ; yes             ; User Verilog HDL File        ; C:/New folder/ex18/ex18.v                                     ;         ;
+; scfifo.tdf                       ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/scfifo.tdf     ;         ;
+; a_regfifo.inc                    ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_regfifo.inc  ;         ;
+; a_dpfifo.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_dpfifo.inc   ;         ;
+; a_i2fifo.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_i2fifo.inc   ;         ;
+; a_fffifo.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_fffifo.inc   ;         ;
+; a_f2fifo.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_f2fifo.inc   ;         ;
+; aglobal160.inc                   ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc ;         ;
+; db/scfifo_4l81.tdf               ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex18/db/scfifo_4l81.tdf                         ;         ;
+; db/a_dpfifo_br81.tdf             ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex18/db/a_dpfifo_br81.tdf                       ;         ;
+; db/a_fefifo_4be.tdf              ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex18/db/a_fefifo_4be.tdf                        ;         ;
+; db/cntr_di7.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex18/db/cntr_di7.tdf                            ;         ;
+; db/altsyncram_44t1.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex18/db/altsyncram_44t1.tdf                     ;         ;
+; db/cntr_1ib.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex18/db/cntr_1ib.tdf                            ;         ;
++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimate of Logic utilization (ALMs needed) ; 91             ;
+;                                             ;                ;
+; Combinational ALUT usage for logic          ; 157            ;
+;     -- 7 input functions                    ; 0              ;
+;     -- 6 input functions                    ; 8              ;
+;     -- 5 input functions                    ; 19             ;
+;     -- 4 input functions                    ; 27             ;
+;     -- <=3 input functions                  ; 103            ;
+;                                             ;                ;
+; Dedicated logic registers                   ; 154            ;
+;                                             ;                ;
+; I/O pins                                    ; 41             ;
+; Total MLAB memory bits                      ; 0              ;
+; Total block memory bits                     ; 73728          ;
+;                                             ;                ;
+; Total DSP Blocks                            ; 0              ;
+;                                             ;                ;
+; Maximum fan-out node                        ; CLOCK_50~input ;
+; Maximum fan-out                             ; 112            ;
+; Total fan-out                               ; 1223           ;
+; Average fan-out                             ; 3.04           ;
++---------------------------------------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                             ;
++---------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                  ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                    ; Entity Name     ; Library Name ;
++---------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex18                                       ; 157 (0)           ; 154 (0)      ; 73728             ; 0          ; 41   ; 0            ; |ex18                                                                                                                                                  ; ex18            ; work         ;
+;    |clktick_16:GEN_10K|                     ; 20 (20)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex18|clktick_16:GEN_10K                                                                                                                               ; clktick_16      ; work         ;
+;    |hex_to_7seg:SEG0|                       ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex18|hex_to_7seg:SEG0                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:SEG1|                       ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex18|hex_to_7seg:SEG1                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |hex_to_7seg:SEG2|                       ; 3 (3)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex18|hex_to_7seg:SEG2                                                                                                                                 ; hex_to_7seg     ; work         ;
+;    |processor:ALLPASS|                      ; 60 (15)           ; 51 (10)      ; 73728             ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS                                                                                                                                ; processor       ; work         ;
+;       |FIFO:fifo|                           ; 45 (0)            ; 40 (0)       ; 73728             ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo                                                                                                                      ; FIFO            ; work         ;
+;          |scfifo:scfifo_component|          ; 45 (0)            ; 40 (0)       ; 73728             ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component                                                                                              ; scfifo          ; work         ;
+;             |scfifo_4l81:auto_generated|    ; 45 (0)            ; 40 (0)       ; 73728             ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated                                                                   ; scfifo_4l81     ; work         ;
+;                |a_dpfifo_br81:dpfifo|       ; 45 (1)            ; 40 (0)       ; 73728             ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo                                              ; a_dpfifo_br81   ; work         ;
+;                   |a_fefifo_4be:fifo_state| ; 18 (5)            ; 14 (1)       ; 0                 ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state                      ; a_fefifo_4be    ; work         ;
+;                      |cntr_di7:count_usedw| ; 13 (13)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw ; cntr_di7        ; work         ;
+;                   |altsyncram_44t1:FIFOram| ; 0 (0)             ; 0 (0)        ; 73728             ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram                      ; altsyncram_44t1 ; work         ;
+;                   |cntr_1ib:rd_ptr_count|   ; 13 (13)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:rd_ptr_count                        ; cntr_1ib        ; work         ;
+;                   |cntr_1ib:wr_ptr|         ; 13 (13)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:wr_ptr                              ; cntr_1ib        ; work         ;
+;       |d_ff:d|                              ; 0 (0)             ; 1 (1)        ; 0                 ; 0          ; 0    ; 0            ; |ex18|processor:ALLPASS|d_ff:d                                                                                                                         ; d_ff            ; work         ;
+;    |pwm:PWM_DC|                             ; 19 (19)           ; 21 (21)      ; 0                 ; 0          ; 0    ; 0            ; |ex18|pwm:PWM_DC                                                                                                                                       ; pwm             ; work         ;
+;    |spi2adc:SPI_ADC|                        ; 21 (21)           ; 39 (39)      ; 0                 ; 0          ; 0    ; 0            ; |ex18|spi2adc:SPI_ADC                                                                                                                                  ; spi2adc         ; work         ;
+;    |spi2dac:SPI_DAC|                        ; 20 (20)           ; 26 (26)      ; 0                 ; 0          ; 0    ; 0            ; |ex18|spi2dac:SPI_DAC                                                                                                                                  ; spi2dac         ; work         ;
++---------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                            ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; Name                                                                                                                                   ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8192         ; 10           ; 8192         ; 10           ; 81920 ; None ;
++----------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                    ;
++--------+--------------+---------+--------------+--------------+-----------------------------------+----------------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                   ; IP Include File      ;
++--------+--------------+---------+--------------+--------------+-----------------------------------+----------------------+
+; Altera ; FIFO         ; 16.0    ; N/A          ; N/A          ; |ex18|processor:ALLPASS|FIFO:fifo ; verilog_files/FIFO.v ;
++--------+--------------+---------+--------------+--------------+-----------------------------------+----------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex18|spi2adc:SPI_ADC|sr_state                                           ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex18|spi2dac:SPI_DAC|sr_state                                           ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                               ;
++-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+; Register name                                                                                                                           ; Reason for Removal                     ;
++-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+; spi2dac:SPI_DAC|shift_reg[0,1]                                                                                                          ; Stuck at GND due to stuck port data_in ;
+; spi2dac:SPI_DAC|ctr[4]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[4]     ;
+; spi2dac:SPI_DAC|ctr[3]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[3]     ;
+; spi2dac:SPI_DAC|ctr[2]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[2]     ;
+; spi2dac:SPI_DAC|ctr[1]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[1]     ;
+; spi2dac:SPI_DAC|ctr[0]                                                                                                                  ; Merged with spi2adc:SPI_ADC|ctr[0]     ;
+; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|b_non_empty ; Stuck at VCC due to stuck port data_in ;
+; Total Number of Removed Registers = 8                                                                                                   ;                                        ;
++-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                       ;
++------------------------------+---------------------------+----------------------------------------+
+; Register name                ; Reason for Removal        ; Registers Removed due to This Register ;
++------------------------------+---------------------------+----------------------------------------+
+; spi2dac:SPI_DAC|shift_reg[0] ; Stuck at GND              ; spi2dac:SPI_DAC|shift_reg[1]           ;
+;                              ; due to stuck port data_in ;                                        ;
++------------------------------+---------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 154   ;
+; Number of registers using Synchronous Clear  ; 9     ;
+; Number of registers using Synchronous Load   ; 9     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 71    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; spi2dac:SPI_DAC|dac_cs                 ; 12      ;
+; spi2adc:SPI_ADC|adc_cs                 ; 7       ;
+; Total number of inverted registers = 2 ;         ;
++----------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                   ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                    ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ;
++----------------+-------+----------------------------------------+
+; Parameter Name ; Value ; Type                                   ;
++----------------+-------+----------------------------------------+
+; N_BIT          ; 16    ; Signed Integer                         ;
++----------------+-------+----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; BUF            ; 1     ; Unsigned Binary                     ;
+; GA_N           ; 1     ; Unsigned Binary                     ;
+; SHDN_N         ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; SGL            ; 1     ; Unsigned Binary                     ;
+; MSBF           ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:ALLPASS ;
++----------------+------------+----------------------------------+
+; Parameter Name ; Value      ; Type                             ;
++----------------+------------+----------------------------------+
+; ADC_OFFSET     ; 0110000001 ; Unsigned Binary                  ;
+; DAC_OFFSET     ; 1000000000 ; Unsigned Binary                  ;
++----------------+------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component ;
++-------------------------+-------------+----------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                     ;
++-------------------------+-------------+----------------------------------------------------------+
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                               ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                             ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                             ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                           ;
+; lpm_width               ; 10          ; Signed Integer                                           ;
+; LPM_NUMWORDS            ; 8192        ; Signed Integer                                           ;
+; LPM_WIDTHU              ; 13          ; Signed Integer                                           ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                  ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                  ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                  ;
+; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                  ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                  ;
+; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                  ;
+; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                  ;
+; ENABLE_ECC              ; FALSE       ; Untyped                                                  ;
+; USE_EAB                 ; ON          ; Untyped                                                  ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                  ;
+; DEVICE_FAMILY           ; Cyclone V   ; Untyped                                                  ;
+; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                  ;
+; CBXI_PARAMETER          ; scfifo_4l81 ; Untyped                                                  ;
++-------------------------+-------------+----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------+
+; scfifo Parameter Settings by Entity Instance                                     ;
++----------------------------+-----------------------------------------------------+
+; Name                       ; Value                                               ;
++----------------------------+-----------------------------------------------------+
+; Number of entity instances ; 1                                                   ;
+; Entity Instance            ; processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component ;
+;     -- FIFO Type           ; Single Clock                                        ;
+;     -- lpm_width           ; 10                                                  ;
+;     -- LPM_NUMWORDS        ; 8192                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                 ;
+;     -- USE_EAB             ; ON                                                  ;
++----------------------------+-----------------------------------------------------+
+
+
++----------------------------------------------+
+; Port Connectivity Checks: "hex_to_7seg:SEG2" ;
++----------+-------+----------+----------------+
+; Port     ; Type  ; Severity ; Details        ;
++----------+-------+----------+----------------+
+; in[3..2] ; Input ; Info     ; Stuck at GND   ;
++----------+-------+----------+----------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "spi2adc:SPI_ADC"                                                                          ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port       ; Type   ; Severity ; Details                                                                             ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+; channel    ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; data_valid ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------+
+; Port Connectivity Checks: "clktick_16:GEN_10K" ;
++-----------+-------+----------+-----------------+
+; Port      ; Type  ; Severity ; Details         ;
++-----------+-------+----------+-----------------+
+; enable    ; Input ; Info     ; Stuck at VCC    ;
+; N[9..7]   ; Input ; Info     ; Stuck at VCC    ;
+; N[2..0]   ; Input ; Info     ; Stuck at VCC    ;
+; N[15..13] ; Input ; Info     ; Stuck at GND    ;
+; N[11..10] ; Input ; Info     ; Stuck at GND    ;
+; N[6..3]   ; Input ; Info     ; Stuck at GND    ;
+; N[12]     ; Input ; Info     ; Stuck at VCC    ;
++-----------+-------+----------+-----------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 154                         ;
+;     ENA               ; 71                          ;
+;     SCLR              ; 9                           ;
+;     SLD               ; 9                           ;
+;     plain             ; 65                          ;
+; arriav_lcell_comb     ; 165                         ;
+;     arith             ; 77                          ;
+;         1 data inputs ; 54                          ;
+;         2 data inputs ; 23                          ;
+;     normal            ; 88                          ;
+;         0 data inputs ; 1                           ;
+;         1 data inputs ; 11                          ;
+;         2 data inputs ; 13                          ;
+;         3 data inputs ; 9                           ;
+;         4 data inputs ; 27                          ;
+;         5 data inputs ; 19                          ;
+;         6 data inputs ; 8                           ;
+; boundary_port         ; 41                          ;
+; stratixv_ram_block    ; 9                           ;
+;                       ;                             ;
+; Max LUT depth         ; 3.90                        ;
+; Average LUT depth     ; 1.78                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 11:26:08 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex18 -c ex18
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/mult_echo_synth.v
+    Info (12023): Found entity 1: processor File: C:/New folder/ex18/verilog_files/mult_echo_synth.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v
+    Info (12023): Found entity 1: spi2dac File: C:/New folder/ex18/verilog_files/spi2dac.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v
+    Info (12023): Found entity 1: spi2adc File: C:/New folder/ex18/verilog_files/spi2adc.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/pwm.v
+    Info (12023): Found entity 1: pwm File: C:/New folder/ex18/verilog_files/pwm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v
+    Info (12023): Found entity 1: pulse_gen File: C:/New folder/ex18/verilog_files/pulse_gen.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v
+    Info (12023): Found entity 1: multiply_k File: C:/New folder/ex18/verilog_files/multiply_k.v Line: 39
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex18/verilog_files/hex_to_7seg.v Line: 10
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/fifo.v
+    Info (12023): Found entity 1: FIFO File: C:/New folder/ex18/verilog_files/FIFO.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v
+    Info (12023): Found entity 1: div_by_2 File: C:/New folder/ex18/verilog_files/div_by_2.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v
+    Info (12023): Found entity 1: delay_ram File: C:/New folder/ex18/verilog_files/delay_ram.v Line: 39
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v
+    Info (12023): Found entity 1: d_ff File: C:/New folder/ex18/verilog_files/d_ff.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v
+    Info (12023): Found entity 1: clktick_16 File: C:/New folder/ex18/verilog_files/clktick_16.v Line: 6
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex18/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file ex18.v
+    Info (12023): Found entity 1: ex18 File: C:/New folder/ex18/ex18.v Line: 1
+Critical Warning (10846): Verilog HDL Instantiation warning at mult_echo_synth.v(25): instance has no name File: C:/New folder/ex18/verilog_files/mult_echo_synth.v Line: 25
+Info (12127): Elaborating entity "ex18" for the top level hierarchy
+Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: C:/New folder/ex18/ex18.v Line: 24
+Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: C:/New folder/ex18/ex18.v Line: 26
+Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: C:/New folder/ex18/ex18.v Line: 27
+Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: C:/New folder/ex18/ex18.v Line: 38
+Info (12128): Elaborating entity "processor" for hierarchy "processor:ALLPASS" File: C:/New folder/ex18/ex18.v Line: 40
+Info (12128): Elaborating entity "FIFO" for hierarchy "processor:ALLPASS|FIFO:fifo" File: C:/New folder/ex18/verilog_files/mult_echo_synth.v Line: 19
+Info (12128): Elaborating entity "scfifo" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component" File: C:/New folder/ex18/verilog_files/FIFO.v Line: 73
+Info (12130): Elaborated megafunction instantiation "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component" File: C:/New folder/ex18/verilog_files/FIFO.v Line: 73
+Info (12133): Instantiated megafunction "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component" with the following parameter: File: C:/New folder/ex18/verilog_files/FIFO.v Line: 73
+    Info (12134): Parameter "add_ram_output_register" = "OFF"
+    Info (12134): Parameter "intended_device_family" = "Cyclone V"
+    Info (12134): Parameter "lpm_numwords" = "8192"
+    Info (12134): Parameter "lpm_showahead" = "OFF"
+    Info (12134): Parameter "lpm_type" = "scfifo"
+    Info (12134): Parameter "lpm_width" = "10"
+    Info (12134): Parameter "lpm_widthu" = "13"
+    Info (12134): Parameter "overflow_checking" = "ON"
+    Info (12134): Parameter "underflow_checking" = "ON"
+    Info (12134): Parameter "use_eab" = "ON"
+Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_4l81.tdf
+    Info (12023): Found entity 1: scfifo_4l81 File: C:/New folder/ex18/db/scfifo_4l81.tdf Line: 25
+Info (12128): Elaborating entity "scfifo_4l81" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/scfifo.tdf Line: 300
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_br81.tdf
+    Info (12023): Found entity 1: a_dpfifo_br81 File: C:/New folder/ex18/db/a_dpfifo_br81.tdf Line: 29
+Info (12128): Elaborating entity "a_dpfifo_br81" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo" File: C:/New folder/ex18/db/scfifo_4l81.tdf Line: 35
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_4be.tdf
+    Info (12023): Found entity 1: a_fefifo_4be File: C:/New folder/ex18/db/a_fefifo_4be.tdf Line: 25
+Info (12128): Elaborating entity "a_fefifo_4be" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state" File: C:/New folder/ex18/db/a_dpfifo_br81.tdf Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_di7.tdf
+    Info (12023): Found entity 1: cntr_di7 File: C:/New folder/ex18/db/cntr_di7.tdf Line: 26
+Info (12128): Elaborating entity "cntr_di7" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|a_fefifo_4be:fifo_state|cntr_di7:count_usedw" File: C:/New folder/ex18/db/a_fefifo_4be.tdf Line: 38
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_44t1.tdf
+    Info (12023): Found entity 1: altsyncram_44t1 File: C:/New folder/ex18/db/altsyncram_44t1.tdf Line: 28
+Info (12128): Elaborating entity "altsyncram_44t1" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram" File: C:/New folder/ex18/db/a_dpfifo_br81.tdf Line: 41
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ib.tdf
+    Info (12023): Found entity 1: cntr_1ib File: C:/New folder/ex18/db/cntr_1ib.tdf Line: 26
+Info (12128): Elaborating entity "cntr_1ib" for hierarchy "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|cntr_1ib:rd_ptr_count" File: C:/New folder/ex18/db/a_dpfifo_br81.tdf Line: 42
+Info (12128): Elaborating entity "d_ff" for hierarchy "processor:ALLPASS|d_ff:d" File: C:/New folder/ex18/verilog_files/mult_echo_synth.v Line: 21
+Info (12128): Elaborating entity "div_by_2" for hierarchy "processor:ALLPASS|div_by_2:comb_5" File: C:/New folder/ex18/verilog_files/mult_echo_synth.v Line: 25
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "hex_to_7seg:SEG0" File: C:/New folder/ex18/ex18.v Line: 42
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "processor:ALLPASS|FIFO:fifo|scfifo:scfifo_component|scfifo_4l81:auto_generated|a_dpfifo_br81:dpfifo|altsyncram_44t1:FIFOram|q_b[0]" File: C:/New folder/ex18/db/altsyncram_44t1.tdf Line: 40
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX2[1]" is stuck at GND File: C:/New folder/ex18/ex18.v Line: 7
+Info (286030): Timing-Driven Synthesis is running
+Info (144001): Generated suppressed messages file C:/New folder/ex18/output_files/ex18.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 10 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "SW[0]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[1]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[2]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[3]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[4]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[5]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[6]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[7]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[8]" File: C:/New folder/ex18/ex18.v Line: 6
+    Warning (15610): No output dependent on input pin "SW[9]" File: C:/New folder/ex18/ex18.v Line: 6
+Info (21057): Implemented 256 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 12 input pins
+    Info (21059): Implemented 29 output pins
+    Info (21061): Implemented 206 logic cells
+    Info (21064): Implemented 9 RAM segments
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings
+    Info: Peak virtual memory: 911 megabytes
+    Info: Processing ended: Fri Dec 02 11:26:18 2016
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:22
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in C:/New folder/ex18/output_files/ex18.map.smsg.
+
+
diff --git a/part_2/ex9_partially_working/output_files/ex9.map.smsg b/part_4/ex18/output_files/ex18.map.smsg
index 4b23fa8..7f85b32 100755
--- a/part_2/ex9_partially_working/output_files/ex9.map.smsg
+++ b/part_4/ex18/output_files/ex18.map.smsg
@@ -1,38 +1,35 @@
-Warning (10268): Verilog HDL information at formula_fsm.v(36): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex9/verilog_files/formula_fsm.v Line: 36
-Info (10281): Verilog HDL Declaration information at delay.v(7): object "time_out" differs only in case from object "TIME_OUT" in the same scope File: C:/New folder/ex9/verilog_files/delay.v Line: 7
-Warning (10268): Verilog HDL information at counter_16.v(16): always construct contains both blocking and non-blocking assignments File: C:/New folder/ex9/verilog_files/counter_16.v Line: 16
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 20
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 21
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
-Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex9/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex18/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_4/ex18/output_files/ex18.map.summary b/part_4/ex18/output_files/ex18.map.summary
new file mode 100755
index 0000000..150eefd
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Fri Dec 02 11:26:18 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex18
+Top-level Entity Name : ex18
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 154
+Total pins : 41
+Total virtual pins : 0
+Total block memory bits : 73,728
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_4/ex18/output_files/ex18.pin b/part_4/ex18/output_files/ex18.pin
new file mode 100755
index 0000000..1455472
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.pin
@@ -0,0 +1,560 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       2.5V
+ --                  Bank 3B:       2.5V
+ --                  Bank 4A:       2.5V
+ --                  Bank 5A:       2.5V
+ --                  Bank 5B:       2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
+ --                  either individually through a 10k Ohm resistor to GND or tie all pins
+ --                  together and connect through a single 10k Ohm resistor to GND.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex18"  ASSIGNED TO AN: 5CGXFC7C7F23C8
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+RREF                         : A1        :        :                   :         :           :                
+MSEL2                        : A2        :        :                   :         : 9A        :                
+VCCBAT                       : A3        : power  :                   : 1.2V    :           :                
+nCONFIG                      : A4        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+VCCIO8A                      : A6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+GND                          : A11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7A        :                
+VCCIO7A                      : A16       : power  :                   : 2.5V    : 7A        :                
+HEX0[0]                      : A17       : output : 2.5 V             :         : 7A        : N              
+HEX0[2]                      : A18       : output : 2.5 V             :         : 7A        : N              
+HEX0[5]                      : A19       : output : 2.5 V             :         : 7A        : N              
+HEX0[1]                      : A20       : output : 2.5 V             :         : 7A        : N              
+GND                          : A21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A22       :        :                   :         : 7A        :                
+GND                          : AA1       :        :                   :         : B0L       :                
+GND                          : AA2       :        :                   :         : B0L       :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+AS_DATA2, DATA2              : AA5       :        :                   :         : 3A        :                
+GND                          : AA6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3B        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4A        :                
+VCCIO4A                      : AA16      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+VCCIO4A                      : AA21      : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 4A        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AB3       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AB4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3B        :                
+GND                          : AB9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12      :        :                   :         : 4A        :                
+SW[3]                        : AB13      : input  : 2.5 V             :         : 4A        : N              
+GND                          : AB14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4A        :                
+VREFB4AN0                    : AB16      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4A        :                
+GND                          : AB19      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4A        :                
+SW[7]                        : AB21      : input  : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22      :        :                   :         : 4A        :                
+GND                          : B1        : gnd    :                   :         :           :                
+GND                          : B2        : gnd    :                   :         :           :                
+DNU                          : B3        :        :                   :         :           :                
+DNU                          : B4        :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+VREFB8AN0                    : B8        : power  :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7A        :                
+VCCIO7A                      : B19       : power  :                   : 2.5V    : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+GND                          : C1        :        :                   :         : B1L       :                
+GND                          : C2        :        :                   :         : B1L       :                
+GND                          : C3        : gnd    :                   :         :           :                
+GND                          : C4        : gnd    :                   :         :           :                
+GND                          : C5        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8A        :                
+VCCIO8A                      : C7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+VCCPD7A8A                    : C10       : power  :                   : 2.5V    : 7A, 8A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7A        :                
+VCCIO7A                      : C12       : power  :                   : 2.5V    : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7A        :                
+VREFB7AN0                    : C14       : power  :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7A        :                
+SW[0]                        : C16       : input  : 2.5 V             :         : 7A        : N              
+GND                          : C17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 7A        :                
+VCCIO7A                      : C22       : power  :                   : 2.5V    : 7A        :                
+GND                          : D1        : gnd    :                   :         :           :                
+GND                          : D2        : gnd    :                   :         :           :                
+GXB_NC                       : D3        :        :                   :         : B1L       :                
+GXB_NC                       : D4        :        :                   :         : B1L       :                
+GND                          : D5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCPD7A8A                    : D8        : power  :                   : 2.5V    : 7A, 8A    :                
+SW[2]                        : D9        : input  : 2.5 V             :         : 8A        : N              
+GND                          : D10       : gnd    :                   :         :           :                
+VCC_AUX                      : D11       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7A        :                
+VCCPD7A8A                    : D14       : power  :                   : 2.5V    : 7A, 8A    :                
+VCCIO7A                      : D15       : power  :                   : 2.5V    : 7A        :                
+VCCPD7A8A                    : D16       : power  :                   : 2.5V    : 7A, 8A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7A        :                
+VCC_AUX                      : D18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7A        :                
+GND                          : D20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GXB_NC                       : E1        :        :                   :         : B1L       :                
+GXB_NC                       : E2        :        :                   :         : B1L       :                
+GND                          : E3        : gnd    :                   :         :           :                
+GND                          : E4        : gnd    :                   :         :           :                
+MSEL3                        : E5        :        :                   :         : 9A        :                
+VCC_AUX                      : E6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+VCCIO8A                      : E8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8A        :                
+VCCPD7A8A                    : E11       : power  :                   : 2.5V    : 7A, 8A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7A        :                
+GND                          : E13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7A        :                
+DNU                          : E17       :        :                   :         :           :                
+VCCIO7A                      : E18       : power  :                   : 2.5V    : 7A        :                
+SW[1]                        : E19       : input  : 2.5 V             :         : 7A        : N              
+HEX0[4]                      : E20       : output : 2.5 V             :         : 7A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7A        :                
+HEX2[1]                      : E22       : output : 2.5 V             :         : 7A        : N              
+GND                          : F1        : gnd    :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+MSEL4                        : F3        :        :                   :         : 9A        :                
+VCCA_FPLL                    : F4        : power  :                   : 2.5V    :           :                
+GND                          : F5        :        :                   :         : B1L       :                
+GND                          : F6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8A        :                
+VCCPGM                       : F8        : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+VCCIO7A                      : F11       : power  :                   : 2.5V    : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7A        :                
+GND                          : F16       : gnd    :                   :         :           :                
+GND                          : F17       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7A        :                
+HEX2[5]                      : F19       : output : 2.5 V             :         : 7A        : N              
+HEX2[4]                      : F20       : output : 2.5 V             :         : 7A        : N              
+VCCIO7A                      : F21       : power  :                   : 2.5V    : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 7A        :                
+GND                          : G1        :        :                   :         : B1L       :                
+GND                          : G2        :        :                   :         : B1L       :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        :        :                   :         : B1L       :                
+nCE                          : G5        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G6        :        :                   :         : 8A        :                
+VCCIO8A                      : G7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+GND                          : G9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7A        :                
+VCCIO7A                      : G14       : power  :                   : 2.5V    : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7A        :                
+GND                          : G19       : gnd    :                   :         :           :                
+DAC_SCK                      : G20       : output : 2.5 V             :         : 7A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+GND                          : H3        : gnd    :                   :         :           :                
+GND                          : H4        : gnd    :                   :         :           :                
+nSTATUS                      : H5        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H6        :        :                   :         : 8A        :                
+GND                          : H7        : gnd    :                   :         :           :                
+SW[5]                        : H8        : input  : 2.5 V             :         : 8A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 7A        :                
+GND                          : H12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 7A        :                
+VCCIO7A                      : H17       : power  :                   : 2.5V    : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7A        :                
+VCCA_FPLL                    : H19       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21       :        :                   :         : 7A        :                
+GND                          : H22       : gnd    :                   :         :           :                
+GXB_NC                       : J1        :        :                   :         : B1L       :                
+GXB_NC                       : J2        :        :                   :         : B1L       :                
+GND                          : J3        : gnd    :                   :         :           :                
+VCCE_GXBL                    : J4        : power  :                   : 1.1V    :           :                
+GND                          : J5        : gnd    :                   :         :           :                
+MSEL1                        : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+VCC                          : J10       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J11       :        :                   :         : 7A        :                
+VCC                          : J12       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J13       :        :                   :         : 7A        :                
+VCC                          : J14       : power  :                   : 1.1V    :           :                
+GND                          : J15       : gnd    :                   :         :           :                
+VCC                          : J16       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7A        :                
+GND                          : J20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22       :        :                   :         : 7A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+VCCL_GXBL                    : K3        : power  :                   : 1.1V    :           :                
+GND                          : K4        : gnd    :                   :         :           :                
+VCCE_GXBL                    : K5        : power  :                   : 1.1V    :           :                
+CONF_DONE                    : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+GND                          : K8        : gnd    :                   :         :           :                
+SW[8]                        : K9        : input  : 2.5 V             :         : 7A        : N              
+GND                          : K10       : gnd    :                   :         :           :                
+VCC                          : K11       : power  :                   : 1.1V    :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+VCC                          : K13       : power  :                   : 1.1V    :           :                
+GND                          : K14       : gnd    :                   :         :           :                
+VCC                          : K15       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 7A        :                
+HEX1[5]                      : K17       : output : 2.5 V             :         : 5B        : N              
+VCCIO5B                      : K18       : power  :                   : 2.5V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K20       :        :                   :         : 7A        :                
+PWM_OUT                      : K21       : output : 2.5 V             :         : 5B        : N              
+HEX1[2]                      : K22       : output : 2.5 V             :         : 5B        : N              
+GND                          : L1        :        :                   :         : B1L       :                
+GND                          : L2        :        :                   :         : B1L       :                
+GND                          : L3        : gnd    :                   :         :           :                
+VCCE_GXBL                    : L4        : power  :                   : 1.1V    :           :                
+GND                          : L5        : gnd    :                   :         :           :                
+MSEL0                        : L6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 7A        :                
+DNU                          : L9        :        :                   :         :           :                
+VCC                          : L10       : power  :                   : 1.1V    :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCC                          : L12       : power  :                   : 1.1V    :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCC                          : L14       : power  :                   : 1.1V    :           :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC                          : L16       : power  :                   : 1.1V    :           :                
+HEX1[4]                      : L17       : output : 2.5 V             :         : 5B        : N              
+HEX1[6]                      : L18       : output : 2.5 V             :         : 5B        : N              
+HEX1[0]                      : L19       : output : 2.5 V             :         : 5B        : N              
+VREFB5BN0                    : L20       : power  :                   :         : 5B        :                
+GND                          : L21       : gnd    :                   :         :           :                
+ADC_SCK                      : L22       : output : 2.5 V             :         : 5B        : N              
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+VCCH_GXBL                    : M3        : power  :                   : 2.5V    :           :                
+GND                          : M4        : gnd    :                   :         :           :                
+TDO                          : M5        : output :                   :         : 3A        :                
+SW[4]                        : M6        : input  : 2.5 V             :         : 3A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M9        :        :                   :         : 3B        :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC                          : M15       : power  :                   : 1.1V    :           :                
+CLOCK_50                     : M16       : input  : 2.5 V             :         : 5B        : N              
+VCCPD5B                      : M17       : power  :                   : 2.5V    : 5B        :                
+DAC_CS                       : M18       : output : 2.5 V             :         : 5B        : N              
+VCCIO5B                      : M19       : power  :                   : 2.5V    : 5B        :                
+DAC_SDI                      : M20       : output : 2.5 V             :         : 5B        : N              
+HEX2[6]                      : M21       : output : 2.5 V             :         : 5B        : N              
+ADC_SDO                      : M22       : input  : 2.5 V             :         : 5B        : N              
+GXB_NC                       : N1        :        :                   :         : B0L       :                
+GXB_NC                       : N2        :        :                   :         : B0L       :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCE_GXBL                    : N4        : power  :                   : 1.1V    :           :                
+GND                          : N5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3A        :                
+GND                          : N7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N9        :        :                   :         : 3B        :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+HEX1[1]                      : N16       : output : 2.5 V             :         : 5B        : N              
+GND                          : N17       : gnd    :                   :         :           :                
+VCCPD5B                      : N18       : power  :                   : 2.5V    : 5B        :                
+ADC_CS                       : N19       : output : 2.5 V             :         : 5B        : N              
+DAC_LD                       : N20       : output : 2.5 V             :         : 5B        : N              
+HEX1[3]                      : N21       : output : 2.5 V             :         : 5B        : N              
+GND                          : N22       : gnd    :                   :         :           :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+VCCL_GXBL                    : P3        : power  :                   : 1.1V    :           :                
+GND                          : P4        : gnd    :                   :         :           :                
+TMS                          : P5        : input  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P9        :        :                   :         : 3B        :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P12       :        :                   :         : 3B        :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 4A        :                
+VCC                          : P15       : power  :                   : 1.1V    :           :                
+HEX2[2]                      : P16       : output : 2.5 V             :         : 5A        : N              
+HEX2[0]                      : P17       : output : 2.5 V             :         : 5A        : N              
+HEX0[3]                      : P18       : output : 2.5 V             :         : 5A        : N              
+HEX2[3]                      : P19       : output : 2.5 V             :         : 5A        : N              
+VCCIO5A                      : P20       : power  :                   : 2.5V    : 5A        :                
+VCCPD5A                      : P21       : power  :                   : 2.5V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5A        :                
+GND                          : R1        :        :                   :         : B0L       :                
+GND                          : R2        :        :                   :         : B0L       :                
+GND                          : R3        : gnd    :                   :         :           :                
+nCSO, DATA4                  : R4        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 3A        :                
+SW[9]                        : R7        : input  : 2.5 V             :         : 3A        : N              
+VCCIO3B                      : R8        : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3B        :                
+GND                          : R13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5A        :                
+VCCIO5A                      : R18       : power  :                   : 2.5V    : 5A        :                
+VCCPGM                       : R19       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VREFB5AN0                    : R20       : power  :                   :         : 5A        :                
+HEX0[6]                      : R21       : output : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5A        :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+VCCH_GXBL                    : T3        : power  :                   : 2.5V    :           :                
+AS_DATA3, DATA3              : T4        :        :                   :         : 3A        :                
+VCCA_FPLL                    : T5        : power  :                   : 2.5V    :           :                
+VCCIO3A                      : T6        : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3B        :                
+VCCIO3B                      : T11       : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T13       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 5A        :                
+GND                          : T16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5A        :                
+SW[6]                        : T18       : input  : 2.5 V             :         : 5A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T19       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T20       :        :                   :         : 5A        :                
+GND                          : T21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T22       :        :                   :         : 5A        :                
+GXB_NC                       : U1        :        :                   :         : B0L       :                
+GXB_NC                       : U2        :        :                   :         : B0L       :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        :        :                   :         : B0L       :                
+GND                          : U5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U6        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4A        :                
+VCCIO4A                      : U14       : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U17       :        :                   :         : 4A        :                
+VCCA_FPLL                    : U18       : power  :                   : 2.5V    :           :                
+VCCIO4A                      : U19       : power  :                   : 2.5V    : 4A        :                
+ADC_SDI                      : U20       : output : 2.5 V             :         : 4A        : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 4A        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DCLK                         : V3        :        :                   :         : 3A        :                
+GND                          : V4        :        :                   :         : B0L       :                
+TCK                          : V5        : input  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3A        :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCPGM                       : V8        : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3B        :                
+DNU                          : V11       :        :                   :         :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+GND                          : V17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 4A        :                
+GND                          : V22       : gnd    :                   :         :           :                
+GND                          : W1        :        :                   :         : B0L       :                
+GND                          : W2        :        :                   :         : B0L       :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+TDI                          : W5        : input  :                   :         : 3A        :                
+VCCPD3A                      : W6        : power  :                   : 2.5V    : 3A        :                
+VCC_AUX                      : W7        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W9        :        :                   :         : 3A        :                
+VCCIO3B                      : W10       : power  :                   : 2.5V    : 3B        :                
+VCCPD3B4A                    : W11       : power  :                   : 2.5V    : 3B, 4A    :                
+VCCPD3B4A                    : W12       : power  :                   : 2.5V    : 3B, 4A    :                
+VCC_AUX                      : W13       : power  :                   : 2.5V    :           :                
+VCCPD3B4A                    : W14       : power  :                   : 2.5V    : 3B, 4A    :                
+VCCIO4A                      : W15       : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+VCCPD3B4A                    : W17       : power  :                   : 2.5V    : 3B, 4A    :                
+VCC_AUX                      : W18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+VCCIO4A                      : W20       : power  :                   : 2.5V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 4A        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+GXB_NC                       : Y3        :        :                   :         : B0L       :                
+GXB_NC                       : Y4        :        :                   :         : B0L       :                
+GND                          : Y5        : gnd    :                   :         :           :                
+DNU                          : Y6        :        :                   :         :           :                
+VREFB3AN0                    : Y7        : power  :                   :         : 3A        :                
+VCCIO3A                      : Y8        : power  :                   : 2.5V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y9        :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y11       :        :                   :         : 3B        :                
+VREFB3BN0                    : Y12       : power  :                   :         : 3B        :                
+VCCIO3B                      : Y13       : power  :                   : 2.5V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y14       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y15       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+GND                          : Y18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y20       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 4A        :                
diff --git a/part_4/ex18/output_files/ex18.sld b/part_4/ex18/output_files/ex18.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/part_4/ex18/output_files/ex18.sof b/part_4/ex18/output_files/ex18.sof
new file mode 100755
index 0000000..dd6f23a
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.sof
diff --git a/part_4/ex18/output_files/ex18.sta.rpt b/part_4/ex18/output_files/ex18.sta.rpt
new file mode 100755
index 0000000..9aaa80e
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.sta.rpt
@@ -0,0 +1,901 @@
+TimeQuest Timing Analyzer report for ex18
+Fri Dec 02 11:27:15 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1100mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1100mV 85C Model Setup Summary
+  8. Slow 1100mV 85C Model Hold Summary
+  9. Slow 1100mV 85C Model Recovery Summary
+ 10. Slow 1100mV 85C Model Removal Summary
+ 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1100mV 85C Model Metastability Summary
+ 13. Slow 1100mV 0C Model Fmax Summary
+ 14. Slow 1100mV 0C Model Setup Summary
+ 15. Slow 1100mV 0C Model Hold Summary
+ 16. Slow 1100mV 0C Model Recovery Summary
+ 17. Slow 1100mV 0C Model Removal Summary
+ 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1100mV 0C Model Metastability Summary
+ 20. Fast 1100mV 85C Model Setup Summary
+ 21. Fast 1100mV 85C Model Hold Summary
+ 22. Fast 1100mV 85C Model Recovery Summary
+ 23. Fast 1100mV 85C Model Removal Summary
+ 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
+ 25. Fast 1100mV 85C Model Metastability Summary
+ 26. Fast 1100mV 0C Model Setup Summary
+ 27. Fast 1100mV 0C Model Hold Summary
+ 28. Fast 1100mV 0C Model Recovery Summary
+ 29. Fast 1100mV 0C Model Removal Summary
+ 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
+ 31. Fast 1100mV 0C Model Metastability Summary
+ 32. Multicorner Timing Analysis Summary
+ 33. Board Trace Model Assignments
+ 34. Input Transition Times
+ 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
+ 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
+ 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
+ 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
+ 39. Setup Transfers
+ 40. Hold Transfers
+ 41. Report TCCS
+ 42. Report RSKM
+ 43. Unconstrained Paths Summary
+ 44. Clock Status Summary
+ 45. Unconstrained Input Ports
+ 46. Unconstrained Output Ports
+ 47. Unconstrained Input Ports
+ 48. Unconstrained Output Ports
+ 49. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                               ;
++-----------------------+---------------------------------------------------------+
+; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Timing Analyzer       ; TimeQuest                                               ;
+; Revision Name         ; ex18                                                    ;
+; Device Family         ; Cyclone V                                               ;
+; Device Name           ; 5CGXFC7C7F23C8                                          ;
+; Timing Models         ; Final                                                   ;
+; Delay Model           ; Combined                                                ;
+; Rise/Fall Delays      ; Enabled                                                 ;
++-----------------------+---------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.15        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   5.0%      ;
+;     Processor 3            ;   4.9%      ;
+;     Processor 4            ;   4.9%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                             ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+; Clock Name               ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                      ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+; clktick_16:GEN_10K|tick  ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clktick_16:GEN_10K|tick }  ;
+; CLOCK_50                 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                 ;
+; spi2adc:SPI_ADC|clk_1MHz ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2adc:SPI_ADC|clk_1MHz } ;
+; spi2dac:SPI_DAC|clk_1MHz ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2dac:SPI_DAC|clk_1MHz } ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 85C Model Fmax Summary                             ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 87.75 MHz  ; 87.75 MHz       ; CLOCK_50                 ;      ;
+; 155.96 MHz ; 155.96 MHz      ; spi2adc:SPI_ADC|clk_1MHz ;      ;
+; 336.59 MHz ; 336.59 MHz      ; spi2dac:SPI_DAC|clk_1MHz ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++----------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary                ;
++--------------------------+---------+---------------+
+; Clock                    ; Slack   ; End Point TNS ;
++--------------------------+---------+---------------+
+; CLOCK_50                 ; -10.396 ; -1930.765     ;
+; spi2adc:SPI_ADC|clk_1MHz ; -4.481  ; -76.352       ;
+; spi2dac:SPI_DAC|clk_1MHz ; -4.340  ; -79.060       ;
+; clktick_16:GEN_10K|tick  ; -3.446  ; -3.446        ;
++--------------------------+---------+---------------+
+
+
++--------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary               ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; CLOCK_50                 ; 0.177 ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.433 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.752 ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 2.922 ; 0.000         ;
++--------------------------+-------+---------------+
+
+
+------------------------------------------
+; Slow 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -3.166 ; -2106.846     ;
+; spi2adc:SPI_ADC|clk_1MHz ; -0.724 ; -35.901       ;
+; spi2dac:SPI_DAC|clk_1MHz ; -0.724 ; -26.588       ;
+; clktick_16:GEN_10K|tick  ; -0.724 ; -1.136        ;
++--------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Slow 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary                              ;
++------------+-----------------+--------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
++------------+-----------------+--------------------------+------+
+; 86.54 MHz  ; 86.54 MHz       ; CLOCK_50                 ;      ;
+; 167.06 MHz ; 167.06 MHz      ; spi2adc:SPI_ADC|clk_1MHz ;      ;
+; 330.58 MHz ; 330.58 MHz      ; spi2dac:SPI_DAC|clk_1MHz ;      ;
++------------+-----------------+--------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++----------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary                 ;
++--------------------------+---------+---------------+
+; Clock                    ; Slack   ; End Point TNS ;
++--------------------------+---------+---------------+
+; CLOCK_50                 ; -10.556 ; -1900.830     ;
+; spi2adc:SPI_ADC|clk_1MHz ; -4.649  ; -73.671       ;
+; spi2dac:SPI_DAC|clk_1MHz ; -4.477  ; -81.791       ;
+; clktick_16:GEN_10K|tick  ; -3.689  ; -3.689        ;
++--------------------------+---------+---------------+
+
+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary                 ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -0.251 ; -2.476        ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.516  ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.750  ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 3.173  ; 0.000         ;
++--------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Slow 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary  ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -3.166 ; -2105.141     ;
+; spi2adc:SPI_ADC|clk_1MHz ; -0.724 ; -35.136       ;
+; spi2dac:SPI_DAC|clk_1MHz ; -0.724 ; -26.303       ;
+; clktick_16:GEN_10K|tick  ; -0.724 ; -1.131        ;
++--------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Slow 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary               ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -4.377 ; -721.833      ;
+; spi2dac:SPI_DAC|clk_1MHz ; -1.710 ; -26.172       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -1.537 ; -25.590       ;
+; clktick_16:GEN_10K|tick  ; -1.128 ; -1.128        ;
++--------------------------+--------+---------------+
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -0.177 ; -0.991        ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.172  ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.240  ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 1.116  ; 0.000         ;
++--------------------------+--------+---------------+
+
+
+------------------------------------------
+; Fast 1100mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1100mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1313.734     ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.082  ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.104  ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 0.126  ; 0.000         ;
++--------------------------+--------+---------------+
+
+
+-----------------------------------------------
+; Fast 1100mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -3.956 ; -615.142      ;
+; spi2dac:SPI_DAC|clk_1MHz ; -1.593 ; -24.610       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -1.474 ; -23.182       ;
+; clktick_16:GEN_10K|tick  ; -1.111 ; -1.111        ;
++--------------------------+--------+---------------+
+
+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary                 ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -0.307 ; -14.229       ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.157  ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.212  ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 1.109  ; 0.000         ;
++--------------------------+--------+---------------+
+
+
+-----------------------------------------
+; Fast 1100mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1100mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary  ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1314.254     ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.104  ; 0.000         ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.122  ; 0.000         ;
+; clktick_16:GEN_10K|tick  ; 0.131  ; 0.000         ;
++--------------------------+--------+---------------+
+
+
+----------------------------------------------
+; Fast 1100mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                        ;
++---------------------------+-----------+---------+----------+---------+---------------------+
+; Clock                     ; Setup     ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
++---------------------------+-----------+---------+----------+---------+---------------------+
+; Worst-case Slack          ; -10.556   ; -0.307  ; N/A      ; N/A     ; -3.166              ;
+;  CLOCK_50                 ; -10.556   ; -0.307  ; N/A      ; N/A     ; -3.166              ;
+;  clktick_16:GEN_10K|tick  ; -3.689    ; 1.109   ; N/A      ; N/A     ; -0.724              ;
+;  spi2adc:SPI_ADC|clk_1MHz ; -4.649    ; 0.157   ; N/A      ; N/A     ; -0.724              ;
+;  spi2dac:SPI_DAC|clk_1MHz ; -4.477    ; 0.212   ; N/A      ; N/A     ; -0.724              ;
+; Design-wide TNS           ; -2089.623 ; -14.229 ; 0.0      ; 0.0     ; -2170.471           ;
+;  CLOCK_50                 ; -1930.765 ; -14.229 ; N/A      ; N/A     ; -2106.846           ;
+;  clktick_16:GEN_10K|tick  ; -3.689    ; 0.000   ; N/A      ; N/A     ; -1.136              ;
+;  spi2adc:SPI_ADC|clk_1MHz ; -76.352   ; 0.000   ; N/A      ; N/A     ; -35.901             ;
+;  spi2dac:SPI_DAC|clk_1MHz ; -81.791   ; 0.000   ; N/A      ; N/A     ; -26.588             ;
++---------------------------+-----------+---------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                              ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin     ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; HEX0[0] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6] ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SDI ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SCK ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_CS  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_LD  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SDI ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SCK ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_CS  ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PWM_OUT ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++-------------------------------------------------------------+
+; Input Transition Times                                      ;
++----------+--------------+-----------------+-----------------+
+; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++----------+--------------+-----------------+-----------------+
+; SW[0]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[1]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[2]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[3]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[4]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[5]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[6]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[7]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[8]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; SW[9]    ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; CLOCK_50 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ADC_SDO  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++----------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.91e-08 V                   ; 2.35 V              ; -0.0136 V           ; 0.17 V                               ; 0.118 V                              ; 4.69e-10 s                  ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.91e-08 V                  ; 2.35 V             ; -0.0136 V          ; 0.17 V                              ; 0.118 V                             ; 4.69e-10 s                 ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
+; HEX0[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX0[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.86e-08 V                   ; 2.4 V               ; -0.0326 V           ; 0.227 V                              ; 0.16 V                               ; 4.73e-10 s                  ; 4.78e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.86e-08 V                  ; 2.4 V              ; -0.0326 V          ; 0.227 V                             ; 0.16 V                              ; 4.73e-10 s                 ; 4.78e-10 s                 ; No                        ; Yes                       ;
+; HEX0[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.0409 V           ; 0.192 V                              ; 0.125 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.0409 V          ; 0.192 V                             ; 0.125 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX0[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX0[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.0409 V           ; 0.192 V                              ; 0.125 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.0409 V          ; 0.192 V                             ; 0.125 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX0[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX1[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.86e-08 V                   ; 2.4 V               ; -0.0326 V           ; 0.227 V                              ; 0.16 V                               ; 4.73e-10 s                  ; 4.78e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.86e-08 V                  ; 2.4 V              ; -0.0326 V          ; 0.227 V                             ; 0.16 V                              ; 4.73e-10 s                 ; 4.78e-10 s                 ; No                        ; Yes                       ;
+; HEX1[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.86e-08 V                   ; 2.4 V               ; -0.0326 V           ; 0.227 V                              ; 0.16 V                               ; 4.73e-10 s                  ; 4.78e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.86e-08 V                  ; 2.4 V              ; -0.0326 V          ; 0.227 V                             ; 0.16 V                              ; 4.73e-10 s                 ; 4.78e-10 s                 ; No                        ; Yes                       ;
+; HEX1[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.0409 V           ; 0.192 V                              ; 0.125 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.0409 V          ; 0.192 V                             ; 0.125 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX1[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.0409 V           ; 0.192 V                              ; 0.125 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.0409 V          ; 0.192 V                             ; 0.125 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX1[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.91e-08 V                   ; 2.35 V              ; -0.0136 V           ; 0.17 V                               ; 0.118 V                              ; 4.69e-10 s                  ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.91e-08 V                  ; 2.35 V             ; -0.0136 V          ; 0.17 V                              ; 0.118 V                             ; 4.69e-10 s                 ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
+; HEX1[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.86e-08 V                   ; 2.4 V               ; -0.0326 V           ; 0.227 V                              ; 0.16 V                               ; 4.73e-10 s                  ; 4.78e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.86e-08 V                  ; 2.4 V              ; -0.0326 V          ; 0.227 V                             ; 0.16 V                              ; 4.73e-10 s                 ; 4.78e-10 s                 ; No                        ; Yes                       ;
+; HEX1[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.91e-08 V                   ; 2.35 V              ; -0.0136 V           ; 0.17 V                               ; 0.118 V                              ; 4.69e-10 s                  ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.91e-08 V                  ; 2.35 V             ; -0.0136 V          ; 0.17 V                              ; 0.118 V                             ; 4.69e-10 s                 ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.91e-08 V                   ; 2.35 V              ; -0.0136 V           ; 0.17 V                               ; 0.118 V                              ; 4.69e-10 s                  ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.91e-08 V                  ; 2.35 V             ; -0.0136 V          ; 0.17 V                              ; 0.118 V                             ; 4.69e-10 s                 ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
+; HEX2[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX2[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.86e-08 V                   ; 2.4 V               ; -0.0326 V           ; 0.227 V                              ; 0.16 V                               ; 4.73e-10 s                  ; 4.78e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.86e-08 V                  ; 2.4 V              ; -0.0326 V          ; 0.227 V                             ; 0.16 V                              ; 4.73e-10 s                 ; 4.78e-10 s                 ; No                        ; Yes                       ;
+; HEX2[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX2[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.0409 V           ; 0.192 V                              ; 0.125 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.0409 V          ; 0.192 V                             ; 0.125 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; HEX2[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.86e-08 V                   ; 2.4 V               ; -0.0326 V           ; 0.227 V                              ; 0.16 V                               ; 4.73e-10 s                  ; 4.78e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.86e-08 V                  ; 2.4 V              ; -0.0326 V          ; 0.227 V                             ; 0.16 V                              ; 4.73e-10 s                 ; 4.78e-10 s                 ; No                        ; Yes                       ;
+; HEX2[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.0409 V           ; 0.192 V                              ; 0.125 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.0409 V          ; 0.192 V                             ; 0.125 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; DAC_SDI ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; DAC_SCK ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.86e-08 V                   ; 2.4 V               ; -0.0326 V           ; 0.227 V                              ; 0.16 V                               ; 4.73e-10 s                  ; 4.78e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.86e-08 V                  ; 2.4 V              ; -0.0326 V          ; 0.227 V                             ; 0.16 V                              ; 4.73e-10 s                 ; 4.78e-10 s                 ; No                        ; Yes                       ;
+; DAC_CS  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 5.91e-08 V                   ; 2.35 V              ; -0.0136 V           ; 0.17 V                               ; 0.118 V                              ; 4.69e-10 s                  ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 5.91e-08 V                  ; 2.35 V             ; -0.0136 V          ; 0.17 V                              ; 0.118 V                             ; 4.69e-10 s                 ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_LD  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; ADC_SDI ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; ADC_SCK ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.0409 V           ; 0.192 V                              ; 0.125 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.0409 V          ; 0.192 V                             ; 0.125 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
+; ADC_CS  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.86e-08 V                   ; 2.4 V               ; -0.0326 V           ; 0.227 V                              ; 0.16 V                               ; 4.73e-10 s                  ; 4.78e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.86e-08 V                  ; 2.4 V              ; -0.0326 V          ; 0.227 V                             ; 0.16 V                              ; 4.73e-10 s                 ; 4.78e-10 s                 ; No                        ; Yes                       ;
+; PWM_OUT ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.72e-08 V                   ; 2.4 V               ; -0.041 V            ; 0.19 V                               ; 0.126 V                              ; 4.59e-10 s                  ; 4.54e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 6.72e-08 V                  ; 2.4 V              ; -0.041 V           ; 0.19 V                              ; 0.126 V                             ; 4.59e-10 s                 ; 4.54e-10 s                 ; No                        ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.38e-06 V                   ; 2.34 V              ; -0.00733 V          ; 0.234 V                              ; 0.071 V                              ; 5.36e-10 s                  ; 5.75e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 9.38e-06 V                  ; 2.34 V             ; -0.00733 V         ; 0.234 V                             ; 0.071 V                             ; 5.36e-10 s                 ; 5.75e-10 s                 ; No                        ; Yes                       ;
+; HEX0[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; HEX0[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.05e-05 V                   ; 2.37 V              ; -0.0225 V           ; 0.277 V                              ; 0.104 V                              ; 5.22e-10 s                  ; 6.28e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.05e-05 V                  ; 2.37 V             ; -0.0225 V          ; 0.277 V                             ; 0.104 V                             ; 5.22e-10 s                 ; 6.28e-10 s                 ; No                        ; Yes                       ;
+; HEX0[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.027 V            ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.18e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.027 V           ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.18e-10 s                 ; No                        ; Yes                       ;
+; HEX0[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; HEX0[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.027 V            ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.18e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.027 V           ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.18e-10 s                 ; No                        ; Yes                       ;
+; HEX0[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; HEX1[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.05e-05 V                   ; 2.37 V              ; -0.0225 V           ; 0.277 V                              ; 0.104 V                              ; 5.22e-10 s                  ; 6.28e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.05e-05 V                  ; 2.37 V             ; -0.0225 V          ; 0.277 V                             ; 0.104 V                             ; 5.22e-10 s                 ; 6.28e-10 s                 ; No                        ; Yes                       ;
+; HEX1[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.05e-05 V                   ; 2.37 V              ; -0.0225 V           ; 0.277 V                              ; 0.104 V                              ; 5.22e-10 s                  ; 6.28e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.05e-05 V                  ; 2.37 V             ; -0.0225 V          ; 0.277 V                             ; 0.104 V                             ; 5.22e-10 s                 ; 6.28e-10 s                 ; No                        ; Yes                       ;
+; HEX1[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.027 V            ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.18e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.027 V           ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.18e-10 s                 ; No                        ; Yes                       ;
+; HEX1[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.027 V            ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.18e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.027 V           ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.18e-10 s                 ; No                        ; Yes                       ;
+; HEX1[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.38e-06 V                   ; 2.34 V              ; -0.00733 V          ; 0.234 V                              ; 0.071 V                              ; 5.36e-10 s                  ; 5.75e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 9.38e-06 V                  ; 2.34 V             ; -0.00733 V         ; 0.234 V                             ; 0.071 V                             ; 5.36e-10 s                 ; 5.75e-10 s                 ; No                        ; Yes                       ;
+; HEX1[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.05e-05 V                   ; 2.37 V              ; -0.0225 V           ; 0.277 V                              ; 0.104 V                              ; 5.22e-10 s                  ; 6.28e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.05e-05 V                  ; 2.37 V             ; -0.0225 V          ; 0.277 V                             ; 0.104 V                             ; 5.22e-10 s                 ; 6.28e-10 s                 ; No                        ; Yes                       ;
+; HEX1[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.38e-06 V                   ; 2.34 V              ; -0.00733 V          ; 0.234 V                              ; 0.071 V                              ; 5.36e-10 s                  ; 5.75e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 9.38e-06 V                  ; 2.34 V             ; -0.00733 V         ; 0.234 V                             ; 0.071 V                             ; 5.36e-10 s                 ; 5.75e-10 s                 ; No                        ; Yes                       ;
+; HEX2[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.38e-06 V                   ; 2.34 V              ; -0.00733 V          ; 0.234 V                              ; 0.071 V                              ; 5.36e-10 s                  ; 5.75e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 9.38e-06 V                  ; 2.34 V             ; -0.00733 V         ; 0.234 V                             ; 0.071 V                             ; 5.36e-10 s                 ; 5.75e-10 s                 ; No                        ; Yes                       ;
+; HEX2[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; HEX2[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.05e-05 V                   ; 2.37 V              ; -0.0225 V           ; 0.277 V                              ; 0.104 V                              ; 5.22e-10 s                  ; 6.28e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.05e-05 V                  ; 2.37 V             ; -0.0225 V          ; 0.277 V                             ; 0.104 V                             ; 5.22e-10 s                 ; 6.28e-10 s                 ; No                        ; Yes                       ;
+; HEX2[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; HEX2[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.027 V            ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.18e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.027 V           ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.18e-10 s                 ; No                        ; Yes                       ;
+; HEX2[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.05e-05 V                   ; 2.37 V              ; -0.0225 V           ; 0.277 V                              ; 0.104 V                              ; 5.22e-10 s                  ; 6.28e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.05e-05 V                  ; 2.37 V             ; -0.0225 V          ; 0.277 V                             ; 0.104 V                             ; 5.22e-10 s                 ; 6.28e-10 s                 ; No                        ; Yes                       ;
+; HEX2[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.027 V            ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.18e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.027 V           ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.18e-10 s                 ; No                        ; Yes                       ;
+; DAC_SDI ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; DAC_SCK ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.05e-05 V                   ; 2.37 V              ; -0.0225 V           ; 0.277 V                              ; 0.104 V                              ; 5.22e-10 s                  ; 6.28e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.05e-05 V                  ; 2.37 V             ; -0.0225 V          ; 0.277 V                             ; 0.104 V                             ; 5.22e-10 s                 ; 6.28e-10 s                 ; No                        ; Yes                       ;
+; DAC_CS  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.38e-06 V                   ; 2.34 V              ; -0.00733 V          ; 0.234 V                              ; 0.071 V                              ; 5.36e-10 s                  ; 5.75e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 9.38e-06 V                  ; 2.34 V             ; -0.00733 V         ; 0.234 V                             ; 0.071 V                             ; 5.36e-10 s                 ; 5.75e-10 s                 ; No                        ; Yes                       ;
+; DAC_LD  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ADC_SDI ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
+; ADC_SCK ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.027 V            ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.18e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.027 V           ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.18e-10 s                 ; No                        ; Yes                       ;
+; ADC_CS  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.05e-05 V                   ; 2.37 V              ; -0.0225 V           ; 0.277 V                              ; 0.104 V                              ; 5.22e-10 s                  ; 6.28e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.05e-05 V                  ; 2.37 V             ; -0.0225 V          ; 0.277 V                             ; 0.104 V                             ; 5.22e-10 s                 ; 6.28e-10 s                 ; No                        ; Yes                       ;
+; PWM_OUT ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.04e-05 V                   ; 2.38 V              ; -0.0273 V           ; 0.226 V                              ; 0.08 V                               ; 4.84e-10 s                  ; 5.19e-10 s                  ; No                         ; Yes                        ; 2.32 V                      ; 1.04e-05 V                  ; 2.38 V             ; -0.0273 V          ; 0.226 V                             ; 0.08 V                              ; 4.84e-10 s                 ; 5.19e-10 s                 ; No                        ; Yes                       ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; HEX0[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX0[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; HEX0[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX0[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX0[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX0[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX1[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; HEX1[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; HEX1[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX1[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX1[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; HEX1[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; HEX1[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; HEX2[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; HEX2[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX2[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; HEX2[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX2[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; HEX2[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; HEX2[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; DAC_SDI ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; DAC_SCK ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; DAC_CS  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 3.54e-06 V                   ; 2.81 V              ; -0.0578 V           ; 0.303 V                              ; 0.28 V                               ; 2.93e-10 s                  ; 3.01e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 3.54e-06 V                  ; 2.81 V             ; -0.0578 V          ; 0.303 V                             ; 0.28 V                              ; 2.93e-10 s                 ; 3.01e-10 s                 ; No                        ; No                        ;
+; DAC_LD  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; ADC_SDI ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; ADC_SCK ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.121 V            ; 0.326 V                              ; 0.297 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.121 V           ; 0.326 V                             ; 0.297 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
+; ADC_CS  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.25e-06 V                   ; 2.9 V               ; -0.107 V            ; 0.378 V                              ; 0.16 V                               ; 2.87e-10 s                  ; 4.28e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 4.25e-06 V                  ; 2.9 V              ; -0.107 V           ; 0.378 V                             ; 0.16 V                              ; 2.87e-10 s                 ; 4.28e-10 s                 ; No                        ; No                        ;
+; PWM_OUT ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 4.14e-06 V                   ; 2.91 V              ; -0.119 V            ; 0.326 V                              ; 0.298 V                              ; 2.74e-10 s                  ; 2.8e-10 s                   ; No                         ; No                         ; 2.75 V                      ; 4.14e-06 V                  ; 2.91 V             ; -0.119 V           ; 0.326 V                             ; 0.298 V                             ; 2.74e-10 s                 ; 2.8e-10 s                  ; No                        ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1100mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin     ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; HEX0[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; HEX0[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX0[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; HEX0[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX0[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX0[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX0[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX1[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; HEX1[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; HEX1[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX1[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX1[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; HEX1[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; HEX1[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; HEX2[0] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; HEX2[1] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX2[2] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; HEX2[3] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX2[4] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; HEX2[5] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; HEX2[6] ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; DAC_SDI ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; DAC_SCK ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; DAC_CS  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000213 V                   ; 2.79 V              ; -0.0324 V           ; 0.139 V                              ; 0.119 V                              ; 4.42e-10 s                  ; 4.33e-10 s                  ; No                         ; Yes                        ; 2.75 V                      ; 0.000213 V                  ; 2.79 V             ; -0.0324 V          ; 0.139 V                             ; 0.119 V                             ; 4.42e-10 s                 ; 4.33e-10 s                 ; No                        ; Yes                       ;
+; DAC_LD  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; ADC_SDI ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
+; ADC_SCK ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0814 V           ; 0.36 V                               ; 0.156 V                              ; 3e-10 s                     ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0814 V          ; 0.36 V                              ; 0.156 V                             ; 3e-10 s                    ; 4.34e-10 s                 ; No                        ; No                        ;
+; ADC_CS  ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000247 V                   ; 2.85 V              ; -0.0711 V           ; 0.204 V                              ; 0.181 V                              ; 4.55e-10 s                  ; 4.49e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000247 V                  ; 2.85 V             ; -0.0711 V          ; 0.204 V                             ; 0.181 V                             ; 4.55e-10 s                 ; 4.49e-10 s                 ; No                        ; No                        ;
+; PWM_OUT ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.75 V                       ; 0.000242 V                   ; 2.86 V              ; -0.0805 V           ; 0.358 V                              ; 0.156 V                              ; 3.01e-10 s                  ; 4.34e-10 s                  ; No                         ; No                         ; 2.75 V                      ; 0.000242 V                  ; 2.86 V             ; -0.0805 V          ; 0.358 V                             ; 0.156 V                             ; 3.01e-10 s                 ; 4.34e-10 s                 ; No                        ; No                        ;
++---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                 ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; From Clock               ; To Clock                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; CLOCK_50                 ; clktick_16:GEN_10K|tick  ; 1        ; 0        ; 0        ; 0        ;
+; clktick_16:GEN_10K|tick  ; CLOCK_50                 ; 199      ; 162      ; 0        ; 0        ;
+; CLOCK_50                 ; CLOCK_50                 ; 2621     ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 1349     ; 1        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; CLOCK_50                 ; 5        ; 1        ; 0        ; 0        ;
+; CLOCK_50                 ; spi2adc:SPI_ADC|clk_1MHz ; 3        ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; 56       ; 10       ; 20       ; 9        ;
+; CLOCK_50                 ; spi2dac:SPI_DAC|clk_1MHz ; 26       ; 0        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; 65       ; 0        ; 0        ; 0        ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                  ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; From Clock               ; To Clock                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; CLOCK_50                 ; clktick_16:GEN_10K|tick  ; 1        ; 0        ; 0        ; 0        ;
+; clktick_16:GEN_10K|tick  ; CLOCK_50                 ; 199      ; 162      ; 0        ; 0        ;
+; CLOCK_50                 ; CLOCK_50                 ; 2621     ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 1349     ; 1        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; CLOCK_50                 ; 5        ; 1        ; 0        ; 0        ;
+; CLOCK_50                 ; spi2adc:SPI_ADC|clk_1MHz ; 3        ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; 56       ; 10       ; 20       ; 9        ;
+; CLOCK_50                 ; spi2dac:SPI_DAC|clk_1MHz ; 26       ; 0        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; 65       ; 0        ; 0        ; 0        ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary                    ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 1     ; 1    ;
+; Unconstrained Input Port Paths  ; 1     ; 1    ;
+; Unconstrained Output Ports      ; 28    ; 28   ;
+; Unconstrained Output Port Paths ; 76    ; 76   ;
++---------------------------------+-------+------+
+
+
++--------------------------------------------------------------------------+
+; Clock Status Summary                                                     ;
++--------------------------+--------------------------+------+-------------+
+; Target                   ; Clock                    ; Type ; Status      ;
++--------------------------+--------------------------+------+-------------+
+; CLOCK_50                 ; CLOCK_50                 ; Base ; Constrained ;
+; clktick_16:GEN_10K|tick  ; clktick_16:GEN_10K|tick  ; Base ; Constrained ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; Base ; Constrained ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; Base ; Constrained ;
++--------------------------+--------------------------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports                                                                         ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment                                                                              ;
++------------+--------------------------------------------------------------------------------------+
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports                                                                          ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment                                                                               ;
++-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX0[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX1[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime TimeQuest Timing Analyzer
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Fri Dec 02 11:27:08 2016
+Info: Command: quartus_sta ex18 -c ex18
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex18.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+    Info (332105): create_clock -period 1.000 -name spi2adc:SPI_ADC|clk_1MHz spi2adc:SPI_ADC|clk_1MHz
+    Info (332105): create_clock -period 1.000 -name clktick_16:GEN_10K|tick clktick_16:GEN_10K|tick
+    Info (332105): create_clock -period 1.000 -name spi2dac:SPI_DAC|clk_1MHz spi2dac:SPI_DAC|clk_1MHz
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -10.396
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):   -10.396           -1930.765 CLOCK_50 
+    Info (332119):    -4.481             -76.352 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -4.340             -79.060 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -3.446              -3.446 clktick_16:GEN_10K|tick 
+Info (332146): Worst-case hold slack is 0.177
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.177               0.000 CLOCK_50 
+    Info (332119):     0.433               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.752               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     2.922               0.000 clktick_16:GEN_10K|tick 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.166
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.166           -2106.846 CLOCK_50 
+    Info (332119):    -0.724             -35.901 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.724             -26.588 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -0.724              -1.136 clktick_16:GEN_10K|tick 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -10.556
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):   -10.556           -1900.830 CLOCK_50 
+    Info (332119):    -4.649             -73.671 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -4.477             -81.791 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -3.689              -3.689 clktick_16:GEN_10K|tick 
+Info (332146): Worst-case hold slack is -0.251
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.251              -2.476 CLOCK_50 
+    Info (332119):     0.516               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.750               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     3.173               0.000 clktick_16:GEN_10K|tick 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.166
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.166           -2105.141 CLOCK_50 
+    Info (332119):    -0.724             -35.136 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.724             -26.303 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -0.724              -1.131 clktick_16:GEN_10K|tick 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -4.377
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -4.377            -721.833 CLOCK_50 
+    Info (332119):    -1.710             -26.172 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -1.537             -25.590 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -1.128              -1.128 clktick_16:GEN_10K|tick 
+Info (332146): Worst-case hold slack is -0.177
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.177              -0.991 CLOCK_50 
+    Info (332119):     0.172               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.240               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     1.116               0.000 clktick_16:GEN_10K|tick 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174           -1313.734 CLOCK_50 
+    Info (332119):     0.082               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     0.104               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.126               0.000 clktick_16:GEN_10K|tick 
+Info: Analyzing Fast 1100mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -3.956
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.956            -615.142 CLOCK_50 
+    Info (332119):    -1.593             -24.610 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -1.474             -23.182 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -1.111              -1.111 clktick_16:GEN_10K|tick 
+Info (332146): Worst-case hold slack is -0.307
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.307             -14.229 CLOCK_50 
+    Info (332119):     0.157               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.212               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     1.109               0.000 clktick_16:GEN_10K|tick 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -2.174
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -2.174           -1314.254 CLOCK_50 
+    Info (332119):     0.104               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     0.122               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.131               0.000 clktick_16:GEN_10K|tick 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 1312 megabytes
+    Info: Processing ended: Fri Dec 02 11:27:15 2016
+    Info: Elapsed time: 00:00:07
+    Info: Total CPU time (on all processors): 00:00:08
+
+
diff --git a/part_4/ex18/output_files/ex18.sta.summary b/part_4/ex18/output_files/ex18.sta.summary
new file mode 100755
index 0000000..7481f54
--- /dev/null
+++ b/part_4/ex18/output_files/ex18.sta.summary
@@ -0,0 +1,197 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -10.396
+TNS   : -1930.765
+
+Type  : Slow 1100mV 85C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -4.481
+TNS   : -76.352
+
+Type  : Slow 1100mV 85C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -4.340
+TNS   : -79.060
+
+Type  : Slow 1100mV 85C Model Setup 'clktick_16:GEN_10K|tick'
+Slack : -3.446
+TNS   : -3.446
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.177
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.433
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.752
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'clktick_16:GEN_10K|tick'
+Slack : 2.922
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -3.166
+TNS   : -2106.846
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -0.724
+TNS   : -35.901
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -0.724
+TNS   : -26.588
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'clktick_16:GEN_10K|tick'
+Slack : -0.724
+TNS   : -1.136
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -10.556
+TNS   : -1900.830
+
+Type  : Slow 1100mV 0C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -4.649
+TNS   : -73.671
+
+Type  : Slow 1100mV 0C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -4.477
+TNS   : -81.791
+
+Type  : Slow 1100mV 0C Model Setup 'clktick_16:GEN_10K|tick'
+Slack : -3.689
+TNS   : -3.689
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : -0.251
+TNS   : -2.476
+
+Type  : Slow 1100mV 0C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.516
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.750
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'clktick_16:GEN_10K|tick'
+Slack : 3.173
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -3.166
+TNS   : -2105.141
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -0.724
+TNS   : -35.136
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -0.724
+TNS   : -26.303
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'clktick_16:GEN_10K|tick'
+Slack : -0.724
+TNS   : -1.131
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -4.377
+TNS   : -721.833
+
+Type  : Fast 1100mV 85C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -1.710
+TNS   : -26.172
+
+Type  : Fast 1100mV 85C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -1.537
+TNS   : -25.590
+
+Type  : Fast 1100mV 85C Model Setup 'clktick_16:GEN_10K|tick'
+Slack : -1.128
+TNS   : -1.128
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : -0.177
+TNS   : -0.991
+
+Type  : Fast 1100mV 85C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.172
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.240
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'clktick_16:GEN_10K|tick'
+Slack : 1.116
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1313.734
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.082
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.104
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'clktick_16:GEN_10K|tick'
+Slack : 0.126
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -3.956
+TNS   : -615.142
+
+Type  : Fast 1100mV 0C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -1.593
+TNS   : -24.610
+
+Type  : Fast 1100mV 0C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -1.474
+TNS   : -23.182
+
+Type  : Fast 1100mV 0C Model Setup 'clktick_16:GEN_10K|tick'
+Slack : -1.111
+TNS   : -1.111
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : -0.307
+TNS   : -14.229
+
+Type  : Fast 1100mV 0C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.157
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.212
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'clktick_16:GEN_10K|tick'
+Slack : 1.109
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1314.254
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.104
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.122
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'clktick_16:GEN_10K|tick'
+Slack : 0.131
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_4/ex18/verilog_files/FIFO.qip b/part_4/ex18/verilog_files/FIFO.qip
new file mode 100755
index 0000000..5559867
--- /dev/null
+++ b/part_4/ex18/verilog_files/FIFO.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "FIFO.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FIFO_bb.v"]
diff --git a/part_4/ex18/verilog_files/FIFO.v b/part_4/ex18/verilog_files/FIFO.v
new file mode 100755
index 0000000..07ece20
--- /dev/null
+++ b/part_4/ex18/verilog_files/FIFO.v
@@ -0,0 +1,153 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: FIFO.v
+// Megafunction Name(s):
+// 			scfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module FIFO (
+	clock,
+	data,
+	rdreq,
+	wrreq,
+	full,
+	q);
+
+	input	  clock;
+	input	[9:0]  data;
+	input	  rdreq;
+	input	  wrreq;
+	output	  full;
+	output	[9:0]  q;
+
+	wire  sub_wire0;
+	wire [9:0] sub_wire1;
+	wire  full = sub_wire0;
+	wire [9:0] q = sub_wire1[9:0];
+
+	scfifo	scfifo_component (
+				.clock (clock),
+				.data (data),
+				.rdreq (rdreq),
+				.wrreq (wrreq),
+				.full (sub_wire0),
+				.q (sub_wire1),
+				.aclr (),
+				.almost_empty (),
+				.almost_full (),
+				.eccstatus (),
+				.empty (),
+				.sclr (),
+				.usedw ());
+	defparam
+		scfifo_component.add_ram_output_register = "OFF",
+		scfifo_component.intended_device_family = "Cyclone V",
+		scfifo_component.lpm_numwords = 8192,
+		scfifo_component.lpm_showahead = "OFF",
+		scfifo_component.lpm_type = "scfifo",
+		scfifo_component.lpm_width = 10,
+		scfifo_component.lpm_widthu = 13,
+		scfifo_component.overflow_checking = "ON",
+		scfifo_component.underflow_checking = "ON",
+		scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "8192"
+// Retrieval info: PRIVATE: Empty NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "10"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "10"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex18/verilog_files/FIFO_bb.v b/part_4/ex18/verilog_files/FIFO_bb.v
new file mode 100755
index 0000000..7e480c2
--- /dev/null
+++ b/part_4/ex18/verilog_files/FIFO_bb.v
@@ -0,0 +1,116 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: FIFO.v
+// Megafunction Name(s):
+// 			scfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module FIFO (
+	clock,
+	data,
+	rdreq,
+	wrreq,
+	full,
+	q);
+
+	input	  clock;
+	input	[9:0]  data;
+	input	  rdreq;
+	input	  wrreq;
+	output	  full;
+	output	[9:0]  q;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "8192"
+// Retrieval info: PRIVATE: Empty NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "10"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "10"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL "data[9..0]"
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+// Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 10 0 data 0 0 10 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex18/verilog_files/add3_ge5.v b/part_4/ex18/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..0daf78a
--- /dev/null
+++ b/part_4/ex18/verilog_files/add3_ge5.v
@@ -0,0 +1,31 @@
+//------------------------------
+// Module name: add3_ge5
+// Function: Add 3 to input if it is 5 or above
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     21 Jan 2014
+//------------------------------
+
+module add3_ge5(w,a); 
+	input [3:0] w; 
+	output [3:0] a; 
+	reg [3:0] a; 
+ 
+	always @ (w) 
+		case (w) 
+			4'b0000: a <= 4'b0000; 
+			4'b0001: a <= 4'b0001; 
+			4'b0010: a <= 4'b0010; 
+			4'b0011: a <= 4'b0011; 
+			4'b0100: a <= 4'b0100; 
+			4'b0101: a <= 4'b1000; 
+			4'b0110: a <= 4'b1001; 
+			4'b0111: a <= 4'b1010; 
+			4'b1000: a <= 4'b1011; 
+			4'b1001: a <= 4'b1100;
+			4'b1010: a <= 4'b1101;	
+			4'b1011: a <= 4'b1110;	
+			4'b1100: a <= 4'b1111;	
+			default: a <= 4'b0000; // a cannot be 13 or larger, else overflow
+		endcase 
+endmodule 
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/bin2bcd_16.v b/part_4/ex18/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..b25d0bd
--- /dev/null
+++ b/part_4/ex18/verilog_files/bin2bcd_16.v
@@ -0,0 +1,109 @@
+//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+//            .... it uses a shift-and-add3 algorithm
+// Creator:  Peter Cheung
+// Version:  2.0  (Correct mistake - problem with numbers 0x5000 or larger)
+// Date:     24 Nov 2016
+//------------------------------
+//   For more explanation of how this work, see 
+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+	input [15:0]	B;		// binary input number
+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD
+	
+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+	wire [3:0]	w26,w27,w28,w29,w30,w31,w32,w33,w34,w35;
+	wire [3:0]	a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+	wire [3:0]	a26,a27,a28,a29,a30,a31,a32,a33,a34,a35;
+
+	// Instantiate a tree of add3-if-greater than or equal to 5 cells
+	//  ... input is w_n, and output is a_n
+	add3_ge5 A1 (w1,a1);
+	add3_ge5 A2 (w2,a2);
+	add3_ge5 A3 (w3,a3);
+	add3_ge5 A4 (w4,a4);
+	add3_ge5 A5 (w5,a5);
+	add3_ge5 A6 (w6,a6);
+	add3_ge5 A7 (w7,a7);
+	add3_ge5 A8 (w8,a8);
+	add3_ge5 A9 (w9,a9);
+	add3_ge5 A10 (w10,a10);
+	add3_ge5 A11 (w11,a11);
+	add3_ge5 A12 (w12,a12);
+	add3_ge5 A13 (w13,a13);
+	add3_ge5 A14 (w14,a14);
+	add3_ge5 A15 (w15,a15);
+	add3_ge5 A16 (w16,a16);
+	add3_ge5 A17 (w17,a17);
+	add3_ge5 A18 (w18,a18);
+	add3_ge5 A19 (w19,a19);
+	add3_ge5 A20 (w20,a20);
+	add3_ge5 A21 (w21,a21);
+	add3_ge5 A22 (w22,a22);
+	add3_ge5 A23 (w23,a23);
+	add3_ge5 A24 (w24,a24);
+	add3_ge5 A25 (w25,a25);
+	add3_ge5 A26 (w26,a26);
+	add3_ge5 A27 (w27,a27);
+	add3_ge5 A28 (w28,a28);
+	add3_ge5 A29 (w29,a29);
+	add3_ge5 A30 (w30,a30);
+	add3_ge5 A31 (w31,a31);
+	add3_ge5 A32 (w32,a32);
+	add3_ge5 A33 (w33,a33);
+	add3_ge5 A34 (w34,a34);
+	add3_ge5 A35 (w35,a35);
+		
+	// wire the tree of add3 modules together
+	assign  w1 = {1'b0,B[15:13]};		// w_n is the input port to module a_n
+	assign  w2 = {a1[2:0], B[12]};		
+	assign  w3 = {a2[2:0], B[11]};		
+	assign  w4 = {1'b0,a1[3],a2[3],a3[3]};
+	assign  w5 = {a3[2:0], B[10]};
+	assign  w6 = {a4[2:0], a5[3]};
+	assign  w7 = {a5[2:0], B[9]};
+	assign  w8 = {a6[2:0], a7[3]};
+	assign  w9 = {a7[2:0], B[8]};
+	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};
+	assign  w11 = {a8[2:0], a9[3]};
+	assign  w12 = {a9[2:0], B[7]};
+	assign  w13 = {a10[2:0], a11[3]};
+	assign  w14 = {a11[2:0], a12[3]};
+	assign  w15 = {a12[2:0], B[6]};
+	assign  w16 = {a13[2:0], a14[3]};
+	assign  w17 = {a14[2:0], a15[3]};
+	assign  w18 = {a15[2:0], B[5]};
+	assign  w19 = {1'b0, a10[3], a13[3], a16[3]};
+	assign  w20 = {a16[2:0], a17[3]};
+	assign  w21 = {a17[2:0], a18[3]};
+	assign  w22 = {a18[2:0], B[4]};
+	assign  w23 = {a19[2:0], a20[3]};
+	assign  w24 = {a20[2:0], a21[3]};
+	assign  w25 = {a21[2:0], a22[3]};
+	assign  w26 = {a22[2:0], B[3]};
+	assign  w27 = {a23[2:0], a24[3]};
+	assign  w28 = {a24[2:0], a25[3]};
+	assign  w29 = {a25[2:0], a26[3]};
+	assign  w30 = {a26[2:0], B[2]};
+	assign  w31 = {1'b0,a19[3], a23[3], a27[3]};
+	assign  w32 = {a27[2:0], a28[3]};
+	assign  w33 = {a28[2:0], a29[3]};
+	assign  w34 = {a29[2:0], a30[3]};
+	assign  w35 = {a30[2:0], B[1]};
+	
+	// connect up to four BCD digit outputs	
+	assign BCD_0 = {a35[2:0],B[0]};
+	assign BCD_1 = {a34[2:0],a35[3]};
+	assign BCD_2 = {a33[2:0],a34[3]};
+	assign BCD_3 = {a32[2:0],a33[3]};
+	assign BCD_4 = {a31[2:0],a32[3]};	
+endmodule
+
+	
+	
+
diff --git a/part_4/ex18/verilog_files/clktick_16.v b/part_4/ex18/verilog_files/clktick_16.v
new file mode 100755
index 0000000..e6b99eb
--- /dev/null
+++ b/part_4/ex18/verilog_files/clktick_16.v
@@ -0,0 +1,42 @@
+// Design Name : clktick_16
+// File Name : clktick.v
+// Function : divide an input clock signal by n+1
+//-----------------------------------------------------
+
+module clktick_16 (
+  clkin, 	// Clock input to the design
+  enable,	// enable clk divider
+  N,			// Clock division factor is N+1
+  tick		// pulse_out goes high for one cycle (n+1) clock cycles
+); 			// 	End of port list
+
+parameter	N_BIT = 16;
+//-------------Input Ports-----------------------------
+input clkin;
+input enable;
+input [N_BIT-1:0] N;
+
+//-------------Output Ports----------------------------
+output 	tick;
+
+//-------------Output Ports Data Type------------------
+// Output port can be a storage element (reg) or a wire
+reg [N_BIT-1:0] count;
+reg			tick;
+
+initial		tick = 1'b0;
+
+//------------ Main Body of the module ------------------------
+
+	always @ (posedge clkin)  
+		if (enable == 1'b1)
+			if (count == 0)	begin
+				tick <= 1'b1;
+				count <= N;
+				end
+			else	begin
+				tick <= 1'b0;
+				count <= count - 1'b1;
+				end
+		
+endmodule // End of Module clktick
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/d_ff.v b/part_4/ex18/verilog_files/d_ff.v
new file mode 100755
index 0000000..65aec4d
--- /dev/null
+++ b/part_4/ex18/verilog_files/d_ff.v
@@ -0,0 +1,11 @@
+module d_ff(clk, in, out);
+
+	input clk, in;
+	output out;
+	wire in;
+	reg out;
+
+	always @ (posedge clk)
+		out <= in;
+
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/d_ff.v.bak b/part_4/ex18/verilog_files/d_ff.v.bak
new file mode 100755
index 0000000..1463387
--- /dev/null
+++ b/part_4/ex18/verilog_files/d_ff.v.bak
@@ -0,0 +1,6 @@
+module d_ff(clk, in, out);
+
+	always @ (posedge clk)
+		in <= out;
+
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/delay_ram.v b/part_4/ex18/verilog_files/delay_ram.v
new file mode 100755
index 0000000..23d49af
--- /dev/null
+++ b/part_4/ex18/verilog_files/delay_ram.v
@@ -0,0 +1,220 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: delay_ram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module delay_ram (
+	clock,
+	data,
+	rdaddress,
+	rden,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[8:0]  data;
+	input	[12:0]  rdaddress;
+	input	  rden;
+	input	[12:0]  wraddress;
+	input	  wren;
+	output	[8:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [8:0] sub_wire0;
+	wire [8:0] q = sub_wire0[8:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.rden_b (rden),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({9{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 8192,
+		altsyncram_component.numwords_b = 8192,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "CLOCK0",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.rdcontrol_reg_b = "CLOCK0",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 13,
+		altsyncram_component.widthad_b = 13,
+		altsyncram_component.width_a = 9,
+		altsyncram_component.width_b = 9,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
+// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
+// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex18/verilog_files/div_by_2.v b/part_4/ex18/verilog_files/div_by_2.v
new file mode 100755
index 0000000..11b8e75
--- /dev/null
+++ b/part_4/ex18/verilog_files/div_by_2.v
@@ -0,0 +1,8 @@
+module div_by_2(in, out);
+
+	input signed [9:0] in;
+	output signed [9:0] out;
+	
+	assign out = in >>> 1;
+	
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/div_by_4.v.bak b/part_4/ex18/verilog_files/div_by_4.v.bak
new file mode 100755
index 0000000..8ceab41
--- /dev/null
+++ b/part_4/ex18/verilog_files/div_by_4.v.bak
@@ -0,0 +1,8 @@
+module div_by_4(in, out);
+
+	input in;
+	output out;
+	
+	assign out = in >> 2;
+	
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/echo_synth.v.bak b/part_4/ex18/verilog_files/echo_synth.v.bak
new file mode 100755
index 0000000..91d95dc
--- /dev/null
+++ b/part_4/ex18/verilog_files/echo_synth.v.bak
@@ -0,0 +1,27 @@
+module processor (sysclk, data_in, data_out);
+
+	input				sysclk;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	// This part should include your own processing hardware 
+	// ... that takes x to produce y
+	// ... In this case, it is ALL PASS.
+	assign y = x;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/hex_to_7seg.v b/part_4/ex18/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..1c39f02
--- /dev/null
+++ b/part_4/ex18/verilog_files/hex_to_7seg.v
@@ -0,0 +1,38 @@
+//------------------------------
+// Module name: hex_to_7seg
+// Function: convert 4-bit hex value to drive 7 segment display
+//           output is low active - using case statement
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     23 Oct 2011
+//------------------------------
+
+module hex_to_7seg	(out,in);
+
+	output	[6:0]	out;    // low-active output to drive 7 segment display
+	input	[3:0]	in;		// 4-bit binary input of a hexademical number
+	
+	reg		[6:0]	out;	// make out a variable for use in procedural assignment
+	
+	always @ (in)
+	  case (in)
+		4'h0: out = 7'b1000000;
+		4'h1: out = 7'b1111001;		// -- 0 ---
+		4'h2: out = 7'b0100100; 	// |	  |
+		4'h3: out = 7'b0110000; 	// 5      1
+		4'h4: out = 7'b0011001; 	// |	  |
+		4'h5: out = 7'b0010010; 	// -- 6 ---
+		4'h6: out = 7'b0000010; 	// |	  |
+		4'h7: out = 7'b1111000; 	// 4      2
+		4'h8: out = 7'b0000000; 	// |	  |
+		4'h9: out = 7'b0011000; 	// -- 3 ---
+		4'ha: out = 7'b0001000;
+		4'hb: out = 7'b0000011;
+		4'hc: out = 7'b1000110;
+		4'hd: out = 7'b0100001;
+		4'he: out = 7'b0000110;
+		4'hf: out = 7'b0001110;
+	  endcase
+endmodule
+
+
diff --git a/part_4/ex18/verilog_files/mult_echo_synth.v b/part_4/ex18/verilog_files/mult_echo_synth.v
new file mode 100755
index 0000000..6589fd8
--- /dev/null
+++ b/part_4/ex18/verilog_files/mult_echo_synth.v
@@ -0,0 +1,34 @@
+module processor (sysclk, tick, data_in, data_out);
+
+	input				sysclk, tick;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+	wire [9:0]		tmp_data, echoed_data;
+	wire is_full, and_if, from_dff;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	FIFO fifo(sysclk, y, and_if, tick, is_full, tmp_data);
+	
+	d_ff d(tick, is_full, from_dff);
+	
+	assign and_if = tick & from_dff;
+	
+	div_by_2(tmp_data, echoed_data);
+		
+	assign y = x - echoed_data;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/mult_echo_synth.v.bak b/part_4/ex18/verilog_files/mult_echo_synth.v.bak
new file mode 100755
index 0000000..d5507b5
--- /dev/null
+++ b/part_4/ex18/verilog_files/mult_echo_synth.v.bak
@@ -0,0 +1,34 @@
+module processor (sysclk, tick, data_in, data_out);
+
+	input				sysclk, tick;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+	wire [9:0]		tmp_data, echoed_data;
+	wire is_full, and_if, from_dff;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	FIFO fifo(sysclk, x, and_if, tick, is_full, tmp_data);
+	
+	d_ff d(tick, is_full, from_dff);
+	
+	assign and_if = tick & from_dff;
+	
+	div_by_2(tmp_data, echoed_data);
+		
+	assign y = x + echoed_data;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/multiply_k.v b/part_4/ex18/verilog_files/multiply_k.v
new file mode 100755
index 0000000..8292b58
--- /dev/null
+++ b/part_4/ex18/verilog_files/multiply_k.v
@@ -0,0 +1,107 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: multiply_k.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module multiply_k (
+	dataa,
+	result);
+
+	input	[8:0]  dataa;
+	output	[19:0]  result;
+
+	wire [19:0] sub_wire0;
+	wire [10:0] sub_wire1 = 11'h666;
+	wire [19:0] result = sub_wire0[19:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (sub_wire1),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 9,
+		lpm_mult_component.lpm_widthb = 11,
+		lpm_mult_component.lpm_widthp = 20;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "1638"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "9"
+// Retrieval info: PRIVATE: WidthB NUMERIC "11"
+// Retrieval info: PRIVATE: WidthP NUMERIC "20"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20"
+// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
+// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]"
+// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
+// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0
+// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_4/ex18/verilog_files/pulse_gen.v b/part_4/ex18/verilog_files/pulse_gen.v
new file mode 100755
index 0000000..d82fe49
--- /dev/null
+++ b/part_4/ex18/verilog_files/pulse_gen.v
@@ -0,0 +1,43 @@
+//------------------------------
+// Module name: pulse_gen (Moore)
+// Function: Generate one clock pulse on +ve edge of input
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     29 Jan 2014
+//------------------------------
+
+module pulse_gen(pulse, in, clk);
+
+	output 			pulse;	// output pulse lasting one clk cycle
+	input 			in;		// input, +ve edge to be detected
+	input 			clk;		// clock signal
+
+	reg [1:0]	state;
+	reg	pulse;
+	
+	parameter	IDLE = 2'b0;	// state coding for IDLE state
+	parameter	IN_HIGH = 2'b01;
+	parameter	WAIT_LOW = 2'b10;  
+	
+	initial state = IDLE;
+	
+	always @ (posedge clk) 
+		begin	
+			pulse <= 0;		 // default output
+			case (state)
+			IDLE: 	if (in == 1'b1) begin
+							state <= IN_HIGH;	pulse <= 1'b1; end
+						else 
+							state <= IDLE; 
+			IN_HIGH: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						else 
+							state <= IDLE; 
+			WAIT_LOW: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						 else  
+							state <= IDLE;
+			default: ;
+			endcase
+		end			//... always
+endmodule
diff --git a/part_4/ex18/verilog_files/pwm.v b/part_4/ex18/verilog_files/pwm.v
new file mode 100755
index 0000000..c3b34d9
--- /dev/null
+++ b/part_4/ex18/verilog_files/pwm.v
@@ -0,0 +1,25 @@
+module pwm (clk, data_in, load, pwm_out);
+
+	input				clk;			// system clock
+	input [9:0] 	data_in;		// input data for conversion
+	input 			load;			// high pulse to load new data
+	output			pwm_out;		// PWM output
+
+	reg [9:0]		d;				// internal register
+	reg [9:0]		count;		// internal 10-bit counter
+	reg				pwm_out;
+
+	always @ (posedge clk)
+		if (load == 1'b1) d <= data_in;
+	
+	initial count = 10'b0;	
+	
+	always @ (posedge clk) begin
+		count <= count + 1'b1;
+		if (count > d)
+			pwm_out <= 1'b0;
+		else	
+			pwm_out <= 1'b1;
+		end
+
+endmodule
diff --git a/part_4/ex18/verilog_files/spi2adc.v b/part_4/ex18/verilog_files/spi2adc.v
new file mode 100755
index 0000000..3878f71
--- /dev/null
+++ b/part_4/ex18/verilog_files/spi2adc.v
@@ -0,0 +1,150 @@
+//------------------------------
+// Module name: spi2adc
+// Function: SPI interface for MCP3002 ADC
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     24 Jan 2014
+//------------------------------
+
+module spi2adc (sysclk, start, channel, data_from_adc, data_valid, 
+						sdata_to_adc, adc_cs, adc_sck, sdata_from_adc);
+
+	input	sysclk;			// 50MHz system clock of DE0
+	input	start;			// Pulse to start ADC, minimum wide = clock period
+	input	channel;			// channel 0 or 1 to be converted
+	output [9:0] data_from_adc;	// 10-bit ADC result
+	output data_valid;	// High indicates that converted data valid
+	output sdata_to_adc;	// Serial commands send to adc chip
+	output adc_cs;			// chip select - low when converting
+	output adc_sck;		// SPI clock - active during conversion
+	input sdata_from_adc;	// Converted serial data from ADC, MSB first
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire	sysclk, start, sdata_from_adc;
+
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg [9:0]	data_from_adc;
+	reg			adc_cs;
+	wire			sdata_to_adc, adc_sck, data_valid;
+	
+//-------------Configuration parameters for ADC --------
+	parameter	SGL=1'b1;	// 0:diff i/p, 1:single-ended
+	parameter	MSBF=1'b1;	// 0:LSB first, 1:MSB first
+			
+// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... to start.  Initialise to make simulation easier
+	end
+		
+	always @ (posedge sysclk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+// ---- end internal clock generator ----------
+
+// ---- Detect start is asserted with a small state machine
+	// .... FF set on positive edge of start
+	// .... reset when adc_cs goes high again
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			adc_start;
+	
+	initial begin
+		sr_state = IDLE;
+		adc_start = 1'b0;	// set while sending data to ADC
+		end
+	
+	always @ (posedge sysclk)
+		case (sr_state)
+			IDLE:	if (start==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						adc_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (adc_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (adc_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						adc_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+//------- End circuit to detect start and end of conversion	
+
+	
+// spi controller designed as a state machine
+// .... with 16 states (idle, and S1-S15 indicated by state value
+
+	reg [4:0] 	state;
+	reg  	adc_done, adc_din, shift_ena;
+	
+	initial	begin	
+		state = 5'b0; adc_cs = 1'b1; adc_done = 1'b0; 
+		adc_din = 1'b0; shift_ena <= 1'b0;
+		end
+		
+	always @(posedge clk_1MHz)  begin
+	
+	// default outputs and state transition
+		adc_cs <= 1'b0;  adc_done <= 1'b0;  adc_din <= 1'b0; shift_ena <= 1'b0;
+		state <= state + 1'b1;
+		case (state)
+			5'd0:	begin
+						if (adc_start==1'b0) begin
+							state <= 5'd0;			// still idle
+							adc_cs <= 1'b1;		// chip select not active
+							end
+						else begin
+							state <= 5'd1;			// start converting
+							adc_din <= 1'b1;		// start bit is 1
+							end
+					end
+			5'd1:	adc_din <= SGL;				// SGL bit
+			5'd2:	adc_din <= channel;			// CH bit
+			5'd3:	adc_din <= MSBF;				// MSB first bit
+			5'd4: shift_ena <= 1'b1;  			// start shifting data from adc
+			5'd15: begin
+						shift_ena <= 1'b0;
+						adc_done <= 1'b1;
+					 end
+			5'd16: begin  
+						adc_cs <= 1'b1;		// last state - disable chip select
+						state <= 5'd0;  		// go back to idle state
+					 end
+			default: 				
+						shift_ena <= 1'b1;	// unspecified states are covered by default above
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [9:0] shift_reg;
+	initial	begin
+			shift_reg = 10'b0;
+			data_from_adc = 10'b0;
+			end
+	
+	always @(negedge clk_1MHz)
+		if((adc_cs==1'b0)&&(shift_ena==1'b1))		// start shifting data_in
+				shift_reg <= {shift_reg[8:0],sdata_from_adc};
+	
+	// Latch converted output data
+	always @(posedge clk_1MHz)
+		if(adc_done) 					
+				data_from_adc = shift_reg;
+
+	// Assign outputs to drive SPI interface to DAC
+		assign adc_sck = !clk_1MHz & !adc_cs;
+		assign sdata_to_adc = adc_din;
+		assign data_valid = adc_cs;
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex18/verilog_files/spi2dac.v b/part_4/ex18/verilog_files/spi2dac.v
new file mode 100755
index 0000000..ccfb4e8
--- /dev/null
+++ b/part_4/ex18/verilog_files/spi2dac.v
@@ -0,0 +1,128 @@
+//------------------------------
+// Module name: spi2dac
+// Function: SPI interface for MPC4911 DAC
+// Creator:  Peter Cheung
+// Version:  1.3
+// Date:     8 Nov 2016
+//------------------------------
+
+module spi2dac (clk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld);
+
+	input	clk;				// 50MHz system clock of DE0
+	input	[9:0]	data_in;	// input data to DAC
+	input	load;				// Pulse to load data to dac
+	output dac_sdi;		// SPI serial data out
+	output dac_cs;			// chip select - low when sending data to dac
+	output dac_sck;		// SPI clock, 16 cycles at half clk freq
+	output dac_ld;
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire			clk, load;
+	wire [9:0]	data_in;
+	
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg			dac_cs, dac_ld;
+	wire			dac_sck, dac_sdi;
+	
+	parameter	BUF=1'b1;		// 0:no buffer, 1:Vref buffered
+	parameter	GA_N=1'b1;		// 0:gain = 2x, 1:gain = 1x
+	parameter	SHDN_N=1'b1;	// 0:power down, 1:dac active
+	
+	wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N};  // wire to VDD or GND
+	
+	// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... Initialise when FPGA is configured
+	end
+		
+	always @ (posedge clk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+	// ---- end internal clock generator ----------
+
+	// ---- Detect posedge of load with a small state machine
+	// .... FF set on posedge of load
+	// .... reset when dac_cs goes high at the end of DAC output cycle
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			dac_start;		 // set if a DAC write is detected
+	
+	initial begin
+		sr_state = IDLE;
+		dac_start = 1'b0;	// set while sending data to DAC
+		end
+	
+	always @ (posedge clk)
+		case (sr_state)
+			IDLE:	if (load==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						dac_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (dac_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						dac_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+	//------- End circuit to detect start and end of conversion	
+
+	//------- spi controller designed as a state machine
+	// .... with 17 states (idle, and S1-S16 
+	// .... for the 16 cycles each sending 1-bit to dac)
+	reg [4:0] 	state;
+	
+	initial	begin	
+		state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; 
+		end
+		
+	always @(posedge clk_1MHz)  begin
+		// default outputs and state transition
+		dac_cs <= 1'b0; dac_ld <= 1'b1; 
+		state <= state + 1'b1;	// move to next state by default
+		case (state)
+			5'd0:	if (dac_start == 1'b0)  begin  
+						state <= 5'd0; 				// still waiting
+						dac_cs <= 1'b1; 
+						end
+			5'd16: begin  
+						dac_cs <= 1'b1; dac_ld <= 1'b0; 
+						state <= 5'd0;  // go back to idle state
+					end
+			default:   begin					// all other states
+					dac_cs <= 1'b0; dac_ld <= 1'b1; 
+					state <= state + 1'b1;	// default state transition
+					end
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [15:0] shift_reg;
+	initial	begin	
+		shift_reg = 16'b0; 
+		end
+
+	always @(posedge clk_1MHz)
+		if((dac_start==1'b1)&&(dac_cs==1'b1))		// parallel load data to shift reg
+			shift_reg <= {cmd,data_in,2'b00};
+		else 													// .. else start shifting
+			shift_reg <= {shift_reg[14:0],1'b0};
+	
+	// Assign outputs to drive SPI interface to DAC
+			assign dac_sck = !clk_1MHz&!dac_cs;
+			assign dac_sdi = shift_reg[15];
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/c5_pin_model_dump.txt b/part_4/ex19/c5_pin_model_dump.txt
new file mode 100755
index 0000000..a895a64
--- /dev/null
+++ b/part_4/ex19/c5_pin_model_dump.txt
@@ -0,0 +1,118 @@
+io_4iomodule_c5_index: 55gpio_index: 2
+io_4iomodule_c5_index: 54gpio_index: 465
+io_4iomodule_c5_index: 33gpio_index: 6
+io_4iomodule_c5_index: 51gpio_index: 461
+io_4iomodule_c5_index: 27gpio_index: 10
+io_4iomodule_c5_index: 57gpio_index: 457
+io_4iomodule_c5_index: 34gpio_index: 14
+io_4iomodule_c5_index: 28gpio_index: 453
+io_4iomodule_c5_index: 26gpio_index: 19
+io_4iomodule_c5_index: 47gpio_index: 449
+io_4iomodule_c5_index: 29gpio_index: 22
+io_4iomodule_c5_index: 3gpio_index: 445
+io_4iomodule_c5_index: 16gpio_index: 27
+io_4iomodule_c5_index: 6gpio_index: 441
+io_4iomodule_c5_index: 50gpio_index: 30
+io_4iomodule_c5_index: 35gpio_index: 437
+io_4iomodule_c5_index: 7gpio_index: 35
+io_4iomodule_c5_index: 53gpio_index: 433
+io_4iomodule_c5_index: 12gpio_index: 38
+io_4iomodule_c5_index: 1gpio_index: 429
+io_4iomodule_c5_index: 22gpio_index: 43
+io_4iomodule_c5_index: 8gpio_index: 425
+io_4iomodule_c5_index: 20gpio_index: 46
+io_4iomodule_c5_index: 30gpio_index: 421
+io_4iomodule_c5_index: 2gpio_index: 51
+io_4iomodule_c5_index: 31gpio_index: 417
+io_4iomodule_c5_index: 39gpio_index: 54
+io_4iomodule_c5_index: 18gpio_index: 413
+io_4iomodule_c5_index: 10gpio_index: 59
+io_4iomodule_c5_index: 42gpio_index: 409
+io_4iomodule_c5_index: 5gpio_index: 62
+io_4iomodule_c5_index: 24gpio_index: 405
+io_4iomodule_c5_index: 37gpio_index: 67
+io_4iomodule_c5_index: 13gpio_index: 401
+io_4iomodule_c5_index: 0gpio_index: 70
+io_4iomodule_c5_index: 44gpio_index: 397
+io_4iomodule_c5_index: 38gpio_index: 75
+io_4iomodule_c5_index: 52gpio_index: 393
+io_4iomodule_c5_index: 32gpio_index: 78
+io_4iomodule_c5_index: 56gpio_index: 389
+io_4iomodule_a_index: 13gpio_index: 385
+io_4iomodule_c5_index: 4gpio_index: 83
+io_4iomodule_c5_index: 23gpio_index: 86
+io_4iomodule_a_index: 15gpio_index: 381
+io_4iomodule_a_index: 8gpio_index: 377
+io_4iomodule_c5_index: 46gpio_index: 91
+io_4iomodule_a_index: 5gpio_index: 373
+io_4iomodule_a_index: 11gpio_index: 369
+io_4iomodule_c5_index: 41gpio_index: 94
+io_4iomodule_a_index: 3gpio_index: 365
+io_4iomodule_c5_index: 25gpio_index: 99
+io_4iomodule_a_index: 7gpio_index: 361
+io_4iomodule_c5_index: 9gpio_index: 102
+io_4iomodule_a_index: 0gpio_index: 357
+io_4iomodule_c5_index: 14gpio_index: 107
+io_4iomodule_a_index: 12gpio_index: 353
+io_4iomodule_c5_index: 45gpio_index: 110
+io_4iomodule_c5_index: 17gpio_index: 115
+io_4iomodule_a_index: 4gpio_index: 349
+io_4iomodule_c5_index: 36gpio_index: 118
+io_4iomodule_a_index: 10gpio_index: 345
+io_4iomodule_a_index: 16gpio_index: 341
+io_4iomodule_c5_index: 15gpio_index: 123
+io_4iomodule_a_index: 14gpio_index: 337
+io_4iomodule_c5_index: 43gpio_index: 126
+io_4iomodule_c5_index: 19gpio_index: 131
+io_4iomodule_a_index: 1gpio_index: 333
+io_4iomodule_c5_index: 59gpio_index: 134
+io_4iomodule_a_index: 2gpio_index: 329
+io_4iomodule_a_index: 9gpio_index: 325
+io_4iomodule_c5_index: 48gpio_index: 139
+io_4iomodule_a_index: 6gpio_index: 321
+io_4iomodule_a_index: 17gpio_index: 317
+io_4iomodule_c5_index: 40gpio_index: 142
+io_4iomodule_c5_index: 11gpio_index: 147
+io_4iomodule_c5_index: 58gpio_index: 150
+io_4iomodule_c5_index: 21gpio_index: 155
+io_4iomodule_c5_index: 49gpio_index: 158
+io_4iomodule_h_c5_index: 0gpio_index: 161
+io_4iomodule_h_c5_index: 6gpio_index: 165
+io_4iomodule_h_c5_index: 10gpio_index: 169
+io_4iomodule_h_c5_index: 3gpio_index: 173
+io_4iomodule_h_c5_index: 8gpio_index: 176
+io_4iomodule_h_c5_index: 11gpio_index: 180
+io_4iomodule_h_c5_index: 7gpio_index: 184
+io_4iomodule_h_c5_index: 5gpio_index: 188
+io_4iomodule_h_c5_index: 1gpio_index: 192
+io_4iomodule_h_c5_index: 2gpio_index: 196
+io_4iomodule_h_c5_index: 9gpio_index: 200
+io_4iomodule_h_c5_index: 4gpio_index: 204
+io_4iomodule_h_index: 15gpio_index: 208
+io_4iomodule_h_index: 1gpio_index: 212
+io_4iomodule_h_index: 3gpio_index: 216
+io_4iomodule_h_index: 2gpio_index: 220
+io_4iomodule_h_index: 11gpio_index: 224
+io_4iomodule_vref_h_index: 1gpio_index: 228
+io_4iomodule_h_index: 20gpio_index: 231
+io_4iomodule_h_index: 8gpio_index: 235
+io_4iomodule_h_index: 6gpio_index: 239
+io_4iomodule_h_index: 10gpio_index: 243
+io_4iomodule_h_index: 23gpio_index: 247
+io_4iomodule_h_index: 7gpio_index: 251
+io_4iomodule_h_index: 22gpio_index: 255
+io_4iomodule_h_index: 5gpio_index: 259
+io_4iomodule_h_index: 24gpio_index: 263
+io_4iomodule_h_index: 0gpio_index: 267
+io_4iomodule_h_index: 13gpio_index: 271
+io_4iomodule_h_index: 21gpio_index: 275
+io_4iomodule_h_index: 16gpio_index: 279
+io_4iomodule_vref_h_index: 0gpio_index: 283
+io_4iomodule_h_index: 12gpio_index: 286
+io_4iomodule_h_index: 4gpio_index: 290
+io_4iomodule_h_index: 19gpio_index: 294
+io_4iomodule_h_index: 18gpio_index: 298
+io_4iomodule_h_index: 17gpio_index: 302
+io_4iomodule_h_index: 25gpio_index: 306
+io_4iomodule_h_index: 14gpio_index: 310
+io_4iomodule_h_index: 9gpio_index: 314
diff --git a/part_4/ex19/db/.cmp.kpt b/part_4/ex19/db/.cmp.kpt
new file mode 100755
index 0000000..f004ca5
--- /dev/null
+++ b/part_4/ex19/db/.cmp.kpt
diff --git a/part_4/ex19/db/add_sub_a9h.tdf b/part_4/ex19/db/add_sub_a9h.tdf
new file mode 100755
index 0000000..ef3fd5b
--- /dev/null
+++ b/part_4/ex19/db/add_sub_a9h.tdf
@@ -0,0 +1,32 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=15 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+
+--synthesis_resources = lut 15 
+SUBDESIGN add_sub_a9h
+( 
+	dataa[14..0]	:	input;
+	datab[14..0]	:	input;
+	result[14..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_4/ex19/db/add_sub_e9h.tdf b/part_4/ex19/db/add_sub_e9h.tdf
new file mode 100755
index 0000000..b85c02c
--- /dev/null
+++ b/part_4/ex19/db/add_sub_e9h.tdf
@@ -0,0 +1,32 @@
+--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone V" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=19 ONE_INPUT_IS_CONSTANT="YES" dataa datab result
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+
+--synthesis_resources = lut 19 
+SUBDESIGN add_sub_e9h
+( 
+	dataa[18..0]	:	input;
+	datab[18..0]	:	input;
+	result[18..0]	:	output;
+) 
+BEGIN 
+	result[] = dataa[] + datab[];
+END;
+--VALID FILE
diff --git a/part_4/ex19/db/altsyncram_mst1.tdf b/part_4/ex19/db/altsyncram_mst1.tdf
new file mode 100755
index 0000000..0e654bc
--- /dev/null
+++ b/part_4/ex19/db/altsyncram_mst1.tdf
@@ -0,0 +1,359 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO" NUMWORDS_A=8192 NUMWORDS_B=8192 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=9 WIDTH_B=9 WIDTH_BYTEENA_A=1 WIDTHAD_A=13 WIDTHAD_B=13 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 9 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_mst1
+( 
+	address_a[12..0]	:	input;
+	address_b[12..0]	:	input;
+	clock0	:	input;
+	data_a[8..0]	:	input;
+	q_b[8..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[12..0]	: WIRE;
+	address_b_wire[12..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[8..0].clk0 = clock0;
+	ram_block1a[8..0].clk1 = clock0;
+	ram_block1a[8..0].ena0 = wren_a;
+	ram_block1a[8..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[8].portadatain[] = ( data_a[8..8]);
+	ram_block1a[8..0].portawe = wren_a;
+	ram_block1a[8..0].portbaddr[] = ( address_b_wire[12..0]);
+	ram_block1a[8..0].portbre = B"111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block1a[8..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_4/ex19/db/altsyncram_nm22.tdf b/part_4/ex19/db/altsyncram_nm22.tdf
new file mode 100755
index 0000000..357de41
--- /dev/null
+++ b/part_4/ex19/db/altsyncram_nm22.tdf
@@ -0,0 +1,361 @@
+--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO" NUMWORDS_A=8192 NUMWORDS_B=8192 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M10K" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=9 WIDTH_B=9 WIDTH_BYTEENA_A=1 WIDTHAD_A=13 WIDTHAD_B=13 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
+RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M10K 9 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_nm22
+( 
+	address_a[12..0]	:	input;
+	address_b[12..0]	:	input;
+	clock0	:	input;
+	data_a[8..0]	:	input;
+	q_b[8..0]	:	output;
+	rden_b	:	input;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block1a0 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	ram_block1a1 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	ram_block1a2 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	ram_block1a3 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	ram_block1a4 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	ram_block1a5 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	ram_block1a6 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	ram_block1a7 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	ram_block1a8 : cyclonev_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "ena1",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "none",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 13,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 8191,
+			PORT_A_LOGICAL_RAM_DEPTH = 8192,
+			PORT_A_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 13,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 8191,
+			PORT_B_LOGICAL_RAM_DEPTH = 8192,
+			PORT_B_LOGICAL_RAM_WIDTH = 9,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			POWER_UP_UNINITIALIZED = "false",
+			RAM_BLOCK_TYPE = "M10K"
+		);
+	address_a_wire[12..0]	: WIRE;
+	address_b_wire[12..0]	: WIRE;
+
+BEGIN 
+	ram_block1a[8..0].clk0 = clock0;
+	ram_block1a[8..0].clk1 = clock0;
+	ram_block1a[8..0].ena0 = wren_a;
+	ram_block1a[8..0].ena1 = rden_b;
+	ram_block1a[8..0].portaaddr[] = ( address_a_wire[12..0]);
+	ram_block1a[0].portadatain[] = ( data_a[0..0]);
+	ram_block1a[1].portadatain[] = ( data_a[1..1]);
+	ram_block1a[2].portadatain[] = ( data_a[2..2]);
+	ram_block1a[3].portadatain[] = ( data_a[3..3]);
+	ram_block1a[4].portadatain[] = ( data_a[4..4]);
+	ram_block1a[5].portadatain[] = ( data_a[5..5]);
+	ram_block1a[6].portadatain[] = ( data_a[6..6]);
+	ram_block1a[7].portadatain[] = ( data_a[7..7]);
+	ram_block1a[8].portadatain[] = ( data_a[8..8]);
+	ram_block1a[8..0].portawe = wren_a;
+	ram_block1a[8..0].portbaddr[] = ( address_b_wire[12..0]);
+	ram_block1a[8..0].portbre = B"111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block1a[8..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/part_4/ex19/db/cntr_cjh.tdf b/part_4/ex19/db/cntr_cjh.tdf
new file mode 100755
index 0000000..0bd71f0
--- /dev/null
+++ b/part_4/ex19/db/cntr_cjh.tdf
@@ -0,0 +1,153 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=13 clock q CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, the Altera Quartus Prime License Agreement,
+--  the Altera MegaCore Function License Agreement, or other 
+--  applicable license agreement, including, without limitation, 
+--  that your use is for the sole purpose of programming logic 
+--  devices manufactured by Altera and sold by Altera or its 
+--  authorized distributors.  Please refer to the applicable 
+--  agreement for further details.
+
+
+FUNCTION cyclonev_lcell_comb (cin, dataa, datab, datac, datad, datae, dataf, datag, sharein)
+WITH ( DONT_TOUCH, EXTENDED_LUT, LUT_MASK, SHARED_ARITH)
+RETURNS ( combout, cout, shareout, sumout);
+
+--synthesis_resources = lut 13 reg 13 
+SUBDESIGN cntr_cjh
+( 
+	clock	:	input;
+	q[12..0]	:	output;
+) 
+VARIABLE 
+	counter_reg_bit[12..0] : dffeas;
+	counter_comb_bita0 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "000000000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita1 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita2 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita3 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita4 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita5 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita6 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita7 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita8 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita9 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita10 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita11 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	counter_comb_bita12 : cyclonev_lcell_comb
+		WITH (
+			EXTENDED_LUT = "off",
+			LUT_MASK = "0000FF000000FF00",
+			SHARED_ARITH = "off"
+		);
+	aclr_actual	: WIRE;
+	clk_en	: NODE;
+	cnt_en	: NODE;
+	data[12..0]	: NODE;
+	external_cin	: WIRE;
+	lsb_cin	: WIRE;
+	s_val[12..0]	: WIRE;
+	safe_q[12..0]	: WIRE;
+	sclr	: NODE;
+	sload	: NODE;
+	sset	: NODE;
+	updown_dir	: WIRE;
+	updown_lsb	: WIRE;
+	updown_other_bits	: WIRE;
+
+BEGIN 
+	counter_reg_bit[].asdata = ((sset & s_val[]) # ((! sset) & data[]));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[12..0].sumout);
+	counter_reg_bit[].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
+	counter_reg_bit[].sclr = sclr;
+	counter_reg_bit[].sload = (sset # sload);
+	counter_comb_bita[12..0].cin = ( counter_comb_bita[11..0].cout, lsb_cin);
+	counter_comb_bita[12..0].datad = ( counter_reg_bit[12..0].q);
+	counter_comb_bita[12..0].dataf = ( updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_other_bits, updown_lsb);
+	aclr_actual = B"0";
+	clk_en = VCC;
+	cnt_en = VCC;
+	data[] = GND;
+	external_cin = B"1";
+	lsb_cin = B"0";
+	q[] = safe_q[];
+	s_val[] = B"1111111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sclr = GND;
+	sload = GND;
+	sset = GND;
+	updown_dir = B"1";
+	updown_lsb = updown_dir;
+	updown_other_bits = ((! external_cin) # updown_dir);
+END;
+--VALID FILE
diff --git a/part_4/ex19/db/ex19.(0).cnf.cdb b/part_4/ex19/db/ex19.(0).cnf.cdb
new file mode 100755
index 0000000..bb49b89
--- /dev/null
+++ b/part_4/ex19/db/ex19.(0).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(0).cnf.hdb b/part_4/ex19/db/ex19.(0).cnf.hdb
new file mode 100755
index 0000000..fad3d00
--- /dev/null
+++ b/part_4/ex19/db/ex19.(0).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(1).cnf.cdb b/part_4/ex19/db/ex19.(1).cnf.cdb
new file mode 100755
index 0000000..bafd7f8
--- /dev/null
+++ b/part_4/ex19/db/ex19.(1).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(1).cnf.hdb b/part_4/ex19/db/ex19.(1).cnf.hdb
new file mode 100755
index 0000000..bf76785
--- /dev/null
+++ b/part_4/ex19/db/ex19.(1).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(10).cnf.cdb b/part_4/ex19/db/ex19.(10).cnf.cdb
new file mode 100755
index 0000000..25c03bb
--- /dev/null
+++ b/part_4/ex19/db/ex19.(10).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(10).cnf.hdb b/part_4/ex19/db/ex19.(10).cnf.hdb
new file mode 100755
index 0000000..1785197
--- /dev/null
+++ b/part_4/ex19/db/ex19.(10).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(11).cnf.cdb b/part_4/ex19/db/ex19.(11).cnf.cdb
new file mode 100755
index 0000000..e5b15c0
--- /dev/null
+++ b/part_4/ex19/db/ex19.(11).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(11).cnf.hdb b/part_4/ex19/db/ex19.(11).cnf.hdb
new file mode 100755
index 0000000..2bf8e9a
--- /dev/null
+++ b/part_4/ex19/db/ex19.(11).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(12).cnf.cdb b/part_4/ex19/db/ex19.(12).cnf.cdb
new file mode 100755
index 0000000..296c3ed
--- /dev/null
+++ b/part_4/ex19/db/ex19.(12).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(12).cnf.hdb b/part_4/ex19/db/ex19.(12).cnf.hdb
new file mode 100755
index 0000000..6ba3316
--- /dev/null
+++ b/part_4/ex19/db/ex19.(12).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(13).cnf.cdb b/part_4/ex19/db/ex19.(13).cnf.cdb
new file mode 100755
index 0000000..a33ca19
--- /dev/null
+++ b/part_4/ex19/db/ex19.(13).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(13).cnf.hdb b/part_4/ex19/db/ex19.(13).cnf.hdb
new file mode 100755
index 0000000..a5bd3db
--- /dev/null
+++ b/part_4/ex19/db/ex19.(13).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(14).cnf.cdb b/part_4/ex19/db/ex19.(14).cnf.cdb
new file mode 100755
index 0000000..026c01a
--- /dev/null
+++ b/part_4/ex19/db/ex19.(14).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(14).cnf.hdb b/part_4/ex19/db/ex19.(14).cnf.hdb
new file mode 100755
index 0000000..e7d00a2
--- /dev/null
+++ b/part_4/ex19/db/ex19.(14).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(15).cnf.cdb b/part_4/ex19/db/ex19.(15).cnf.cdb
new file mode 100755
index 0000000..98ac987
--- /dev/null
+++ b/part_4/ex19/db/ex19.(15).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(15).cnf.hdb b/part_4/ex19/db/ex19.(15).cnf.hdb
new file mode 100755
index 0000000..0792fc2
--- /dev/null
+++ b/part_4/ex19/db/ex19.(15).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(16).cnf.cdb b/part_4/ex19/db/ex19.(16).cnf.cdb
new file mode 100755
index 0000000..582bc80
--- /dev/null
+++ b/part_4/ex19/db/ex19.(16).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(16).cnf.hdb b/part_4/ex19/db/ex19.(16).cnf.hdb
new file mode 100755
index 0000000..3d73695
--- /dev/null
+++ b/part_4/ex19/db/ex19.(16).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(17).cnf.cdb b/part_4/ex19/db/ex19.(17).cnf.cdb
new file mode 100755
index 0000000..e5d9a34
--- /dev/null
+++ b/part_4/ex19/db/ex19.(17).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(17).cnf.hdb b/part_4/ex19/db/ex19.(17).cnf.hdb
new file mode 100755
index 0000000..040efe4
--- /dev/null
+++ b/part_4/ex19/db/ex19.(17).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(18).cnf.cdb b/part_4/ex19/db/ex19.(18).cnf.cdb
new file mode 100755
index 0000000..22dc5df
--- /dev/null
+++ b/part_4/ex19/db/ex19.(18).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(18).cnf.hdb b/part_4/ex19/db/ex19.(18).cnf.hdb
new file mode 100755
index 0000000..415d098
--- /dev/null
+++ b/part_4/ex19/db/ex19.(18).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(19).cnf.cdb b/part_4/ex19/db/ex19.(19).cnf.cdb
new file mode 100755
index 0000000..f658314
--- /dev/null
+++ b/part_4/ex19/db/ex19.(19).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(19).cnf.hdb b/part_4/ex19/db/ex19.(19).cnf.hdb
new file mode 100755
index 0000000..2fdedce
--- /dev/null
+++ b/part_4/ex19/db/ex19.(19).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(2).cnf.cdb b/part_4/ex19/db/ex19.(2).cnf.cdb
new file mode 100755
index 0000000..1562ac6
--- /dev/null
+++ b/part_4/ex19/db/ex19.(2).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(2).cnf.hdb b/part_4/ex19/db/ex19.(2).cnf.hdb
new file mode 100755
index 0000000..86324f4
--- /dev/null
+++ b/part_4/ex19/db/ex19.(2).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(20).cnf.cdb b/part_4/ex19/db/ex19.(20).cnf.cdb
new file mode 100755
index 0000000..564cb13
--- /dev/null
+++ b/part_4/ex19/db/ex19.(20).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(20).cnf.hdb b/part_4/ex19/db/ex19.(20).cnf.hdb
new file mode 100755
index 0000000..e3b5618
--- /dev/null
+++ b/part_4/ex19/db/ex19.(20).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(21).cnf.cdb b/part_4/ex19/db/ex19.(21).cnf.cdb
new file mode 100755
index 0000000..f95a3f0
--- /dev/null
+++ b/part_4/ex19/db/ex19.(21).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(21).cnf.hdb b/part_4/ex19/db/ex19.(21).cnf.hdb
new file mode 100755
index 0000000..51df98e
--- /dev/null
+++ b/part_4/ex19/db/ex19.(21).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(22).cnf.cdb b/part_4/ex19/db/ex19.(22).cnf.cdb
new file mode 100755
index 0000000..70a7e2e
--- /dev/null
+++ b/part_4/ex19/db/ex19.(22).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(22).cnf.hdb b/part_4/ex19/db/ex19.(22).cnf.hdb
new file mode 100755
index 0000000..575026c
--- /dev/null
+++ b/part_4/ex19/db/ex19.(22).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(23).cnf.cdb b/part_4/ex19/db/ex19.(23).cnf.cdb
new file mode 100755
index 0000000..378391a
--- /dev/null
+++ b/part_4/ex19/db/ex19.(23).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(23).cnf.hdb b/part_4/ex19/db/ex19.(23).cnf.hdb
new file mode 100755
index 0000000..2296126
--- /dev/null
+++ b/part_4/ex19/db/ex19.(23).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(24).cnf.cdb b/part_4/ex19/db/ex19.(24).cnf.cdb
new file mode 100755
index 0000000..130f894
--- /dev/null
+++ b/part_4/ex19/db/ex19.(24).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(24).cnf.hdb b/part_4/ex19/db/ex19.(24).cnf.hdb
new file mode 100755
index 0000000..88bfb2d
--- /dev/null
+++ b/part_4/ex19/db/ex19.(24).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(25).cnf.cdb b/part_4/ex19/db/ex19.(25).cnf.cdb
new file mode 100755
index 0000000..be7af8e
--- /dev/null
+++ b/part_4/ex19/db/ex19.(25).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(25).cnf.hdb b/part_4/ex19/db/ex19.(25).cnf.hdb
new file mode 100755
index 0000000..2634707
--- /dev/null
+++ b/part_4/ex19/db/ex19.(25).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(26).cnf.cdb b/part_4/ex19/db/ex19.(26).cnf.cdb
new file mode 100755
index 0000000..d3c5b09
--- /dev/null
+++ b/part_4/ex19/db/ex19.(26).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(26).cnf.hdb b/part_4/ex19/db/ex19.(26).cnf.hdb
new file mode 100755
index 0000000..c06681c
--- /dev/null
+++ b/part_4/ex19/db/ex19.(26).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(27).cnf.cdb b/part_4/ex19/db/ex19.(27).cnf.cdb
new file mode 100755
index 0000000..07a4f7d
--- /dev/null
+++ b/part_4/ex19/db/ex19.(27).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(27).cnf.hdb b/part_4/ex19/db/ex19.(27).cnf.hdb
new file mode 100755
index 0000000..ac8ab82
--- /dev/null
+++ b/part_4/ex19/db/ex19.(27).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(28).cnf.cdb b/part_4/ex19/db/ex19.(28).cnf.cdb
new file mode 100755
index 0000000..fb62f43
--- /dev/null
+++ b/part_4/ex19/db/ex19.(28).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(28).cnf.hdb b/part_4/ex19/db/ex19.(28).cnf.hdb
new file mode 100755
index 0000000..e5cb6d3
--- /dev/null
+++ b/part_4/ex19/db/ex19.(28).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(3).cnf.cdb b/part_4/ex19/db/ex19.(3).cnf.cdb
new file mode 100755
index 0000000..d4817e6
--- /dev/null
+++ b/part_4/ex19/db/ex19.(3).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(3).cnf.hdb b/part_4/ex19/db/ex19.(3).cnf.hdb
new file mode 100755
index 0000000..95f2fa7
--- /dev/null
+++ b/part_4/ex19/db/ex19.(3).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(4).cnf.cdb b/part_4/ex19/db/ex19.(4).cnf.cdb
new file mode 100755
index 0000000..2eecdb0
--- /dev/null
+++ b/part_4/ex19/db/ex19.(4).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(4).cnf.hdb b/part_4/ex19/db/ex19.(4).cnf.hdb
new file mode 100755
index 0000000..83911e4
--- /dev/null
+++ b/part_4/ex19/db/ex19.(4).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(5).cnf.cdb b/part_4/ex19/db/ex19.(5).cnf.cdb
new file mode 100755
index 0000000..b4a65f6
--- /dev/null
+++ b/part_4/ex19/db/ex19.(5).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(5).cnf.hdb b/part_4/ex19/db/ex19.(5).cnf.hdb
new file mode 100755
index 0000000..84b2622
--- /dev/null
+++ b/part_4/ex19/db/ex19.(5).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(6).cnf.cdb b/part_4/ex19/db/ex19.(6).cnf.cdb
new file mode 100755
index 0000000..bd921a0
--- /dev/null
+++ b/part_4/ex19/db/ex19.(6).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(6).cnf.hdb b/part_4/ex19/db/ex19.(6).cnf.hdb
new file mode 100755
index 0000000..9a4544e
--- /dev/null
+++ b/part_4/ex19/db/ex19.(6).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(7).cnf.cdb b/part_4/ex19/db/ex19.(7).cnf.cdb
new file mode 100755
index 0000000..8f1fa86
--- /dev/null
+++ b/part_4/ex19/db/ex19.(7).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(7).cnf.hdb b/part_4/ex19/db/ex19.(7).cnf.hdb
new file mode 100755
index 0000000..89225a4
--- /dev/null
+++ b/part_4/ex19/db/ex19.(7).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(8).cnf.cdb b/part_4/ex19/db/ex19.(8).cnf.cdb
new file mode 100755
index 0000000..98824a7
--- /dev/null
+++ b/part_4/ex19/db/ex19.(8).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(8).cnf.hdb b/part_4/ex19/db/ex19.(8).cnf.hdb
new file mode 100755
index 0000000..7463ff6
--- /dev/null
+++ b/part_4/ex19/db/ex19.(8).cnf.hdb
diff --git a/part_4/ex19/db/ex19.(9).cnf.cdb b/part_4/ex19/db/ex19.(9).cnf.cdb
new file mode 100755
index 0000000..da17ff2
--- /dev/null
+++ b/part_4/ex19/db/ex19.(9).cnf.cdb
diff --git a/part_4/ex19/db/ex19.(9).cnf.hdb b/part_4/ex19/db/ex19.(9).cnf.hdb
new file mode 100755
index 0000000..28eafa7
--- /dev/null
+++ b/part_4/ex19/db/ex19.(9).cnf.hdb
diff --git a/part_4/ex19/db/ex19.analyze_file.qmsg b/part_4/ex19/db/ex19.analyze_file.qmsg
new file mode 100755
index 0000000..0cb6e5a
--- /dev/null
+++ b/part_4/ex19/db/ex19.analyze_file.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1480684839085 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1480684839087 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 02 13:20:38 2016 " "Processing started: Fri Dec 02 13:20:38 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1480684839087 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1480684839087 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19 --analyze_file=\"C:/New folder/ex19/verilog_files/mult.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19 --analyze_file=\"C:/New folder/ex19/verilog_files/mult.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1480684839087 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1480684839511 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1480684839511 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analyze Current File 0 s 1  Quartus Prime " "Quartus Prime Analyze Current File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "829 " "Peak virtual memory: 829 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1480684847929 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 02 13:20:47 2016 " "Processing ended: Fri Dec 02 13:20:47 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1480684847929 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1480684847929 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1480684847929 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1480684847929 ""}
diff --git a/part_4/ex19/db/ex19.asm.qmsg b/part_4/ex19/db/ex19.asm.qmsg
new file mode 100755
index 0000000..3ad85e0
--- /dev/null
+++ b/part_4/ex19/db/ex19.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481017633576 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481017633578 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 06 09:47:13 2016 " "Processing started: Tue Dec 06 09:47:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481017633578 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481017633578 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex19 -c ex19 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex19 -c ex19" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481017633579 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481017634373 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481017639051 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "894 " "Peak virtual memory: 894 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017639396 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:47:19 2016 " "Processing ended: Tue Dec 06 09:47:19 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017639396 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017639396 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017639396 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481017639396 ""}
diff --git a/part_4/ex19/db/ex19.asm.rdb b/part_4/ex19/db/ex19.asm.rdb
new file mode 100755
index 0000000..2c4aed6
--- /dev/null
+++ b/part_4/ex19/db/ex19.asm.rdb
diff --git a/part_4/ex19/db/ex19.cbx.xml b/part_4/ex19/db/ex19.cbx.xml
new file mode 100755
index 0000000..b4abc97
--- /dev/null
+++ b/part_4/ex19/db/ex19.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ex19">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/part_4/ex19/db/ex19.cmp.ammdb b/part_4/ex19/db/ex19.cmp.ammdb
new file mode 100755
index 0000000..afc49bc
--- /dev/null
+++ b/part_4/ex19/db/ex19.cmp.ammdb
diff --git a/part_4/ex19/db/ex19.cmp.bpm b/part_4/ex19/db/ex19.cmp.bpm
new file mode 100755
index 0000000..74d42c3
--- /dev/null
+++ b/part_4/ex19/db/ex19.cmp.bpm
diff --git a/part_4/ex19/db/ex19.cmp.cdb b/part_4/ex19/db/ex19.cmp.cdb
new file mode 100755
index 0000000..d39c49d
--- /dev/null
+++ b/part_4/ex19/db/ex19.cmp.cdb
diff --git a/part_4/ex19/db/ex19.cmp.hdb b/part_4/ex19/db/ex19.cmp.hdb
new file mode 100755
index 0000000..9467c6e
--- /dev/null
+++ b/part_4/ex19/db/ex19.cmp.hdb
diff --git a/part_4/ex19/db/ex19.cmp.idb b/part_4/ex19/db/ex19.cmp.idb
new file mode 100755
index 0000000..42ffe34
--- /dev/null
+++ b/part_4/ex19/db/ex19.cmp.idb
diff --git a/part_2/ex9_final/db/ex9.cmp.logdb b/part_4/ex19/db/ex19.cmp.logdb
index b4567d7..42a0ae5 100755
--- a/part_2/ex9_final/db/ex9.cmp.logdb
+++ b/part_4/ex19/db/ex19.cmp.logdb
@@ -28,12 +28,11 @@ IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for
 IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
 IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
 IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000034,
-IO_RULES_MATRIX,Total Pass,57;0;57;0;0;57;57;0;57;57;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Pass,55;0;55;0;0;55;55;0;55;55;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
 IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;57;0;57;57;0;0;57;0;0;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57;57,
+IO_RULES_MATRIX,Total Inapplicable,0;55;0;55;55;0;0;55;0;0;55;55;55;55;55;55;55;55;55;55;55;55;55;55;55;55;55;55,
 IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
@@ -69,26 +68,25 @@ IO_RULES_MATRIX,HEX4[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pa
 IO_RULES_MATRIX,HEX4[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX4[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,HEX4[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,HEX5[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DAC_LD,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDI,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SCK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_CS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PWM_OUT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,KEY[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,ADC_SDO,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
 IO_RULES_SUMMARY,Total I/O Rules,28,
 IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
 IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
diff --git a/part_4/ex19/db/ex19.cmp.rdb b/part_4/ex19/db/ex19.cmp.rdb
new file mode 100755
index 0000000..7fcda29
--- /dev/null
+++ b/part_4/ex19/db/ex19.cmp.rdb
diff --git a/part_4/ex19/db/ex19.cmp_merge.kpt b/part_4/ex19/db/ex19.cmp_merge.kpt
new file mode 100755
index 0000000..045bec4
--- /dev/null
+++ b/part_4/ex19/db/ex19.cmp_merge.kpt
diff --git a/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ff_0c_fast.hsd b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ff_0c_fast.hsd
new file mode 100755
index 0000000..da61997
--- /dev/null
+++ b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ff_0c_fast.hsd
diff --git a/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ff_85c_fast.hsd b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ff_85c_fast.hsd
new file mode 100755
index 0000000..3a7a497
--- /dev/null
+++ b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ff_85c_fast.hsd
diff --git a/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ss_0c_slow.hsd b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ss_0c_slow.hsd
new file mode 100755
index 0000000..3f61b64
--- /dev/null
+++ b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ss_0c_slow.hsd
diff --git a/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ss_85c_slow.hsd b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ss_85c_slow.hsd
new file mode 100755
index 0000000..6aaa577
--- /dev/null
+++ b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.ss_85c_slow.hsd
diff --git a/part_4/ex19/db/ex19.cyclonev_io_sim_cache.tt_0c_slow.hsd b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.tt_0c_slow.hsd
new file mode 100755
index 0000000..aa473fa
--- /dev/null
+++ b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.tt_0c_slow.hsd
diff --git a/part_4/ex19/db/ex19.cyclonev_io_sim_cache.tt_85c_slow.hsd b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.tt_85c_slow.hsd
new file mode 100755
index 0000000..dce4f6b
--- /dev/null
+++ b/part_4/ex19/db/ex19.cyclonev_io_sim_cache.tt_85c_slow.hsd
diff --git a/part_4/ex19/db/ex19.db_info b/part_4/ex19/db/ex19.db_info
new file mode 100755
index 0000000..18f6d82
--- /dev/null
+++ b/part_4/ex19/db/ex19.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Tue Dec 06 09:04:57 2016
diff --git a/part_4/ex19/db/ex19.fit.qmsg b/part_4/ex19/db/ex19.fit.qmsg
new file mode 100755
index 0000000..8a8f171
--- /dev/null
+++ b/part_4/ex19/db/ex19.fit.qmsg
@@ -0,0 +1,45 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481017591218 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481017591218 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex19 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex19\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481017591474 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481017591527 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481017591527 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481017591921 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481017592066 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1481017592072 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481017602211 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 69 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 69 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481017602313 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481017602313 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017602314 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481017602319 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481017602320 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481017602321 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481017602322 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481017602322 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481017602323 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex19.sdc " "Synopsys Design Constraints File file not found: 'ex19.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481017603188 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481017603189 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481017603193 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481017603194 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481017603195 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481017603215 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481017603216 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481017603216 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017603267 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481017603267 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017603268 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481017608236 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481017608494 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017609294 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481017610425 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481017611734 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017611734 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481017613113 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "7 X67_Y0 X77_Y10 " "Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex19/" { { 1 { 0 "Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10"} { { 12 { 0 ""} 67 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481017618404 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481017618404 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481017626093 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481017626093 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:09 " "Fitter routing operations ending: elapsed time is 00:00:09" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017626097 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.76 " "Total time spent on timing analysis during the Fitter is 0.76 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481017627573 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481017627614 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481017628134 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481017628134 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481017628627 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017631374 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481017631627 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex19/output_files/ex19.fit.smsg " "Generated suppressed messages file C:/New folder/ex19/output_files/ex19.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481017631692 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 31 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2764 " "Peak virtual memory: 2764 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017632186 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:47:12 2016 " "Processing ended: Tue Dec 06 09:47:12 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017632186 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:42 " "Elapsed time: 00:00:42" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017632186 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:11 " "Total CPU time (on all processors): 00:01:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017632186 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481017632186 ""}
diff --git a/part_4/ex19/db/ex19.hier_info b/part_4/ex19/db/ex19.hier_info
new file mode 100755
index 0000000..cfea879
--- /dev/null
+++ b/part_4/ex19/db/ex19.hier_info
@@ -0,0 +1,2308 @@
+|ex19
+CLOCK_50 => CLOCK_50.IN5
+SW[0] => SW[0].IN1
+SW[1] => SW[1].IN1
+SW[2] => SW[2].IN1
+SW[3] => SW[3].IN1
+SW[4] => SW[4].IN1
+SW[5] => SW[5].IN1
+SW[6] => SW[6].IN1
+SW[7] => SW[7].IN1
+SW[8] => SW[8].IN1
+SW[9] => SW[9].IN1
+HEX0[0] << processor:echo_var_delay.port6
+HEX0[1] << processor:echo_var_delay.port6
+HEX0[2] << processor:echo_var_delay.port6
+HEX0[3] << processor:echo_var_delay.port6
+HEX0[4] << processor:echo_var_delay.port6
+HEX0[5] << processor:echo_var_delay.port6
+HEX0[6] << processor:echo_var_delay.port6
+HEX1[0] << processor:echo_var_delay.port7
+HEX1[1] << processor:echo_var_delay.port7
+HEX1[2] << processor:echo_var_delay.port7
+HEX1[3] << processor:echo_var_delay.port7
+HEX1[4] << processor:echo_var_delay.port7
+HEX1[5] << processor:echo_var_delay.port7
+HEX1[6] << processor:echo_var_delay.port7
+HEX2[0] << processor:echo_var_delay.port8
+HEX2[1] << processor:echo_var_delay.port8
+HEX2[2] << processor:echo_var_delay.port8
+HEX2[3] << processor:echo_var_delay.port8
+HEX2[4] << processor:echo_var_delay.port8
+HEX2[5] << processor:echo_var_delay.port8
+HEX2[6] << processor:echo_var_delay.port8
+HEX3[0] << processor:echo_var_delay.port9
+HEX3[1] << processor:echo_var_delay.port9
+HEX3[2] << processor:echo_var_delay.port9
+HEX3[3] << processor:echo_var_delay.port9
+HEX3[4] << processor:echo_var_delay.port9
+HEX3[5] << processor:echo_var_delay.port9
+HEX3[6] << processor:echo_var_delay.port9
+HEX4[0] << processor:echo_var_delay.port10
+HEX4[1] << processor:echo_var_delay.port10
+HEX4[2] << processor:echo_var_delay.port10
+HEX4[3] << processor:echo_var_delay.port10
+HEX4[4] << processor:echo_var_delay.port10
+HEX4[5] << processor:echo_var_delay.port10
+HEX4[6] << processor:echo_var_delay.port10
+DAC_SDI << spi2dac:SPI_DAC.port3
+DAC_SCK << spi2dac:SPI_DAC.port5
+DAC_CS << spi2dac:SPI_DAC.port4
+DAC_LD << spi2dac:SPI_DAC.port6
+ADC_SDI << spi2adc:SPI_ADC.sdata_to_adc
+ADC_SCK << spi2adc:SPI_ADC.adc_sck
+ADC_CS << spi2adc:SPI_ADC.adc_cs
+ADC_SDO => ADC_SDO.IN1
+PWM_OUT << pwm:PWM_DC.port3
+
+
+|ex19|clktick_16:GEN_10K
+clkin => count[0].CLK
+clkin => count[1].CLK
+clkin => count[2].CLK
+clkin => count[3].CLK
+clkin => count[4].CLK
+clkin => count[5].CLK
+clkin => count[6].CLK
+clkin => count[7].CLK
+clkin => count[8].CLK
+clkin => count[9].CLK
+clkin => count[10].CLK
+clkin => count[11].CLK
+clkin => count[12].CLK
+clkin => count[13].CLK
+clkin => count[14].CLK
+clkin => count[15].CLK
+clkin => tick~reg0.CLK
+enable => count[0].ENA
+enable => count[1].ENA
+enable => count[2].ENA
+enable => count[3].ENA
+enable => count[4].ENA
+enable => count[5].ENA
+enable => count[6].ENA
+enable => count[7].ENA
+enable => count[8].ENA
+enable => count[9].ENA
+enable => count[10].ENA
+enable => count[11].ENA
+enable => count[12].ENA
+enable => count[13].ENA
+enable => count[14].ENA
+enable => count[15].ENA
+enable => tick~reg0.ENA
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => count.DATAB
+N[8] => count.DATAB
+N[9] => count.DATAB
+N[10] => count.DATAB
+N[11] => count.DATAB
+N[12] => count.DATAB
+N[13] => count.DATAB
+N[14] => count.DATAB
+N[15] => count.DATAB
+tick <= tick~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|spi2dac:SPI_DAC
+clk => dac_start.CLK
+clk => clk_1MHz.CLK
+clk => ctr[0].CLK
+clk => ctr[1].CLK
+clk => ctr[2].CLK
+clk => ctr[3].CLK
+clk => ctr[4].CLK
+clk => sr_state~1.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => Selector1.IN1
+load => dac_start.OUTPUTSELECT
+load => Selector0.IN1
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= dac_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= dac_ld~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|pwm:PWM_DC
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|spi2adc:SPI_ADC
+sysclk => adc_start.CLK
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~1.DATAIN
+start => Selector1.IN1
+start => adc_start.OUTPUTSELECT
+start => Selector0.IN1
+channel => Selector6.IN6
+data_from_adc[0] <= data_from_adc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[1] <= data_from_adc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[2] <= data_from_adc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[3] <= data_from_adc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[4] <= data_from_adc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[5] <= data_from_adc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[6] <= data_from_adc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[7] <= data_from_adc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[8] <= data_from_adc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[9] <= data_from_adc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+sdata_to_adc <= adc_din.DB_MAX_OUTPUT_PORT_TYPE
+adc_cs <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+adc_sck <= adc_sck.DB_MAX_OUTPUT_PORT_TYPE
+sdata_from_adc => shift_reg[0].DATAIN
+
+
+|ex19|processor:echo_var_delay
+sysclk => sysclk.IN1
+tick => tick.IN2
+SW[0] => SW[0].IN1
+SW[1] => SW[1].IN1
+SW[2] => SW[2].IN1
+SW[3] => SW[3].IN1
+SW[4] => SW[4].IN1
+SW[5] => SW[5].IN1
+SW[6] => SW[6].IN1
+SW[7] => SW[7].IN1
+SW[8] => SW[8].IN1
+SW[9] => SW[9].IN1
+data_in[0] => data_in[0].IN1
+data_in[1] => data_in[1].IN1
+data_in[2] => data_in[2].IN1
+data_in[3] => data_in[3].IN1
+data_in[4] => data_in[4].IN1
+data_in[5] => data_in[5].IN1
+data_in[6] => data_in[6].IN1
+data_in[7] => data_in[7].IN1
+data_in[8] => data_in[8].IN1
+data_in[9] => data_in[9].IN1
+data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid => _.IN1
+hex0[0] <= hex_to_7seg:h0.port0
+hex0[1] <= hex_to_7seg:h0.port0
+hex0[2] <= hex_to_7seg:h0.port0
+hex0[3] <= hex_to_7seg:h0.port0
+hex0[4] <= hex_to_7seg:h0.port0
+hex0[5] <= hex_to_7seg:h0.port0
+hex0[6] <= hex_to_7seg:h0.port0
+hex1[0] <= hex_to_7seg:h1.port0
+hex1[1] <= hex_to_7seg:h1.port0
+hex1[2] <= hex_to_7seg:h1.port0
+hex1[3] <= hex_to_7seg:h1.port0
+hex1[4] <= hex_to_7seg:h1.port0
+hex1[5] <= hex_to_7seg:h1.port0
+hex1[6] <= hex_to_7seg:h1.port0
+hex2[0] <= hex_to_7seg:h2.port0
+hex2[1] <= hex_to_7seg:h2.port0
+hex2[2] <= hex_to_7seg:h2.port0
+hex2[3] <= hex_to_7seg:h2.port0
+hex2[4] <= hex_to_7seg:h2.port0
+hex2[5] <= hex_to_7seg:h2.port0
+hex2[6] <= hex_to_7seg:h2.port0
+hex3[0] <= hex_to_7seg:h3.port0
+hex3[1] <= hex_to_7seg:h3.port0
+hex3[2] <= hex_to_7seg:h3.port0
+hex3[3] <= hex_to_7seg:h3.port0
+hex3[4] <= hex_to_7seg:h3.port0
+hex3[5] <= hex_to_7seg:h3.port0
+hex3[6] <= hex_to_7seg:h3.port0
+hex4[0] <= hex_to_7seg:h4.port0
+hex4[1] <= hex_to_7seg:h4.port0
+hex4[2] <= hex_to_7seg:h4.port0
+hex4[3] <= hex_to_7seg:h4.port0
+hex4[4] <= hex_to_7seg:h4.port0
+hex4[5] <= hex_to_7seg:h4.port0
+hex4[6] <= hex_to_7seg:h4.port0
+
+
+|ex19|processor:echo_var_delay|ctr_13_bit:ctr
+clock => clock.IN1
+q[0] <= lpm_counter:LPM_COUNTER_component.q
+q[1] <= lpm_counter:LPM_COUNTER_component.q
+q[2] <= lpm_counter:LPM_COUNTER_component.q
+q[3] <= lpm_counter:LPM_COUNTER_component.q
+q[4] <= lpm_counter:LPM_COUNTER_component.q
+q[5] <= lpm_counter:LPM_COUNTER_component.q
+q[6] <= lpm_counter:LPM_COUNTER_component.q
+q[7] <= lpm_counter:LPM_COUNTER_component.q
+q[8] <= lpm_counter:LPM_COUNTER_component.q
+q[9] <= lpm_counter:LPM_COUNTER_component.q
+q[10] <= lpm_counter:LPM_COUNTER_component.q
+q[11] <= lpm_counter:LPM_COUNTER_component.q
+q[12] <= lpm_counter:LPM_COUNTER_component.q
+
+
+|ex19|processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component
+clock => cntr_cjh:auto_generated.clock
+clk_en => ~NO_FANOUT~
+cnt_en => ~NO_FANOUT~
+updown => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+aset => ~NO_FANOUT~
+aconst => ~NO_FANOUT~
+aload => ~NO_FANOUT~
+sclr => ~NO_FANOUT~
+sset => ~NO_FANOUT~
+sconst => ~NO_FANOUT~
+sload => ~NO_FANOUT~
+data[0] => ~NO_FANOUT~
+data[1] => ~NO_FANOUT~
+data[2] => ~NO_FANOUT~
+data[3] => ~NO_FANOUT~
+data[4] => ~NO_FANOUT~
+data[5] => ~NO_FANOUT~
+data[6] => ~NO_FANOUT~
+data[7] => ~NO_FANOUT~
+data[8] => ~NO_FANOUT~
+data[9] => ~NO_FANOUT~
+data[10] => ~NO_FANOUT~
+data[11] => ~NO_FANOUT~
+data[12] => ~NO_FANOUT~
+cin => ~NO_FANOUT~
+q[0] <= cntr_cjh:auto_generated.q[0]
+q[1] <= cntr_cjh:auto_generated.q[1]
+q[2] <= cntr_cjh:auto_generated.q[2]
+q[3] <= cntr_cjh:auto_generated.q[3]
+q[4] <= cntr_cjh:auto_generated.q[4]
+q[5] <= cntr_cjh:auto_generated.q[5]
+q[6] <= cntr_cjh:auto_generated.q[6]
+q[7] <= cntr_cjh:auto_generated.q[7]
+q[8] <= cntr_cjh:auto_generated.q[8]
+q[9] <= cntr_cjh:auto_generated.q[9]
+q[10] <= cntr_cjh:auto_generated.q[10]
+q[11] <= cntr_cjh:auto_generated.q[11]
+q[12] <= cntr_cjh:auto_generated.q[12]
+cout <= <GND>
+eq[0] <= <GND>
+eq[1] <= <GND>
+eq[2] <= <GND>
+eq[3] <= <GND>
+eq[4] <= <GND>
+eq[5] <= <GND>
+eq[6] <= <GND>
+eq[7] <= <GND>
+eq[8] <= <GND>
+eq[9] <= <GND>
+eq[10] <= <GND>
+eq[11] <= <GND>
+eq[12] <= <GND>
+eq[13] <= <GND>
+eq[14] <= <GND>
+eq[15] <= <GND>
+
+
+|ex19|processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated
+clock => counter_reg_bit[12].CLK
+clock => counter_reg_bit[11].CLK
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+q[11] <= counter_reg_bit[11].DB_MAX_OUTPUT_PORT_TYPE
+q[12] <= counter_reg_bit[12].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|delay_block:del
+clock => clock.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+rdaddress[0] => rdaddress[0].IN1
+rdaddress[1] => rdaddress[1].IN1
+rdaddress[2] => rdaddress[2].IN1
+rdaddress[3] => rdaddress[3].IN1
+rdaddress[4] => rdaddress[4].IN1
+rdaddress[5] => rdaddress[5].IN1
+rdaddress[6] => rdaddress[6].IN1
+rdaddress[7] => rdaddress[7].IN1
+rdaddress[8] => rdaddress[8].IN1
+rdaddress[9] => rdaddress[9].IN1
+rdaddress[10] => rdaddress[10].IN1
+rdaddress[11] => rdaddress[11].IN1
+rdaddress[12] => rdaddress[12].IN1
+rden => rden.IN1
+wraddress[0] => wraddress[0].IN1
+wraddress[1] => wraddress[1].IN1
+wraddress[2] => wraddress[2].IN1
+wraddress[3] => wraddress[3].IN1
+wraddress[4] => wraddress[4].IN1
+wraddress[5] => wraddress[5].IN1
+wraddress[6] => wraddress[6].IN1
+wraddress[7] => wraddress[7].IN1
+wraddress[8] => wraddress[8].IN1
+wraddress[9] => wraddress[9].IN1
+wraddress[10] => wraddress[10].IN1
+wraddress[11] => wraddress[11].IN1
+wraddress[12] => wraddress[12].IN1
+wren => wren.IN1
+q[0] <= altsyncram:altsyncram_component.q_b
+q[1] <= altsyncram:altsyncram_component.q_b
+q[2] <= altsyncram:altsyncram_component.q_b
+q[3] <= altsyncram:altsyncram_component.q_b
+q[4] <= altsyncram:altsyncram_component.q_b
+q[5] <= altsyncram:altsyncram_component.q_b
+q[6] <= altsyncram:altsyncram_component.q_b
+q[7] <= altsyncram:altsyncram_component.q_b
+q[8] <= altsyncram:altsyncram_component.q_b
+
+
+|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component
+wren_a => altsyncram_nm22:auto_generated.wren_a
+rden_a => ~NO_FANOUT~
+wren_b => ~NO_FANOUT~
+rden_b => altsyncram_nm22:auto_generated.rden_b
+data_a[0] => altsyncram_nm22:auto_generated.data_a[0]
+data_a[1] => altsyncram_nm22:auto_generated.data_a[1]
+data_a[2] => altsyncram_nm22:auto_generated.data_a[2]
+data_a[3] => altsyncram_nm22:auto_generated.data_a[3]
+data_a[4] => altsyncram_nm22:auto_generated.data_a[4]
+data_a[5] => altsyncram_nm22:auto_generated.data_a[5]
+data_a[6] => altsyncram_nm22:auto_generated.data_a[6]
+data_a[7] => altsyncram_nm22:auto_generated.data_a[7]
+data_a[8] => altsyncram_nm22:auto_generated.data_a[8]
+data_b[0] => ~NO_FANOUT~
+data_b[1] => ~NO_FANOUT~
+data_b[2] => ~NO_FANOUT~
+data_b[3] => ~NO_FANOUT~
+data_b[4] => ~NO_FANOUT~
+data_b[5] => ~NO_FANOUT~
+data_b[6] => ~NO_FANOUT~
+data_b[7] => ~NO_FANOUT~
+data_b[8] => ~NO_FANOUT~
+address_a[0] => altsyncram_nm22:auto_generated.address_a[0]
+address_a[1] => altsyncram_nm22:auto_generated.address_a[1]
+address_a[2] => altsyncram_nm22:auto_generated.address_a[2]
+address_a[3] => altsyncram_nm22:auto_generated.address_a[3]
+address_a[4] => altsyncram_nm22:auto_generated.address_a[4]
+address_a[5] => altsyncram_nm22:auto_generated.address_a[5]
+address_a[6] => altsyncram_nm22:auto_generated.address_a[6]
+address_a[7] => altsyncram_nm22:auto_generated.address_a[7]
+address_a[8] => altsyncram_nm22:auto_generated.address_a[8]
+address_a[9] => altsyncram_nm22:auto_generated.address_a[9]
+address_a[10] => altsyncram_nm22:auto_generated.address_a[10]
+address_a[11] => altsyncram_nm22:auto_generated.address_a[11]
+address_a[12] => altsyncram_nm22:auto_generated.address_a[12]
+address_b[0] => altsyncram_nm22:auto_generated.address_b[0]
+address_b[1] => altsyncram_nm22:auto_generated.address_b[1]
+address_b[2] => altsyncram_nm22:auto_generated.address_b[2]
+address_b[3] => altsyncram_nm22:auto_generated.address_b[3]
+address_b[4] => altsyncram_nm22:auto_generated.address_b[4]
+address_b[5] => altsyncram_nm22:auto_generated.address_b[5]
+address_b[6] => altsyncram_nm22:auto_generated.address_b[6]
+address_b[7] => altsyncram_nm22:auto_generated.address_b[7]
+address_b[8] => altsyncram_nm22:auto_generated.address_b[8]
+address_b[9] => altsyncram_nm22:auto_generated.address_b[9]
+address_b[10] => altsyncram_nm22:auto_generated.address_b[10]
+address_b[11] => altsyncram_nm22:auto_generated.address_b[11]
+address_b[12] => altsyncram_nm22:auto_generated.address_b[12]
+addressstall_a => ~NO_FANOUT~
+addressstall_b => ~NO_FANOUT~
+clock0 => altsyncram_nm22:auto_generated.clock0
+clock1 => ~NO_FANOUT~
+clocken0 => ~NO_FANOUT~
+clocken1 => ~NO_FANOUT~
+clocken2 => ~NO_FANOUT~
+clocken3 => ~NO_FANOUT~
+aclr0 => ~NO_FANOUT~
+aclr1 => ~NO_FANOUT~
+byteena_a[0] => ~NO_FANOUT~
+byteena_b[0] => ~NO_FANOUT~
+q_a[0] <= <GND>
+q_a[1] <= <GND>
+q_a[2] <= <GND>
+q_a[3] <= <GND>
+q_a[4] <= <GND>
+q_a[5] <= <GND>
+q_a[6] <= <GND>
+q_a[7] <= <GND>
+q_a[8] <= <GND>
+q_b[0] <= altsyncram_nm22:auto_generated.q_b[0]
+q_b[1] <= altsyncram_nm22:auto_generated.q_b[1]
+q_b[2] <= altsyncram_nm22:auto_generated.q_b[2]
+q_b[3] <= altsyncram_nm22:auto_generated.q_b[3]
+q_b[4] <= altsyncram_nm22:auto_generated.q_b[4]
+q_b[5] <= altsyncram_nm22:auto_generated.q_b[5]
+q_b[6] <= altsyncram_nm22:auto_generated.q_b[6]
+q_b[7] <= altsyncram_nm22:auto_generated.q_b[7]
+q_b[8] <= altsyncram_nm22:auto_generated.q_b[8]
+eccstatus[0] <= <GND>
+eccstatus[1] <= <GND>
+eccstatus[2] <= <GND>
+
+
+|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated
+address_a[0] => ram_block1a0.PORTAADDR
+address_a[0] => ram_block1a1.PORTAADDR
+address_a[0] => ram_block1a2.PORTAADDR
+address_a[0] => ram_block1a3.PORTAADDR
+address_a[0] => ram_block1a4.PORTAADDR
+address_a[0] => ram_block1a5.PORTAADDR
+address_a[0] => ram_block1a6.PORTAADDR
+address_a[0] => ram_block1a7.PORTAADDR
+address_a[0] => ram_block1a8.PORTAADDR
+address_a[1] => ram_block1a0.PORTAADDR1
+address_a[1] => ram_block1a1.PORTAADDR1
+address_a[1] => ram_block1a2.PORTAADDR1
+address_a[1] => ram_block1a3.PORTAADDR1
+address_a[1] => ram_block1a4.PORTAADDR1
+address_a[1] => ram_block1a5.PORTAADDR1
+address_a[1] => ram_block1a6.PORTAADDR1
+address_a[1] => ram_block1a7.PORTAADDR1
+address_a[1] => ram_block1a8.PORTAADDR1
+address_a[2] => ram_block1a0.PORTAADDR2
+address_a[2] => ram_block1a1.PORTAADDR2
+address_a[2] => ram_block1a2.PORTAADDR2
+address_a[2] => ram_block1a3.PORTAADDR2
+address_a[2] => ram_block1a4.PORTAADDR2
+address_a[2] => ram_block1a5.PORTAADDR2
+address_a[2] => ram_block1a6.PORTAADDR2
+address_a[2] => ram_block1a7.PORTAADDR2
+address_a[2] => ram_block1a8.PORTAADDR2
+address_a[3] => ram_block1a0.PORTAADDR3
+address_a[3] => ram_block1a1.PORTAADDR3
+address_a[3] => ram_block1a2.PORTAADDR3
+address_a[3] => ram_block1a3.PORTAADDR3
+address_a[3] => ram_block1a4.PORTAADDR3
+address_a[3] => ram_block1a5.PORTAADDR3
+address_a[3] => ram_block1a6.PORTAADDR3
+address_a[3] => ram_block1a7.PORTAADDR3
+address_a[3] => ram_block1a8.PORTAADDR3
+address_a[4] => ram_block1a0.PORTAADDR4
+address_a[4] => ram_block1a1.PORTAADDR4
+address_a[4] => ram_block1a2.PORTAADDR4
+address_a[4] => ram_block1a3.PORTAADDR4
+address_a[4] => ram_block1a4.PORTAADDR4
+address_a[4] => ram_block1a5.PORTAADDR4
+address_a[4] => ram_block1a6.PORTAADDR4
+address_a[4] => ram_block1a7.PORTAADDR4
+address_a[4] => ram_block1a8.PORTAADDR4
+address_a[5] => ram_block1a0.PORTAADDR5
+address_a[5] => ram_block1a1.PORTAADDR5
+address_a[5] => ram_block1a2.PORTAADDR5
+address_a[5] => ram_block1a3.PORTAADDR5
+address_a[5] => ram_block1a4.PORTAADDR5
+address_a[5] => ram_block1a5.PORTAADDR5
+address_a[5] => ram_block1a6.PORTAADDR5
+address_a[5] => ram_block1a7.PORTAADDR5
+address_a[5] => ram_block1a8.PORTAADDR5
+address_a[6] => ram_block1a0.PORTAADDR6
+address_a[6] => ram_block1a1.PORTAADDR6
+address_a[6] => ram_block1a2.PORTAADDR6
+address_a[6] => ram_block1a3.PORTAADDR6
+address_a[6] => ram_block1a4.PORTAADDR6
+address_a[6] => ram_block1a5.PORTAADDR6
+address_a[6] => ram_block1a6.PORTAADDR6
+address_a[6] => ram_block1a7.PORTAADDR6
+address_a[6] => ram_block1a8.PORTAADDR6
+address_a[7] => ram_block1a0.PORTAADDR7
+address_a[7] => ram_block1a1.PORTAADDR7
+address_a[7] => ram_block1a2.PORTAADDR7
+address_a[7] => ram_block1a3.PORTAADDR7
+address_a[7] => ram_block1a4.PORTAADDR7
+address_a[7] => ram_block1a5.PORTAADDR7
+address_a[7] => ram_block1a6.PORTAADDR7
+address_a[7] => ram_block1a7.PORTAADDR7
+address_a[7] => ram_block1a8.PORTAADDR7
+address_a[8] => ram_block1a0.PORTAADDR8
+address_a[8] => ram_block1a1.PORTAADDR8
+address_a[8] => ram_block1a2.PORTAADDR8
+address_a[8] => ram_block1a3.PORTAADDR8
+address_a[8] => ram_block1a4.PORTAADDR8
+address_a[8] => ram_block1a5.PORTAADDR8
+address_a[8] => ram_block1a6.PORTAADDR8
+address_a[8] => ram_block1a7.PORTAADDR8
+address_a[8] => ram_block1a8.PORTAADDR8
+address_a[9] => ram_block1a0.PORTAADDR9
+address_a[9] => ram_block1a1.PORTAADDR9
+address_a[9] => ram_block1a2.PORTAADDR9
+address_a[9] => ram_block1a3.PORTAADDR9
+address_a[9] => ram_block1a4.PORTAADDR9
+address_a[9] => ram_block1a5.PORTAADDR9
+address_a[9] => ram_block1a6.PORTAADDR9
+address_a[9] => ram_block1a7.PORTAADDR9
+address_a[9] => ram_block1a8.PORTAADDR9
+address_a[10] => ram_block1a0.PORTAADDR10
+address_a[10] => ram_block1a1.PORTAADDR10
+address_a[10] => ram_block1a2.PORTAADDR10
+address_a[10] => ram_block1a3.PORTAADDR10
+address_a[10] => ram_block1a4.PORTAADDR10
+address_a[10] => ram_block1a5.PORTAADDR10
+address_a[10] => ram_block1a6.PORTAADDR10
+address_a[10] => ram_block1a7.PORTAADDR10
+address_a[10] => ram_block1a8.PORTAADDR10
+address_a[11] => ram_block1a0.PORTAADDR11
+address_a[11] => ram_block1a1.PORTAADDR11
+address_a[11] => ram_block1a2.PORTAADDR11
+address_a[11] => ram_block1a3.PORTAADDR11
+address_a[11] => ram_block1a4.PORTAADDR11
+address_a[11] => ram_block1a5.PORTAADDR11
+address_a[11] => ram_block1a6.PORTAADDR11
+address_a[11] => ram_block1a7.PORTAADDR11
+address_a[11] => ram_block1a8.PORTAADDR11
+address_a[12] => ram_block1a0.PORTAADDR12
+address_a[12] => ram_block1a1.PORTAADDR12
+address_a[12] => ram_block1a2.PORTAADDR12
+address_a[12] => ram_block1a3.PORTAADDR12
+address_a[12] => ram_block1a4.PORTAADDR12
+address_a[12] => ram_block1a5.PORTAADDR12
+address_a[12] => ram_block1a6.PORTAADDR12
+address_a[12] => ram_block1a7.PORTAADDR12
+address_a[12] => ram_block1a8.PORTAADDR12
+address_b[0] => ram_block1a0.PORTBADDR
+address_b[0] => ram_block1a1.PORTBADDR
+address_b[0] => ram_block1a2.PORTBADDR
+address_b[0] => ram_block1a3.PORTBADDR
+address_b[0] => ram_block1a4.PORTBADDR
+address_b[0] => ram_block1a5.PORTBADDR
+address_b[0] => ram_block1a6.PORTBADDR
+address_b[0] => ram_block1a7.PORTBADDR
+address_b[0] => ram_block1a8.PORTBADDR
+address_b[1] => ram_block1a0.PORTBADDR1
+address_b[1] => ram_block1a1.PORTBADDR1
+address_b[1] => ram_block1a2.PORTBADDR1
+address_b[1] => ram_block1a3.PORTBADDR1
+address_b[1] => ram_block1a4.PORTBADDR1
+address_b[1] => ram_block1a5.PORTBADDR1
+address_b[1] => ram_block1a6.PORTBADDR1
+address_b[1] => ram_block1a7.PORTBADDR1
+address_b[1] => ram_block1a8.PORTBADDR1
+address_b[2] => ram_block1a0.PORTBADDR2
+address_b[2] => ram_block1a1.PORTBADDR2
+address_b[2] => ram_block1a2.PORTBADDR2
+address_b[2] => ram_block1a3.PORTBADDR2
+address_b[2] => ram_block1a4.PORTBADDR2
+address_b[2] => ram_block1a5.PORTBADDR2
+address_b[2] => ram_block1a6.PORTBADDR2
+address_b[2] => ram_block1a7.PORTBADDR2
+address_b[2] => ram_block1a8.PORTBADDR2
+address_b[3] => ram_block1a0.PORTBADDR3
+address_b[3] => ram_block1a1.PORTBADDR3
+address_b[3] => ram_block1a2.PORTBADDR3
+address_b[3] => ram_block1a3.PORTBADDR3
+address_b[3] => ram_block1a4.PORTBADDR3
+address_b[3] => ram_block1a5.PORTBADDR3
+address_b[3] => ram_block1a6.PORTBADDR3
+address_b[3] => ram_block1a7.PORTBADDR3
+address_b[3] => ram_block1a8.PORTBADDR3
+address_b[4] => ram_block1a0.PORTBADDR4
+address_b[4] => ram_block1a1.PORTBADDR4
+address_b[4] => ram_block1a2.PORTBADDR4
+address_b[4] => ram_block1a3.PORTBADDR4
+address_b[4] => ram_block1a4.PORTBADDR4
+address_b[4] => ram_block1a5.PORTBADDR4
+address_b[4] => ram_block1a6.PORTBADDR4
+address_b[4] => ram_block1a7.PORTBADDR4
+address_b[4] => ram_block1a8.PORTBADDR4
+address_b[5] => ram_block1a0.PORTBADDR5
+address_b[5] => ram_block1a1.PORTBADDR5
+address_b[5] => ram_block1a2.PORTBADDR5
+address_b[5] => ram_block1a3.PORTBADDR5
+address_b[5] => ram_block1a4.PORTBADDR5
+address_b[5] => ram_block1a5.PORTBADDR5
+address_b[5] => ram_block1a6.PORTBADDR5
+address_b[5] => ram_block1a7.PORTBADDR5
+address_b[5] => ram_block1a8.PORTBADDR5
+address_b[6] => ram_block1a0.PORTBADDR6
+address_b[6] => ram_block1a1.PORTBADDR6
+address_b[6] => ram_block1a2.PORTBADDR6
+address_b[6] => ram_block1a3.PORTBADDR6
+address_b[6] => ram_block1a4.PORTBADDR6
+address_b[6] => ram_block1a5.PORTBADDR6
+address_b[6] => ram_block1a6.PORTBADDR6
+address_b[6] => ram_block1a7.PORTBADDR6
+address_b[6] => ram_block1a8.PORTBADDR6
+address_b[7] => ram_block1a0.PORTBADDR7
+address_b[7] => ram_block1a1.PORTBADDR7
+address_b[7] => ram_block1a2.PORTBADDR7
+address_b[7] => ram_block1a3.PORTBADDR7
+address_b[7] => ram_block1a4.PORTBADDR7
+address_b[7] => ram_block1a5.PORTBADDR7
+address_b[7] => ram_block1a6.PORTBADDR7
+address_b[7] => ram_block1a7.PORTBADDR7
+address_b[7] => ram_block1a8.PORTBADDR7
+address_b[8] => ram_block1a0.PORTBADDR8
+address_b[8] => ram_block1a1.PORTBADDR8
+address_b[8] => ram_block1a2.PORTBADDR8
+address_b[8] => ram_block1a3.PORTBADDR8
+address_b[8] => ram_block1a4.PORTBADDR8
+address_b[8] => ram_block1a5.PORTBADDR8
+address_b[8] => ram_block1a6.PORTBADDR8
+address_b[8] => ram_block1a7.PORTBADDR8
+address_b[8] => ram_block1a8.PORTBADDR8
+address_b[9] => ram_block1a0.PORTBADDR9
+address_b[9] => ram_block1a1.PORTBADDR9
+address_b[9] => ram_block1a2.PORTBADDR9
+address_b[9] => ram_block1a3.PORTBADDR9
+address_b[9] => ram_block1a4.PORTBADDR9
+address_b[9] => ram_block1a5.PORTBADDR9
+address_b[9] => ram_block1a6.PORTBADDR9
+address_b[9] => ram_block1a7.PORTBADDR9
+address_b[9] => ram_block1a8.PORTBADDR9
+address_b[10] => ram_block1a0.PORTBADDR10
+address_b[10] => ram_block1a1.PORTBADDR10
+address_b[10] => ram_block1a2.PORTBADDR10
+address_b[10] => ram_block1a3.PORTBADDR10
+address_b[10] => ram_block1a4.PORTBADDR10
+address_b[10] => ram_block1a5.PORTBADDR10
+address_b[10] => ram_block1a6.PORTBADDR10
+address_b[10] => ram_block1a7.PORTBADDR10
+address_b[10] => ram_block1a8.PORTBADDR10
+address_b[11] => ram_block1a0.PORTBADDR11
+address_b[11] => ram_block1a1.PORTBADDR11
+address_b[11] => ram_block1a2.PORTBADDR11
+address_b[11] => ram_block1a3.PORTBADDR11
+address_b[11] => ram_block1a4.PORTBADDR11
+address_b[11] => ram_block1a5.PORTBADDR11
+address_b[11] => ram_block1a6.PORTBADDR11
+address_b[11] => ram_block1a7.PORTBADDR11
+address_b[11] => ram_block1a8.PORTBADDR11
+address_b[12] => ram_block1a0.PORTBADDR12
+address_b[12] => ram_block1a1.PORTBADDR12
+address_b[12] => ram_block1a2.PORTBADDR12
+address_b[12] => ram_block1a3.PORTBADDR12
+address_b[12] => ram_block1a4.PORTBADDR12
+address_b[12] => ram_block1a5.PORTBADDR12
+address_b[12] => ram_block1a6.PORTBADDR12
+address_b[12] => ram_block1a7.PORTBADDR12
+address_b[12] => ram_block1a8.PORTBADDR12
+clock0 => ram_block1a0.CLK0
+clock0 => ram_block1a0.CLK1
+clock0 => ram_block1a1.CLK0
+clock0 => ram_block1a1.CLK1
+clock0 => ram_block1a2.CLK0
+clock0 => ram_block1a2.CLK1
+clock0 => ram_block1a3.CLK0
+clock0 => ram_block1a3.CLK1
+clock0 => ram_block1a4.CLK0
+clock0 => ram_block1a4.CLK1
+clock0 => ram_block1a5.CLK0
+clock0 => ram_block1a5.CLK1
+clock0 => ram_block1a6.CLK0
+clock0 => ram_block1a6.CLK1
+clock0 => ram_block1a7.CLK0
+clock0 => ram_block1a7.CLK1
+clock0 => ram_block1a8.CLK0
+clock0 => ram_block1a8.CLK1
+data_a[0] => ram_block1a0.PORTADATAIN
+data_a[1] => ram_block1a1.PORTADATAIN
+data_a[2] => ram_block1a2.PORTADATAIN
+data_a[3] => ram_block1a3.PORTADATAIN
+data_a[4] => ram_block1a4.PORTADATAIN
+data_a[5] => ram_block1a5.PORTADATAIN
+data_a[6] => ram_block1a6.PORTADATAIN
+data_a[7] => ram_block1a7.PORTADATAIN
+data_a[8] => ram_block1a8.PORTADATAIN
+q_b[0] <= ram_block1a0.PORTBDATAOUT
+q_b[1] <= ram_block1a1.PORTBDATAOUT
+q_b[2] <= ram_block1a2.PORTBDATAOUT
+q_b[3] <= ram_block1a3.PORTBDATAOUT
+q_b[4] <= ram_block1a4.PORTBDATAOUT
+q_b[5] <= ram_block1a5.PORTBDATAOUT
+q_b[6] <= ram_block1a6.PORTBDATAOUT
+q_b[7] <= ram_block1a7.PORTBDATAOUT
+q_b[8] <= ram_block1a8.PORTBDATAOUT
+rden_b => ram_block1a0.ENA1
+rden_b => ram_block1a1.ENA1
+rden_b => ram_block1a2.ENA1
+rden_b => ram_block1a3.ENA1
+rden_b => ram_block1a4.ENA1
+rden_b => ram_block1a5.ENA1
+rden_b => ram_block1a6.ENA1
+rden_b => ram_block1a7.ENA1
+rden_b => ram_block1a8.ENA1
+wren_a => ram_block1a0.PORTAWE
+wren_a => ram_block1a0.ENA0
+wren_a => ram_block1a1.PORTAWE
+wren_a => ram_block1a1.ENA0
+wren_a => ram_block1a2.PORTAWE
+wren_a => ram_block1a2.ENA0
+wren_a => ram_block1a3.PORTAWE
+wren_a => ram_block1a3.ENA0
+wren_a => ram_block1a4.PORTAWE
+wren_a => ram_block1a4.ENA0
+wren_a => ram_block1a5.PORTAWE
+wren_a => ram_block1a5.ENA0
+wren_a => ram_block1a6.PORTAWE
+wren_a => ram_block1a6.ENA0
+wren_a => ram_block1a7.PORTAWE
+wren_a => ram_block1a7.ENA0
+wren_a => ram_block1a8.PORTAWE
+wren_a => ram_block1a8.ENA0
+
+
+|ex19|processor:echo_var_delay|div_by_2:comb_6
+in[0] => ~NO_FANOUT~
+in[1] => out[0].DATAIN
+in[2] => out[1].DATAIN
+in[3] => out[2].DATAIN
+in[4] => out[3].DATAIN
+in[5] => out[4].DATAIN
+in[6] => out[5].DATAIN
+in[7] => out[6].DATAIN
+in[8] => out[7].DATAIN
+in[9] => out[8].DATAIN
+in[9] => out[9].DATAIN
+out[0] <= in[1].DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= in[2].DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= in[3].DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= in[4].DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= in[5].DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= in[6].DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= in[7].DB_MAX_OUTPUT_PORT_TYPE
+out[7] <= in[8].DB_MAX_OUTPUT_PORT_TYPE
+out[8] <= in[9].DB_MAX_OUTPUT_PORT_TYPE
+out[9] <= in[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666
+dataa[0] => dataa[0].IN1
+dataa[1] => dataa[1].IN1
+dataa[2] => dataa[2].IN1
+dataa[3] => dataa[3].IN1
+dataa[4] => dataa[4].IN1
+dataa[5] => dataa[5].IN1
+dataa[6] => dataa[6].IN1
+dataa[7] => dataa[7].IN1
+dataa[8] => dataa[8].IN1
+result[0] <= lpm_mult:lpm_mult_component.result
+result[1] <= lpm_mult:lpm_mult_component.result
+result[2] <= lpm_mult:lpm_mult_component.result
+result[3] <= lpm_mult:lpm_mult_component.result
+result[4] <= lpm_mult:lpm_mult_component.result
+result[5] <= lpm_mult:lpm_mult_component.result
+result[6] <= lpm_mult:lpm_mult_component.result
+result[7] <= lpm_mult:lpm_mult_component.result
+result[8] <= lpm_mult:lpm_mult_component.result
+result[9] <= lpm_mult:lpm_mult_component.result
+result[10] <= lpm_mult:lpm_mult_component.result
+result[11] <= lpm_mult:lpm_mult_component.result
+result[12] <= lpm_mult:lpm_mult_component.result
+result[13] <= lpm_mult:lpm_mult_component.result
+result[14] <= lpm_mult:lpm_mult_component.result
+result[15] <= lpm_mult:lpm_mult_component.result
+result[16] <= lpm_mult:lpm_mult_component.result
+result[17] <= lpm_mult:lpm_mult_component.result
+result[18] <= lpm_mult:lpm_mult_component.result
+result[19] <= lpm_mult:lpm_mult_component.result
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component
+dataa[0] => multcore:mult_core.dataa[0]
+dataa[1] => multcore:mult_core.dataa[1]
+dataa[2] => multcore:mult_core.dataa[2]
+dataa[3] => multcore:mult_core.dataa[3]
+dataa[4] => multcore:mult_core.dataa[4]
+dataa[5] => multcore:mult_core.dataa[5]
+dataa[6] => multcore:mult_core.dataa[6]
+dataa[7] => multcore:mult_core.dataa[7]
+dataa[8] => multcore:mult_core.dataa[8]
+datab[0] => multcore:mult_core.datab[0]
+datab[1] => multcore:mult_core.datab[1]
+datab[2] => multcore:mult_core.datab[2]
+datab[3] => multcore:mult_core.datab[3]
+datab[4] => multcore:mult_core.datab[4]
+datab[5] => multcore:mult_core.datab[5]
+datab[6] => multcore:mult_core.datab[6]
+datab[7] => multcore:mult_core.datab[7]
+datab[8] => multcore:mult_core.datab[8]
+datab[9] => multcore:mult_core.datab[9]
+datab[10] => multcore:mult_core.datab[10]
+sum[0] => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+sclr => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= altshift:external_latency_ffs.result[0]
+result[1] <= altshift:external_latency_ffs.result[1]
+result[2] <= altshift:external_latency_ffs.result[2]
+result[3] <= altshift:external_latency_ffs.result[3]
+result[4] <= altshift:external_latency_ffs.result[4]
+result[5] <= altshift:external_latency_ffs.result[5]
+result[6] <= altshift:external_latency_ffs.result[6]
+result[7] <= altshift:external_latency_ffs.result[7]
+result[8] <= altshift:external_latency_ffs.result[8]
+result[9] <= altshift:external_latency_ffs.result[9]
+result[10] <= altshift:external_latency_ffs.result[10]
+result[11] <= altshift:external_latency_ffs.result[11]
+result[12] <= altshift:external_latency_ffs.result[12]
+result[13] <= altshift:external_latency_ffs.result[13]
+result[14] <= altshift:external_latency_ffs.result[14]
+result[15] <= altshift:external_latency_ffs.result[15]
+result[16] <= altshift:external_latency_ffs.result[16]
+result[17] <= altshift:external_latency_ffs.result[17]
+result[18] <= altshift:external_latency_ffs.result[18]
+result[19] <= altshift:external_latency_ffs.result[19]
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[0] => _.IN0
+dataa[0] => _.IN3
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[1] => _.IN0
+dataa[1] => _.IN0
+dataa[1] => _.IN2
+dataa[1] => _.IN2
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN0
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[2] => _.IN1
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[3] => _.IN0
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[4] => _.IN0
+dataa[4] => _.IN3
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[5] => _.IN0
+dataa[5] => _.IN0
+dataa[5] => _.IN2
+dataa[5] => _.IN2
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN0
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[6] => _.IN1
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[7] => _.IN0
+dataa[8] => ina_reg_clkd[0].IN0
+datab[0] => op_1.IN28
+datab[0] => op_2.IN29
+datab[0] => op_4.IN29
+datab[0] => op_5.IN29
+datab[0] => op_6.IN29
+datab[0] => op_7.IN29
+datab[0] => op_8.IN29
+datab[0] => op_9.IN29
+datab[0] => op_10.IN29
+datab[0] => op_11.IN29
+datab[0] => romout[0][0].IN1
+datab[0] => romout[1][0].IN1
+datab[0] => op_1.IN27
+datab[0] => op_3.IN27
+datab[0] => romout[0][1].IN1
+datab[0] => romout[1][1].IN1
+datab[0] => op_2.IN24
+datab[0] => op_3.IN24
+datab[0] => romout[0][2].IN1
+datab[0] => romout[1][2].IN1
+datab[0] => op_5.IN22
+datab[0] => romout[0][3].IN1
+datab[0] => romout[1][3].IN1
+datab[0] => romout[2][0].IN1
+datab[0] => romout[2][1].IN1
+datab[0] => romout[2][2].IN1
+datab[0] => romout[2][3].IN1
+datab[1] => op_1.IN26
+datab[1] => op_2.IN27
+datab[1] => op_4.IN27
+datab[1] => op_5.IN27
+datab[1] => op_6.IN27
+datab[1] => op_7.IN27
+datab[1] => op_8.IN27
+datab[1] => op_9.IN27
+datab[1] => op_10.IN27
+datab[1] => op_11.IN27
+datab[1] => romout[0][1].IN1
+datab[1] => romout[1][1].IN1
+datab[1] => op_1.IN25
+datab[1] => op_3.IN25
+datab[1] => romout[0][2].IN1
+datab[1] => romout[1][2].IN1
+datab[1] => op_2.IN22
+datab[1] => op_3.IN22
+datab[1] => romout[0][3].IN1
+datab[1] => romout[1][3].IN1
+datab[1] => op_5.IN20
+datab[1] => romout[0][4].IN1
+datab[1] => romout[1][4].IN1
+datab[1] => romout[2][1].IN1
+datab[1] => romout[2][2].IN1
+datab[1] => romout[2][3].IN1
+datab[1] => romout[2][4].IN1
+datab[2] => op_1.IN24
+datab[2] => op_2.IN25
+datab[2] => op_4.IN25
+datab[2] => op_5.IN25
+datab[2] => op_6.IN25
+datab[2] => op_7.IN25
+datab[2] => op_8.IN25
+datab[2] => op_9.IN25
+datab[2] => op_10.IN25
+datab[2] => op_11.IN25
+datab[2] => romout[0][2].IN1
+datab[2] => romout[1][2].IN1
+datab[2] => op_1.IN23
+datab[2] => op_3.IN23
+datab[2] => romout[0][3].IN1
+datab[2] => romout[1][3].IN1
+datab[2] => op_2.IN20
+datab[2] => op_3.IN20
+datab[2] => romout[0][4].IN1
+datab[2] => romout[1][4].IN1
+datab[2] => op_5.IN18
+datab[2] => romout[0][5].IN1
+datab[2] => romout[1][5].IN1
+datab[2] => romout[2][2].IN1
+datab[2] => romout[2][3].IN1
+datab[2] => romout[2][4].IN1
+datab[2] => romout[2][5].IN1
+datab[3] => op_1.IN22
+datab[3] => op_2.IN23
+datab[3] => op_4.IN23
+datab[3] => op_5.IN23
+datab[3] => op_6.IN23
+datab[3] => op_7.IN23
+datab[3] => op_8.IN23
+datab[3] => op_9.IN23
+datab[3] => op_10.IN23
+datab[3] => op_11.IN23
+datab[3] => romout[0][3].IN1
+datab[3] => romout[1][3].IN1
+datab[3] => op_1.IN21
+datab[3] => op_3.IN21
+datab[3] => romout[0][4].IN1
+datab[3] => romout[1][4].IN1
+datab[3] => op_2.IN18
+datab[3] => op_3.IN18
+datab[3] => romout[0][5].IN1
+datab[3] => romout[1][5].IN1
+datab[3] => op_5.IN16
+datab[3] => romout[0][6].IN1
+datab[3] => romout[1][6].IN1
+datab[3] => romout[2][3].IN1
+datab[3] => romout[2][4].IN1
+datab[3] => romout[2][5].IN1
+datab[3] => romout[2][6].IN1
+datab[4] => op_1.IN20
+datab[4] => op_2.IN21
+datab[4] => op_4.IN21
+datab[4] => op_5.IN21
+datab[4] => op_6.IN21
+datab[4] => op_7.IN21
+datab[4] => op_8.IN21
+datab[4] => op_9.IN21
+datab[4] => op_10.IN21
+datab[4] => op_11.IN21
+datab[4] => romout[0][4].IN1
+datab[4] => romout[1][4].IN1
+datab[4] => op_1.IN19
+datab[4] => op_3.IN19
+datab[4] => romout[0][5].IN1
+datab[4] => romout[1][5].IN1
+datab[4] => op_2.IN16
+datab[4] => op_3.IN16
+datab[4] => romout[0][6].IN1
+datab[4] => romout[1][6].IN1
+datab[4] => op_5.IN14
+datab[4] => romout[0][7].IN1
+datab[4] => romout[1][7].IN1
+datab[4] => romout[2][4].IN1
+datab[4] => romout[2][5].IN1
+datab[4] => romout[2][6].IN1
+datab[4] => romout[2][7].IN1
+datab[5] => op_1.IN18
+datab[5] => op_2.IN19
+datab[5] => op_4.IN19
+datab[5] => op_5.IN19
+datab[5] => op_6.IN19
+datab[5] => op_7.IN19
+datab[5] => op_8.IN19
+datab[5] => op_9.IN19
+datab[5] => op_10.IN19
+datab[5] => op_11.IN19
+datab[5] => romout[0][5].IN1
+datab[5] => romout[1][5].IN1
+datab[5] => op_1.IN17
+datab[5] => op_3.IN17
+datab[5] => romout[0][6].IN1
+datab[5] => romout[1][6].IN1
+datab[5] => op_2.IN14
+datab[5] => op_3.IN14
+datab[5] => romout[0][7].IN1
+datab[5] => romout[1][7].IN1
+datab[5] => op_5.IN12
+datab[5] => romout[0][8].IN1
+datab[5] => romout[1][8].IN1
+datab[5] => romout[2][5].IN1
+datab[5] => romout[2][6].IN1
+datab[5] => romout[2][7].IN1
+datab[5] => romout[2][8].IN1
+datab[6] => op_1.IN16
+datab[6] => op_2.IN17
+datab[6] => op_4.IN17
+datab[6] => op_5.IN17
+datab[6] => op_6.IN17
+datab[6] => op_7.IN17
+datab[6] => op_8.IN17
+datab[6] => op_9.IN17
+datab[6] => op_10.IN17
+datab[6] => op_11.IN17
+datab[6] => romout[0][6].IN1
+datab[6] => romout[1][6].IN1
+datab[6] => op_1.IN15
+datab[6] => op_3.IN15
+datab[6] => romout[0][7].IN1
+datab[6] => romout[1][7].IN1
+datab[6] => op_2.IN12
+datab[6] => op_3.IN12
+datab[6] => romout[0][8].IN1
+datab[6] => romout[1][8].IN1
+datab[6] => op_5.IN10
+datab[6] => romout[0][9].IN1
+datab[6] => romout[1][9].IN1
+datab[6] => romout[2][6].IN1
+datab[6] => romout[2][7].IN1
+datab[6] => romout[2][8].IN1
+datab[6] => romout[2][9].IN1
+datab[7] => op_1.IN14
+datab[7] => op_2.IN15
+datab[7] => op_4.IN15
+datab[7] => op_5.IN15
+datab[7] => op_6.IN15
+datab[7] => op_7.IN15
+datab[7] => op_8.IN15
+datab[7] => op_9.IN15
+datab[7] => op_10.IN15
+datab[7] => op_11.IN15
+datab[7] => romout[0][7].IN1
+datab[7] => romout[1][7].IN1
+datab[7] => op_1.IN13
+datab[7] => op_3.IN13
+datab[7] => romout[0][8].IN1
+datab[7] => romout[1][8].IN1
+datab[7] => op_2.IN10
+datab[7] => op_3.IN10
+datab[7] => romout[0][9].IN1
+datab[7] => romout[1][9].IN1
+datab[7] => op_5.IN8
+datab[7] => romout[0][10].IN1
+datab[7] => romout[1][10].IN1
+datab[7] => romout[2][7].IN1
+datab[7] => romout[2][8].IN1
+datab[7] => romout[2][9].IN1
+datab[7] => romout[2][10].IN1
+datab[8] => op_1.IN12
+datab[8] => op_2.IN13
+datab[8] => op_4.IN13
+datab[8] => op_5.IN13
+datab[8] => op_6.IN13
+datab[8] => op_7.IN13
+datab[8] => op_8.IN13
+datab[8] => op_9.IN13
+datab[8] => op_10.IN13
+datab[8] => op_11.IN13
+datab[8] => romout[0][8].IN1
+datab[8] => romout[1][8].IN1
+datab[8] => op_1.IN11
+datab[8] => op_3.IN11
+datab[8] => romout[0][9].IN1
+datab[8] => romout[1][9].IN1
+datab[8] => op_2.IN8
+datab[8] => op_3.IN8
+datab[8] => romout[0][10].IN1
+datab[8] => romout[1][10].IN1
+datab[8] => op_5.IN6
+datab[8] => romout[0][11].IN1
+datab[8] => romout[1][11].IN1
+datab[8] => romout[2][8].IN1
+datab[8] => romout[2][9].IN1
+datab[8] => romout[2][10].IN1
+datab[8] => romout[2][11].IN1
+datab[9] => op_1.IN10
+datab[9] => op_2.IN11
+datab[9] => op_4.IN11
+datab[9] => op_5.IN11
+datab[9] => op_6.IN11
+datab[9] => op_7.IN11
+datab[9] => op_8.IN11
+datab[9] => op_9.IN11
+datab[9] => op_10.IN11
+datab[9] => op_11.IN11
+datab[9] => romout[0][9].IN1
+datab[9] => romout[1][9].IN1
+datab[9] => op_1.IN9
+datab[9] => op_3.IN9
+datab[9] => romout[0][10].IN1
+datab[9] => romout[1][10].IN1
+datab[9] => op_2.IN6
+datab[9] => op_3.IN6
+datab[9] => romout[0][11].IN1
+datab[9] => romout[1][11].IN1
+datab[9] => op_5.IN4
+datab[9] => romout[0][12].IN1
+datab[9] => romout[1][12].IN1
+datab[9] => romout[2][9].IN1
+datab[9] => romout[2][10].IN1
+datab[9] => romout[2][11].IN1
+datab[9] => romout[2][12].IN1
+datab[10] => op_1.IN8
+datab[10] => op_2.IN9
+datab[10] => op_4.IN9
+datab[10] => op_5.IN9
+datab[10] => op_6.IN9
+datab[10] => op_7.IN9
+datab[10] => op_8.IN9
+datab[10] => op_9.IN9
+datab[10] => op_10.IN9
+datab[10] => op_11.IN9
+datab[10] => romout[0][10].IN1
+datab[10] => romout[1][10].IN1
+datab[10] => op_1.IN7
+datab[10] => op_3.IN7
+datab[10] => romout[0][11].IN1
+datab[10] => romout[1][11].IN1
+datab[10] => op_2.IN4
+datab[10] => op_3.IN4
+datab[10] => romout[0][12].IN1
+datab[10] => romout[1][12].IN1
+datab[10] => op_5.IN2
+datab[10] => romout[0][13].IN1
+datab[10] => romout[1][13].IN1
+datab[10] => romout[2][10].IN1
+datab[10] => romout[2][11].IN1
+datab[10] => romout[2][12].IN1
+datab[10] => romout[2][13].IN1
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mpar_add:padder.result[0]
+result[1] <= mpar_add:padder.result[1]
+result[2] <= mpar_add:padder.result[2]
+result[3] <= mpar_add:padder.result[3]
+result[4] <= mpar_add:padder.result[4]
+result[5] <= mpar_add:padder.result[5]
+result[6] <= mpar_add:padder.result[6]
+result[7] <= mpar_add:padder.result[7]
+result[8] <= mpar_add:padder.result[8]
+result[9] <= mpar_add:padder.result[9]
+result[10] <= mpar_add:padder.result[10]
+result[11] <= mpar_add:padder.result[11]
+result[12] <= mpar_add:padder.result[12]
+result[13] <= mpar_add:padder.result[13]
+result[14] <= mpar_add:padder.result[14]
+result[15] <= mpar_add:padder.result[15]
+result[16] <= mpar_add:padder.result[16]
+result[17] <= mpar_add:padder.result[17]
+result[18] <= mpar_add:padder.result[18]
+result[19] <= mpar_add:padder.result[19]
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder
+data[0][0] => mpar_add:sub_par_add.data[0][0]
+data[0][1] => mpar_add:sub_par_add.data[0][1]
+data[0][2] => mpar_add:sub_par_add.data[0][2]
+data[0][3] => mpar_add:sub_par_add.data[0][3]
+data[0][4] => lpm_add_sub:adder[0].dataa[0]
+data[0][5] => lpm_add_sub:adder[0].dataa[1]
+data[0][6] => lpm_add_sub:adder[0].dataa[2]
+data[0][7] => lpm_add_sub:adder[0].dataa[3]
+data[0][8] => lpm_add_sub:adder[0].dataa[4]
+data[0][9] => lpm_add_sub:adder[0].dataa[5]
+data[0][10] => lpm_add_sub:adder[0].dataa[6]
+data[0][11] => lpm_add_sub:adder[0].dataa[7]
+data[0][12] => lpm_add_sub:adder[0].dataa[8]
+data[0][13] => lpm_add_sub:adder[0].dataa[9]
+data[0][14] => lpm_add_sub:adder[0].dataa[10]
+data[1][0] => lpm_add_sub:adder[0].datab[0]
+data[1][1] => lpm_add_sub:adder[0].datab[1]
+data[1][2] => lpm_add_sub:adder[0].datab[2]
+data[1][3] => lpm_add_sub:adder[0].datab[3]
+data[1][4] => lpm_add_sub:adder[0].datab[4]
+data[1][5] => lpm_add_sub:adder[0].datab[5]
+data[1][6] => lpm_add_sub:adder[0].datab[6]
+data[1][7] => lpm_add_sub:adder[0].datab[7]
+data[1][8] => lpm_add_sub:adder[0].datab[8]
+data[1][9] => lpm_add_sub:adder[0].datab[9]
+data[1][10] => lpm_add_sub:adder[0].datab[10]
+data[1][11] => lpm_add_sub:adder[0].datab[11]
+data[1][12] => lpm_add_sub:adder[0].datab[12]
+data[1][13] => lpm_add_sub:adder[0].datab[13]
+data[1][14] => lpm_add_sub:adder[0].datab[14]
+data[2][0] => mpar_add:sub_par_add.data[1][0]
+data[2][1] => mpar_add:sub_par_add.data[1][1]
+data[2][2] => mpar_add:sub_par_add.data[1][2]
+data[2][3] => mpar_add:sub_par_add.data[1][3]
+data[2][4] => mpar_add:sub_par_add.data[1][4]
+data[2][5] => mpar_add:sub_par_add.data[1][5]
+data[2][6] => mpar_add:sub_par_add.data[1][6]
+data[2][7] => mpar_add:sub_par_add.data[1][7]
+data[2][8] => mpar_add:sub_par_add.data[1][8]
+data[2][9] => mpar_add:sub_par_add.data[1][9]
+data[2][10] => mpar_add:sub_par_add.data[1][10]
+data[2][11] => mpar_add:sub_par_add.data[1][11]
+data[2][12] => mpar_add:sub_par_add.data[1][12]
+data[2][13] => mpar_add:sub_par_add.data[1][13]
+data[2][14] => mpar_add:sub_par_add.data[1][14]
+cin => ~NO_FANOUT~
+clk => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mpar_add:sub_par_add.result[0]
+result[1] <= mpar_add:sub_par_add.result[1]
+result[2] <= mpar_add:sub_par_add.result[2]
+result[3] <= mpar_add:sub_par_add.result[3]
+result[4] <= mpar_add:sub_par_add.result[4]
+result[5] <= mpar_add:sub_par_add.result[5]
+result[6] <= mpar_add:sub_par_add.result[6]
+result[7] <= mpar_add:sub_par_add.result[7]
+result[8] <= mpar_add:sub_par_add.result[8]
+result[9] <= mpar_add:sub_par_add.result[9]
+result[10] <= mpar_add:sub_par_add.result[10]
+result[11] <= mpar_add:sub_par_add.result[11]
+result[12] <= mpar_add:sub_par_add.result[12]
+result[13] <= mpar_add:sub_par_add.result[13]
+result[14] <= mpar_add:sub_par_add.result[14]
+result[15] <= mpar_add:sub_par_add.result[15]
+result[16] <= mpar_add:sub_par_add.result[16]
+result[17] <= mpar_add:sub_par_add.result[17]
+result[18] <= mpar_add:sub_par_add.result[18]
+result[19] <= mpar_add:sub_par_add.result[19]
+result[20] <= mpar_add:sub_par_add.result[20]
+result[21] <= mpar_add:sub_par_add.result[21]
+result[22] <= mpar_add:sub_par_add.result[22]
+result[23] <= mpar_add:sub_par_add.result[23]
+result[24] <= mpar_add:sub_par_add.result[24]
+result[25] <= mpar_add:sub_par_add.result[25]
+result[26] <= mpar_add:sub_par_add.result[26]
+clk_out <= <GND>
+aclr_out <= <GND>
+clken_out <= <GND>
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]
+dataa[0] => add_sub_a9h:auto_generated.dataa[0]
+dataa[1] => add_sub_a9h:auto_generated.dataa[1]
+dataa[2] => add_sub_a9h:auto_generated.dataa[2]
+dataa[3] => add_sub_a9h:auto_generated.dataa[3]
+dataa[4] => add_sub_a9h:auto_generated.dataa[4]
+dataa[5] => add_sub_a9h:auto_generated.dataa[5]
+dataa[6] => add_sub_a9h:auto_generated.dataa[6]
+dataa[7] => add_sub_a9h:auto_generated.dataa[7]
+dataa[8] => add_sub_a9h:auto_generated.dataa[8]
+dataa[9] => add_sub_a9h:auto_generated.dataa[9]
+dataa[10] => add_sub_a9h:auto_generated.dataa[10]
+dataa[11] => add_sub_a9h:auto_generated.dataa[11]
+dataa[12] => add_sub_a9h:auto_generated.dataa[12]
+dataa[13] => add_sub_a9h:auto_generated.dataa[13]
+dataa[14] => add_sub_a9h:auto_generated.dataa[14]
+datab[0] => add_sub_a9h:auto_generated.datab[0]
+datab[1] => add_sub_a9h:auto_generated.datab[1]
+datab[2] => add_sub_a9h:auto_generated.datab[2]
+datab[3] => add_sub_a9h:auto_generated.datab[3]
+datab[4] => add_sub_a9h:auto_generated.datab[4]
+datab[5] => add_sub_a9h:auto_generated.datab[5]
+datab[6] => add_sub_a9h:auto_generated.datab[6]
+datab[7] => add_sub_a9h:auto_generated.datab[7]
+datab[8] => add_sub_a9h:auto_generated.datab[8]
+datab[9] => add_sub_a9h:auto_generated.datab[9]
+datab[10] => add_sub_a9h:auto_generated.datab[10]
+datab[11] => add_sub_a9h:auto_generated.datab[11]
+datab[12] => add_sub_a9h:auto_generated.datab[12]
+datab[13] => add_sub_a9h:auto_generated.datab[13]
+datab[14] => add_sub_a9h:auto_generated.datab[14]
+cin => ~NO_FANOUT~
+add_sub => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= add_sub_a9h:auto_generated.result[0]
+result[1] <= add_sub_a9h:auto_generated.result[1]
+result[2] <= add_sub_a9h:auto_generated.result[2]
+result[3] <= add_sub_a9h:auto_generated.result[3]
+result[4] <= add_sub_a9h:auto_generated.result[4]
+result[5] <= add_sub_a9h:auto_generated.result[5]
+result[6] <= add_sub_a9h:auto_generated.result[6]
+result[7] <= add_sub_a9h:auto_generated.result[7]
+result[8] <= add_sub_a9h:auto_generated.result[8]
+result[9] <= add_sub_a9h:auto_generated.result[9]
+result[10] <= add_sub_a9h:auto_generated.result[10]
+result[11] <= add_sub_a9h:auto_generated.result[11]
+result[12] <= add_sub_a9h:auto_generated.result[12]
+result[13] <= add_sub_a9h:auto_generated.result[13]
+result[14] <= add_sub_a9h:auto_generated.result[14]
+cout <= <GND>
+overflow <= <GND>
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated
+dataa[0] => op_1.IN28
+dataa[1] => op_1.IN26
+dataa[2] => op_1.IN24
+dataa[3] => op_1.IN22
+dataa[4] => op_1.IN20
+dataa[5] => op_1.IN18
+dataa[6] => op_1.IN16
+dataa[7] => op_1.IN14
+dataa[8] => op_1.IN12
+dataa[9] => op_1.IN10
+dataa[10] => op_1.IN8
+dataa[11] => op_1.IN6
+dataa[12] => op_1.IN4
+dataa[13] => op_1.IN2
+dataa[14] => op_1.IN0
+datab[0] => op_1.IN29
+datab[1] => op_1.IN27
+datab[2] => op_1.IN25
+datab[3] => op_1.IN23
+datab[4] => op_1.IN21
+datab[5] => op_1.IN19
+datab[6] => op_1.IN17
+datab[7] => op_1.IN15
+datab[8] => op_1.IN13
+datab[9] => op_1.IN11
+datab[10] => op_1.IN9
+datab[11] => op_1.IN7
+datab[12] => op_1.IN5
+datab[13] => op_1.IN3
+datab[14] => op_1.IN1
+result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add
+data[0][0] => result[0].DATAIN
+data[0][1] => result[1].DATAIN
+data[0][2] => result[2].DATAIN
+data[0][3] => result[3].DATAIN
+data[0][4] => result[4].DATAIN
+data[0][5] => result[5].DATAIN
+data[0][6] => result[6].DATAIN
+data[0][7] => result[7].DATAIN
+data[0][8] => lpm_add_sub:adder[0].dataa[0]
+data[0][9] => lpm_add_sub:adder[0].dataa[1]
+data[0][10] => lpm_add_sub:adder[0].dataa[2]
+data[0][11] => lpm_add_sub:adder[0].dataa[3]
+data[0][12] => lpm_add_sub:adder[0].dataa[4]
+data[0][13] => lpm_add_sub:adder[0].dataa[5]
+data[0][14] => lpm_add_sub:adder[0].dataa[6]
+data[0][15] => lpm_add_sub:adder[0].dataa[7]
+data[0][16] => lpm_add_sub:adder[0].dataa[8]
+data[0][17] => lpm_add_sub:adder[0].dataa[9]
+data[0][18] => lpm_add_sub:adder[0].dataa[10]
+data[1][0] => lpm_add_sub:adder[0].datab[0]
+data[1][1] => lpm_add_sub:adder[0].datab[1]
+data[1][2] => lpm_add_sub:adder[0].datab[2]
+data[1][3] => lpm_add_sub:adder[0].datab[3]
+data[1][4] => lpm_add_sub:adder[0].datab[4]
+data[1][5] => lpm_add_sub:adder[0].datab[5]
+data[1][6] => lpm_add_sub:adder[0].datab[6]
+data[1][7] => lpm_add_sub:adder[0].datab[7]
+data[1][8] => lpm_add_sub:adder[0].datab[8]
+data[1][9] => lpm_add_sub:adder[0].datab[9]
+data[1][10] => lpm_add_sub:adder[0].datab[10]
+data[1][11] => lpm_add_sub:adder[0].datab[11]
+data[1][12] => lpm_add_sub:adder[0].datab[12]
+data[1][13] => lpm_add_sub:adder[0].datab[13]
+data[1][14] => lpm_add_sub:adder[0].datab[14]
+data[1][15] => ~NO_FANOUT~
+data[1][16] => ~NO_FANOUT~
+data[1][17] => ~NO_FANOUT~
+data[1][18] => ~NO_FANOUT~
+cin => ~NO_FANOUT~
+clk => clk_out.IN0
+aclr => aclr_out.IN0
+clken => clken_out.IN0
+result[0] <= data[0][0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= data[0][1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= data[0][2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= data[0][3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= data[0][4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= data[0][5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= data[0][6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= data[0][7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= level_result_node[0][0].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= level_result_node[0][1].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= level_result_node[0][2].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= level_result_node[0][3].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= level_result_node[0][4].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= level_result_node[0][5].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= level_result_node[0][6].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= level_result_node[0][7].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= level_result_node[0][8].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= level_result_node[0][9].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= level_result_node[0][10].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= level_result_node[0][11].DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= level_result_node[0][12].DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= level_result_node[0][13].DB_MAX_OUTPUT_PORT_TYPE
+result[22] <= level_result_node[0][14].DB_MAX_OUTPUT_PORT_TYPE
+result[23] <= level_result_node[0][15].DB_MAX_OUTPUT_PORT_TYPE
+result[24] <= level_result_node[0][16].DB_MAX_OUTPUT_PORT_TYPE
+result[25] <= level_result_node[0][17].DB_MAX_OUTPUT_PORT_TYPE
+result[26] <= level_result_node[0][18].DB_MAX_OUTPUT_PORT_TYPE
+clk_out <= clk_out.DB_MAX_OUTPUT_PORT_TYPE
+aclr_out <= aclr_out.DB_MAX_OUTPUT_PORT_TYPE
+clken_out <= clken_out.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]
+dataa[0] => add_sub_e9h:auto_generated.dataa[0]
+dataa[1] => add_sub_e9h:auto_generated.dataa[1]
+dataa[2] => add_sub_e9h:auto_generated.dataa[2]
+dataa[3] => add_sub_e9h:auto_generated.dataa[3]
+dataa[4] => add_sub_e9h:auto_generated.dataa[4]
+dataa[5] => add_sub_e9h:auto_generated.dataa[5]
+dataa[6] => add_sub_e9h:auto_generated.dataa[6]
+dataa[7] => add_sub_e9h:auto_generated.dataa[7]
+dataa[8] => add_sub_e9h:auto_generated.dataa[8]
+dataa[9] => add_sub_e9h:auto_generated.dataa[9]
+dataa[10] => add_sub_e9h:auto_generated.dataa[10]
+dataa[11] => add_sub_e9h:auto_generated.dataa[11]
+dataa[12] => add_sub_e9h:auto_generated.dataa[12]
+dataa[13] => add_sub_e9h:auto_generated.dataa[13]
+dataa[14] => add_sub_e9h:auto_generated.dataa[14]
+dataa[15] => add_sub_e9h:auto_generated.dataa[15]
+dataa[16] => add_sub_e9h:auto_generated.dataa[16]
+dataa[17] => add_sub_e9h:auto_generated.dataa[17]
+dataa[18] => add_sub_e9h:auto_generated.dataa[18]
+datab[0] => add_sub_e9h:auto_generated.datab[0]
+datab[1] => add_sub_e9h:auto_generated.datab[1]
+datab[2] => add_sub_e9h:auto_generated.datab[2]
+datab[3] => add_sub_e9h:auto_generated.datab[3]
+datab[4] => add_sub_e9h:auto_generated.datab[4]
+datab[5] => add_sub_e9h:auto_generated.datab[5]
+datab[6] => add_sub_e9h:auto_generated.datab[6]
+datab[7] => add_sub_e9h:auto_generated.datab[7]
+datab[8] => add_sub_e9h:auto_generated.datab[8]
+datab[9] => add_sub_e9h:auto_generated.datab[9]
+datab[10] => add_sub_e9h:auto_generated.datab[10]
+datab[11] => add_sub_e9h:auto_generated.datab[11]
+datab[12] => add_sub_e9h:auto_generated.datab[12]
+datab[13] => add_sub_e9h:auto_generated.datab[13]
+datab[14] => add_sub_e9h:auto_generated.datab[14]
+datab[15] => add_sub_e9h:auto_generated.datab[15]
+datab[16] => add_sub_e9h:auto_generated.datab[16]
+datab[17] => add_sub_e9h:auto_generated.datab[17]
+datab[18] => add_sub_e9h:auto_generated.datab[18]
+cin => ~NO_FANOUT~
+add_sub => ~NO_FANOUT~
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= add_sub_e9h:auto_generated.result[0]
+result[1] <= add_sub_e9h:auto_generated.result[1]
+result[2] <= add_sub_e9h:auto_generated.result[2]
+result[3] <= add_sub_e9h:auto_generated.result[3]
+result[4] <= add_sub_e9h:auto_generated.result[4]
+result[5] <= add_sub_e9h:auto_generated.result[5]
+result[6] <= add_sub_e9h:auto_generated.result[6]
+result[7] <= add_sub_e9h:auto_generated.result[7]
+result[8] <= add_sub_e9h:auto_generated.result[8]
+result[9] <= add_sub_e9h:auto_generated.result[9]
+result[10] <= add_sub_e9h:auto_generated.result[10]
+result[11] <= add_sub_e9h:auto_generated.result[11]
+result[12] <= add_sub_e9h:auto_generated.result[12]
+result[13] <= add_sub_e9h:auto_generated.result[13]
+result[14] <= add_sub_e9h:auto_generated.result[14]
+result[15] <= add_sub_e9h:auto_generated.result[15]
+result[16] <= add_sub_e9h:auto_generated.result[16]
+result[17] <= add_sub_e9h:auto_generated.result[17]
+result[18] <= add_sub_e9h:auto_generated.result[18]
+cout <= <GND>
+overflow <= <GND>
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated
+dataa[0] => op_1.IN36
+dataa[1] => op_1.IN34
+dataa[2] => op_1.IN32
+dataa[3] => op_1.IN30
+dataa[4] => op_1.IN28
+dataa[5] => op_1.IN26
+dataa[6] => op_1.IN24
+dataa[7] => op_1.IN22
+dataa[8] => op_1.IN20
+dataa[9] => op_1.IN18
+dataa[10] => op_1.IN16
+dataa[11] => op_1.IN14
+dataa[12] => op_1.IN12
+dataa[13] => op_1.IN10
+dataa[14] => op_1.IN8
+dataa[15] => op_1.IN6
+dataa[16] => op_1.IN4
+dataa[17] => op_1.IN2
+dataa[18] => op_1.IN0
+datab[0] => op_1.IN37
+datab[1] => op_1.IN35
+datab[2] => op_1.IN33
+datab[3] => op_1.IN31
+datab[4] => op_1.IN29
+datab[5] => op_1.IN27
+datab[6] => op_1.IN25
+datab[7] => op_1.IN23
+datab[8] => op_1.IN21
+datab[9] => op_1.IN19
+datab[10] => op_1.IN17
+datab[11] => op_1.IN15
+datab[12] => op_1.IN13
+datab[13] => op_1.IN11
+datab[14] => op_1.IN9
+datab[15] => op_1.IN7
+datab[16] => op_1.IN5
+datab[17] => op_1.IN3
+datab[18] => op_1.IN1
+result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|altshift:external_latency_ffs
+data[0] => result[0].DATAIN
+data[1] => result[1].DATAIN
+data[2] => result[2].DATAIN
+data[3] => result[3].DATAIN
+data[4] => result[4].DATAIN
+data[5] => result[5].DATAIN
+data[6] => result[6].DATAIN
+data[7] => result[7].DATAIN
+data[8] => result[8].DATAIN
+data[9] => result[9].DATAIN
+data[10] => result[10].DATAIN
+data[11] => result[11].DATAIN
+data[12] => result[12].DATAIN
+data[13] => result[13].DATAIN
+data[14] => result[14].DATAIN
+data[15] => result[15].DATAIN
+data[16] => result[16].DATAIN
+data[17] => result[17].DATAIN
+data[18] => result[18].DATAIN
+data[19] => result[19].DATAIN
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= data[12].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= data[13].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= data[14].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= data[15].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= data[16].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= data[17].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= data[18].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= data[19].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd
+B[0] => BCD_0[0].DATAIN
+B[1] => w35[0].IN1
+B[2] => w30[0].IN1
+B[3] => w26[0].IN1
+B[4] => w22[0].IN1
+B[5] => w18[0].IN1
+B[6] => w15[0].IN1
+B[7] => w12[0].IN1
+B[8] => w9[0].IN1
+B[9] => w7[0].IN1
+B[10] => w5[0].IN1
+B[11] => w3[0].IN1
+B[12] => w2[0].IN1
+B[13] => w1[0].IN1
+B[14] => w1[1].IN1
+B[15] => w1[2].IN1
+BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE
+BCD_0[1] <= add3_ge5:A35.port1
+BCD_0[2] <= add3_ge5:A35.port1
+BCD_0[3] <= add3_ge5:A35.port1
+BCD_1[0] <= add3_ge5:A35.port1
+BCD_1[1] <= add3_ge5:A34.port1
+BCD_1[2] <= add3_ge5:A34.port1
+BCD_1[3] <= add3_ge5:A34.port1
+BCD_2[0] <= add3_ge5:A34.port1
+BCD_2[1] <= add3_ge5:A33.port1
+BCD_2[2] <= add3_ge5:A33.port1
+BCD_2[3] <= add3_ge5:A33.port1
+BCD_3[0] <= add3_ge5:A33.port1
+BCD_3[1] <= add3_ge5:A32.port1
+BCD_3[2] <= add3_ge5:A32.port1
+BCD_3[3] <= add3_ge5:A32.port1
+BCD_4[0] <= add3_ge5:A32.port1
+BCD_4[1] <= add3_ge5:A31.port1
+BCD_4[2] <= add3_ge5:A31.port1
+BCD_4[3] <= add3_ge5:A31.port1
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A1
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A2
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A3
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A4
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A5
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A6
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A7
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A8
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A9
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A10
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A11
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A12
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A13
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A14
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A15
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A16
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A17
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A18
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A19
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A20
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A21
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A22
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A23
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A24
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A25
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A26
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A27
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A28
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A29
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A30
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A31
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A32
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A33
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A34
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A35
+w[0] => Decoder0.IN3
+w[1] => Decoder0.IN2
+w[2] => Decoder0.IN1
+w[3] => Decoder0.IN0
+a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex19|processor:echo_var_delay|hex_to_7seg:h0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex19|processor:echo_var_delay|hex_to_7seg:h1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex19|processor:echo_var_delay|hex_to_7seg:h2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex19|processor:echo_var_delay|hex_to_7seg:h3
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex19|processor:echo_var_delay|hex_to_7seg:h4
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
diff --git a/part_4/ex19/db/ex19.hif b/part_4/ex19/db/ex19.hif
new file mode 100755
index 0000000..0727b65
--- /dev/null
+++ b/part_4/ex19/db/ex19.hif
diff --git a/part_4/ex19/db/ex19.lpc.html b/part_4/ex19/db/ex19.lpc.html
new file mode 100755
index 0000000..40006c1
--- /dev/null
+++ b/part_4/ex19/db/ex19.lpc.html
@@ -0,0 +1,882 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >echo_var_delay|h4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|h3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|h2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|h1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|h0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A35</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A34</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A33</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A32</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A31</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A30</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A29</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A28</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A27</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A26</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A25</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A24</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A23</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A22</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A21</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A20</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A19</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A18</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A17</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A16</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A15</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A14</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A13</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A12</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A11</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A10</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A9</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A8</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A4</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd|A1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|bcd</TD>
+<TD >16</TD>
+<TD >6</TD>
+<TD >0</TD>
+<TD >6</TD>
+<TD >20</TD>
+<TD >6</TD>
+<TD >6</TD>
+<TD >6</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|mul_by_h666|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated</TD>
+<TD >38</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >19</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|mul_by_h666|lpm_mult_component|mult_core|padder|adder[0]|auto_generated</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >15</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|mul_by_h666</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|comb_6</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|del|altsyncram_component|auto_generated</TD>
+<TD >38</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|del</TD>
+<TD >38</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >9</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|ctr|LPM_COUNTER_component|auto_generated</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay|ctr</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >13</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >echo_var_delay</TD>
+<TD >23</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >45</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_ADC</TD>
+<TD >4</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >14</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >PWM_DC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >SPI_DAC</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >4</TD>
+<TD >0</TD>
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+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >GEN_10K</TD>
+<TD >18</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >1</TD>
+<TD >16</TD>
+<TD >16</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/part_4/ex19/db/ex19.lpc.rdb b/part_4/ex19/db/ex19.lpc.rdb
new file mode 100755
index 0000000..8f66ed0
--- /dev/null
+++ b/part_4/ex19/db/ex19.lpc.rdb
diff --git a/part_4/ex19/db/ex19.lpc.txt b/part_4/ex19/db/ex19.lpc.txt
new file mode 100755
index 0000000..48af67e
--- /dev/null
+++ b/part_4/ex19/db/ex19.lpc.txt
@@ -0,0 +1,60 @@
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                                                                              ;
++----------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                                                                          ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++----------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; echo_var_delay|h4                                                                                  ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|h3                                                                                  ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|h2                                                                                  ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|h1                                                                                  ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|h0                                                                                  ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A35                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A34                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A33                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A32                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A31                                                                             ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A30                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A29                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A28                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A27                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A26                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A25                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A24                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A23                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A22                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A21                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A20                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A19                                                                             ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A18                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A17                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A16                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A15                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A14                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A13                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A12                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A11                                                                             ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A10                                                                             ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A9                                                                              ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A8                                                                              ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A7                                                                              ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A6                                                                              ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A5                                                                              ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A4                                                                              ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A3                                                                              ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A2                                                                              ; 4     ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd|A1                                                                              ; 4     ; 1              ; 0            ; 1              ; 4      ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|bcd                                                                                 ; 16    ; 6              ; 0            ; 6              ; 20     ; 6               ; 6             ; 6               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|mul_by_h666|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated ; 38    ; 0              ; 0            ; 0              ; 19     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|mul_by_h666|lpm_mult_component|mult_core|padder|adder[0]|auto_generated             ; 30    ; 0              ; 0            ; 0              ; 15     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|mul_by_h666                                                                         ; 9     ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|comb_6                                                                              ; 10    ; 0              ; 1            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|del|altsyncram_component|auto_generated                                             ; 38    ; 0              ; 0            ; 0              ; 9      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|del                                                                                 ; 38    ; 0              ; 0            ; 0              ; 9      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|ctr|LPM_COUNTER_component|auto_generated                                            ; 1     ; 0              ; 0            ; 0              ; 13     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay|ctr                                                                                 ; 1     ; 0              ; 0            ; 0              ; 13     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; echo_var_delay                                                                                     ; 23    ; 0              ; 0            ; 0              ; 45     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_ADC                                                                                            ; 4     ; 1              ; 0            ; 1              ; 14     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; PWM_DC                                                                                             ; 12    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; SPI_DAC                                                                                            ; 12    ; 0              ; 0            ; 0              ; 4      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; GEN_10K                                                                                            ; 18    ; 16             ; 0            ; 16             ; 1      ; 16              ; 16            ; 16              ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++----------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/part_4/ex19/db/ex19.map.ammdb b/part_4/ex19/db/ex19.map.ammdb
new file mode 100755
index 0000000..174eb00
--- /dev/null
+++ b/part_4/ex19/db/ex19.map.ammdb
diff --git a/part_4/ex19/db/ex19.map.bpm b/part_4/ex19/db/ex19.map.bpm
new file mode 100755
index 0000000..2324e83
--- /dev/null
+++ b/part_4/ex19/db/ex19.map.bpm
diff --git a/part_4/ex19/db/ex19.map.cdb b/part_4/ex19/db/ex19.map.cdb
new file mode 100755
index 0000000..0766c5e
--- /dev/null
+++ b/part_4/ex19/db/ex19.map.cdb
diff --git a/part_4/ex19/db/ex19.map.hdb b/part_4/ex19/db/ex19.map.hdb
new file mode 100755
index 0000000..9cc2f59
--- /dev/null
+++ b/part_4/ex19/db/ex19.map.hdb
diff --git a/part_4/ex19/db/ex19.map.kpt b/part_4/ex19/db/ex19.map.kpt
new file mode 100755
index 0000000..cf84eff
--- /dev/null
+++ b/part_4/ex19/db/ex19.map.kpt
diff --git a/part_4/ex19/db/ex19.map.logdb b/part_4/ex19/db/ex19.map.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex19/db/ex19.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex19/db/ex19.map.qmsg b/part_4/ex19/db/ex19.map.qmsg
new file mode 100755
index 0000000..52a9905
--- /dev/null
+++ b/part_4/ex19/db/ex19.map.qmsg
@@ -0,0 +1,110 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481017578667 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481017578668 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 06 09:46:18 2016 " "Processing started: Tue Dec 06 09:46:18 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481017578668 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017578668 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017578669 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481017579170 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481017579171 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/variable_echo.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/variable_echo.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587579 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587579 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex19/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587581 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587581 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "verilog_files/spi2adc.v" "" { Text "C:/New folder/ex19/verilog_files/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587583 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587583 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex19/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587585 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587585 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" {  } { { "verilog_files/pulse_gen.v" "" { Text "C:/New folder/ex19/verilog_files/pulse_gen.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587586 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587586 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" {  } { { "verilog_files/multiply_k.v" "" { Text "C:/New folder/ex19/verilog_files/multiply_k.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587588 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587588 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex19/verilog_files/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587590 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587590 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/div_by_2.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_by_2 " "Found entity 1: div_by_2" {  } { { "verilog_files/div_by_2.v" "" { Text "C:/New folder/ex19/verilog_files/div_by_2.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587591 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587591 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "verilog_files/delay_ram.v" "" { Text "C:/New folder/ex19/verilog_files/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587593 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587593 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" {  } { { "verilog_files/d_ff.v" "" { Text "C:/New folder/ex19/verilog_files/d_ff.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587595 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587595 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" {  } { { "verilog_files/clktick_16.v" "" { Text "C:/New folder/ex19/verilog_files/clktick_16.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587596 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587596 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587600 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587600 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex19/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587601 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587601 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex19.v 1 1 " "Found 1 design units, including 1 entities, in source file ex19.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex19 " "Found entity 1: ex19" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587603 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587603 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_block.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_block.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_block " "Found entity 1: delay_block" {  } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587604 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587604 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ctr_13_bit.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ctr_13_bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 ctr_13_bit " "Found entity 1: ctr_13_bit" {  } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587606 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587606 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult_by_h666.v 1 1 " "Found 1 design units, including 1 entities, in source file mult_by_h666.v" { { "Info" "ISGN_ENTITY_NAME" "1 mult_by_h666 " "Found entity 1: mult_by_h666" {  } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587608 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587608 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "variable_echo.v(32) " "Verilog HDL Instantiation warning at variable_echo.v(32): instance has no name" {  } { { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 32 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1481017587608 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex19 " "Elaborating entity \"ex19\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481017587729 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clktick_16 clktick_16:GEN_10K " "Elaborating entity \"clktick_16\" for hierarchy \"clktick_16:GEN_10K\"" {  } { { "ex19.v" "GEN_10K" { Text "C:/New folder/ex19/ex19.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587731 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" {  } { { "ex19.v" "SPI_DAC" { Text "C:/New folder/ex19/ex19.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587732 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" {  } { { "ex19.v" "PWM_DC" { Text "C:/New folder/ex19/ex19.v" 27 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587733 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "ex19.v" "SPI_ADC" { Text "C:/New folder/ex19/ex19.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587733 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:echo_var_delay " "Elaborating entity \"processor\" for hierarchy \"processor:echo_var_delay\"" {  } { { "ex19.v" "echo_var_delay" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587735 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ctr_13_bit processor:echo_var_delay\|ctr_13_bit:ctr " "Elaborating entity \"ctr_13_bit\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\"" {  } { { "verilog_files/variable_echo.v" "ctr" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 28 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587749 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Elaborating entity \"lpm_counter\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\"" {  } { { "verilog_files/ctr_13_bit.v" "LPM_COUNTER_component" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587786 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\"" {  } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587787 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Instantiated megafunction \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_port_updown PORT_UNUSED " "Parameter \"lpm_port_updown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 13 " "Parameter \"lpm_width\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587787 ""}  } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017587787 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cjh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_cjh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cjh " "Found entity 1: cntr_cjh" {  } { { "db/cntr_cjh.tdf" "" { Text "C:/New folder/ex19/db/cntr_cjh.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587829 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587829 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cjh processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\|cntr_cjh:auto_generated " "Elaborating entity \"cntr_cjh\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\|cntr_cjh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_counter.tdf" 259 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587829 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay_block processor:echo_var_delay\|delay_block:del " "Elaborating entity \"delay_block\" for hierarchy \"processor:echo_var_delay\|delay_block:del\"" {  } { { "verilog_files/variable_echo.v" "del" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587837 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/delay_block.v" "altsyncram_component" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587877 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587880 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Instantiated megafunction \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8192 " "Parameter \"numwords_a\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8192 " "Parameter \"numwords_b\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M10K " "Parameter \"ram_block_type\" = \"M10K\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 13 " "Parameter \"widthad_a\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 13 " "Parameter \"widthad_b\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 9 " "Parameter \"width_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""}  } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017587880 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_nm22.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_nm22.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_nm22 " "Found entity 1: altsyncram_nm22" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587924 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587924 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_nm22 processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated " "Elaborating entity \"altsyncram_nm22\" for hierarchy \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587924 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_by_2 processor:echo_var_delay\|div_by_2:comb_6 " "Elaborating entity \"div_by_2\" for hierarchy \"processor:echo_var_delay\|div_by_2:comb_6\"" {  } { { "verilog_files/variable_echo.v" "comb_6" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 32 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587929 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_by_h666 processor:echo_var_delay\|mult_by_h666:mul_by_h666 " "Elaborating entity \"mult_by_h666\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\"" {  } { { "verilog_files/variable_echo.v" "mul_by_h666" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 34 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587935 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mult_by_h666.v" "lpm_mult_component" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587963 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587964 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 9 " "Parameter \"lpm_widtha\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 11 " "Parameter \"lpm_widthb\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 20 " "Parameter \"lpm_widthp\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""}  } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017587964 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multcore processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core " "Elaborating entity \"multcore\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\"" {  } { { "lpm_mult.tdf" "mult_core" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587995 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587998 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder " "Elaborating entity \"mpar_add\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\"" {  } { { "multcore.tdf" "padder" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588017 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "multcore.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588019 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588046 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588047 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_a9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_a9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_a9h " "Found entity 1: add_sub_a9h" {  } { { "db/add_sub_a9h.tdf" "" { Text "C:/New folder/ex19/db/add_sub_a9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017588088 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017588088 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_a9h processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated " "Elaborating entity \"add_sub_a9h\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588088 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add " "Elaborating entity \"mpar_add\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\"" {  } { { "mpar_add.tdf" "sub_par_add" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588092 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588092 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588096 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588097 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_e9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_e9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_e9h " "Found entity 1: add_sub_e9h" {  } { { "db/add_sub_e9h.tdf" "" { Text "C:/New folder/ex19/db/add_sub_e9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017588138 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017588138 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_e9h processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated " "Elaborating entity \"add_sub_e9h\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588138 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs " "Elaborating entity \"altshift\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\"" {  } { { "lpm_mult.tdf" "external_latency_ffs" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588157 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588157 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 processor:echo_var_delay\|bin2bcd_16:bcd " "Elaborating entity \"bin2bcd_16\" for hierarchy \"processor:echo_var_delay\|bin2bcd_16:bcd\"" {  } { { "verilog_files/variable_echo.v" "bcd" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 36 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588158 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 processor:echo_var_delay\|bin2bcd_16:bcd\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"processor:echo_var_delay\|bin2bcd_16:bcd\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588160 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg processor:echo_var_delay\|hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"processor:echo_var_delay\|hex_to_7seg:h0\"" {  } { { "verilog_files/variable_echo.v" "h0" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588167 ""}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[9\] " "Net \"processor:echo_var_delay\|tmp_data\[9\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[9\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017588209 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1481017588209 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[0\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[0\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 39 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017588289 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a0"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1481017588289 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1481017588289 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "4 " "4 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481017588762 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] GND " "Pin \"HEX3\[1\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] GND " "Pin \"HEX3\[2\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Pin \"HEX3\[6\]\" is stuck at VCC" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[0\] GND " "Pin \"HEX4\[0\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[1\] GND " "Pin \"HEX4\[1\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[2\] GND " "Pin \"HEX4\[2\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[3\] GND " "Pin \"HEX4\[3\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[4\] GND " "Pin \"HEX4\[4\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[5\] GND " "Pin \"HEX4\[5\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[6\] VCC " "Pin \"HEX4\[6\]\" is stuck at VCC" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481017588860 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481017588940 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex19/output_files/ex19.map.smsg " "Generated suppressed messages file C:/New folder/ex19/output_files/ex19.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017589229 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481017589331 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017589331 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017589402 "|ex19|SW[9]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481017589402 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "312 " "Implemented 312 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481017589404 ""} { "Info" "ICUT_CUT_TM_OPINS" "43 " "Implemented 43 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481017589404 ""} { "Info" "ICUT_CUT_TM_LCELLS" "249 " "Implemented 249 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481017589404 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1481017589404 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481017589404 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "916 " "Peak virtual memory: 916 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017589423 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:46:29 2016 " "Processing ended: Tue Dec 06 09:46:29 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017589423 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017589423 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017589423 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017589423 ""}
diff --git a/part_4/ex19/db/ex19.map.rdb b/part_4/ex19/db/ex19.map.rdb
new file mode 100755
index 0000000..2c308f4
--- /dev/null
+++ b/part_4/ex19/db/ex19.map.rdb
diff --git a/part_4/ex19/db/ex19.map_bb.cdb b/part_4/ex19/db/ex19.map_bb.cdb
new file mode 100755
index 0000000..90bbded
--- /dev/null
+++ b/part_4/ex19/db/ex19.map_bb.cdb
diff --git a/part_4/ex19/db/ex19.map_bb.hdb b/part_4/ex19/db/ex19.map_bb.hdb
new file mode 100755
index 0000000..2f2e6d8
--- /dev/null
+++ b/part_4/ex19/db/ex19.map_bb.hdb
diff --git a/part_4/ex19/db/ex19.map_bb.logdb b/part_4/ex19/db/ex19.map_bb.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex19/db/ex19.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex19/db/ex19.pre_map.hdb b/part_4/ex19/db/ex19.pre_map.hdb
new file mode 100755
index 0000000..6e958be
--- /dev/null
+++ b/part_4/ex19/db/ex19.pre_map.hdb
diff --git a/part_4/ex19/db/ex19.root_partition.map.reg_db.cdb b/part_4/ex19/db/ex19.root_partition.map.reg_db.cdb
new file mode 100755
index 0000000..c0372f8
--- /dev/null
+++ b/part_4/ex19/db/ex19.root_partition.map.reg_db.cdb
diff --git a/part_4/ex19/db/ex19.routing.rdb b/part_4/ex19/db/ex19.routing.rdb
new file mode 100755
index 0000000..74aecef
--- /dev/null
+++ b/part_4/ex19/db/ex19.routing.rdb
diff --git a/part_4/ex19/db/ex19.rtlv.hdb b/part_4/ex19/db/ex19.rtlv.hdb
new file mode 100755
index 0000000..e6a5cbf
--- /dev/null
+++ b/part_4/ex19/db/ex19.rtlv.hdb
diff --git a/part_4/ex19/db/ex19.rtlv_sg.cdb b/part_4/ex19/db/ex19.rtlv_sg.cdb
new file mode 100755
index 0000000..880c286
--- /dev/null
+++ b/part_4/ex19/db/ex19.rtlv_sg.cdb
diff --git a/part_4/ex19/db/ex19.rtlv_sg_swap.cdb b/part_4/ex19/db/ex19.rtlv_sg_swap.cdb
new file mode 100755
index 0000000..335d17c
--- /dev/null
+++ b/part_4/ex19/db/ex19.rtlv_sg_swap.cdb
diff --git a/part_4/ex19/db/ex19.sld_design_entry.sci b/part_4/ex19/db/ex19.sld_design_entry.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_4/ex19/db/ex19.sld_design_entry.sci
diff --git a/part_4/ex19/db/ex19.sld_design_entry_dsc.sci b/part_4/ex19/db/ex19.sld_design_entry_dsc.sci
new file mode 100755
index 0000000..92c1102
--- /dev/null
+++ b/part_4/ex19/db/ex19.sld_design_entry_dsc.sci
diff --git a/part_4/ex19/db/ex19.smart_action.txt b/part_4/ex19/db/ex19.smart_action.txt
new file mode 100755
index 0000000..437a63e
--- /dev/null
+++ b/part_4/ex19/db/ex19.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/part_4/ex19/db/ex19.smp_dump.txt b/part_4/ex19/db/ex19.smp_dump.txt
new file mode 100755
index 0000000..4a1287f
--- /dev/null
+++ b/part_4/ex19/db/ex19.smp_dump.txt
@@ -0,0 +1,12 @@
+
+State Machine - |ex19|spi2adc:SPI_ADC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
+
+State Machine - |ex19|spi2dac:SPI_DAC|sr_state
+Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
+sr_state.IDLE 0 0 0 
+sr_state.WAIT_CSB_FALL 1 0 1 
+sr_state.WAIT_CSB_HIGH 1 1 0 
diff --git a/part_4/ex19/db/ex19.sta.qmsg b/part_4/ex19/db/ex19.sta.qmsg
new file mode 100755
index 0000000..f5fb260
--- /dev/null
+++ b/part_4/ex19/db/ex19.sta.qmsg
@@ -0,0 +1,56 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481017640983 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481017640984 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 06 09:47:20 2016 " "Processing started: Tue Dec 06 09:47:20 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481017640984 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017640984 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex19 -c ex19 " "Command: quartus_sta ex19 -c ex19" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017640984 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017641121 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017641707 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017641707 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017641755 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017641755 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex19.sdc " "Synopsys Design Constraints File file not found: 'ex19.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642291 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642291 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481017642294 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz " "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481017642294 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2adc:SPI_ADC\|adc_cs spi2adc:SPI_ADC\|adc_cs " "create_clock -period 1.000 -name spi2adc:SPI_ADC\|adc_cs spi2adc:SPI_ADC\|adc_cs" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481017642294 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2dac:SPI_DAC\|clk_1MHz spi2dac:SPI_DAC\|clk_1MHz " "create_clock -period 1.000 -name spi2dac:SPI_DAC\|clk_1MHz spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481017642294 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642294 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642297 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642307 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017642309 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017642317 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481017642346 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642346 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.675 " "Worst-case setup slack is -5.675" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642348 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642348 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.675           -1310.496 CLOCK_50  " "   -5.675           -1310.496 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642348 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.850             -67.920 spi2dac:SPI_DAC\|clk_1MHz  " "   -3.850             -67.920 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642348 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.352             -52.261 spi2adc:SPI_ADC\|clk_1MHz  " "   -3.352             -52.261 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642348 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.060             -28.823 spi2adc:SPI_ADC\|adc_cs  " "   -2.060             -28.823 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642348 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642348 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.121 " "Worst-case hold slack is 0.121" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.121               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.121               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.225               0.000 CLOCK_50  " "    0.225               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.438               0.000 spi2adc:SPI_ADC\|adc_cs  " "    0.438               0.000 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642353 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.767               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.767               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642353 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642353 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642355 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642356 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1208.848 CLOCK_50  " "   -2.174           -1208.848 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -16.455 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.394             -16.455 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -13.115 spi2dac:SPI_DAC\|clk_1MHz  " "   -0.394             -13.115 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -8.336 spi2adc:SPI_ADC\|adc_cs  " "   -0.394              -8.336 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017642358 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642358 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1481017642371 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642371 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017642375 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017642412 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643618 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643694 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481017643703 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643703 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.268 " "Worst-case setup slack is -5.268" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.268           -1146.977 CLOCK_50  " "   -5.268           -1146.977 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.985             -70.248 spi2dac:SPI_DAC\|clk_1MHz  " "   -3.985             -70.248 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.474             -50.644 spi2adc:SPI_ADC\|clk_1MHz  " "   -3.474             -50.644 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.136             -29.447 spi2adc:SPI_ADC\|adc_cs  " "   -2.136             -29.447 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643704 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643704 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.113 " "Worst-case hold slack is 0.113" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.113               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.113               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.216               0.000 CLOCK_50  " "    0.216               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.451               0.000 spi2adc:SPI_ADC\|adc_cs  " "    0.451               0.000 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643708 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.729               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.729               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643708 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643708 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643710 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643712 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1202.219 CLOCK_50  " "   -2.174           -1202.219 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -16.947 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.394             -16.947 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -13.226 spi2dac:SPI_DAC\|clk_1MHz  " "   -0.394             -13.226 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643713 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394              -8.192 spi2adc:SPI_ADC\|adc_cs  " "   -0.394              -8.192 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017643713 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643713 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1481017643726 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643726 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017643729 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017643884 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017644935 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645011 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481017645014 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645014 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.917 " "Worst-case setup slack is -3.917" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.917            -921.485 CLOCK_50  " "   -3.917            -921.485 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.773             -30.272 spi2dac:SPI_DAC\|clk_1MHz  " "   -1.773             -30.272 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.528             -26.809 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.528             -26.809 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645016 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.942             -13.341 spi2adc:SPI_ADC\|adc_cs  " "   -0.942             -13.341 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645016 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645016 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.084 " "Worst-case hold slack is 0.084" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.084               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.084               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.130               0.000 CLOCK_50  " "    0.130               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.162               0.000 spi2adc:SPI_ADC\|adc_cs  " "    0.162               0.000 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.345               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.345               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645020 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645020 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645021 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645023 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1213.382 CLOCK_50  " "   -2.174           -1213.382 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.033               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.033               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.054               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.054               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.156               0.000 spi2adc:SPI_ADC\|adc_cs  " "    0.156               0.000 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645024 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645024 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1481017645037 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645037 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017645041 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645213 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481017645216 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645216 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.277 " "Worst-case setup slack is -3.277" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.277            -712.908 CLOCK_50  " "   -3.277            -712.908 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.708             -28.858 spi2dac:SPI_DAC\|clk_1MHz  " "   -1.708             -28.858 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.479             -23.942 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.479             -23.942 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.834             -11.645 spi2adc:SPI_ADC\|adc_cs  " "   -0.834             -11.645 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645218 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645218 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.104 " "Worst-case hold slack is 0.104" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.104               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.104               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.123               0.000 CLOCK_50  " "    0.123               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.149               0.000 spi2adc:SPI_ADC\|adc_cs  " "    0.149               0.000 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645222 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.314               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.314               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645222 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645222 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645224 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645226 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.174 " "Worst-case minimum pulse width slack is -2.174" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.174           -1236.838 CLOCK_50  " "   -2.174           -1236.838 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.062               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.062               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.076               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.076               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645227 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.161               0.000 spi2adc:SPI_ADC\|adc_cs  " "    0.161               0.000 spi2adc:SPI_ADC\|adc_cs " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017645227 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645227 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 9 synchronizer chains. " "Report Metastability: Found 9 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Design MTBF is not calculated because the design doesn't meet its timing requirements. " "Design MTBF is not calculated because the design doesn't meet its timing requirements." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1481017645241 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017645241 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017646705 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017646707 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1237 " "Peak virtual memory: 1237 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017646757 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:47:26 2016 " "Processing ended: Tue Dec 06 09:47:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017646757 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017646757 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017646757 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017646757 ""}
diff --git a/part_4/ex19/db/ex19.sta.rdb b/part_4/ex19/db/ex19.sta.rdb
new file mode 100755
index 0000000..524c041
--- /dev/null
+++ b/part_4/ex19/db/ex19.sta.rdb
diff --git a/part_4/ex19/db/ex19.sta_cmp.6_slow_1100mv_85c.tdb b/part_4/ex19/db/ex19.sta_cmp.6_slow_1100mv_85c.tdb
new file mode 100755
index 0000000..faa6de9
--- /dev/null
+++ b/part_4/ex19/db/ex19.sta_cmp.6_slow_1100mv_85c.tdb
diff --git a/part_4/ex19/db/ex19.tis_db_list.ddb b/part_4/ex19/db/ex19.tis_db_list.ddb
new file mode 100755
index 0000000..70684ad
--- /dev/null
+++ b/part_4/ex19/db/ex19.tis_db_list.ddb
diff --git a/part_4/ex19/db/ex19.tiscmp.fast_1100mv_0c.ddb b/part_4/ex19/db/ex19.tiscmp.fast_1100mv_0c.ddb
new file mode 100755
index 0000000..55e76a1
--- /dev/null
+++ b/part_4/ex19/db/ex19.tiscmp.fast_1100mv_0c.ddb
diff --git a/part_4/ex19/db/ex19.tiscmp.fast_1100mv_85c.ddb b/part_4/ex19/db/ex19.tiscmp.fast_1100mv_85c.ddb
new file mode 100755
index 0000000..7272524
--- /dev/null
+++ b/part_4/ex19/db/ex19.tiscmp.fast_1100mv_85c.ddb
diff --git a/part_4/ex19/db/ex19.tiscmp.slow_1100mv_0c.ddb b/part_4/ex19/db/ex19.tiscmp.slow_1100mv_0c.ddb
new file mode 100755
index 0000000..7ac1366
--- /dev/null
+++ b/part_4/ex19/db/ex19.tiscmp.slow_1100mv_0c.ddb
diff --git a/part_4/ex19/db/ex19.tiscmp.slow_1100mv_85c.ddb b/part_4/ex19/db/ex19.tiscmp.slow_1100mv_85c.ddb
new file mode 100755
index 0000000..39e38f6
--- /dev/null
+++ b/part_4/ex19/db/ex19.tiscmp.slow_1100mv_85c.ddb
diff --git a/part_4/ex19/db/ex19.tmw_info b/part_4/ex19/db/ex19.tmw_info
new file mode 100755
index 0000000..f029c05
--- /dev/null
+++ b/part_4/ex19/db/ex19.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:01:10
+start_analysis_synthesis:s:00:00:13-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:42-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:08-start_full_compilation
diff --git a/part_4/ex19/db/ex19.vpr.ammdb b/part_4/ex19/db/ex19.vpr.ammdb
new file mode 100755
index 0000000..0635455
--- /dev/null
+++ b/part_4/ex19/db/ex19.vpr.ammdb
diff --git a/part_4/ex19/db/ex19_partition_pins.json b/part_4/ex19/db/ex19_partition_pins.json
new file mode 100755
index 0000000..f06d6c1
--- /dev/null
+++ b/part_4/ex19/db/ex19_partition_pins.json
@@ -0,0 +1,185 @@
+{
+	"partitions" : [
+		{
+			"name" : "Top",
+			"pins" : [
+				{
+					"name" : "HEX0[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX0[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX1[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[1]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[2]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[5]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX2[6]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[0]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[3]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[4]",
+					"strict" : false
+				},
+				{
+					"name" : "HEX3[5]",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "DAC_LD",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDI",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SCK",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_CS",
+					"strict" : false
+				},
+				{
+					"name" : "PWM_OUT",
+					"strict" : false
+				},
+				{
+					"name" : "SW[8]",
+					"strict" : false
+				},
+				{
+					"name" : "CLOCK_50",
+					"strict" : false
+				},
+				{
+					"name" : "SW[6]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[5]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[4]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[3]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[2]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[1]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[0]",
+					"strict" : false
+				},
+				{
+					"name" : "SW[7]",
+					"strict" : false
+				},
+				{
+					"name" : "ADC_SDO",
+					"strict" : false
+				}
+			]
+		}
+	]
+}
+\ No newline at end of file
diff --git a/part_4/ex19/db/prev_cmp_ex19.qmsg b/part_4/ex19/db/prev_cmp_ex19.qmsg
new file mode 100755
index 0000000..976b26c
--- /dev/null
+++ b/part_4/ex19/db/prev_cmp_ex19.qmsg
@@ -0,0 +1,221 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481017382448 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481017382450 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 06 09:43:02 2016 " "Processing started: Tue Dec 06 09:43:02 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481017382450 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017382450 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017382451 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481017382970 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481017382970 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/variable_echo.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/variable_echo.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" {  } { { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391356 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391356 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" {  } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex19/verilog_files/spi2dac.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391358 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391358 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" {  } { { "verilog_files/spi2adc.v" "" { Text "C:/New folder/ex19/verilog_files/spi2adc.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391360 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391360 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" {  } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex19/verilog_files/pwm.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391361 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391361 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" {  } { { "verilog_files/pulse_gen.v" "" { Text "C:/New folder/ex19/verilog_files/pulse_gen.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391363 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391363 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" {  } { { "verilog_files/multiply_k.v" "" { Text "C:/New folder/ex19/verilog_files/multiply_k.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391365 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391365 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" {  } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex19/verilog_files/hex_to_7seg.v" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391366 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391366 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/div_by_2.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_by_2 " "Found entity 1: div_by_2" {  } { { "verilog_files/div_by_2.v" "" { Text "C:/New folder/ex19/verilog_files/div_by_2.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391368 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391368 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" {  } { { "verilog_files/delay_ram.v" "" { Text "C:/New folder/ex19/verilog_files/delay_ram.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391370 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391370 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" {  } { { "verilog_files/d_ff.v" "" { Text "C:/New folder/ex19/verilog_files/d_ff.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391371 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391371 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" {  } { { "verilog_files/clktick_16.v" "" { Text "C:/New folder/ex19/verilog_files/clktick_16.v" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391373 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391373 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391375 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" {  } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391376 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391376 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" {  } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex19/verilog_files/add3_ge5.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391378 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391378 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex19.v 1 1 " "Found 1 design units, including 1 entities, in source file ex19.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex19 " "Found entity 1: ex19" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391380 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391380 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_block.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_block.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_block " "Found entity 1: delay_block" {  } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391382 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391382 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ctr_13_bit.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ctr_13_bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 ctr_13_bit " "Found entity 1: ctr_13_bit" {  } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391384 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391384 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult_by_h666.v 1 1 " "Found 1 design units, including 1 entities, in source file mult_by_h666.v" { { "Info" "ISGN_ENTITY_NAME" "1 mult_by_h666 " "Found entity 1: mult_by_h666" {  } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391385 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391385 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "variable_echo.v(32) " "Verilog HDL Instantiation warning at variable_echo.v(32): instance has no name" {  } { { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 32 0 0 } }  } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1481017391386 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex19 " "Elaborating entity \"ex19\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481017391489 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clktick_16 clktick_16:GEN_10K " "Elaborating entity \"clktick_16\" for hierarchy \"clktick_16:GEN_10K\"" {  } { { "ex19.v" "GEN_10K" { Text "C:/New folder/ex19/ex19.v" 24 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391490 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" {  } { { "ex19.v" "SPI_DAC" { Text "C:/New folder/ex19/ex19.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391491 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" {  } { { "ex19.v" "PWM_DC" { Text "C:/New folder/ex19/ex19.v" 27 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391492 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" {  } { { "ex19.v" "SPI_ADC" { Text "C:/New folder/ex19/ex19.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391493 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:echo_var_delay " "Elaborating entity \"processor\" for hierarchy \"processor:echo_var_delay\"" {  } { { "ex19.v" "echo_var_delay" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391494 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ctr_13_bit processor:echo_var_delay\|ctr_13_bit:ctr " "Elaborating entity \"ctr_13_bit\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\"" {  } { { "verilog_files/variable_echo.v" "ctr" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 28 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391501 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Elaborating entity \"lpm_counter\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\"" {  } { { "verilog_files/ctr_13_bit.v" "LPM_COUNTER_component" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391535 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\"" {  } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391536 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Instantiated megafunction \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391537 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_port_updown PORT_UNUSED " "Parameter \"lpm_port_updown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391537 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391537 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 13 " "Parameter \"lpm_width\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391537 ""}  } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017391537 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cjh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_cjh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cjh " "Found entity 1: cntr_cjh" {  } { { "db/cntr_cjh.tdf" "" { Text "C:/New folder/ex19/db/cntr_cjh.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391577 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391577 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cjh processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\|cntr_cjh:auto_generated " "Elaborating entity \"cntr_cjh\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\|cntr_cjh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_counter.tdf" 259 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391577 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay_block processor:echo_var_delay\|delay_block:del " "Elaborating entity \"delay_block\" for hierarchy \"processor:echo_var_delay\|delay_block:del\"" {  } { { "verilog_files/variable_echo.v" "del" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391585 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/delay_block.v" "altsyncram_component" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391644 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\"" {  } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391655 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Instantiated megafunction \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8192 " "Parameter \"numwords_a\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8192 " "Parameter \"numwords_b\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M10K " "Parameter \"ram_block_type\" = \"M10K\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 13 " "Parameter \"widthad_a\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 13 " "Parameter \"widthad_b\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 9 " "Parameter \"width_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391655 ""}  } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017391655 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_nm22.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_nm22.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_nm22 " "Found entity 1: altsyncram_nm22" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391696 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391696 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_nm22 processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated " "Elaborating entity \"altsyncram_nm22\" for hierarchy \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391697 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_by_2 processor:echo_var_delay\|div_by_2:comb_6 " "Elaborating entity \"div_by_2\" for hierarchy \"processor:echo_var_delay\|div_by_2:comb_6\"" {  } { { "verilog_files/variable_echo.v" "comb_6" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 32 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391709 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_by_h666 processor:echo_var_delay\|mult_by_h666:mul_by_h666 " "Elaborating entity \"mult_by_h666\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\"" {  } { { "verilog_files/variable_echo.v" "mul_by_h666" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 34 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391716 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mult_by_h666.v" "lpm_mult_component" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391742 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391743 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391743 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391743 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391743 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 9 " "Parameter \"lpm_widtha\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391743 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 11 " "Parameter \"lpm_widthb\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391743 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 20 " "Parameter \"lpm_widthp\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017391743 ""}  } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017391743 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multcore processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core " "Elaborating entity \"multcore\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\"" {  } { { "lpm_mult.tdf" "mult_core" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391772 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391774 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder " "Elaborating entity \"mpar_add\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\"" {  } { { "multcore.tdf" "padder" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391793 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "multcore.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391794 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391819 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391821 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_a9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_a9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_a9h " "Found entity 1: add_sub_a9h" {  } { { "db/add_sub_a9h.tdf" "" { Text "C:/New folder/ex19/db/add_sub_a9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391861 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391861 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_a9h processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated " "Elaborating entity \"add_sub_a9h\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391862 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add " "Elaborating entity \"mpar_add\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\"" {  } { { "mpar_add.tdf" "sub_par_add" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391865 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391866 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\"" {  } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391869 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391870 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_e9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_e9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_e9h " "Found entity 1: add_sub_e9h" {  } { { "db/add_sub_e9h.tdf" "" { Text "C:/New folder/ex19/db/add_sub_e9h.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017391910 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017391910 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_e9h processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated " "Elaborating entity \"add_sub_e9h\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391910 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs " "Elaborating entity \"altshift\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\"" {  } { { "lpm_mult.tdf" "external_latency_ffs" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391928 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391929 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 processor:echo_var_delay\|bin2bcd_16:bcd " "Elaborating entity \"bin2bcd_16\" for hierarchy \"processor:echo_var_delay\|bin2bcd_16:bcd\"" {  } { { "verilog_files/variable_echo.v" "bcd" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 36 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391930 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 processor:echo_var_delay\|bin2bcd_16:bcd\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"processor:echo_var_delay\|bin2bcd_16:bcd\|add3_ge5:A1\"" {  } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 26 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391931 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg processor:echo_var_delay\|hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"processor:echo_var_delay\|hex_to_7seg:h0\"" {  } { { "verilog_files/variable_echo.v" "h0" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 38 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017391939 ""}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[9\] " "Net \"processor:echo_var_delay\|tmp_data\[9\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[9\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[8\] " "Net \"processor:echo_var_delay\|tmp_data\[8\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[8\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[7\] " "Net \"processor:echo_var_delay\|tmp_data\[7\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[7\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[6\] " "Net \"processor:echo_var_delay\|tmp_data\[6\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[6\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[5\] " "Net \"processor:echo_var_delay\|tmp_data\[5\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[5\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[4\] " "Net \"processor:echo_var_delay\|tmp_data\[4\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[4\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[3\] " "Net \"processor:echo_var_delay\|tmp_data\[3\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[3\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[2\] " "Net \"processor:echo_var_delay\|tmp_data\[2\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[2\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[1\] " "Net \"processor:echo_var_delay\|tmp_data\[1\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[1\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""} { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[0\] " "Net \"processor:echo_var_delay\|tmp_data\[0\]\" is missing source, defaulting to GND" {  } { { "verilog_files/variable_echo.v" "tmp_data\[0\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } }  } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017391983 ""}  } {  } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1481017391983 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[0\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[0\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 39 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[1\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[1\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 72 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[2\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[2\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 105 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[3\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[3\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 138 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[4\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[4\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 171 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[5\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[5\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 204 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[6\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[6\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 237 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[7\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[7\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 270 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[8\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[8\]\"" {  } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 303 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017392066 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a8"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1481017392066 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1481017392066 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "4 " "4 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481017392535 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] GND " "Pin \"HEX3\[1\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] GND " "Pin \"HEX3\[2\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Pin \"HEX3\[6\]\" is stuck at VCC" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[0\] GND " "Pin \"HEX4\[0\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX4[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[1\] GND " "Pin \"HEX4\[1\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX4[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[2\] GND " "Pin \"HEX4\[2\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX4[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[3\] GND " "Pin \"HEX4\[3\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX4[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[4\] GND " "Pin \"HEX4\[4\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX4[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[5\] GND " "Pin \"HEX4\[5\]\" is stuck at GND" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX4[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[6\] VCC " "Pin \"HEX4\[6\]\" is stuck at VCC" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017392627 "|ex19|HEX4[6]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481017392627 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481017392705 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "13 " "13 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1481017392950 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex19/output_files/ex19.map.smsg " "Generated suppressed messages file C:/New folder/ex19/output_files/ex19.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017393006 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481017393104 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017393104 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 6 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017393174 "|ex19|SW[9]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481017393174 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "282 " "Implemented 282 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481017393176 ""} { "Info" "ICUT_CUT_TM_OPINS" "43 " "Implemented 43 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481017393176 ""} { "Info" "ICUT_CUT_TM_LCELLS" "227 " "Implemented 227 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481017393176 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481017393176 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 38 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 38 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "918 " "Peak virtual memory: 918 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017393195 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:43:13 2016 " "Processing ended: Tue Dec 06 09:43:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017393195 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017393195 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017393195 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017393195 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1481017394703 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481017394705 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 06 09:43:14 2016 " "Processing started: Tue Dec 06 09:43:14 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481017394705 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1481017394705 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ex19 -c ex19 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off ex19 -c ex19" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1481017394705 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1481017394829 ""}
+{ "Info" "0" "" "Project  = ex19" {  } {  } 0 0 "Project  = ex19" 0 0 "Fitter" 0 0 1481017394829 ""}
+{ "Info" "0" "" "Revision = ex19" {  } {  } 0 0 "Revision = ex19" 0 0 "Fitter" 0 0 1481017394829 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1481017394953 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1481017394953 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ex19 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"ex19\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1481017395218 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481017395282 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1481017395282 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1481017395673 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1481017395817 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" {  } {  } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1481017406272 ""}
+{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1  (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 61 global CLKCTRL_G6 " "CLOCK_50~inputCLKENA0 with 61 fanout uses global clock CLKCTRL_G6" {  } {  } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1481017406379 ""}  } {  } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1481017406379 ""}
+{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" {  } {  } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017406380 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1481017406383 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481017406384 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1481017406385 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1481017406386 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1481017406386 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1481017406387 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex19.sdc " "Synopsys Design Constraints File file not found: 'ex19.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1481017407006 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1481017407007 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1481017407011 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1481017407011 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1481017407012 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" {  } {  } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1481017407026 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1481017407027 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1481017407027 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CLK " "Node \"OLED_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_CS " "Node \"OLED_CS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_CS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DATA " "Node \"OLED_DATA\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DATA" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_DC " "Node \"OLED_DC\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_DC" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OLED_RST " "Node \"OLED_RST\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "OLED_RST" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1481017407074 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1481017407074 ""}
+{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:12 " "Fitter preparation operations ending: elapsed time is 00:00:12" {  } {  } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017407076 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1481017411966 ""}
+{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." {  } {  } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1481017412216 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017412927 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1481017413530 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1481017414358 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017414358 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1481017415513 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X56_Y0 X66_Y10 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10" {  } { { "loc" "" { Generic "C:/New folder/ex19/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X56_Y0 to location X66_Y10"} { { 12 { 0 ""} 56 0 11 11 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1481017420157 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1481017420157 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1481017422638 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1481017422638 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017422641 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.46 " "Total time spent on timing analysis during the Fitter is 0.46 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1481017424101 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481017424140 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481017424582 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1481017424582 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1481017425014 ""}
+{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:03 " "Fitter post-fit operations ending: elapsed time is 00:00:03" {  } {  } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1481017427698 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1481017427949 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex19/output_files/ex19.fit.smsg " "Generated suppressed messages file C:/New folder/ex19/output_files/ex19.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1481017428014 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 31 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2593 " "Peak virtual memory: 2593 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017428493 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:43:48 2016 " "Processing ended: Tue Dec 06 09:43:48 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017428493 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017428493 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:00 " "Total CPU time (on all processors): 00:01:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017428493 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1481017428493 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1481017429830 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481017429832 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 06 09:43:49 2016 " "Processing started: Tue Dec 06 09:43:49 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481017429832 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1481017429832 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ex19 -c ex19 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ex19 -c ex19" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1481017429832 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1481017430622 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1481017435220 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "892 " "Peak virtual memory: 892 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017435562 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:43:55 2016 " "Processing ended: Tue Dec 06 09:43:55 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017435562 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017435562 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017435562 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1481017435562 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1481017436222 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1481017437131 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481017437132 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 06 09:43:56 2016 " "Processing started: Tue Dec 06 09:43:56 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481017437132 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017437132 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ex19 -c ex19 " "Command: quartus_sta ex19 -c ex19" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017437133 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017437267 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017437850 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017437850 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017437898 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017437899 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ex19.sdc " "Synopsys Design Constraints File file not found: 'ex19.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438424 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438424 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481017438425 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz " "create_clock -period 1.000 -name spi2adc:SPI_ADC\|clk_1MHz spi2adc:SPI_ADC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481017438425 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi2dac:SPI_DAC\|clk_1MHz spi2dac:SPI_DAC\|clk_1MHz " "create_clock -period 1.000 -name spi2dac:SPI_DAC\|clk_1MHz spi2dac:SPI_DAC\|clk_1MHz" {  } {  } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1481017438425 ""}  } {  } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438425 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438428 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438433 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017438434 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017438443 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481017438461 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438461 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.533 " "Worst-case setup slack is -5.533" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.533            -134.350 CLOCK_50  " "   -5.533            -134.350 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.697             -63.997 spi2dac:SPI_DAC\|clk_1MHz  " "   -3.697             -63.997 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.608             -53.040 spi2adc:SPI_ADC\|clk_1MHz  " "   -3.608             -53.040 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438463 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438463 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.268 " "Worst-case hold slack is 0.268" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.268               0.000 CLOCK_50  " "    0.268               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.429               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.429               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.724               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.724               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438466 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438466 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438468 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438470 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.665 " "Worst-case minimum pulse width slack is -0.665" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438471 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438471 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.665             -46.732 CLOCK_50  " "   -0.665             -46.732 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438471 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -17.153 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.394             -17.153 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438471 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -11.436 spi2dac:SPI_DAC\|clk_1MHz  " "   -0.394             -11.436 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017438471 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438471 ""}
+{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017438483 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017438519 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439408 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439471 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481017439478 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439478 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.107 " "Worst-case setup slack is -5.107" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -5.107            -120.389 CLOCK_50  " "   -5.107            -120.389 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.744             -65.414 spi2dac:SPI_DAC\|clk_1MHz  " "   -3.744             -65.414 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439479 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.698             -51.186 spi2adc:SPI_ADC\|clk_1MHz  " "   -3.698             -51.186 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439479 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439479 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.117 " "Worst-case hold slack is -0.117" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.117              -0.307 CLOCK_50  " "   -0.117              -0.307 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.488               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.488               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.675               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.675               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439482 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439482 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439483 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439485 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.696 " "Worst-case minimum pulse width slack is -0.696" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439486 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439486 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.696             -43.006 CLOCK_50  " "   -0.696             -43.006 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439486 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -16.519 spi2adc:SPI_ADC\|clk_1MHz  " "   -0.394             -16.519 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439486 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.394             -11.253 spi2dac:SPI_DAC\|clk_1MHz  " "   -0.394             -11.253 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017439486 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439486 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017439497 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017439643 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440408 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440472 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481017440474 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440474 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.979 " "Worst-case setup slack is -3.979" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440475 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440475 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.979             -82.494 CLOCK_50  " "   -3.979             -82.494 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440475 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.705             -25.124 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.705             -25.124 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440475 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.685             -28.616 spi2dac:SPI_DAC\|clk_1MHz  " "   -1.685             -28.616 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440475 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440475 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.182 " "Worst-case hold slack is 0.182" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.182               0.000 CLOCK_50  " "    0.182               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.192               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.192               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.327               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.327               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440478 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440478 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440480 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440482 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.763 " "Worst-case minimum pulse width slack is -0.763" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.763             -32.290 CLOCK_50  " "   -0.763             -32.290 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.134               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.134               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.147               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.147               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440483 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440483 ""}
+{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1481017440495 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440650 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1481017440652 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440652 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.274 " "Worst-case setup slack is -3.274" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.274             -63.037 CLOCK_50  " "   -3.274             -63.037 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.637             -22.819 spi2adc:SPI_ADC\|clk_1MHz  " "   -1.637             -22.819 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.609             -27.165 spi2dac:SPI_DAC\|clk_1MHz  " "   -1.609             -27.165 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440654 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440654 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.024 " "Worst-case hold slack is 0.024" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440656 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440656 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.024               0.000 CLOCK_50  " "    0.024               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440656 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.178               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.178               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440656 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.295               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.295               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440656 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440656 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440658 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440660 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -0.790 " "Worst-case minimum pulse width slack is -0.790" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.790             -38.300 CLOCK_50  " "   -0.790             -38.300 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.143               0.000 spi2adc:SPI_ADC\|clk_1MHz  " "    0.143               0.000 spi2adc:SPI_ADC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440661 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.155               0.000 spi2dac:SPI_DAC\|clk_1MHz  " "    0.155               0.000 spi2dac:SPI_DAC\|clk_1MHz " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1481017440661 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017440661 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017442132 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017442133 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1210 " "Peak virtual memory: 1210 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017442181 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:44:02 2016 " "Processing ended: Tue Dec 06 09:44:02 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017442181 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017442181 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017442181 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017442181 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 76 s " "Quartus Prime Full Compilation was successful. 0 errors, 76 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1481017442994 ""}
diff --git a/part_4/ex19/ex19.qpf b/part_4/ex19/ex19.qpf
new file mode 100755
index 0000000..4a9e0a7
--- /dev/null
+++ b/part_4/ex19/ex19.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:44:56  December 02, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "16.0"
+DATE = "11:44:56  December 02, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "ex19"
diff --git a/part_2/ex9_partially_working/ex9.qsf b/part_4/ex19/ex19.qsf
index fbba305..d459ef9 100755
--- a/part_2/ex9_partially_working/ex9.qsf
+++ b/part_4/ex19/ex19.qsf
@@ -229,14 +229,14 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
 #
 # Quartus Prime
 # Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-# Date created = 10:28:00  November 25, 2016
+# Date created = 11:44:57  December 02, 2016
 #
 # -------------------------------------------------------------------------- #
 #
 # Notes:
 #
 # 1) The default values for assignments are stored in the file:
-#		ex9_assignment_defaults.qdf
+#		ex19_assignment_defaults.qdf
 #    If this file doesn't exist, see file:
 #		assignment_defaults.qdf
 #
@@ -249,27 +249,34 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
 
 set_global_assignment -name FAMILY "Cyclone V"
 set_global_assignment -name DEVICE 5CSEMA5F31C6
-set_global_assignment -name TOP_LEVEL_ENTITY ex9
+set_global_assignment -name TOP_LEVEL_ENTITY ex19
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:28:00  NOVEMBER 25, 2016"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:44:57  DECEMBER 02, 2016"
 set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VERILOG_FILE verilog_files/tick_50000.v
-set_global_assignment -name VERILOG_FILE verilog_files/tick_2500.v
-set_global_assignment -name VERILOG_FILE verilog_files/LFSR.v
-set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
-set_global_assignment -name VERILOG_FILE verilog_files/formula_fsm.v
-set_global_assignment -name VERILOG_FILE verilog_files/delay.v
-set_global_assignment -name VERILOG_FILE verilog_files/counter_16.v
-set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
-set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
-set_global_assignment -name VERILOG_FILE verilog_files/ex9.v
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE verilog_files/variable_echo.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2dac.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2adc.v
+set_global_assignment -name VERILOG_FILE verilog_files/pwm.v
+set_global_assignment -name VERILOG_FILE verilog_files/pulse_gen.v
+set_global_assignment -name VERILOG_FILE verilog_files/multiply_k.v
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE verilog_files/div_by_2.v
+set_global_assignment -name VERILOG_FILE verilog_files/delay_ram.v
+set_global_assignment -name VERILOG_FILE verilog_files/d_ff.v
+set_global_assignment -name VERILOG_FILE verilog_files/clktick_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
+set_global_assignment -name VERILOG_FILE ex19.v
+set_global_assignment -name QIP_FILE verilog_files/delay_block.qip
+set_global_assignment -name QIP_FILE verilog_files/ctr_13_bit.qip
+set_global_assignment -name QIP_FILE mult_by_h666.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 \ No newline at end of file
diff --git a/part_4/ex19/ex19.qsf.bak b/part_4/ex19/ex19.qsf.bak
new file mode 100755
index 0000000..818cadd
--- /dev/null
+++ b/part_4/ex19/ex19.qsf.bak
@@ -0,0 +1,72 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus Prime License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+# Date created = 11:44:57  December 02, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ex19_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEMA5F31C6
+set_global_assignment -name TOP_LEVEL_ENTITY ex19
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:44:57  DECEMBER 02, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE verilog_files/variable_echo.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2dac.v
+set_global_assignment -name VERILOG_FILE verilog_files/spi2adc.v
+set_global_assignment -name VERILOG_FILE verilog_files/pwm.v
+set_global_assignment -name VERILOG_FILE verilog_files/pulse_gen.v
+set_global_assignment -name VERILOG_FILE verilog_files/multiply_k.v
+set_global_assignment -name VERILOG_FILE verilog_files/hex_to_7seg.v
+set_global_assignment -name VERILOG_FILE verilog_files/div_by_2.v
+set_global_assignment -name VERILOG_FILE verilog_files/delay_ram.v
+set_global_assignment -name VERILOG_FILE verilog_files/d_ff.v
+set_global_assignment -name VERILOG_FILE verilog_files/clktick_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/bin2bcd_16.v
+set_global_assignment -name VERILOG_FILE verilog_files/add3_ge5.v
+set_global_assignment -name VERILOG_FILE ex19.v
+set_global_assignment -name QIP_FILE verilog_files/delay_block.qip
+set_global_assignment -name QIP_FILE verilog_files/ctr_13_bit.qip
+set_global_assignment -name VERILOG_FILE verilog_files/mult.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
diff --git a/part_4/ex19/ex19.qws b/part_4/ex19/ex19.qws
new file mode 100755
index 0000000..ab9bf4e
--- /dev/null
+++ b/part_4/ex19/ex19.qws
diff --git a/part_4/ex19/ex19.v b/part_4/ex19/ex19.v
new file mode 100755
index 0000000..d14c992
--- /dev/null
+++ b/part_4/ex19/ex19.v
@@ -0,0 +1,42 @@
+module ex19 (CLOCK_50, SW, HEX0, HEX1, HEX2, HEX3, HEX4, 
+					DAC_SDI, DAC_SCK, DAC_CS, DAC_LD,
+					ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT);
+
+	input			CLOCK_50;		// DE0 50MHz system clock
+	input [9:0]	SW;				// 10 slide switches to specify address to ROM
+	output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
+	output 		DAC_SDI;			//Serial data out to SDI of the DAC
+	output 		DAC_SCK;				//Serial clock signal to both DAC and ADC
+	output		DAC_CS;			//Chip select to the DAC, low active
+	output 		DAC_LD;			//Load new data to DAC, low active	
+	output 		ADC_SDI;			//Serial data out to SDI of the ADC
+	output 		ADC_SCK;		// ADC Clock signal
+	output		ADC_CS;			//Chip select to the ADC, low active
+	input 		ADC_SDO;			//Converted serial data from ADC	
+	output		PWM_OUT;			// PWM output to R channel
+		
+	wire			tick_10k;		// internal clock at 10kHz
+	wire [9:0] 	data_in;		// converted data from ADC
+	wire [9:0] 	data_out;	// processed data to DAC
+	wire			data_valid;
+	wire			DAC_SCK, ADC_SCK;
+	
+	clktick_16  GEN_10K (CLOCK_50, data_valid, 16'd4999, tick_10k);  	// generate 10KHz sampling clock ticks
+	spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, 		// send processed sample to DAC
+					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);		// order of signals matter
+	pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT);		// output via PWM - R-channel
+					
+	spi2adc SPI_ADC (												// perform a A-to-D conversion
+		.sysclk (CLOCK_50), 										// order of parameters do not matter
+		.channel (1'b1), 											// use only CH1
+		.start (tick_10k),
+		.data_from_adc (data_in),
+		.data_valid (data_valid),
+		.sdata_to_adc (ADC_SDI),
+		.adc_cs (ADC_CS),
+		.adc_sck (ADC_SCK),
+		.sdata_from_adc (ADC_SDO));		
+					
+	processor	echo_var_delay(CLOCK_50, tick_10k, SW, data_in, data_out, data_valid, HEX0, HEX1, HEX2, HEX3, HEX4);	// do some processing on the data
+			
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/ex19.v.bak b/part_4/ex19/ex19.v.bak
new file mode 100755
index 0000000..0e33a83
--- /dev/null
+++ b/part_4/ex19/ex19.v.bak
@@ -0,0 +1,46 @@
+module ex18 (CLOCK_50, SW, HEX0, HEX1, HEX2, 
+					DAC_SDI, DAC_SCK, DAC_CS, DAC_LD,
+					ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT);
+
+	input			CLOCK_50;		// DE0 50MHz system clock
+	input [9:0]	SW;				// 10 slide switches to specify address to ROM
+	output [6:0] HEX0, HEX1, HEX2;
+	output 		DAC_SDI;			//Serial data out to SDI of the DAC
+	output 		DAC_SCK;				//Serial clock signal to both DAC and ADC
+	output		DAC_CS;			//Chip select to the DAC, low active
+	output 		DAC_LD;			//Load new data to DAC, low active	
+	output 		ADC_SDI;			//Serial data out to SDI of the ADC
+	output 		ADC_SCK;		// ADC Clock signal
+	output		ADC_CS;			//Chip select to the ADC, low active
+	input 		ADC_SDO;			//Converted serial data from ADC	
+	output		PWM_OUT;			// PWM output to R channel
+		
+	wire			tick_10k;		// internal clock at 10kHz
+	wire [9:0] 	data_in;		// converted data from ADC
+	wire [9:0] 	data_out;	// processed data to DAC
+	wire			data_valid;
+	wire			DAC_SCK, ADC_SCK;
+	
+	clktick_16  GEN_10K (CLOCK_50, 1'b1, 16'd4999, tick_10k);  	// generate 10KHz sampling clock ticks
+	spi2dac SPI_DAC (CLOCK_50, data_out, tick_10k, 		// send processed sample to DAC
+					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);		// order of signals matter
+	pwm PWM_DC(CLOCK_50, data_out, tick_10k, PWM_OUT);		// output via PWM - R-channel
+					
+	spi2adc SPI_ADC (												// perform a A-to-D conversion
+		.sysclk (CLOCK_50), 										// order of parameters do not matter
+		.channel (1'b1), 											// use only CH1
+		.start (tick_10k),
+		.data_from_adc (data_in),
+		.data_valid (data_valid),
+		.sdata_to_adc (ADC_SDI),
+		.adc_cs (ADC_CS),
+		.adc_sck (ADC_SCK),
+		.sdata_from_adc (ADC_SDO));		
+					
+	processor	ALLPASS (CLOCK_50, tick_10k, data_in, data_out);	// do some processing on the data
+	
+	hex_to_7seg		SEG0 (HEX0, data_in[3:0]);			
+	hex_to_7seg		SEG1 (HEX1, data_in[7:4]);			
+	hex_to_7seg		SEG2 (HEX2, {2'b0,data_in[9:8]});			
+		
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/greybox_tmp/cbx_args.txt b/part_4/ex19/greybox_tmp/cbx_args.txt
new file mode 100755
index 0000000..97eb40c
--- /dev/null
+++ b/part_4/ex19/greybox_tmp/cbx_args.txt
@@ -0,0 +1,10 @@
+LPM_HINT=INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5
+LPM_REPRESENTATION=UNSIGNED
+LPM_TYPE=LPM_MULT
+LPM_WIDTHA=9
+LPM_WIDTHB=11
+LPM_WIDTHP=20
+DEVICE_FAMILY="Cyclone V"
+dataa
+datab
+result
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.db_info b/part_4/ex19/incremental_db/compiled_partitions/ex19.db_info
new file mode 100755
index 0000000..6962935
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Version_Index = 402707200
+Creation_Time = Fri Dec 02 13:34:35 2016
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.ammdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.ammdb
new file mode 100755
index 0000000..6569adc
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.ammdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.cdb
new file mode 100755
index 0000000..2a593d9
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.dfp b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.dfp
new file mode 100755
index 0000000..b1c67d6
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.dfp
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.cdb
new file mode 100755
index 0000000..1924c7b
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.hdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.hdb
new file mode 100755
index 0000000..5befede
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.hdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.sig b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hdb
new file mode 100755
index 0000000..1a0182c
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.hdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.logdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.logdb
new file mode 100755
index 0000000..d45424f
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.rcfdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.rcfdb
new file mode 100755
index 0000000..5330b52
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.cmp.rcfdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.cdb
new file mode 100755
index 0000000..e2a93fb
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.dpi b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.dpi
new file mode 100755
index 0000000..5903eb4
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.dpi
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.cdb
new file mode 100755
index 0000000..0164566
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.hb_info b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.hb_info
new file mode 100755
index 0000000..8210c55
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.hb_info
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.hdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.hdb
new file mode 100755
index 0000000..9320d69
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.hdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.sig b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.sig
new file mode 100755
index 0000000..af9b8e9
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7aee213afbf8301ed5eefc8c827f49a3
+\ No newline at end of file
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hdb
new file mode 100755
index 0000000..c7e2ec0
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.hdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.kpt b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.kpt
new file mode 100755
index 0000000..d46d54e
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.kpt
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.olf.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.olf.cdb
new file mode 100755
index 0000000..db7da22
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.olf.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.olm.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.olm.cdb
new file mode 100755
index 0000000..79f3347
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.olm.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.oln.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.oln.cdb
new file mode 100755
index 0000000..9e0e777
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.oln.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.opi b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.opi
new file mode 100755
index 0000000..56a6051
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.opi
@@ -0,0 +1 @@
+1
+\ No newline at end of file
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orf.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orf.cdb
new file mode 100755
index 0000000..db73793
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orf.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orm.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orm.cdb
new file mode 100755
index 0000000..4751c5d
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orm.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orn.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orn.cdb
new file mode 100755
index 0000000..908b3e3
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.map.orn.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.cdb
new file mode 100755
index 0000000..e2a93fb
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hbdb.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hbdb.cdb
new file mode 100755
index 0000000..0164566
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hbdb.cdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hbdb.hdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hbdb.hdb
new file mode 100755
index 0000000..9320d69
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hbdb.hdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hdb
new file mode 100755
index 0000000..c7e2ec0
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.hdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.kpt b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.kpt
new file mode 100755
index 0000000..d46d54e
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.root_partition.rrp.kpt
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.rrp.hdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.rrp.hdb
new file mode 100755
index 0000000..dda3383
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.rrp.hdb
diff --git a/part_4/ex19/incremental_db/compiled_partitions/ex19.rrs.cdb b/part_4/ex19/incremental_db/compiled_partitions/ex19.rrs.cdb
new file mode 100755
index 0000000..9559b75
--- /dev/null
+++ b/part_4/ex19/incremental_db/compiled_partitions/ex19.rrs.cdb
diff --git a/part_4/ex19/mult_by_h666.qip b/part_4/ex19/mult_by_h666.qip
new file mode 100755
index 0000000..c4c854e
--- /dev/null
+++ b/part_4/ex19/mult_by_h666.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mult_by_h666.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mult_by_h666_bb.v"]
diff --git a/part_4/ex19/mult_by_h666.v b/part_4/ex19/mult_by_h666.v
new file mode 100755
index 0000000..ab05171
--- /dev/null
+++ b/part_4/ex19/mult_by_h666.v
@@ -0,0 +1,109 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: mult_by_h666.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module mult_by_h666 (
+	dataa,
+	result);
+
+	input	[8:0]  dataa;
+	output	[19:0]  result;
+
+	wire [10:0] sub_wire0 = 11'h666;
+	wire [19:0] sub_wire1;
+	wire [19:0] result = sub_wire1[19:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (sub_wire0),
+				.result (sub_wire1),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sclr (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 9,
+		lpm_mult_component.lpm_widthb = 11,
+		lpm_mult_component.lpm_widthp = 20;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "1638"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "9"
+// Retrieval info: PRIVATE: WidthB NUMERIC "11"
+// Retrieval info: PRIVATE: WidthP NUMERIC "20"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20"
+// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
+// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]"
+// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
+// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0
+// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_4/ex19/mult_by_h666_bb.v b/part_4/ex19/mult_by_h666_bb.v
new file mode 100755
index 0000000..305ee6c
--- /dev/null
+++ b/part_4/ex19/mult_by_h666_bb.v
@@ -0,0 +1,82 @@
+// megafunction wizard: %LPM_MULT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: mult_by_h666.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module mult_by_h666 (
+	dataa,
+	result);
+
+	input	[8:0]  dataa;
+	output	[19:0]  result;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "1638"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "9"
+// Retrieval info: PRIVATE: WidthB NUMERIC "11"
+// Retrieval info: PRIVATE: WidthP NUMERIC "20"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20"
+// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
+// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]"
+// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
+// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0
+// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mult_by_h666_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_2/ex9_partially_working/output_files/ex9.asm.rpt b/part_4/ex19/output_files/ex19.asm.rpt
index 30feebf..0dbf800 100755
--- a/part_2/ex9_partially_working/output_files/ex9.asm.rpt
+++ b/part_4/ex19/output_files/ex19.asm.rpt
@@ -1,5 +1,5 @@
-Assembler report for ex9
-Fri Nov 25 11:28:01 2016
+Assembler report for ex19
+Tue Dec 06 09:47:19 2016
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 
 
@@ -10,7 +10,7 @@ Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
   2. Assembler Summary
   3. Assembler Settings
   4. Assembler Generated Files
-  5. Assembler Device Options: C:/New folder/ex9/output_files/ex9.sof
+  5. Assembler Device Options: C:/New folder/ex19/output_files/ex19.sof
   6. Assembler Messages
 
 
@@ -38,9 +38,9 @@ agreement for further details.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Fri Nov 25 11:28:01 2016 ;
-; Revision Name         ; ex9                                   ;
-; Top-level Entity Name ; ex9                                   ;
+; Assembler Status      ; Successful - Tue Dec 06 09:47:19 2016 ;
+; Revision Name         ; ex19                                  ;
+; Top-level Entity Name ; ex19                                  ;
 ; Family                ; Cyclone V                             ;
 ; Device                ; 5CSEMA5F31C6                          ;
 +-----------------------+---------------------------------------+
@@ -53,24 +53,24 @@ agreement for further details.
 +--------+---------+---------------+
 
 
-+----------------------------------------+
-; Assembler Generated Files              ;
-+----------------------------------------+
-; File Name                              ;
-+----------------------------------------+
-; C:/New folder/ex9/output_files/ex9.sof ;
-+----------------------------------------+
++------------------------------------------+
+; Assembler Generated Files                ;
++------------------------------------------+
+; File Name                                ;
++------------------------------------------+
+; C:/New folder/ex19/output_files/ex19.sof ;
++------------------------------------------+
 
 
-+------------------------------------------------------------------+
-; Assembler Device Options: C:/New folder/ex9/output_files/ex9.sof ;
-+----------------+-------------------------------------------------+
-; Option         ; Setting                                         ;
-+----------------+-------------------------------------------------+
-; Device         ; 5CSEMA5F31C6                                    ;
-; JTAG usercode  ; 0x00B4745D                                      ;
-; Checksum       ; 0x00B4745D                                      ;
-+----------------+-------------------------------------------------+
++--------------------------------------------------------------------+
+; Assembler Device Options: C:/New folder/ex19/output_files/ex19.sof ;
++----------------+---------------------------------------------------+
+; Option         ; Setting                                           ;
++----------------+---------------------------------------------------+
+; Device         ; 5CSEMA5F31C6                                      ;
+; JTAG usercode  ; 0x00DCE707                                        ;
+; Checksum       ; 0x00DCE707                                        ;
++----------------+---------------------------------------------------+
 
 
 +--------------------+
@@ -79,13 +79,13 @@ agreement for further details.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Fri Nov 25 11:27:55 2016
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex9 -c ex9
+    Info: Processing started: Tue Dec 06 09:47:13 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ex19 -c ex19
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 896 megabytes
-    Info: Processing ended: Fri Nov 25 11:28:01 2016
+    Info: Peak virtual memory: 894 megabytes
+    Info: Processing ended: Tue Dec 06 09:47:19 2016
     Info: Elapsed time: 00:00:06
     Info: Total CPU time (on all processors): 00:00:06
 
diff --git a/part_4/ex19/output_files/ex19.done b/part_4/ex19/output_files/ex19.done
new file mode 100755
index 0000000..0deb19a
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.done
@@ -0,0 +1 @@
+Tue Dec 06 09:47:27 2016
diff --git a/part_4/ex19/output_files/ex19.fit.rpt b/part_4/ex19/output_files/ex19.fit.rpt
new file mode 100755
index 0000000..b26106e
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.fit.rpt
@@ -0,0 +1,2240 @@
+Fitter report for ex19
+Tue Dec 06 09:47:11 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Fitter Partition Statistics
+ 14. Input Pins
+ 15. Output Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Fitter RAM Summary
+ 24. Routing Usage Summary
+ 25. I/O Rules Summary
+ 26. I/O Rules Details
+ 27. I/O Rules Matrix
+ 28. Fitter Device Options
+ 29. Operating Settings and Conditions
+ 30. Estimated Delay Added for Hold Timing Summary
+ 31. Estimated Delay Added for Hold Timing Details
+ 32. Fitter Messages
+ 33. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++---------------------------------+-------------------------------------------------+
+; Fitter Status                   ; Successful - Tue Dec 06 09:47:11 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex19                                            ;
+; Top-level Entity Name           ; ex19                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 118 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 136                                             ;
+; Total pins                      ; 55 / 457 ( 12 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 65,536 / 4,065,280 ( 2 % )                      ;
+; Total RAM Blocks                ; 8 / 397 ( 2 % )                                 ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; 5CSEMA5F31C6                          ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Device initialization clock source                                         ; INIT_INTOSC                           ; INIT_INTOSC                           ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; Auto RAM to MLAB Conversion                                                ; On                                    ; On                                    ;
+; Equivalent RAM and MLAB Power Up                                           ; Auto                                  ; Auto                                  ;
+; Equivalent RAM and MLAB Paused Read Capabilities                           ; Care                                  ; Care                                  ;
+; PowerPlay Power Optimization During Fitting                                ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate Full Fit Report During ECO Compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; Periphery to Core Placement and Routing Optimization                       ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Auto                                  ; Auto                                  ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Active Serial clock source                                                 ; FREQ_100MHz                           ; FREQ_100MHz                           ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Clamping Diode                                                             ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
+; Advanced Physical Optimization                                             ; On                                    ; On                                    ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.03        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processor 2            ;   1.1%      ;
+;     Processor 3            ;   1.0%      ;
+;     Processor 4            ;   1.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------------+
+; I/O Assignment Warnings                         ;
++----------+--------------------------------------+
+; Pin Name ; Reason                               ;
++----------+--------------------------------------+
+; HEX0[0]  ; Missing drive strength and slew rate ;
+; HEX0[1]  ; Missing drive strength and slew rate ;
+; HEX0[2]  ; Missing drive strength and slew rate ;
+; HEX0[3]  ; Missing drive strength and slew rate ;
+; HEX0[4]  ; Missing drive strength and slew rate ;
+; HEX0[5]  ; Missing drive strength and slew rate ;
+; HEX0[6]  ; Missing drive strength and slew rate ;
+; HEX1[0]  ; Missing drive strength and slew rate ;
+; HEX1[1]  ; Missing drive strength and slew rate ;
+; HEX1[2]  ; Missing drive strength and slew rate ;
+; HEX1[3]  ; Missing drive strength and slew rate ;
+; HEX1[4]  ; Missing drive strength and slew rate ;
+; HEX1[5]  ; Missing drive strength and slew rate ;
+; HEX1[6]  ; Missing drive strength and slew rate ;
+; HEX2[0]  ; Missing drive strength and slew rate ;
+; HEX2[1]  ; Missing drive strength and slew rate ;
+; HEX2[2]  ; Missing drive strength and slew rate ;
+; HEX2[3]  ; Missing drive strength and slew rate ;
+; HEX2[4]  ; Missing drive strength and slew rate ;
+; HEX2[5]  ; Missing drive strength and slew rate ;
+; HEX2[6]  ; Missing drive strength and slew rate ;
+; HEX3[0]  ; Missing drive strength and slew rate ;
+; HEX3[1]  ; Missing drive strength and slew rate ;
+; HEX3[2]  ; Missing drive strength and slew rate ;
+; HEX3[3]  ; Missing drive strength and slew rate ;
+; HEX3[4]  ; Missing drive strength and slew rate ;
+; HEX3[5]  ; Missing drive strength and slew rate ;
+; HEX3[6]  ; Missing drive strength and slew rate ;
+; HEX4[0]  ; Missing drive strength and slew rate ;
+; HEX4[1]  ; Missing drive strength and slew rate ;
+; HEX4[2]  ; Missing drive strength and slew rate ;
+; HEX4[3]  ; Missing drive strength and slew rate ;
+; HEX4[4]  ; Missing drive strength and slew rate ;
+; HEX4[5]  ; Missing drive strength and slew rate ;
+; HEX4[6]  ; Missing drive strength and slew rate ;
+; DAC_SDI  ; Missing drive strength and slew rate ;
+; DAC_SCK  ; Missing drive strength and slew rate ;
+; DAC_CS   ; Missing drive strength and slew rate ;
+; DAC_LD   ; Missing drive strength and slew rate ;
+; ADC_SDI  ; Missing drive strength and slew rate ;
+; ADC_SCK  ; Missing drive strength and slew rate ;
+; ADC_CS   ; Missing drive strength and slew rate ;
+; PWM_OUT  ; Missing drive strength and slew rate ;
++----------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                                                                                ;
++----------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
+; Node                                                                                                                 ; Action     ; Operation                                         ; Reason                     ; Node Port ; Node Port Name ; Destination Node                                                                                                               ; Destination Port ; Destination Port Name ;
++----------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
+; CLOCK_50~inputCLKENA0                                                                                                ; Created    ; Placement                                         ; Fitter Periphery Placement ;           ;                ;                                                                                                                                ;                  ;                       ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[3]~DUPLICATE ;                  ;                       ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[6] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[6]~DUPLICATE ;                  ;                       ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[7]~DUPLICATE ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[0]                                                                                               ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[0]~DUPLICATE                                                                                               ;                  ;                       ;
+; spi2adc:SPI_ADC|ctr[1]                                                                                               ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|ctr[1]~DUPLICATE                                                                                               ;                  ;                       ;
+; spi2adc:SPI_ADC|state[1]                                                                                             ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[1]~DUPLICATE                                                                                             ;                  ;                       ;
+; spi2adc:SPI_ADC|state[4]                                                                                             ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2adc:SPI_ADC|state[4]~DUPLICATE                                                                                             ;                  ;                       ;
+; spi2dac:SPI_DAC|state[1]                                                                                             ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:SPI_DAC|state[1]~DUPLICATE                                                                                             ;                  ;                       ;
+; spi2dac:SPI_DAC|state[2]                                                                                             ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:SPI_DAC|state[2]~DUPLICATE                                                                                             ;                  ;                       ;
+; spi2dac:SPI_DAC|state[3]                                                                                             ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization   ;           ;                ; spi2dac:SPI_DAC|state[3]~DUPLICATE                                                                                             ;                  ;                       ;
++----------------------------------------------------------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
+
+
++--------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                        ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+------------+---------------+----------------+
+; Location     ;                ;              ; HEX5[0]    ; PIN_V25       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[1]    ; PIN_AA28      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[2]    ; PIN_Y27       ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[3]    ; PIN_AB27      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[4]    ; PIN_AB26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[5]    ; PIN_AA26      ; QSF Assignment ;
+; Location     ;                ;              ; HEX5[6]    ; PIN_AA25      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[0]     ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]     ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[3]     ; PIN_Y16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[0]    ; PIN_V16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[1]    ; PIN_W16       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[2]    ; PIN_V17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[3]    ; PIN_V18       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[4]    ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[5]    ; PIN_W19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[6]    ; PIN_Y19       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[7]    ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[8]    ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; LEDR[9]    ; PIN_Y21       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CLK   ; PIN_AJ19      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_CS    ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DATA  ; PIN_AJ16      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_DC    ; PIN_AK18      ; QSF Assignment ;
+; Location     ;                ;              ; OLED_RST   ; PIN_Y18       ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; HEX5[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; HEX5[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; HEX5[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; HEX5[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; HEX5[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; HEX5[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; HEX5[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; KEY[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; KEY[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; KEY[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; KEY[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; LEDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; OLED_CLK   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; OLED_CS    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; OLED_DATA  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; OLED_DC    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ; ex19           ;              ; OLED_RST   ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+------------+---------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                     ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]      ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 455 ) ; 0.00 % ( 0 / 455 )         ; 0.00 % ( 0 / 455 )       ;
+;     -- Achieved     ; 0.00 % ( 0 / 455 ) ; 0.00 % ( 0 / 455 )         ; 0.00 % ( 0 / 455 )       ;
+;                     ;                    ;                            ;                          ;
+; Routing (by net)    ;                    ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )   ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 455 )    ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 )      ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/New folder/ex19/output_files/ex19.pin.
+
+
++------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                                            ;
++-------------------------------------------------------------+--------------------+-------+
+; Resource                                                    ; Usage              ; %     ;
++-------------------------------------------------------------+--------------------+-------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 118 / 32,070       ; < 1 % ;
+; ALMs needed [=A-B+C]                                        ; 118                ;       ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 133 / 32,070       ; < 1 % ;
+;         [a] ALMs used for LUT logic and registers           ; 43                 ;       ;
+;         [b] ALMs used for LUT logic                         ; 69                 ;       ;
+;         [c] ALMs used for registers                         ; 21                 ;       ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                  ;       ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 15 / 32,070        ; < 1 % ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32,070         ; 0 %   ;
+;         [a] Due to location constrained logic               ; 0                  ;       ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                  ;       ;
+;         [c] Due to LAB input limits                         ; 0                  ;       ;
+;         [d] Due to virtual I/Os                             ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Difficulty packing design                                   ; Low                ;       ;
+;                                                             ;                    ;       ;
+; Total LABs:  partially or completely used                   ; 20 / 3,207         ; < 1 % ;
+;     -- Logic LABs                                           ; 20                 ;       ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                  ;       ;
+;                                                             ;                    ;       ;
+; Combinational ALUT usage for logic                          ; 210                ;       ;
+;     -- 7 input functions                                    ; 0                  ;       ;
+;     -- 6 input functions                                    ; 14                 ;       ;
+;     -- 5 input functions                                    ; 22                 ;       ;
+;     -- 4 input functions                                    ; 76                 ;       ;
+;     -- <=3 input functions                                  ; 98                 ;       ;
+; Combinational ALUT usage for route-throughs                 ; 23                 ;       ;
+; Dedicated logic registers                                   ; 136                ;       ;
+;     -- By type:                                             ;                    ;       ;
+;         -- Primary logic registers                          ; 126 / 64,140       ; < 1 % ;
+;         -- Secondary logic registers                        ; 10 / 64,140        ; < 1 % ;
+;     -- By function:                                         ;                    ;       ;
+;         -- Design implementation registers                  ; 126                ;       ;
+;         -- Routing optimization registers                   ; 10                 ;       ;
+;                                                             ;                    ;       ;
+; Virtual pins                                                ; 0                  ;       ;
+; I/O pins                                                    ; 55 / 457           ; 12 %  ;
+;     -- Clock pins                                           ; 1 / 8              ; 13 %  ;
+;     -- Dedicated input pins                                 ; 0 / 21             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Hard processor system peripheral utilization                ;                    ;       ;
+;     -- Boot from FPGA                                       ; 0 / 1 ( 0 % )      ;       ;
+;     -- Clock resets                                         ; 0 / 1 ( 0 % )      ;       ;
+;     -- Cross trigger                                        ; 0 / 1 ( 0 % )      ;       ;
+;     -- S2F AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- F2S AXI                                              ; 0 / 1 ( 0 % )      ;       ;
+;     -- AXI Lightweight                                      ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDRAM                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- Interrupts                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- JTAG                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- Loan I/O                                             ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU event standby                                    ; 0 / 1 ( 0 % )      ;       ;
+;     -- MPU general purpose                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- STM event                                            ; 0 / 1 ( 0 % )      ;       ;
+;     -- TPIU trace                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- DMA                                                  ; 0 / 1 ( 0 % )      ;       ;
+;     -- CAN                                                  ; 0 / 2 ( 0 % )      ;       ;
+;     -- EMAC                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- I2C                                                  ; 0 / 4 ( 0 % )      ;       ;
+;     -- NAND Flash                                           ; 0 / 1 ( 0 % )      ;       ;
+;     -- QSPI                                                 ; 0 / 1 ( 0 % )      ;       ;
+;     -- SDMMC                                                ; 0 / 1 ( 0 % )      ;       ;
+;     -- SPI Master                                           ; 0 / 2 ( 0 % )      ;       ;
+;     -- SPI Slave                                            ; 0 / 2 ( 0 % )      ;       ;
+;     -- UART                                                 ; 0 / 2 ( 0 % )      ;       ;
+;     -- USB                                                  ; 0 / 2 ( 0 % )      ;       ;
+;                                                             ;                    ;       ;
+; Global signals                                              ; 1                  ;       ;
+; M10K blocks                                                 ; 8 / 397            ; 2 %   ;
+; Total MLAB memory bits                                      ; 0                  ;       ;
+; Total block memory bits                                     ; 65,536 / 4,065,280 ; 2 %   ;
+; Total block memory implementation bits                      ; 81,920 / 4,065,280 ; 2 %   ;
+;                                                             ;                    ;       ;
+; Total DSP Blocks                                            ; 0 / 87             ; 0 %   ;
+;                                                             ;                    ;       ;
+; Fractional PLLs                                             ; 0 / 6              ; 0 %   ;
+; Global clocks                                               ; 1 / 16             ; 6 %   ;
+; Quadrant clocks                                             ; 0 / 66             ; 0 %   ;
+; Horizontal periphery clocks                                 ; 0 / 18             ; 0 %   ;
+; SERDES Transmitters                                         ; 0 / 100            ; 0 %   ;
+; SERDES Receivers                                            ; 0 / 100            ; 0 %   ;
+; JTAGs                                                       ; 0 / 1              ; 0 %   ;
+; ASMI blocks                                                 ; 0 / 1              ; 0 %   ;
+; CRC blocks                                                  ; 0 / 1              ; 0 %   ;
+; Remote update blocks                                        ; 0 / 1              ; 0 %   ;
+; Oscillator blocks                                           ; 0 / 1              ; 0 %   ;
+; Impedance control blocks                                    ; 0 / 4              ; 0 %   ;
+; Hard Memory Controllers                                     ; 0 / 2              ; 0 %   ;
+; Average interconnect usage (total/H/V)                      ; 0.5% / 0.5% / 0.4% ;       ;
+; Peak interconnect usage (total/H/V)                         ; 7.0% / 7.4% / 5.9% ;       ;
+; Maximum fan-out                                             ; 71                 ;       ;
+; Highest non-global fan-out                                  ; 40                 ;       ;
+; Total fan-out                                               ; 1389               ;       ;
+; Average fan-out                                             ; 2.85               ;       ;
++-------------------------------------------------------------+--------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                                          ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                                   ; Top                   ; hard_block:auto_generated_inst ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+; Logic utilization (ALMs needed / total ALMs on device)      ; 118 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+; ALMs needed [=A-B+C]                                        ; 118                   ; 0                              ;
+;     [A] ALMs used in final placement [=a+b+c+d]             ; 133 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % )              ;
+;         [a] ALMs used for LUT logic and registers           ; 43                    ; 0                              ;
+;         [b] ALMs used for LUT logic                         ; 69                    ; 0                              ;
+;         [c] ALMs used for registers                         ; 21                    ; 0                              ;
+;         [d] ALMs used for memory (up to half of total ALMs) ; 0                     ; 0                              ;
+;     [B] Estimate of ALMs recoverable by dense packing       ; 15 / 32070 ( < 1 % )  ; 0 / 32070 ( 0 % )              ;
+;     [C] Estimate of ALMs unavailable [=a+b+c+d]             ; 0 / 32070 ( 0 % )     ; 0 / 32070 ( 0 % )              ;
+;         [a] Due to location constrained logic               ; 0                     ; 0                              ;
+;         [b] Due to LAB-wide signal conflicts                ; 0                     ; 0                              ;
+;         [c] Due to LAB input limits                         ; 0                     ; 0                              ;
+;         [d] Due to virtual I/Os                             ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Difficulty packing design                                   ; Low                   ; Low                            ;
+;                                                             ;                       ;                                ;
+; Total LABs:  partially or completely used                   ; 20 / 3207 ( < 1 % )   ; 0 / 3207 ( 0 % )               ;
+;     -- Logic LABs                                           ; 20                    ; 0                              ;
+;     -- Memory LABs (up to half of total LABs)               ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Combinational ALUT usage for logic                          ; 210                   ; 0                              ;
+;     -- 7 input functions                                    ; 0                     ; 0                              ;
+;     -- 6 input functions                                    ; 14                    ; 0                              ;
+;     -- 5 input functions                                    ; 22                    ; 0                              ;
+;     -- 4 input functions                                    ; 76                    ; 0                              ;
+;     -- <=3 input functions                                  ; 98                    ; 0                              ;
+; Combinational ALUT usage for route-throughs                 ; 23                    ; 0                              ;
+; Memory ALUT usage                                           ; 0                     ; 0                              ;
+;     -- 64-address deep                                      ; 0                     ; 0                              ;
+;     -- 32-address deep                                      ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Dedicated logic registers                                   ; 0                     ; 0                              ;
+;     -- By type:                                             ;                       ;                                ;
+;         -- Primary logic registers                          ; 126 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % )              ;
+;         -- Secondary logic registers                        ; 10 / 64140 ( < 1 % )  ; 0 / 64140 ( 0 % )              ;
+;     -- By function:                                         ;                       ;                                ;
+;         -- Design implementation registers                  ; 126                   ; 0                              ;
+;         -- Routing optimization registers                   ; 10                    ; 0                              ;
+;                                                             ;                       ;                                ;
+;                                                             ;                       ;                                ;
+; Virtual pins                                                ; 0                     ; 0                              ;
+; I/O pins                                                    ; 55                    ; 0                              ;
+; I/O registers                                               ; 0                     ; 0                              ;
+; Total block memory bits                                     ; 65536                 ; 0                              ;
+; Total block memory implementation bits                      ; 81920                 ; 0                              ;
+; M10K block                                                  ; 8 / 397 ( 2 % )       ; 0 / 397 ( 0 % )                ;
+; Clock enable block                                          ; 1 / 116 ( < 1 % )     ; 0 / 116 ( 0 % )                ;
+;                                                             ;                       ;                                ;
+; Connections                                                 ;                       ;                                ;
+;     -- Input Connections                                    ; 0                     ; 0                              ;
+;     -- Registered Input Connections                         ; 0                     ; 0                              ;
+;     -- Output Connections                                   ; 0                     ; 0                              ;
+;     -- Registered Output Connections                        ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Internal Connections                                        ;                       ;                                ;
+;     -- Total Connections                                    ; 1558                  ; 0                              ;
+;     -- Registered Connections                               ; 694                   ; 0                              ;
+;                                                             ;                       ;                                ;
+; External Connections                                        ;                       ;                                ;
+;     -- Top                                                  ; 0                     ; 0                              ;
+;     -- hard_block:auto_generated_inst                       ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Partition Interface                                         ;                       ;                                ;
+;     -- Input Ports                                          ; 12                    ; 0                              ;
+;     -- Output Ports                                         ; 43                    ; 0                              ;
+;     -- Bidir Ports                                          ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Registered Ports                                            ;                       ;                                ;
+;     -- Registered Input Ports                               ; 0                     ; 0                              ;
+;     -- Registered Output Ports                              ; 0                     ; 0                              ;
+;                                                             ;                       ;                                ;
+; Port Connectivity                                           ;                       ;                                ;
+;     -- Input Ports driven by GND                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND                           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC                            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC                           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source                          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout                           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout                          ; 0                     ; 0                              ;
++-------------------------------------------------------------+-----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                              ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+; ADC_SDO  ; AJ21  ; 4A       ; 62           ; 0            ; 51           ; 1                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; CLOCK_50 ; AF14  ; 3B       ; 32           ; 0            ; 0            ; 73                    ; 0                  ; yes    ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[0]    ; AB12  ; 3A       ; 12           ; 0            ; 17           ; 9                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[1]    ; AC12  ; 3A       ; 16           ; 0            ; 0            ; 9                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[2]    ; AF9   ; 3A       ; 8            ; 0            ; 34           ; 9                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[3]    ; AF10  ; 3A       ; 4            ; 0            ; 51           ; 9                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[4]    ; AD11  ; 3A       ; 2            ; 0            ; 40           ; 15                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[5]    ; AD12  ; 3A       ; 16           ; 0            ; 17           ; 14                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[6]    ; AE11  ; 3A       ; 4            ; 0            ; 34           ; 13                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[7]    ; AC9   ; 3A       ; 4            ; 0            ; 0            ; 12                    ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[8]    ; AD10  ; 3A       ; 4            ; 0            ; 17           ; 7                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
+; SW[9]    ; AE12  ; 3A       ; 2            ; 0            ; 57           ; 0                     ; 0                  ; no     ; no             ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; --                        ; User                 ; no        ;
++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+; ADC_CS  ; AG20  ; 4A       ; 62           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; ADC_SCK ; AF21  ; 4A       ; 70           ; 0            ; 17           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; ADC_SDI ; AG21  ; 4A       ; 54           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_CS  ; AD20  ; 4A       ; 82           ; 0            ; 40           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_LD  ; AK21  ; 4A       ; 68           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SCK ; AF20  ; 4A       ; 70           ; 0            ; 0            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; DAC_SDI ; AG18  ; 4A       ; 58           ; 0            ; 74           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[0] ; AE26  ; 5A       ; 89           ; 8            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[1] ; AE27  ; 5A       ; 89           ; 11           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[2] ; AE28  ; 5A       ; 89           ; 11           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[3] ; AG27  ; 5A       ; 89           ; 4            ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[4] ; AF28  ; 5A       ; 89           ; 13           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[5] ; AG28  ; 5A       ; 89           ; 13           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX0[6] ; AH28  ; 5A       ; 89           ; 4            ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[0] ; AJ29  ; 5A       ; 89           ; 6            ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[1] ; AH29  ; 5A       ; 89           ; 6            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[2] ; AH30  ; 5A       ; 89           ; 16           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[3] ; AG30  ; 5A       ; 89           ; 16           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[4] ; AF29  ; 5A       ; 89           ; 15           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[5] ; AF30  ; 5A       ; 89           ; 15           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX1[6] ; AD27  ; 5A       ; 89           ; 8            ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[0] ; AB23  ; 5A       ; 89           ; 9            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[1] ; AE29  ; 5B       ; 89           ; 23           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[2] ; AD29  ; 5B       ; 89           ; 23           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[3] ; AC28  ; 5B       ; 89           ; 20           ; 77           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[4] ; AD30  ; 5B       ; 89           ; 25           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[5] ; AC29  ; 5B       ; 89           ; 20           ; 94           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX2[6] ; AC30  ; 5B       ; 89           ; 25           ; 54           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[0] ; AD26  ; 5A       ; 89           ; 16           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[1] ; AC27  ; 5A       ; 89           ; 16           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[2] ; AD25  ; 5A       ; 89           ; 4            ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[3] ; AC25  ; 5A       ; 89           ; 4            ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[4] ; AB28  ; 5B       ; 89           ; 21           ; 37           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[5] ; AB25  ; 5A       ; 89           ; 11           ; 60           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX3[6] ; AB22  ; 5A       ; 89           ; 9            ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[0] ; AA24  ; 5A       ; 89           ; 11           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[1] ; Y23   ; 5A       ; 89           ; 13           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[2] ; Y24   ; 5A       ; 89           ; 13           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[3] ; W22   ; 5A       ; 89           ; 8            ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[4] ; W24   ; 5A       ; 89           ; 15           ; 20           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[5] ; V23   ; 5A       ; 89           ; 15           ; 3            ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; HEX4[6] ; W25   ; 5B       ; 89           ; 20           ; 43           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
+; PWM_OUT ; AJ20  ; 4A       ; 62           ; 0            ; 34           ; no              ; no                     ; 1         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 16mA             ; Off         ; --                        ; no                         ; no                          ; 0                   ; Off                         ; User                 ; -                    ; -                   ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++----------------------------------------------------------------------------+
+; I/O Bank Usage                                                             ;
++----------+------------------+---------------+--------------+---------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
++----------+------------------+---------------+--------------+---------------+
+; B2L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; B1L      ; 0 / 0 ( -- )     ; --            ; --           ; --            ;
+; 3A       ; 10 / 32 ( 31 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 3B       ; 1 / 48 ( 2 % )   ; 3.3V          ; --           ; 3.3V          ;
+; 4A       ; 9 / 80 ( 11 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 5A       ; 27 / 32 ( 84 % ) ; 3.3V          ; --           ; 3.3V          ;
+; 5B       ; 8 / 16 ( 50 % )  ; 3.3V          ; --           ; 3.3V          ;
+; 6B       ; 0 / 44 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 6A       ; 0 / 56 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7A       ; 0 / 19 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7B       ; 0 / 22 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7C       ; 0 / 12 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 7D       ; 0 / 14 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
+; 8A       ; 0 / 80 ( 0 % )   ; 2.5V          ; --           ; 2.5V          ;
++----------+------------------+---------------+--------------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                  ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank       ; Pin Name/Usage                  ; Dir.   ; I/O Standard ; Voltage             ; I/O Type     ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+; A2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A3       ; 493        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A4       ; 491        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A5       ; 489        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A6       ; 487        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A7       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; A8       ; 473        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A9       ; 471        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A10      ; 465        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A11      ; 463        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A13      ; 461        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A14      ; 455        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A15      ; 447        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A16      ; 439        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A18      ; 425        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A19      ; 423        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A20      ; 415        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A21      ; 411        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A23      ; 395        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A24      ; 391        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A25      ; 389        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; A26      ; 382        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; A28      ; 380        ; 7A             ; ^HPS_TRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; A29      ; 378        ; 7A             ; ^HPS_TMS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA5      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; AA6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA7      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA8      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AA9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA12     ; 74         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA13     ; 90         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA14     ; 122        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA15     ; 120        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA16     ; 146        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA17     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA18     ; 168        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA19     ; 176        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA20     ; 200        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA21     ; 210        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AA22     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA23     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AA24     ; 228        ; 5A             ; HEX4[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AA25     ; 224        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA26     ; 252        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA27     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AA28     ; 251        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AA29     ;            ; 5B             ; VREFB5BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AA30     ; 250        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB6      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB7      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB8      ; 43         ; 3A             ; ^nCSO, DATA4                    ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AB9      ; 42         ; 3A             ; #TDO                            ; output ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB10     ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; AB11     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB12     ; 72         ; 3A             ; SW[0]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AB13     ; 88         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB14     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB15     ; 106        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB16     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AB17     ; 144        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB18     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB19     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB20     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB21     ; 208        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AB22     ; 225        ; 5A             ; HEX3[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB23     ; 227        ; 5A             ; HEX2[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB24     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AB25     ; 230        ; 5A             ; HEX3[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB26     ; 226        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB27     ; 254        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AB28     ; 249        ; 5B             ; HEX3[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AB29     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AB30     ; 248        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; AC1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC5      ; 46         ; 3A             ; #TCK                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC7      ; 45         ; 3A             ; ^AS_DATA3, DATA3                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AC8      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC9      ; 58         ; 3A             ; SW[7]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC10     ;            ; 3A             ; VCCPD3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC11     ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC12     ; 82         ; 3A             ; SW[1]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AC13     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC14     ; 104        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC15     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC16     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC17     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC18     ; 162        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC19     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC20     ; 186        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC21     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AC22     ; 207        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC23     ; 205        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AC24     ;            ; 5A             ; VREFB5AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC25     ; 215        ; 5A             ; HEX3[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC26     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AC27     ; 242        ; 5A             ; HEX3[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC28     ; 245        ; 5B             ; HEX2[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC29     ; 247        ; 5B             ; HEX2[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AC30     ; 259        ; 5B             ; HEX2[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD3      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD4      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD6      ;            ; 3A             ; VREFB3AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD7      ; 62         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD8      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD9      ; 55         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD10     ; 56         ; 3A             ; SW[8]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD11     ; 54         ; 3A             ; SW[4]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD12     ; 80         ; 3A             ; SW[5]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD14     ; 98         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD15     ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD16     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD17     ; 160        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD18     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD19     ; 184        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD20     ; 199        ; 4A             ; DAC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AD21     ; 197        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD22     ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; AD23     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AD24     ; 211        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AD25     ; 213        ; 5A             ; HEX3[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD26     ; 240        ; 5A             ; HEX3[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD27     ; 222        ; 5A             ; HEX1[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD28     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AD29     ; 255        ; 5B             ; HEX2[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AD30     ; 257        ; 5B             ; HEX2[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE4      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE5      ; 49         ; 3A             ; ^AS_DATA1, DATA1                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE6      ; 51         ; 3A             ; ^AS_DATA0, ASDO, DATA0          ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE7      ; 60         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE8      ; 47         ; 3A             ; ^AS_DATA2, DATA2                ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; AE9      ; 53         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE10     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE11     ; 59         ; 3A             ; SW[6]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE12     ; 52         ; 3A             ; SW[9]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AE13     ; 95         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE14     ; 96         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE15     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE16     ; 139        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE17     ; 135        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE18     ; 167        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE19     ; 165        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE20     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AE21     ;            ; 3B, 4A         ; VCCPD3B4A                       ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE22     ; 191        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE23     ; 189        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE24     ; 209        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AE25     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AE26     ; 220        ; 5A             ; HEX0[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE27     ; 229        ; 5A             ; HEX0[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE28     ; 231        ; 5A             ; HEX0[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE29     ; 253        ; 5B             ; HEX2[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AE30     ;            ; 5B             ; VCCIO5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF2      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF4      ; 66         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF5      ; 64         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF6      ; 75         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF7      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF8      ; 70         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF9      ; 67         ; 3A             ; SW[2]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF10     ; 57         ; 3A             ; SW[3]                           ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF11     ; 87         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF12     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF13     ; 93         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF14     ; 114        ; 3B             ; CLOCK_50                        ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF15     ; 112        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF16     ; 137        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF17     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF18     ; 133        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF19     ; 159        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF20     ; 175        ; 4A             ; DAC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF21     ; 173        ; 4A             ; ADC_SCK                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AF22     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AF23     ; 183        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF24     ; 181        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF25     ; 206        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF26     ; 204        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AF27     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AF28     ; 235        ; 5A             ; HEX0[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF29     ; 237        ; 5A             ; HEX1[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AF30     ; 239        ; 5A             ; HEX1[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG1      ; 71         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG2      ; 83         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG3      ; 63         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG4      ;            ; 3A             ; VCCIO3A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG5      ; 78         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG6      ; 73         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG7      ; 68         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG8      ; 65         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG9      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG10     ; 86         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG11     ; 85         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG12     ; 103        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG13     ; 101        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG14     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG15     ; 127        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG16     ; 134        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG17     ; 132        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG18     ; 150        ; 4A             ; DAC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG19     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG20     ; 157        ; 4A             ; ADC_CS                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG21     ; 143        ; 4A             ; ADC_SDI                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AG22     ; 166        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG23     ; 163        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG24     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AG25     ; 190        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG26     ; 203        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AG27     ; 212        ; 5A             ; HEX0[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG28     ; 233        ; 5A             ; HEX0[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AG29     ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AG30     ; 243        ; 5A             ; HEX1[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH1      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH2      ; 69         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH3      ; 81         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH4      ; 61         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH5      ; 76         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH6      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH7      ; 115        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH8      ; 113        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH9      ; 84         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH10     ; 118        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH11     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH12     ; 126        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH13     ; 111        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH14     ; 109        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH15     ; 125        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH16     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH17     ; 147        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH18     ; 145        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH19     ; 148        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH20     ; 141        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH21     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AH22     ; 164        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH23     ; 174        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH24     ; 161        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH25     ; 188        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH26     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AH27     ; 201        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AH28     ; 214        ; 5A             ; HEX0[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH29     ; 218        ; 5A             ; HEX1[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AH30     ; 241        ; 5A             ; HEX1[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ1      ; 79         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ2      ; 77         ; 3A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ3      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ4      ; 94         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ5      ; 99         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ6      ; 102        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ7      ; 100        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ8      ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ9      ; 110        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ10     ; 116        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ11     ; 119        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ12     ; 124        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ13     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ14     ; 131        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ15     ;            ; 3B             ; VREFB3BN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ16     ; 142        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ17     ; 151        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ18     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ19     ; 155        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ20     ; 158        ; 4A             ; PWM_OUT                         ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AJ21     ; 156        ; 4A             ; ADC_SDO                         ; input  ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AJ22     ; 172        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ23     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AJ24     ; 182        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ25     ; 180        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ26     ; 187        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ27     ; 195        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AJ28     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AJ29     ; 216        ; 5A             ; HEX1[0]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; AJ30     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK2      ; 91         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK3      ; 89         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK4      ; 92         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK5      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK6      ; 97         ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK7      ; 107        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK8      ; 105        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK9      ; 108        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK10     ;            ; 3B             ; VCCIO3B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK11     ; 117        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK12     ; 123        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK13     ; 121        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK14     ; 129        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK15     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK16     ; 140        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK17     ;            ; 4A             ; VREFB4AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK18     ; 149        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK19     ; 153        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK20     ;            ; 4A             ; VCCIO4A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; AK21     ; 171        ; 4A             ; DAC_LD                          ; output ; 3.3-V LVTTL  ;                     ; Column I/O   ; Y               ; no       ; Off          ;
+; AK22     ; 169        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK23     ; 179        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK24     ; 177        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK25     ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; AK26     ; 185        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK27     ; 193        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK28     ; 198        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; AK29     ; 196        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B1       ; 509        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B2       ; 507        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B3       ; 513        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B4       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; B5       ; 512        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B6       ; 510        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B7       ; 477        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B8       ; 481        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B10      ;            ; 8A             ; VREFB8AN0                       ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; B11      ; 469        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B12      ; 464        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B13      ; 459        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B15      ; 451        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B16      ; 441        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B17      ; 431        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B18      ; 418        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B20      ; 417        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B21      ; 413        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B22      ; 399        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B23      ; 397        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B25      ; 387        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B26      ; 386        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; B27      ; 381        ; 7A             ; ^HPS_TDI                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B28      ; 376        ; 7A             ; ^HPS_TDO                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; B29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; B30      ; 365        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C2       ; 517        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C3       ; 511        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C4       ; 501        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C5       ; 497        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C7       ; 475        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C8       ; 479        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C9       ; 485        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C10      ; 483        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C11      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; C12      ; 467        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C13      ; 462        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C14      ; 448        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C15      ; 453        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C17      ; 433        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C18      ; 435        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C19      ; 427        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C20      ; 421        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C22      ; 396        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C23      ; 401        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C24      ; 393        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C25      ; 388        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; C26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; C27      ; 374        ; 7A             ; ^HPS_nRST                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; C28      ; 369        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C29      ; 367        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; C30      ; 363        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D1       ; 529        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D2       ; 515        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D4       ; 521        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D5       ; 499        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D6       ; 495        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D7       ; 505        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D8       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D9       ; 480        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D10      ; 472        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D11      ; 470        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D12      ; 496        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D14      ; 446        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D15      ; 449        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D16      ; 445        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D17      ; 440        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D18      ;            ; 7C             ; VCCIO7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D19      ; 426        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D20      ; 420        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D21      ; 419        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D22      ; 402        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D23      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; D24      ; 404        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; D25      ; 384        ; 7A             ; ^HPS_CLK1                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D26      ; 373        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; D27      ; 371        ; 6A             ; HPS_RZQ_0                       ;        ;              ;                     ; --           ;                 ; no       ; On           ;
+; D28      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; D29      ; 361        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; D30      ; 359        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E1       ; 527        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E2       ; 525        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E3       ; 523        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E4       ; 519        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E5       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E6       ; 533        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E7       ; 531        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E8       ; 503        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E9       ; 478        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E11      ; 504        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E12      ; 494        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E13      ; 488        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E14      ; 454        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E15      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E16      ; 443        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E17      ; 438        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E18      ; 437        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E19      ; 424        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E20      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; E21      ; 412        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E22      ;            ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS             ; power  ;              ;                     ; --           ;                 ; --       ; --           ;
+; E23      ; 394        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E24      ; 403        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; E25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; E26      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; E27      ; 357        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E28      ; 351        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E29      ; 353        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; E30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F1       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F3       ; 539        ; 9A             ; ^CONF_DONE                      ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F4       ; 541        ; 9A             ; ^nSTATUS                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F6       ; 537        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F8       ; 536        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F9       ; 534        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F10      ; 528        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F11      ; 502        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F12      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F13      ; 486        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F14      ; 468        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F15      ; 466        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F16      ; 442        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F18      ; 430        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F19      ; 410        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F20      ; 407        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F21      ; 409        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; F22      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; F23      ; 375        ; 7A             ; ^HPS_nPOR                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F24      ; 383        ; 7A             ; ^HPS_PORSEL                     ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F25      ; 385        ; 7A             ; ^HPS_CLK2                       ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; F26      ; 341        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; F28      ; 345        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F29      ; 349        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; F30      ; 347        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G1       ;            ;                ; GND                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G2       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G5       ; 542        ; 9A             ; ^nCE                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G6       ; 543        ; 9A             ; ^MSEL2                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G7       ; 535        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G8       ; 492        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G9       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G10      ; 526        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G11      ; 520        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G12      ; 518        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G13      ; 484        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G14      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G15      ; 460        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G16      ; 444        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G17      ; 436        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G18      ; 432        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G19      ;            ; 7B             ; VCCIO7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G20      ; 416        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G21      ; 392        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G22      ; 400        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; G23      ; 377        ; 7A             ; ^VCCRSTCLK_HPS                  ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; G24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; G25      ; 370        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G26      ; 362        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G27      ; 339        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; G28      ; 335        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; G29      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; G30      ; 343        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H6       ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H7       ; 508        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H8       ; 490        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H9       ;            ; --             ; VCCBAT                          ; power  ;              ; 1.2V                ; --           ;                 ; --       ; --           ;
+; H10      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; H12      ; 500        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H13      ; 498        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H14      ; 482        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H15      ; 458        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H16      ;            ; 7D             ; VCCIO7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H17      ; 434        ; 7C             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H18      ; 422        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H19      ; 406        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H20      ; 398        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H21      ;            ; 7A             ; VCCIO7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H22      ; 379        ; 7A             ; ^HPS_TCK                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; H23      ; 390        ; 7A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; H24      ; 364        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H25      ; 368        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H26      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; H27      ; 360        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H28      ; 333        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H29      ; 331        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; H30      ; 337        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J5       ; 545        ; 9A             ; ^nCONFIG                        ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J6       ; 547        ; 9A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J7       ; 506        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J9       ; 532        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J10      ; 530        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J11      ;            ; --             ; VCCPGM                          ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J12      ; 516        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J13      ;            ; 8A             ; VCCIO8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J14      ; 476        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J15      ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J16      ;            ; --             ; VCC_AUX                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J17      ;            ; 7C             ; VCCPD7C_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J19      ; 408        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; J20      ;            ; --             ; VCCRSTCLK_HPS                   ; power  ;              ; 1.8V/2.5V/3.0V/3.3V ; --           ;                 ; --       ; --           ;
+; J21      ;            ; --             ; VCC_AUX_SHARED                  ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; J22      ; 372        ; 7A             ; ^GND                            ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; J23      ; 354        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J24      ; 352        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J25      ; 344        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J26      ; 323        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J27      ; 346        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; J29      ; 327        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; J30      ; 329        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K6       ; 540        ; 9A             ; ^MSEL1                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; K7       ; 522        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K8       ; 524        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K9       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K11      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K12      ; 514        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K13      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K14      ; 474        ; 8A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K16      ;            ; 7D             ; VCCPD7D_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K17      ; 414        ; 7B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; K18      ;            ; 7B             ; VCCPD7B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K19      ;            ; 7A             ; VCCPD7A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K21      ; 366        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K22      ; 336        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K23      ; 338        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; K25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; K26      ; 322        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K27      ; 319        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K28      ; 325        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K29      ; 321        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; K30      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L7       ; 544        ; 9A             ; ^MSEL3                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L8       ; 538        ; 9A             ; ^MSEL0                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L9       ; 546        ; 9A             ; ^MSEL4                          ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; L10      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L12      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L14      ;            ; 8A             ; VCCPD8A                         ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; L21      ;            ; --             ; VCCPLL_HPS                      ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; L23      ; 350        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L24      ; 328        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L25      ; 330        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L26      ; 320        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L27      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; L28      ; 313        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L29      ; 315        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; L30      ; 317        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; M5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; M16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M17      ; 450        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; M18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M19      ; 334        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M22      ; 308        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M23      ; 348        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M24      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; M25      ; 324        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M26      ; 314        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M27      ; 312        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M28      ; 309        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; M29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; M30      ; 311        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N16      ; 452        ; 7D             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; N17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N18      ; 332        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N20      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; N21      ;            ; 6A             ; VCCIO6A_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N22      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; N23      ; 310        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N24      ; 318        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N25      ; 316        ; 6A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N26      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; N27      ; 297        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N28      ; 303        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N29      ; 305        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; N30      ; 307        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; P5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P15      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; P20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; P21      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P22      ; 294        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P23      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P24      ; 290        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P25      ; 288        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P26      ; 298        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P27      ; 296        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P28      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; P29      ; 299        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; P30      ; 301        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R7       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; R17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; R18      ; 302        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R19      ; 300        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R20      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R21      ; 286        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R22      ; 284        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R23      ;            ; 6A, 6B         ; VCCPD6A6B_HPS                   ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R24      ; 272        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R25      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; R26      ; 280        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R27      ; 282        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R28      ; 293        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R29      ; 295        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; R30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; T5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T16      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T17      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T19      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; T20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T21      ; 278        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T22      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; T23      ; 270        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T24      ; 268        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T25      ; 266        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T26      ; 304        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T27      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; T28      ; 287        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T29      ; 289        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; T30      ; 291        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U7       ; 50         ; 3A             ; ^DCLK                           ;        ;              ;                     ; Weak Pull Up ;                 ; --       ; On           ;
+; U8       ; 48         ; 3A             ; #TDI                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; U9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U16      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U17      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U18      ;            ; --             ; VCC_HPS                         ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U19      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; U20      ; 276        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U21      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; U22      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U23      ;            ; 5B             ; VCCPD5B                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; U24      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U25      ; 264        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U26      ; 306        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U27      ; 273        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U28      ; 285        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; U29      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; U30      ; 283        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; --       ; --           ;
+; V1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; V5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V6       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V8       ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V9       ; 44         ; 3A             ; #TMS                            ; input  ;              ;                     ; --           ;                 ; --       ; --           ;
+; V10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V15      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; V16      ; 138        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V17      ; 154        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V18      ; 194        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; V19      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V20      ; 292        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V21      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; V22      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V23      ; 236        ; 5A             ; HEX4[5]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; V24      ;            ; 5A             ; VCCPD5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; V25      ; 246        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V26      ;            ; 6B             ; VCCIO6B_HPS                     ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; V27      ; 265        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V28      ; 271        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V29      ; 275        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; V30      ; 281        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W3       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W4       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W5       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W6       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W9       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W10      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W11      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W12      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W13      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W14      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; W15      ; 130        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W16      ; 136        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W17      ; 152        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W18      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W19      ; 192        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; W20      ; 217        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W21      ; 221        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W22      ; 223        ; 5A             ; HEX4[3]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W23      ;            ; 5A             ; VCCIO5A                         ; power  ;              ; 3.3V                ; --           ;                 ; --       ; --           ;
+; W24      ; 238        ; 5A             ; HEX4[4]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W25      ; 244        ; 5B             ; HEX4[6]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; W26      ; 274        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W27      ; 261        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W28      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; W29      ; 279        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; W30      ; 277        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y1       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y2       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y3       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y4       ;            ;                ; DNU                             ;        ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y5       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y6       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y7       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y8       ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y9       ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y10      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y11      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y12      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y13      ;            ; --             ; VCC                             ; power  ;              ; 1.1V                ; --           ;                 ; --       ; --           ;
+; Y14      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y15      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y16      ; 128        ; 3B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y17      ; 170        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y18      ; 178        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y19      ; 202        ; 4A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Column I/O   ;                 ; no       ; On           ;
+; Y20      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y21      ; 219        ; 5A             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y22      ;            ; --             ; VCCA_FPLL                       ; power  ;              ; 2.5V                ; --           ;                 ; --       ; --           ;
+; Y23      ; 232        ; 5A             ; HEX4[1]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y24      ; 234        ; 5A             ; HEX4[2]                         ; output ; 3.3-V LVTTL  ;                     ; Row I/O      ; Y               ; no       ; Off          ;
+; Y25      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
+; Y26      ; 256        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y27      ; 258        ; 5B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y28      ; 269        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y29      ; 263        ; 6B             ; RESERVED_INPUT_WITH_WEAK_PULLUP ;        ;              ;                     ; Row I/O      ;                 ; no       ; On           ;
+; Y30      ;            ;                ; GND                             ; gnd    ;              ;                     ; --           ;                 ; --       ; --           ;
++----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
++------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                           ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                         ; Entity Name     ; Library Name ;
++------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex19                                                ; 118.0 (0.5)          ; 131.5 (0.5)                      ; 13.5 (0.0)                                        ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 210 (1)             ; 136 (0)                   ; 0 (0)         ; 65536             ; 8     ; 0          ; 55   ; 0            ; |ex19                                                                                                                                                                                       ; ex19            ; work         ;
+;    |clktick_16:GEN_10K|                              ; 11.5 (11.5)          ; 11.5 (11.5)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 20 (20)             ; 17 (17)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|clktick_16:GEN_10K                                                                                                                                                                    ; clktick_16      ; work         ;
+;    |processor:echo_var_delay|                        ; 68.8 (10.0)          ; 68.8 (10.0)                      ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 132 (20)            ; 26 (10)                   ; 0 (0)         ; 65536             ; 8     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay                                                                                                                                                              ; processor       ; work         ;
+;       |bin2bcd_16:bcd|                               ; 21.5 (0.0)           ; 21.5 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 39 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd                                                                                                                                               ; bin2bcd_16      ; work         ;
+;          |add3_ge5:A12|                              ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A12                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A15|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A15                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A18|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A18                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A21|                              ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A21                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A22|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A22                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A25|                              ; 4.0 (4.0)            ; 4.0 (4.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A25                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A26|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A26                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A29|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A29                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A30|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A30                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A33|                              ; 0.5 (0.5)            ; 0.5 (0.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 1 (1)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A33                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A34|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A34                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A35|                              ; 2.0 (2.0)            ; 2.0 (2.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 4 (4)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A35                                                                                                                                  ; add3_ge5        ; work         ;
+;       |ctr_13_bit:ctr|                               ; 6.5 (0.0)            ; 6.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (0)              ; 16 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|ctr_13_bit:ctr                                                                                                                                               ; ctr_13_bit      ; work         ;
+;          |lpm_counter:LPM_COUNTER_component|         ; 6.5 (0.0)            ; 6.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (0)              ; 16 (0)                    ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component                                                                                                             ; lpm_counter     ; work         ;
+;             |cntr_cjh:auto_generated|                ; 6.5 (6.5)            ; 6.5 (6.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 16 (16)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated                                                                                     ; cntr_cjh        ; work         ;
+;       |delay_block:del|                              ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 65536             ; 8     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|delay_block:del                                                                                                                                              ; delay_block     ; work         ;
+;          |altsyncram:altsyncram_component|           ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 65536             ; 8     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component                                                                                                              ; altsyncram      ; work         ;
+;             |altsyncram_nm22:auto_generated|         ; 0.0 (0.0)            ; 0.0 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 0 (0)               ; 0 (0)                     ; 0 (0)         ; 65536             ; 8     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated                                                                               ; altsyncram_nm22 ; work         ;
+;       |hex_to_7seg:h0|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|hex_to_7seg:h0                                                                                                                                               ; hex_to_7seg     ; work         ;
+;       |hex_to_7seg:h1|                               ; 3.5 (3.5)            ; 3.5 (3.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 7 (7)               ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|hex_to_7seg:h1                                                                                                                                               ; hex_to_7seg     ; work         ;
+;       |hex_to_7seg:h2|                               ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 13 (13)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|hex_to_7seg:h2                                                                                                                                               ; hex_to_7seg     ; work         ;
+;       |mult_by_h666:mul_by_h666|                     ; 16.3 (0.0)           ; 16.3 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 33 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666                                                                                                                                     ; mult_by_h666    ; work         ;
+;          |lpm_mult:lpm_mult_component|               ; 16.3 (0.0)           ; 16.3 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 33 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component                                                                                                         ; lpm_mult        ; work         ;
+;             |multcore:mult_core|                     ; 16.3 (3.3)           ; 16.3 (3.3)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 33 (7)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core                                                                                      ; multcore        ; work         ;
+;                |mpar_add:padder|                     ; 13.0 (0.0)           ; 13.0 (0.0)                       ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 26 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder                                                                      ; mpar_add        ; work         ;
+;                   |lpm_add_sub:adder[0]|             ; 7.5 (0.0)            ; 7.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 15 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; lpm_add_sub     ; work         ;
+;                      |add_sub_a9h:auto_generated|    ; 7.5 (7.5)            ; 7.5 (7.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 15 (15)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated                      ; add_sub_a9h     ; work         ;
+;                   |mpar_add:sub_par_add|             ; 5.5 (0.0)            ; 5.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 11 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; mpar_add        ; work         ;
+;                      |lpm_add_sub:adder[0]|          ; 5.5 (0.0)            ; 5.5 (0.0)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 11 (0)              ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; lpm_add_sub     ; work         ;
+;                         |add_sub_e9h:auto_generated| ; 5.5 (5.5)            ; 5.5 (5.5)                        ; 0.0 (0.0)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 11 (11)             ; 0 (0)                     ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated ; add_sub_e9h     ; work         ;
+;    |pwm:PWM_DC|                                      ; 9.1 (9.1)            ; 11.5 (11.5)                      ; 2.4 (2.4)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 16 (16)             ; 21 (21)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|pwm:PWM_DC                                                                                                                                                                            ; pwm             ; work         ;
+;    |spi2adc:SPI_ADC|                                 ; 12.3 (12.3)          ; 21.4 (21.4)                      ; 9.1 (9.1)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 21 (21)             ; 43 (43)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|spi2adc:SPI_ADC                                                                                                                                                                       ; spi2adc         ; work         ;
+;    |spi2dac:SPI_DAC|                                 ; 15.4 (15.4)          ; 17.7 (17.7)                      ; 2.3 (2.3)                                         ; 0.0 (0.0)                        ; 0.0 (0.0)            ; 20 (20)             ; 29 (29)                   ; 0 (0)         ; 0                 ; 0     ; 0          ; 0    ; 0            ; |ex19|spi2dac:SPI_DAC                                                                                                                                                                       ; spi2dac         ; work         ;
++------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                                     ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; Name     ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5   ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+; SW[9]    ; Input    ; -- ; --   ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; HEX0[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX0[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX1[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX2[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX3[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[0]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[1]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[2]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[3]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[4]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[5]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; HEX4[6]  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; DAC_LD   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SDI  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_SCK  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; ADC_CS   ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; PWM_OUT  ; Output   ; -- ; --   ; --   ; -- ; (0)  ; (31)  ; --     ; --                     ; --                       ;
+; SW[8]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; CLOCK_50 ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[6]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[5]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[4]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[3]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[2]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[1]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[0]    ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; SW[7]    ; Input    ; -- ; (0)  ; --   ; -- ; --   ; --    ; --     ; --                     ; --                       ;
+; ADC_SDO  ; Input    ; -- ; --   ; (0)  ; -- ; --   ; --    ; --     ; --                     ; --                       ;
++----------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                                                                                                                                                     ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                                                                                                                                                  ; Pad To Core Index ; Setting ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; SW[9]                                                                                                                                                                                                ;                   ;         ;
+; SW[8]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~42 ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~1  ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~13 ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~17 ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~29 ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated|op_1~33 ; 1                 ; 0       ;
+;      - processor:echo_var_delay|Add1~33                                                                                                                                                              ; 1                 ; 0       ;
+; CLOCK_50                                                                                                                                                                                             ;                   ;         ;
+;      - spi2dac:SPI_DAC|clk_1MHz                                                                                                                                                                      ; 0                 ; 0       ;
+;      - spi2adc:SPI_ADC|clk_1MHz                                                                                                                                                                      ; 0                 ; 0       ;
+; SW[6]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~46                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~1                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~5                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~9                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~13                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~17                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~21                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~25                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~29                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~33                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|Add1~25                                                                                                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~5                                                                               ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][4]~6                                                                               ; 0                 ; 0       ;
+; SW[5]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~50                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~46                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~1                       ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~5                       ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~9                       ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~13                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~17                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~21                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~25                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~29                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~33                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|Add1~21                                                                                                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~5                                                                               ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][4]~6                                                                               ; 1                 ; 0       ;
+; SW[4]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~50                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~46                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~1                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~5                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~9                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~13                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~17                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~21                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~25                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~29                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~33                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|Add1~17                                                                                                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~5                                                                               ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][4]~6                                                                               ; 0                 ; 0       ;
+; SW[3]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~42                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~37                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|Add1~13                                                                                                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][10]~0                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][11]~1                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][12]~2                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][13]~3                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~4                                                                              ; 1                 ; 0       ;
+; SW[2]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~42                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~37                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|Add1~9                                                                                                                                                               ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][10]~0                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][11]~1                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][12]~2                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][13]~3                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~4                                                                              ; 0                 ; 0       ;
+; SW[1]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~42                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~37                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|Add1~5                                                                                                                                                               ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][10]~0                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][11]~1                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][12]~2                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][13]~3                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~4                                                                              ; 0                 ; 0       ;
+; SW[0]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~54                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~42                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~37                      ; 1                 ; 0       ;
+;      - processor:echo_var_delay|Add1~1                                                                                                                                                               ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][10]~0                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][11]~1                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][12]~2                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][13]~3                                                                              ; 1                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[0][14]~4                                                                              ; 1                 ; 0       ;
+; SW[7]                                                                                                                                                                                                ;                   ;         ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~1                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~5                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~9                       ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~13                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~17                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~21                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~25                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~29                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated|op_1~33                      ; 0                 ; 0       ;
+;      - processor:echo_var_delay|Add1~29                                                                                                                                                              ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][9]~5                                                                               ; 0                 ; 0       ;
+;      - processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|romout[1][4]~6                                                                               ; 0                 ; 0       ;
+; ADC_SDO                                                                                                                                                                                              ;                   ;         ;
+;      - spi2adc:SPI_ADC|shift_reg[0]                                                                                                                                                                  ; 1                 ; 0       ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                        ;
++-----------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                        ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-----------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                    ; PIN_AF14           ; 3       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                    ; PIN_AF14           ; 71      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; clktick_16:GEN_10K|Equal0~3 ; LABCELL_X74_Y6_N54 ; 10      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; clktick_16:GEN_10K|tick     ; FF_X74_Y6_N59      ; 24      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|adc_cs      ; FF_X67_Y7_N20      ; 40      ; Clock, Clock enable        ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|adc_done    ; FF_X67_Y7_N2       ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|always3~0   ; LABCELL_X67_Y7_N6  ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2adc:SPI_ADC|clk_1MHz    ; FF_X68_Y7_N53      ; 33      ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|Equal0~0    ; LABCELL_X68_Y7_N48 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|always3~0   ; LABCELL_X67_Y6_N9  ; 9       ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; spi2dac:SPI_DAC|clk_1MHz    ; FF_X68_Y7_N50      ; 26      ; Clock                      ; no     ; --                   ; --               ; --                        ;
++-----------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                         ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; Name     ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+; CLOCK_50 ; PIN_AF14 ; 71      ; Global Clock         ; GCLK6            ; --                        ;
++----------+----------+---------+----------------------+------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++--------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; Name                                                                                                               ; Type       ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF  ; Location                                                                                                                        ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs         ;
++--------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ALTSYNCRAM ; M10K block ; Simple Dual Port ; Single Clock ; 8192         ; 9            ; 8192         ; 9            ; yes                    ; no                      ; yes                    ; yes                     ; 73728 ; 8192                        ; 8                           ; 8192                        ; 8                           ; 65536               ; 8           ; 0          ; None ; M10K_X69_Y10_N0, M10K_X69_Y6_N0, M10K_X69_Y9_N0, M10K_X69_Y8_N0, M10K_X69_Y3_N0, M10K_X69_Y7_N0, M10K_X69_Y5_N0, M10K_X69_Y4_N0 ; Don't care           ; New data        ; New data        ; Off      ; No                     ; No - Address Too Wide ;
++--------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++-----------------------------------------------------------------------+
+; Routing Usage Summary                                                 ;
++---------------------------------------------+-------------------------+
+; Routing Resource Type                       ; Usage                   ;
++---------------------------------------------+-------------------------+
+; Block interconnects                         ; 525 / 289,320 ( < 1 % ) ;
+; C12 interconnects                           ; 75 / 13,420 ( < 1 % )   ;
+; C2 interconnects                            ; 301 / 119,108 ( < 1 % ) ;
+; C4 interconnects                            ; 200 / 56,300 ( < 1 % )  ;
+; DQS bus muxes                               ; 0 / 25 ( 0 % )          ;
+; DQS-18 I/O buses                            ; 0 / 25 ( 0 % )          ;
+; DQS-9 I/O buses                             ; 0 / 25 ( 0 % )          ;
+; Direct links                                ; 38 / 289,320 ( < 1 % )  ;
+; Global clocks                               ; 1 / 16 ( 6 % )          ;
+; HPS SDRAM PLL inputs                        ; 0 / 1 ( 0 % )           ;
+; HPS SDRAM PLL outputs                       ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs         ; 0 / 9 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_INPUTs          ; 0 / 7 ( 0 % )           ;
+; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs         ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_CROSS_TRIGGER_INPUTs          ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs         ; 0 / 24 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_INPUTs                ; 0 / 37 ( 0 % )          ;
+; HPS_INTERFACE_DBG_APB_OUTPUTs               ; 0 / 55 ( 0 % )          ;
+; HPS_INTERFACE_DMA_INPUTs                    ; 0 / 16 ( 0 % )          ;
+; HPS_INTERFACE_DMA_OUTPUTs                   ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_FPGA2HPS_INPUTs               ; 0 / 287 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2HPS_OUTPUTs              ; 0 / 154 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_INPUTs             ; 0 / 852 ( 0 % )         ;
+; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs            ; 0 / 408 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_INPUTs               ; 0 / 165 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs  ; 0 / 67 ( 0 % )          ;
+; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % )         ;
+; HPS_INTERFACE_HPS2FPGA_OUTPUTs              ; 0 / 282 ( 0 % )         ;
+; HPS_INTERFACE_INTERRUPTS_INPUTs             ; 0 / 64 ( 0 % )          ;
+; HPS_INTERFACE_INTERRUPTS_OUTPUTs            ; 0 / 42 ( 0 % )          ;
+; HPS_INTERFACE_JTAG_OUTPUTs                  ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_LOAN_IO_INPUTs                ; 0 / 142 ( 0 % )         ;
+; HPS_INTERFACE_LOAN_IO_OUTPUTs               ; 0 / 85 ( 0 % )          ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs      ; 0 / 1 ( 0 % )           ;
+; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs     ; 0 / 5 ( 0 % )           ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs    ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs   ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs         ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs        ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs        ; 0 / 32 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs       ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs         ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs        ; 0 / 8 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs        ; 0 / 12 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs       ; 0 / 18 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs        ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs       ; 0 / 13 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs      ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs   ; 0 / 6 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs  ; 0 / 4 ( 0 % )           ;
+; HPS_INTERFACE_PERIPHERAL_UART_INPUTs        ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs       ; 0 / 10 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_INPUTs         ; 0 / 22 ( 0 % )          ;
+; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs        ; 0 / 34 ( 0 % )          ;
+; HPS_INTERFACE_STM_EVENT_INPUTs              ; 0 / 28 ( 0 % )          ;
+; HPS_INTERFACE_TEST_INPUTs                   ; 0 / 610 ( 0 % )         ;
+; HPS_INTERFACE_TEST_OUTPUTs                  ; 0 / 513 ( 0 % )         ;
+; HPS_INTERFACE_TPIU_TRACE_INPUTs             ; 0 / 2 ( 0 % )           ;
+; HPS_INTERFACE_TPIU_TRACE_OUTPUTs            ; 0 / 33 ( 0 % )          ;
+; Horizontal periphery clocks                 ; 0 / 72 ( 0 % )          ;
+; Local interconnects                         ; 88 / 84,580 ( < 1 % )   ;
+; Quadrant clocks                             ; 0 / 66 ( 0 % )          ;
+; R14 interconnects                           ; 343 / 12,676 ( 3 % )    ;
+; R14/C12 interconnect drivers                ; 384 / 20,720 ( 2 % )    ;
+; R3 interconnects                            ; 371 / 130,992 ( < 1 % ) ;
+; R6 interconnects                            ; 567 / 266,960 ( < 1 % ) ;
+; Spine clocks                                ; 2 / 360 ( < 1 % )       ;
+; Wire stub REs                               ; 0 / 15,858 ( 0 % )      ;
++---------------------------------------------+-------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 28    ;
+; Number of I/O Rules Passed       ; 6     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 22    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                  ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                   ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.  ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                   ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                               ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                  ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                     ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                            ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                        ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.               ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                          ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                      ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                         ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                    ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.           ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                     ; Critical ; No Clamping Diode assignments found.                                     ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                  ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                      ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                              ; Critical ; No open drain assignments found.                                         ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                    ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.      ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                     ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                     ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                         ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.             ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O.          ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000034    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass         ; 55        ; 0            ; 55        ; 0            ; 0            ; 55        ; 55        ; 0            ; 55        ; 55        ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 55           ; 0         ; 55           ; 55           ; 0         ; 0         ; 55           ; 0         ; 0         ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ; 55           ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ;
+; SW[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[0]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[1]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; HEX4[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; DAC_LD             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDI            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SCK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_CS             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; PWM_OUT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; ADC_SDO            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+
+
++------------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                          ;
++------------------------------------------------------------------+-----------------------------+
+; Option                                                           ; Setting                     ;
++------------------------------------------------------------------+-----------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                         ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                         ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                         ;
+; Enable INIT_DONE output                                          ; Off                         ;
+; Configuration scheme                                             ; Passive Serial              ;
+; Enable Error Detection CRC_ERROR pin                             ; Off                         ;
+; Enable CvP_CONFDONE pin                                          ; Off                         ;
+; Enable open drain on CRC_ERROR pin                               ; On                          ;
+; Enable open drain on CvP_CONFDONE pin                            ; On                          ;
+; Enable open drain on INIT_DONE pin                               ; On                          ;
+; Enable open drain on Partial Reconfiguration pins                ; Off                         ;
+; Enable open drain on nCEO pin                                    ; On                          ;
+; Enable Partial Reconfiguration pins                              ; Off                         ;
+; Enable input tri-state on active configuration pins in user mode ; Off                         ;
+; Enable internal scrubbing                                        ; Off                         ;
+; Active Serial clock source                                       ; 100 MHz Internal Oscillator ;
+; Device initialization clock source                               ; Internal Oscillator         ;
+; Configuration via Protocol                                       ; Off                         ;
+; Configuration Voltage Level                                      ; Auto                        ;
+; Force Configuration Voltage Level                                ; Off                         ;
+; Enable nCEO output                                               ; Off                         ;
+; Data[15..8]                                                      ; Unreserved                  ;
+; Data[7..5]                                                       ; Unreserved                  ;
+; Base pin-out file on sameframe device                            ; Off                         ;
++------------------------------------------------------------------+-----------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.10 V ;
+; Low Junction Temperature  ; 0 �C   ;
+; High Junction Temperature ; 85 �C  ;
++---------------------------+--------+
+
+
++---------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                             ;
++----------------------------+--------------------------+-------------------+
+; Source Clock(s)            ; Destination Clock(s)     ; Delay Added in ns ;
++----------------------------+--------------------------+-------------------+
+; spi2adc:SPI_ADC|clk_1MHz   ; CLOCK_50                 ; 551.9             ;
+; spi2adc:SPI_ADC|adc_cs     ; CLOCK_50                 ; 533.5             ;
+; spi2adc:SPI_ADC|adc_cs,I/O ; CLOCK_50                 ; 127.1             ;
+; spi2adc:SPI_ADC|clk_1MHz   ; spi2adc:SPI_ADC|clk_1MHz ; 31.2              ;
+; spi2dac:SPI_DAC|clk_1MHz   ; spi2dac:SPI_DAC|clk_1MHz ; 27.6              ;
++----------------------------+--------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                       ;
++-----------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                       ; Destination Register                                                                                                                    ; Delay Added in ns ;
++-----------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; spi2adc:SPI_ADC|clk_1MHz                                                                                              ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                ; 5.610             ;
+; spi2dac:SPI_DAC|clk_1MHz                                                                                              ; spi2dac:SPI_DAC|clk_1MHz                                                                                                                ; 5.582             ;
+; spi2adc:SPI_ADC|data_from_adc[1]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.536             ;
+; spi2adc:SPI_ADC|data_from_adc[5]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.536             ;
+; spi2adc:SPI_ADC|data_from_adc[7]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.536             ;
+; spi2adc:SPI_ADC|data_from_adc[0]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.535             ;
+; spi2adc:SPI_ADC|data_from_adc[4]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.535             ;
+; spi2adc:SPI_ADC|data_from_adc[6]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.535             ;
+; spi2adc:SPI_ADC|data_from_adc[2]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.534             ;
+; spi2adc:SPI_ADC|data_from_adc[3]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.527             ;
+; spi2adc:SPI_ADC|data_from_adc[8]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 5.038             ;
+; spi2adc:SPI_ADC|adc_cs                                                                                                ; spi2adc:SPI_ADC|adc_start                                                                                                               ; 4.546             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[0]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 4.208             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[1]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 4.177             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[2]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 4.154             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[3]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 4.119             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[4]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.080             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[12] ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.079             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[11] ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.060             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[9]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.056             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[8]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.053             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[6]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.049             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[5]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.049             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[10] ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.029             ;
+; processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated|counter_reg_bit[7]  ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~portb_address_reg0 ; 4.027             ;
+; spi2dac:SPI_DAC|dac_cs                                                                                                ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL                                                                                                  ; 4.012             ;
+; spi2adc:SPI_ADC|data_from_adc[9]                                                                                      ; processor:echo_var_delay|data_out[9]                                                                                                    ; 3.158             ;
+; SW[0]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 2.373             ;
+; SW[1]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 2.227             ;
+; SW[2]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 2.173             ;
+; clktick_16:GEN_10K|tick                                                                                               ; spi2adc:SPI_ADC|adc_start                                                                                                               ; 2.119             ;
+; spi2adc:SPI_ADC|sr_state.IDLE                                                                                         ; spi2adc:SPI_ADC|adc_start                                                                                                               ; 2.119             ;
+; spi2adc:SPI_ADC|sr_state.WAIT_CSB_FALL                                                                                ; spi2adc:SPI_ADC|adc_start                                                                                                               ; 2.119             ;
+; spi2adc:SPI_ADC|adc_start                                                                                             ; spi2adc:SPI_ADC|adc_start                                                                                                               ; 2.119             ;
+; SW[3]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 2.110             ;
+; SW[4]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 2.049             ;
+; SW[5]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 1.998             ;
+; SW[6]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 1.954             ;
+; SW[7]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 1.855             ;
+; SW[8]                                                                                                                 ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a3~porta_address_reg0 ; 1.729             ;
+; spi2adc:SPI_ADC|ctr[0]                                                                                                ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                ; 1.583             ;
+; spi2adc:SPI_ADC|ctr[2]                                                                                                ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                ; 1.581             ;
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[1]        ; processor:echo_var_delay|data_out[9]                                                                                                    ; 1.579             ;
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[2]        ; processor:echo_var_delay|data_out[9]                                                                                                    ; 1.579             ;
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[3]        ; processor:echo_var_delay|data_out[9]                                                                                                    ; 1.579             ;
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[4]        ; processor:echo_var_delay|data_out[9]                                                                                                    ; 1.579             ;
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[5]        ; processor:echo_var_delay|data_out[9]                                                                                                    ; 1.579             ;
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[6]        ; processor:echo_var_delay|data_out[9]                                                                                                    ; 1.579             ;
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[7]        ; processor:echo_var_delay|data_out[9]                                                                                                    ; 1.579             ;
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[8]        ; processor:echo_var_delay|data_out[9]                                                                                                    ; 1.579             ;
+; spi2adc:SPI_ADC|ctr[4]                                                                                                ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                ; 1.579             ;
+; spi2adc:SPI_ADC|ctr[3]                                                                                                ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                ; 1.556             ;
+; spi2adc:SPI_ADC|ctr[1]                                                                                                ; spi2adc:SPI_ADC|clk_1MHz                                                                                                                ; 1.535             ;
+; spi2adc:SPI_ADC|state[2]                                                                                              ; spi2adc:SPI_ADC|shift_ena                                                                                                               ; 0.977             ;
+; spi2adc:SPI_ADC|state[0]                                                                                              ; spi2adc:SPI_ADC|adc_din                                                                                                                 ; 0.966             ;
+; spi2adc:SPI_ADC|state[4]                                                                                              ; spi2adc:SPI_ADC|adc_din                                                                                                                 ; 0.959             ;
+; spi2dac:SPI_DAC|state[2]                                                                                              ; spi2dac:SPI_DAC|dac_ld                                                                                                                  ; 0.954             ;
+; spi2dac:SPI_DAC|shift_reg[12]                                                                                         ; spi2dac:SPI_DAC|shift_reg[13]                                                                                                           ; 0.953             ;
+; spi2dac:SPI_DAC|shift_reg[14]                                                                                         ; spi2dac:SPI_DAC|shift_reg[15]                                                                                                           ; 0.953             ;
+; spi2dac:SPI_DAC|state[1]                                                                                              ; spi2dac:SPI_DAC|dac_ld                                                                                                                  ; 0.949             ;
+; spi2dac:SPI_DAC|shift_reg[13]                                                                                         ; spi2dac:SPI_DAC|shift_reg[14]                                                                                                           ; 0.938             ;
+; spi2dac:SPI_DAC|shift_reg[11]                                                                                         ; spi2dac:SPI_DAC|shift_reg[12]                                                                                                           ; 0.938             ;
+; spi2dac:SPI_DAC|state[4]                                                                                              ; spi2dac:SPI_DAC|dac_ld                                                                                                                  ; 0.936             ;
+; spi2adc:SPI_ADC|shift_reg[0]                                                                                          ; spi2adc:SPI_ADC|shift_reg[1]                                                                                                            ; 0.919             ;
+; spi2dac:SPI_DAC|state[0]                                                                                              ; spi2dac:SPI_DAC|dac_cs                                                                                                                  ; 0.913             ;
+; spi2adc:SPI_ADC|state[3]                                                                                              ; spi2adc:SPI_ADC|shift_ena                                                                                                               ; 0.887             ;
+; spi2dac:SPI_DAC|state[3]                                                                                              ; spi2dac:SPI_DAC|dac_ld                                                                                                                  ; 0.842             ;
+; spi2adc:SPI_ADC|shift_reg[8]                                                                                          ; spi2adc:SPI_ADC|shift_reg[9]                                                                                                            ; 0.778             ;
+; spi2adc:SPI_ADC|shift_reg[2]                                                                                          ; spi2adc:SPI_ADC|shift_reg[3]                                                                                                            ; 0.771             ;
+; spi2adc:SPI_ADC|shift_reg[4]                                                                                          ; spi2adc:SPI_ADC|shift_reg[5]                                                                                                            ; 0.771             ;
+; spi2adc:SPI_ADC|shift_reg[6]                                                                                          ; spi2adc:SPI_ADC|shift_reg[7]                                                                                                            ; 0.771             ;
+; spi2adc:SPI_ADC|shift_reg[1]                                                                                          ; spi2adc:SPI_ADC|shift_reg[2]                                                                                                            ; 0.769             ;
+; spi2adc:SPI_ADC|shift_reg[3]                                                                                          ; spi2adc:SPI_ADC|shift_reg[4]                                                                                                            ; 0.769             ;
+; spi2adc:SPI_ADC|shift_reg[5]                                                                                          ; spi2adc:SPI_ADC|shift_reg[6]                                                                                                            ; 0.769             ;
+; spi2adc:SPI_ADC|shift_reg[7]                                                                                          ; spi2adc:SPI_ADC|shift_reg[8]                                                                                                            ; 0.769             ;
+; spi2adc:SPI_ADC|shift_ena                                                                                             ; spi2adc:SPI_ADC|shift_reg[7]                                                                                                            ; 0.733             ;
+; spi2adc:SPI_ADC|adc_done                                                                                              ; spi2adc:SPI_ADC|data_from_adc[8]                                                                                                        ; 0.649             ;
+; spi2dac:SPI_DAC|shift_reg[2]                                                                                          ; spi2dac:SPI_DAC|shift_reg[3]                                                                                                            ; 0.599             ;
+; spi2dac:SPI_DAC|shift_reg[4]                                                                                          ; spi2dac:SPI_DAC|shift_reg[5]                                                                                                            ; 0.599             ;
+; spi2dac:SPI_DAC|shift_reg[6]                                                                                          ; spi2dac:SPI_DAC|shift_reg[7]                                                                                                            ; 0.599             ;
+; spi2dac:SPI_DAC|shift_reg[8]                                                                                          ; spi2dac:SPI_DAC|shift_reg[9]                                                                                                            ; 0.599             ;
+; spi2dac:SPI_DAC|shift_reg[3]                                                                                          ; spi2dac:SPI_DAC|shift_reg[4]                                                                                                            ; 0.592             ;
+; spi2dac:SPI_DAC|shift_reg[5]                                                                                          ; spi2dac:SPI_DAC|shift_reg[6]                                                                                                            ; 0.592             ;
+; spi2dac:SPI_DAC|shift_reg[7]                                                                                          ; spi2dac:SPI_DAC|shift_reg[8]                                                                                                            ; 0.592             ;
+; spi2dac:SPI_DAC|shift_reg[9]                                                                                          ; spi2dac:SPI_DAC|shift_reg[10]                                                                                                           ; 0.592             ;
+; spi2dac:SPI_DAC|shift_reg[10]                                                                                         ; spi2dac:SPI_DAC|shift_reg[11]                                                                                                           ; 0.592             ;
+; pwm:PWM_DC|d[8]                                                                                                       ; pwm:PWM_DC|pwm_out                                                                                                                      ; 0.421             ;
+; spi2adc:SPI_ADC|state[1]                                                                                              ; spi2adc:SPI_ADC|adc_din                                                                                                                 ; 0.406             ;
+; spi2dac:SPI_DAC|sr_state.WAIT_CSB_HIGH                                                                                ; spi2dac:SPI_DAC|sr_state.IDLE                                                                                                           ; 0.381             ;
+; spi2adc:SPI_ADC|shift_reg[9]                                                                                          ; spi2adc:SPI_ADC|data_from_adc[9]                                                                                                        ; 0.379             ;
+; spi2adc:SPI_ADC|sr_state.WAIT_CSB_HIGH                                                                                ; spi2adc:SPI_ADC|sr_state.IDLE                                                                                                           ; 0.367             ;
+; spi2dac:SPI_DAC|sr_state.IDLE                                                                                         ; spi2dac:SPI_DAC|sr_state.WAIT_CSB_HIGH                                                                                                  ; 0.365             ;
+; pwm:PWM_DC|d[9]                                                                                                       ; pwm:PWM_DC|pwm_out                                                                                                                      ; 0.358             ;
+; spi2dac:SPI_DAC|sr_state.WAIT_CSB_FALL                                                                                ; spi2dac:SPI_DAC|dac_start                                                                                                               ; 0.326             ;
+; pwm:PWM_DC|count[9]                                                                                                   ; pwm:PWM_DC|pwm_out                                                                                                                      ; 0.275             ;
+; pwm:PWM_DC|count[0]                                                                                                   ; pwm:PWM_DC|count[9]                                                                                                                     ; 0.257             ;
+; processor:echo_var_delay|data_out[9]                                                                                  ; pwm:PWM_DC|d[9]                                                                                                                         ; 0.196             ;
+; processor:echo_var_delay|data_out[8]                                                                                  ; pwm:PWM_DC|d[8]                                                                                                                         ; 0.196             ;
+; spi2dac:SPI_DAC|dac_start                                                                                             ; spi2dac:SPI_DAC|shift_reg[11]                                                                                                           ; 0.153             ;
+; pwm:PWM_DC|count[7]                                                                                                   ; pwm:PWM_DC|pwm_out                                                                                                                      ; 0.123             ;
++-----------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device 5CSEMA5F31C6 for design "ex19"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Info (184020): Starting Fitter periphery placement operations
+Info (11191): Automatically promoted 1 clock (1 global)
+    Info (11162): CLOCK_50~inputCLKENA0 with 69 fanout uses global clock CLKCTRL_G6
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
+Info (176233): Starting register packing
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex19.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_CS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DATA" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_DC" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "OLED_RST" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:11
+Info (170189): Fitter placement preparation operations beginning
+Info (14951): The Fitter is using Advanced Physical Optimization.
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X67_Y0 to location X77_Y10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:09
+Info (11888): Total time spent on timing analysis during the Fitter is 0.76 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:04
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file C:/New folder/ex19/output_files/ex19.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 31 warnings
+    Info: Peak virtual memory: 2764 megabytes
+    Info: Processing ended: Tue Dec 06 09:47:12 2016
+    Info: Elapsed time: 00:00:42
+    Info: Total CPU time (on all processors): 00:01:11
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/New folder/ex19/output_files/ex19.fit.smsg.
+
+
diff --git a/part_4/ex19/output_files/ex19.fit.smsg b/part_4/ex19/output_files/ex19.fit.smsg
new file mode 100755
index 0000000..43eead5
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.fit.smsg
@@ -0,0 +1,6 @@
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks
diff --git a/part_4/ex19/output_files/ex19.fit.summary b/part_4/ex19/output_files/ex19.fit.summary
new file mode 100755
index 0000000..408d8b2
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.fit.summary
@@ -0,0 +1,20 @@
+Fitter Status : Successful - Tue Dec 06 09:47:11 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex19
+Top-level Entity Name : ex19
+Family : Cyclone V
+Device : 5CSEMA5F31C6
+Timing Models : Final
+Logic utilization (in ALMs) : 118 / 32,070 ( < 1 % )
+Total registers : 136
+Total pins : 55 / 457 ( 12 % )
+Total virtual pins : 0
+Total block memory bits : 65,536 / 4,065,280 ( 2 % )
+Total RAM Blocks : 8 / 397 ( 2 % )
+Total DSP Blocks : 0 / 87 ( 0 % )
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 4 ( 0 % )
diff --git a/part_4/ex19/output_files/ex19.flow.rpt b/part_4/ex19/output_files/ex19.flow.rpt
new file mode 100755
index 0000000..db4a90e
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.flow.rpt
@@ -0,0 +1,131 @@
+Flow report for ex19
+Tue Dec 06 09:47:26 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++---------------------------------+-------------------------------------------------+
+; Flow Status                     ; Successful - Tue Dec 06 09:47:19 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex19                                            ;
+; Top-level Entity Name           ; ex19                                            ;
+; Family                          ; Cyclone V                                       ;
+; Device                          ; 5CSEMA5F31C6                                    ;
+; Timing Models                   ; Final                                           ;
+; Logic utilization (in ALMs)     ; 118 / 32,070 ( < 1 % )                          ;
+; Total registers                 ; 136                                             ;
+; Total pins                      ; 55 / 457 ( 12 % )                               ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 65,536 / 4,065,280 ( 2 % )                      ;
+; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0 / 6 ( 0 % )                                   ;
+; Total DLLs                      ; 0 / 4 ( 0 % )                                   ;
++---------------------------------+-------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 12/06/2016 09:46:19 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ex19                ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564170200.148101757810172       ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; MISC_FILE                           ; verilog_files/delay_block_bb.v        ; --            ; --          ; --         ;
+; MISC_FILE                           ; verilog_files/ctr_13_bit_bb.v         ; --            ; --          ; --         ;
+; MISC_FILE                           ; mult_by_h666_bb.v                     ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 16764057                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; PROJECT_OUTPUT_DIRECTORY            ; output_files                          ; --            ; --          ; --         ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:11     ; 1.0                     ; 916 MB              ; 00:00:22                           ;
+; Fitter                    ; 00:00:41     ; 1.0                     ; 2764 MB             ; 00:01:10                           ;
+; Assembler                 ; 00:00:06     ; 1.0                     ; 894 MB              ; 00:00:06                           ;
+; TimeQuest Timing Analyzer ; 00:00:06     ; 1.2                     ; 1237 MB             ; 00:00:07                           ;
+; Total                     ; 00:01:04     ; --                      ; --                  ; 00:01:45                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-016     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19
+quartus_fit --read_settings_files=off --write_settings_files=off ex19 -c ex19
+quartus_asm --read_settings_files=off --write_settings_files=off ex19 -c ex19
+quartus_sta ex19 -c ex19
+
+
+
diff --git a/part_4/ex19/output_files/ex19.jdi b/part_4/ex19/output_files/ex19.jdi
new file mode 100755
index 0000000..92a1627
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="181382ee410b6190f908"/>
+  </project>
+  <file_info>
+    <file device="5CSEMA5F31C6" path="ex19.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/part_4/ex19/output_files/ex19.map.rpt b/part_4/ex19/output_files/ex19.map.rpt
new file mode 100755
index 0000000..0a43044
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.map.rpt
@@ -0,0 +1,970 @@
+Analysis & Synthesis report for ex19
+Tue Dec 06 09:46:29 2016
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |ex19|spi2adc:SPI_ADC|sr_state
+ 11. State Machine - |ex19|spi2dac:SPI_DAC|sr_state
+ 12. Registers Removed During Synthesis
+ 13. Removed Registers Triggering Further Register Optimizations
+ 14. General Register Statistics
+ 15. Inverted Register Statistics
+ 16. Source assignments for processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated
+ 17. Parameter Settings for User Entity Instance: clktick_16:GEN_10K
+ 18. Parameter Settings for User Entity Instance: spi2dac:SPI_DAC
+ 19. Parameter Settings for User Entity Instance: spi2adc:SPI_ADC
+ 20. Parameter Settings for User Entity Instance: processor:echo_var_delay
+ 21. Parameter Settings for User Entity Instance: processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component
+ 22. Parameter Settings for User Entity Instance: processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component
+ 23. Parameter Settings for User Entity Instance: processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component
+ 24. altsyncram Parameter Settings by Entity Instance
+ 25. lpm_mult Parameter Settings by Entity Instance
+ 26. Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A31"
+ 27. Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A19"
+ 28. Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A10"
+ 29. Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A4"
+ 30. Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A1"
+ 31. Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd"
+ 32. Port Connectivity Checks: "processor:echo_var_delay|mult_by_h666:mul_by_h666"
+ 33. Port Connectivity Checks: "processor:echo_var_delay|div_by_2:comb_6"
+ 34. Port Connectivity Checks: "processor:echo_var_delay|delay_block:del"
+ 35. Port Connectivity Checks: "spi2adc:SPI_ADC"
+ 36. Port Connectivity Checks: "clktick_16:GEN_10K"
+ 37. Post-Synthesis Netlist Statistics for Top Partition
+ 38. Elapsed Time Per Partition
+ 39. Analysis & Synthesis Messages
+ 40. Analysis & Synthesis Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++---------------------------------+-------------------------------------------------+
+; Analysis & Synthesis Status     ; Successful - Tue Dec 06 09:46:29 2016           ;
+; Quartus Prime Version           ; 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
+; Revision Name                   ; ex19                                            ;
+; Top-level Entity Name           ; ex19                                            ;
+; Family                          ; Cyclone V                                       ;
+; Logic utilization (in ALMs)     ; N/A                                             ;
+; Total registers                 ; 126                                             ;
+; Total pins                      ; 55                                              ;
+; Total virtual pins              ; 0                                               ;
+; Total block memory bits         ; 65,536                                          ;
+; Total DSP Blocks                ; 0                                               ;
+; Total HSSI RX PCSs              ; 0                                               ;
+; Total HSSI PMA RX Deserializers ; 0                                               ;
+; Total HSSI TX PCSs              ; 0                                               ;
+; Total HSSI PMA TX Serializers   ; 0                                               ;
+; Total PLLs                      ; 0                                               ;
+; Total DLLs                      ; 0                                               ;
++---------------------------------+-------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                             ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                          ; Setting            ; Default Value      ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                          ; 5CSEMA5F31C6       ;                    ;
+; Top-level entity name                                                           ; ex19               ; ex19               ;
+; Family name                                                                     ; Cyclone V          ; Cyclone V          ;
+; Use smart compilation                                                           ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation      ; On                 ; On                 ;
+; Enable compact report table                                                     ; Off                ; Off                ;
+; Restructure Multiplexers                                                        ; Auto               ; Auto               ;
+; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off                ; Off                ;
+; Create Debugging Nodes for IP Cores                                             ; Off                ; Off                ;
+; Preserve fewer node names                                                       ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                       ; Off                ; Off                ;
+; Verilog Version                                                                 ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                                    ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                        ; Auto               ; Auto               ;
+; Safe State Machine                                                              ; Off                ; Off                ;
+; Extract Verilog State Machines                                                  ; On                 ; On                 ;
+; Extract VHDL State Machines                                                     ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                               ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                      ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                                  ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                         ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                       ; On                 ; On                 ;
+; Parallel Synthesis                                                              ; On                 ; On                 ;
+; DSP Block Balancing                                                             ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                              ; On                 ; On                 ;
+; Power-Up Don't Care                                                             ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                                    ; Off                ; Off                ;
+; Remove Duplicate Registers                                                      ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                            ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                          ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                           ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                       ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                            ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                             ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                                  ; Off                ; Off                ;
+; Optimization Technique                                                          ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                              ; 70                 ; 70                 ;
+; Auto Carry Chains                                                               ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                            ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                           ; Off                ; Off                ;
+; Auto ROM Replacement                                                            ; On                 ; On                 ;
+; Auto RAM Replacement                                                            ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                      ; On                 ; On                 ;
+; Auto Shift Register Replacement                                                 ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                                 ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                                   ; On                 ; On                 ;
+; Strict RAM Replacement                                                          ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                               ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                           ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                              ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                                   ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                             ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                               ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                         ; On                 ; On                 ;
+; Report Parameter Settings                                                       ; On                 ; On                 ;
+; Report Source Assignments                                                       ; On                 ; On                 ;
+; Report Connectivity Checks                                                      ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                              ; Off                ; Off                ;
+; Synchronization Register Chain Length                                           ; 3                  ; 3                  ;
+; PowerPlay Power Optimization During Synthesis                                   ; Normal compilation ; Normal compilation ;
+; HDL message level                                                               ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                                 ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                        ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                              ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                       ; 100                ; 100                ;
+; Clock MUX Protection                                                            ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                     ; Off                ; Off                ;
+; Block Design Naming                                                             ; Auto               ; Auto               ;
+; SDC constraint protection                                                       ; Off                ; Off                ;
+; Synthesis Effort                                                                ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal                    ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                            ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                              ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                     ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                          ; On                 ; On                 ;
+; Synthesis Seed                                                                  ; 1                  ; 1                  ;
+; Automatic Parallel Synthesis                                                    ; On                 ; On                 ;
+; Partial Reconfiguration Bitstream ID                                            ; Off                ; Off                ;
++---------------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   0.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                               ;
++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                           ; Library ;
++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------+---------+
+; verilog_files/variable_echo.v    ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/variable_echo.v                       ;         ;
+; verilog_files/spi2dac.v          ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/spi2dac.v                             ;         ;
+; verilog_files/spi2adc.v          ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/spi2adc.v                             ;         ;
+; verilog_files/pwm.v              ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/pwm.v                                 ;         ;
+; verilog_files/hex_to_7seg.v      ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/hex_to_7seg.v                         ;         ;
+; verilog_files/div_by_2.v         ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/div_by_2.v                            ;         ;
+; verilog_files/clktick_16.v       ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/clktick_16.v                          ;         ;
+; verilog_files/bin2bcd_16.v       ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/bin2bcd_16.v                          ;         ;
+; verilog_files/add3_ge5.v         ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/verilog_files/add3_ge5.v                            ;         ;
+; ex19.v                           ; yes             ; User Verilog HDL File        ; C:/New folder/ex19/ex19.v                                              ;         ;
+; verilog_files/delay_block.v      ; yes             ; User Wizard-Generated File   ; C:/New folder/ex19/verilog_files/delay_block.v                         ;         ;
+; verilog_files/ctr_13_bit.v       ; yes             ; User Wizard-Generated File   ; C:/New folder/ex19/verilog_files/ctr_13_bit.v                          ;         ;
+; mult_by_h666.v                   ; yes             ; User Wizard-Generated File   ; C:/New folder/ex19/mult_by_h666.v                                      ;         ;
+; lpm_counter.tdf                  ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_counter.tdf         ;         ;
+; lpm_constant.inc                 ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_constant.inc        ;         ;
+; lpm_decode.inc                   ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_decode.inc          ;         ;
+; lpm_add_sub.inc                  ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.inc         ;         ;
+; cmpconst.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/cmpconst.inc            ;         ;
+; lpm_compare.inc                  ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_compare.inc         ;         ;
+; lpm_counter.inc                  ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_counter.inc         ;         ;
+; dffeea.inc                       ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/dffeea.inc              ;         ;
+; alt_counter_stratix.inc          ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/alt_counter_stratix.inc ;         ;
+; aglobal160.inc                   ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc          ;         ;
+; db/cntr_cjh.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex19/db/cntr_cjh.tdf                                     ;         ;
+; altsyncram.tdf                   ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf          ;         ;
+; stratix_ram_block.inc            ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/stratix_ram_block.inc   ;         ;
+; lpm_mux.inc                      ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_mux.inc             ;         ;
+; a_rdenreg.inc                    ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/a_rdenreg.inc           ;         ;
+; altrom.inc                       ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/altrom.inc              ;         ;
+; altram.inc                       ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/altram.inc              ;         ;
+; altdpram.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/altdpram.inc            ;         ;
+; db/altsyncram_nm22.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex19/db/altsyncram_nm22.tdf                              ;         ;
+; lpm_mult.tdf                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf            ;         ;
+; multcore.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/multcore.inc            ;         ;
+; bypassff.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/bypassff.inc            ;         ;
+; altshift.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/altshift.inc            ;         ;
+; multcore.tdf                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf            ;         ;
+; csa_add.inc                      ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/csa_add.inc             ;         ;
+; mpar_add.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.inc            ;         ;
+; muleabz.inc                      ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/muleabz.inc             ;         ;
+; mul_lfrg.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/mul_lfrg.inc            ;         ;
+; mul_boothc.inc                   ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/mul_boothc.inc          ;         ;
+; alt_ded_mult.inc                 ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult.inc        ;         ;
+; alt_ded_mult_y.inc               ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult_y.inc      ;         ;
+; dffpipe.inc                      ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/dffpipe.inc             ;         ;
+; mpar_add.tdf                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf            ;         ;
+; lpm_add_sub.tdf                  ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;         ;
+; addcore.inc                      ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/addcore.inc             ;         ;
+; look_add.inc                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/look_add.inc            ;         ;
+; alt_stratix_add_sub.inc          ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;         ;
+; db/add_sub_a9h.tdf               ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex19/db/add_sub_a9h.tdf                                  ;         ;
+; db/add_sub_e9h.tdf               ; yes             ; Auto-Generated Megafunction  ; C:/New folder/ex19/db/add_sub_e9h.tdf                                  ;         ;
+; altshift.tdf                     ; yes             ; Megafunction                 ; c:/altera/16.0/quartus/libraries/megafunctions/altshift.tdf            ;         ;
++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimate of Logic utilization (ALMs needed) ; 119            ;
+;                                             ;                ;
+; Combinational ALUT usage for logic          ; 209            ;
+;     -- 7 input functions                    ; 0              ;
+;     -- 6 input functions                    ; 14             ;
+;     -- 5 input functions                    ; 22             ;
+;     -- 4 input functions                    ; 76             ;
+;     -- <=3 input functions                  ; 97             ;
+;                                             ;                ;
+; Dedicated logic registers                   ; 126            ;
+;                                             ;                ;
+; I/O pins                                    ; 55             ;
+; Total MLAB memory bits                      ; 0              ;
+; Total block memory bits                     ; 65536          ;
+;                                             ;                ;
+; Total DSP Blocks                            ; 0              ;
+;                                             ;                ;
+; Maximum fan-out node                        ; CLOCK_50~input ;
+; Maximum fan-out                             ; 71             ;
+; Total fan-out                               ; 1345           ;
+; Average fan-out                             ; 2.97           ;
++---------------------------------------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                           ;
++------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; Compilation Hierarchy Node                           ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                         ; Entity Name     ; Library Name ;
++------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+; |ex19                                                ; 209 (0)           ; 126 (0)      ; 65536             ; 0          ; 55   ; 0            ; |ex19                                                                                                                                                                                       ; ex19            ; work         ;
+;    |clktick_16:GEN_10K|                              ; 20 (20)           ; 17 (17)      ; 0                 ; 0          ; 0    ; 0            ; |ex19|clktick_16:GEN_10K                                                                                                                                                                    ; clktick_16      ; work         ;
+;    |processor:echo_var_delay|                        ; 132 (20)          ; 23 (10)      ; 65536             ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay                                                                                                                                                              ; processor       ; work         ;
+;       |bin2bcd_16:bcd|                               ; 39 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd                                                                                                                                               ; bin2bcd_16      ; work         ;
+;          |add3_ge5:A12|                              ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A12                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A15|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A15                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A18|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A18                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A21|                              ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A21                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A22|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A22                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A25|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A25                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A26|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A26                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A29|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A29                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A30|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A30                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A33|                              ; 1 (1)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A33                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A34|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A34                                                                                                                                  ; add3_ge5        ; work         ;
+;          |add3_ge5:A35|                              ; 4 (4)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A35                                                                                                                                  ; add3_ge5        ; work         ;
+;       |ctr_13_bit:ctr|                               ; 13 (0)            ; 13 (0)       ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|ctr_13_bit:ctr                                                                                                                                               ; ctr_13_bit      ; work         ;
+;          |lpm_counter:LPM_COUNTER_component|         ; 13 (0)            ; 13 (0)       ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component                                                                                                             ; lpm_counter     ; work         ;
+;             |cntr_cjh:auto_generated|                ; 13 (13)           ; 13 (13)      ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated                                                                                     ; cntr_cjh        ; work         ;
+;       |delay_block:del|                              ; 0 (0)             ; 0 (0)        ; 65536             ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|delay_block:del                                                                                                                                              ; delay_block     ; work         ;
+;          |altsyncram:altsyncram_component|           ; 0 (0)             ; 0 (0)        ; 65536             ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component                                                                                                              ; altsyncram      ; work         ;
+;             |altsyncram_nm22:auto_generated|         ; 0 (0)             ; 0 (0)        ; 65536             ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated                                                                               ; altsyncram_nm22 ; work         ;
+;       |hex_to_7seg:h0|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|hex_to_7seg:h0                                                                                                                                               ; hex_to_7seg     ; work         ;
+;       |hex_to_7seg:h1|                               ; 7 (7)             ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|hex_to_7seg:h1                                                                                                                                               ; hex_to_7seg     ; work         ;
+;       |hex_to_7seg:h2|                               ; 13 (13)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|hex_to_7seg:h2                                                                                                                                               ; hex_to_7seg     ; work         ;
+;       |mult_by_h666:mul_by_h666|                     ; 33 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666                                                                                                                                     ; mult_by_h666    ; work         ;
+;          |lpm_mult:lpm_mult_component|               ; 33 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component                                                                                                         ; lpm_mult        ; work         ;
+;             |multcore:mult_core|                     ; 33 (7)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core                                                                                      ; multcore        ; work         ;
+;                |mpar_add:padder|                     ; 26 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder                                                                      ; mpar_add        ; work         ;
+;                   |lpm_add_sub:adder[0]|             ; 15 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; lpm_add_sub     ; work         ;
+;                      |add_sub_a9h:auto_generated|    ; 15 (15)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated                      ; add_sub_a9h     ; work         ;
+;                   |mpar_add:sub_par_add|             ; 11 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; mpar_add        ; work         ;
+;                      |lpm_add_sub:adder[0]|          ; 11 (0)            ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; lpm_add_sub     ; work         ;
+;                         |add_sub_e9h:auto_generated| ; 11 (11)           ; 0 (0)        ; 0                 ; 0          ; 0    ; 0            ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated ; add_sub_e9h     ; work         ;
+;    |pwm:PWM_DC|                                      ; 16 (16)           ; 21 (21)      ; 0                 ; 0          ; 0    ; 0            ; |ex19|pwm:PWM_DC                                                                                                                                                                            ; pwm             ; work         ;
+;    |spi2adc:SPI_ADC|                                 ; 21 (21)           ; 39 (39)      ; 0                 ; 0          ; 0    ; 0            ; |ex19|spi2adc:SPI_ADC                                                                                                                                                                       ; spi2adc         ; work         ;
+;    |spi2dac:SPI_DAC|                                 ; 20 (20)           ; 26 (26)      ; 0                 ; 0          ; 0    ; 0            ; |ex19|spi2dac:SPI_DAC                                                                                                                                                                       ; spi2dac         ; work         ;
++------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                              ;
++--------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; Name                                                                                                               ; Type       ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
++--------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ALTSYNCRAM ; M10K block ; Simple Dual Port ; 8192         ; 9            ; 8192         ; 9            ; 73728 ; None ;
++--------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+-------+------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                                 ;
++--------+--------------+---------+--------------+--------------+---------------------------------------------------------+-----------------------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                         ; IP Include File             ;
++--------+--------------+---------+--------------+--------------+---------------------------------------------------------+-----------------------------+
+; Altera ; LPM_COUNTER  ; 16.0    ; N/A          ; N/A          ; |ex19|processor:echo_var_delay|ctr_13_bit:ctr           ; verilog_files/ctr_13_bit.v  ;
+; Altera ; RAM: 2-PORT  ; 16.0    ; N/A          ; N/A          ; |ex19|processor:echo_var_delay|delay_block:del          ; verilog_files/delay_block.v ;
+; Altera ; LPM_MULT     ; 16.0    ; N/A          ; N/A          ; |ex19|processor:echo_var_delay|mult_by_h666:mul_by_h666 ; mult_by_h666.v              ;
++--------+--------------+---------+--------------+--------------+---------------------------------------------------------+-----------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex19|spi2adc:SPI_ADC|sr_state                                           ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------+
+; State Machine - |ex19|spi2dac:SPI_DAC|sr_state                                           ;
++------------------------+---------------+------------------------+------------------------+
+; Name                   ; sr_state.IDLE ; sr_state.WAIT_CSB_HIGH ; sr_state.WAIT_CSB_FALL ;
++------------------------+---------------+------------------------+------------------------+
+; sr_state.IDLE          ; 0             ; 0                      ; 0                      ;
+; sr_state.WAIT_CSB_FALL ; 1             ; 0                      ; 1                      ;
+; sr_state.WAIT_CSB_HIGH ; 1             ; 1                      ; 0                      ;
++------------------------+---------------+------------------------+------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                             ;
++---------------------------------------+----------------------------------------+
+; Register name                         ; Reason for Removal                     ;
++---------------------------------------+----------------------------------------+
+; spi2dac:SPI_DAC|shift_reg[0,1]        ; Stuck at GND due to stuck port data_in ;
+; spi2dac:SPI_DAC|ctr[4]                ; Merged with spi2adc:SPI_ADC|ctr[4]     ;
+; spi2dac:SPI_DAC|ctr[3]                ; Merged with spi2adc:SPI_ADC|ctr[3]     ;
+; spi2dac:SPI_DAC|ctr[2]                ; Merged with spi2adc:SPI_ADC|ctr[2]     ;
+; spi2dac:SPI_DAC|ctr[1]                ; Merged with spi2adc:SPI_ADC|ctr[1]     ;
+; spi2dac:SPI_DAC|ctr[0]                ; Merged with spi2adc:SPI_ADC|ctr[0]     ;
+; Total Number of Removed Registers = 7 ;                                        ;
++---------------------------------------+----------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                       ;
++------------------------------+---------------------------+----------------------------------------+
+; Register name                ; Reason for Removal        ; Registers Removed due to This Register ;
++------------------------------+---------------------------+----------------------------------------+
+; spi2dac:SPI_DAC|shift_reg[0] ; Stuck at GND              ; spi2dac:SPI_DAC|shift_reg[1]           ;
+;                              ; due to stuck port data_in ;                                        ;
++------------------------------+---------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 126   ;
+; Number of registers using Synchronous Clear  ; 9     ;
+; Number of registers using Synchronous Load   ; 9     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 49    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------+
+; Inverted Register Statistics                     ;
++----------------------------------------+---------+
+; Inverted Register                      ; Fan out ;
++----------------------------------------+---------+
+; spi2dac:SPI_DAC|dac_cs                 ; 12      ;
+; spi2adc:SPI_ADC|adc_cs                 ; 37      ;
+; Total number of inverted registers = 2 ;         ;
++----------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated ;
++---------------------------------+--------------------+------+------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                               ;
++---------------------------------+--------------------+------+------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                ;
++---------------------------------+--------------------+------+------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: clktick_16:GEN_10K ;
++----------------+-------+----------------------------------------+
+; Parameter Name ; Value ; Type                                   ;
++----------------+-------+----------------------------------------+
+; N_BIT          ; 16    ; Signed Integer                         ;
++----------------+-------+----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2dac:SPI_DAC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; BUF            ; 1     ; Unsigned Binary                     ;
+; GA_N           ; 1     ; Unsigned Binary                     ;
+; SHDN_N         ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: spi2adc:SPI_ADC ;
++----------------+-------+-------------------------------------+
+; Parameter Name ; Value ; Type                                ;
++----------------+-------+-------------------------------------+
+; SGL            ; 1     ; Unsigned Binary                     ;
+; MSBF           ; 1     ; Unsigned Binary                     ;
+; TIME_CONSTANT  ; 11000 ; Unsigned Binary                     ;
+; IDLE           ; 00    ; Unsigned Binary                     ;
+; WAIT_CSB_FALL  ; 01    ; Unsigned Binary                     ;
+; WAIT_CSB_HIGH  ; 10    ; Unsigned Binary                     ;
++----------------+-------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:echo_var_delay ;
++----------------+------------+-----------------------------------------+
+; Parameter Name ; Value      ; Type                                    ;
++----------------+------------+-----------------------------------------+
+; ADC_OFFSET     ; 0110000001 ; Unsigned Binary                         ;
+; DAC_OFFSET     ; 1000000000 ; Unsigned Binary                         ;
++----------------+------------+-----------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component ;
++------------------------+-------------+---------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                            ;
++------------------------+-------------+---------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                      ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                    ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                    ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                  ;
+; LPM_WIDTH              ; 13          ; Signed Integer                                                                  ;
+; LPM_DIRECTION          ; UP          ; Untyped                                                                         ;
+; LPM_MODULUS            ; 0           ; Untyped                                                                         ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                         ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                         ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                         ;
+; DEVICE_FAMILY          ; Cyclone V   ; Untyped                                                                         ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                         ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                              ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                              ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                                         ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                                         ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                         ;
+; CBXI_PARAMETER         ; cntr_cjh    ; Untyped                                                                         ;
++------------------------+-------------+---------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component ;
++------------------------------------+----------------------+-----------------------------------------------------------+
+; Parameter Name                     ; Value                ; Type                                                      ;
++------------------------------------+----------------------+-----------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                   ;
+; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                ;
+; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                              ;
+; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                              ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                            ;
+; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                   ;
+; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                   ;
+; WIDTH_A                            ; 9                    ; Signed Integer                                            ;
+; WIDTHAD_A                          ; 13                   ; Signed Integer                                            ;
+; NUMWORDS_A                         ; 8192                 ; Signed Integer                                            ;
+; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                   ;
+; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                   ;
+; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                   ;
+; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                   ;
+; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                   ;
+; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                   ;
+; WIDTH_B                            ; 9                    ; Signed Integer                                            ;
+; WIDTHAD_B                          ; 13                   ; Signed Integer                                            ;
+; NUMWORDS_B                         ; 8192                 ; Signed Integer                                            ;
+; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                   ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                   ;
+; RDCONTROL_REG_B                    ; CLOCK0               ; Untyped                                                   ;
+; ADDRESS_REG_B                      ; CLOCK0               ; Untyped                                                   ;
+; OUTDATA_REG_B                      ; CLOCK0               ; Untyped                                                   ;
+; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                   ;
+; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                   ;
+; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                   ;
+; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                   ;
+; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                   ;
+; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                   ;
+; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                   ;
+; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                                            ;
+; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                   ;
+; RAM_BLOCK_TYPE                     ; M10K                 ; Untyped                                                   ;
+; BYTE_SIZE                          ; 8                    ; Untyped                                                   ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                   ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                   ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                   ;
+; INIT_FILE                          ; UNUSED               ; Untyped                                                   ;
+; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                   ;
+; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                   ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                                                   ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS               ; Untyped                                                   ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                   ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS               ; Untyped                                                   ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                   ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                   ;
+; ENABLE_ECC                         ; FALSE                ; Untyped                                                   ;
+; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                                                   ;
+; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                                                   ;
+; DEVICE_FAMILY                      ; Cyclone V            ; Untyped                                                   ;
+; CBXI_PARAMETER                     ; altsyncram_nm22      ; Untyped                                                   ;
++------------------------------------+----------------------+-----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component ;
++------------------------------------------------+-----------+---------------------------------------------------------------+
+; Parameter Name                                 ; Value     ; Type                                                          ;
++------------------------------------------------+-----------+---------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON        ; AUTO_CARRY                                                    ;
+; IGNORE_CARRY_BUFFERS                           ; OFF       ; IGNORE_CARRY                                                  ;
+; AUTO_CASCADE_CHAINS                            ; ON        ; AUTO_CASCADE                                                  ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF       ; IGNORE_CASCADE                                                ;
+; LPM_WIDTHA                                     ; 9         ; Signed Integer                                                ;
+; LPM_WIDTHB                                     ; 11        ; Signed Integer                                                ;
+; LPM_WIDTHP                                     ; 20        ; Signed Integer                                                ;
+; LPM_WIDTHR                                     ; 0         ; Untyped                                                       ;
+; LPM_WIDTHS                                     ; 1         ; Untyped                                                       ;
+; LPM_REPRESENTATION                             ; UNSIGNED  ; Untyped                                                       ;
+; LPM_PIPELINE                                   ; 0         ; Untyped                                                       ;
+; LATENCY                                        ; 0         ; Untyped                                                       ;
+; INPUT_A_IS_CONSTANT                            ; NO        ; Untyped                                                       ;
+; INPUT_B_IS_CONSTANT                            ; YES       ; Untyped                                                       ;
+; USE_EAB                                        ; OFF       ; Untyped                                                       ;
+; MAXIMIZE_SPEED                                 ; 5         ; Untyped                                                       ;
+; DEVICE_FAMILY                                  ; Cyclone V ; Untyped                                                       ;
+; CARRY_CHAIN                                    ; MANUAL    ; Untyped                                                       ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT       ; TECH_MAPPER_APEX20K                                           ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO      ; Untyped                                                       ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0         ; Untyped                                                       ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0         ; Untyped                                                       ;
+; CBXI_PARAMETER                                 ; NOTHING   ; Untyped                                                       ;
+; INPUT_A_FIXED_VALUE                            ; Bx        ; Untyped                                                       ;
+; INPUT_B_FIXED_VALUE                            ; Bx        ; Untyped                                                       ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF       ; Untyped                                                       ;
++------------------------------------------------+-----------+---------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance                                                                     ;
++-------------------------------------------+--------------------------------------------------------------------------+
+; Name                                      ; Value                                                                    ;
++-------------------------------------------+--------------------------------------------------------------------------+
+; Number of entity instances                ; 1                                                                        ;
+; Entity Instance                           ; processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component ;
+;     -- OPERATION_MODE                     ; DUAL_PORT                                                                ;
+;     -- WIDTH_A                            ; 9                                                                        ;
+;     -- NUMWORDS_A                         ; 8192                                                                     ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                             ;
+;     -- WIDTH_B                            ; 9                                                                        ;
+;     -- NUMWORDS_B                         ; 8192                                                                     ;
+;     -- ADDRESS_REG_B                      ; CLOCK0                                                                   ;
+;     -- OUTDATA_REG_B                      ; CLOCK0                                                                   ;
+;     -- RAM_BLOCK_TYPE                     ; M10K                                                                     ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                ;
++-------------------------------------------+--------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                                                        ;
++---------------------------------------+-------------------------------------------------------------------------------+
+; Name                                  ; Value                                                                         ;
++---------------------------------------+-------------------------------------------------------------------------------+
+; Number of entity instances            ; 1                                                                             ;
+; Entity Instance                       ; processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component ;
+;     -- LPM_WIDTHA                     ; 9                                                                             ;
+;     -- LPM_WIDTHB                     ; 11                                                                            ;
+;     -- LPM_WIDTHP                     ; 20                                                                            ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                      ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                            ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                           ;
+;     -- USE_EAB                        ; OFF                                                                           ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                          ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                            ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                            ;
++---------------------------------------+-------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A31"                               ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; w[3] ; Input  ; Info     ; Stuck at GND                                                                        ;
+; a[3] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A19" ;
++------+-------+----------+--------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                ;
++------+-------+----------+--------------------------------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                                           ;
++------+-------+----------+--------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A10" ;
++------+-------+----------+--------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                ;
++------+-------+----------+--------------------------------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                                           ;
++------+-------+----------+--------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A4" ;
++------+-------+----------+-------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                               ;
++------+-------+----------+-------------------------------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                                          ;
++------+-------+----------+-------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A1" ;
++------+-------+----------+-------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                               ;
++------+-------+----------+-------------------------------------------------------+
+; w[3] ; Input ; Info     ; Stuck at GND                                          ;
++------+-------+----------+-------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|bin2bcd_16:bcd"                                                                                                     ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                                                                                                       ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; B    ; Input ; Warning  ; Input port expression (10 bits) is smaller than the input port (16 bits) it drives.  Extra input bit(s) "B[15..10]" will be connected to GND. ;
++------+-------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|mult_by_h666:mul_by_h666"                                                                                                                                        ;
++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                                                                                           ;
++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; dataa        ; Input  ; Warning  ; Input port expression (10 bits) is wider than the input port (9 bits) it drives.  The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; result[9..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                               ;
++--------------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|div_by_2:comb_6"                                                                                                                                         ;
++------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type  ; Severity ; Details                                                                                                                                                                            ;
++------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; in   ; Input ; Warning  ; Input port expression (11 bits) is wider than the input port (10 bits) it drives.  The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
++------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "processor:echo_var_delay|delay_block:del"                                                                                                                                         ;
++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                                                                                                                           ;
++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; data ; Input  ; Warning  ; Input port expression (10 bits) is wider than the input port (9 bits) it drives.  The 1 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; q    ; Output ; Warning  ; Output or bidir port (9 bits) is smaller than the port expression (10 bits) it drives.  The 1 most-significant bit(s) in the port expression will be connected to GND.            ;
++------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------+
+; Port Connectivity Checks: "spi2adc:SPI_ADC" ;
++---------+-------+----------+----------------+
+; Port    ; Type  ; Severity ; Details        ;
++---------+-------+----------+----------------+
+; channel ; Input ; Info     ; Stuck at VCC   ;
++---------+-------+----------+----------------+
+
+
++------------------------------------------------+
+; Port Connectivity Checks: "clktick_16:GEN_10K" ;
++-----------+-------+----------+-----------------+
+; Port      ; Type  ; Severity ; Details         ;
++-----------+-------+----------+-----------------+
+; N[9..7]   ; Input ; Info     ; Stuck at VCC    ;
+; N[2..0]   ; Input ; Info     ; Stuck at VCC    ;
+; N[15..13] ; Input ; Info     ; Stuck at GND    ;
+; N[11..10] ; Input ; Info     ; Stuck at GND    ;
+; N[6..3]   ; Input ; Info     ; Stuck at GND    ;
+; N[12]     ; Input ; Info     ; Stuck at VCC    ;
++-----------+-------+----------+-----------------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-----------------------+-----------------------------+
+; Type                  ; Count                       ;
++-----------------------+-----------------------------+
+; arriav_ff             ; 126                         ;
+;     ENA               ; 40                          ;
+;     ENA SCLR          ; 9                           ;
+;     SLD               ; 9                           ;
+;     plain             ; 68                          ;
+; arriav_lcell_comb     ; 223                         ;
+;     arith             ; 73                          ;
+;         0 data inputs ; 2                           ;
+;         1 data inputs ; 41                          ;
+;         2 data inputs ; 16                          ;
+;         3 data inputs ; 1                           ;
+;         4 data inputs ; 5                           ;
+;         5 data inputs ; 8                           ;
+;     normal            ; 140                         ;
+;         0 data inputs ; 2                           ;
+;         1 data inputs ; 16                          ;
+;         2 data inputs ; 12                          ;
+;         3 data inputs ; 11                          ;
+;         4 data inputs ; 71                          ;
+;         5 data inputs ; 14                          ;
+;         6 data inputs ; 14                          ;
+;     shared            ; 10                          ;
+;         1 data inputs ; 2                           ;
+;         2 data inputs ; 8                           ;
+; boundary_port         ; 55                          ;
+; stratixv_ram_block    ; 8                           ;
+;                       ;                             ;
+; Max LUT depth         ; 13.30                       ;
+; Average LUT depth     ; 4.86                        ;
++-----------------------+-----------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+    Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+    Info: Processing started: Tue Dec 06 09:46:18 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/variable_echo.v
+    Info (12023): Found entity 1: processor File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v
+    Info (12023): Found entity 1: spi2dac File: C:/New folder/ex19/verilog_files/spi2dac.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v
+    Info (12023): Found entity 1: spi2adc File: C:/New folder/ex19/verilog_files/spi2adc.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/pwm.v
+    Info (12023): Found entity 1: pwm File: C:/New folder/ex19/verilog_files/pwm.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v
+    Info (12023): Found entity 1: pulse_gen File: C:/New folder/ex19/verilog_files/pulse_gen.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v
+    Info (12023): Found entity 1: multiply_k File: C:/New folder/ex19/verilog_files/multiply_k.v Line: 39
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v
+    Info (12023): Found entity 1: hex_to_7seg File: C:/New folder/ex19/verilog_files/hex_to_7seg.v Line: 10
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v
+    Info (12023): Found entity 1: div_by_2 File: C:/New folder/ex19/verilog_files/div_by_2.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v
+    Info (12023): Found entity 1: delay_ram File: C:/New folder/ex19/verilog_files/delay_ram.v Line: 39
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v
+    Info (12023): Found entity 1: d_ff File: C:/New folder/ex19/verilog_files/d_ff.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v
+    Info (12023): Found entity 1: clktick_16 File: C:/New folder/ex19/verilog_files/clktick_16.v Line: 6
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v
+    Info (12023): Found entity 1: bin2bcd_16 File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 12
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v
+    Info (12023): Found entity 1: add3_ge5 File: C:/New folder/ex19/verilog_files/add3_ge5.v Line: 9
+Info (12021): Found 1 design units, including 1 entities, in source file ex19.v
+    Info (12023): Found entity 1: ex19 File: C:/New folder/ex19/ex19.v Line: 1
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/delay_block.v
+    Info (12023): Found entity 1: delay_block File: C:/New folder/ex19/verilog_files/delay_block.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file verilog_files/ctr_13_bit.v
+    Info (12023): Found entity 1: ctr_13_bit File: C:/New folder/ex19/verilog_files/ctr_13_bit.v Line: 40
+Info (12021): Found 1 design units, including 1 entities, in source file mult_by_h666.v
+    Info (12023): Found entity 1: mult_by_h666 File: C:/New folder/ex19/mult_by_h666.v Line: 40
+Critical Warning (10846): Verilog HDL Instantiation warning at variable_echo.v(32): instance has no name File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 32
+Info (12127): Elaborating entity "ex19" for the top level hierarchy
+Info (12128): Elaborating entity "clktick_16" for hierarchy "clktick_16:GEN_10K" File: C:/New folder/ex19/ex19.v Line: 24
+Info (12128): Elaborating entity "spi2dac" for hierarchy "spi2dac:SPI_DAC" File: C:/New folder/ex19/ex19.v Line: 26
+Info (12128): Elaborating entity "pwm" for hierarchy "pwm:PWM_DC" File: C:/New folder/ex19/ex19.v Line: 27
+Info (12128): Elaborating entity "spi2adc" for hierarchy "spi2adc:SPI_ADC" File: C:/New folder/ex19/ex19.v Line: 38
+Info (12128): Elaborating entity "processor" for hierarchy "processor:echo_var_delay" File: C:/New folder/ex19/ex19.v Line: 40
+Info (12128): Elaborating entity "ctr_13_bit" for hierarchy "processor:echo_var_delay|ctr_13_bit:ctr" File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 28
+Info (12128): Elaborating entity "lpm_counter" for hierarchy "processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component" File: C:/New folder/ex19/verilog_files/ctr_13_bit.v Line: 65
+Info (12130): Elaborated megafunction instantiation "processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component" File: C:/New folder/ex19/verilog_files/ctr_13_bit.v Line: 65
+Info (12133): Instantiated megafunction "processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component" with the following parameter: File: C:/New folder/ex19/verilog_files/ctr_13_bit.v Line: 65
+    Info (12134): Parameter "lpm_direction" = "UP"
+    Info (12134): Parameter "lpm_port_updown" = "PORT_UNUSED"
+    Info (12134): Parameter "lpm_type" = "LPM_COUNTER"
+    Info (12134): Parameter "lpm_width" = "13"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cjh.tdf
+    Info (12023): Found entity 1: cntr_cjh File: C:/New folder/ex19/db/cntr_cjh.tdf Line: 26
+Info (12128): Elaborating entity "cntr_cjh" for hierarchy "processor:echo_var_delay|ctr_13_bit:ctr|lpm_counter:LPM_COUNTER_component|cntr_cjh:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_counter.tdf Line: 259
+Info (12128): Elaborating entity "delay_block" for hierarchy "processor:echo_var_delay|delay_block:del" File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 30
+Info (12128): Elaborating entity "altsyncram" for hierarchy "processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component" File: C:/New folder/ex19/verilog_files/delay_block.v Line: 92
+Info (12130): Elaborated megafunction instantiation "processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component" File: C:/New folder/ex19/verilog_files/delay_block.v Line: 92
+Info (12133): Instantiated megafunction "processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component" with the following parameter: File: C:/New folder/ex19/verilog_files/delay_block.v Line: 92
+    Info (12134): Parameter "address_aclr_b" = "NONE"
+    Info (12134): Parameter "address_reg_b" = "CLOCK0"
+    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
+    Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
+    Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
+    Info (12134): Parameter "intended_device_family" = "Cyclone V"
+    Info (12134): Parameter "lpm_type" = "altsyncram"
+    Info (12134): Parameter "numwords_a" = "8192"
+    Info (12134): Parameter "numwords_b" = "8192"
+    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
+    Info (12134): Parameter "outdata_aclr_b" = "NONE"
+    Info (12134): Parameter "outdata_reg_b" = "CLOCK0"
+    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
+    Info (12134): Parameter "ram_block_type" = "M10K"
+    Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0"
+    Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE"
+    Info (12134): Parameter "widthad_a" = "13"
+    Info (12134): Parameter "widthad_b" = "13"
+    Info (12134): Parameter "width_a" = "9"
+    Info (12134): Parameter "width_b" = "9"
+    Info (12134): Parameter "width_byteena_a" = "1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nm22.tdf
+    Info (12023): Found entity 1: altsyncram_nm22 File: C:/New folder/ex19/db/altsyncram_nm22.tdf Line: 28
+Info (12128): Elaborating entity "altsyncram_nm22" for hierarchy "processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf Line: 792
+Info (12128): Elaborating entity "div_by_2" for hierarchy "processor:echo_var_delay|div_by_2:comb_6" File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 32
+Info (12128): Elaborating entity "mult_by_h666" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666" File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 34
+Info (12128): Elaborating entity "lpm_mult" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" File: C:/New folder/ex19/mult_by_h666.v Line: 59
+Info (12130): Elaborated megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" File: C:/New folder/ex19/mult_by_h666.v Line: 59
+Info (12133): Instantiated megafunction "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" with the following parameter: File: C:/New folder/ex19/mult_by_h666.v Line: 59
+    Info (12134): Parameter "lpm_hint" = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+    Info (12134): Parameter "lpm_representation" = "UNSIGNED"
+    Info (12134): Parameter "lpm_type" = "LPM_MULT"
+    Info (12134): Parameter "lpm_widtha" = "9"
+    Info (12134): Parameter "lpm_widthb" = "11"
+    Info (12134): Parameter "lpm_widthp" = "20"
+Info (12128): Elaborating entity "multcore" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309
+Info (12131): Elaborated megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core", which is child of megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 309
+Info (12128): Elaborating entity "mpar_add" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder" File: c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf Line: 229
+Info (12131): Elaborated megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf Line: 229
+Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12131): Elaborated megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]", which is child of megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_a9h.tdf
+    Info (12023): Found entity 1: add_sub_a9h File: C:/New folder/ex19/db/add_sub_a9h.tdf Line: 23
+Info (12128): Elaborating entity "add_sub_a9h" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_a9h:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119
+Info (12128): Elaborating entity "mpar_add" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
+Info (12131): Elaborated megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 138
+Info (12128): Elaborating entity "lpm_add_sub" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12131): Elaborated megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf Line: 78
+Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_e9h.tdf
+    Info (12023): Found entity 1: add_sub_e9h File: C:/New folder/ex19/db/add_sub_e9h.tdf Line: 23
+Info (12128): Elaborating entity "add_sub_e9h" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_e9h:auto_generated" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf Line: 119
+Info (12128): Elaborating entity "altshift" for hierarchy "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|altshift:external_latency_ffs" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352
+Info (12131): Elaborated megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component|altshift:external_latency_ffs", which is child of megafunction instantiation "processor:echo_var_delay|mult_by_h666:mul_by_h666|lpm_mult:lpm_mult_component" File: c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf Line: 352
+Info (12128): Elaborating entity "bin2bcd_16" for hierarchy "processor:echo_var_delay|bin2bcd_16:bcd" File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 36
+Info (12128): Elaborating entity "add3_ge5" for hierarchy "processor:echo_var_delay|bin2bcd_16:bcd|add3_ge5:A1" File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 26
+Info (12128): Elaborating entity "hex_to_7seg" for hierarchy "processor:echo_var_delay|hex_to_7seg:h0" File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 38
+Warning (12011): Net is missing source, defaulting to GND
+    Warning (12110): Net "processor:echo_var_delay|tmp_data[9]" is missing source, defaulting to GND File: C:/New folder/ex19/verilog_files/variable_echo.v Line: 15
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|q_b[0]" File: C:/New folder/ex19/db/altsyncram_nm22.tdf Line: 39
+Warning (12241): 4 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "HEX3[1]" is stuck at GND File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX3[2]" is stuck at GND File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX3[6]" is stuck at VCC File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX4[0]" is stuck at GND File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX4[1]" is stuck at GND File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX4[2]" is stuck at GND File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX4[3]" is stuck at GND File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX4[4]" is stuck at GND File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX4[5]" is stuck at GND File: C:/New folder/ex19/ex19.v Line: 7
+    Warning (13410): Pin "HEX4[6]" is stuck at VCC File: C:/New folder/ex19/ex19.v Line: 7
+Info (286030): Timing-Driven Synthesis is running
+Info (144001): Generated suppressed messages file C:/New folder/ex19/output_files/ex19.map.smsg
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 1 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "SW[9]" File: C:/New folder/ex19/ex19.v Line: 6
+Info (21057): Implemented 312 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 12 input pins
+    Info (21059): Implemented 43 output pins
+    Info (21061): Implemented 249 logic cells
+    Info (21064): Implemented 8 RAM segments
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 21 warnings
+    Info: Peak virtual memory: 916 megabytes
+    Info: Processing ended: Tue Dec 06 09:46:29 2016
+    Info: Elapsed time: 00:00:11
+    Info: Total CPU time (on all processors): 00:00:23
+
+
++------------------------------------------+
+; Analysis & Synthesis Suppressed Messages ;
++------------------------------------------+
+The suppressed messages can be found in C:/New folder/ex19/output_files/ex19.map.smsg.
+
+
diff --git a/part_4/ex19/output_files/ex19.map.smsg b/part_4/ex19/output_files/ex19.map.smsg
new file mode 100755
index 0000000..c7460c7
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.map.smsg
@@ -0,0 +1,35 @@
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a1" differs only in case from object "A1" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a2" differs only in case from object "A2" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a3" differs only in case from object "A3" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a4" differs only in case from object "A4" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a5" differs only in case from object "A5" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a6" differs only in case from object "A6" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a7" differs only in case from object "A7" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a8" differs only in case from object "A8" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a9" differs only in case from object "A9" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a10" differs only in case from object "A10" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a11" differs only in case from object "A11" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a12" differs only in case from object "A12" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(20): object "a13" differs only in case from object "A13" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 20
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a14" differs only in case from object "A14" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a15" differs only in case from object "A15" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a16" differs only in case from object "A16" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a17" differs only in case from object "A17" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a18" differs only in case from object "A18" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a19" differs only in case from object "A19" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a20" differs only in case from object "A20" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a21" differs only in case from object "A21" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a22" differs only in case from object "A22" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a23" differs only in case from object "A23" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a24" differs only in case from object "A24" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(21): object "a25" differs only in case from object "A25" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 21
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a26" differs only in case from object "A26" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a27" differs only in case from object "A27" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a28" differs only in case from object "A28" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a29" differs only in case from object "A29" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a30" differs only in case from object "A30" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a31" differs only in case from object "A31" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a32" differs only in case from object "A32" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a33" differs only in case from object "A33" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a34" differs only in case from object "A34" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
+Info (10281): Verilog HDL Declaration information at bin2bcd_16.v(22): object "a35" differs only in case from object "A35" in the same scope File: C:/New folder/ex19/verilog_files/bin2bcd_16.v Line: 22
diff --git a/part_4/ex19/output_files/ex19.map.summary b/part_4/ex19/output_files/ex19.map.summary
new file mode 100755
index 0000000..b995765
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.map.summary
@@ -0,0 +1,17 @@
+Analysis & Synthesis Status : Successful - Tue Dec 06 09:46:29 2016
+Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+Revision Name : ex19
+Top-level Entity Name : ex19
+Family : Cyclone V
+Logic utilization (in ALMs) : N/A
+Total registers : 126
+Total pins : 55
+Total virtual pins : 0
+Total block memory bits : 65,536
+Total DSP Blocks : 0
+Total HSSI RX PCSs : 0
+Total HSSI PMA RX Deserializers : 0
+Total HSSI TX PCSs : 0
+Total HSSI PMA TX Serializers : 0
+Total PLLs : 0
+Total DLLs : 0
diff --git a/part_4/ex19/output_files/ex19.pin b/part_4/ex19/output_files/ex19.pin
new file mode 100755
index 0000000..42bb9e7
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.pin
@@ -0,0 +1,976 @@
+ -- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, the Altera Quartus Prime License Agreement,
+ -- the Altera MegaCore Function License Agreement, or other 
+ -- applicable license agreement, including, without limitation, 
+ -- that your use is for the sole purpose of programming logic 
+ -- devices manufactured by Altera and sold by Altera or its 
+ -- authorized distributors.  Please refer to the applicable 
+ -- agreement for further details.
+ -- 
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCPGM        : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.1V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --                  Bank 3A:       3.3V
+ --                  Bank 3B:       3.3V
+ --                  Bank 4A:       3.3V
+ --                  Bank 5A:       3.3V
+ --                  Bank 5B:       3.3V
+ --                  Bank 6B:       2.5V
+ --                  Bank 6A:  2.5V
+ --                  Bank 7A:  2.5V
+ --                  Bank 7B:  2.5V
+ --                  Bank 7C:  2.5V
+ --                  Bank 7D:  2.5V
+ --                  Bank 8A:  2.5V
+ -- RREF          : External reference resistor for the quad, MUST be connected to
+ --                 GND via a 2k Ohm resistor.
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --                  It can also be used to report unused dedicated pins. The connection
+ --                  on the board for unused dedicated pins depends on whether this will
+ --                  be used in a future design. One example is device migration. When
+ --                  using device migration, refer to the device pin-tables. If it is a
+ --                  GND pin in the pin table or if it will not be used in a future design
+ --                  for another purpose the it MUST be connected to GND. If it is an unused
+ --                  dedicated pin, then it can be connected to a valid signal on the board
+ --                  (low, high, or toggling) if that signal is required for a different
+ --                  revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --                  This pin should be connected to GND. It may also be connected  to a
+ --                  valid signal  on the board  (low, high, or toggling)  if that signal
+ --                  is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --                  or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ -- GXB_NC        : Unused GXB Transmitter or dedicated clock output pin. This pin
+ --                 must not be connected.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+CHIP  "ex19"  ASSIGNED TO AN: 5CSEMA5F31C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8A        :                
+VCCIO8A                      : A7        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11       :        :                   :         : 8A        :                
+GND                          : A12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7C        :                
+GND                          : A17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21       :        :                   :         : 7B        :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25       :        :                   :         : 7A        :                
+GND                          : A26       :        :                   :         : 7A        :                
+GND                          : A27       : gnd    :                   :         :           :                
+HPS_TRST                     : A28       :        :                   :         : 7A        :                
+HPS_TMS                      : A29       :        :                   :         : 7A        :                
+GND                          : AA1       : gnd    :                   :         :           :                
+GND                          : AA2       : gnd    :                   :         :           :                
+GND                          : AA3       : gnd    :                   :         :           :                
+GND                          : AA4       : gnd    :                   :         :           :                
+VCC                          : AA5       : power  :                   : 1.1V    :           :                
+GND                          : AA6       : gnd    :                   :         :           :                
+DNU                          : AA7       :        :                   :         :           :                
+VCCA_FPLL                    : AA8       : power  :                   : 2.5V    :           :                
+GND                          : AA9       : gnd    :                   :         :           :                
+VCCPD3A                      : AA10      : power  :                   : 3.3V    : 3A        :                
+GND                          : AA11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12      :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4A        :                
+VCCIO4A                      : AA17      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 4A        :                
+GND                          : AA22      : gnd    :                   :         :           :                
+VCCPGM                       : AA23      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+HEX4[0]                      : AA24      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26      :        :                   :         : 5B        :                
+VCCIO5B                      : AA27      : power  :                   : 3.3V    : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA28      :        :                   :         : 5B        :                
+VREFB5BN0                    : AA29      : power  :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA30      :        :                   :         : 5B        :                
+GND                          : AB1       : gnd    :                   :         :           :                
+GND                          : AB2       : gnd    :                   :         :           :                
+DNU                          : AB3       :        :                   :         :           :                
+DNU                          : AB4       :        :                   :         :           :                
+GND                          : AB5       : gnd    :                   :         :           :                
+VCCA_FPLL                    : AB6       : power  :                   : 2.5V    :           :                
+GND                          : AB7       : gnd    :                   :         :           :                
+nCSO, DATA4                  : AB8       :        :                   :         : 3A        :                
+TDO                          : AB9       : output :                   :         : 3A        :                
+VCCPGM                       : AB10      : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX                      : AB11      : power  :                   : 2.5V    :           :                
+SW[0]                        : AB12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 3B        :                
+VCCIO3B                      : AB14      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 3B        :                
+VCC_AUX                      : AB16      : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AB18      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AB19      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AB20      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21      :        :                   :         : 4A        :                
+HEX3[6]                      : AB22      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[0]                      : AB23      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AB24      : power  :                   : 3.3V    : 5A        :                
+HEX3[5]                      : AB25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB26      :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB27      :        :                   :         : 5B        :                
+HEX3[4]                      : AB28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AB29      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB30      :        :                   :         : 5B        :                
+GND                          : AC1       : gnd    :                   :         :           :                
+GND                          : AC2       : gnd    :                   :         :           :                
+GND                          : AC3       : gnd    :                   :         :           :                
+GND                          : AC4       : gnd    :                   :         :           :                
+TCK                          : AC5       : input  :                   :         : 3A        :                
+GND                          : AC6       : gnd    :                   :         :           :                
+AS_DATA3, DATA3              : AC7       :        :                   :         : 3A        :                
+GND                          : AC8       : gnd    :                   :         :           :                
+SW[7]                        : AC9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3A                      : AC10      : power  :                   : 3.3V    : 3A        :                
+VCCIO3A                      : AC11      : power  :                   : 3.3V    : 3A        :                
+SW[1]                        : AC12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCPD3B4A                    : AC13      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14      :        :                   :         : 3B        :                
+VCCPD3B4A                    : AC15      : power  :                   : 3.3V    : 3B, 4A    :                
+GND                          : AC16      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AC17      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18      :        :                   :         : 4A        :                
+VCCPD3B4A                    : AC19      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC20      :        :                   :         : 4A        :                
+VCCIO4A                      : AC21      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC23      :        :                   :         : 4A        :                
+VREFB5AN0                    : AC24      : power  :                   :         : 5A        :                
+HEX3[3]                      : AC25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AC26      : gnd    :                   :         :           :                
+HEX3[1]                      : AC27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[3]                      : AC28      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[5]                      : AC29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[6]                      : AC30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AD1       : gnd    :                   :         :           :                
+GND                          : AD2       : gnd    :                   :         :           :                
+DNU                          : AD3       :        :                   :         :           :                
+DNU                          : AD4       :        :                   :         :           :                
+GND                          : AD5       : gnd    :                   :         :           :                
+VREFB3AN0                    : AD6       : power  :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7       :        :                   :         : 3A        :                
+VCCIO3A                      : AD8       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD9       :        :                   :         : 3A        :                
+SW[8]                        : AD10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[4]                        : AD11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[5]                        : AD12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+VCCIO3B                      : AD13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14      :        :                   :         : 3B        :                
+DNU                          : AD15      :        :                   :         :           :                
+VCCPD3B4A                    : AD16      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17      :        :                   :         : 4A        :                
+VCCIO4A                      : AD18      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19      :        :                   :         : 4A        :                
+DAC_CS                       : AD20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21      :        :                   :         : 4A        :                
+VCC_AUX                      : AD22      : power  :                   : 2.5V    :           :                
+GND                          : AD23      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24      :        :                   :         : 4A        :                
+HEX3[2]                      : AD25      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX3[0]                      : AD26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[6]                      : AD27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AD28      : power  :                   : 3.3V    : 5A        :                
+HEX2[2]                      : AD29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+HEX2[4]                      : AD30      : output : 3.3-V LVTTL       :         : 5B        : Y              
+GND                          : AE1       : gnd    :                   :         :           :                
+GND                          : AE2       : gnd    :                   :         :           :                
+GND                          : AE3       : gnd    :                   :         :           :                
+GND                          : AE4       : gnd    :                   :         :           :                
+AS_DATA1, DATA1              : AE5       :        :                   :         : 3A        :                
+AS_DATA0, ASDO, DATA0        : AE6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7       :        :                   :         : 3A        :                
+AS_DATA2, DATA2              : AE8       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9       :        :                   :         : 3A        :                
+GND                          : AE10      : gnd    :                   :         :           :                
+SW[6]                        : AE11      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[9]                        : AE12      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14      :        :                   :         : 3B        :                
+VCCIO3B                      : AE15      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19      :        :                   :         : 4A        :                
+GND                          : AE20      : gnd    :                   :         :           :                
+VCCPD3B4A                    : AE21      : power  :                   : 3.3V    : 3B, 4A    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24      :        :                   :         : 4A        :                
+VCCIO4A                      : AE25      : power  :                   : 3.3V    : 4A        :                
+HEX0[0]                      : AE26      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[1]                      : AE27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[2]                      : AE28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX2[1]                      : AE29      : output : 3.3-V LVTTL       :         : 5B        : Y              
+VCCIO5B                      : AE30      : power  :                   : 3.3V    : 5B        :                
+GND                          : AF1       : gnd    :                   :         :           :                
+GND                          : AF2       : gnd    :                   :         :           :                
+GND                          : AF3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6       :        :                   :         : 3A        :                
+VCCIO3A                      : AF7       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8       :        :                   :         : 3A        :                
+SW[2]                        : AF9       : input  : 3.3-V LVTTL       :         : 3A        : Y              
+SW[3]                        : AF10      : input  : 3.3-V LVTTL       :         : 3A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11      :        :                   :         : 3B        :                
+GND                          : AF12      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13      :        :                   :         : 3B        :                
+CLOCK_50                     : AF14      : input  : 3.3-V LVTTL       :         : 3B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16      :        :                   :         : 4A        :                
+GND                          : AF17      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19      :        :                   :         : 4A        :                
+DAC_SCK                      : AF20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SCK                      : AF21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+VCCIO4A                      : AF22      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26      :        :                   :         : 4A        :                
+GND                          : AF27      : gnd    :                   :         :           :                
+HEX0[4]                      : AF28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[4]                      : AF29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[5]                      : AF30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3       :        :                   :         : 3A        :                
+VCCIO3A                      : AG4       : power  :                   : 3.3V    : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG5       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8       :        :                   :         : 3A        :                
+GND                          : AG9       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG13      :        :                   :         : 3B        :                
+GND                          : AG14      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG15      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17      :        :                   :         : 4A        :                
+DAC_SDI                      : AG18      : output : 3.3-V LVTTL       :         : 4A        : Y              
+VCCIO4A                      : AG19      : power  :                   : 3.3V    : 4A        :                
+ADC_CS                       : AG20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SDI                      : AG21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23      :        :                   :         : 4A        :                
+GND                          : AG24      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26      :        :                   :         : 4A        :                
+HEX0[3]                      : AG27      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX0[5]                      : AG28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : AG29      : power  :                   : 3.3V    : 5A        :                
+HEX1[3]                      : AG30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AH1       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH2       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH5       :        :                   :         : 3A        :                
+GND                          : AH6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10      :        :                   :         : 3B        :                
+GND                          : AH11      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH14      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH15      :        :                   :         : 3B        :                
+VCCIO4A                      : AH16      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH20      :        :                   :         : 4A        :                
+GND                          : AH21      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25      :        :                   :         : 4A        :                
+VCCIO4A                      : AH26      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH27      :        :                   :         : 4A        :                
+HEX0[6]                      : AH28      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[1]                      : AH29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX1[2]                      : AH30      : output : 3.3-V LVTTL       :         : 5A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1       :        :                   :         : 3A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ2       :        :                   :         : 3A        :                
+GND                          : AJ3       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ5       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7       :        :                   :         : 3B        :                
+VCCIO3B                      : AJ8       : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ10      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12      :        :                   :         : 3B        :                
+VCCIO3B                      : AJ13      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14      :        :                   :         : 3B        :                
+VREFB3BN0                    : AJ15      : power  :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17      :        :                   :         : 4A        :                
+GND                          : AJ18      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19      :        :                   :         : 4A        :                
+PWM_OUT                      : AJ20      : output : 3.3-V LVTTL       :         : 4A        : Y              
+ADC_SDO                      : AJ21      : input  : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ22      :        :                   :         : 4A        :                
+VCCIO4A                      : AJ23      : power  :                   : 3.3V    : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ24      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27      :        :                   :         : 4A        :                
+GND                          : AJ28      : gnd    :                   :         :           :                
+HEX1[0]                      : AJ29      : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : AJ30      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK2       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK3       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK4       :        :                   :         : 3B        :                
+GND                          : AK5       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK6       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK7       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK8       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK9       :        :                   :         : 3B        :                
+VCCIO3B                      : AK10      : power  :                   : 3.3V    : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK11      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK12      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK13      :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK14      :        :                   :         : 3B        :                
+GND                          : AK15      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK16      :        :                   :         : 4A        :                
+VREFB4AN0                    : AK17      : power  :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK18      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK19      :        :                   :         : 4A        :                
+VCCIO4A                      : AK20      : power  :                   : 3.3V    : 4A        :                
+DAC_LD                       : AK21      : output : 3.3-V LVTTL       :         : 4A        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK22      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK23      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK24      :        :                   :         : 4A        :                
+GND                          : AK25      : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK26      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK27      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK28      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AK29      :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8A        :                
+VCCIO8A                      : B4        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8A        :                
+GND                          : B9        : gnd    :                   :         :           :                
+VREFB8AN0                    : B10       : power  :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 8A        :                
+GND                          : B14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7B        :                
+GND                          : B19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23       :        :                   :         : 7A        :                
+GND                          : B24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26       :        :                   :         : 7A        :                
+HPS_TDI                      : B27       :        :                   :         : 7A        :                
+HPS_TDO                      : B28       :        :                   :         : 7A        :                
+GND                          : B29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B30       :        :                   :         : 6A        :                
+GND                          : C1        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5        :        :                   :         : 8A        :                
+GND                          : C6        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8A        :                
+VCCIO8A                      : C11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7D        :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 7B        :                
+GND                          : C21       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25       :        :                   :         : 7A        :                
+GND                          : C26       : gnd    :                   :         :           :                
+HPS_nRST                     : C27       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2        :        :                   :         : 8A        :                
+GND                          : D3        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8A        :                
+VCCIO8A                      : D8        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 8A        :                
+GND                          : D13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7C        :                
+VCCIO7C_HPS                  : D18       : power  :                   : 2.5V    : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 7A        :                
+GND                          : D23       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24       :        :                   :         : 7A        :                
+HPS_CLK1                     : D25       :        :                   :         : 7A        :                
+GND                          : D26       :        :                   :         : 7A        :                
+HPS_RZQ_0                    : D27       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : D28       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D30       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E2        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 8A        :                
+VCCIO8A                      : E5        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8A        :                
+GND                          : E10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7D        :                
+VCCIO7D_HPS                  : E15       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E19       :        :                   :         : 7B        :                
+VCCIO7B_HPS                  : E20       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 7B        :                
+VREFB7A7B7C7DN0_HPS          : E22       : power  :                   :         : 7A, 7B, 7C, 7D :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24       :        :                   :         : 7A        :                
+GND                          : E25       : gnd    :                   :         :           :                
+DNU                          : E26       :        :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E29       :        :                   :         : 6A        :                
+GND                          : E30       : gnd    :                   :         :           :                
+DNU                          : F1        :        :                   :         :           :                
+GND                          : F2        : gnd    :                   :         :           :                
+CONF_DONE                    : F3        :        :                   :         : 9A        :                
+nSTATUS                      : F4        :        :                   :         : 9A        :                
+GND                          : F5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F6        :        :                   :         : 8A        :                
+GND                          : F7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11       :        :                   :         : 8A        :                
+VCCIO8A                      : F12       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7D        :                
+GND                          : F17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F18       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 7B        :                
+VCCIO7A_HPS                  : F22       : power  :                   : 2.5V    : 7A        :                
+HPS_nPOR                     : F23       :        :                   :         : 7A        :                
+HPS_PORSEL                   : F24       :        :                   :         : 7A        :                
+HPS_CLK2                     : F25       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26       :        :                   :         : 6A        :                
+GND                          : F27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F30       :        :                   :         : 6A        :                
+GND                          : G1        :        :                   :         :           :                
+DNU                          : G2        :        :                   :         :           :                
+GND                          : G3        : gnd    :                   :         :           :                
+GND                          : G4        : gnd    :                   :         :           :                
+nCE                          : G5        :        :                   :         : 9A        :                
+MSEL2                        : G6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8A        :                
+VCCIO8A                      : G9        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 8A        :                
+VCCIO8A                      : G14       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 7C        :                
+VCCIO7B_HPS                  : G19       : power  :                   : 2.5V    : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22       :        :                   :         : 7A        :                
+VCCRSTCLK_HPS                : G23       :        :                   :         : 7A        :                
+GND                          : G24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : G29       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G30       :        :                   :         : 6A        :                
+GND                          : H1        : gnd    :                   :         :           :                
+GND                          : H2        : gnd    :                   :         :           :                
+DNU                          : H3        :        :                   :         :           :                
+DNU                          : H4        :        :                   :         :           :                
+GND                          : H5        : gnd    :                   :         :           :                
+VCCIO8A                      : H6        : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 8A        :                
+VCCBAT                       : H9        : power  :                   : 1.2V    :           :                
+VCC_AUX                      : H10       : power  :                   : 2.5V    :           :                
+GND                          : H11       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 8A        :                
+VCCIO7D_HPS                  : H16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17       :        :                   :         : 7C        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H19       :        :                   :         : 7B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H20       :        :                   :         : 7A        :                
+VCCIO7A_HPS                  : H21       : power  :                   : 2.5V    : 7A        :                
+HPS_TCK                      : H22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : H26       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H30       :        :                   :         : 6A        :                
+GND                          : J1        : gnd    :                   :         :           :                
+GND                          : J2        : gnd    :                   :         :           :                
+GND                          : J3        : gnd    :                   :         :           :                
+GND                          : J4        : gnd    :                   :         :           :                
+nCONFIG                      : J5        :        :                   :         : 9A        :                
+GND                          : J6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7        :        :                   :         : 8A        :                
+GND                          : J8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J9        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10       :        :                   :         : 8A        :                
+VCCPGM                       : J11       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12       :        :                   :         : 8A        :                
+VCCIO8A                      : J13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 8A        :                
+DNU                          : J15       :        :                   :         :           :                
+VCC_AUX                      : J16       : power  :                   : 2.5V    :           :                
+VCCPD7C_HPS                  : J17       : power  :                   : 2.5V    : 7C        :                
+GND                          : J18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J19       :        :                   :         : 7B        :                
+VCCRSTCLK_HPS                : J20       : power  :                   : 1.8V/2.5V/3.0V/3.3V :           :                
+VCC_AUX_SHARED               : J21       : power  :                   : 2.5V    :           :                
+GND                          : J22       :        :                   :         : 7A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J27       :        :                   :         : 6A        :                
+GND                          : J28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J30       :        :                   :         : 6A        :                
+GND                          : K1        : gnd    :                   :         :           :                
+GND                          : K2        : gnd    :                   :         :           :                
+DNU                          : K3        :        :                   :         :           :                
+DNU                          : K4        :        :                   :         :           :                
+GND                          : K5        : gnd    :                   :         :           :                
+MSEL1                        : K6        :        :                   :         : 9A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 8A        :                
+VCCA_FPLL                    : K9        : power  :                   : 2.5V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+VCCPD8A                      : K11       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K12       :        :                   :         : 8A        :                
+VCCPD8A                      : K13       : power  :                   : 2.5V    : 8A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K14       :        :                   :         : 8A        :                
+GND                          : K15       : gnd    :                   :         :           :                
+VCCPD7D_HPS                  : K16       : power  :                   : 2.5V    : 7D        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K17       :        :                   :         : 7B        :                
+VCCPD7B_HPS                  : K18       : power  :                   : 2.5V    : 7B        :                
+VCCPD7A_HPS                  : K19       : power  :                   : 2.5V    : 7A        :                
+GND                          : K20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K24       : power  :                   : 2.5V    : 6A        :                
+GND                          : K25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K29       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : K30       : power  :                   : 2.5V    : 6A        :                
+GND                          : L1        : gnd    :                   :         :           :                
+GND                          : L2        : gnd    :                   :         :           :                
+GND                          : L3        : gnd    :                   :         :           :                
+GND                          : L4        : gnd    :                   :         :           :                
+VCC                          : L5        : power  :                   : 1.1V    :           :                
+GND                          : L6        : gnd    :                   :         :           :                
+MSEL3                        : L7        :        :                   :         : 9A        :                
+MSEL0                        : L8        :        :                   :         : 9A        :                
+MSEL4                        : L9        :        :                   :         : 9A        :                
+VCCPD8A                      : L10       : power  :                   : 2.5V    : 8A        :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCPD8A                      : L12       : power  :                   : 2.5V    : 8A        :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCPD8A                      : L14       : power  :                   : 2.5V    : 8A        :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCC_HPS                      : L16       : power  :                   : 1.1V    :           :                
+GND                          : L17       : gnd    :                   :         :           :                
+VCC_HPS                      : L18       : power  :                   : 1.1V    :           :                
+GND                          : L19       : gnd    :                   :         :           :                
+VCC_HPS                      : L20       : power  :                   : 1.1V    :           :                
+VCCPLL_HPS                   : L21       : power  :                   : 2.5V    :           :                
+GND                          : L22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : L27       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L29       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L30       :        :                   :         : 6A        :                
+GND                          : M1        : gnd    :                   :         :           :                
+GND                          : M2        : gnd    :                   :         :           :                
+DNU                          : M3        :        :                   :         :           :                
+DNU                          : M4        :        :                   :         :           :                
+GND                          : M5        : gnd    :                   :         :           :                
+VCC                          : M6        : power  :                   : 1.1V    :           :                
+GND                          : M7        : gnd    :                   :         :           :                
+GND                          : M8        : gnd    :                   :         :           :                
+VCC                          : M9        : power  :                   : 1.1V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+VCC                          : M11       : power  :                   : 1.1V    :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+VCC                          : M13       : power  :                   : 1.1V    :           :                
+GND                          : M14       : gnd    :                   :         :           :                
+VCC_HPS                      : M15       : power  :                   : 1.1V    :           :                
+GND                          : M16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M17       :        :                   :         : 7D        :                
+GND                          : M18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 6A        :                
+GND                          : M20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : M21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M23       :        :                   :         : 6A        :                
+VCCIO6A_HPS                  : M24       : power  :                   : 2.5V    : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28       :        :                   :         : 6A        :                
+GND                          : M29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M30       :        :                   :         : 6A        :                
+GND                          : N1        : gnd    :                   :         :           :                
+GND                          : N2        : gnd    :                   :         :           :                
+GND                          : N3        : gnd    :                   :         :           :                
+GND                          : N4        : gnd    :                   :         :           :                
+VCC                          : N5        : power  :                   : 1.1V    :           :                
+GND                          : N6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : N7        : power  :                   : 2.5V    :           :                
+GND                          : N8        : gnd    :                   :         :           :                
+GND                          : N9        : gnd    :                   :         :           :                
+VCC                          : N10       : power  :                   : 1.1V    :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+VCC                          : N12       : power  :                   : 1.1V    :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCC                          : N14       : power  :                   : 1.1V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 7D        :                
+GND                          : N17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 6A        :                
+GND                          : N19       : gnd    :                   :         :           :                
+VCC_HPS                      : N20       : power  :                   : 1.1V    :           :                
+VCCIO6A_HPS                  : N21       : power  :                   : 2.5V    : 6A        :                
+VCCPD6A6B_HPS                : N22       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N23       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N24       :        :                   :         : 6A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25       :        :                   :         : 6A        :                
+GND                          : N26       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N30       :        :                   :         : 6B        :                
+GND                          : P1        : gnd    :                   :         :           :                
+GND                          : P2        : gnd    :                   :         :           :                
+DNU                          : P3        :        :                   :         :           :                
+DNU                          : P4        :        :                   :         :           :                
+GND                          : P5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : P6        : power  :                   : 2.5V    :           :                
+GND                          : P7        : gnd    :                   :         :           :                
+GND                          : P8        : gnd    :                   :         :           :                
+GND                          : P9        : gnd    :                   :         :           :                
+GND                          : P10       : gnd    :                   :         :           :                
+VCC                          : P11       : power  :                   : 1.1V    :           :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCC                          : P13       : power  :                   : 1.1V    :           :                
+GND                          : P14       : gnd    :                   :         :           :                
+VCC_HPS                      : P15       : power  :                   : 1.1V    :           :                
+GND                          : P16       : gnd    :                   :         :           :                
+VCC_HPS                      : P17       : power  :                   : 1.1V    :           :                
+GND                          : P18       : gnd    :                   :         :           :                
+VCC_HPS                      : P19       : power  :                   : 1.1V    :           :                
+GND                          : P20       : gnd    :                   :         :           :                
+VCCPD6A6B_HPS                : P21       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P23       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : P28       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P30       :        :                   :         : 6B        :                
+GND                          : R1        : gnd    :                   :         :           :                
+GND                          : R2        : gnd    :                   :         :           :                
+GND                          : R3        : gnd    :                   :         :           :                
+GND                          : R4        : gnd    :                   :         :           :                
+VCC                          : R5        : power  :                   : 1.1V    :           :                
+GND                          : R6        : gnd    :                   :         :           :                
+VCCA_FPLL                    : R7        : power  :                   : 2.5V    :           :                
+GND                          : R8        : gnd    :                   :         :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCC                          : R10       : power  :                   : 1.1V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCC                          : R12       : power  :                   : 1.1V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+VCC                          : R14       : power  :                   : 1.1V    :           :                
+GND                          : R15       : gnd    :                   :         :           :                
+VCC_HPS                      : R16       : power  :                   : 1.1V    :           :                
+GND                          : R17       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R20       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 6B        :                
+VCCPD6A6B_HPS                : R23       : power  :                   : 2.5V    : 6A, 6B    :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : R25       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R29       :        :                   :         : 6B        :                
+GND                          : R30       : gnd    :                   :         :           :                
+GND                          : T1        : gnd    :                   :         :           :                
+GND                          : T2        : gnd    :                   :         :           :                
+DNU                          : T3        :        :                   :         :           :                
+DNU                          : T4        :        :                   :         :           :                
+GND                          : T5        : gnd    :                   :         :           :                
+VCC                          : T6        : power  :                   : 1.1V    :           :                
+GND                          : T7        : gnd    :                   :         :           :                
+GND                          : T8        : gnd    :                   :         :           :                
+GND                          : T9        : gnd    :                   :         :           :                
+GND                          : T10       : gnd    :                   :         :           :                
+VCC                          : T11       : power  :                   : 1.1V    :           :                
+GND                          : T12       : gnd    :                   :         :           :                
+VCC                          : T13       : power  :                   : 1.1V    :           :                
+GND                          : T14       : gnd    :                   :         :           :                
+GND                          : T15       : gnd    :                   :         :           :                
+GND                          : T16       : gnd    :                   :         :           :                
+VCC_HPS                      : T17       : power  :                   : 1.1V    :           :                
+GND                          : T18       : gnd    :                   :         :           :                
+VCC_HPS                      : T19       : power  :                   : 1.1V    :           :                
+GND                          : T20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21       :        :                   :         : 6B        :                
+VCCIO6B_HPS                  : T22       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T23       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T24       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26       :        :                   :         : 6B        :                
+GND                          : T27       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T30       :        :                   :         : 6B        :                
+GND                          : U1        : gnd    :                   :         :           :                
+GND                          : U2        : gnd    :                   :         :           :                
+GND                          : U3        : gnd    :                   :         :           :                
+GND                          : U4        : gnd    :                   :         :           :                
+VCC                          : U5        : power  :                   : 1.1V    :           :                
+GND                          : U6        : gnd    :                   :         :           :                
+DCLK                         : U7        :        :                   :         : 3A        :                
+TDI                          : U8        : input  :                   :         : 3A        :                
+GND                          : U9        : gnd    :                   :         :           :                
+VCC                          : U10       : power  :                   : 1.1V    :           :                
+GND                          : U11       : gnd    :                   :         :           :                
+VCC                          : U12       : power  :                   : 1.1V    :           :                
+GND                          : U13       : gnd    :                   :         :           :                
+VCC                          : U14       : power  :                   : 1.1V    :           :                
+GND                          : U15       : gnd    :                   :         :           :                
+VCC_HPS                      : U16       : power  :                   : 1.1V    :           :                
+GND                          : U17       : gnd    :                   :         :           :                
+VCC_HPS                      : U18       : power  :                   : 1.1V    :           :                
+VCCIO6B_HPS                  : U19       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 6B        :                
+VCC                          : U21       : power  :                   : 1.1V    :           :                
+GND                          : U22       : gnd    :                   :         :           :                
+VCCPD5B                      : U23       : power  :                   : 3.3V    : 5B        :                
+GND                          : U24       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28       :        :                   :         : 6B        :                
+GND                          : U29       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U30       :        :                   :         : 6B        :                
+GND                          : V1        : gnd    :                   :         :           :                
+GND                          : V2        : gnd    :                   :         :           :                
+DNU                          : V3        :        :                   :         :           :                
+DNU                          : V4        :        :                   :         :           :                
+GND                          : V5        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V6        : power  :                   : 2.5V    :           :                
+GND                          : V7        : gnd    :                   :         :           :                
+VCCA_FPLL                    : V8        : power  :                   : 2.5V    :           :                
+TMS                          : V9        : input  :                   :         : 3A        :                
+GND                          : V10       : gnd    :                   :         :           :                
+VCC                          : V11       : power  :                   : 1.1V    :           :                
+GND                          : V12       : gnd    :                   :         :           :                
+VCC                          : V13       : power  :                   : 1.1V    :           :                
+GND                          : V14       : gnd    :                   :         :           :                
+VCC                          : V15       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V18       :        :                   :         : 4A        :                
+GND                          : V19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V20       :        :                   :         : 6B        :                
+GND                          : V21       : gnd    :                   :         :           :                
+VCCPD5A                      : V22       : power  :                   : 3.3V    : 5A        :                
+HEX4[5]                      : V23       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCPD5A                      : V24       : power  :                   : 3.3V    : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25       :        :                   :         : 5B        :                
+VCCIO6B_HPS                  : V26       : power  :                   : 2.5V    : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V30       :        :                   :         : 6B        :                
+GND                          : W1        : gnd    :                   :         :           :                
+GND                          : W2        : gnd    :                   :         :           :                
+GND                          : W3        : gnd    :                   :         :           :                
+GND                          : W4        : gnd    :                   :         :           :                
+VCC                          : W5        : power  :                   : 1.1V    :           :                
+GND                          : W6        : gnd    :                   :         :           :                
+GND                          : W7        : gnd    :                   :         :           :                
+GND                          : W8        : gnd    :                   :         :           :                
+GND                          : W9        : gnd    :                   :         :           :                
+VCC                          : W10       : power  :                   : 1.1V    :           :                
+GND                          : W11       : gnd    :                   :         :           :                
+VCC                          : W12       : power  :                   : 1.1V    :           :                
+GND                          : W13       : gnd    :                   :         :           :                
+VCC                          : W14       : power  :                   : 1.1V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W16       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4A        :                
+GND                          : W18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5A        :                
+HEX4[3]                      : W22       : output : 3.3-V LVTTL       :         : 5A        : Y              
+VCCIO5A                      : W23       : power  :                   : 3.3V    : 5A        :                
+HEX4[4]                      : W24       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[6]                      : W25       : output : 3.3-V LVTTL       :         : 5B        : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27       :        :                   :         : 6B        :                
+GND                          : W28       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W29       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W30       :        :                   :         : 6B        :                
+GND                          : Y1        : gnd    :                   :         :           :                
+GND                          : Y2        : gnd    :                   :         :           :                
+DNU                          : Y3        :        :                   :         :           :                
+DNU                          : Y4        :        :                   :         :           :                
+GND                          : Y5        : gnd    :                   :         :           :                
+VCC                          : Y6        : power  :                   : 1.1V    :           :                
+GND                          : Y7        : gnd    :                   :         :           :                
+GND                          : Y8        : gnd    :                   :         :           :                
+VCC                          : Y9        : power  :                   : 1.1V    :           :                
+GND                          : Y10       : gnd    :                   :         :           :                
+VCC                          : Y11       : power  :                   : 1.1V    :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VCC                          : Y13       : power  :                   : 1.1V    :           :                
+GND                          : Y14       : gnd    :                   :         :           :                
+GND                          : Y15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16       :        :                   :         : 3B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y18       :        :                   :         : 4A        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19       :        :                   :         : 4A        :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5A        :                
+VCCA_FPLL                    : Y22       : power  :                   : 2.5V    :           :                
+HEX4[1]                      : Y23       : output : 3.3-V LVTTL       :         : 5A        : Y              
+HEX4[2]                      : Y24       : output : 3.3-V LVTTL       :         : 5A        : Y              
+GND                          : Y25       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y27       :        :                   :         : 5B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y28       :        :                   :         : 6B        :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y29       :        :                   :         : 6B        :                
+GND                          : Y30       : gnd    :                   :         :           :                
diff --git a/part_4/ex19/output_files/ex19.sld b/part_4/ex19/output_files/ex19.sld
new file mode 100755
index 0000000..41a6030
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.sld
@@ -0,0 +1 @@
+<sld_project_info/>
diff --git a/part_4/ex19/output_files/ex19.sof b/part_4/ex19/output_files/ex19.sof
new file mode 100755
index 0000000..169600d
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.sof
diff --git a/part_2/ex9_partially_working/output_files/ex9.sta.rpt b/part_4/ex19/output_files/ex19.sta.rpt
index b7af62e..2c7752c 100755
--- a/part_2/ex9_partially_working/output_files/ex9.sta.rpt
+++ b/part_4/ex19/output_files/ex19.sta.rpt
@@ -1,5 +1,5 @@
-TimeQuest Timing Analyzer report for ex9
-Fri Nov 25 11:28:08 2016
+TimeQuest Timing Analyzer report for ex19
+Tue Dec 06 09:47:26 2016
 Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
 
 
@@ -83,7 +83,7 @@ agreement for further details.
 +-----------------------+---------------------------------------------------------+
 ; Quartus Prime Version ; Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition ;
 ; Timing Analyzer       ; TimeQuest                                               ;
-; Revision Name         ; ex9                                                     ;
+; Revision Name         ; ex19                                                    ;
 ; Device Family         ; Cyclone V                                               ;
 ; Device Name           ; 5CSEMA5F31C6                                            ;
 ; Timing Models         ; Final                                                   ;
@@ -100,27 +100,27 @@ agreement for further details.
 ; Number detected on machine ; 8           ;
 ; Maximum allowed            ; 4           ;
 ;                            ;             ;
-; Average used               ; 1.13        ;
+; Average used               ; 1.20        ;
 ; Maximum used               ; 4           ;
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   4.6%      ;
-;     Processor 3            ;   4.5%      ;
-;     Processor 4            ;   4.4%      ;
+;     Processor 2            ;   6.8%      ;
+;     Processor 3            ;   6.7%      ;
+;     Processor 4            ;   6.6%      ;
 +----------------------------+-------------+
 
 
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks                                                                                                                                                                                                                                   ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; Clock Name                          ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                 ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
-; CLOCK_50                            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                            ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { formula_fsm:FSM|state.LIGHT_UP_LEDS } ;
-; tick_2500:TICK1|CLK_OUT             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_2500:TICK1|CLK_OUT }             ;
-; tick_50000:TICK0|CLK_OUT            ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { tick_50000:TICK0|CLK_OUT }            ;
-+-------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                             ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+; Clock Name               ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                      ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
+; CLOCK_50                 ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                 ;
+; spi2adc:SPI_ADC|adc_cs   ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2adc:SPI_ADC|adc_cs }   ;
+; spi2adc:SPI_ADC|clk_1MHz ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2adc:SPI_ADC|clk_1MHz } ;
+; spi2dac:SPI_DAC|clk_1MHz ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { spi2dac:SPI_DAC|clk_1MHz } ;
++--------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------------------------+
 
 
 +----------------------------------------------------------------+
@@ -128,9 +128,10 @@ agreement for further details.
 +------------+-----------------+--------------------------+------+
 ; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
 +------------+-----------------+--------------------------+------+
-; 239.81 MHz ; 239.81 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 295.86 MHz ; 295.86 MHz      ; CLOCK_50                 ;      ;
-; 446.83 MHz ; 446.83 MHz      ; tick_2500:TICK1|CLK_OUT  ;      ;
+; 197.01 MHz ; 197.01 MHz      ; spi2adc:SPI_ADC|clk_1MHz ;      ;
+; 206.78 MHz ; 206.78 MHz      ; CLOCK_50                 ;      ;
+; 326.8 MHz  ; 326.8 MHz       ; spi2adc:SPI_ADC|adc_cs   ;      ;
+; 421.59 MHz ; 421.59 MHz      ; spi2dac:SPI_DAC|clk_1MHz ;      ;
 +------------+-----------------+--------------------------+------+
 This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
 
@@ -141,28 +142,28 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
 HTML report is unavailable in plain text report export.
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -4.063 ; -92.490       ;
-; tick_50000:TICK0|CLK_OUT            ; -3.170 ; -100.678      ;
-; tick_2500:TICK1|CLK_OUT             ; -1.647 ; -14.530       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.569 ; -1.569        ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary               ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -5.675 ; -1310.496     ;
+; spi2dac:SPI_DAC|clk_1MHz ; -3.850 ; -67.920       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -3.352 ; -52.261       ;
+; spi2adc:SPI_ADC|adc_cs   ; -2.060 ; -28.823       ;
++--------------------------+--------+---------------+
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Hold Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -2.594 ; -2.594        ;
-; tick_50000:TICK0|CLK_OUT            ; 0.279  ; 0.000         ;
-; tick_2500:TICK1|CLK_OUT             ; 0.351  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.556  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++--------------------------------------------------+
+; Slow 1100mV 85C Model Hold Summary               ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; spi2adc:SPI_ADC|clk_1MHz ; 0.121 ; 0.000         ;
+; CLOCK_50                 ; 0.225 ; 0.000         ;
+; spi2adc:SPI_ADC|adc_cs   ; 0.438 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.767 ; 0.000         ;
++--------------------------+-------+---------------+
 
 
 ------------------------------------------
@@ -177,22 +178,23 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.746 ; -27.464       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -24.429       ;
-; tick_2500:TICK1|CLK_OUT             ; -0.394 ; -5.270        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.461  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1208.848     ;
+; spi2adc:SPI_ADC|clk_1MHz ; -0.394 ; -16.455       ;
+; spi2dac:SPI_DAC|clk_1MHz ; -0.394 ; -13.115       ;
+; spi2adc:SPI_ADC|adc_cs   ; -0.394 ; -8.336        ;
++--------------------------+--------+---------------+
 
 
 -----------------------------------------------
 ; Slow 1100mV 85C Model Metastability Summary ;
 -----------------------------------------------
-No synchronizer chains to report.
+Design MTBF is not calculated because the design doesn't meet its timing requirements.
+
 
 
 +----------------------------------------------------------------+
@@ -200,35 +202,36 @@ No synchronizer chains to report.
 +------------+-----------------+--------------------------+------+
 ; Fmax       ; Restricted Fmax ; Clock Name               ; Note ;
 +------------+-----------------+--------------------------+------+
-; 244.98 MHz ; 244.98 MHz      ; tick_50000:TICK0|CLK_OUT ;      ;
-; 276.93 MHz ; 276.93 MHz      ; CLOCK_50                 ;      ;
-; 451.06 MHz ; 451.06 MHz      ; tick_2500:TICK1|CLK_OUT  ;      ;
+; 206.44 MHz ; 206.44 MHz      ; spi2adc:SPI_ADC|clk_1MHz ;      ;
+; 208.29 MHz ; 208.29 MHz      ; CLOCK_50                 ;      ;
+; 318.88 MHz ; 318.88 MHz      ; spi2adc:SPI_ADC|adc_cs   ;      ;
+; 425.71 MHz ; 425.71 MHz      ; spi2dac:SPI_DAC|clk_1MHz ;      ;
 +------------+-----------------+--------------------------+------+
 This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -3.620 ; -88.501       ;
-; tick_50000:TICK0|CLK_OUT            ; -3.082 ; -96.216       ;
-; tick_2500:TICK1|CLK_OUT             ; -1.680 ; -14.714       ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.485 ; -1.485        ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -5.268 ; -1146.977     ;
+; spi2dac:SPI_DAC|clk_1MHz ; -3.985 ; -70.248       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -3.474 ; -50.644       ;
+; spi2adc:SPI_ADC|adc_cs   ; -2.136 ; -29.447       ;
++--------------------------+--------+---------------+
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Hold Summary                            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -2.768 ; -2.768        ;
-; tick_50000:TICK0|CLK_OUT            ; 0.282  ; 0.000         ;
-; tick_2500:TICK1|CLK_OUT             ; 0.351  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.430  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++--------------------------------------------------+
+; Slow 1100mV 0C Model Hold Summary                ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; spi2adc:SPI_ADC|clk_1MHz ; 0.113 ; 0.000         ;
+; CLOCK_50                 ; 0.216 ; 0.000         ;
+; spi2adc:SPI_ADC|adc_cs   ; 0.451 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.729 ; 0.000         ;
++--------------------------+-------+---------------+
 
 
 -----------------------------------------
@@ -243,46 +246,47 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.788 ; -25.568       ;
-; tick_50000:TICK0|CLK_OUT            ; -0.394 ; -24.417       ;
-; tick_2500:TICK1|CLK_OUT             ; -0.394 ; -5.220        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.471  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Slow 1100mV 0C Model Minimum Pulse Width Summary  ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1202.219     ;
+; spi2adc:SPI_ADC|clk_1MHz ; -0.394 ; -16.947       ;
+; spi2dac:SPI_DAC|clk_1MHz ; -0.394 ; -13.226       ;
+; spi2adc:SPI_ADC|adc_cs   ; -0.394 ; -8.192        ;
++--------------------------+--------+---------------+
 
 
 ----------------------------------------------
 ; Slow 1100mV 0C Model Metastability Summary ;
 ----------------------------------------------
-No synchronizer chains to report.
+Design MTBF is not calculated because the design doesn't meet its timing requirements.
+
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Setup Summary                          ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -3.305 ; -54.566       ;
-; tick_50000:TICK0|CLK_OUT            ; -1.630 ; -50.049       ;
-; tick_2500:TICK1|CLK_OUT             ; -1.087 ; -9.482        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.488 ; -0.488        ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary               ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -3.917 ; -921.485      ;
+; spi2dac:SPI_DAC|clk_1MHz ; -1.773 ; -30.272       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -1.528 ; -26.809       ;
+; spi2adc:SPI_ADC|adc_cs   ; -0.942 ; -13.341       ;
++--------------------------+--------+---------------+
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Hold Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -1.523 ; -1.523        ;
-; tick_2500:TICK1|CLK_OUT             ; -0.071 ; -0.328        ;
-; tick_50000:TICK0|CLK_OUT            ; 0.094  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.134  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++--------------------------------------------------+
+; Fast 1100mV 85C Model Hold Summary               ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; spi2adc:SPI_ADC|clk_1MHz ; 0.084 ; 0.000         ;
+; CLOCK_50                 ; 0.130 ; 0.000         ;
+; spi2adc:SPI_ADC|adc_cs   ; 0.162 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.345 ; 0.000         ;
++--------------------------+-------+---------------+
 
 
 ------------------------------------------
@@ -297,46 +301,47 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.856 ; -19.710       ;
-; tick_50000:TICK0|CLK_OUT            ; 0.062  ; 0.000         ;
-; tick_2500:TICK1|CLK_OUT             ; 0.127  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.480  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1213.382     ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.033  ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.054  ; 0.000         ;
+; spi2adc:SPI_ADC|adc_cs   ; 0.156  ; 0.000         ;
++--------------------------+--------+---------------+
 
 
 -----------------------------------------------
 ; Fast 1100mV 85C Model Metastability Summary ;
 -----------------------------------------------
-No synchronizer chains to report.
+Design MTBF is not calculated because the design doesn't meet its timing requirements.
+
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Setup Summary                           ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -2.694 ; -44.892       ;
-; tick_50000:TICK0|CLK_OUT            ; -1.427 ; -42.012       ;
-; tick_2500:TICK1|CLK_OUT             ; -0.980 ; -8.435        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; -0.386 ; -0.386        ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary                ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -3.277 ; -712.908      ;
+; spi2dac:SPI_DAC|clk_1MHz ; -1.708 ; -28.858       ;
+; spi2adc:SPI_ADC|clk_1MHz ; -1.479 ; -23.942       ;
+; spi2adc:SPI_ADC|adc_cs   ; -0.834 ; -11.645       ;
++--------------------------+--------+---------------+
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Hold Summary                            ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -1.553 ; -1.553        ;
-; tick_2500:TICK1|CLK_OUT             ; -0.102 ; -0.665        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.064  ; 0.000         ;
-; tick_50000:TICK0|CLK_OUT            ; 0.081  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++--------------------------------------------------+
+; Fast 1100mV 0C Model Hold Summary                ;
++--------------------------+-------+---------------+
+; Clock                    ; Slack ; End Point TNS ;
++--------------------------+-------+---------------+
+; spi2adc:SPI_ADC|clk_1MHz ; 0.104 ; 0.000         ;
+; CLOCK_50                 ; 0.123 ; 0.000         ;
+; spi2adc:SPI_ADC|adc_cs   ; 0.149 ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.314 ; 0.000         ;
++--------------------------+-------+---------------+
 
 
 -----------------------------------------
@@ -351,40 +356,41 @@ No paths to report.
 No paths to report.
 
 
-+--------------------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary             ;
-+-------------------------------------+--------+---------------+
-; Clock                               ; Slack  ; End Point TNS ;
-+-------------------------------------+--------+---------------+
-; CLOCK_50                            ; -0.880 ; -23.155       ;
-; tick_50000:TICK0|CLK_OUT            ; 0.079  ; 0.000         ;
-; tick_2500:TICK1|CLK_OUT             ; 0.135  ; 0.000         ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 0.483  ; 0.000         ;
-+-------------------------------------+--------+---------------+
++---------------------------------------------------+
+; Fast 1100mV 0C Model Minimum Pulse Width Summary  ;
++--------------------------+--------+---------------+
+; Clock                    ; Slack  ; End Point TNS ;
++--------------------------+--------+---------------+
+; CLOCK_50                 ; -2.174 ; -1236.838     ;
+; spi2adc:SPI_ADC|clk_1MHz ; 0.062  ; 0.000         ;
+; spi2dac:SPI_DAC|clk_1MHz ; 0.076  ; 0.000         ;
+; spi2adc:SPI_ADC|adc_cs   ; 0.161  ; 0.000         ;
++--------------------------+--------+---------------+
 
 
 ----------------------------------------------
 ; Fast 1100mV 0C Model Metastability Summary ;
 ----------------------------------------------
-No synchronizer chains to report.
+Design MTBF is not calculated because the design doesn't meet its timing requirements.
 
 
-+-----------------------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary                                                                 ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Clock                                ; Setup    ; Hold   ; Recovery ; Removal ; Minimum Pulse Width ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
-; Worst-case Slack                     ; -4.063   ; -2.768 ; N/A      ; N/A     ; -0.880              ;
-;  CLOCK_50                            ; -4.063   ; -2.768 ; N/A      ; N/A     ; -0.880              ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.569   ; 0.064  ; N/A      ; N/A     ; 0.461               ;
-;  tick_2500:TICK1|CLK_OUT             ; -1.680   ; -0.102 ; N/A      ; N/A     ; -0.394              ;
-;  tick_50000:TICK0|CLK_OUT            ; -3.170   ; 0.081  ; N/A      ; N/A     ; -0.394              ;
-; Design-wide TNS                      ; -209.267 ; -2.768 ; 0.0      ; 0.0     ; -57.163             ;
-;  CLOCK_50                            ; -92.490  ; -2.768 ; N/A      ; N/A     ; -27.464             ;
-;  formula_fsm:FSM|state.LIGHT_UP_LEDS ; -1.569   ; 0.000  ; N/A      ; N/A     ; 0.000               ;
-;  tick_2500:TICK1|CLK_OUT             ; -14.714  ; -0.665 ; N/A      ; N/A     ; -5.270              ;
-;  tick_50000:TICK0|CLK_OUT            ; -100.678 ; 0.000  ; N/A      ; N/A     ; -24.429             ;
-+--------------------------------------+----------+--------+----------+---------+---------------------+
+
++------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                      ;
++---------------------------+-----------+-------+----------+---------+---------------------+
+; Clock                     ; Setup     ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++---------------------------+-----------+-------+----------+---------+---------------------+
+; Worst-case Slack          ; -5.675    ; 0.084 ; N/A      ; N/A     ; -2.174              ;
+;  CLOCK_50                 ; -5.675    ; 0.123 ; N/A      ; N/A     ; -2.174              ;
+;  spi2adc:SPI_ADC|adc_cs   ; -2.136    ; 0.149 ; N/A      ; N/A     ; -0.394              ;
+;  spi2adc:SPI_ADC|clk_1MHz ; -3.474    ; 0.084 ; N/A      ; N/A     ; -0.394              ;
+;  spi2dac:SPI_DAC|clk_1MHz ; -3.985    ; 0.314 ; N/A      ; N/A     ; -0.394              ;
+; Design-wide TNS           ; -1459.5   ; 0.0   ; 0.0      ; 0.0     ; -1246.754           ;
+;  CLOCK_50                 ; -1310.496 ; 0.000 ; N/A      ; N/A     ; -1236.838           ;
+;  spi2adc:SPI_ADC|adc_cs   ; -29.447   ; 0.000 ; N/A      ; N/A     ; -8.336              ;
+;  spi2adc:SPI_ADC|clk_1MHz ; -52.261   ; 0.000 ; N/A      ; N/A     ; -16.947             ;
+;  spi2dac:SPI_DAC|clk_1MHz ; -70.248   ; 0.000 ; N/A      ; N/A     ; -13.226             ;
++---------------------------+-----------+-------+----------+---------+---------------------+
 
 
 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -427,23 +433,14 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
 +---------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
 
 
@@ -452,11 +449,18 @@ No synchronizer chains to report.
 +----------+--------------+-----------------+-----------------+
 ; Pin      ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
 +----------+--------------+-----------------+-----------------+
-; KEY[1]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[2]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[0]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
 ; CLOCK_50 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; KEY[3]   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]    ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ADC_SDO  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
 +----------+--------------+-----------------+-----------------+
 
 
@@ -500,23 +504,14 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.257 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.257 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.5e-07 V                    ; 3.14 V              ; -0.195 V            ; 0.158 V                              ; 0.394 V                              ; 4.46e-10 s                  ; 1.64e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.5e-07 V                   ; 3.14 V             ; -0.195 V           ; 0.158 V                             ; 0.394 V                             ; 4.46e-10 s                 ; 1.64e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.62e-07 V                   ; 3.1 V               ; -0.153 V            ; 0.035 V                              ; 0.31 V                               ; 4.23e-10 s                  ; 1.59e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.62e-07 V                  ; 3.1 V              ; -0.153 V           ; 0.035 V                             ; 0.31 V                              ; 4.23e-10 s                 ; 1.59e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.35e-07 V                   ; 3.14 V              ; -0.258 V            ; 0.13 V                               ; 0.399 V                              ; 4.27e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 3.35e-07 V                  ; 3.14 V             ; -0.258 V           ; 0.13 V                              ; 0.399 V                             ; 4.27e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 
 
@@ -560,23 +555,14 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.136 V            ; 0.025 V                              ; 0.167 V                              ; 4.92e-10 s                  ; 3.12e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.136 V           ; 0.025 V                             ; 0.167 V                             ; 4.92e-10 s                 ; 3.12e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.32e-05 V                   ; 3.09 V              ; -0.11 V             ; 0.031 V                              ; 0.155 V                              ; 5.43e-10 s                  ; 3.14e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.32e-05 V                  ; 3.09 V             ; -0.11 V            ; 0.031 V                             ; 0.155 V                             ; 5.43e-10 s                 ; 3.14e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.61e-05 V                   ; 3.09 V              ; -0.0638 V           ; 0.034 V                              ; 0.099 V                              ; 5.12e-10 s                  ; 2.97e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.61e-05 V                  ; 3.09 V             ; -0.0638 V          ; 0.034 V                             ; 0.099 V                             ; 5.12e-10 s                 ; 2.97e-10 s                 ; Yes                       ; Yes                       ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.19e-05 V                   ; 3.1 V               ; -0.133 V            ; 0.025 V                              ; 0.169 V                              ; 4.92e-10 s                  ; 3.13e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 3.19e-05 V                  ; 3.1 V              ; -0.133 V           ; 0.025 V                             ; 0.169 V                             ; 4.92e-10 s                 ; 3.13e-10 s                 ; Yes                       ; No                        ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 
 
@@ -620,23 +606,14 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.621 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.621 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.94e-06 V                   ; 3.69 V              ; -0.414 V            ; 0.134 V                              ; 0.585 V                              ; 4.19e-10 s                  ; 1.53e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.94e-06 V                  ; 3.69 V             ; -0.414 V           ; 0.134 V                             ; 0.585 V                             ; 4.19e-10 s                 ; 1.53e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 3.63e-06 V                   ; 3.64 V              ; -0.326 V            ; 0.091 V                              ; 0.479 V                              ; 3.83e-10 s                  ; 1.5e-10 s                   ; Yes                        ; No                         ; 3.63 V                      ; 3.63e-06 V                  ; 3.64 V             ; -0.326 V           ; 0.091 V                             ; 0.479 V                             ; 3.83e-10 s                 ; 1.5e-10 s                  ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 4.72e-06 V                   ; 3.7 V               ; -0.49 V             ; 0.117 V                              ; 0.622 V                              ; 3.84e-10 s                  ; 1.48e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 4.72e-06 V                  ; 3.7 V              ; -0.49 V            ; 0.117 V                             ; 0.622 V                             ; 3.84e-10 s                 ; 1.48e-10 s                 ; Yes                       ; No                        ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 
 
@@ -680,59 +657,52 @@ No synchronizer chains to report.
 ; HEX4[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
 ; HEX4[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX5[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX5[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; HEX5[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.319 V            ; 0.041 V                              ; 0.528 V                              ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.319 V           ; 0.041 V                             ; 0.528 V                             ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; HEX5[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; HEX5[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
-; LEDR[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[2] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[3] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[4] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[5] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
-; LEDR[6] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[7] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[8] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
-; LEDR[9] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; DAC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; DAC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; DAC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; DAC_LD  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
+; ADC_SDI ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000238 V                   ; 3.64 V              ; -0.254 V            ; 0.052 V                              ; 0.543 V                              ; 4.59e-10 s                  ; 1.96e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000238 V                  ; 3.64 V             ; -0.254 V           ; 0.052 V                             ; 0.543 V                             ; 4.59e-10 s                 ; 1.96e-10 s                 ; Yes                       ; No                        ;
+; ADC_SCK ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; ADC_CS  ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000184 V                   ; 3.64 V              ; -0.19 V             ; 0.019 V                              ; 0.425 V                              ; 4.44e-10 s                  ; 1.91e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000184 V                  ; 3.64 V             ; -0.19 V            ; 0.019 V                             ; 0.425 V                             ; 4.44e-10 s                 ; 1.91e-10 s                 ; Yes                       ; No                        ;
+; PWM_OUT ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.63 V                       ; 0.000229 V                   ; 3.65 V              ; -0.316 V            ; 0.041 V                              ; 0.53 V                               ; 4.29e-10 s                  ; 1.87e-10 s                  ; Yes                        ; No                         ; 3.63 V                      ; 0.000229 V                  ; 3.65 V             ; -0.316 V           ; 0.041 V                             ; 0.53 V                              ; 4.29e-10 s                 ; 1.87e-10 s                 ; Yes                       ; No                        ;
 +---------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------+
-; Setup Transfers                                                                                                       ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 574      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; CLOCK_50                            ; 13       ; 13       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_2500:TICK1|CLK_OUT             ; 9        ; 9        ; 0        ; 0        ;
-; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; 9        ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_2500:TICK1|CLK_OUT             ; 10       ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 26       ; 9        ; 0        ; 0        ;
-; tick_2500:TICK1|CLK_OUT             ; tick_50000:TICK0|CLK_OUT            ; 20       ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 605      ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
++-------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                 ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; From Clock               ; To Clock                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; CLOCK_50                 ; CLOCK_50                 ; 579      ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|adc_cs   ; CLOCK_50                 ; 517      ; 21       ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 219      ; 1        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; CLOCK_50                 ; 5        ; 1        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|adc_cs   ; spi2adc:SPI_ADC|adc_cs   ; 110      ; 0        ; 0        ; 0        ;
+; CLOCK_50                 ; spi2adc:SPI_ADC|clk_1MHz ; 3        ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|adc_cs   ; spi2adc:SPI_ADC|clk_1MHz ; 0        ; 0        ; 10       ; 10       ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; 56       ; 10       ; 10       ; 9        ;
+; CLOCK_50                 ; spi2dac:SPI_DAC|clk_1MHz ; 26       ; 0        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; 65       ; 0        ; 0        ; 0        ;
++--------------------------+--------------------------+----------+----------+----------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
 
 
-+-----------------------------------------------------------------------------------------------------------------------+
-; Hold Transfers                                                                                                        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; From Clock                          ; To Clock                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
-; CLOCK_50                            ; CLOCK_50                            ; 574      ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; CLOCK_50                            ; 13       ; 13       ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; 1        ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_2500:TICK1|CLK_OUT             ; 9        ; 9        ; 0        ; 0        ;
-; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; 9        ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_2500:TICK1|CLK_OUT             ; 10       ; 0        ; 0        ; 0        ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; tick_50000:TICK0|CLK_OUT            ; 26       ; 9        ; 0        ; 0        ;
-; tick_2500:TICK1|CLK_OUT             ; tick_50000:TICK0|CLK_OUT            ; 20       ; 0        ; 0        ; 0        ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; 605      ; 0        ; 0        ; 0        ;
-+-------------------------------------+-------------------------------------+----------+----------+----------+----------+
++-------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                  ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; From Clock               ; To Clock                 ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++--------------------------+--------------------------+----------+----------+----------+----------+
+; CLOCK_50                 ; CLOCK_50                 ; 579      ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|adc_cs   ; CLOCK_50                 ; 517      ; 21       ; 0        ; 0        ;
+; spi2adc:SPI_ADC|clk_1MHz ; CLOCK_50                 ; 219      ; 1        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; CLOCK_50                 ; 5        ; 1        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|adc_cs   ; spi2adc:SPI_ADC|adc_cs   ; 110      ; 0        ; 0        ; 0        ;
+; CLOCK_50                 ; spi2adc:SPI_ADC|clk_1MHz ; 3        ; 0        ; 0        ; 0        ;
+; spi2adc:SPI_ADC|adc_cs   ; spi2adc:SPI_ADC|clk_1MHz ; 0        ; 0        ; 10       ; 10       ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; 56       ; 10       ; 10       ; 9        ;
+; CLOCK_50                 ; spi2dac:SPI_DAC|clk_1MHz ; 26       ; 0        ; 0        ; 0        ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; 65       ; 0        ; 0        ; 0        ;
++--------------------------+--------------------------+----------+----------+----------+----------+
 Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
 
 
@@ -755,23 +725,23 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +---------------------------------+-------+------+
 ; Illegal Clocks                  ; 0     ; 0    ;
 ; Unconstrained Clocks            ; 0     ; 0    ;
-; Unconstrained Input Ports       ; 2     ; 2    ;
-; Unconstrained Input Port Paths  ; 20    ; 20   ;
-; Unconstrained Output Ports      ; 45    ; 45   ;
-; Unconstrained Output Port Paths ; 500   ; 500  ;
+; Unconstrained Input Ports       ; 10    ; 10   ;
+; Unconstrained Input Port Paths  ; 586   ; 586  ;
+; Unconstrained Output Ports      ; 33    ; 33   ;
+; Unconstrained Output Port Paths ; 235   ; 235  ;
 +---------------------------------+-------+------+
 
 
-+------------------------------------------------------------------------------------------------+
-; Clock Status Summary                                                                           ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; Target                              ; Clock                               ; Type ; Status      ;
-+-------------------------------------+-------------------------------------+------+-------------+
-; CLOCK_50                            ; CLOCK_50                            ; Base ; Constrained ;
-; formula_fsm:FSM|state.LIGHT_UP_LEDS ; formula_fsm:FSM|state.LIGHT_UP_LEDS ; Base ; Constrained ;
-; tick_2500:TICK1|CLK_OUT             ; tick_2500:TICK1|CLK_OUT             ; Base ; Constrained ;
-; tick_50000:TICK0|CLK_OUT            ; tick_50000:TICK0|CLK_OUT            ; Base ; Constrained ;
-+-------------------------------------+-------------------------------------+------+-------------+
++--------------------------------------------------------------------------+
+; Clock Status Summary                                                     ;
++--------------------------+--------------------------+------+-------------+
+; Target                   ; Clock                    ; Type ; Status      ;
++--------------------------+--------------------------+------+-------------+
+; CLOCK_50                 ; CLOCK_50                 ; Base ; Constrained ;
+; spi2adc:SPI_ADC|adc_cs   ; spi2adc:SPI_ADC|adc_cs   ; Base ; Constrained ;
+; spi2adc:SPI_ADC|clk_1MHz ; spi2adc:SPI_ADC|clk_1MHz ; Base ; Constrained ;
+; spi2dac:SPI_DAC|clk_1MHz ; spi2dac:SPI_DAC|clk_1MHz ; Base ; Constrained ;
++--------------------------+--------------------------+------+-------------+
 
 
 +---------------------------------------------------------------------------------------------------+
@@ -779,8 +749,16 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +------------+--------------------------------------------------------------------------------------+
 ; Input Port ; Comment                                                                              ;
 +------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +------------+--------------------------------------------------------------------------------------+
 
 
@@ -789,6 +767,13 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +-------------+---------------------------------------------------------------------------------------+
 ; Output Port ; Comment                                                                               ;
 +-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -811,29 +796,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +-------------+---------------------------------------------------------------------------------------+
 
 
@@ -842,8 +808,16 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +------------+--------------------------------------------------------------------------------------+
 ; Input Port ; Comment                                                                              ;
 +------------+--------------------------------------------------------------------------------------+
-; KEY[0]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDO    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[0]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8]      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +------------+--------------------------------------------------------------------------------------+
 
 
@@ -852,6 +826,13 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 +-------------+---------------------------------------------------------------------------------------+
 ; Output Port ; Comment                                                                               ;
 +-------------+---------------------------------------------------------------------------------------+
+; ADC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; ADC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_CS      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_LD      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SCK     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; DAC_SDI     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX0[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
@@ -874,29 +855,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 ; HEX2[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX2[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 ; HEX3[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX4[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[0]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[1]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[2]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[3]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[4]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[5]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[6]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[7]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[8]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; LEDR[9]     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; PWM_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
 +-------------+---------------------------------------------------------------------------------------+
 
 
@@ -906,141 +868,148 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime TimeQuest Timing Analyzer
     Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition
-    Info: Processing started: Fri Nov 25 11:28:02 2016
-Info: Command: quartus_sta ex9 -c ex9
+    Info: Processing started: Tue Dec 06 09:47:20 2016
+Info: Command: quartus_sta ex19 -c ex19
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
-Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex9.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ex19.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
 Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
 Info (332105): Deriving Clocks
-    Info (332105): create_clock -period 1.000 -name tick_50000:TICK0|CLK_OUT tick_50000:TICK0|CLK_OUT
     Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
-    Info (332105): create_clock -period 1.000 -name tick_2500:TICK1|CLK_OUT tick_2500:TICK1|CLK_OUT
-    Info (332105): create_clock -period 1.000 -name formula_fsm:FSM|state.LIGHT_UP_LEDS formula_fsm:FSM|state.LIGHT_UP_LEDS
+    Info (332105): create_clock -period 1.000 -name spi2adc:SPI_ADC|clk_1MHz spi2adc:SPI_ADC|clk_1MHz
+    Info (332105): create_clock -period 1.000 -name spi2adc:SPI_ADC|adc_cs spi2adc:SPI_ADC|adc_cs
+    Info (332105): create_clock -period 1.000 -name spi2dac:SPI_DAC|clk_1MHz spi2dac:SPI_DAC|clk_1MHz
 Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
 Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
 Info: Analyzing Slow 1100mV 85C Model
 Critical Warning (332148): Timing requirements not met
     Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -4.063
+Info (332146): Worst-case setup slack is -5.675
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -4.063             -92.490 CLOCK_50 
-    Info (332119):    -3.170            -100.678 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -1.647             -14.530 tick_2500:TICK1|CLK_OUT 
-    Info (332119):    -1.569              -1.569 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -2.594
+    Info (332119):    -5.675           -1310.496 CLOCK_50 
+    Info (332119):    -3.850             -67.920 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -3.352             -52.261 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -2.060             -28.823 spi2adc:SPI_ADC|adc_cs 
+Info (332146): Worst-case hold slack is 0.121
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -2.594              -2.594 CLOCK_50 
-    Info (332119):     0.279               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.351               0.000 tick_2500:TICK1|CLK_OUT 
-    Info (332119):     0.556               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):     0.121               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.225               0.000 CLOCK_50 
+    Info (332119):     0.438               0.000 spi2adc:SPI_ADC|adc_cs 
+    Info (332119):     0.767               0.000 spi2dac:SPI_DAC|clk_1MHz 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.746
+Info (332146): Worst-case minimum pulse width slack is -2.174
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.746             -27.464 CLOCK_50 
-    Info (332119):    -0.394             -24.429 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.394              -5.270 tick_2500:TICK1|CLK_OUT 
-    Info (332119):     0.461               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -2.174           -1208.848 CLOCK_50 
+    Info (332119):    -0.394             -16.455 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.394             -13.115 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -0.394              -8.336 spi2adc:SPI_ADC|adc_cs 
+Info (332114): Report Metastability: Found 9 synchronizer chains.
+    Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
 Info: Analyzing Slow 1100mV 0C Model
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
 Critical Warning (332148): Timing requirements not met
     Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.620
+Info (332146): Worst-case setup slack is -5.268
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -3.620             -88.501 CLOCK_50 
-    Info (332119):    -3.082             -96.216 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -1.680             -14.714 tick_2500:TICK1|CLK_OUT 
-    Info (332119):    -1.485              -1.485 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -2.768
+    Info (332119):    -5.268           -1146.977 CLOCK_50 
+    Info (332119):    -3.985             -70.248 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -3.474             -50.644 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -2.136             -29.447 spi2adc:SPI_ADC|adc_cs 
+Info (332146): Worst-case hold slack is 0.113
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -2.768              -2.768 CLOCK_50 
-    Info (332119):     0.282               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.351               0.000 tick_2500:TICK1|CLK_OUT 
-    Info (332119):     0.430               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):     0.113               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.216               0.000 CLOCK_50 
+    Info (332119):     0.451               0.000 spi2adc:SPI_ADC|adc_cs 
+    Info (332119):     0.729               0.000 spi2dac:SPI_DAC|clk_1MHz 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.788
+Info (332146): Worst-case minimum pulse width slack is -2.174
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.788             -25.568 CLOCK_50 
-    Info (332119):    -0.394             -24.417 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.394              -5.220 tick_2500:TICK1|CLK_OUT 
-    Info (332119):     0.471               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -2.174           -1202.219 CLOCK_50 
+    Info (332119):    -0.394             -16.947 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.394             -13.226 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -0.394              -8.192 spi2adc:SPI_ADC|adc_cs 
+Info (332114): Report Metastability: Found 9 synchronizer chains.
+    Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
 Info: Analyzing Fast 1100mV 85C Model
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
 Critical Warning (332148): Timing requirements not met
     Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -3.305
+Info (332146): Worst-case setup slack is -3.917
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -3.305             -54.566 CLOCK_50 
-    Info (332119):    -1.630             -50.049 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -1.087              -9.482 tick_2500:TICK1|CLK_OUT 
-    Info (332119):    -0.488              -0.488 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -1.523
+    Info (332119):    -3.917            -921.485 CLOCK_50 
+    Info (332119):    -1.773             -30.272 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -1.528             -26.809 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.942             -13.341 spi2adc:SPI_ADC|adc_cs 
+Info (332146): Worst-case hold slack is 0.084
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -1.523              -1.523 CLOCK_50 
-    Info (332119):    -0.071              -0.328 tick_2500:TICK1|CLK_OUT 
-    Info (332119):     0.094               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.134               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):     0.084               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.130               0.000 CLOCK_50 
+    Info (332119):     0.162               0.000 spi2adc:SPI_ADC|adc_cs 
+    Info (332119):     0.345               0.000 spi2dac:SPI_DAC|clk_1MHz 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.856
+Info (332146): Worst-case minimum pulse width slack is -2.174
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.856             -19.710 CLOCK_50 
-    Info (332119):     0.062               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.127               0.000 tick_2500:TICK1|CLK_OUT 
-    Info (332119):     0.480               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -2.174           -1213.382 CLOCK_50 
+    Info (332119):     0.033               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.054               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     0.156               0.000 spi2adc:SPI_ADC|adc_cs 
+Info (332114): Report Metastability: Found 9 synchronizer chains.
+    Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
 Info: Analyzing Fast 1100mV 0C Model
 Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
 Critical Warning (332148): Timing requirements not met
     Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -2.694
+Info (332146): Worst-case setup slack is -3.277
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -2.694             -44.892 CLOCK_50 
-    Info (332119):    -1.427             -42.012 tick_50000:TICK0|CLK_OUT 
-    Info (332119):    -0.980              -8.435 tick_2500:TICK1|CLK_OUT 
-    Info (332119):    -0.386              -0.386 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-Info (332146): Worst-case hold slack is -1.553
+    Info (332119):    -3.277            -712.908 CLOCK_50 
+    Info (332119):    -1.708             -28.858 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):    -1.479             -23.942 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):    -0.834             -11.645 spi2adc:SPI_ADC|adc_cs 
+Info (332146): Worst-case hold slack is 0.104
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -1.553              -1.553 CLOCK_50 
-    Info (332119):    -0.102              -0.665 tick_2500:TICK1|CLK_OUT 
-    Info (332119):     0.064               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
-    Info (332119):     0.081               0.000 tick_50000:TICK0|CLK_OUT 
+    Info (332119):     0.104               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.123               0.000 CLOCK_50 
+    Info (332119):     0.149               0.000 spi2adc:SPI_ADC|adc_cs 
+    Info (332119):     0.314               0.000 spi2dac:SPI_DAC|clk_1MHz 
 Info (332140): No Recovery paths to report
 Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -0.880
+Info (332146): Worst-case minimum pulse width slack is -2.174
     Info (332119):     Slack       End Point TNS Clock 
     Info (332119): ========= =================== =====================
-    Info (332119):    -0.880             -23.155 CLOCK_50 
-    Info (332119):     0.079               0.000 tick_50000:TICK0|CLK_OUT 
-    Info (332119):     0.135               0.000 tick_2500:TICK1|CLK_OUT 
-    Info (332119):     0.483               0.000 formula_fsm:FSM|state.LIGHT_UP_LEDS 
+    Info (332119):    -2.174           -1236.838 CLOCK_50 
+    Info (332119):     0.062               0.000 spi2adc:SPI_ADC|clk_1MHz 
+    Info (332119):     0.076               0.000 spi2dac:SPI_DAC|clk_1MHz 
+    Info (332119):     0.161               0.000 spi2adc:SPI_ADC|adc_cs 
+Info (332114): Report Metastability: Found 9 synchronizer chains.
+    Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
-    Info: Peak virtual memory: 1211 megabytes
-    Info: Processing ended: Fri Nov 25 11:28:08 2016
+Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
+    Info: Peak virtual memory: 1237 megabytes
+    Info: Processing ended: Tue Dec 06 09:47:26 2016
     Info: Elapsed time: 00:00:06
-    Info: Total CPU time (on all processors): 00:00:06
+    Info: Total CPU time (on all processors): 00:00:07
 
 
diff --git a/part_4/ex19/output_files/ex19.sta.summary b/part_4/ex19/output_files/ex19.sta.summary
new file mode 100755
index 0000000..57dc001
--- /dev/null
+++ b/part_4/ex19/output_files/ex19.sta.summary
@@ -0,0 +1,197 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -5.675
+TNS   : -1310.496
+
+Type  : Slow 1100mV 85C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -3.850
+TNS   : -67.920
+
+Type  : Slow 1100mV 85C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -3.352
+TNS   : -52.261
+
+Type  : Slow 1100mV 85C Model Setup 'spi2adc:SPI_ADC|adc_cs'
+Slack : -2.060
+TNS   : -28.823
+
+Type  : Slow 1100mV 85C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.121
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.225
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'spi2adc:SPI_ADC|adc_cs'
+Slack : 0.438
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.767
+TNS   : 0.000
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1208.848
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -0.394
+TNS   : -16.455
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -0.394
+TNS   : -13.115
+
+Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|adc_cs'
+Slack : -0.394
+TNS   : -8.336
+
+Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -5.268
+TNS   : -1146.977
+
+Type  : Slow 1100mV 0C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -3.985
+TNS   : -70.248
+
+Type  : Slow 1100mV 0C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -3.474
+TNS   : -50.644
+
+Type  : Slow 1100mV 0C Model Setup 'spi2adc:SPI_ADC|adc_cs'
+Slack : -2.136
+TNS   : -29.447
+
+Type  : Slow 1100mV 0C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.113
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.216
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'spi2adc:SPI_ADC|adc_cs'
+Slack : 0.451
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.729
+TNS   : 0.000
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1202.219
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -0.394
+TNS   : -16.947
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -0.394
+TNS   : -13.226
+
+Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|adc_cs'
+Slack : -0.394
+TNS   : -8.192
+
+Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
+Slack : -3.917
+TNS   : -921.485
+
+Type  : Fast 1100mV 85C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -1.773
+TNS   : -30.272
+
+Type  : Fast 1100mV 85C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -1.528
+TNS   : -26.809
+
+Type  : Fast 1100mV 85C Model Setup 'spi2adc:SPI_ADC|adc_cs'
+Slack : -0.942
+TNS   : -13.341
+
+Type  : Fast 1100mV 85C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.084
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
+Slack : 0.130
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'spi2adc:SPI_ADC|adc_cs'
+Slack : 0.162
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.345
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1213.382
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.033
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.054
+TNS   : 0.000
+
+Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spi2adc:SPI_ADC|adc_cs'
+Slack : 0.156
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
+Slack : -3.277
+TNS   : -712.908
+
+Type  : Fast 1100mV 0C Model Setup 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : -1.708
+TNS   : -28.858
+
+Type  : Fast 1100mV 0C Model Setup 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : -1.479
+TNS   : -23.942
+
+Type  : Fast 1100mV 0C Model Setup 'spi2adc:SPI_ADC|adc_cs'
+Slack : -0.834
+TNS   : -11.645
+
+Type  : Fast 1100mV 0C Model Hold 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.104
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
+Slack : 0.123
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'spi2adc:SPI_ADC|adc_cs'
+Slack : 0.149
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Hold 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.314
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -2.174
+TNS   : -1236.838
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|clk_1MHz'
+Slack : 0.062
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2dac:SPI_DAC|clk_1MHz'
+Slack : 0.076
+TNS   : 0.000
+
+Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spi2adc:SPI_ADC|adc_cs'
+Slack : 0.161
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/part_4/ex19/output_files/greybox_tmp/cbx_args.txt b/part_4/ex19/output_files/greybox_tmp/cbx_args.txt
new file mode 100755
index 0000000..dc67ebe
--- /dev/null
+++ b/part_4/ex19/output_files/greybox_tmp/cbx_args.txt
@@ -0,0 +1,29 @@
+ADDRESS_ACLR_B=NONE
+ADDRESS_REG_B=CLOCK0
+CLOCK_ENABLE_INPUT_A=BYPASS
+CLOCK_ENABLE_INPUT_B=BYPASS
+CLOCK_ENABLE_OUTPUT_B=BYPASS
+INTENDED_DEVICE_FAMILY="Cyclone V"
+LPM_TYPE=altsyncram
+NUMWORDS_A=8192
+NUMWORDS_B=8192
+OPERATION_MODE=DUAL_PORT
+OUTDATA_ACLR_B=NONE
+OUTDATA_REG_B=CLOCK0
+POWER_UP_UNINITIALIZED=FALSE
+RAM_BLOCK_TYPE=M10K
+RDCONTROL_REG_B=CLOCK0
+READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
+WIDTHAD_A=13
+WIDTHAD_B=13
+WIDTH_A=9
+WIDTH_B=9
+WIDTH_BYTEENA_A=1
+DEVICE_FAMILY="Cyclone V"
+address_a
+address_b
+clock0
+data_a
+rden_b
+wren_a
+q_b
diff --git a/part_4/ex19/verilog_files/add3_ge5.v b/part_4/ex19/verilog_files/add3_ge5.v
new file mode 100755
index 0000000..0daf78a
--- /dev/null
+++ b/part_4/ex19/verilog_files/add3_ge5.v
@@ -0,0 +1,31 @@
+//------------------------------
+// Module name: add3_ge5
+// Function: Add 3 to input if it is 5 or above
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     21 Jan 2014
+//------------------------------
+
+module add3_ge5(w,a); 
+	input [3:0] w; 
+	output [3:0] a; 
+	reg [3:0] a; 
+ 
+	always @ (w) 
+		case (w) 
+			4'b0000: a <= 4'b0000; 
+			4'b0001: a <= 4'b0001; 
+			4'b0010: a <= 4'b0010; 
+			4'b0011: a <= 4'b0011; 
+			4'b0100: a <= 4'b0100; 
+			4'b0101: a <= 4'b1000; 
+			4'b0110: a <= 4'b1001; 
+			4'b0111: a <= 4'b1010; 
+			4'b1000: a <= 4'b1011; 
+			4'b1001: a <= 4'b1100;
+			4'b1010: a <= 4'b1101;	
+			4'b1011: a <= 4'b1110;	
+			4'b1100: a <= 4'b1111;	
+			default: a <= 4'b0000; // a cannot be 13 or larger, else overflow
+		endcase 
+endmodule 
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/bin2bcd_16.v b/part_4/ex19/verilog_files/bin2bcd_16.v
new file mode 100755
index 0000000..b25d0bd
--- /dev/null
+++ b/part_4/ex19/verilog_files/bin2bcd_16.v
@@ -0,0 +1,109 @@
+//------------------------------
+// Module name: bin2bcd_16
+// Function: Converts a 16-bit binary number to 5 digits BCD
+//            .... it uses a shift-and-add3 algorithm
+// Creator:  Peter Cheung
+// Version:  2.0  (Correct mistake - problem with numbers 0x5000 or larger)
+// Date:     24 Nov 2016
+//------------------------------
+//   For more explanation of how this work, see 
+//     ... instructions on wwww.ee.ic.ac.uk/pcheung/teaching/E2_experiment
+
+module bin2bcd_16 (B, BCD_0, BCD_1, BCD_2, BCD_3, BCD_4);
+
+	input [15:0]	B;		// binary input number
+	output [3:0]	BCD_0, BCD_1, BCD_2, BCD_3, BCD_4;   // BCD digit LSD to MSD
+	
+	wire [3:0]	w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
+	wire [3:0]	w14,w15,w16,w17,w18,w19,w20,w21,w22,w23,w24,w25;
+	wire [3:0]	w26,w27,w28,w29,w30,w31,w32,w33,w34,w35;
+	wire [3:0]	a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13;
+	wire [3:0]	a14,a15,a16,a17,a18,a19,a20,a21,a22,a23,a24,a25;
+	wire [3:0]	a26,a27,a28,a29,a30,a31,a32,a33,a34,a35;
+
+	// Instantiate a tree of add3-if-greater than or equal to 5 cells
+	//  ... input is w_n, and output is a_n
+	add3_ge5 A1 (w1,a1);
+	add3_ge5 A2 (w2,a2);
+	add3_ge5 A3 (w3,a3);
+	add3_ge5 A4 (w4,a4);
+	add3_ge5 A5 (w5,a5);
+	add3_ge5 A6 (w6,a6);
+	add3_ge5 A7 (w7,a7);
+	add3_ge5 A8 (w8,a8);
+	add3_ge5 A9 (w9,a9);
+	add3_ge5 A10 (w10,a10);
+	add3_ge5 A11 (w11,a11);
+	add3_ge5 A12 (w12,a12);
+	add3_ge5 A13 (w13,a13);
+	add3_ge5 A14 (w14,a14);
+	add3_ge5 A15 (w15,a15);
+	add3_ge5 A16 (w16,a16);
+	add3_ge5 A17 (w17,a17);
+	add3_ge5 A18 (w18,a18);
+	add3_ge5 A19 (w19,a19);
+	add3_ge5 A20 (w20,a20);
+	add3_ge5 A21 (w21,a21);
+	add3_ge5 A22 (w22,a22);
+	add3_ge5 A23 (w23,a23);
+	add3_ge5 A24 (w24,a24);
+	add3_ge5 A25 (w25,a25);
+	add3_ge5 A26 (w26,a26);
+	add3_ge5 A27 (w27,a27);
+	add3_ge5 A28 (w28,a28);
+	add3_ge5 A29 (w29,a29);
+	add3_ge5 A30 (w30,a30);
+	add3_ge5 A31 (w31,a31);
+	add3_ge5 A32 (w32,a32);
+	add3_ge5 A33 (w33,a33);
+	add3_ge5 A34 (w34,a34);
+	add3_ge5 A35 (w35,a35);
+		
+	// wire the tree of add3 modules together
+	assign  w1 = {1'b0,B[15:13]};		// w_n is the input port to module a_n
+	assign  w2 = {a1[2:0], B[12]};		
+	assign  w3 = {a2[2:0], B[11]};		
+	assign  w4 = {1'b0,a1[3],a2[3],a3[3]};
+	assign  w5 = {a3[2:0], B[10]};
+	assign  w6 = {a4[2:0], a5[3]};
+	assign  w7 = {a5[2:0], B[9]};
+	assign  w8 = {a6[2:0], a7[3]};
+	assign  w9 = {a7[2:0], B[8]};
+	assign  w10 = {1'b0, a4[3], a6[3], a8[3]};
+	assign  w11 = {a8[2:0], a9[3]};
+	assign  w12 = {a9[2:0], B[7]};
+	assign  w13 = {a10[2:0], a11[3]};
+	assign  w14 = {a11[2:0], a12[3]};
+	assign  w15 = {a12[2:0], B[6]};
+	assign  w16 = {a13[2:0], a14[3]};
+	assign  w17 = {a14[2:0], a15[3]};
+	assign  w18 = {a15[2:0], B[5]};
+	assign  w19 = {1'b0, a10[3], a13[3], a16[3]};
+	assign  w20 = {a16[2:0], a17[3]};
+	assign  w21 = {a17[2:0], a18[3]};
+	assign  w22 = {a18[2:0], B[4]};
+	assign  w23 = {a19[2:0], a20[3]};
+	assign  w24 = {a20[2:0], a21[3]};
+	assign  w25 = {a21[2:0], a22[3]};
+	assign  w26 = {a22[2:0], B[3]};
+	assign  w27 = {a23[2:0], a24[3]};
+	assign  w28 = {a24[2:0], a25[3]};
+	assign  w29 = {a25[2:0], a26[3]};
+	assign  w30 = {a26[2:0], B[2]};
+	assign  w31 = {1'b0,a19[3], a23[3], a27[3]};
+	assign  w32 = {a27[2:0], a28[3]};
+	assign  w33 = {a28[2:0], a29[3]};
+	assign  w34 = {a29[2:0], a30[3]};
+	assign  w35 = {a30[2:0], B[1]};
+	
+	// connect up to four BCD digit outputs	
+	assign BCD_0 = {a35[2:0],B[0]};
+	assign BCD_1 = {a34[2:0],a35[3]};
+	assign BCD_2 = {a33[2:0],a34[3]};
+	assign BCD_3 = {a32[2:0],a33[3]};
+	assign BCD_4 = {a31[2:0],a32[3]};	
+endmodule
+
+	
+	
+
diff --git a/part_4/ex19/verilog_files/clktick_16.v b/part_4/ex19/verilog_files/clktick_16.v
new file mode 100755
index 0000000..e6b99eb
--- /dev/null
+++ b/part_4/ex19/verilog_files/clktick_16.v
@@ -0,0 +1,42 @@
+// Design Name : clktick_16
+// File Name : clktick.v
+// Function : divide an input clock signal by n+1
+//-----------------------------------------------------
+
+module clktick_16 (
+  clkin, 	// Clock input to the design
+  enable,	// enable clk divider
+  N,			// Clock division factor is N+1
+  tick		// pulse_out goes high for one cycle (n+1) clock cycles
+); 			// 	End of port list
+
+parameter	N_BIT = 16;
+//-------------Input Ports-----------------------------
+input clkin;
+input enable;
+input [N_BIT-1:0] N;
+
+//-------------Output Ports----------------------------
+output 	tick;
+
+//-------------Output Ports Data Type------------------
+// Output port can be a storage element (reg) or a wire
+reg [N_BIT-1:0] count;
+reg			tick;
+
+initial		tick = 1'b0;
+
+//------------ Main Body of the module ------------------------
+
+	always @ (posedge clkin)  
+		if (enable == 1'b1)
+			if (count == 0)	begin
+				tick <= 1'b1;
+				count <= N;
+				end
+			else	begin
+				tick <= 1'b0;
+				count <= count - 1'b1;
+				end
+		
+endmodule // End of Module clktick
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/ctr_13_bit.qip b/part_4/ex19/verilog_files/ctr_13_bit.qip
new file mode 100755
index 0000000..a8f7d83
--- /dev/null
+++ b/part_4/ex19/verilog_files/ctr_13_bit.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ctr_13_bit.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ctr_13_bit_bb.v"]
diff --git a/part_4/ex19/verilog_files/ctr_13_bit.v b/part_4/ex19/verilog_files/ctr_13_bit.v
new file mode 100755
index 0000000..3511037
--- /dev/null
+++ b/part_4/ex19/verilog_files/ctr_13_bit.v
@@ -0,0 +1,112 @@
+// megafunction wizard: %LPM_COUNTER%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_COUNTER 
+
+// ============================================================
+// File Name: ctr_13_bit.v
+// Megafunction Name(s):
+// 			LPM_COUNTER
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ctr_13_bit (
+	clock,
+	q);
+
+	input	  clock;
+	output	[12:0]  q;
+
+	wire [12:0] sub_wire0;
+	wire [12:0] q = sub_wire0[12:0];
+
+	lpm_counter	LPM_COUNTER_component (
+				.clock (clock),
+				.q (sub_wire0),
+				.aclr (1'b0),
+				.aload (1'b0),
+				.aset (1'b0),
+				.cin (1'b1),
+				.clk_en (1'b1),
+				.cnt_en (1'b1),
+				.cout (),
+				.data ({13{1'b0}}),
+				.eq (),
+				.sclr (1'b0),
+				.sload (1'b0),
+				.sset (1'b0),
+				.updown (1'b1));
+	defparam
+		LPM_COUNTER_component.lpm_direction = "UP",
+		LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
+		LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
+		LPM_COUNTER_component.lpm_width = 13;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACLR NUMERIC "0"
+// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+// Retrieval info: PRIVATE: ASET NUMERIC "0"
+// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+// Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Direction NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
+// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
+// Retrieval info: PRIVATE: SCLR NUMERIC "0"
+// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+// Retrieval info: PRIVATE: SSET NUMERIC "0"
+// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: nBit NUMERIC "13"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
+// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "13"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_4/ex19/verilog_files/ctr_13_bit_bb.v b/part_4/ex19/verilog_files/ctr_13_bit_bb.v
new file mode 100755
index 0000000..908f22d
--- /dev/null
+++ b/part_4/ex19/verilog_files/ctr_13_bit_bb.v
@@ -0,0 +1,81 @@
+// megafunction wizard: %LPM_COUNTER%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_COUNTER 
+
+// ============================================================
+// File Name: ctr_13_bit.v
+// Megafunction Name(s):
+// 			LPM_COUNTER
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module ctr_13_bit (
+	clock,
+	q);
+
+	input	  clock;
+	output	[12:0]  q;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACLR NUMERIC "0"
+// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+// Retrieval info: PRIVATE: ASET NUMERIC "0"
+// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+// Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Direction NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
+// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
+// Retrieval info: PRIVATE: SCLR NUMERIC "0"
+// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+// Retrieval info: PRIVATE: SSET NUMERIC "0"
+// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: nBit NUMERIC "13"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
+// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "13"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_4/ex19/verilog_files/d_ff.v b/part_4/ex19/verilog_files/d_ff.v
new file mode 100755
index 0000000..65aec4d
--- /dev/null
+++ b/part_4/ex19/verilog_files/d_ff.v
@@ -0,0 +1,11 @@
+module d_ff(clk, in, out);
+
+	input clk, in;
+	output out;
+	wire in;
+	reg out;
+
+	always @ (posedge clk)
+		out <= in;
+
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/d_ff.v.bak b/part_4/ex19/verilog_files/d_ff.v.bak
new file mode 100755
index 0000000..1463387
--- /dev/null
+++ b/part_4/ex19/verilog_files/d_ff.v.bak
@@ -0,0 +1,6 @@
+module d_ff(clk, in, out);
+
+	always @ (posedge clk)
+		in <= out;
+
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/delay_block.qip b/part_4/ex19/verilog_files/delay_block.qip
new file mode 100755
index 0000000..d9a8dd8
--- /dev/null
+++ b/part_4/ex19/verilog_files/delay_block.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "16.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "delay_block.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "delay_block_bb.v"]
diff --git a/part_4/ex19/verilog_files/delay_block.v b/part_4/ex19/verilog_files/delay_block.v
new file mode 100755
index 0000000..1e87a99
--- /dev/null
+++ b/part_4/ex19/verilog_files/delay_block.v
@@ -0,0 +1,223 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: delay_block.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module delay_block (
+	clock,
+	data,
+	rdaddress,
+	rden,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[8:0]  data;
+	input	[12:0]  rdaddress;
+	input	  rden;
+	input	[12:0]  wraddress;
+	input	  wren;
+	output	[8:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [8:0] sub_wire0;
+	wire [8:0] q = sub_wire0[8:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.address_b (rdaddress),
+				.clock0 (clock),
+				.data_a (data),
+				.rden_b (rden),
+				.wren_a (wren),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({9{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone V",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 8192,
+		altsyncram_component.numwords_b = 8192,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "CLOCK0",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.ram_block_type = "M10K",
+		altsyncram_component.rdcontrol_reg_b = "CLOCK0",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 13,
+		altsyncram_component.widthad_b = 13,
+		altsyncram_component.width_a = 9,
+		altsyncram_component.width_b = 9,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
+// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
+// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
+// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex19/verilog_files/delay_block_bb.v b/part_4/ex19/verilog_files/delay_block_bb.v
new file mode 100755
index 0000000..d9bcc5c
--- /dev/null
+++ b/part_4/ex19/verilog_files/delay_block_bb.v
@@ -0,0 +1,167 @@
+// megafunction wizard: %RAM: 2-PORT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: delay_block.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module delay_block (
+	clock,
+	data,
+	rdaddress,
+	rden,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[8:0]  data;
+	input	[12:0]  rdaddress;
+	input	  rden;
+	input	[12:0]  wraddress;
+	input	  wren;
+	output	[8:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
+// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
+// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
+// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_block_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex19/verilog_files/delay_ram.v b/part_4/ex19/verilog_files/delay_ram.v
new file mode 100755
index 0000000..23d49af
--- /dev/null
+++ b/part_4/ex19/verilog_files/delay_ram.v
@@ -0,0 +1,220 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: delay_ram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module delay_ram (
+	clock,
+	data,
+	rdaddress,
+	rden,
+	wraddress,
+	wren,
+	q);
+
+	input	  clock;
+	input	[8:0]  data;
+	input	[12:0]  rdaddress;
+	input	  rden;
+	input	[12:0]  wraddress;
+	input	  wren;
+	output	[8:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+	tri0	  wren;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [8:0] sub_wire0;
+	wire [8:0] q = sub_wire0[8:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.rden_b (rden),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({9{1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 8192,
+		altsyncram_component.numwords_b = 8192,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "CLOCK0",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.rdcontrol_reg_b = "CLOCK0",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = 13,
+		altsyncram_component.widthad_b = 13,
+		altsyncram_component.width_a = 9,
+		altsyncram_component.width_b = 9,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "73728"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "9"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "9"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "9"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
+// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
+// Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
+// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+// Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
+// Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 9 0 data 0 0 9 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 9 0 @q_b 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL delay_ram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/part_4/ex19/verilog_files/div_by_2.v b/part_4/ex19/verilog_files/div_by_2.v
new file mode 100755
index 0000000..11b8e75
--- /dev/null
+++ b/part_4/ex19/verilog_files/div_by_2.v
@@ -0,0 +1,8 @@
+module div_by_2(in, out);
+
+	input signed [9:0] in;
+	output signed [9:0] out;
+	
+	assign out = in >>> 1;
+	
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/div_by_4.v.bak b/part_4/ex19/verilog_files/div_by_4.v.bak
new file mode 100755
index 0000000..8ceab41
--- /dev/null
+++ b/part_4/ex19/verilog_files/div_by_4.v.bak
@@ -0,0 +1,8 @@
+module div_by_4(in, out);
+
+	input in;
+	output out;
+	
+	assign out = in >> 2;
+	
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/echo_synth.v.bak b/part_4/ex19/verilog_files/echo_synth.v.bak
new file mode 100755
index 0000000..91d95dc
--- /dev/null
+++ b/part_4/ex19/verilog_files/echo_synth.v.bak
@@ -0,0 +1,27 @@
+module processor (sysclk, data_in, data_out);
+
+	input				sysclk;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	// This part should include your own processing hardware 
+	// ... that takes x to produce y
+	// ... In this case, it is ALL PASS.
+	assign y = x;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/hex_to_7seg.v b/part_4/ex19/verilog_files/hex_to_7seg.v
new file mode 100755
index 0000000..1c39f02
--- /dev/null
+++ b/part_4/ex19/verilog_files/hex_to_7seg.v
@@ -0,0 +1,38 @@
+//------------------------------
+// Module name: hex_to_7seg
+// Function: convert 4-bit hex value to drive 7 segment display
+//           output is low active - using case statement
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     23 Oct 2011
+//------------------------------
+
+module hex_to_7seg	(out,in);
+
+	output	[6:0]	out;    // low-active output to drive 7 segment display
+	input	[3:0]	in;		// 4-bit binary input of a hexademical number
+	
+	reg		[6:0]	out;	// make out a variable for use in procedural assignment
+	
+	always @ (in)
+	  case (in)
+		4'h0: out = 7'b1000000;
+		4'h1: out = 7'b1111001;		// -- 0 ---
+		4'h2: out = 7'b0100100; 	// |	  |
+		4'h3: out = 7'b0110000; 	// 5      1
+		4'h4: out = 7'b0011001; 	// |	  |
+		4'h5: out = 7'b0010010; 	// -- 6 ---
+		4'h6: out = 7'b0000010; 	// |	  |
+		4'h7: out = 7'b1111000; 	// 4      2
+		4'h8: out = 7'b0000000; 	// |	  |
+		4'h9: out = 7'b0011000; 	// -- 3 ---
+		4'ha: out = 7'b0001000;
+		4'hb: out = 7'b0000011;
+		4'hc: out = 7'b1000110;
+		4'hd: out = 7'b0100001;
+		4'he: out = 7'b0000110;
+		4'hf: out = 7'b0001110;
+	  endcase
+endmodule
+
+
diff --git a/part_4/ex19/verilog_files/mult.v b/part_4/ex19/verilog_files/mult.v
new file mode 100755
index 0000000..785990c
--- /dev/null
+++ b/part_4/ex19/verilog_files/mult.v
@@ -0,0 +1,13 @@
+module mult(in, out);
+
+	input signed [8:0] in;
+	parameter mult_num = 11'd1638;
+	
+	output signed [19:0] out;
+	
+	wire [8:0] in;
+	wire [19:0] out;
+	
+	assign out = mult_num * in;
+
+endmodule 
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/mult.v.bak b/part_4/ex19/verilog_files/mult.v.bak
new file mode 100755
index 0000000..dddfc0e
--- /dev/null
+++ b/part_4/ex19/verilog_files/mult.v.bak
@@ -0,0 +1,13 @@
+module mult(in, out);
+
+	input signed [8:0] in;
+	parameter mult_num = 11'd1638;
+	
+	output signed [19:0] out;
+	
+	wire [8:0] in;
+	wire [19:0] out;
+	
+	out = mult_num * in;
+
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/mult_echo_synth.v.bak b/part_4/ex19/verilog_files/mult_echo_synth.v.bak
new file mode 100755
index 0000000..d5507b5
--- /dev/null
+++ b/part_4/ex19/verilog_files/mult_echo_synth.v.bak
@@ -0,0 +1,34 @@
+module processor (sysclk, tick, data_in, data_out);
+
+	input				sysclk, tick;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+	wire [9:0]		tmp_data, echoed_data;
+	wire is_full, and_if, from_dff;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	FIFO fifo(sysclk, x, and_if, tick, is_full, tmp_data);
+	
+	d_ff d(tick, is_full, from_dff);
+	
+	assign and_if = tick & from_dff;
+	
+	div_by_2(tmp_data, echoed_data);
+		
+	assign y = x + echoed_data;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/multiply_k.v b/part_4/ex19/verilog_files/multiply_k.v
new file mode 100755
index 0000000..8292b58
--- /dev/null
+++ b/part_4/ex19/verilog_files/multiply_k.v
@@ -0,0 +1,107 @@
+// megafunction wizard: %LPM_MULT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: lpm_mult 
+
+// ============================================================
+// File Name: multiply_k.v
+// Megafunction Name(s):
+// 			lpm_mult
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module multiply_k (
+	dataa,
+	result);
+
+	input	[8:0]  dataa;
+	output	[19:0]  result;
+
+	wire [19:0] sub_wire0;
+	wire [10:0] sub_wire1 = 11'h666;
+	wire [19:0] result = sub_wire0[19:0];
+
+	lpm_mult	lpm_mult_component (
+				.dataa (dataa),
+				.datab (sub_wire1),
+				.result (sub_wire0),
+				.aclr (1'b0),
+				.clken (1'b1),
+				.clock (1'b0),
+				.sum (1'b0));
+	defparam
+		lpm_mult_component.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
+		lpm_mult_component.lpm_representation = "UNSIGNED",
+		lpm_mult_component.lpm_type = "LPM_MULT",
+		lpm_mult_component.lpm_widtha = 9,
+		lpm_mult_component.lpm_widthb = 11,
+		lpm_mult_component.lpm_widthp = 20;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
+// Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
+// Retrieval info: PRIVATE: ConstantB NUMERIC "1638"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+// Retrieval info: PRIVATE: Latency NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
+// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
+// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
+// Retrieval info: PRIVATE: WidthA NUMERIC "9"
+// Retrieval info: PRIVATE: WidthB NUMERIC "11"
+// Retrieval info: PRIVATE: WidthP NUMERIC "20"
+// Retrieval info: PRIVATE: aclr NUMERIC "0"
+// Retrieval info: PRIVATE: clken NUMERIC "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: PRIVATE: optimize NUMERIC "0"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
+// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
+// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "11"
+// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "20"
+// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
+// Retrieval info: USED_PORT: result 0 0 20 0 OUTPUT NODEFVAL "result[19..0]"
+// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
+// Retrieval info: CONNECT: @datab 0 0 11 0 1638 0 0 11 0
+// Retrieval info: CONNECT: result 0 0 20 0 @result 0 0 20 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL multiply_k_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm
diff --git a/part_4/ex19/verilog_files/pulse_gen.v b/part_4/ex19/verilog_files/pulse_gen.v
new file mode 100755
index 0000000..d82fe49
--- /dev/null
+++ b/part_4/ex19/verilog_files/pulse_gen.v
@@ -0,0 +1,43 @@
+//------------------------------
+// Module name: pulse_gen (Moore)
+// Function: Generate one clock pulse on +ve edge of input
+// Creator:  Peter Cheung
+// Version:  1.0
+// Date:     29 Jan 2014
+//------------------------------
+
+module pulse_gen(pulse, in, clk);
+
+	output 			pulse;	// output pulse lasting one clk cycle
+	input 			in;		// input, +ve edge to be detected
+	input 			clk;		// clock signal
+
+	reg [1:0]	state;
+	reg	pulse;
+	
+	parameter	IDLE = 2'b0;	// state coding for IDLE state
+	parameter	IN_HIGH = 2'b01;
+	parameter	WAIT_LOW = 2'b10;  
+	
+	initial state = IDLE;
+	
+	always @ (posedge clk) 
+		begin	
+			pulse <= 0;		 // default output
+			case (state)
+			IDLE: 	if (in == 1'b1) begin
+							state <= IN_HIGH;	pulse <= 1'b1; end
+						else 
+							state <= IDLE; 
+			IN_HIGH: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						else 
+							state <= IDLE; 
+			WAIT_LOW: if (in == 1'b1) 
+							state <= WAIT_LOW;
+						 else  
+							state <= IDLE;
+			default: ;
+			endcase
+		end			//... always
+endmodule
diff --git a/part_4/ex19/verilog_files/pwm.v b/part_4/ex19/verilog_files/pwm.v
new file mode 100755
index 0000000..c3b34d9
--- /dev/null
+++ b/part_4/ex19/verilog_files/pwm.v
@@ -0,0 +1,25 @@
+module pwm (clk, data_in, load, pwm_out);
+
+	input				clk;			// system clock
+	input [9:0] 	data_in;		// input data for conversion
+	input 			load;			// high pulse to load new data
+	output			pwm_out;		// PWM output
+
+	reg [9:0]		d;				// internal register
+	reg [9:0]		count;		// internal 10-bit counter
+	reg				pwm_out;
+
+	always @ (posedge clk)
+		if (load == 1'b1) d <= data_in;
+	
+	initial count = 10'b0;	
+	
+	always @ (posedge clk) begin
+		count <= count + 1'b1;
+		if (count > d)
+			pwm_out <= 1'b0;
+		else	
+			pwm_out <= 1'b1;
+		end
+
+endmodule
diff --git a/part_4/ex19/verilog_files/spi2adc.v b/part_4/ex19/verilog_files/spi2adc.v
new file mode 100755
index 0000000..3878f71
--- /dev/null
+++ b/part_4/ex19/verilog_files/spi2adc.v
@@ -0,0 +1,150 @@
+//------------------------------
+// Module name: spi2adc
+// Function: SPI interface for MCP3002 ADC
+// Creator:  Peter Cheung
+// Version:  1.1
+// Date:     24 Jan 2014
+//------------------------------
+
+module spi2adc (sysclk, start, channel, data_from_adc, data_valid, 
+						sdata_to_adc, adc_cs, adc_sck, sdata_from_adc);
+
+	input	sysclk;			// 50MHz system clock of DE0
+	input	start;			// Pulse to start ADC, minimum wide = clock period
+	input	channel;			// channel 0 or 1 to be converted
+	output [9:0] data_from_adc;	// 10-bit ADC result
+	output data_valid;	// High indicates that converted data valid
+	output sdata_to_adc;	// Serial commands send to adc chip
+	output adc_cs;			// chip select - low when converting
+	output adc_sck;		// SPI clock - active during conversion
+	input sdata_from_adc;	// Converted serial data from ADC, MSB first
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire	sysclk, start, sdata_from_adc;
+
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg [9:0]	data_from_adc;
+	reg			adc_cs;
+	wire			sdata_to_adc, adc_sck, data_valid;
+	
+//-------------Configuration parameters for ADC --------
+	parameter	SGL=1'b1;	// 0:diff i/p, 1:single-ended
+	parameter	MSBF=1'b1;	// 0:LSB first, 1:MSB first
+			
+// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... to start.  Initialise to make simulation easier
+	end
+		
+	always @ (posedge sysclk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+// ---- end internal clock generator ----------
+
+// ---- Detect start is asserted with a small state machine
+	// .... FF set on positive edge of start
+	// .... reset when adc_cs goes high again
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			adc_start;
+	
+	initial begin
+		sr_state = IDLE;
+		adc_start = 1'b0;	// set while sending data to ADC
+		end
+	
+	always @ (posedge sysclk)
+		case (sr_state)
+			IDLE:	if (start==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						adc_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (adc_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (adc_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						adc_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+//------- End circuit to detect start and end of conversion	
+
+	
+// spi controller designed as a state machine
+// .... with 16 states (idle, and S1-S15 indicated by state value
+
+	reg [4:0] 	state;
+	reg  	adc_done, adc_din, shift_ena;
+	
+	initial	begin	
+		state = 5'b0; adc_cs = 1'b1; adc_done = 1'b0; 
+		adc_din = 1'b0; shift_ena <= 1'b0;
+		end
+		
+	always @(posedge clk_1MHz)  begin
+	
+	// default outputs and state transition
+		adc_cs <= 1'b0;  adc_done <= 1'b0;  adc_din <= 1'b0; shift_ena <= 1'b0;
+		state <= state + 1'b1;
+		case (state)
+			5'd0:	begin
+						if (adc_start==1'b0) begin
+							state <= 5'd0;			// still idle
+							adc_cs <= 1'b1;		// chip select not active
+							end
+						else begin
+							state <= 5'd1;			// start converting
+							adc_din <= 1'b1;		// start bit is 1
+							end
+					end
+			5'd1:	adc_din <= SGL;				// SGL bit
+			5'd2:	adc_din <= channel;			// CH bit
+			5'd3:	adc_din <= MSBF;				// MSB first bit
+			5'd4: shift_ena <= 1'b1;  			// start shifting data from adc
+			5'd15: begin
+						shift_ena <= 1'b0;
+						adc_done <= 1'b1;
+					 end
+			5'd16: begin  
+						adc_cs <= 1'b1;		// last state - disable chip select
+						state <= 5'd0;  		// go back to idle state
+					 end
+			default: 				
+						shift_ena <= 1'b1;	// unspecified states are covered by default above
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [9:0] shift_reg;
+	initial	begin
+			shift_reg = 10'b0;
+			data_from_adc = 10'b0;
+			end
+	
+	always @(negedge clk_1MHz)
+		if((adc_cs==1'b0)&&(shift_ena==1'b1))		// start shifting data_in
+				shift_reg <= {shift_reg[8:0],sdata_from_adc};
+	
+	// Latch converted output data
+	always @(posedge clk_1MHz)
+		if(adc_done) 					
+				data_from_adc = shift_reg;
+
+	// Assign outputs to drive SPI interface to DAC
+		assign adc_sck = !clk_1MHz & !adc_cs;
+		assign sdata_to_adc = adc_din;
+		assign data_valid = adc_cs;
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/spi2dac.v b/part_4/ex19/verilog_files/spi2dac.v
new file mode 100755
index 0000000..ccfb4e8
--- /dev/null
+++ b/part_4/ex19/verilog_files/spi2dac.v
@@ -0,0 +1,128 @@
+//------------------------------
+// Module name: spi2dac
+// Function: SPI interface for MPC4911 DAC
+// Creator:  Peter Cheung
+// Version:  1.3
+// Date:     8 Nov 2016
+//------------------------------
+
+module spi2dac (clk, data_in, load, dac_sdi, dac_cs, dac_sck, dac_ld);
+
+	input	clk;				// 50MHz system clock of DE0
+	input	[9:0]	data_in;	// input data to DAC
+	input	load;				// Pulse to load data to dac
+	output dac_sdi;		// SPI serial data out
+	output dac_cs;			// chip select - low when sending data to dac
+	output dac_sck;		// SPI clock, 16 cycles at half clk freq
+	output dac_ld;
+
+//-------------Input Ports-----------------------------
+// All the input ports should be wires
+	wire			clk, load;
+	wire [9:0]	data_in;
+	
+//-------------Output Ports-----------------------------
+// Output port can be a storage element (reg) or a wire
+	reg			dac_cs, dac_ld;
+	wire			dac_sck, dac_sdi;
+	
+	parameter	BUF=1'b1;		// 0:no buffer, 1:Vref buffered
+	parameter	GA_N=1'b1;		// 0:gain = 2x, 1:gain = 1x
+	parameter	SHDN_N=1'b1;	// 0:power down, 1:dac active
+	
+	wire [3:0] cmd = {1'b0,BUF,GA_N,SHDN_N};  // wire to VDD or GND
+	
+	// --- Submodule: Generate internal clock at 1 MHz -----
+	reg			clk_1MHz;	// 1Mhz clock derived from 50MHz
+	reg [4:0]	ctr;			// internal counter
+	parameter	TIME_CONSTANT = 5'd24;  // change this for diff clk freq
+	initial begin
+		clk_1MHz = 0;			// don't need to reset - don't care if it is 1 or 0 to start
+		ctr = 5'b0;				//  ... Initialise when FPGA is configured
+	end
+		
+	always @ (posedge clk)   // 
+	  if (ctr==0) begin
+		  ctr <= TIME_CONSTANT;
+		  clk_1MHz <= ~clk_1MHz; // toggle the output clock for squarewave
+		end
+	  else
+		  ctr <= ctr - 1'b1;
+	// ---- end internal clock generator ----------
+
+	// ---- Detect posedge of load with a small state machine
+	// .... FF set on posedge of load
+	// .... reset when dac_cs goes high at the end of DAC output cycle
+	reg [1:0] 	sr_state;
+	parameter	IDLE  = 2'b00,WAIT_CSB_FALL = 2'b01, WAIT_CSB_HIGH = 2'b10;
+	reg			dac_start;		 // set if a DAC write is detected
+	
+	initial begin
+		sr_state = IDLE;
+		dac_start = 1'b0;	// set while sending data to DAC
+		end
+	
+	always @ (posedge clk)
+		case (sr_state)
+			IDLE:	if (load==1'b0) sr_state <= IDLE;
+					else	begin
+						sr_state <= WAIT_CSB_FALL;
+						dac_start <= 1'b1;
+						end  				
+			WAIT_CSB_FALL: if (dac_cs==1'b1) sr_state <= WAIT_CSB_FALL;
+					else sr_state <= WAIT_CSB_HIGH;
+					
+			WAIT_CSB_HIGH: if (dac_cs==1'b0) sr_state <= WAIT_CSB_HIGH;
+					else begin
+						sr_state <= IDLE;
+						dac_start <= 1'b0;
+						end	
+			default: sr_state <= IDLE;
+		endcase
+	//------- End circuit to detect start and end of conversion	
+
+	//------- spi controller designed as a state machine
+	// .... with 17 states (idle, and S1-S16 
+	// .... for the 16 cycles each sending 1-bit to dac)
+	reg [4:0] 	state;
+	
+	initial	begin	
+		state = 5'b0; dac_ld = 1'b0; dac_cs = 1'b1; 
+		end
+		
+	always @(posedge clk_1MHz)  begin
+		// default outputs and state transition
+		dac_cs <= 1'b0; dac_ld <= 1'b1; 
+		state <= state + 1'b1;	// move to next state by default
+		case (state)
+			5'd0:	if (dac_start == 1'b0)  begin  
+						state <= 5'd0; 				// still waiting
+						dac_cs <= 1'b1; 
+						end
+			5'd16: begin  
+						dac_cs <= 1'b1; dac_ld <= 1'b0; 
+						state <= 5'd0;  // go back to idle state
+					end
+			default:   begin					// all other states
+					dac_cs <= 1'b0; dac_ld <= 1'b1; 
+					state <= state + 1'b1;	// default state transition
+					end
+			endcase
+		end	// ... always
+	
+	// shift register for output data
+	reg [15:0] shift_reg;
+	initial	begin	
+		shift_reg = 16'b0; 
+		end
+
+	always @(posedge clk_1MHz)
+		if((dac_start==1'b1)&&(dac_cs==1'b1))		// parallel load data to shift reg
+			shift_reg <= {cmd,data_in,2'b00};
+		else 													// .. else start shifting
+			shift_reg <= {shift_reg[14:0],1'b0};
+	
+	// Assign outputs to drive SPI interface to DAC
+			assign dac_sck = !clk_1MHz&!dac_cs;
+			assign dac_sdi = shift_reg[15];
+endmodule
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/variable_echo.v b/part_4/ex19/verilog_files/variable_echo.v
new file mode 100755
index 0000000..ed22919
--- /dev/null
+++ b/part_4/ex19/verilog_files/variable_echo.v
@@ -0,0 +1,51 @@
+module processor (sysclk, tick, SW, data_in, data_out, data_valid, hex0, hex1, hex2, hex3, hex4);
+
+	input				sysclk, tick, data_valid;		// system clock
+	input [9:0]		data_in;
+	output [9:0] 	data_out;	// 10-bit output data
+
+	output [6:0]  	hex0, hex1, hex2, hex3, hex4;
+	
+	input [9:0]		SW;
+	
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+	wire [9:0]		tmp_data, echoed_data;
+	
+	wire [12:0]		raw_address;
+	
+	wire [19:0]		delay;
+	
+	wire [3:0]		bcd0, bcd1, bcd2, bcd3, bcd4;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in - ADC_OFFSET;		// x is input in 2's complement
+	
+	ctr_13_bit ctr(~data_valid, raw_address);
+	
+	delay_block del(sysclk, data_in, raw_address, tick, raw_address + {SW[8:0], 4'b0}, tick, tmp_data);
+	
+	div_by_2({tmp_data[8],tmp_data}, echoed_data);
+		
+	mult_by_h666 mul_by_h666(SW, delay);
+		
+	bin2bcd_16 bcd(delay[19:10], bcd0, bcd1, bcd2, bcd3, bcd4);
+		
+	hex_to_7seg h0(hex0, bcd0);
+	hex_to_7seg h1(hex1, bcd1);
+	hex_to_7seg h2(hex2, bcd2);
+	hex_to_7seg h3(hex3, bcd3);
+	hex_to_7seg h4(hex4, bcd4);
+		
+	assign y = x + echoed_data;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
diff --git a/part_4/ex19/verilog_files/variable_echo.v.bak b/part_4/ex19/verilog_files/variable_echo.v.bak
new file mode 100755
index 0000000..6589fd8
--- /dev/null
+++ b/part_4/ex19/verilog_files/variable_echo.v.bak
@@ -0,0 +1,34 @@
+module processor (sysclk, tick, data_in, data_out);
+
+	input				sysclk, tick;		// system clock
+	input [9:0]		data_in;		// 10-bit input data
+	output [9:0] 	data_out;	// 10-bit output data
+
+	wire				sysclk;
+	wire [9:0]		data_in;
+	reg [9:0] 		data_out;
+	wire [9:0]		x,y;
+	wire [9:0]		tmp_data, echoed_data;
+	wire is_full, and_if, from_dff;
+
+	parameter 		ADC_OFFSET = 10'h181;
+	parameter 		DAC_OFFSET = 10'h200;
+
+	assign x = data_in[9:0] - ADC_OFFSET;		// x is input in 2's complement
+	
+	FIFO fifo(sysclk, y, and_if, tick, is_full, tmp_data);
+	
+	d_ff d(tick, is_full, from_dff);
+	
+	assign and_if = tick & from_dff;
+	
+	div_by_2(tmp_data, echoed_data);
+		
+	assign y = x - echoed_data;
+	
+	//  Now clock y output with system clock
+	always @(posedge sysclk)
+		data_out <=  y + DAC_OFFSET;
+		
+endmodule
+	
+\ No newline at end of file
author	zedarider <ymherklotz@gmail.com>	2016-12-12 13:19:22 +0000
committer	zedarider <ymherklotz@gmail.com>	2016-12-12 13:19:22 +0000
commit	aee06a47eca6d7f5532a10e59e394fd33904670a (patch)
tree	9abf1adeec021a72863f1bfc8e1270513b26f1cb
parent	c2618f0b8ff2ed70d1e830b612b9ecfe722ece5f (diff)
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